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pipeline_stages_base.py
|
# --------------------------------------------------------------------------
# Copyright (c) Microsoft Corporation. All rights reserved.
# Licensed under the MIT License. See License.txt in the project root for
# license information.
# --------------------------------------------------------------------------
import logging
import abc
import time
import traceback
import uuid
import weakref
import threading
import queue
from . import pipeline_events_base
from . import pipeline_ops_base, pipeline_ops_mqtt
from . import pipeline_thread
from . import pipeline_exceptions
from .pipeline_nucleus import ConnectionState
from azure.iot.device.common import transport_exceptions, alarm
from azure.iot.device.common.auth import sastoken as st
logger = logging.getLogger(__name__)
class PipelineStage(abc.ABC):
"""
Base class representing a stage in the processing pipeline. Each stage is responsible for receiving
PipelineOperation objects from the top, possibly processing them, and possibly passing them down. It
is also responsible for receiving PipelineEvent objects from the bottom, possibly processing them, and
possibly passing them up.
Each PipelineStage in the pipeline, is expected to act on some well-defined set of PipelineOperation
types and/or some set of PipelineEvent types. If any stage does not act on an operation or event, it
should pass it to the next stage (for operations) or the previous stage (for events). In this way, the
pipeline implements the "chain of responsibility" design pattern (Gamma, et.al. "Design Patterns".
Addison Wesley. 1995), with each stage being responsible for implementing some "rule" or "policy" of the
pipeline, and each stage being ignorant of the stages that are before or after it in the pipeline.
Each stage in the pipeline should act on the smallest set of rules possible, thus making stages small
and easily testable. Complex logic should be the exception and not the rule, and complex stages should
operate on the most generic type of operation possible, thus allowing us to re-use complex logic for
multiple cases. The best way to do this is with "converter" stages that convert a specific operation to
a more general one and with other converter stages that convert general operations to more specific ones.
An example of a specific-to-generic stage is UseSkAuthProviderStage which takes a specific operation
(use an auth provider) and converts it into something more generic (here is your device_id, etc, and use
this SAS token when connecting).
An example of a generic-to-specific stage is IoTHubMQTTTranslationStage which converts IoTHub operations
(such as SendD2CMessageOperation) to MQTT operations (such as Publish).
Each stage should also work in the broadest domain possible. For example a generic stage (say
"AutoConnectStage") that initiates a connection if any arbitrary operation needs a connection is more useful
than having some MQTT-specific code that re-connects to the MQTT broker if the user calls Publish and
there's no connection.
One way to think about stages is to look at every "block of functionality" in your code and ask yourself
"is this the one and only time I will need this code"? If the answer is no, it might be worthwhile to
implement that code in it's own stage in a very generic way.
:ivar name: The name of the stage. This is used primarily for logging
:type name: str
:ivar next: The next stage in the pipeline. Set to None if this is the last stage in the pipeline.
:type next: PipelineStage
:ivar previous: The previous stage in the pipeline. Set to None if this is the first stage in the pipeline.
:type previous: PipelineStage
:ivar nucleus: The pipeline's "nucleus" which contains global pipeline information, accessible
from all stages
:type nucleus: PipelineNucleus
"""
def __init__(self):
"""
Initializer for PipelineStage objects.
"""
self.name = self.__class__.__name__
self.next = None
self.previous = None
self.nucleus = None
@pipeline_thread.runs_on_pipeline_thread
def run_op(self, op):
"""
Run the given operation. This is the public function that outside callers would call to run an
operation. Derived classes should override the private _run_op function to implement
stage-specific behavior. When run_op returns, that doesn't mean that the operation has executed
to completion. Rather, it means that the pipeline has done something that will cause the
operation to eventually execute to completion. That might mean that something was sent over
the network and some stage is waiting for a reply, or it might mean that the operation is sitting
in a queue until something happens, or it could mean something entirely different. The only
thing you can assume is that the operation will _eventually_ complete successfully or fail, and the
operation's callback will be called when that happens.
:param PipelineOperation op: The operation to run.
"""
try:
self._run_op(op)
except Exception as e:
# This path is ONLY for unexpected errors. Expected errors should cause a fail completion
# within ._run_op().
#
# We tag errors from here as logger.warning because, while we return them to the
# caller and rely on the caller to handle them, they're somewhat unexpected and might be
# worthy of investigation.
# Do not use exc_info parameter on logger.* calls. This causes pytest to save the
# traceback which saves stack frames which shows up as a leak
logger.warning(msg="Unexpected error in {}._run_op() call".format(self))
logger.warning(traceback.format_exc())
# Only complete the operation if it is not already completed.
# Attempting to complete a completed operation would raise an exception.
if not op.completed:
op.complete(error=e)
else:
# Note that this would be very unlikely to occur. It could only happen if a stage
# was doing something after completing an operation, and an exception was raised,
# which is unlikely because stages usually don't do anything after completing an
# operation.
raise e
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
"""
Implementation of the stage-specific function of .run_op(). Override this method instead of
.run_op() in child classes in order to change how a stage behaves when running an operation.
See the description of the .run_op() method for more discussion on what it means to "run"
an operation.
:param PipelineOperation op: The operation to run.
"""
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def handle_pipeline_event(self, event):
"""
Handle a pipeline event that arrives from the stage below this stage. Derived
classes should not override this function. Any stage-specific handling of
PipelineEvent objects should be implemented by overriding the private
_handle_pipeline_event function in the derived stage.
:param PipelineEvent event: The event that is being passed back up the pipeline
"""
try:
self._handle_pipeline_event(event)
except Exception as e:
# Do not use exc_info parameter on logger.* calls. This causes pytest to save the
# traceback which saves stack frames which shows up as a leak
logger.warning(
msg="{}: Unexpected error in ._handle_pipeline_event() call: {}".format(self, e)
)
if self.previous:
logger.warning("{}: Raising background exception")
self.report_background_exception(e)
else:
# Nothing else we can do but log this. There exists no stage we can send the
# exception to, and raising would send the error back down the pipeline.
logger.warning(
"{}: Cannot report a background exception because there is no previous stage!"
)
@pipeline_thread.runs_on_pipeline_thread
def _handle_pipeline_event(self, event):
"""
Handle a pipeline event that arrives from the stage below this stage. This
is a function that is intended to be overridden in any stages that want to implement
stage-specific handling of any events
:param PipelineEvent event: The event that is being passed back up the pipeline
"""
self.send_event_up(event)
@pipeline_thread.runs_on_pipeline_thread
def send_op_down(self, op):
"""
Helper function to continue a given operation by passing it to the next stage
in the pipeline. If there is no next stage in the pipeline, this function
will fail the operation and call complete_op to return the failure back up the
pipeline.
:param PipelineOperation op: Operation which is being passed on
"""
if self.next:
self.next.run_op(op)
else:
# This shouldn't happen if the pipeline was created correctly
logger.warning(
"{}({}): no next stage.cannot send op down. completing with error".format(
self.name, op.name
)
)
raise pipeline_exceptions.PipelineRuntimeError(
"{} not handled after {} stage with no next stage".format(op.name, self.name)
)
@pipeline_thread.runs_on_pipeline_thread
def send_event_up(self, event):
"""
Helper function to pass an event to the previous stage of the pipeline. This is the default
behavior of events while traveling through the pipeline. They start somewhere (maybe the
bottom) and move up the pipeline until they're handled or until they error out.
"""
if self.previous:
self.previous.handle_pipeline_event(event)
else:
# This shouldn't happen if the pipeline was created correctly
logger.critical(
"{}({}): no previous stage. cannot send event up".format(event.name, self.name)
)
# NOTE: We can't report a background exception here because that involves
# sending an event up, which is what got us into this problem in the first place.
# Instead, raise, and let the method invoking this method handle it
raise pipeline_exceptions.PipelineRuntimeError(
"{} not handled after {} stage with no previous stage".format(event.name, self.name)
)
@pipeline_thread.runs_on_pipeline_thread
def report_background_exception(self, e):
"""
Send an exception up the pipeline that occurred in the background.
These would typically be in response to unsolicited actions, such as receiving data or
timer-based operations, which cannot be raised to the user because they occurred on a
non-application thread.
Note that this function leverages pipeline event flow, which means that any background
exceptions in the core event flow itself become problematic (it's a good thing it's well
tested then!)
:param Exception e: The exception that occurred in the background
"""
event = pipeline_events_base.BackgroundExceptionEvent(e)
self.send_event_up(event)
class PipelineRootStage(PipelineStage):
"""
Object representing the root of a pipeline. This is where the functions to build
the pipeline exist. This is also where clients can add event handlers to receive
events from the pipeline.
:ivar on_pipeline_event_handler: Handler which can be set by users of the pipeline to
receive PipelineEvent objects. This is how users receive any "unsolicited"
events from the pipeline (such as C2D messages). This function is called with
a PipelineEvent object every time any such event occurs.
:type on_pipeline_event_handler: Function
:ivar on_connected_handler: Handler which can be set by users of the pipeline to
receive events every time the underlying transport connects
:type on_connected_handler: Function
:ivar on_disconnected_handler: Handler which can be set by users of the pipeline to
receive events every time the underlying transport disconnects
:type on_disconnected_handler: Function
"""
def __init__(self, nucleus):
super().__init__()
self.on_pipeline_event_handler = None
self.on_connected_handler = None
self.on_disconnected_handler = None
self.on_new_sastoken_required_handler = None
self.on_background_exception_handler = None
self.nucleus = nucleus
def run_op(self, op):
# CT-TODO: make this more elegant
op.callback_stack[0] = pipeline_thread.invoke_on_callback_thread_nowait(
op.callback_stack[0]
)
pipeline_thread.invoke_on_pipeline_thread(super().run_op)(op)
def append_stage(self, new_stage):
"""
Add the next stage to the end of the pipeline. This is the function that callers
use to build the pipeline by appending stages. This function returns the root of
the pipeline so that calls to this function can be chained together.
:param PipelineStage new_stage: Stage to add to the end of the pipeline
:returns: The root of the pipeline.
"""
old_tail = self
while old_tail.next:
old_tail = old_tail.next
old_tail.next = new_stage
new_stage.previous = old_tail
new_stage.nucleus = self.nucleus
return self
@pipeline_thread.runs_on_pipeline_thread
def _handle_pipeline_event(self, event):
"""
Override of the PipelineEvent handler. Because this is the root of the pipeline,
this function calls the on_pipeline_event_handler to pass the event to the
caller.
:param PipelineEvent event: Event to be handled, i.e. returned to the caller
through the handle_pipeline_event (if provided).
"""
# Base events that are common to all pipelines are handled here
if isinstance(event, pipeline_events_base.ConnectedEvent):
logger.debug(
"{}: ConnectedEvent received. Calling on_connected_handler".format(self.name)
)
if self.on_connected_handler:
pipeline_thread.invoke_on_callback_thread_nowait(self.on_connected_handler)()
elif isinstance(event, pipeline_events_base.DisconnectedEvent):
logger.debug(
"{}: DisconnectedEvent received. Calling on_disconnected_handler".format(self.name)
)
if self.on_disconnected_handler:
pipeline_thread.invoke_on_callback_thread_nowait(self.on_disconnected_handler)()
elif isinstance(event, pipeline_events_base.NewSasTokenRequiredEvent):
logger.debug(
"{}: NewSasTokenRequiredEvent received. Calling on_new_sastoken_required_handler".format(
self.name
)
)
if self.on_new_sastoken_required_handler:
pipeline_thread.invoke_on_callback_thread_nowait(
self.on_new_sastoken_required_handler
)()
elif isinstance(event, pipeline_events_base.BackgroundExceptionEvent):
logger.debug(
"{}: BackgroundExceptionEvent received. Calling on_background_exception_handler".format(
self.name
)
)
if self.on_background_exception_handler:
pipeline_thread.invoke_on_callback_thread_nowait(
self.on_background_exception_handler
)(event.e)
# Events that are domain-specific and unique to each pipeline are handled by the provided
# domain-specific .on_pipeline_event_handler
else:
if self.on_pipeline_event_handler:
pipeline_thread.invoke_on_callback_thread_nowait(self.on_pipeline_event_handler)(
event
)
else:
# unexpected condition: we should be handling all pipeline events
logger.debug("incoming {} event with no handler. dropping.".format(event.name))
# NOTE: This stage could be a candidate for being refactored into some kind of other
# pipeline-related structure. What's odd about it as a stage is that it doesn't really respond
# to operations or events so much as it spawns them on a timer.
# Perhaps some kind of... Pipeline Daemon?
class SasTokenStage(PipelineStage):
# Amount of time, in seconds, prior to token expiration to trigger alarm
DEFAULT_TOKEN_UPDATE_MARGIN = 120
def __init__(self):
super().__init__()
# Indicates when token needs to be updated
self._token_update_alarm = None
# Indicates when to retry a failed reauthorization attempt
# (only used with renewable SAS auth)
self._reauth_retry_timer = None
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
if (
isinstance(op, pipeline_ops_base.InitializePipelineOperation)
and self.nucleus.pipeline_configuration.sastoken is not None
):
# Start an alarm (renewal or replacement depending on token type)
self._start_token_update_alarm()
self.send_op_down(op)
elif (
isinstance(op, pipeline_ops_base.ReauthorizeConnectionOperation)
and self.nucleus.pipeline_configuration.sastoken is not None
):
# NOTE 1: This case (currently) implies that we are using Non-Renewable SAS,
# although it's not enforced here (it's a product of how the pipeline and client are
# configured overall)
# NOTE 2: There's a theoretically possible case where the new token has the same expiry
# time as the old token, and thus a new update alarm wouldn't really be required, but
# I don't want to include the complexity of checking. Just start a new alarm anyway.
# NOTE 3: Yeah, this is the same logic as the above case for the InitializePipeline op,
# but if it weren't separate, how would you get all these nice informative comments?
# (Also, it leaves room for the logic to change in the future)
self._start_token_update_alarm()
self.send_op_down(op)
elif isinstance(op, pipeline_ops_base.ShutdownPipelineOperation):
self._cancel_token_update_alarm()
self._cancel_reauth_retry_timer()
self.send_op_down(op)
else:
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _cancel_token_update_alarm(self):
"""Cancel and delete any pending update alarm"""
old_alarm = self._token_update_alarm
self._token_update_alarm = None
if old_alarm:
logger.debug("Cancelling SAS Token update alarm")
old_alarm.cancel()
old_alarm = None
@pipeline_thread.runs_on_pipeline_thread
def _cancel_reauth_retry_timer(self):
"""Cancel and delete any pending reauth retry timer"""
old_reauth_retry_timer = self._reauth_retry_timer
self._reauth_retry_timer = None
if old_reauth_retry_timer:
logger.debug("Cancelling reauthorization retry timer")
old_reauth_retry_timer.cancel()
old_reauth_retry_timer = None
@pipeline_thread.runs_on_pipeline_thread
def _start_token_update_alarm(self):
"""Begin an update alarm.
If using a RenewableSasToken, when the alarm expires the token will be automatically
renewed, and a new alarm will be set.
If using a NonRenewableSasToken, when the alarm expires, it will trigger a
NewSasTokenRequiredEvent to signal that a new SasToken must be manually provided.
"""
self._cancel_token_update_alarm()
update_time = (
self.nucleus.pipeline_configuration.sastoken.expiry_time
- self.DEFAULT_TOKEN_UPDATE_MARGIN
)
# On Windows platforms, the threading event TIMEOUT_MAX (approximately 49.7 days) could
# conceivably be less than the SAS lifespan, which means we may need to update the token
# before the lifespan ends.
# If we really wanted to adjust this in the future to use the entire SAS lifespan, we could
# implement Alarms that trigger other Alarms, but for now, just forcing a token update
# is good enough.
# Note that this doesn't apply to (most) Unix platforms, where TIMEOUT_MAX is 292.5 years.
if (update_time - time.time()) > threading.TIMEOUT_MAX:
update_time = time.time() + threading.TIMEOUT_MAX
logger.warning(
"SAS Token expiration ({expiry} seconds) exceeds max scheduled renewal time ({max} seconds). Will be renewing after {max} seconds instead".format(
expiry=self.nucleus.pipeline_configuration.sastoken.expiry_time,
max=threading.TIMEOUT_MAX,
)
)
self_weakref = weakref.ref(self)
# For renewable SasTokens, create an alarm that will automatically renew the token,
# and then start another alarm.
if isinstance(self.nucleus.pipeline_configuration.sastoken, st.RenewableSasToken):
logger.debug(
"{}: Scheduling automatic SAS Token renewal at epoch time: {}".format(
self.name, update_time
)
)
@pipeline_thread.invoke_on_pipeline_thread_nowait
def renew_token():
this = self_weakref()
# Cancel any token reauth retry timer in progress (from a previous renewal)
this._cancel_reauth_retry_timer()
logger.info("{}: Renewing SAS Token...".format(self.name))
# Renew the token
sastoken = this.nucleus.pipeline_configuration.sastoken
try:
sastoken.refresh()
except st.SasTokenError as e:
logger.error("{}: SAS Token renewal failed".format(self.name))
this.report_background_exception(e)
# TODO: then what? How do we respond to this? Retry?
# What if it never works and the token expires?
else:
# If the pipeline is already connected, send order to reauthorize the connection
# now that token has been renewed. If the pipeline is not currently connected,
# there is no need to do this, as the next connection will be using the new
# credentials.
if this.nucleus.connected:
this._reauthorize()
# Once again, start a renewal alarm
this._start_token_update_alarm()
self._token_update_alarm = alarm.Alarm(update_time, renew_token)
# For nonrenewable SasTokens, create an alarm that will issue a NewSasTokenRequiredEvent
else:
logger.debug(
"Scheduling manual SAS Token renewal at epoch time: {}".format(update_time)
)
@pipeline_thread.invoke_on_pipeline_thread_nowait
def request_new_token():
this = self_weakref()
logger.info("Requesting new SAS Token....")
# Send request
this.send_event_up(pipeline_events_base.NewSasTokenRequiredEvent())
self._token_update_alarm = alarm.Alarm(update_time, request_new_token)
self._token_update_alarm.daemon = True
self._token_update_alarm.start()
@pipeline_thread.runs_on_pipeline_thread
def _reauthorize(self):
self_weakref = weakref.ref(self)
@pipeline_thread.runs_on_pipeline_thread
def on_reauthorize_complete(op, error):
this = self_weakref()
if error:
logger.info(
"{}: Connection reauthorization failed. Error={}".format(this.name, error)
)
self.report_background_exception(error)
# If connection has not been somehow re-established, we need to keep trying
# because for the reauthorization to originally have been issued, we were in
# a connected state.
# NOTE: we only do this if connection retry is enabled on the pipeline. If it is,
# we have a contract to maintain a connection. If it has been disabled, we have
# a contract to not do so.
# NOTE: We can't rely on the ConnectionStateStage to do this because 1) the pipeline
# stages should stand on their own, and 2) if the reauth failed, the ConnectionStateStage
# wouldn't know to reconnect, because the expected state of a failed reauth is
# to be disconnected.
if (
not this.nucleus.connected
and this.nucleus.pipeline_configuration.connection_retry
):
logger.info("{}: Retrying connection reauthorization".format(this.name))
# No need to cancel the timer, because if this is running, it has already ended
@pipeline_thread.invoke_on_pipeline_thread_nowait
def retry_reauthorize():
# We need to check this when the timer expires as well as before creating
# the timer in case connection has been re-established while timer was
# running
if not this.nucleus.connected:
this._reauthorize()
this._reauth_retry_timer = threading.Timer(
this.nucleus.pipeline_configuration.connection_retry_interval,
retry_reauthorize,
)
this._reauth_retry_timer.daemon = True
this._reauth_retry_timer.start()
else:
logger.info("{}: Connection reauthorization successful".format(this.name))
logger.info("{}: Starting reauthorization process for new SAS token".format(self.name))
self.send_op_down(
pipeline_ops_base.ReauthorizeConnectionOperation(callback=on_reauthorize_complete)
)
class AutoConnectStage(PipelineStage):
"""
This stage is responsible for ensuring that the protocol is connected when
it needs to be connected.
"""
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
# Any operation that requires a connection can trigger a connection if
# we're not connected and the auto-connect feature is enabled.
if (
op.needs_connection
and not self.nucleus.connected
and self.nucleus.pipeline_configuration.auto_connect
):
logger.debug(
"{}({}): Op needs connection. Queueing this op and starting a ConnectionOperation".format(
self.name, op.name
)
)
self._do_connect(op)
else:
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _do_connect(self, op):
"""
Start connecting the transport in response to some operation
"""
# Alias to avoid overload within the callback below
# CT-TODO: remove the need for this with better callback semantics
op_needs_connect = op
# function that gets called after we're connected.
@pipeline_thread.runs_on_pipeline_thread
def on_connect_op_complete(op, error):
if error:
logger.debug(
"{}({}): Connection failed. Completing with failure because of connection failure: {}".format(
self.name, op_needs_connect.name, error
)
)
op_needs_connect.complete(error=error)
else:
logger.debug(
"{}({}): connection is complete. Running op that triggered connection.".format(
self.name, op_needs_connect.name
)
)
self.run_op(op_needs_connect)
# call down to the next stage to connect.
logger.debug("{}({}): calling down with Connect operation".format(self.name, op.name))
self.send_op_down(pipeline_ops_base.ConnectOperation(callback=on_connect_op_complete))
class CoordinateRequestAndResponseStage(PipelineStage):
"""
Pipeline stage which is responsible for coordinating RequestAndResponseOperation operations. For each
RequestAndResponseOperation operation, this stage passes down a RequestOperation operation and waits for
an ResponseEvent event. All other events are passed down unmodified.
"""
def __init__(self):
super().__init__()
self.pending_responses = {}
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
if isinstance(op, pipeline_ops_base.RequestAndResponseOperation):
# Convert RequestAndResponseOperation operation into a RequestOperation operation
# and send it down. A lower level will convert the RequestOperation into an
# actual protocol client operation. The RequestAndResponseOperation operation will be
# completed when the corresponding IotResponse event is received in this stage.
request_id = str(uuid.uuid4())
logger.debug(
"{}({}): adding request {} to pending list".format(self.name, op.name, request_id)
)
self.pending_responses[request_id] = op
self._send_request_down(request_id, op)
else:
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _send_request_down(self, request_id, op):
# Alias to avoid overload within the callback below
# CT-TODO: remove the need for this with better callback semantics
op_waiting_for_response = op
@pipeline_thread.runs_on_pipeline_thread
def on_send_request_done(op, error):
logger.debug(
"{}({}): Finished sending {} request to {} resource {}".format(
self.name,
op_waiting_for_response.name,
op_waiting_for_response.request_type,
op_waiting_for_response.method,
op_waiting_for_response.resource_location,
)
)
if error:
logger.debug(
"{}({}): removing request {} from pending list".format(
self.name, op_waiting_for_response.name, request_id
)
)
# if there's no pending response for the given request_id, there's nothing to delete
if request_id in self.pending_responses:
del self.pending_responses[request_id]
op_waiting_for_response.complete(error=error)
else:
# NOTE: This shouldn't ever happen under normal conditions, but the following logic
# ensures that, if it does, it's handled safely.
logger.debug(
"{}({}): request_id {} not found in pending list. Unexpected behavior. Dropping".format(
self.name, op_waiting_for_response.name, request_id
)
)
pass
else:
# request sent. Nothing to do except wait for the response
pass
logger.debug(
"{}({}): Sending {} request to {} resource {}".format(
self.name, op.name, op.request_type, op.method, op.resource_location
)
)
new_op = pipeline_ops_base.RequestOperation(
method=op.method,
resource_location=op.resource_location,
request_body=op.request_body,
request_id=request_id,
request_type=op.request_type,
callback=on_send_request_done,
query_params=op.query_params,
)
self.send_op_down(new_op)
@pipeline_thread.runs_on_pipeline_thread
def _handle_pipeline_event(self, event):
if isinstance(event, pipeline_events_base.ResponseEvent):
# match ResponseEvent events to the saved dictionary of RequestAndResponseOperation
# operations which have not received responses yet. If the operation is found,
# complete it.
logger.debug(
"{}({}): Handling event with request_id {}".format(
self.name, event.name, event.request_id
)
)
if event.request_id in self.pending_responses:
op = self.pending_responses[event.request_id]
del self.pending_responses[event.request_id]
op.status_code = event.status_code
op.response_body = event.response_body
op.retry_after = event.retry_after
logger.debug(
"{}({}): Completing {} request to {} resource {} with status {}".format(
self.name,
op.name,
op.request_type,
op.method,
op.resource_location,
op.status_code,
)
)
op.complete()
else:
logger.info(
"{}({}): request_id {} not found in pending list. Nothing to do. Dropping".format(
self.name, event.name, event.request_id
)
)
else:
self.send_event_up(event)
class OpTimeoutStage(PipelineStage):
"""
The purpose of the timeout stage is to add timeout errors to select operations
The timeout_intervals attribute contains a list of operations to track along with
their timeout values. Right now this list is hard-coded but the operations and
intervals will eventually become a parameter.
For each operation that needs a timeout check, this stage will add a timer to
the operation. If the timer elapses, this stage will fail the operation with
a OperationTimeout. The intention is that a higher stage will know what to
do with that error and act accordingly (either return the error to the user or
retry).
This stage currently assumes that all timed out operation are just "lost".
It does not attempt to cancel the operation, as Paho doesn't have a way to
cancel an operation, and with QOS=1, sending a pub or sub twice is not
catastrophic.
Also, as a long-term plan, the operations that need to be watched for timeout
will become an initialization parameter for this stage so that different
instances of this stage can watch for timeouts on different operations.
This will be done because we want a lower-level timeout stage which can watch
for timeouts at the MQTT level, and we want a higher-level timeout stage which
can watch for timeouts at the iothub level. In this way, an MQTT operation that
times out can be retried as an MQTT operation and a higher-level IoTHub operation
which times out can be retried as an IoTHub operation (which might necessitate
redoing multiple MQTT operations).
"""
def __init__(self):
super().__init__()
# use a fixed list and fixed intervals for now. Later, this info will come in
# as an init param or a retry policy
self.timeout_intervals = {
pipeline_ops_mqtt.MQTTSubscribeOperation: 10,
pipeline_ops_mqtt.MQTTUnsubscribeOperation: 10,
# Only Sub and Unsub are here because MQTT auto retries pub
}
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
if type(op) in self.timeout_intervals:
# Create a timer to watch for operation timeout on this op and attach it
# to the op.
self_weakref = weakref.ref(self)
@pipeline_thread.invoke_on_pipeline_thread_nowait
def on_timeout():
this = self_weakref()
logger.info("{}({}): returning timeout error".format(this.name, op.name))
op.complete(
error=pipeline_exceptions.OperationTimeout(
"operation timed out before protocol client could respond"
)
)
logger.debug("{}({}): Creating timer".format(self.name, op.name))
op.timeout_timer = threading.Timer(self.timeout_intervals[type(op)], on_timeout)
op.timeout_timer.start()
# Send the op down, but intercept the return of the op so we can
# remove the timer when the op is done
op.add_callback(self._clear_timer)
logger.debug("{}({}): Sending down".format(self.name, op.name))
self.send_op_down(op)
else:
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _clear_timer(self, op, error):
# When an op comes back, delete the timer and pass it right up.
if op.timeout_timer:
logger.debug("{}({}): Cancelling timer".format(self.name, op.name))
op.timeout_timer.cancel()
op.timeout_timer = None
class RetryStage(PipelineStage):
"""
The purpose of the retry stage is to watch specific operations for specific
errors and retry the operations as appropriate.
Unlike the OpTimeoutStage, this stage will never need to worry about cancelling
failed operations. When an operation is retried at this stage, it is already
considered "failed", so no cancellation needs to be done.
"""
def __init__(self):
super().__init__()
# Retry intervals are hardcoded for now. Later, they come in as an
# init param, probably via retry policy.
self.retry_intervals = {
pipeline_ops_mqtt.MQTTSubscribeOperation: 20,
pipeline_ops_mqtt.MQTTUnsubscribeOperation: 20,
# Only Sub and Unsub are here because MQTT auto retries pub
}
self.ops_waiting_to_retry = []
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
"""
Send all ops down and intercept their return to "watch for retry"
"""
if self._should_watch_for_retry(op):
op.add_callback(self._do_retry_if_necessary)
self.send_op_down(op)
else:
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _should_watch_for_retry(self, op):
"""
Return True if this op needs to be watched for retry. This can be
called before the op runs.
"""
return type(op) in self.retry_intervals
@pipeline_thread.runs_on_pipeline_thread
def _should_retry(self, op, error):
"""
Return True if this op needs to be retried. This must be called after
the op completes.
"""
if error:
if self._should_watch_for_retry(op):
if isinstance(error, pipeline_exceptions.OperationTimeout):
return True
return False
@pipeline_thread.runs_on_pipeline_thread
def _do_retry_if_necessary(self, op, error):
"""
Handler which gets called when operations are complete. This function
is where we check to see if a retry is necessary and set a "retry timer"
which can be used to send the op down again.
"""
if self._should_retry(op, error):
self_weakref = weakref.ref(self)
@pipeline_thread.invoke_on_pipeline_thread_nowait
def do_retry():
this = self_weakref()
logger.debug("{}({}): retrying".format(this.name, op.name))
op.retry_timer.cancel()
op.retry_timer = None
this.ops_waiting_to_retry.remove(op)
# Don't just send it down directly. Instead, go through run_op so we get
# retry functionality this time too
this.run_op(op)
interval = self.retry_intervals[type(op)]
logger.info(
"{}({}): Op needs retry with interval {} because of {}. Setting timer.".format(
self.name, op.name, interval, error
)
)
# if we don't keep track of this op, it might get collected.
op.halt_completion()
self.ops_waiting_to_retry.append(op)
op.retry_timer = threading.Timer(self.retry_intervals[type(op)], do_retry)
op.retry_timer.start()
else:
if op.retry_timer:
op.retry_timer.cancel()
op.retry_timer = None
class ConnectionStateStage(PipelineStage):
intermediate_states = [
ConnectionState.CONNECTING,
ConnectionState.DISCONNECTING,
ConnectionState.REAUTHORIZING,
]
transient_connect_errors = [
pipeline_exceptions.OperationCancelled,
pipeline_exceptions.OperationTimeout,
pipeline_exceptions.OperationError,
transport_exceptions.ConnectionFailedError,
transport_exceptions.ConnectionDroppedError,
transport_exceptions.TlsExchangeAuthError,
]
def __init__(self):
super().__init__()
self.reconnect_timer = None
self.waiting_ops = queue.Queue()
# NOTE: In this stage states are both checked, and changed, but there is no lock to protect
# this state value, or the logic that surrounds it from multithreading. This is because due
# to the threading model of the pipeline, there is a dedicated pipeline thread that handles
# everything that runs here, and it can only be doing one thing at a time. Thus we don't
# need to have a threading lock on our state, or be concerned with how atomic things are.
@pipeline_thread.runs_on_pipeline_thread
def _run_op(self, op):
# If receiving an operation while the connection state is changing, wait for the
# connection state to reach a stable state before continuing.
if self.nucleus.connection_state in self.intermediate_states:
logger.debug(
"{}({}): State is {} - waiting for in-progress operation to finish".format(
self.name, op.name, self.nucleus.connection_state
)
)
self.waiting_ops.put_nowait(op)
else:
if isinstance(op, pipeline_ops_base.ConnectOperation):
if self.nucleus.connection_state is ConnectionState.CONNECTED:
logger.debug(
"{}({}): State is already CONNECTED. Completing operation".format(
self.name, op.name
)
)
op.complete()
elif self.nucleus.connection_state is ConnectionState.DISCONNECTED:
logger.debug(
"{}({}): State changes DISCONNECTED -> CONNECTING. Sending op down".format(
self.name, op.name
)
)
self.nucleus.connection_state = ConnectionState.CONNECTING
self._add_connection_op_callback(op)
self.send_op_down(op)
else:
# This should be impossible to reach. If the state were intermediate, it
# would have been added to the waiting ops queue above.
logger.warning(
"{}({}): Invalid State - {}".format(
self.name, op.name, self.nucleus.connection_state
)
)
self.send_op_down(op)
elif isinstance(op, pipeline_ops_base.DisconnectOperation):
# First, always clear any reconnect timer. Because a manual disconnection is
# occurring, we won't want to be reconnecting any more.
self._clear_reconnect_timer()
if self.nucleus.connection_state is ConnectionState.CONNECTED:
logger.debug(
"{}({}): State changes CONNECTED -> DISCONNECTING. Sending op down.".format(
self.name, op.name
)
)
self.nucleus.connection_state = ConnectionState.DISCONNECTING
self._add_connection_op_callback(op)
self.send_op_down(op)
elif self.nucleus.connection_state is ConnectionState.DISCONNECTED:
logger.debug(
"{}({}): State is already DISCONNECTED. Completing operation".format(
self.name, op.name
)
)
op.complete()
else:
# This should be impossible to reach. If the state were intermediate, it
# would have been added to the waiting ops queue above.
logger.warning(
"{}({}): Invalid State - {}".format(
self.name, op.name, self.nucleus.connection_state
)
)
self.send_op_down(op)
elif isinstance(op, pipeline_ops_base.ReauthorizeConnectionOperation):
if self.nucleus.connection_state is ConnectionState.CONNECTED:
logger.debug(
"{}({}): State changes CONNECTED -> REAUTHORIZING. Sending op down.".format(
self.name, op.name
)
)
self.nucleus.connection_state = ConnectionState.REAUTHORIZING
self._add_connection_op_callback(op)
self.send_op_down(op)
elif self.nucleus.connection_state is ConnectionState.DISCONNECTED:
logger.debug(
"{}({}): State changes DISCONNECTED -> REAUTHORIZING. Sending op down".format(
self.name, op.name
)
)
self.nucleus.connection_state = ConnectionState.REAUTHORIZING
self._add_connection_op_callback(op)
self.send_op_down(op)
else:
# This should be impossible to reach. If the state were intermediate, it
# would have been added to the waiting ops queue above.
logger.warning(
"{}({}): Invalid State - {}".format(
self.name, op.name, self.nucleus.connection_state
)
)
self.send_op_down(op)
elif isinstance(op, pipeline_ops_base.ShutdownPipelineOperation):
self._clear_reconnect_timer()
# Cancel all pending ops so they don't hang
while not self.waiting_ops.empty():
waiting_op = self.waiting_ops.get_nowait()
cancel_error = pipeline_exceptions.OperationCancelled(
"Operation waiting in ConnectionStateStage cancelled by shutdown"
)
waiting_op.complete(error=cancel_error)
self.send_op_down(op)
else:
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _handle_pipeline_event(self, event):
if isinstance(event, pipeline_events_base.ConnectedEvent):
# First, clear the reconnect timer no matter what.
# We are now connected, so any ongoing reconnect is unnecessary
self._clear_reconnect_timer()
# EXPECTED CONNECTION (ConnectOperation was previously issued)
if self.nucleus.connection_state is ConnectionState.CONNECTING:
logger.debug(
"{}({}): State changes CONNECTING -> CONNECTED. Connection established".format(
self.name, event.name
)
)
self.nucleus.connection_state = ConnectionState.CONNECTED
# EXPECTED CONNECTION (ReauthorizeConnectionOperation was previously issued)
elif self.nucleus.connection_state is ConnectionState.REAUTHORIZING:
logger.debug(
"{}({}): State changes REAUTHORIZING -> CONNECTED. Connection re-established after re-authentication".format(
self.name, event.name
)
)
self.nucleus.connection_state = ConnectionState.CONNECTED
# BAD STATE (this block should not be reached)
else:
logger.warning(
"{}: ConnectedEvent received while in unexpected state - {}".format(
self.name, self.nucleus.connection_state
)
)
logger.debug(
"{}({}): State changes {} -> CONNECTED. Unexpected connection".format(
self.name, event.name, self.nucleus.connection_state
)
)
self.nucleus.connection_state = ConnectionState.CONNECTED
elif isinstance(event, pipeline_events_base.DisconnectedEvent):
# UNEXPECTED DISCONNECTION (i.e. Connection has been lost)
if self.nucleus.connection_state is ConnectionState.CONNECTED:
# Set the state change before starting the timer in order to make sure
# there's no issues when the timer expires. The pipeline threading model should
# already be preventing any weirdness with timing, but can't hurt to do this
# as well.
self.nucleus.connection_state = ConnectionState.DISCONNECTED
if self.nucleus.pipeline_configuration.connection_retry:
# When we get disconnected, we try to reconnect as soon as we can. We set a
# timer here that will start the process in another thread because we don't
# want to hold up the event flow
logger.debug(
"{}({}): State changes CONNECTED -> DISCONNECTED. Attempting to reconnect".format(
self.name, event.name
)
)
self._start_reconnect_timer(0.01)
else:
logger.debug(
"{}({}): State changes CONNECTED -> DISCONNECTED. Not attempting to reconnect (Connection retry disabled)".format(
self.name, event.name
)
)
# EXPECTED DISCONNECTION (DisconnectOperation was previously issued)
elif self.nucleus.connection_state is ConnectionState.DISCONNECTING:
# No reconnect timer will be created.
logger.debug(
"{}({}): State changes DISCONNECTING -> DISCONNECTED. Not attempting to reconnect (User-initiated disconnect)".format(
self.name, event.name
)
)
self.nucleus.connection_state = ConnectionState.DISCONNECTED
# EXPECTED DISCONNECTION (Reauthorization process)
elif self.nucleus.connection_state is ConnectionState.REAUTHORIZING:
# ConnectionState will remain REAUTHORIZING until completion of the process
# upon re-establishing the connection
# NOTE: There is a ~small~ chance of a false positive here if an unexpected
# disconnection occurs while a ReauthorizationOperation is in flight.
# However, it will sort itself out - the ensuing connect that occurs as part
# of the reauthorization will restore connection (no harm done) or it will
# fail, at which point the failure was a result of a manual operation and
# reconnection is not supposed to occur. So either way, we end up where we want
# to be despite the false positive - just be aware that this can happen.
logger.debug(
"{}({}): Not attempting to reconnect (Reauthorization in progress)".format(
self.name, event.name
)
)
# BAD STATE (this block should not be reached)
else:
logger.warning(
"{}: DisconnectEvent received while in unexpected state - {}".format(
self.name, self.nucleus.connection_state
)
)
logger.debug(
"{}({}): State changes {} -> DISCONNECTED. Unexpected disconnect in unexpected state".format(
self.name, event.name, self.nucleus.connection_state
)
)
self.nucleus.connection_state = ConnectionState.DISCONNECTED
# In all cases the event is sent up
self.send_event_up(event)
@pipeline_thread.runs_on_pipeline_thread
def _add_connection_op_callback(self, op):
"""Adds callback to a connection op passing through to do necessary stage upkeep"""
self_weakref = weakref.ref(self)
@pipeline_thread.runs_on_pipeline_thread
def on_complete(op, error):
this = self_weakref()
# If error, set us back to a DISCONNECTED state. It doesn't matter what kind of
# connection op this was, any failure should result in a disconnected state.
# NOTE: Due to the stage waiting any ops if an ongoing connection op is in-progress
# as well as the way that the reconnection process checks if there is an in-progress
# connection op (and punts the reconnect if so), there is no risk here of setting
# directly to DISCONNECTED - the intermediate state being overwritten is always going
# to be due to this op that is now completing, we can be assured of that.
if error:
logger.debug(
"{}({}): failed, state change {} -> DISCONNECTED".format(
this.name, op.name, this.nucleus.connection_state
)
)
this.nucleus.connection_state = ConnectionState.DISCONNECTED
# Allow the next waiting op to proceed (if any)
this._run_all_waiting_ops()
op.add_callback(on_complete)
@pipeline_thread.runs_on_pipeline_thread
def _run_all_waiting_ops(self):
if not self.waiting_ops.empty():
queuecopy = self.waiting_ops
self.waiting_ops = queue.Queue()
while not queuecopy.empty():
next_op = queuecopy.get_nowait()
if not next_op.completed:
logger.debug(
"{}: Resolving next waiting op: {}".format(self.name, next_op.name)
)
self.run_op(next_op)
@pipeline_thread.runs_on_pipeline_thread
def _reconnect(self):
self_weakref = weakref.ref(self)
@pipeline_thread.runs_on_pipeline_thread
def on_reconnect_complete(op, error):
this = self_weakref()
if this:
logger.debug(
"{}({}): on_connect_complete error={} state={} ".format(
this.name,
op.name,
error,
this.nucleus.connection_state,
)
)
if error:
# Set state back to DISCONNECTED so as not to block anything else
logger.debug(
"{}: State change {} -> DISCONNECTED".format(
this.name, this.nucleus.connection_state
)
)
this.nucleus.connection_state = ConnectionState.DISCONNECTED
# report background exception to indicate this failure occurred
this.report_background_exception(error)
# Determine if should try reconnect again
if this._should_reconnect(error):
# transient errors can cause a reconnect attempt
logger.debug(
"{}: Reconnect failed. Starting reconnection timer".format(this.name)
)
this._start_reconnect_timer(
this.nucleus.pipeline_configuration.connection_retry_interval
)
else:
# all others are permanent errors
logger.debug(
"{}: Cannot reconnect. Ending reconnection process".format(this.name)
)
# Now see if there's anything that may have blocked waiting for us to finish
this._run_all_waiting_ops()
# NOTE: I had considered leveraging the run_op infrastructure instead of sending this
# directly down. Ultimately however, I think it's best to keep reconnects completely
# distinct from other operations that come through the pipeline - for instance, we don't
# really want them to end up queued up behind other operations via the .waiting_ops queue.
# Reconnects have a top priority.
op = pipeline_ops_base.ConnectOperation(callback=on_reconnect_complete)
self.send_op_down(op)
@pipeline_thread.runs_on_pipeline_thread
def _should_reconnect(self, error):
"""Returns True if a reconnect should occur in response to an error, False otherwise"""
if self.nucleus.pipeline_configuration.connection_retry:
if type(error) in self.transient_connect_errors:
return True
return False
@pipeline_thread.runs_on_pipeline_thread
def _start_reconnect_timer(self, delay):
"""
Set a timer to reconnect after some period of time
"""
self._clear_reconnect_timer()
self_weakref = weakref.ref(self)
@pipeline_thread.invoke_on_pipeline_thread_nowait
def on_reconnect_timer_expired():
this = self_weakref()
logger.debug(
"{}: Reconnect timer expired. State is {}.".format(
self.name, self.nucleus.connection_state
)
)
# Clear the reconnect timer here first and foremost so it doesn't accidentally
# get left around somehow. Don't use the _clear_reconnect_timer method, as the timer
# has expired, and thus cannot be cancelled.
this.reconnect_timer = None
if this.nucleus.connection_state is ConnectionState.DISCONNECTED:
# We are still disconnected, so reconnect
# NOTE: Because any reconnect timer would have been cancelled upon a manual
# disconnect, there is no way this block could be executing if we were happy
# with our DISCONNECTED state.
logger.debug("{}: Starting reconnection".format(this.name))
logger.debug(
"{}: State changes {} -> CONNECTING. Sending new connect op down in reconnect attempt".format(
self.name, self.nucleus.connection_state
)
)
self.nucleus.connection_state = ConnectionState.CONNECTING
this._reconnect()
elif this.nucleus.connection_state in self.intermediate_states:
# If another connection op is in progress, just wait and try again later to avoid
# any extra confusion (i.e. punt the reconnection)
logger.debug(
"{}: Other connection operation in-progress, setting a new reconnection timer".format(
this.name
)
)
this._start_reconnect_timer(
this.nucleus.pipeline_configuration.connection_retry_interval
)
else:
logger.debug(
"{}: Unexpected state reached ({}) after reconnection timer expired".format(
this.name, this.nucleus.connection_state
)
)
self.reconnect_timer = threading.Timer(delay, on_reconnect_timer_expired)
self.reconnect_timer.start()
@pipeline_thread.runs_on_pipeline_thread
def _clear_reconnect_timer(self):
"""
Clear any previous reconnect timer
"""
if self.reconnect_timer:
logger.debug("{}: clearing reconnect timer".format(self.name))
self.reconnect_timer.cancel()
self.reconnect_timer = None
|
8c2b9a37bc723f7c2f5f4d2f15c3bd2959015a17
|
4091caecbc727e6d6ae0d827afce11c5979a84fd
|
/tools/accuracy_checker/openvino/tools/accuracy_checker/presenters.py
|
43b6ab362225dd526f092a5a1a66211f197322e1
|
[
"Apache-2.0"
] |
permissive
|
openvinotoolkit/open_model_zoo
|
fdb03dd40bfccb854e4ed4f7b9beaa90596963cd
|
7929adbe91e9cfe8dc5dc1daad5ae7392f9719a0
|
refs/heads/master
| 2023-08-18T18:03:47.254427
| 2023-08-18T10:54:31
| 2023-08-18T10:54:31
| 153,097,694
| 1,712
| 730
|
Apache-2.0
| 2023-09-11T11:31:20
| 2018-10-15T10:55:02
|
Python
|
UTF-8
|
Python
| false
| false
| 12,329
|
py
|
presenters.py
|
"""
Copyright (c) 2018-2023 Intel Corporation
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
"""
from collections import namedtuple
from copy import deepcopy
from csv import DictWriter
import numpy as np
from .utils import Color, color_format, check_file_existence
from .dependency import ClassProvider
from .logging import print_info
EvaluationResult = namedtuple(
'EvaluationResult', [
'evaluated_value', 'reference_value', 'name', 'metric_type', 'abs_threshold', 'rel_threshold', 'meta',
'profiling_file'
]
)
class BasePresenter(ClassProvider):
__provider_type__ = "presenter"
def write_result(self, evaluation_result, ignore_results_formatting=False, ignore_metric_reference=False):
raise NotImplementedError
def extract_result(self, evaluation_result, names_from_refs=False):
raise NotImplementedError
class ScalarPrintPresenter(BasePresenter):
__provider__ = "print_scalar"
def write_result(self, evaluation_result: EvaluationResult, ignore_results_formatting=False,
ignore_metric_reference=False):
value, reference, name, _, abs_threshold, rel_threshold, meta, _ = evaluation_result
value = '' if not np.isscalar(value) and (value is None or None in value) else float(np.mean(value))
postfix, scale, result_format = get_result_format_parameters(meta, ignore_results_formatting)
difference = None
if reference and not ignore_metric_reference:
difference = compare_with_ref(reference, value, name)
write_scalar_result(
value, name, abs_threshold, rel_threshold, difference,
postfix=postfix, scale=scale, result_format=result_format
)
def extract_result(self, evaluation_result, names_from_refs=False):
value, ref, name, metric_type, abs_threshold, rel_threshold, meta, profiling_file = evaluation_result
if isinstance(ref, dict):
ref = ref.get(name)
result_dict = {
'name': name,
'value': '' if not np.isscalar(value) and (value is None or None in value) else float(np.mean(value)),
'type': metric_type,
'ref': ref or '',
'abs_threshold': abs_threshold or 0,
'ref_threshold': rel_threshold or 0,
'profiling_file': profiling_file
}
return result_dict, meta
class VectorPrintPresenter(BasePresenter):
__provider__ = "print_vector"
def write_result(self, evaluation_result: EvaluationResult, ignore_results_formatting=False,
ignore_metric_reference=False):
value, reference, name, _, abs_threshold, rel_threshold, meta, _ = evaluation_result
if abs_threshold:
abs_threshold = float(abs_threshold)
if rel_threshold:
rel_threshold = float(rel_threshold)
value_names = meta.get('names')
postfix, scale, result_format = get_result_format_parameters(meta, ignore_results_formatting)
if np.isscalar(value) or np.size(value) == 1:
if not np.isscalar(value):
if np.ndim(value) == 0:
value = value.tolist()
else:
value = value[0]
difference = None
value_name = value_names[0] if value_names else None
if reference and not ignore_metric_reference:
difference = compare_with_ref(reference, value, value_name)
write_scalar_result(
value, name, abs_threshold, rel_threshold, difference,
value_name=value_name,
postfix=postfix[0] if not np.isscalar(postfix) else postfix,
scale=scale[0] if not np.isscalar(scale) else scale,
result_format=result_format
)
return
for index, res in enumerate(value):
difference = None
value_scale = scale[index] if not np.isscalar(scale) else scale
value_name = value_names[index] if value_names else None
if reference and not ignore_metric_reference and isinstance(reference, dict):
difference = compare_with_ref(reference, res, value_name)
write_scalar_result(
res, name, abs_threshold, rel_threshold, difference,
value_name=value_name,
postfix=postfix[index] if not np.isscalar(postfix) else postfix,
scale=value_scale,
result_format=result_format
)
if len(value) > 1 and meta.get('calculate_mean', True):
mean_value = '' if not np.isscalar(value) and (value is None or None in value) else float(np.mean(value))
value_scale = scale[0] if not np.isscalar(scale) else scale
difference = None
if reference and not ignore_metric_reference:
difference = compare_with_ref(reference, mean_value, 'mean')
write_scalar_result(
mean_value, name, abs_threshold, rel_threshold, difference, value_name='mean',
postfix=postfix[-1] if not np.isscalar(postfix) else postfix, scale=value_scale,
result_format=result_format
)
def extract_result(self, evaluation_result, names_from_refs=False):
value, reference, name, metric_type, abs_threshold, rel_threshold, meta, profiling_file = evaluation_result
len_value = len(value) if not np.isscalar(value) and np.ndim(value) > 0 else 1
value_names_orig = meta.get('names', list(range(0, len_value)))
if names_from_refs and isinstance(reference, dict):
calculate_mean = meta.get('calculate_mean', True)
value_names_orig = (
[name for name in reference if name != 'mean'] if calculate_mean else list(reference.keys())
)
value_names = ['{}@{}'.format(name, value_name) for value_name in value_names_orig]
if np.isscalar(value) or np.size(value) <= 1:
value_name = value_names[0] if value_names and 'names' in meta else name
value_name_orig = value_names_orig[0] if value_name != name else name
if isinstance(reference, dict):
ref = reference.get(value_name_orig, '')
else:
ref = reference or ''
if not np.isscalar(value):
if np.ndim(value) == 0:
value = value.tolist()
else:
value = value[0]
result_dict = {
'name': value_name,
'value': value,
'type': metric_type,
'ref': ref,
'abs_threshold': abs_threshold or 0,
'rel_threshold': rel_threshold or 0,
'profiling_file': profiling_file
}
return result_dict, meta
if meta.get('calculate_mean', True):
value_names_orig.append('mean')
value_names.append('{}@mean'.format(name))
mean_value = '' if not np.isscalar(value) and (value is None or None in value) else float(np.mean(value))
value = np.append(value, mean_value)
per_value_meta = []
target_per_value = meta.pop('target_per_value', {})
target = meta.pop('target', 'higher-better')
for orig_name in value_names_orig:
target_for_value = target_per_value.get(orig_name, target)
meta_for_value = deepcopy(meta)
meta_for_value['target'] = target_for_value
meta_for_value['class_name'] = orig_name
per_value_meta.append(meta_for_value)
results = []
for idx, value_item in enumerate(value):
orig_name = value_names_orig[idx]
ref = ''
if isinstance(reference, dict):
ref = reference.get(orig_name, '')
results.append(
{
'name': value_names[idx],
'value': value_item,
'type': metric_type,
'ref': ref,
'abs_threshold': 0,
'rel_threshold': 0
}
)
return results, per_value_meta
def write_scalar_result(
res_value, name, abs_threshold=None, rel_threshold=None, diff_with_ref=None, value_name=None,
postfix='%', scale=100, result_format='{:.2f}'
):
display_name = "{}@{}".format(name, value_name) if value_name else name
display_result = result_format.format(res_value * scale)
message = '{}: {}{}'.format(display_name, display_result, postfix)
if diff_with_ref and (diff_with_ref[0] or diff_with_ref[1]):
abs_threshold = abs_threshold or 0
rel_threshold = rel_threshold or 0
if abs_threshold <= diff_with_ref[0] or rel_threshold <= diff_with_ref[1]:
fail_message = "[FAILED: abs error = {:.4} | relative error = {:.4}]".format(
diff_with_ref[0] * scale, diff_with_ref[1]
)
message = "{} {}".format(message, color_format(fail_message, Color.FAILED))
else:
message = "{} {}".format(message, color_format("[OK]", Color.PASSED))
print_info(message)
def compare_with_ref(reference, res_value, name=None):
if isinstance(reference, dict):
if name is None:
ref = next(iter(reference.values()))
else:
ref = reference.get(name)
else:
ref = reference
ref = ref if ref is None else float(ref)
if ref is None:
return None
return abs(ref - res_value), abs(ref - res_value) / ref
def get_result_format_parameters(meta, use_default_formatting):
postfix = ' '
scale = 1
result_format = '{}'
if not use_default_formatting:
postfix = meta.get('postfix', '%')
scale = meta.get('scale', 100)
result_format = meta.get('data_format', '{:.2f}')
return postfix, scale, result_format
def generate_csv_report(processing_info, metric_results, dataset_size, metrics_meta):
field_names = [
'model', 'launcher', 'device', 'dataset',
'tags', 'metric_name', 'metric_type', 'metric_value', 'metric_target', 'metric_scale', 'metric_postfix',
'dataset_size', 'ref', 'abs_threshold', 'rel_threshold', 'profiling_file']
model, launcher, device, tags, dataset = processing_info
main_info = {
'model': model,
'launcher': launcher,
'device': device.upper(),
'tags': ' '.join(tags) if tags else '',
'dataset': dataset,
'dataset_size': dataset_size
}
rows = []
for metric_result, metric_meta in zip(metric_results, metrics_meta):
rows.append({
**main_info,
'metric_name': metric_result['name'],
'metric_type': metric_result['type'],
'metric_value': metric_result['value'],
'metric_target': metric_meta.get('target', 'higher-better'),
'metric_scale': metric_meta.get('scale', 100),
'metric_postfix': metric_meta.get('postfix', '%'),
'ref': metric_result.get('ref', ''),
'abs_threshold': metric_result.get('abs_threshold', 0),
'rel_threshold': metric_result.get('rel_threshold', 0),
'profiling_file': metric_result.get('profiling_file', '')
})
return field_names, rows
def write_csv_result(csv_file, processing_info, metric_results, dataset_size, metrics_meta):
new_file = not check_file_existence(csv_file)
field_names, rows = generate_csv_report(processing_info, metric_results, dataset_size, metrics_meta)
with open(csv_file, 'a+', newline='', encoding='utf-8') as f:
writer = DictWriter(f, fieldnames=field_names)
if new_file:
writer.writeheader()
writer.writerows(rows)
|
8bd8bf00787800f73f1004bb7ca688d49ce3a018
|
5dc77586e3e0f9de1f032fd2ca68494d8e58928f
|
/great_expectations/core/usage_statistics/schemas.py
|
97bbefea7c5d16bc109c41db7f95405c1c971969
|
[
"Apache-2.0"
] |
permissive
|
great-expectations/great_expectations
|
dd7c22e6277d6b08bee3ff38a015e6e8cd434df6
|
b0290e2fd2aa05aec6d7d8871b91cb4478e9501d
|
refs/heads/develop
| 2023-09-04T09:30:26.395518
| 2023-09-02T00:00:13
| 2023-09-02T00:00:13
| 103,071,520
| 8,931
| 1,535
|
Apache-2.0
| 2023-09-14T19:57:16
| 2017-09-11T00:18:46
|
Python
|
UTF-8
|
Python
| false
| false
| 45,158
|
py
|
schemas.py
|
###
# These schemas are used to ensure that we *never* take unexpected usage stats message and provide full transparency
# about usage statistics. Please reach out to the Great Expectations with any questions!
###
from typing import List
from great_expectations.core.usage_statistics.anonymizers.types.base import (
CLISuiteInteractiveFlagCombinations,
)
# An anonymized string *must* be an md5 hash, so must have exactly 32 characters
from great_expectations.core.usage_statistics.events import UsageStatsEvents
from great_expectations.core.usage_statistics.execution_environment import (
InstallEnvironment,
)
SCHEMA: str = "https://json-schema.org/draft/2020-12/schema"
ALLOWED_VERSIONS: List[str] = ["1.0.0", "1.0.1", "2"]
anonymized_string_schema = {
"$schema": SCHEMA,
"title": "anonymized-string",
"type": "string",
"minLength": 32,
"maxLength": 32,
}
anonymized_datasource_name_schema = {
"$schema": SCHEMA,
"title": "anonymized-datasource-name",
"definitions": {"anonymized_string": anonymized_string_schema},
"anyOf": [
{
"type": "string",
"maxLength": 256,
},
{
"$ref": "#/definitions/anonymized_string",
},
],
}
anonymized_run_time_schema = {
"$schema": SCHEMA,
"title": "anonymized-run-time",
"definitions": {"anonymized_string": anonymized_string_schema},
"anyOf": [
{
"type": "string",
"format": "date-time",
},
{
"$ref": "#/definitions/anonymized_string",
},
],
}
anonymized_class_info_schema = {
"$schema": SCHEMA,
"title": "anonymized-class-info",
"definitions": {"anonymized_string": anonymized_string_schema},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
},
"additionalProperties": True,
# we don't want this to be true, but this is required to allow show_cta_footer
# Note AJB-20201218 show_cta_footer was removed in v 0.9.9 via PR #1249
"required": ["parent_class"],
},
],
}
anonymized_datasource_schema = {
"$schema": SCHEMA,
"title": "anonymized-datasource",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_class_info": anonymized_class_info_schema,
},
"anyOf": [
# v2 (Batch Kwargs) API:
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"sqlalchemy_dialect": {"type": "string", "maxLength": 256},
},
"additionalProperties": False,
"required": ["parent_class", "anonymized_name"],
},
# v3 (Batch Request) API:
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"sqlalchemy_dialect": {"type": "string", "maxLength": 256},
"anonymized_execution_engine": {
"$ref": "#/definitions/anonymized_class_info"
},
"anonymized_data_connectors": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_class_info"},
},
},
"additionalProperties": False,
"required": ["parent_class", "anonymized_name"],
},
],
}
anonymized_store_schema = {
"$schema": SCHEMA,
"title": "anonymized-store",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_class_info": anonymized_class_info_schema,
},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"anonymized_store_backend": {
"$ref": "#/definitions/anonymized_class_info"
},
},
"additionalProperties": False,
"required": ["parent_class", "anonymized_name"],
},
],
}
anonymized_action_schema = {
"$schema": SCHEMA,
"title": "anonymized-action",
"definitions": {"anonymized_string": anonymized_string_schema},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
},
"additionalProperties": False,
"required": ["parent_class", "anonymized_name"],
},
],
}
anonymized_action_list_schema = {
"$schema": SCHEMA,
"title": "anonymized-action-list",
"definitions": {"anonymized_action": anonymized_action_schema},
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_action"},
}
anonymized_validation_operator_schema = {
"$schema": SCHEMA,
"title": "anonymized-validation-operator",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_action_list": anonymized_action_list_schema,
},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"anonymized_action_list": {
"$ref": "#/definitions/anonymized_action_list"
},
},
"additionalProperties": False,
"required": ["parent_class", "anonymized_name"],
},
],
}
empty_payload_schema = {
"$schema": SCHEMA,
"title": "empty-payload",
"type": "object",
"properties": {},
"additionalProperties": False,
}
anonymized_data_docs_site_schema = {
"$schema": SCHEMA,
"title": "anonymized-data-docs-site",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_class_info": anonymized_class_info_schema,
},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"anonymized_store_backend": {
"$ref": "#/definitions/anonymized_class_info"
},
"anonymized_site_index_builder": {
"$ref": "#/definitions/anonymized_class_info"
},
},
"additionalProperties": False,
"required": ["parent_class", "anonymized_name"],
},
],
}
anonymized_expectation_suite_schema = {
"$schema": SCHEMA,
"title": "anonymized-expectation-suite",
"definitions": {"anonymized_string": anonymized_string_schema},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"expectation_count": {"type": "number"},
"anonymized_expectation_type_counts": {"type": "object"},
},
"additionalProperties": False,
},
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"expectation_count": {"type": "number"},
"anonymized_expectation_counts": {
"type": "array",
"items": {
"type": "object",
"properties": {
"expectation_type": {"type": "string"},
"anonymized_expectation_type": {
"$ref": "#/definitions/anonymized_string"
},
"count": {"type": "number"},
},
},
},
},
"additionalProperties": False,
},
],
}
package_info_schema = {
"$schema": SCHEMA,
"title": "package-info",
"type": "object",
"properties": {
"package_name": {"type": "string", "maxLength": 256},
"installed": {"type": "boolean"},
"install_environment": {
"enum": [ie.value for ie in InstallEnvironment],
},
"version": {"anyOf": [{"type": "string", "maxLength": 256}, {"type": "null"}]},
},
"additionalProperties": False,
}
anonymized_init_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-init-payload",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_class_info": anonymized_class_info_schema,
"anonymized_datasource": anonymized_datasource_schema,
"anonymized_validation_operator": anonymized_validation_operator_schema,
"anonymized_data_docs_site": anonymized_data_docs_site_schema,
"anonymized_store": anonymized_store_schema,
"anonymized_action": anonymized_action_schema,
"anonymized_action_list": anonymized_action_list_schema,
"anonymized_expectation_suite": anonymized_expectation_suite_schema,
"package_info": package_info_schema,
},
"type": "object",
"properties": {
"version": {"enum": ALLOWED_VERSIONS},
"platform.system": {"type": "string", "maxLength": 256},
"platform.release": {"type": "string", "maxLength": 256},
"version_info": {"type": "string", "maxLength": 256},
"anonymized_datasources": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_datasource"},
},
"anonymized_stores": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_store"},
},
"anonymized_validation_operators": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_validation_operator"},
},
"anonymized_data_docs_sites": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_data_docs_site"},
},
"anonymized_expectation_suites": {
"type": "array",
"items": {"$ref": "#/definitions/anonymized_expectation_suite"},
},
"dependencies": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/package_info"},
},
},
"required": [
"platform.system",
"platform.release",
"version_info",
"anonymized_datasources",
"anonymized_stores",
"anonymized_data_docs_sites",
"anonymized_expectation_suites",
],
"additionalProperties": False,
}
anonymized_batch_request_schema = {
"$schema": SCHEMA,
"title": "anonymized-batch-request",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
},
"type": "object",
"properties": {
"anonymized_batch_request_required_top_level_properties": {
"type": "object",
"properties": {
"anonymized_datasource_name": {
"$ref": "#/definitions/anonymized_datasource_name",
},
"anonymized_data_connector_name": {
"$ref": "#/definitions/anonymized_string",
},
"anonymized_data_asset_name": {
"$ref": "#/definitions/anonymized_string",
},
},
"required": [
"anonymized_datasource_name",
"anonymized_data_connector_name",
"anonymized_data_asset_name",
],
"additionalProperties": False,
},
"batch_request_optional_top_level_keys": {
"type": "array",
"minItems": 1,
"maxItems": 4,
"items": {
"type": "string",
"enum": [
"batch_identifiers",
"batch_spec_passthrough",
"data_connector_query",
"runtime_parameters",
],
},
"uniqueItems": True,
},
"data_connector_query_keys": {
"type": "array",
"minItems": 1,
"maxItems": 4,
"items": {
"type": "string",
"enum": [
"batch_filter_parameters",
"custom_filter_function",
"index",
"limit",
],
},
"uniqueItems": True,
},
"runtime_parameters_keys": {
"type": "array",
"minItems": 1,
"maxItems": 1,
"items": {
"type": "string",
"enum": [
"batch_data",
"query",
"path",
],
},
},
"batch_spec_passthrough_keys": {
"type": "array",
"minItems": 1,
"maxItems": 6,
"items": {
"type": "string",
"enum": [
"reader_method",
"reader_options",
"sampling_method",
"sampling_kwargs",
"splitter_method",
"splitter_kwargs",
],
},
"uniqueItems": True,
},
},
"additionalProperties": False,
}
anonymized_batch_schema = {
"$schema": SCHEMA,
"title": "anonymized-batch",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_batch_kwarg_keys": {
"type": "array",
"maxItems": 1000,
"items": {"oneOf": [{"type": "string", "maxLength": 256}]},
},
"anonymized_expectation_suite_name": {
"$ref": "#/definitions/anonymized_string"
},
"anonymized_datasource_name": {
"$ref": "#/definitions/anonymized_datasource_name",
},
},
"additionalProperties": False,
"required": [
"anonymized_batch_kwarg_keys",
"anonymized_expectation_suite_name",
"anonymized_datasource_name",
],
},
],
}
anonymized_run_validation_operator_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-run-validation-operator-payload",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_batch": anonymized_batch_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
},
"type": "object",
"properties": {
"anonymized_operator_name": {"$ref": "#/definitions/anonymized_string"},
"anonymized_batches": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_batch"},
},
},
"required": ["anonymized_operator_name"],
"additionalProperties": False,
}
anonymized_validation_schema = {
"$schema": SCHEMA,
"title": "anonymized-validation",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_action_list": anonymized_action_list_schema,
},
"type": "object",
"properties": {
"anonymized_batch_request": {"$ref": "#/definitions/anonymized_batch_request"},
"anonymized_expectation_suite_name": {
"$ref": "#/definitions/anonymized_string"
},
"anonymized_action_list": {"$ref": "#/definitions/anonymized_action_list"},
},
"additionalProperties": False,
}
anonymized_validations_list_schema = {
"$schema": SCHEMA,
"title": "anonymized-validations",
"definitions": {"anonymized_validation": anonymized_validation_schema},
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_validation"},
}
anonymized_get_or_edit_or_save_expectation_suite_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-get-or-edit-or-save-expectation-suite-payload",
"definitions": {"anonymized_string": anonymized_string_schema},
"type": "object",
"properties": {
"anonymized_expectation_suite_name": {
"$ref": "#/definitions/anonymized_string"
},
},
"required": ["anonymized_expectation_suite_name"],
"additionalProperties": False,
}
anonymized_cli_suite_expectation_suite_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-cli-suite-expectation-suite-payload",
"definitions": {"anonymized_string": anonymized_string_schema},
"type": "object",
"properties": {
"interactive_flag": {
"type": ["boolean", "null"],
},
"interactive_attribution": {
"enum": [
element.value["interactive_attribution"]
for element in CLISuiteInteractiveFlagCombinations
],
},
"api_version": {"type": "string", "maxLength": 256},
"cancelled": {
"type": ["boolean", "null"],
},
},
}
anonymized_cli_suite_new_expectation_suite_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-cli-suite-new-expectation-suite-payload",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_cli_suite_expectation_suite_payload": anonymized_cli_suite_expectation_suite_payload_schema,
},
"items": {
"$ref": "#/definitions/anonymized_cli_suite_expectation_suite_payload",
"properties": {
"anonymized_expectation_suite_name": {
"$ref": "#/definitions/anonymized_string"
},
},
"additionalProperties": False,
},
}
anonymized_cli_suite_edit_expectation_suite_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-cli-suite-edit-expectation-suite-payload",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_cli_suite_expectation_suite_payload": anonymized_cli_suite_expectation_suite_payload_schema,
},
"items": {
"$ref": "#/definitions/anonymized_cli_suite_expectation_suite_payload",
"properties": {
"anonymized_expectation_suite_name": {
"$ref": "#/definitions/anonymized_string"
},
},
"required": ["anonymized_expectation_suite_name"],
"additionalProperties": False,
},
}
anonymized_cli_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-cli-payload",
"type": "object",
"properties": {
"api_version": {
"type": "string",
"maxLength": 256,
},
"cancelled": {
"type": ["boolean", "null"],
},
},
"additionalProperties": False,
}
anonymized_cli_new_ds_choice_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-cli-new-ds-choice-payload",
"type": "object",
"properties": {
"type": {"type": "string", "maxLength": 256},
"db": {"type": "string", "maxLength": 256},
"api_version": {"type": "string", "maxLength": 256},
},
"required": ["type"],
"additionalProperties": False,
}
anonymized_datasource_sqlalchemy_connect_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-datasource-sqlalchemy-connect-payload",
"type": "object",
"properties": {
"anonymized_name": {"type": "string", "maxLength": 256},
"sqlalchemy_dialect": {"type": "string", "maxLength": 256},
},
"required": ["anonymized_name"],
"additionalProperties": False,
}
anonymized_test_yaml_config_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-test-yaml-config-payload",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_class_info": anonymized_class_info_schema,
},
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"diagnostic_info": {
"type": "array",
"maxItems": 1000,
"items": {
"enum": [
"__substitution_error__",
"__yaml_parse_error__",
"__custom_subclass_not_core_ge__",
"__class_name_not_provided__",
],
},
},
# Store
"anonymized_store_backend": {"$ref": "#/definitions/anonymized_class_info"},
# Datasource v2 (Batch Kwargs) API & v3 (Batch Request) API:
"sqlalchemy_dialect": {"type": "string", "maxLength": 256},
# Datasource v3 (Batch Request) API only:
"anonymized_execution_engine": {"$ref": "#/definitions/anonymized_class_info"},
"anonymized_data_connectors": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_class_info"},
},
},
"additionalProperties": False,
}
anonymized_checkpoint_run_schema = {
"$schema": SCHEMA,
"title": "anonymized-checkpoint-run-payload",
"definitions": {
"empty_payload": empty_payload_schema,
"anonymized_string": anonymized_string_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
"anonymized_run_time": anonymized_run_time_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_action": anonymized_action_schema,
"anonymized_action_list": anonymized_action_list_schema,
"anonymized_validation": anonymized_validation_schema,
"anonymized_validations": anonymized_validations_list_schema,
},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"config_version": {"type": "number", "minimum": 1},
"anonymized_template_name": {"$ref": "#/definitions/anonymized_string"},
"anonymized_run_name_template": {
"$ref": "#/definitions/anonymized_string"
},
"anonymized_expectation_suite_name": {
"$ref": "#/definitions/anonymized_string"
},
"anonymized_batch_request": {
"$ref": "#/definitions/anonymized_batch_request"
},
"anonymized_action_list": {
"$ref": "#/definitions/anonymized_action_list"
},
"anonymized_validations": {
"$ref": "#/definitions/anonymized_validations"
},
"anonymized_run_id": {"$ref": "#/definitions/anonymized_string"},
"anonymized_run_name": {"$ref": "#/definitions/anonymized_run_name"},
"anonymized_run_time": {"$ref": "#/definitions/anonymized_run_time"},
"anonymized_expectation_suite_ge_cloud_id": {
"$ref": "#/definitions/anonymized_string"
},
"checkpoint_optional_top_level_keys": {
"type": "array",
"minItems": 1,
"maxItems": 3,
"items": {
"type": "string",
"enum": [
"evaluation_parameters",
"runtime_configuration",
"profilers",
],
},
"uniqueItems": True,
},
},
"required": ["anonymized_name", "config_version"],
"additionalProperties": False,
},
{"$ref": "#/definitions/empty_payload"},
],
}
anonymized_legacy_profiler_build_suite_payload_schema = {
"$schema": SCHEMA,
"title": "anonymized-legacy-profiler-build-suite-payload",
"type": "object",
"properties": {
"profile_dataset_type": {"type": "string", "maxLength": 256},
"excluded_expectations_specified": {
"type": ["boolean"],
},
"ignored_columns_specified": {
"type": ["boolean"],
},
"not_null_only": {
"type": ["boolean"],
},
"primary_or_compound_key_specified": {
"type": ["boolean"],
},
"semantic_types_dict_specified": {
"type": ["boolean"],
},
"table_expectations_only": {
"type": ["boolean"],
},
"value_set_threshold_specified": {
"type": ["boolean"],
},
"api_version": {"type": "string", "maxLength": 256},
},
"required": [
"profile_dataset_type",
"excluded_expectations_specified",
"ignored_columns_specified",
"not_null_only",
"primary_or_compound_key_specified",
"semantic_types_dict_specified",
"table_expectations_only",
"value_set_threshold_specified",
"api_version",
],
"additionalProperties": False,
}
anonymized_domain_builder_schema = {
"$schema": SCHEMA,
"title": "anonymized-domain-builder",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
},
"type": "object",
"properties": {
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"anonymized_batch_request": {"$ref": "#/definitions/anonymized_batch_request"},
},
"additionalProperties": False,
"required": ["parent_class"],
}
anonymized_parameter_builder_schema = {
"$schema": SCHEMA,
"title": "anonymized-parameter-builder",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
},
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"anonymized_batch_request": {"$ref": "#/definitions/anonymized_batch_request"},
},
"additionalProperties": False,
"required": ["anonymized_name", "parent_class"],
}
anonymized_expectation_configuration_builder_schema = {
"$schema": SCHEMA,
"title": "anonymized-expectation-configuration-builder",
"definitions": {
"anonymized_string": anonymized_string_schema,
},
"type": "object",
"properties": {
"parent_class": {"type": "string", "maxLength": 256},
"anonymized_class": {"$ref": "#/definitions/anonymized_string"},
"expectation_type": {"type": "string", "maxLength": 256},
"anonymized_expectation_type": {"$ref": "#/definitions/anonymized_string"},
"anonymized_condition": {"$ref": "#/definitions/anonymized_string"},
},
"additionalProperties": False,
"required": ["parent_class"],
}
anonymized_rule_schema = {
"$schema": SCHEMA,
"title": "anonymized-rules",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_domain_builder": anonymized_domain_builder_schema,
"anonymized_parameter_builder": anonymized_parameter_builder_schema,
"anonymized_expectation_configuration_builder": anonymized_expectation_configuration_builder_schema,
},
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"anonymized_domain_builder": {
"$ref": "#/definitions/anonymized_domain_builder"
},
"anonymized_parameter_builders": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_parameter_builder"},
},
"anonymized_expectation_configuration_builders": {
"type": "array",
"maxItems": 1000,
"items": {
"$ref": "#/definitions/anonymized_expectation_configuration_builder"
},
},
},
"additionalProperties": False,
"required": ["anonymized_name", "anonymized_expectation_configuration_builders"],
}
anonymized_rule_based_profiler_run_schema = {
"$schema": SCHEMA,
"title": "anonymized-rule-based-profiler-run-payload",
"definitions": {
"empty_payload": empty_payload_schema,
"anonymized_string": anonymized_string_schema,
"anonymized_rule": anonymized_rule_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_domain_builder": anonymized_domain_builder_schema,
"anonymized_parameter_builder": anonymized_parameter_builder_schema,
"anonymized_expectation_configuration_builder": anonymized_expectation_configuration_builder_schema,
},
"oneOf": [
{
"type": "object",
"properties": {
"anonymized_name": {"$ref": "#/definitions/anonymized_string"},
"config_version": {"type": "number", "minimum": 1},
"rule_count": {"type": "number", "minimum": 0},
"variable_count": {"type": "number", "minimum": 0},
"anonymized_rules": {
"type": "array",
"maxItems": 1000,
"items": {"$ref": "#/definitions/anonymized_rule"},
},
},
"required": [
"anonymized_name",
"config_version",
"rule_count",
"variable_count",
"anonymized_rules",
],
"additionalProperties": False,
},
{"$ref": "#/definitions/empty_payload"},
],
}
cloud_migrate_schema = {
"$schema": SCHEMA,
"title": "cloud-migrate",
"type": "object",
"properties": {
"organization_id": {"type": "string", "maxLength": 256},
},
"required": ["organization_id"],
"additionalProperties": False,
}
anonymized_usage_statistics_record_schema = {
"$schema": SCHEMA,
"title": "anonymized-usage-statistics-record",
"definitions": {
"anonymized_string": anonymized_string_schema,
"anonymized_datasource_name": anonymized_datasource_name_schema,
"anonymized_datasource": anonymized_datasource_schema,
"anonymized_store": anonymized_store_schema,
"anonymized_class_info": anonymized_class_info_schema,
"anonymized_validation_operator": anonymized_validation_operator_schema,
"anonymized_action": anonymized_action_schema,
"anonymized_action_list": anonymized_action_list_schema,
"empty_payload": empty_payload_schema,
"anonymized_init_payload": anonymized_init_payload_schema,
"anonymized_run_validation_operator_payload": anonymized_run_validation_operator_payload_schema,
"anonymized_data_docs_site": anonymized_data_docs_site_schema,
"anonymized_batch_request": anonymized_batch_request_schema,
"anonymized_batch": anonymized_batch_schema,
"anonymized_expectation_suite": anonymized_expectation_suite_schema,
"anonymized_get_or_edit_or_save_expectation_suite_payload": anonymized_get_or_edit_or_save_expectation_suite_payload_schema,
"anonymized_cli_suite_expectation_suite_payload": anonymized_cli_suite_expectation_suite_payload_schema,
"anonymized_cli_suite_new_expectation_suite_payload": anonymized_cli_suite_new_expectation_suite_payload_schema,
"anonymized_cli_suite_edit_expectation_suite_payload": anonymized_cli_suite_edit_expectation_suite_payload_schema,
"anonymized_cli_payload": anonymized_cli_payload_schema,
"anonymized_cli_new_ds_choice_payload": anonymized_cli_new_ds_choice_payload_schema,
"anonymized_datasource_sqlalchemy_connect_payload": anonymized_datasource_sqlalchemy_connect_payload_schema,
"anonymized_test_yaml_config_payload": anonymized_test_yaml_config_payload_schema,
"anonymized_validation": anonymized_validation_schema,
"anonymized_validations": anonymized_validations_list_schema,
"anonymized_checkpoint_run": anonymized_checkpoint_run_schema,
"anonymized_legacy_profiler_build_suite_payload": anonymized_legacy_profiler_build_suite_payload_schema,
"anonymized_domain_builder": anonymized_domain_builder_schema,
"anonymized_parameter_builder": anonymized_parameter_builder_schema,
"anonymized_expectation_configuration_builder": anonymized_expectation_configuration_builder_schema,
"anonymized_rule": anonymized_rule_schema,
"anonymized_rule_based_profiler_run": anonymized_rule_based_profiler_run_schema,
"package_info": package_info_schema,
"cloud_migrate": cloud_migrate_schema,
},
"type": "object",
"properties": {
"version": {"enum": ALLOWED_VERSIONS},
"ge_version": {"type": "string", "maxLength": 32},
"data_context_id": {"type": "string", "format": "uuid"},
"data_context_instance_id": {"type": "string", "format": "uuid"},
"mac_address": {"type": "string"},
"oss_id": {"type": ["string", "null"], "format": "uuid"},
"event_time": {"type": "string", "format": "date-time"},
"event_duration": {"type": "number"},
"x-forwarded-for": {"type": "string"},
"success": {"type": ["boolean", "null"]},
},
"oneOf": [
{
"type": "object",
"properties": {
"event": {"enum": ["data_context.__init__"]},
"event_payload": {"$ref": "#/definitions/anonymized_init_payload"},
},
},
{
"type": "object",
"properties": {
"event": {"enum": ["data_context.run_validation_operator"]},
"event_payload": {
"$ref": "#/definitions/anonymized_run_validation_operator_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {"enum": ["data_context.get_batch_list"]},
"event_payload": {"$ref": "#/definitions/anonymized_batch_request"},
},
},
{
"type": "object",
"properties": {
"event": {"enum": ["data_asset.validate"]},
"event_payload": {"$ref": "#/definitions/anonymized_batch"},
},
},
{
"type": "object",
"properties": {
"event": {"enum": ["cli.new_ds_choice"]},
"event_payload": {
"$ref": "#/definitions/anonymized_cli_new_ds_choice_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {"enum": ["data_context.add_datasource"]},
"event_payload": {"$ref": "#/definitions/anonymized_datasource"},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": [
"datasource.sqlalchemy.connect",
"execution_engine.sqlalchemy.connect",
]
},
"event_payload": {
"$ref": "#/definitions/anonymized_datasource_sqlalchemy_connect_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": [
"data_context.build_data_docs",
"data_context.open_data_docs",
"data_context.run_checkpoint",
"expectation_suite.add_expectation",
"data_context.run_profiler_with_dynamic_arguments",
"data_context.run_profiler_on_data",
],
},
"event_payload": {"$ref": "#/definitions/empty_payload"},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": [
"data_context.save_expectation_suite",
"profiler.result.get_expectation_suite",
"data_assistant.result.get_expectation_suite",
],
},
"event_payload": {
"$ref": "#/definitions/anonymized_get_or_edit_or_save_expectation_suite_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": ["data_context.test_yaml_config"],
},
"event_payload": {
"$ref": "#/definitions/anonymized_test_yaml_config_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": [
"cli.suite.new",
"cli.suite.new.begin",
"cli.suite.new.end",
],
},
"event_payload": {
"$ref": "#/definitions/anonymized_cli_suite_new_expectation_suite_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": [
"cli.suite.edit",
"cli.suite.edit.begin",
"cli.suite.edit.end",
],
},
"event_payload": {
"$ref": "#/definitions/anonymized_cli_suite_edit_expectation_suite_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": ["checkpoint.run"],
},
"event_payload": {"$ref": "#/definitions/anonymized_checkpoint_run"},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": ["legacy_profiler.build_suite"],
},
"event_payload": {
"$ref": "#/definitions/anonymized_legacy_profiler_build_suite_payload"
},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": ["profiler.run"],
},
"event_payload": {
"$ref": "#/definitions/anonymized_rule_based_profiler_run"
},
},
},
{
"type": "object",
"properties": {
"event": {"enum": [UsageStatsEvents.CLOUD_MIGRATE]},
"event_payload": {"$ref": "#/definitions/cloud_migrate"},
},
},
{
"type": "object",
"properties": {
"event": {
"enum": [
"cli.checkpoint.delete",
"cli.checkpoint.delete.begin",
"cli.checkpoint.delete.end",
"cli.checkpoint.list",
"cli.checkpoint.list.begin",
"cli.checkpoint.list.end",
"cli.checkpoint.new",
"cli.checkpoint.new.begin",
"cli.checkpoint.new.end",
"cli.checkpoint.run",
"cli.checkpoint.run.begin",
"cli.checkpoint.run.end",
"cli.checkpoint.script",
"cli.checkpoint.script.begin",
"cli.checkpoint.script.end",
"cli.datasource.list",
"cli.datasource.list.begin",
"cli.datasource.list.end",
"cli.datasource.new",
"cli.datasource.new.begin",
"cli.datasource.new.end",
"cli.datasource.delete",
"cli.datasource.delete.begin",
"cli.datasource.delete.end",
"cli.datasource.profile",
"cli.docs.build",
"cli.docs.build.begin",
"cli.docs.build.end",
"cli.docs.clean",
"cli.docs.clean.begin",
"cli.docs.clean.end",
"cli.docs.list",
"cli.docs.list.begin",
"cli.docs.list.end",
"cli.init.create",
"cli.project.check_config",
"cli.project.upgrade.begin",
"cli.project.upgrade.end",
"cli.store.list",
"cli.store.list.begin",
"cli.store.list.end",
"cli.suite.delete",
"cli.suite.delete.begin",
"cli.suite.delete.end",
"cli.suite.demo",
"cli.suite.demo.begin",
"cli.suite.demo.end",
"cli.suite.list",
"cli.suite.list.begin",
"cli.suite.list.end",
"cli.suite.scaffold",
"cli.validation_operator.list",
"cli.validation_operator.run",
],
},
"event_payload": {"$ref": "#/definitions/anonymized_cli_payload"},
},
},
],
"required": [
"version",
"event_time",
"data_context_id",
"data_context_instance_id",
"ge_version",
"event",
"success",
"event_payload",
],
}
def write_schema_to_file(target_dir: str) -> None:
"""Utility to write schema to disk.
The file name will always be "usage_statistics_record_schema.json" but the target directory can be specified.
Args:
target_dir (str): The dir you wish to write the schema to.
"""
import json
import os
file: str = "usage_statistics_record_schema.json"
out: str = os.path.join(target_dir, file) # noqa: PTH118
with open(out, "w") as outfile:
json.dump(anonymized_usage_statistics_record_schema, outfile, indent=2)
if __name__ == "__main__":
import sys
target_dir = sys.argv[1] if len(sys.argv) >= 2 else "." # noqa: PLR2004
write_schema_to_file(target_dir)
|
2ce229a5bdc50b270f03ab436adf892082358cf2
|
a902290fb3b911676358ae4d93f83061a6c2bd0f
|
/InvenTree/part/migrations/0084_partcategory_icon.py
|
8b92cfaad0bebadec58d434157185dd896024731
|
[
"MIT",
"LicenseRef-scancode-unknown-license-reference"
] |
permissive
|
inventree/InvenTree
|
a15e54182c9bfafdf5348cc9a66da1004e23e760
|
e88a8e99a5f0b201c67a95cba097c729f090d5e2
|
refs/heads/master
| 2023-09-03T19:32:35.438375
| 2023-08-30T00:25:40
| 2023-08-30T00:25:40
| 85,894,461
| 3,077
| 549
|
MIT
| 2023-09-14T14:21:01
| 2017-03-23T01:44:10
|
Python
|
UTF-8
|
Python
| false
| false
| 449
|
py
|
0084_partcategory_icon.py
|
# Generated by Django 3.2.15 on 2022-08-15 08:38
from django.db import migrations, models
class Migration(migrations.Migration):
dependencies = [
('part', '0083_auto_20220731_2357'),
]
operations = [
migrations.AddField(
model_name='partcategory',
name='icon',
field=models.CharField(blank=True, help_text='Icon (optional)', max_length=100, verbose_name='Icon'),
),
]
|
6d734ef69b61849c146b1dadb3f6282a25469026
|
0760fb4901a75766921a205b55686d6d6f049b30
|
/ci/lint/check_api_annotations.py
|
4f5ee74b3ce8100b0b6c97ec809e807365df7f17
|
[
"Apache-2.0",
"MIT",
"BSD-3-Clause"
] |
permissive
|
ray-project/ray
|
a4bb6940b08b59a61ef0b8e755a52d8563a2f867
|
edba68c3e7cf255d1d6479329f305adb7fa4c3ed
|
refs/heads/master
| 2023-08-31T03:36:48.164405
| 2023-08-31T03:20:38
| 2023-08-31T03:20:38
| 71,932,349
| 29,482
| 5,669
|
Apache-2.0
| 2023-09-14T21:48:14
| 2016-10-25T19:38:30
|
Python
|
UTF-8
|
Python
| false
| false
| 3,207
|
py
|
check_api_annotations.py
|
#!/usr/bin/env python
import inspect
import ray
from ray.util.annotations import _is_annotated
IGNORE_PATHS = {
".impl.",
".backend.",
".experimental.",
".internal.",
".generated.",
".test_utils.",
".annotations.",
".deprecation.",
".protobuf.",
".cloudpickle.",
}
def _fullname(attr):
"""Fully qualified name of an attribute."""
fullname = ""
try:
if hasattr(attr, "__module__"):
fullname += attr.__module__
if hasattr(attr, "__name__"):
if fullname:
fullname += "."
fullname += attr.__name__
if not fullname:
fullname = str(attr)
except Exception as e:
print("Error qualifying", e)
return fullname
def _ignore(attr, extra_ignore):
"""Whether an attr should be ignored from annotation checking."""
attr = _fullname(attr)
if "ray." not in attr or "._" in attr:
return True
for path in IGNORE_PATHS:
if path in attr:
return True
for path in extra_ignore or []:
if path in attr:
return True
return False
def verify(symbol, scanned, ok, output, prefix=None, ignore=None):
"""Recursively verify all child symbols of a given module."""
if not prefix:
prefix = symbol.__name__ + "."
if symbol in scanned:
return
scanned.add(symbol)
for child in dir(symbol):
if child.startswith("_"):
continue
attr = getattr(symbol, child)
if _ignore(attr, ignore):
continue
if (inspect.isclass(attr) or inspect.isfunction(attr)) and prefix in _fullname(
attr
):
print("Scanning class", attr)
if _is_annotated(attr):
if attr not in scanned:
print("OK:", _fullname(attr))
ok.add(attr)
else:
output.add(attr)
scanned.add(attr)
elif inspect.ismodule(attr):
print("Scanning module", attr)
verify(attr, scanned, ok, output, prefix, ignore)
else:
print("Not scanning", attr, type(attr))
if __name__ == "__main__":
import ray.data
import ray.rllib
import ray.serve
import ray.train
import ray.tune
import ray.workflow
output = set()
ok = set()
verify(ray.data, set(), ok, output)
# Sanity check the lint logic.
assert len(ok) >= 60, len(ok)
verify(ray.rllib, set(), ok, output)
verify(ray.air, set(), ok, output)
verify(ray.train, set(), ok, output)
verify(ray.tune, set(), ok, output)
verify(
ray,
set(),
ok,
output,
ignore=["ray.workflow", "ray.tune", "ray.serve"],
)
verify(ray.serve, set(), ok, output)
assert len(ok) >= 500, len(ok)
# TODO(ekl) enable it for all modules.
# verify(ray.tune, set(), ok, output)
# verify(ray.workflow, set(), ok, output)
print("Num ok", len(ok))
print("Num bad", len(output))
print("!!! No API stability annotation found for:")
for x in sorted([_fullname(x) for x in output]):
print(x)
if output:
exit(1)
|
dd63b64e80f5dfc0914b8ae21f99cd6a92478c37
|
a40ad075eeadf753167a7e9be2bb41253bb443e9
|
/lit_nlp/api/dataset.py
|
d3166927a429871f9924fdf5982d698bd9fe71c1
|
[
"Apache-2.0"
] |
permissive
|
PAIR-code/lit
|
1cd55c5471bd24a8205174d3a40a2ec91ea56d27
|
a41130960d6ccb92acf6ffc603377eaecce8a62b
|
refs/heads/main
| 2023-09-05T15:35:22.731062
| 2022-12-02T19:48:37
| 2022-12-02T19:48:37
| 283,215,238
| 3,201
| 351
|
Apache-2.0
| 2023-09-14T06:08:56
| 2020-07-28T13:07:26
|
TypeScript
|
UTF-8
|
Python
| false
| false
| 11,826
|
py
|
dataset.py
|
# Copyright 2020 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ==============================================================================
"""Base classes for LIT models."""
import glob
import inspect
import os
import random
from types import MappingProxyType # pylint: disable=g-importing-member
from typing import cast, Optional, Callable, Mapping, Sequence
from absl import logging
from lit_nlp.api import types
from lit_nlp.lib import serialize
from lit_nlp.lib import utils
JsonDict = types.JsonDict
IndexedInput = types.IndexedInput
ExampleId = types.ExampleId
Spec = types.Spec
LIT_FILE_EXTENSION = '.lit.jsonl'
LIT_SPEC_EXTENSION = '.spec'
class SliceWrapper(object):
"""Shim object to implement custom slicing via foo[a:b:c] rather than constructing a slice object explicitly."""
def __init__(self, handler):
self._handler = handler
def __getitem__(self, slice_obj):
return self._handler(slice_obj)
class Dataset(object):
"""Base class for LIT datasets."""
_spec: Spec = {}
_examples: list[JsonDict] = []
_description: Optional[str] = None
_base: Optional['Dataset'] = None
def __init__(self,
spec: Optional[Spec] = None,
examples: Optional[list[JsonDict]] = None,
description: Optional[str] = None,
base: Optional['Dataset'] = None):
"""Base class constructor.
This can derive from another dataset by passing the 'base' argument;
if so it will pre-populate with those fields, and override only those
specified individually as arguments.
Args:
spec: dataset spec
examples: data examples (datapoints)
description: optional human-readable description of this component
base: optional base dataset to derive from
"""
self._base = base
if self._base is not None:
self._examples = self._base.examples
self._spec = self._base.spec()
self._description = self._base.description()
# In case user child class requires the instance to convert examples
# this makes sure the user class is preserved. We cannot do this below
# as the default method is static and does not require instance.
self.bytes_from_lit_example = self._base.bytes_from_lit_example
self.lit_example_from_bytes = self._base.lit_example_from_bytes
# Override from direct arguments.
self._examples = examples if examples is not None else self._examples
self._spec = spec or self._spec
self._description = description or self._description
def description(self) -> str:
"""Return a human-readable description of this component.
Defaults to class docstring, but subclass may override this (or simply set
self._description) to be instance-dependent - for example, including the
path from which the data was loaded.
Returns:
(string) A human-readable description for display in the UI.
"""
return self._description or inspect.getdoc(self) or '' # pytype: disable=bad-return-type
def load(self, path: str):
"""Load and return additional previously-saved datapoints for this dataset.
Args:
path: The path to the persisted datapoint file.
Returns:
(Dataset) A dataset containing the loaded data.
"""
if self._base is not None:
return self._base.load(path)
pass
def save(self, examples: list[IndexedInput], path: str):
"""Save newly-created datapoints to disk in a dataset-specific format.
Subclasses should override this method if they wish to save new, persisted
datapoints in their own file format in addition to the LIT-specific format
they are already saved in.
Args:
examples: A list of datapoints to save.
path: The path to save the datapoints to.
Returns:
(string) The path to the saved data, or None if unimplemented.
"""
if self._base is not None:
return self._base.save(examples, path)
pass
def spec(self) -> Spec:
"""Return a spec describing dataset elements."""
return self._spec
@property
def examples(self) -> list[JsonDict]:
"""Return examples, in format described by spec."""
return self._examples
def __len__(self):
return len(self.examples)
@property
def slice(self):
"""Syntactic sugar, allows dataset.slice[i:j] to return a new Dataset."""
def _slicer(slice_obj):
return Dataset(examples=self.examples[slice_obj], base=self)
return SliceWrapper(_slicer)
def sample(self, n, seed=42):
"""Return a new dataset with a random subset of examples."""
rng = random.Random(seed)
if n < len(self.examples):
examples = rng.sample(self.examples, n)
else:
logging.warning(
'Requested sample %d is larger than dataset size %d; returning full dataset.',
n, len(self.examples))
examples = list(self.examples)
return Dataset(examples=examples, base=self)
def filter(self, predicate: Callable[[JsonDict], bool]):
selected_examples = list(filter(predicate, self.examples))
return Dataset(examples=selected_examples, base=self)
def shuffle(self, seed=42):
"""Return a new dataset with randomized example order."""
# random.shuffle will shuffle in-place; use sample to make a new list.
return self.sample(n=len(self), seed=seed)
def remap(self, field_map: dict[str, str]):
"""Return a copy of this dataset with some fields renamed."""
new_spec = utils.remap_dict(self.spec(), field_map)
new_examples = [utils.remap_dict(ex, field_map) for ex in self.examples]
return Dataset(new_spec, new_examples, base=self)
@staticmethod
def lit_example_from_bytes(input_bytes: bytes) -> Optional[JsonDict]:
"""Convert bytes representation to LIT example."""
return serialize.from_json(input_bytes.decode('utf-8'))
@staticmethod
def bytes_from_lit_example(lit_example: JsonDict) -> bytes:
"""Convert LIT example to bytes representation."""
return serialize.to_json(lit_example).encode('utf-8')
IdFnType = Callable[[types.Input], ExampleId]
class IndexedDataset(Dataset):
"""Dataset with additional indexing information."""
_index: dict[ExampleId, IndexedInput] = {}
def index_inputs(self, examples: list[types.Input]) -> list[IndexedInput]:
"""Create indexed versions of inputs."""
# pylint: disable=g-complex-comprehension not complex, just a line-too-long
return [
IndexedInput(
data=example,
id=self.id_fn(example),
meta=types.InputMetadata(added=None, parentId=None, source=None))
for example in examples
]
# pylint: enable=g-complex-comprehension
def __init__(self,
*args,
id_fn: Optional[IdFnType] = None,
indexed_examples: Optional[list[IndexedInput]] = None,
**kw):
super().__init__(*args, **kw)
assert id_fn is not None, 'id_fn must be specified.'
self.id_fn = id_fn
if indexed_examples:
self._indexed_examples = indexed_examples
self._examples = [ex['data'] for ex in indexed_examples]
else:
self._indexed_examples = self.index_inputs(self._examples)
self._index = {ex['id']: ex for ex in self._indexed_examples}
@property
def slice(self):
"""Syntactic sugar, allows .slice[i:j] to return a new IndexedDataset."""
def _slicer(slice_obj):
return IndexedDataset(
indexed_examples=self.indexed_examples[slice_obj],
id_fn=self.id_fn,
base=self)
return SliceWrapper(_slicer)
@classmethod
def index_all(cls, datasets: Mapping[str, Dataset], id_fn: IdFnType):
"""Convenience function to convert a dict of datasets."""
return {name: cls(base=ds, id_fn=id_fn) for name, ds in datasets.items()}
@property
def indexed_examples(self) -> Sequence[IndexedInput]:
return self._indexed_examples
@property
def index(self) -> Mapping[ExampleId, IndexedInput]:
"""Return a read-only view of the index."""
return MappingProxyType(self._index)
def save(self, examples: list[IndexedInput], path: str):
"""Save newly-created datapoints to disk.
Args:
examples: A list of datapoints to save.
path: The path to save the datapoints to.
Returns:
(string) The file path of the saved datapoints.
"""
# Attempt to save the datapoints using the base save method, which
# datasets can override. Then also save in the lit json format and save
# the spec as well.
if not path.endswith(LIT_FILE_EXTENSION):
self._base.save(examples, path)
path += LIT_FILE_EXTENSION
with open(path, 'w') as fd:
for ex in examples:
fd.write(serialize.to_json(ex) + '\n')
spec_path = path + LIT_SPEC_EXTENSION
with open(spec_path, 'w') as fd:
fd.write(serialize.to_json(self.spec()))
return path
def load(self, path: str):
"""Load and return additional previously-saved datapoints for this dataset.
Args:
path: The path to the persisted datapoint file.
Returns:
(IndexedDataset) A dataset containing the loaded data.
"""
if not path.endswith(LIT_FILE_EXTENSION):
# Try to load data using the base load method. If any data is
# returned, then use that. Otherwise try loading the lit json extension
# data format.
new_dataset = self._base.load(path)
if new_dataset is not None:
description = (f'{len(new_dataset)} examples from '
f'{path}\n{self._base.description()}')
return IndexedDataset(
base=new_dataset, id_fn=self.id_fn, description=description)
path += LIT_FILE_EXTENSION
with open(path, 'r') as fd:
examples = [
cast(IndexedInput, serialize.from_json(line))
for line in fd.readlines()
]
# Load the side-by-side spec if it exists on disk.
spec_path = path + LIT_SPEC_EXTENSION
if os.path.exists(spec_path):
with open(spec_path, 'r') as fd:
spec = serialize.from_json(fd.read())
description = (f'{len(examples)} examples from '
f'{path}\n{self._base.description()}')
return IndexedDataset(
base=self._base,
indexed_examples=examples,
spec=spec,
description=description,
id_fn=self.id_fn)
def __hash__(self):
return hash(tuple([ex['id'] for ex in self._indexed_examples]))
def __eq__(self, other):
self_ids = [ex['id'] for ex in self._indexed_examples]
other_ids = [ex['id'] for ex in other._indexed_examples]
return self_ids == other_ids
class NoneDataset(Dataset):
"""Empty dataset, with fields as the union of model specs."""
def __init__(self, models): # pylint: disable=super-init-not-called
self._examples = []
self._models = models
def spec(self):
combined_spec = {}
for _, model in self._models.items():
req_inputs = {k: v for (k, v) in model.spec().input.items() if v.required}
# Ensure that there are no conflicting spec keys.
assert not self.has_conflicting_keys(combined_spec, req_inputs)
combined_spec.update(req_inputs)
return combined_spec
def has_conflicting_keys(self, spec0: Spec, spec1: Spec):
for k, v in spec0.items():
if k in spec1 and spec1[k] != v:
return True
return False
|
89249ed03fa3322babeb8900957e6622fb9acfd8
|
753cd066a9bd26b6c37c8d53a86c7a9c659ec18c
|
/vision/vit/pytorch/checkpoint.py
|
07785d3383002cecba8799489e5d9d87233ff1f2
|
[
"MIT",
"CC-BY-NC-4.0",
"BSD-3-Clause",
"Apache-2.0",
"HPND"
] |
permissive
|
graphcore/examples
|
ac872015808ed2a913d4d7bf0d63202ce15ebbae
|
e2f834dd60e7939672c1795b4ac62e89ad0bca49
|
refs/heads/master
| 2023-08-05T02:08:12.341836
| 2023-07-27T11:13:10
| 2023-07-27T11:13:10
| 143,977,106
| 311
| 80
|
MIT
| 2023-09-11T16:42:56
| 2018-08-08T07:29:17
|
Python
|
UTF-8
|
Python
| false
| false
| 3,110
|
py
|
checkpoint.py
|
# Copyright (c) 2021 Graphcore Ltd. All rights reserved.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import os
import torch
from pathlib import Path
from log import logger
def _check_config_is_compatible(saved_config, config):
depth_mismatch = saved_config.num_hidden_layers != config.num_hidden_layers
breadth_mismatch = saved_config.hidden_size != config.hidden_size
attention_size_mismatch = saved_config.num_attention_heads != config.num_attention_heads
if depth_mismatch or breadth_mismatch or attention_size_mismatch:
raise RuntimeError(
"Checkpoint being loaded does not match model definition.\n"
f"Hidden layers: {'match' * int(depth_mismatch) + 'not match' * int(not depth_mismatch)}\n"
f"Hidden size: {'match' * int(breadth_mismatch) + 'not match' * int(not breadth_mismatch)}\n"
f"Attention layer size: {'match' * int(attention_size_mismatch) + 'not match' * int(not attention_size_mismatch)}\n"
)
def _load_checkpoint_from_file(file_path):
abs_path_ckpt = os.path.abspath(file_path)
# Return checkpoint if valid
if os.path.isfile(abs_path_ckpt):
try:
checkpoint = torch.load(abs_path_ckpt)
return checkpoint
except Exception as e:
logger.error(f"Failed with exception {e}.")
else:
raise RuntimeError("Please specify a PyTorch checkpoint file.")
def restore_checkpoint(config, val=False):
model_path = Path(config.pretrained_checkpoint) / f"pytorch_model.bin"
model_state_dict = _load_checkpoint_from_file(model_path)
if val:
return model_state_dict
training_state_path = Path(config.pretrained_checkpoint) / f"training_state.pt"
training_state = _load_checkpoint_from_file(training_state_path)
_check_config_is_compatible(training_state["config"], config)
return model_state_dict, training_state
def save_checkpoint(config, model, optimizer, step, metrics=None):
if config.checkpoint_output_dir:
path = Path(config.checkpoint_output_dir) / f"step_{step}"
os.makedirs(path, exist_ok=True)
logger.info(f"Saving checkpoint for step {step} to: {path}\n")
if hasattr(model, "save_pretrained"):
model.save_pretrained(path)
else:
torch.save(model.state_dict(), path / f"pytorch_model.bin")
optimizer_state = optimizer.state_dict()
torch.save(
{"step": step, "optimizer_state_dict": optimizer_state, "metrics": metrics, "config": config},
os.path.join(path, "training_state.pt"),
)
|
605b7809c3c0d610dd45a163d2ad54393ed2a8a5
|
017090be7ab186cb6b47f49e1066ac5cfec3a542
|
/src/neptune/types/namespace.py
|
ede2023558db49560393cb749eb4b193960edada
|
[
"Apache-2.0"
] |
permissive
|
neptune-ai/neptune-client
|
9a79f9d93c84b3a20114e6e49a80652930399ece
|
9b697ce548634c30dbc5881d4a0b223c8987515d
|
refs/heads/master
| 2023-08-18T01:48:22.634432
| 2023-08-17T11:55:57
| 2023-08-17T11:55:57
| 170,117,229
| 408
| 55
|
Apache-2.0
| 2023-09-13T12:51:03
| 2019-02-11T11:25:57
|
Python
|
UTF-8
|
Python
| false
| false
| 1,727
|
py
|
namespace.py
|
#
# Copyright (c) 2022, Neptune Labs Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
__all__ = ["Namespace"]
from dataclasses import dataclass
from typing import (
TYPE_CHECKING,
TypeVar,
)
from neptune.internal.utils.logger import logger
from neptune.internal.utils.paths import parse_path
from neptune.types.value import Value
if TYPE_CHECKING:
from neptune.types.value_visitor import ValueVisitor
Ret = TypeVar("Ret")
@dataclass
class Namespace(Value):
value: dict
def __init__(self, value):
self.value = value
empty_keys = [k for k in self.value.keys() if not parse_path(k)]
if empty_keys:
all_keys = ", ".join(['"' + k + '"' for k in empty_keys])
logger.warning(
f"Key(s) {all_keys} can't be used in Namespaces and dicts stored in Neptune. Please use non-empty "
f"keys instead. The value(s) will be dropped.",
)
self.value = value.copy()
[self.value.pop(key) for key in empty_keys]
def accept(self, visitor: "ValueVisitor[Ret]") -> Ret:
return visitor.visit_namespace(self)
def __str__(self):
return "Namespace({})".format(str(self.value))
|
fc8cf1feb3cdd825449c39520fa1f0013d37357f
|
9907672fcd81ab73ac63b2a83422a82bf31eadde
|
/atcoder/tyama_atcoderAGC015C.py
|
bfd411ad330c0c35470ecbe9790c8b461bbceabc
|
[
"0BSD"
] |
permissive
|
cielavenir/procon
|
bbe1974b9bddb51b76d58722a0686a5b477c4456
|
746e1a91f574f20647e8aaaac0d9e6173f741176
|
refs/heads/master
| 2023-06-21T23:11:24.562546
| 2023-06-11T13:15:15
| 2023-06-11T13:15:15
| 7,557,464
| 137
| 136
| null | 2020-10-20T09:35:52
| 2013-01-11T09:40:26
|
C++
|
UTF-8
|
Python
| false
| false
| 536
|
py
|
tyama_atcoderAGC015C.py
|
#!/usr/bin/python
f=lambda s,h,w,a,q:s[h+1].__setitem__(w+1,s[h+1][w]+s[h][w+1]-s[h][w]+a[h][w]*q)
g=lambda s,y1,x1,y2,x2:s[y2][x2]-s[y2][x1-1]-s[y1-1][x2]+s[y1-1][x1-1]
H,W,N=map(int,raw_input().split())
a=[map(int,raw_input())for _ in[0]*H]
s,s1,s2=[[[0]*(W+1)for _ in[0]*-~H]for _ in[0]*3]
for h in range(H):
for w in range(W):
f(s,h,w,a,1)
f(s1,h,w,a,w+1<W and a[h][w+1])
f(s2,h,w,a,h+1<H and a[h+1][w])
for _ in[0]*N:
y1,x1,y2,x2=map(int,raw_input().split())
print g(s,y1,x1,y2,x2)-g(s1,y1,x1,y2,x2-1)-g(s2,y1,x1,y2-1,x2)
|
0c819355d7e8581523fdae30905abe70c1e43513
|
f6aac61a48a87743be9c40fecdc24344bae4d263
|
/scripts/00z/asos_high.py
|
a41aefe79fa14622e0694a325fc45c26ac516a27
|
[
"MIT"
] |
permissive
|
akrherz/iem
|
8714d99b371c8818f7cdde73dd24639e9fc7d42b
|
178015584b7fb5b585f65be6013eaf16fb6db0c7
|
refs/heads/main
| 2023-08-19T02:58:24.507782
| 2023-08-18T12:08:31
| 2023-08-18T12:08:31
| 4,253,774
| 118
| 74
|
MIT
| 2023-09-14T18:28:41
| 2012-05-07T20:32:59
|
Python
|
UTF-8
|
Python
| false
| false
| 2,462
|
py
|
asos_high.py
|
"""Generate a map of the 00z high temperature.
run from RUN_0Z.sh
"""
import datetime
import pandas as pd
from pyiem.plot import MapPlot
from pyiem.util import get_sqlalchemy_conn, logger, utc
from sqlalchemy import text
LOG = logger()
def main():
"""Go Main Go"""
now = utc().replace(hour=0, minute=0, second=0, microsecond=0)
sts = now - datetime.timedelta(hours=12)
with get_sqlalchemy_conn("iem") as conn:
df = pd.read_sql(
text(
"""
WITH highs as (
SELECT c.iemid,
max(tmpf) as calc_high,
max(max_tmpf_6hr) as reported_high
from current_log c JOIN stations s
ON (s.iemid = c.iemid)
WHERE valid >= :sts and valid < :ets
and s.network ~* 'ASOS'
and s.country = 'US' and s.state not in ('HI', 'AK') GROUP by c.iemid
)
select t.id, t.state, ST_x(t.geom) as lon, ST_y(t.geom) as lat,
greatest(l.calc_high, l.reported_high) as high from
highs l JOIN stations t on (t.iemid = l.iemid)
"""
),
conn,
params={"sts": sts, "ets": now},
index_col="id",
)
df = df[df["high"].notnull()]
LOG.info("found %s observations for %s", len(df.index), now)
for sector in ["iowa", "midwest", "conus"]:
mp = MapPlot(
sector=sector if len(sector) > 2 else "state",
state=sector if len(sector) == 2 else "IA",
title=f"{sts:%-d %b %Y} ASOS 12-00 UTC High Temperature",
subtitle=("includes available 18z and 0z 6-hr maxes"),
axisbg="white",
)
if sector == "iowa" or len(sector) == 2:
df2 = df[df["state"] == ("IA" if len(sector) > 2 else sector)]
labels = df2.index.values
mp.drawcounties()
size = 14
else:
df2 = df
labels = None
size = 10
mp.plot_values(
df2["lon"].values,
df2["lat"].values,
df2["high"].values,
fmt="%.0f",
labels=labels,
labelbuffer=1,
textsize=size,
)
pqstr = (
f"plot ac {sts:%Y%m%d%H%M} "
f"summary/{sector.lower()}_asos_0z_high.png "
f"{sector.lower()}_asos_0z_high.png png"
)
LOG.info(pqstr)
mp.postprocess(pqstr=pqstr)
mp.close()
if __name__ == "__main__":
main()
|
7ced2817d30992625e6a869131f7dae5428947da
|
881cef6f3e6cbea821029bf8675a1689fdf2501f
|
/test/test_amd64.py
|
837392d5801017be714b356c83c6c69ec03bb2ae
|
[
"BSD-3-Clause"
] |
permissive
|
feliam/pysymemu
|
d8173f28380a152908c32719ec318107383fe99f
|
ad02e52122099d537372eb4d11fd5024b8a3857f
|
refs/heads/master
| 2022-07-03T08:44:26.019205
| 2021-08-28T02:20:56
| 2021-08-28T02:20:56
| 13,131,159
| 282
| 59
|
BSD-3-Clause
| 2021-08-28T02:20:57
| 2013-09-26T18:46:01
|
Python
|
UTF-8
|
Python
| false
| false
| 6,284,585
|
py
|
test_amd64.py
|
from cpu import Cpu
import unittest
class CPUTest(unittest.TestCase):
class ROOperand(object):
''' Mocking class for operand ronly '''
def __init__(self, size, value):
self.size = size
self.value = value
def read(self):
return self.value & ((1<<self.size)-1)
class RWOperand(ROOperand):
''' Mocking class for operand rw '''
def write(self, value):
self.value = value & ((1<<self.size)-1)
return self.value
class Mem(object):
''' Mocking class for memory '''
def __init__(self, mem):
self.mem = dict(mem)
def getchar(self, addr):
#print "getchar",hex(addr), "%02x"%ord(self.mem[addr])
return self.mem[addr]
def putchar(self, addr, char):
#print "putchar",hex(addr), "%02x"%ord(char)
self.mem[addr]=char
def isExecutable(self,addr):
return True
def testADC_1(self):
''' Instruction ADC EDX, -0x1 '''
test = {'mnemonic': 'ADC', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336752L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'text': '\x83\xd2\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'disassembly': 'ADC EDX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADC_2(self):
''' Instruction ADC EDX, -0x1 '''
test = {'mnemonic': 'ADC', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336752L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'text': '\x83\xd2\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'disassembly': 'ADC EDX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADC_3(self):
''' Instruction ADC EDX, -0x1 '''
test = {'mnemonic': 'ADC', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336752L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'text': '\x83\xd2\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'disassembly': 'ADC EDX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADC_4(self):
''' Instruction ADC EDX, -0x1 '''
test = {'mnemonic': 'ADC', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336752L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'text': '\x83\xd2\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'disassembly': 'ADC EDX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADC_5(self):
''' Instruction ADC EDX, -0x1 '''
test = {'mnemonic': 'ADC', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336752L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'text': '\x83\xd2\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'disassembly': 'ADC EDX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADC_6(self):
''' Instruction ADC EDX, -0x1 '''
test = {'mnemonic': 'ADC', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336752L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'text': '\x83\xd2\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {4336752L: '\x83', 4336753L: '\xd2', 4336754L: '\xff'}}, 'disassembly': 'ADC EDX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_1(self):
''' Instruction ADD R8, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R8': 1L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392706L, 'RBP': 7049504L}, 'memory': {4392706L: 'I', 4392707L: '\x83', 4392708L: '\xc0', 4392709L: '\x01'}}, 'text': 'I\x83\xc0\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R8': 2L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392710L, 'RBP': 7049504L}, 'memory': {4392706L: 'I', 4392707L: '\x83', 4392708L: '\xc0', 4392709L: '\x01'}}, 'disassembly': 'ADD R8, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_10(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346832L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488350544L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346840L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322534L, 'RBP': 140737488350544L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_100(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052056L, 'RSP': 140737488345712L, 'RDX': 720L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052056L, 'RSP': 140737488345712L, 'RDX': 736L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_101(self):
''' Instruction ADD RDI, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346512L, 'RAX': 140737488347397L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195971L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'text': 'H\x83\xc7\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346520L, 'RAX': 140737488347397L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'disassembly': 'ADD RDI, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_11(self):
''' Instruction ADD DWORD [RBP-0x5ac], 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 2147483636L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4338847L, 'RBP': 140737488345936L}, 'memory': {140737488344512: '\x15', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 4338853L: '\x01', 4338852L: '\xff', 4338847L: '\x83', 4338848L: '\x85', 4338849L: 'T', 4338850L: '\xfa', 4338851L: '\xff', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\n', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00'}}, 'text': '\x83\x85T\xfa\xff\xff\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 2147483636L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4338854L, 'RBP': 140737488345936L}, 'memory': {140737488344512: '\x15', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 4338853L: '\x01', 4338852L: '\xff', 4338847L: '\x83', 4338848L: '\x85', 4338849L: 'T', 4338850L: '\xfa', 4338851L: '\xff', 140737488344484: '\x01', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\n', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00'}}, 'disassembly': 'ADD DWORD [RBP-0x5ac], 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_12(self):
''' Instruction ADD R8D, ECX '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 32L, 'RDX': 8L, 'RBP': 1L, 'RDI': 6L, 'RSI': 7065696L, 'R8D': 10L, 'RIP': 4300198L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 132775L, 'ECX': 32L}, 'memory': {4300200L: '\xc8', 4300198L: 'A', 4300199L: '\x01'}}, 'text': 'A\x01\xc8', 'pos': {'registers': {'RCX': 32L, 'RDX': 8L, 'RBP': 1L, 'RDI': 6L, 'RSI': 7065696L, 'R8D': 42L, 'RIP': 4300201L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 132775L, 'ECX': 32L}, 'memory': {4300200L: '\xc8', 4300198L: 'A', 4300199L: '\x01'}}, 'disassembly': 'ADD R8D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_13(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346592L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488347906L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346600L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488347906L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_14(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346728L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488350196L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346736L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488350196L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_15(self):
''' Instruction ADD RDI, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347232L, 'RAX': 18446744073709551614L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296984L, 'RBP': 0L}, 'memory': {4296984L: 'H', 4296985L: '\x83', 4296986L: '\xc7', 4296987L: '\x10'}}, 'text': 'H\x83\xc7\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347248L, 'RAX': 18446744073709551614L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296988L, 'RBP': 0L}, 'memory': {4296984L: 'H', 4296985L: '\x83', 4296986L: '\xc7', 4296987L: '\x10'}}, 'disassembly': 'ADD RDI, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_16(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346688L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488349988L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346696L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322534L, 'RBP': 140737488349988L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_17(self):
''' Instruction ADD RAX, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 52L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 140737354125650L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392697L, 'RBP': 7049504L}, 'memory': {4392697L: 'H', 4392698L: '\x83', 4392699L: '\xc0', 4392700L: '\x01'}}, 'text': 'H\x83\xc0\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 52L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 140737354125651L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392697L: 'H', 4392698L: '\x83', 4392699L: '\xc0', 4392700L: '\x01'}}, 'disassembly': 'ADD RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_18(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346840L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350562L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346848L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350562L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_19(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053160L, 'RSP': 140737488345712L, 'RDX': 1824L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053160L, 'RSP': 140737488345712L, 'RDX': 1840L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_2(self):
''' Instruction ADD R13, R14 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 8L, 'R14': 0L, 'RSI': 4792480L, 'RIP': 4320753L, 'RSP': 140737488345888L, 'RFLAGS': 659L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'text': 'M\x01\xf5', 'pos': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 8L, 'R14': 0L, 'RSI': 4792480L, 'RIP': 4320756L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'disassembly': 'ADD R13, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_20(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346936L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488351032L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346944L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322534L, 'RBP': 140737488351032L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_21(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346864L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488350642L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346872L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488350642L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_22(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346520L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488347630L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346528L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322534L, 'RBP': 140737488347630L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_23(self):
''' Instruction ADD RDI, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 4297216L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297220L, 'RBP': 0L}, 'memory': {4297220L: 'H', 4297221L: '\x83', 4297222L: '\xc7', 4297223L: '\x10'}}, 'text': 'H\x83\xc7\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 4297216L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297224L, 'RBP': 0L}, 'memory': {4297220L: 'H', 4297221L: '\x83', 4297222L: '\xc7', 4297223L: '\x10'}}, 'disassembly': 'ADD RDI, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_24(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346776L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350405L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346784L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322534L, 'RBP': 140737488350405L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_25(self):
''' Instruction ADD EDX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'EDX': 16L, 'RAX': 140737488346000L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338816L, 'RBP': 140737488345936L}, 'memory': {4338816L: '\x83', 4338817L: '\xc2', 4338818L: '\x08'}}, 'text': '\x83\xc2\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'EDX': 24L, 'RAX': 140737488346000L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338819L, 'RBP': 140737488345936L}, 'memory': {4338816L: '\x83', 4338817L: '\xc2', 4338818L: '\x08'}}, 'disassembly': 'ADD EDX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_26(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RBX': 140737488346808L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488350473L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 29L, 'RSI': 1L, 'RBX': 140737488346816L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488350473L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_27(self):
''' Instruction ADD RSP, 0x18 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 7065216L, 'RSP': 140737488346160L, 'RDX': 7065176L, 'RIP': 4197312L, 'RBP': 10L}, 'memory': {4197312L: 'H', 4197313L: '\x83', 4197314L: '\xc4', 4197315L: '\x18'}}, 'text': 'H\x83\xc4\x18', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 7065216L, 'RSP': 140737488346184L, 'RDX': 7065176L, 'RIP': 4197316L, 'RBP': 10L}, 'memory': {4197312L: 'H', 4197313L: '\x83', 4197314L: '\xc4', 4197315L: '\x18'}}, 'disassembly': 'ADD RSP, 0x18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_28(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346864L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350642L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346872L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350642L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_29(self):
''' Instruction ADD R12D, R8D '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 4783050L, 'RDX': 30L, 'RBP': 140737488345936L, 'RDI': 140737354125693L, 'RSI': 140737354125695L, 'R8D': 2L, 'RIP': 4338854L, 'R12D': 30L, 'RSP': 140737488344256L, 'RFLAGS': 514L, 'RAX': 2147483617L}, 'memory': {4338856L: '\xc4', 4338854L: 'E', 4338855L: '\x01'}}, 'text': 'E\x01\xc4', 'pos': {'registers': {'RCX': 4783050L, 'RDX': 30L, 'RBP': 140737488345936L, 'RDI': 140737354125693L, 'RSI': 140737354125695L, 'R8D': 2L, 'RIP': 4338857L, 'R12D': 32L, 'RSP': 140737488344256L, 'RFLAGS': 530L, 'RAX': 2147483617L}, 'memory': {4338856L: '\xc4', 4338854L: 'E', 4338855L: '\x01'}}, 'disassembly': 'ADD R12D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_3(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346584L, 'RDI': 7059520L, 'RAX': 140737488347888L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346592L, 'RDI': 7059520L, 'RAX': 140737488347888L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212893L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_30(self):
''' Instruction ADD RAX, [R13+0x10] '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'R13': 140737488345952L, 'RAX': 8L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338812L, 'RBP': 140737488345936L}, 'memory': {140737488345984: '\xe0', 140737488345985: '\x97', 140737488345986: 'k', 140737488345987: '\x00', 140737488345988: '\x00', 140737488345989: '\x00', 140737488345990: '\x00', 140737488345991: '\x00', 140737488345992: '\x15', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '9', 140737488346001: '\xfb', 140737488346002: 'H', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\x04', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: '\x0b', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\x0f', 140737488346025: '\x00', 140737488346026: '\x00', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488345982: '\x00', 140737488345983: '\x00', 140737488345980: '\x00', 140737488345981: '\x00', 140737488345968: '\x80', 140737488345969: '\xdb', 140737488345970: '\xff', 140737488345971: '\xff', 140737488345972: '\xff', 140737488345973: '\x7f', 140737488345974: '\x00', 140737488345975: '\x00', 140737488345976: '\xd0', 140737488345977: '\xf1', 140737488345978: 'k', 140737488345979: '\x00', 4338812L: 'I', 4338813L: '\x03', 4338814L: 'E', 4338815L: '\x10'}}, 'text': 'I\x03E\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 140737488345992L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338816L, 'RBP': 140737488345936L}, 'memory': {140737488345984: '\xe0', 140737488345985: '\x97', 140737488345986: 'k', 140737488345987: '\x00', 140737488345988: '\x00', 140737488345989: '\x00', 140737488345990: '\x00', 140737488345991: '\x00', 140737488345992: '\x15', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '9', 140737488346001: '\xfb', 140737488346002: 'H', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\x04', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: '\x0b', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\x0f', 140737488346025: '\x00', 140737488346026: '\x00', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488345982: '\x00', 140737488345983: '\x00', 140737488345980: '\x00', 140737488345981: '\x00', 140737488345968: '\x80', 140737488345969: '\xdb', 140737488345970: '\xff', 140737488345971: '\xff', 140737488345972: '\xff', 140737488345973: '\x7f', 140737488345974: '\x00', 140737488345975: '\x00', 140737488345976: '\xd0', 140737488345977: '\xf1', 140737488345978: 'k', 140737488345979: '\x00', 4338812L: 'I', 4338813L: '\x03', 4338814L: 'E', 4338815L: '\x10'}}, 'disassembly': 'ADD RAX, [R13+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_31(self):
''' Instruction ADD RSP, 0x38 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 52L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'RAX': 1L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392779L, 'RBP': 140737488345936L}, 'memory': {4392779L: 'H', 4392780L: '\x83', 4392781L: '\xc4', 4392782L: '8'}}, 'text': 'H\x83\xc48', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 52L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'RAX': 1L, 'RSP': 140737488344248L, 'RDX': 140737488345640L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {4392779L: 'H', 4392780L: '\x83', 4392781L: '\xc4', 4392782L: '8'}}, 'disassembly': 'ADD RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_32(self):
''' Instruction ADD R12D, R8D '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 4782904L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 140737354125329L, 'RSI': 140737354125330L, 'R8D': 1L, 'RIP': 4338854L, 'R12D': 17L, 'RSP': 140737488344256L, 'RFLAGS': 514L, 'RAX': 2147483630L}, 'memory': {4338856L: '\xc4', 4338854L: 'E', 4338855L: '\x01'}}, 'text': 'E\x01\xc4', 'pos': {'registers': {'RCX': 4782904L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 140737354125329L, 'RSI': 140737354125330L, 'R8D': 1L, 'RIP': 4338857L, 'R12D': 18L, 'RSP': 140737488344256L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4338856L: '\xc4', 4338854L: 'E', 4338855L: '\x01'}}, 'disassembly': 'ADD R12D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_33(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053064L, 'RSP': 140737488345712L, 'RDX': 1728L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053064L, 'RSP': 140737488345712L, 'RDX': 1744L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_34(self):
''' Instruction ADD R13, R14 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 51L, 'R14': 35L, 'RSI': 4792824L, 'RIP': 4320753L, 'RSP': 140737488345888L, 'RFLAGS': 647L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'text': 'M\x01\xf5', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 86L, 'R14': 35L, 'RSI': 4792824L, 'RIP': 4320756L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'disassembly': 'ADD R13, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_35(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052392L, 'RSP': 140737488345712L, 'RDX': 1056L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052392L, 'RSP': 140737488345712L, 'RDX': 1072L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_36(self):
''' Instruction ADD RAX, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737354125688L, 'RSP': 140737488344192L, 'RDX': 4783044L, 'RIP': 4392697L, 'RBP': 7049504L}, 'memory': {4392697L: 'H', 4392698L: '\x83', 4392699L: '\xc0', 4392700L: '\x01'}}, 'text': 'H\x83\xc0\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737354125689L, 'RSP': 140737488344192L, 'RDX': 4783044L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392697L: 'H', 4392698L: '\x83', 4392699L: '\xc0', 4392700L: '\x01'}}, 'disassembly': 'ADD RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_37(self):
''' Instruction ADD RDX, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 114L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737354125670L, 'RSP': 140737488344192L, 'RDX': 4783024L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392691L: 'H', 4392692L: '\x83', 4392693L: '\xc2', 4392694L: '\x01'}}, 'text': 'H\x83\xc2\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 114L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737354125670L, 'RSP': 140737488344192L, 'RDX': 4783025L, 'RIP': 4392695L, 'RBP': 7049504L}, 'memory': {4392691L: 'H', 4392692L: '\x83', 4392693L: '\xc2', 4392694L: '\x01'}}, 'disassembly': 'ADD RDX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_38(self):
''' Instruction ADD RSP, 0x38 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 51L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 1L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392779L, 'RBP': 140737488345936L}, 'memory': {4392779L: 'H', 4392780L: '\x83', 4392781L: '\xc4', 4392782L: '8'}}, 'text': 'H\x83\xc48', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 51L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 1L, 'RSP': 140737488344248L, 'RDX': 140737488345640L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {4392779L: 'H', 4392780L: '\x83', 4392781L: '\xc4', 4392782L: '8'}}, 'disassembly': 'ADD RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_39(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346904L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350843L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346912L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322534L, 'RBP': 140737488350843L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_4(self):
''' Instruction ADD RAX, RDX '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239744L: '\x01', 4239745L: '\xd0', 4239743L: 'H'}}, 'text': 'H\x01\xd0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239746L, 'RBP': 4782912L}, 'memory': {4239744L: '\x01', 4239745L: '\xd0', 4239743L: 'H'}}, 'disassembly': 'ADD RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_40(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346872L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350653L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346880L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350653L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_41(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 29L, 'RSI': 1L, 'RBX': 140737488346512L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488347397L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RBX': 140737488346520L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488347397L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_42(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052504L, 'RSP': 140737488345712L, 'RDX': 1168L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052504L, 'RSP': 140737488345712L, 'RDX': 1184L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_43(self):
''' Instruction ADD RSP, 0x30 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346080L, 'RDX': 7058304L, 'RIP': 4704481L, 'RBP': 7035176L}, 'memory': {4704481L: 'H', 4704482L: '\x83', 4704483L: '\xc4', 4704484L: '0'}}, 'text': 'H\x83\xc40', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4704485L, 'RBP': 7035176L}, 'memory': {4704481L: 'H', 4704482L: '\x83', 4704483L: '\xc4', 4704484L: '0'}}, 'disassembly': 'ADD RSP, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_44(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RBX': 140737488346848L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322530L, 'RBP': 140737488350606L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RBX': 140737488346856L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322534L, 'RBP': 140737488350606L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_45(self):
''' Instruction ADD RDI, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346632L, 'RAX': 140737488349535L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195971L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'text': 'H\x83\xc7\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346640L, 'RAX': 140737488349535L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'disassembly': 'ADD RDI, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_46(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052104L, 'RSP': 140737488345712L, 'RDX': 768L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052104L, 'RSP': 140737488345712L, 'RDX': 784L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_47(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346808L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488350473L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346816L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322534L, 'RBP': 140737488350473L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_48(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346696L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350013L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346704L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350013L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_49(self):
''' Instruction ADD RDX, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'RAX': 140737354125649L, 'RSP': 140737488344192L, 'RDX': 4782994L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392691L: 'H', 4392692L: '\x83', 4392693L: '\xc2', 4392694L: '\x01'}}, 'text': 'H\x83\xc2\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'RAX': 140737354125649L, 'RSP': 140737488344192L, 'RDX': 4782995L, 'RIP': 4392695L, 'RBP': 7049504L}, 'memory': {4392691L: 'H', 4392692L: '\x83', 4392693L: '\xc2', 4392694L: '\x01'}}, 'disassembly': 'ADD RDX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_5(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052120L, 'RSP': 140737488345712L, 'RDX': 784L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052120L, 'RSP': 140737488345712L, 'RDX': 800L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_50(self):
''' Instruction ADD R12, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 78L, 'RAX': 140737354125488L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199273L, 'RBP': 4782912L}, 'memory': {4199273L: 'I', 4199274L: '\x83', 4199275L: '\xc4', 4199276L: '\x01'}}, 'text': 'I\x83\xc4\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125488L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199277L, 'RBP': 4782912L}, 'memory': {4199273L: 'I', 4199274L: '\x83', 4199275L: '\xc4', 4199276L: '\x01'}}, 'disassembly': 'ADD R12, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_51(self):
''' Instruction ADD RDI, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346560L, 'RAX': 140737488347766L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195971L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'text': 'H\x83\xc7\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346568L, 'RAX': 140737488347766L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'disassembly': 'ADD RDI, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_52(self):
''' Instruction ADD R13, R14 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 2L, 'R14': 0L, 'RSI': 4792432L, 'RIP': 4320753L, 'RSP': 140737488345888L, 'RFLAGS': 659L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'text': 'M\x01\xf5', 'pos': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 2L, 'R14': 0L, 'RSI': 4792432L, 'RIP': 4320756L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'disassembly': 'ADD R13, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_53(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052696L, 'RSP': 140737488345712L, 'RDX': 1360L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052696L, 'RSP': 140737488345712L, 'RDX': 1376L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_54(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346528L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488347664L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346536L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322534L, 'RBP': 140737488347664L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_55(self):
''' Instruction ADD RDI, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 7065424L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297027L, 'RBP': 0L}, 'memory': {4297027L: 'H', 4297028L: '\x83', 4297029L: '\xc7', 4297030L: '\x10'}}, 'text': 'H\x83\xc7\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 7065424L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297031L, 'RBP': 0L}, 'memory': {4297027L: 'H', 4297028L: '\x83', 4297029L: '\xc7', 4297030L: '\x10'}}, 'disassembly': 'ADD RDI, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_56(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052280L, 'RSP': 140737488345712L, 'RDX': 944L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052280L, 'RSP': 140737488345712L, 'RDX': 960L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_57(self):
''' Instruction ADD RSP, 0x48 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4294967040L, 'RSP': 140737488343888L, 'RDX': 18446744073709551568L, 'RIP': 4673681L, 'RBP': 18446744073709551568L}, 'memory': {4673681L: 'H', 4673682L: '\x83', 4673683L: '\xc4', 4673684L: 'H'}}, 'text': 'H\x83\xc4H', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4294967040L, 'RSP': 140737488343960L, 'RDX': 18446744073709551568L, 'RIP': 4673685L, 'RBP': 18446744073709551568L}, 'memory': {4673681L: 'H', 4673682L: '\x83', 4673683L: '\xc4', 4673684L: 'H'}}, 'disassembly': 'ADD RSP, 0x48', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_58(self):
''' Instruction ADD R10, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 37L, 'R10': 4782898L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4336207L, 'RBP': 140737488345936L}, 'memory': {4336208L: '\x83', 4336209L: '\xc2', 4336210L: '\x01', 4336207L: 'I'}}, 'text': 'I\x83\xc2\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 37L, 'R10': 4782899L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4336211L, 'RBP': 140737488345936L}, 'memory': {4336208L: '\x83', 4336209L: '\xc2', 4336210L: '\x01', 4336207L: 'I'}}, 'disassembly': 'ADD R10, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_59(self):
''' Instruction ADD RBP, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4716400L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197574L, 'RBP': 2L}, 'memory': {4197576L: '\xc5', 4197577L: '\x01', 4197574L: 'H', 4197575L: '\x83'}}, 'text': 'H\x83\xc5\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4716400L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197578L, 'RBP': 3L}, 'memory': {4197576L: '\xc5', 4197577L: '\x01', 4197574L: 'H', 4197575L: '\x83'}}, 'disassembly': 'ADD RBP, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_6(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346800L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350464L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346808L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350464L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_60(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346680L, 'RDI': 7059520L, 'RAX': 140737488349968L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346688L, 'RDI': 7059520L, 'RAX': 140737488349968L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212893L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_61(self):
''' Instruction ADD RAX, [R13+0x10] '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'R13': 140737488345952L, 'RAX': 32L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338812L, 'RBP': 140737488345936L}, 'memory': {140737488345984: '\xe0', 140737488345985: '\x97', 140737488345986: 'k', 140737488345987: '\x00', 140737488345988: '\x00', 140737488345989: '\x00', 140737488345990: '\x00', 140737488345991: '\x00', 140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488345982: '\x00', 140737488345983: '\x00', 140737488345980: '\x00', 140737488345981: '\x00', 140737488345968: '\x80', 140737488345969: '\xdb', 140737488345970: '\xff', 140737488345971: '\xff', 140737488345972: '\xff', 140737488345973: '\x7f', 140737488345974: '\x00', 140737488345975: '\x00', 140737488345976: '\xd0', 140737488345977: '\xf1', 140737488345978: 'k', 140737488345979: '\x00', 4338812L: 'I', 4338813L: '\x03', 4338814L: 'E', 4338815L: '\x10'}}, 'text': 'I\x03E\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737488346016L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338816L, 'RBP': 140737488345936L}, 'memory': {140737488345984: '\xe0', 140737488345985: '\x97', 140737488345986: 'k', 140737488345987: '\x00', 140737488345988: '\x00', 140737488345989: '\x00', 140737488345990: '\x00', 140737488345991: '\x00', 140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488345982: '\x00', 140737488345983: '\x00', 140737488345980: '\x00', 140737488345981: '\x00', 140737488345968: '\x80', 140737488345969: '\xdb', 140737488345970: '\xff', 140737488345971: '\xff', 140737488345972: '\xff', 140737488345973: '\x7f', 140737488345974: '\x00', 140737488345975: '\x00', 140737488345976: '\xd0', 140737488345977: '\xf1', 140737488345978: 'k', 140737488345979: '\x00', 4338812L: 'I', 4338813L: '\x03', 4338814L: 'E', 4338815L: '\x10'}}, 'disassembly': 'ADD RAX, [R13+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_62(self):
''' Instruction ADD R13, R14 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 51L, 'R14': 35L, 'RSI': 4792824L, 'RIP': 4320753L, 'RSP': 140737488345888L, 'RFLAGS': 647L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'text': 'M\x01\xf5', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 86L, 'R14': 35L, 'RSI': 4792824L, 'RIP': 4320756L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'disassembly': 'ADD R13, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_63(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 608L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 624L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_64(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346784L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488350429L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346792L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322534L, 'RBP': 140737488350429L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_65(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346888L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488350808L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346896L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322534L, 'RBP': 140737488350808L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_66(self):
''' Instruction ADD R13, R14 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'R14': 0L, 'RSI': 4792688L, 'RIP': 4320753L, 'RSP': 140737488345888L, 'RFLAGS': 663L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'text': 'M\x01\xf5', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'R14': 0L, 'RSI': 4792688L, 'RIP': 4320756L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320753L: 'M', 4320754L: '\x01', 4320755L: '\xf5'}}, 'disassembly': 'ADD R13, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_67(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346656L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488349619L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346664L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488349619L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_68(self):
''' Instruction ADD R14, R13 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 4702111234474983745L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125852L, 'R13': 0L, 'R14': 0L, 'RSI': 4782990L, 'RIP': 4392731L, 'RSP': 140737488346064L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4392731L: 'M', 4392732L: '\x01', 4392733L: '\xee'}}, 'text': 'M\x01\xee', 'pos': {'registers': {'RCX': 4702111234474983745L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125852L, 'R13': 0L, 'R14': 0L, 'RSI': 4782990L, 'RIP': 4392734L, 'RSP': 140737488346064L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4392731L: 'M', 4392732L: '\x01', 4392733L: '\xee'}}, 'disassembly': 'ADD R14, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_69(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346760L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350381L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346768L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350381L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_7(self):
''' Instruction ADD EDI, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 3L, 'RSI': 4194304L, 'RAX': 4L, 'RDI': 3L, 'EDI': 3L, 'RSP': 140737488346144L, 'RDX': 2L, 'RIP': 4284949L, 'RBP': 32768L}, 'memory': {4284949L: '\x83', 4284950L: '\xc7', 4284951L: '\x01'}}, 'text': '\x83\xc7\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 4194304L, 'RAX': 4L, 'RDI': 4L, 'EDI': 4L, 'RSP': 140737488346144L, 'RDX': 2L, 'RIP': 4284952L, 'RBP': 32768L}, 'memory': {4284949L: '\x83', 4284950L: '\xc7', 4284951L: '\x01'}}, 'disassembly': 'ADD EDI, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_70(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346856L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350621L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346864L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350621L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_71(self):
''' Instruction ADD RSP, 0x38 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392779L, 'RBP': 140737488345936L}, 'memory': {4392779L: 'H', 4392780L: '\x83', 4392781L: '\xc4', 4392782L: '8'}}, 'text': 'H\x83\xc48', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 4783046L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {4392779L: 'H', 4392780L: '\x83', 4392781L: '\xc4', 4392782L: '8'}}, 'disassembly': 'ADD RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_72(self):
''' Instruction ADD RDX, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 49L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 140737354125322L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392691L: 'H', 4392692L: '\x83', 4392693L: '\xc2', 4392694L: '\x01'}}, 'text': 'H\x83\xc2\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 49L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 140737354125322L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392695L, 'RBP': 7049504L}, 'memory': {4392691L: 'H', 4392692L: '\x83', 4392693L: '\xc2', 4392694L: '\x01'}}, 'disassembly': 'ADD RDX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_73(self):
''' Instruction ADD RSP, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 531L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 7209408L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239574L, 'RBP': 7051232L}, 'memory': {4239576L: '\xc4', 4239577L: '\x08', 4239574L: 'H', 4239575L: '\x83'}}, 'text': 'H\x83\xc4\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 7209408L, 'RSP': 140737488345816L, 'RDX': 0L, 'RIP': 4239578L, 'RBP': 7051232L}, 'memory': {4239576L: '\xc4', 4239577L: '\x08', 4239574L: 'H', 4239575L: '\x83'}}, 'disassembly': 'ADD RSP, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_74(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346776L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488350405L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 4294967264L, 'RBX': 140737488346784L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322534L, 'RBP': 140737488350405L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_75(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346632L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488349535L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346640L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322534L, 'RBP': 140737488349535L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_76(self):
''' Instruction ADD R10, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 37L, 'R10': 4783021L, 'RDI': 140737354125667L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336207L, 'RBP': 140737488345936L}, 'memory': {4336208L: '\x83', 4336209L: '\xc2', 4336210L: '\x01', 4336207L: 'I'}}, 'text': 'I\x83\xc2\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 37L, 'R10': 4783022L, 'RDI': 140737354125667L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336211L, 'RBP': 140737488345936L}, 'memory': {4336208L: '\x83', 4336209L: '\xc2', 4336210L: '\x01', 4336207L: 'I'}}, 'disassembly': 'ADD R10, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_77(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346752L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350328L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346760L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350328L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_78(self):
''' Instruction ADD RAX, R13 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 0L, 'RDI': 4807352L, 'R13': 80L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 1L, 'RIP': 4520211L, 'RBP': 140737488346112L}, 'memory': {4520211L: 'L', 4520212L: '\x01', 4520213L: '\xe8'}}, 'text': 'L\x01\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 0L, 'RDI': 4807352L, 'R13': 80L, 'RAX': 7074368L, 'RSP': 140737488346080L, 'RDX': 1L, 'RIP': 4520214L, 'RBP': 140737488346112L}, 'memory': {4520211L: 'L', 4520212L: '\x01', 4520213L: '\xe8'}}, 'disassembly': 'ADD RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_79(self):
''' Instruction ADD RSP, 0x28 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199227L, 'RBP': 140737488346224L}, 'memory': {4199227L: 'H', 4199228L: '\x83', 4199229L: '\xc4', 4199230L: '('}}, 'text': 'H\x83\xc4(', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4199231L, 'RBP': 140737488346224L}, 'memory': {4199227L: 'H', 4199228L: '\x83', 4199229L: '\xc4', 4199230L: '('}}, 'disassembly': 'ADD RSP, 0x28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_8(self):
''' Instruction ADD RBX, 0x18 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4194816L, 'RDI': 6L, 'RAX': 4400160L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197563L, 'RBP': 1L}, 'memory': {4197563L: 'H', 4197564L: '\x83', 4197565L: '\xc3', 4197566L: '\x18'}}, 'text': 'H\x83\xc3\x18', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4194840L, 'RDI': 6L, 'RAX': 4400160L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197567L, 'RBP': 1L}, 'memory': {4197563L: 'H', 4197564L: '\x83', 4197565L: '\xc3', 4197566L: '\x18'}}, 'disassembly': 'ADD RBX, 0x18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_80(self):
''' Instruction ADD R12, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 78L, 'RAX': 140737354125932L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199273L, 'RBP': 4782912L}, 'memory': {4199273L: 'I', 4199274L: '\x83', 4199275L: '\xc4', 4199276L: '\x01'}}, 'text': 'I\x83\xc4\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125932L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199277L, 'RBP': 4782912L}, 'memory': {4199273L: 'I', 4199274L: '\x83', 4199275L: '\xc4', 4199276L: '\x01'}}, 'disassembly': 'ADD R12, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_81(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346936L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488351032L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346944L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322534L, 'RBP': 140737488351032L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_82(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346640L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488349565L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346648L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488349565L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_83(self):
''' Instruction ADD EDX, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 64L, 'RSI': 7168L, 'RDI': 4L, 'EDX': 63L, 'RAX': 8L, 'RSP': 140737488345968L, 'RDX': 63L, 'RIP': 4284259L, 'RBP': 3L}, 'memory': {4284259L: '\x83', 4284260L: '\xc2', 4284261L: '\x01'}}, 'text': '\x83\xc2\x01', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 64L, 'RSI': 7168L, 'RDI': 4L, 'EDX': 64L, 'RAX': 8L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4284262L, 'RBP': 3L}, 'memory': {4284259L: '\x83', 4284260L: '\xc2', 4284261L: '\x01'}}, 'disassembly': 'ADD EDX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_84(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RBX': 140737488346704L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488350035L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RBX': 140737488346712L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488350035L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_85(self):
''' Instruction ADD RAX, 0x38 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194424L, 'RSP': 140737488346128L, 'RDX': 1L, 'RIP': 4298133L, 'RBP': 0L}, 'memory': {4298136L: '8', 4298133L: 'H', 4298134L: '\x83', 4298135L: '\xc0'}}, 'text': 'H\x83\xc08', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194480L, 'RSP': 140737488346128L, 'RDX': 1L, 'RIP': 4298137L, 'RBP': 0L}, 'memory': {4298136L: '8', 4298133L: 'H', 4298134L: '\x83', 4298135L: '\xc0'}}, 'disassembly': 'ADD RAX, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_86(self):
''' Instruction ADD EDI, 0x1 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RAX': 45L, 'RDI': 2L, 'EDI': 2L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299477L, 'RBP': 0L}, 'memory': {4299477L: '\x83', 4299478L: '\xc7', 4299479L: '\x01'}}, 'text': '\x83\xc7\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RAX': 45L, 'RDI': 3L, 'EDI': 3L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299480L, 'RBP': 0L}, 'memory': {4299477L: '\x83', 4299478L: '\xc7', 4299479L: '\x01'}}, 'disassembly': 'ADD EDI, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_87(self):
''' Instruction ADD R15, 0x2 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 4793933L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322476L, 'RBP': 140737488347397L}, 'memory': {4322476L: 'I', 4322477L: '\x83', 4322478L: '\xc7', 4322479L: '\x02'}}, 'text': 'I\x83\xc7\x02', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4793935L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322480L, 'RBP': 140737488347397L}, 'memory': {4322476L: 'I', 4322477L: '\x83', 4322478L: '\xc7', 4322479L: '\x02'}}, 'disassembly': 'ADD R15, 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_88(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346896L, 'RDI': 7059520L, 'RAX': 140737488350830L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346904L, 'RDI': 7059520L, 'RAX': 140737488350830L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212893L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_89(self):
''' Instruction ADD RDX, 0x10 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053320L, 'RSP': 140737488345712L, 'RDX': 1984L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'text': 'H\x83\xc2\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053320L, 'RSP': 140737488345712L, 'RDX': 2000L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211140L: 'H', 4211141L: '\x83', 4211142L: '\xc2', 4211143L: '\x10'}}, 'disassembly': 'ADD RDX, 0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_9(self):
''' Instruction ADD RDI, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346520L, 'RAX': 140737488347630L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195971L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'text': 'H\x83\xc7\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346528L, 'RAX': 140737488347630L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195971L: 'H', 4195972L: '\x83', 4195973L: '\xc7', 4195974L: '\x08'}}, 'disassembly': 'ADD RDI, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_90(self):
''' Instruction ADD RAX, RAX '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327730L, 'RBP': 140737488345936L}, 'memory': {4327730L: 'H', 4327731L: '\x01', 4327732L: '\xc0'}}, 'text': 'H\x01\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327733L, 'RBP': 140737488345936L}, 'memory': {4327730L: 'H', 4327731L: '\x01', 4327732L: '\xc0'}}, 'disassembly': 'ADD RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_91(self):
''' Instruction ADD RAX, RDX '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 18446744073709055456L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4296960L: '\xd0', 4296958L: 'H', 4296959L: '\x01'}}, 'text': 'H\x01\xd0', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 4297344L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296960L: '\xd0', 4296958L: 'H', 4296959L: '\x01'}}, 'disassembly': 'ADD RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_92(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346544L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488347727L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346552L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488347727L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_93(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346800L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350464L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 140737488346808L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322534L, 'RBP': 140737488350464L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_94(self):
''' Instruction ADD R14, R13 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RCX': 4702111234474983745L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125931L, 'R13': 0L, 'R14': 0L, 'RSI': 4782990L, 'RIP': 4392731L, 'RSP': 140737488346064L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4392731L: 'M', 4392732L: '\x01', 4392733L: '\xee'}}, 'text': 'M\x01\xee', 'pos': {'registers': {'RCX': 4702111234474983745L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125931L, 'R13': 0L, 'R14': 0L, 'RSI': 4782990L, 'RIP': 4392734L, 'RSP': 140737488346064L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4392731L: 'M', 4392732L: '\x01', 4392733L: '\xee'}}, 'disassembly': 'ADD R14, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_95(self):
''' Instruction ADD RSP, 0xa8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488343968L, 'RDX': 140737354129408L, 'RIP': 4661293L, 'RBP': 4294967295L}, 'memory': {4661293L: 'H', 4661294L: '\x81', 4661295L: '\xc4', 4661296L: '\xa8', 4661297L: '\x00', 4661298L: '\x00', 4661299L: '\x00'}}, 'text': 'H\x81\xc4\xa8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344136L, 'RDX': 140737354129408L, 'RIP': 4661300L, 'RBP': 4294967295L}, 'memory': {4661293L: 'H', 4661294L: '\x81', 4661295L: '\xc4', 4661296L: '\xa8', 4661297L: '\x00', 4661298L: '\x00', 4661299L: '\x00'}}, 'disassembly': 'ADD RSP, 0xa8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_96(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346928L, 'RDI': 7059520L, 'RAX': 140737488351013L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346936L, 'RDI': 7059520L, 'RAX': 140737488351013L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212893L, 'RBP': 0L}, 'memory': {4212889L: 'H', 4212890L: '\x83', 4212891L: '\xc3', 4212892L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_97(self):
''' Instruction ADD RDI, 0x4 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354125475L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244342L, 'RBP': 7049504L}, 'memory': {4244344L: '\xc7', 4244345L: '\x04', 4244342L: 'H', 4244343L: '\x83'}}, 'text': 'H\x83\xc7\x04', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354125479L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244346L, 'RBP': 7049504L}, 'memory': {4244344L: '\xc7', 4244345L: '\x04', 4244342L: 'H', 4244343L: '\x83'}}, 'disassembly': 'ADD RDI, 0x4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_98(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346920L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488350989L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346928L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322534L, 'RBP': 140737488350989L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testADD_99(self):
''' Instruction ADD RBX, 0x8 '''
test = {'mnemonic': 'ADD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346784L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350429L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'text': 'H\x83\xc3\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346792L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350429L}, 'memory': {4322530L: 'H', 4322531L: '\x83', 4322532L: '\xc3', 4322533L: '\x08'}}, 'disassembly': 'ADD RBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_1(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782912L, 'RSI': 140737354125330L, 'ECX': 4782912L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239589L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125330L, 'ECX': 0L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_10(self):
''' Instruction AND ECX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782912L, 'RSI': 4782912L, 'ECX': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244418L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'text': '\x83\xe1\x07', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'ECX': 0L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244421L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'disassembly': 'AND ECX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_100(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035168L, 'RDI': 7071824L, 'EDX': 32L, 'RAX': 7054432L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245728L, 'RBP': 80L}, 'memory': {4245728L: '\x83', 4245729L: '\xe2', 4245730L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035168L, 'RDI': 7071824L, 'EDX': 0L, 'RAX': 7054432L, 'RSP': 140737488346152L, 'RDX': 0L, 'RIP': 4245731L, 'RBP': 80L}, 'memory': {4245728L: '\x83', 4245729L: '\xe2', 4245730L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_101(self):
''' Instruction AND EDX, 0xf0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244368L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'text': '\x81\xe2\xf0\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'EDX': 0L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244374L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'disassembly': 'AND EDX, 0xf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_11(self):
''' Instruction AND RAX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239620L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'text': 'H\x83\xe0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'disassembly': 'AND RAX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_12(self):
''' Instruction AND ESI, 0x3ff '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4096L, 'RSI': 15360L, 'ESI': 15360L, 'RDI': 4L, 'RAX': 16L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4284262L, 'RBP': 9L}, 'memory': {4284262L: '\x81', 4284263L: '\xe6', 4284264L: '\xff', 4284265L: '\x03', 4284266L: '\x00', 4284267L: '\x00'}}, 'text': '\x81\xe6\xff\x03\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 0L, 'ESI': 0L, 'RDI': 4L, 'RAX': 16L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4284268L, 'RBP': 9L}, 'memory': {4284262L: '\x81', 4284263L: '\xe6', 4284264L: '\xff', 4284265L: '\x03', 4284266L: '\x00', 4284267L: '\x00'}}, 'disassembly': 'AND ESI, 0x3ff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_13(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125631L, 'EDX': 78L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244576L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125631L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_14(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_15(self):
''' Instruction AND ECX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782912L, 'RSI': 4782912L, 'ECX': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244418L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'text': '\x83\xe1\x07', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'ECX': 0L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244421L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'disassembly': 'AND ECX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_16(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_17(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_18(self):
''' Instruction AND EAX, 0x8000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198979L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'text': '%\x00\x80\x00\x00', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198984L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'disassembly': 'AND EAX, 0x8000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_19(self):
''' Instruction AND RAX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239620L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'text': 'H\x83\xe0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'disassembly': 'AND RAX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_2(self):
''' Instruction AND EAX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 14680585L, 'RFLAGS': 518L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 14680585L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284089L, 'RBP': 3L}, 'memory': {4284089L: '\x83', 4284090L: '\xe0', 4284091L: '\x07'}}, 'text': '\x83\xe0\x07', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284092L, 'RBP': 3L}, 'memory': {4284089L: '\x83', 4284090L: '\xe0', 4284091L: '\x07'}}, 'disassembly': 'AND EAX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_20(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4793949L, 'RSI': 1L, 'ECX': 4793949L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7074288L, 'RIP': 4239589L, 'RBP': 140737488346472L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'ECX': 29L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7074288L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_21(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_22(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_23(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125759L, 'EDX': 78L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244576L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125759L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_24(self):
''' Instruction AND EDX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 63L, 'RSI': 4194304L, 'RDI': 2L, 'EDX': 14680585L, 'RAX': 469778722L, 'RSP': 140737488346144L, 'RDX': 14680585L, 'RIP': 4284967L, 'RBP': 32768L}, 'memory': {4284968L: '\xe2', 4284969L: '\x07', 4284967L: '\x83'}}, 'text': '\x83\xe2\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 63L, 'RSI': 4194304L, 'RDI': 2L, 'EDX': 1L, 'RAX': 469778722L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4284970L, 'RBP': 32768L}, 'memory': {4284968L: '\xe2', 4284969L: '\x07', 4284967L: '\x83'}}, 'disassembly': 'AND EDX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_25(self):
''' Instruction AND EBX, 0xff '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 513L, 'RSI': 4194304L, 'RDI': 2L, 'EBX': 4L, 'RAX': 4L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285434L, 'RBP': 32768L}, 'memory': {4285434L: '\x81', 4285435L: '\xe3', 4285436L: '\xff', 4285437L: '\x00', 4285438L: '\x00', 4285439L: '\x00'}}, 'text': '\x81\xe3\xff\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 513L, 'RSI': 4194304L, 'RDI': 2L, 'EBX': 4L, 'RAX': 4L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285440L, 'RBP': 32768L}, 'memory': {4285434L: '\x81', 4285435L: '\xe3', 4285436L: '\xff', 4285437L: '\x00', 4285438L: '\x00', 4285439L: '\x00'}}, 'disassembly': 'AND EBX, 0xff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_26(self):
''' Instruction AND R14, -0x8 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 643L, 'R14': 0L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4222448L, 'RBP': 7051232L}, 'memory': {4222448L: 'I', 4222449L: '\x83', 4222450L: '\xe6', 4222451L: '\xf8'}}, 'text': 'I\x83\xe6\xf8', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4222452L, 'RBP': 7051232L}, 'memory': {4222448L: 'I', 4222449L: '\x83', 4222450L: '\xe6', 4222451L: '\xf8'}}, 'disassembly': 'AND R14, -0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_27(self):
''' Instruction AND EAX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 14680585L, 'RFLAGS': 518L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 14680585L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284089L, 'RBP': 9L}, 'memory': {4284089L: '\x83', 4284090L: '\xe0', 4284091L: '\x07'}}, 'text': '\x83\xe0\x07', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284092L, 'RBP': 9L}, 'memory': {4284089L: '\x83', 4284090L: '\xe0', 4284091L: '\x07'}}, 'disassembly': 'AND EAX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_28(self):
''' Instruction AND EDX, 0xf0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125566L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244368L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'text': '\x81\xe2\xf0\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125566L, 'EDX': 0L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244374L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'disassembly': 'AND EDX, 0xf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_29(self):
''' Instruction AND EAX, 0x8000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198979L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'text': '%\x00\x80\x00\x00', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198984L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'disassembly': 'AND EAX, 0x8000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_3(self):
''' Instruction AND EDX, R8D '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 26L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 33824L, 'R8D': 63L, 'RIP': 4416449L, 'EDX': 0L, 'RSP': 140737488346168L, 'RFLAGS': 2567L, 'RAX': 140737488347364L}, 'memory': {4416449L: 'D', 4416450L: '!', 4416451L: '\xc2'}}, 'text': 'D!\xc2', 'pos': {'registers': {'RCX': 26L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 33824L, 'R8D': 63L, 'RIP': 4416452L, 'EDX': 0L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 140737488347364L}, 'memory': {4416449L: 'D', 4416450L: '!', 4416451L: '\xc2'}}, 'disassembly': 'AND EDX, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_30(self):
''' Instruction AND EDX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 18446744073704757701L, 'RDX': 16L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4239651L, 'EDX': 16L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4793968L}, 'memory': {4239651L: '!', 4239652L: '\xf2'}}, 'text': '!\xf2', 'pos': {'registers': {'RCX': 18446744073704757701L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4239653L, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 582L, 'RAX': 4793968L}, 'memory': {4239651L: '!', 4239652L: '\xf2'}}, 'disassembly': 'AND EDX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_31(self):
''' Instruction AND RAX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239620L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'text': 'H\x83\xe0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'disassembly': 'AND RAX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_32(self):
''' Instruction AND RAX, -0x8 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221246L, 'RBP': 7051232L}, 'memory': {4221248L: '\xe0', 4221249L: '\xf8', 4221246L: 'H', 4221247L: '\x83'}}, 'text': 'H\x83\xe0\xf8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221250L, 'RBP': 7051232L}, 'memory': {4221248L: '\xe0', 4221249L: '\xf8', 4221246L: 'H', 4221247L: '\x83'}}, 'disassembly': 'AND RAX, -0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_33(self):
''' Instruction AND RAX, -0x8 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 138817L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4222752L, 'RBP': 7051232L}, 'memory': {4222752L: 'H', 4222753L: '\x83', 4222754L: '\xe0', 4222755L: '\xf8'}}, 'text': 'H\x83\xe0\xf8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 138816L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4222756L, 'RBP': 7051232L}, 'memory': {4222752L: 'H', 4222753L: '\x83', 4222754L: '\xe0', 4222755L: '\xf8'}}, 'disassembly': 'AND RAX, -0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_34(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 250L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 250L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 0L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_35(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 4350L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L, 'ECX': 4350L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 4096L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 4096L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_36(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782912L, 'RSI': 140737354125695L, 'ECX': 4782912L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239589L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125695L, 'ECX': 0L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_37(self):
''' Instruction AND DWORD [RBX], -0x2 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737354125312L, 'RBX': 7049504L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343920L, 'RDX': 140737354129408L, 'RIP': 4203216L, 'RBP': 140737354125312L}, 'memory': {4203216L: '\x83', 4203217L: '#', 4203218L: '\xfe', 7049504: '\x84', 7049505: ' ', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\x00', 7049514: '\x00', 7049515: '\x00', 7049516: '\x00', 7049517: '\x00', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\x00', 7049522: '\x00', 7049523: '\x00', 7049524: '\x00', 7049525: '\x00', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\x00', 7049530: '\x00', 7049531: '\x00', 7049532: '\x00', 7049533: '\x00', 7049534: '\x00', 7049535: '\x00'}}, 'text': '\x83#\xfe', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343920L, 'RDX': 140737354129408L, 'RIP': 4203219L, 'RBP': 140737354125312L}, 'memory': {4203216L: '\x83', 4203217L: '#', 4203218L: '\xfe', 7049504: '\x84', 7049505: ' ', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\x00', 7049514: '\x00', 7049515: '\x00', 7049516: '\x00', 7049517: '\x00', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\x00', 7049522: '\x00', 7049523: '\x00', 7049524: '\x00', 7049525: '\x00', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\x00', 7049530: '\x00', 7049531: '\x00', 7049532: '\x00', 7049533: '\x00', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'AND DWORD [RBX], -0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_38(self):
''' Instruction AND ECX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782912L, 'RSI': 4782912L, 'ECX': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244418L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'text': '\x83\xe1\x07', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'ECX': 0L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244421L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'disassembly': 'AND ECX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_39(self):
''' Instruction AND EDX, 0xf0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125852L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244368L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'text': '\x81\xe2\xf0\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125852L, 'EDX': 0L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244374L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'disassembly': 'AND EDX, 0xf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_4(self):
''' Instruction AND RAX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239620L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'text': 'H\x83\xe0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'disassembly': 'AND RAX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_40(self):
''' Instruction AND AX, 0xf0c0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 831L, 'AX': 895L, 'RAX': 895L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4319822L, 'RBP': 140737488346472L}, 'memory': {4319824L: '\xc0', 4319825L: '\xf0', 4319822L: 'f', 4319823L: '%'}}, 'text': 'f%\xc0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 831L, 'AX': 64L, 'RAX': 64L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4319826L, 'RBP': 140737488346472L}, 'memory': {4319824L: '\xc0', 4319825L: '\xf0', 4319822L: 'f', 4319823L: '%'}}, 'disassembly': 'AND AX, 0xf0c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_41(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4794037L, 'RSI': 4294967264L, 'ECX': 4794037L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239589L, 'RBP': 140737488346472L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 53L, 'RSI': 4294967264L, 'ECX': 53L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_42(self):
''' Instruction AND EDX, 0xfff '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'EDX': 1L, 'RAX': 0L, 'RSP': 140737488343968L, 'RDX': 1L, 'RIP': 4661320L, 'RBP': 8192L}, 'memory': {4661320L: '\x81', 4661321L: '\xe2', 4661322L: '\xff', 4661323L: '\x0f', 4661324L: '\x00', 4661325L: '\x00'}}, 'text': '\x81\xe2\xff\x0f\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'EDX': 1L, 'RAX': 0L, 'RSP': 140737488343968L, 'RDX': 1L, 'RIP': 4661326L, 'RBP': 8192L}, 'memory': {4661320L: '\x81', 4661321L: '\xe2', 4661322L: '\xff', 4661323L: '\x0f', 4661324L: '\x00', 4661325L: '\x00'}}, 'disassembly': 'AND EDX, 0xfff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_43(self):
''' Instruction AND EAX, 0x8000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198979L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'text': '%\x00\x80\x00\x00', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198984L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'disassembly': 'AND EAX, 0x8000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_44(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_45(self):
''' Instruction AND ECX, 0xff0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 513L, 'RSI': 4194304L, 'ECX': 513L, 'RDI': 2L, 'RAX': 4L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285440L, 'RBP': 32768L}, 'memory': {4285440L: '\x81', 4285441L: '\xe1', 4285442L: '\xf0', 4285443L: '\x0f', 4285444L: '\x00', 4285445L: '\x00'}}, 'text': '\x81\xe1\xf0\x0f\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 512L, 'RSI': 4194304L, 'ECX': 512L, 'RDI': 2L, 'RAX': 4L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285446L, 'RBP': 32768L}, 'memory': {4285440L: '\x81', 4285441L: '\xe1', 4285442L: '\xf0', 4285443L: '\x0f', 4285444L: '\x00', 4285445L: '\x00'}}, 'disassembly': 'AND ECX, 0xff0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_46(self):
''' Instruction AND EAX, 0x6 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 7L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 7L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4299904L, 'RBP': 1L}, 'memory': {4299904L: '\x83', 4299905L: '\xe0', 4299906L: '\x06'}}, 'text': '\x83\xe0\x06', 'pos': {'registers': {'EAX': 6L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4299907L, 'RBP': 1L}, 'memory': {4299904L: '\x83', 4299905L: '\xe0', 4299906L: '\x06'}}, 'disassembly': 'AND EAX, 0x6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_47(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125394L, 'EDX': 78L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244576L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125394L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_48(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 4350L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294950912L, 'RSI': 4294950912L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L, 'ECX': 4350L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294950912L, 'RSI': 4294950912L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_49(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_5(self):
''' Instruction AND R15, RCX '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 135231L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223503L, 'RBP': 7051232L}, 'memory': {4223504L: '!', 4223505L: '\xcf', 4223503L: 'I'}}, 'text': 'I!\xcf', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 135168L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223506L, 'RBP': 7051232L}, 'memory': {4223504L: '!', 4223505L: '\xcf', 4223503L: 'I'}}, 'disassembly': 'AND R15, RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_50(self):
''' Instruction AND RDI, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783042L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247979L: 'H', 4247980L: '\x83', 4247981L: '\xe7', 4247982L: '\xf0'}}, 'text': 'H\x83\xe7\xf0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247979L: 'H', 4247980L: '\x83', 4247981L: '\xe7', 4247982L: '\xf0'}}, 'disassembly': 'AND RDI, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_51(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_52(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 57634L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967288L, 'RSI': 4294967288L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L, 'ECX': 57634L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 57632L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967288L, 'RSI': 4294967288L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483638L, 'ECX': 57632L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_53(self):
''' Instruction AND EDX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 4L, 'EDX': 14687755L, 'RAX': 470008163L, 'RSP': 140737488346144L, 'RDX': 14687755L, 'RIP': 4284967L, 'RBP': 32768L}, 'memory': {4284968L: '\xe2', 4284969L: '\x07', 4284967L: '\x83'}}, 'text': '\x83\xe2\x07', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 4L, 'EDX': 3L, 'RAX': 470008163L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4284970L, 'RBP': 32768L}, 'memory': {4284968L: '\xe2', 4284969L: '\x07', 4284967L: '\x83'}}, 'disassembly': 'AND EDX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_54(self):
''' Instruction AND RDX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1623L, 'RIP': 4219368L, 'RBP': 7051232L}, 'memory': {4219368L: 'H', 4219369L: '\x83', 4219370L: '\xe2', 4219371L: '\xf0'}}, 'text': 'H\x83\xe2\xf0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219372L, 'RBP': 7051232L}, 'memory': {4219368L: 'H', 4219369L: '\x83', 4219370L: '\xe2', 4219371L: '\xf0'}}, 'disassembly': 'AND RDX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_55(self):
''' Instruction AND EDX, 0xf0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125645L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244368L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'text': '\x81\xe2\xf0\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125645L, 'EDX': 0L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244374L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'disassembly': 'AND EDX, 0xf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_56(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125996L, 'EDX': 78L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244576L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125996L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_57(self):
''' Instruction AND EDX, 0xf0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244368L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'text': '\x81\xe2\xf0\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'EDX': 0L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244374L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'disassembly': 'AND EDX, 0xf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_58(self):
''' Instruction AND R12D, 0x8000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4294967040L, 'RAX': 4783020L, 'RDI': 4783024L, 'R12D': 4222429316L, 'RSP': 140737488344256L, 'RDX': 12L, 'RIP': 4329679L, 'RBP': 140737488345936L}, 'memory': {4329679L: 'A', 4329680L: '\x81', 4329681L: '\xe4', 4329682L: '\x00', 4329683L: '\x80', 4329684L: '\x00', 4329685L: '\x00'}}, 'text': 'A\x81\xe4\x00\x80\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 4294967040L, 'RAX': 4783020L, 'RDI': 4783024L, 'R12D': 0L, 'RSP': 140737488344256L, 'RDX': 12L, 'RIP': 4329686L, 'RBP': 140737488345936L}, 'memory': {4329679L: 'A', 4329680L: '\x81', 4329681L: '\xe4', 4329682L: '\x00', 4329683L: '\x80', 4329684L: '\x00', 4329685L: '\x00'}}, 'disassembly': 'AND R12D, 0x8000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_59(self):
''' Instruction AND ESI, 0x3ff '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 64L, 'RSI': 7168L, 'ESI': 7168L, 'RDI': 4L, 'RAX': 8L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4284262L, 'RBP': 3L}, 'memory': {4284262L: '\x81', 4284263L: '\xe6', 4284264L: '\xff', 4284265L: '\x03', 4284266L: '\x00', 4284267L: '\x00'}}, 'text': '\x81\xe6\xff\x03\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 64L, 'RSI': 0L, 'ESI': 0L, 'RDI': 4L, 'RAX': 8L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4284268L, 'RBP': 3L}, 'memory': {4284262L: '\x81', 4284263L: '\xe6', 4284264L: '\xff', 4284265L: '\x03', 4284266L: '\x00', 4284267L: '\x00'}}, 'disassembly': 'AND ESI, 0x3ff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_6(self):
''' Instruction AND EBX, 0xff '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 256L, 'RSI': 4194304L, 'RDI': 1L, 'EBX': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285434L, 'RBP': 32768L}, 'memory': {4285434L: '\x81', 4285435L: '\xe3', 4285436L: '\xff', 4285437L: '\x00', 4285438L: '\x00', 4285439L: '\x00'}}, 'text': '\x81\xe3\xff\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 256L, 'RSI': 4194304L, 'RDI': 1L, 'EBX': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285440L, 'RBP': 32768L}, 'memory': {4285434L: '\x81', 4285435L: '\xe3', 4285436L: '\xff', 4285437L: '\x00', 4285438L: '\x00', 4285439L: '\x00'}}, 'disassembly': 'AND EBX, 0xff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_60(self):
''' Instruction AND EDI, 0xf '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 7065696L, 'RAX': 132775L, 'RDI': 518L, 'EDI': 518L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300151L, 'RBP': 1L}, 'memory': {4300152L: '\xe7', 4300153L: '\x0f', 4300151L: '\x83'}}, 'text': '\x83\xe7\x0f', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 7065696L, 'RAX': 132775L, 'RDI': 6L, 'EDI': 6L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300154L, 'RBP': 1L}, 'memory': {4300152L: '\xe7', 4300153L: '\x0f', 4300151L: '\x83'}}, 'disassembly': 'AND EDI, 0xf', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_61(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 1089L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483619L, 'ECX': 1089L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483619L, 'ECX': 1024L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_62(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782912L, 'RSI': 4782990L, 'ECX': 4782912L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239589L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'ECX': 0L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_63(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_64(self):
''' Instruction AND RDI, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782899L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247979L: 'H', 4247980L: '\x83', 4247981L: '\xe7', 4247982L: '\xf0'}}, 'text': 'H\x83\xe7\xf0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247979L: 'H', 4247980L: '\x83', 4247981L: '\xe7', 4247982L: '\xf0'}}, 'disassembly': 'AND RDI, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_65(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125473L, 'EDX': 78L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244576L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125473L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_66(self):
''' Instruction AND AL, CL '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'CL': 1L, 'AL': 0L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'RIP': 4336711L, 'RSP': 140737488344256L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4336712L: '\xc8', 4336711L: ' '}}, 'text': ' \xc8', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'CL': 1L, 'AL': 0L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'RIP': 4336713L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336712L: '\xc8', 4336711L: ' '}}, 'disassembly': 'AND AL, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_67(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 1024L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'ESI': 4294963200L, 'RSI': 4294963200L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L, 'ECX': 1024L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'ESI': 4294963200L, 'RSI': 4294963200L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L, 'ECX': 0L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_68(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 57634L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967168L, 'RSI': 4294967168L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483634L, 'ECX': 57634L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967168L, 'RSI': 4294967168L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483634L, 'ECX': 57600L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_69(self):
''' Instruction AND EAX, 0x8000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198979L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'text': '%\x00\x80\x00\x00', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198984L, 'RBP': 4782912L}, 'memory': {4198979L: '%', 4198980L: '\x00', 4198981L: '\x80', 4198982L: '\x00', 4198983L: '\x00'}}, 'disassembly': 'AND EAX, 0x8000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_7(self):
''' Instruction AND EAX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 14680586L, 'RFLAGS': 518L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 14680586L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284089L, 'RBP': 9L}, 'memory': {4284089L: '\x83', 4284090L: '\xe0', 4284091L: '\x07'}}, 'text': '\x83\xe0\x07', 'pos': {'registers': {'EAX': 2L, 'RFLAGS': 514L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 2L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284092L, 'RBP': 9L}, 'memory': {4284089L: '\x83', 4284090L: '\xe0', 4284091L: '\x07'}}, 'disassembly': 'AND EAX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_70(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_71(self):
''' Instruction AND ECX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7035136L, 'RSI': 7035136L, 'ECX': 7035136L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245559L, 'RBP': 80L}, 'memory': {4245560L: '\xe1', 4245561L: '\x07', 4245559L: '\x83'}}, 'text': '\x83\xe1\x07', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035136L, 'ECX': 0L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245562L, 'RBP': 80L}, 'memory': {4245560L: '\xe1', 4245561L: '\x07', 4245559L: '\x83'}}, 'disassembly': 'AND ECX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_72(self):
''' Instruction AND ECX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782912L, 'RSI': 4782912L, 'ECX': 4782912L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244418L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'text': '\x83\xe1\x07', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'ECX': 0L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244421L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'disassembly': 'AND ECX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_73(self):
''' Instruction AND ECX, 0xff0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 256L, 'RSI': 4194304L, 'ECX': 256L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285440L, 'RBP': 32768L}, 'memory': {4285440L: '\x81', 4285441L: '\xe1', 4285442L: '\xf0', 4285443L: '\x0f', 4285444L: '\x00', 4285445L: '\x00'}}, 'text': '\x81\xe1\xf0\x0f\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 256L, 'RSI': 4194304L, 'ECX': 256L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285446L, 'RBP': 32768L}, 'memory': {4285440L: '\x81', 4285441L: '\xe1', 4285442L: '\xf0', 4285443L: '\x0f', 4285444L: '\x00', 4285445L: '\x00'}}, 'disassembly': 'AND ECX, 0xff0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_74(self):
''' Instruction AND RAX, [RSP+0x40] '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7213503L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223855L, 'RBP': 7051232L}, 'memory': {140737488345888: '\x00', 140737488345889: '\xf0', 140737488345890: '\xff', 140737488345891: '\xff', 140737488345892: '\xff', 140737488345893: '\xff', 140737488345894: '\xff', 140737488345895: '\xff', 140737488345896: '\x01', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: '@', 140737488345905: '\x00', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x00', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\x00', 140737488345929: '\x00', 140737488345930: '\x00', 140737488345931: '\x00', 140737488345932: '\x00', 140737488345933: '\x00', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\x00', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\x02', 140737488345945: '\x00', 140737488345946: '\x00', 140737488345947: '\x00', 140737488345948: '0', 140737488345949: '\x00', 140737488345950: '\x00', 140737488345951: '\x00', 4223855L: 'H', 4223856L: '#', 4223857L: 'D', 4223858L: '$', 4223859L: '@'}}, 'text': 'H#D$@', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7213056L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223860L, 'RBP': 7051232L}, 'memory': {140737488345888: '\x00', 140737488345889: '\xf0', 140737488345890: '\xff', 140737488345891: '\xff', 140737488345892: '\xff', 140737488345893: '\xff', 140737488345894: '\xff', 140737488345895: '\xff', 140737488345896: '\x01', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: '@', 140737488345905: '\x00', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x00', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\x00', 140737488345929: '\x00', 140737488345930: '\x00', 140737488345931: '\x00', 140737488345932: '\x00', 140737488345933: '\x00', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\x00', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\x02', 140737488345945: '\x00', 140737488345946: '\x00', 140737488345947: '\x00', 140737488345948: '0', 140737488345949: '\x00', 140737488345950: '\x00', 140737488345951: '\x00', 4223855L: 'H', 4223856L: '#', 4223857L: 'D', 4223858L: '$', 4223859L: '@'}}, 'disassembly': 'AND RAX, [RSP+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_75(self):
''' Instruction AND EDX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 18446744073704757637L, 'RDX': 16L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4239651L, 'EDX': 16L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4794032L}, 'memory': {4239651L: '!', 4239652L: '\xf2'}}, 'text': '!\xf2', 'pos': {'registers': {'RCX': 18446744073704757637L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4239653L, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 582L, 'RAX': 4794032L}, 'memory': {4239651L: '!', 4239652L: '\xf2'}}, 'disassembly': 'AND EDX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_76(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222427268L, 'RFLAGS': 518L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 4222427268L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_77(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782912L, 'RSI': 4782990L, 'ECX': 4782912L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239589L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'ECX': 0L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_78(self):
''' Instruction AND EDX, 0xf0 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244368L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'text': '\x81\xe2\xf0\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'EDX': 0L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244374L, 'RBP': 7049504L}, 'memory': {4244368L: '\x81', 4244369L: '\xe2', 4244370L: '\xf0', 4244371L: '\x00', 4244372L: '\x00', 4244373L: '\x00'}}, 'disassembly': 'AND EDX, 0xf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_79(self):
''' Instruction AND ECX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782912L, 'RSI': 4782912L, 'ECX': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244418L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'text': '\x83\xe1\x07', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'ECX': 0L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244421L, 'RBP': 7049504L}, 'memory': {4244418L: '\x83', 4244419L: '\xe1', 4244420L: '\x07'}}, 'disassembly': 'AND ECX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_8(self):
''' Instruction AND RBP, 0xfffffffffffff000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661202L, 'RBP': 8191L}, 'memory': {4661202L: 'H', 4661203L: '\x81', 4661204L: '\xe5', 4661205L: '\x00', 4661206L: '\xf0', 4661207L: '\xff', 4661208L: '\xff'}}, 'text': 'H\x81\xe5\x00\xf0\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661209L, 'RBP': 4096L}, 'memory': {4661202L: 'H', 4661203L: '\x81', 4661204L: '\xe5', 4661205L: '\x00', 4661206L: '\xf0', 4661207L: '\xff', 4661208L: '\xff'}}, 'disassembly': 'AND RBP, 0xfffffffffffff000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_80(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_81(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 16384L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'ESI': 4294934528L, 'RSI': 4294934528L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 16384L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'ESI': 4294934528L, 'RSI': 4294934528L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 0L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_82(self):
''' Instruction AND RDI, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416315L, 'RBP': 140737488347312L}, 'memory': {4416315L: 'H', 4416316L: '\x83', 4416317L: '\xe7', 4416318L: '\xf0'}}, 'text': 'H\x83\xe7\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416319L, 'RBP': 140737488347312L}, 'memory': {4416315L: 'H', 4416316L: '\x83', 4416317L: '\xe7', 4416318L: '\xf0'}}, 'disassembly': 'AND RDI, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_83(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 1089L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967292L, 'RSI': 4294967292L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483625L, 'ECX': 1089L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 1088L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967292L, 'RSI': 4294967292L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L, 'ECX': 1088L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_84(self):
''' Instruction AND R11D, 0x10000000 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 275146342400L, 'RSI': 7065696L, 'RDI': 6L, 'R11D': 532341759L, 'RAX': 4398046511104L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300210L, 'RBP': 1L}, 'memory': {4300210L: 'A', 4300211L: '\x81', 4300212L: '\xe3', 4300213L: '\x00', 4300214L: '\x00', 4300215L: '\x00', 4300216L: '\x10'}}, 'text': 'A\x81\xe3\x00\x00\x00\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 275146342400L, 'RSI': 7065696L, 'RDI': 6L, 'R11D': 268435456L, 'RAX': 4398046511104L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300217L, 'RBP': 1L}, 'memory': {4300210L: 'A', 4300211L: '\x81', 4300212L: '\xe3', 4300213L: '\x00', 4300214L: '\x00', 4300215L: '\x00', 4300216L: '\x10'}}, 'disassembly': 'AND R11D, 0x10000000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_85(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_86(self):
''' Instruction AND RDI, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782903L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247979L: 'H', 4247980L: '\x83', 4247981L: '\xe7', 4247982L: '\xf0'}}, 'text': 'H\x83\xe7\xf0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247979L: 'H', 4247980L: '\x83', 4247981L: '\xe7', 4247982L: '\xf0'}}, 'disassembly': 'AND RDI, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_87(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_88(self):
''' Instruction AND RDX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 47L, 'RIP': 4219368L, 'RBP': 7051232L}, 'memory': {4219368L: 'H', 4219369L: '\x83', 4219370L: '\xe2', 4219371L: '\xf0'}}, 'text': 'H\x83\xe2\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219372L, 'RBP': 7051232L}, 'memory': {4219368L: 'H', 4219369L: '\x83', 4219370L: '\xe2', 4219371L: '\xf0'}}, 'disassembly': 'AND RDX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_89(self):
''' Instruction AND EDX, 0xf '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'EDX': 7074240L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 7074240L, 'RIP': 4223804L, 'RBP': 7051232L}, 'memory': {4223804L: '\x83', 4223805L: '\xe2', 4223806L: '\x0f'}}, 'text': '\x83\xe2\x0f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'EDX': 0L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223807L, 'RBP': 7051232L}, 'memory': {4223804L: '\x83', 4223805L: '\xe2', 4223806L: '\x0f'}}, 'disassembly': 'AND EDX, 0xf', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_9(self):
''' Instruction AND ECX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 74L, 'RSI': 1600L, 'ECX': 74L, 'RDI': 7051232L, 'RAX': 2L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221000L, 'RBP': 7051232L}, 'memory': {4221000L: '\x83', 4221001L: '\xe1', 4221002L: '\x1f'}}, 'text': '\x83\xe1\x1f', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 1600L, 'ECX': 10L, 'RDI': 7051232L, 'RAX': 2L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221003L, 'RBP': 7051232L}, 'memory': {4221000L: '\x83', 4221001L: '\xe1', 4221002L: '\x1f'}}, 'disassembly': 'AND ECX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_90(self):
''' Instruction AND ECX, 0x3f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4793961L, 'RSI': 1L, 'ECX': 4793961L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239589L, 'RBP': 140737488346472L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'text': '\x83\xe1?', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'ECX': 41L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239589L: '\x83', 4239590L: '\xe1', 4239591L: '?'}}, 'disassembly': 'AND ECX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_91(self):
''' Instruction AND RAX, -0x8 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 10L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 138785L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221246L, 'RBP': 7051232L}, 'memory': {4221248L: '\xe0', 4221249L: '\xf8', 4221246L: 'H', 4221247L: '\x83'}}, 'text': 'H\x83\xe0\xf8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 10L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221250L, 'RBP': 7051232L}, 'memory': {4221248L: '\xe0', 4221249L: '\xf8', 4221246L: 'H', 4221247L: '\x83'}}, 'disassembly': 'AND RAX, -0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_92(self):
''' Instruction AND EDX, 0x7 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 511L, 'RSI': 4194304L, 'RDI': 3L, 'EDX': 14680586L, 'RAX': 469778755L, 'RSP': 140737488346144L, 'RDX': 14680586L, 'RIP': 4284967L, 'RBP': 32768L}, 'memory': {4284968L: '\xe2', 4284969L: '\x07', 4284967L: '\x83'}}, 'text': '\x83\xe2\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 511L, 'RSI': 4194304L, 'RDI': 3L, 'EDX': 2L, 'RAX': 469778755L, 'RSP': 140737488346144L, 'RDX': 2L, 'RIP': 4284970L, 'RBP': 32768L}, 'memory': {4284968L: '\xe2', 4284969L: '\x07', 4284967L: '\x83'}}, 'disassembly': 'AND EDX, 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_93(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'EDX': 469778755L, 'RAX': 469778755L, 'RSP': 140737488345968L, 'RDX': 469778755L, 'RIP': 4284081L, 'RBP': 9L}, 'memory': {4284081L: '\x83', 4284082L: '\xe2', 4284083L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'EDX': 3L, 'RAX': 469778755L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284084L, 'RBP': 9L}, 'memory': {4284081L: '\x83', 4284082L: '\xe2', 4284083L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_94(self):
''' Instruction AND EDX, 0x1f '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125552L, 'EDX': 78L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244576L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'text': '\x83\xe2\x1f', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125552L, 'EDX': 14L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244576L: '\x83', 4244577L: '\xe2', 4244578L: '\x1f'}}, 'disassembly': 'AND EDX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_95(self):
''' Instruction AND RAX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 4793973L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239629L, 'RBP': 140737488346472L}, 'memory': {4239632L: '\xf0', 4239629L: 'H', 4239630L: '\x83', 4239631L: '\xe0'}}, 'text': 'H\x83\xe0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239633L, 'RBP': 140737488346472L}, 'memory': {4239632L: '\xf0', 4239629L: 'H', 4239630L: '\x83', 4239631L: '\xe0'}}, 'disassembly': 'AND RAX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_96(self):
''' Instruction AND EAX, 0xa00 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'text': '%\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392491L: '%', 4392492L: '\x00', 4392493L: '\n', 4392494L: '\x00', 4392495L: '\x00'}}, 'disassembly': 'AND EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_97(self):
''' Instruction AND AL, CL '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'CL': 1L, 'AL': 0L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'RIP': 4336711L, 'RSP': 140737488344256L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4336712L: '\xc8', 4336711L: ' '}}, 'text': ' \xc8', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'CL': 1L, 'AL': 0L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'RIP': 4336713L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336712L: '\xc8', 4336711L: ' '}}, 'disassembly': 'AND AL, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_98(self):
''' Instruction AND ECX, ESI '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4248034L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L, 'ECX': 8L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'text': '!\xf1', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4248036L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248034L: '!', 4248035L: '\xf1'}}, 'disassembly': 'AND ECX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testAND_99(self):
''' Instruction AND RAX, -0x10 '''
test = {'mnemonic': 'AND', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239620L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'text': 'H\x83\xe0\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239620L: 'H', 4239621L: '\x83', 4239622L: '\xe0', 4239623L: '\xf0'}}, 'disassembly': 'AND RAX, -0x10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_1(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 64L, 'RIP': 4239763L, 'RBP': 140737488346472L}, 'memory': {4239763L: 'H', 4239764L: '\x0f', 4239765L: '\xbc', 4239766L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 6L, 'RIP': 4239767L, 'RBP': 140737488346472L}, 'memory': {4239763L: 'H', 4239764L: '\x0f', 4239765L: '\xbc', 4239766L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_10(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 1089L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248070L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L, 'ECX': 1089L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 1089L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248073L, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L, 'ECX': 1089L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_11(self):
''' Instruction BSF R9D, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 0L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 2048L, 'R9D': 4294967216L, 'RIP': 4416414L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347341L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'text': 'D\x0f\xbc\xc9', 'pos': {'registers': {'RCX': 0L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 2048L, 'R9D': 4294967216L, 'RIP': 4416418L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 140737488347341L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'disassembly': 'BSF R9D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_12(self):
''' Instruction BSF R9D, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 0L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 8208L, 'R9D': 4294967216L, 'RIP': 4416414L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347324L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'text': 'D\x0f\xbc\xc9', 'pos': {'registers': {'RCX': 0L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 8208L, 'R9D': 4294967216L, 'RIP': 4416418L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 140737488347324L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'disassembly': 'BSF R9D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_13(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 1024L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248070L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L, 'ECX': 1024L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 1024L, 'RDX': 10L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248073L, 'EDX': 10L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L, 'ECX': 1024L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_14(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248070L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483619L, 'ECX': 1024L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 1024L, 'RDX': 10L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248073L, 'EDX': 10L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483619L, 'ECX': 1024L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_15(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 57634L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248070L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 57634L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 57634L, 'RDX': 1L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248073L, 'EDX': 1L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L, 'ECX': 57634L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_16(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_17(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_18(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 2048L, 'RIP': 4239739L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 11L, 'RIP': 4239743L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_19(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 128L, 'RIP': 4239739L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7L, 'RIP': 4239743L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_2(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_20(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_21(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 32768L, 'RIP': 4239739L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 15L, 'RIP': 4239743L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_22(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 57632L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248070L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483638L, 'ECX': 57632L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 57632L, 'RDX': 5L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248073L, 'EDX': 5L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L, 'ECX': 57632L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_23(self):
''' Instruction BSF R9D, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4129L, 'R9D': 4294967216L, 'RIP': 4416414L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 0L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'text': 'D\x0f\xbc\xc9', 'pos': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4129L, 'R9D': 4294967216L, 'RIP': 4416418L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 0L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'disassembly': 'BSF R9D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_24(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248070L, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L, 'ECX': 8L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 8L, 'RDX': 3L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248073L, 'EDX': 3L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 8L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_25(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_26(self):
''' Instruction BSF R9D, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 0L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 16L, 'R9D': 4294967216L, 'RIP': 4416414L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'text': 'D\x0f\xbc\xc9', 'pos': {'registers': {'RCX': 0L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 16L, 'R9D': 4294967216L, 'RIP': 4416418L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 140737488347355L, 'ECX': 0L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'disassembly': 'BSF R9D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_27(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_28(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_29(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 16L, 'RIP': 4239763L, 'RBP': 140737488346472L}, 'memory': {4239763L: 'H', 4239764L: '\x0f', 4239765L: '\xbc', 4239766L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 4L, 'RIP': 4239767L, 'RBP': 140737488346472L}, 'memory': {4239763L: 'H', 4239764L: '\x0f', 4239765L: '\xbc', 4239766L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_3(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248070L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483634L, 'ECX': 57600L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 57600L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248073L, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L, 'ECX': 57600L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_30(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 4350L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248070L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L, 'ECX': 4350L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 4350L, 'RDX': 1L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248073L, 'EDX': 1L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L, 'ECX': 4350L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_4(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 1088L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248070L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L, 'ECX': 1088L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 1088L, 'RDX': 6L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248073L, 'EDX': 6L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483625L, 'ECX': 1088L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_5(self):
''' Instruction BSF R9D, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 33824L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 33824L, 'R9D': 4294967216L, 'RIP': 4416414L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L, 'ECX': 33824L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'text': 'D\x0f\xbc\xc9', 'pos': {'registers': {'RCX': 33824L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 33824L, 'R9D': 5L, 'RIP': 4416418L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347364L, 'ECX': 33824L}, 'memory': {4416416L: '\xbc', 4416417L: '\xc9', 4416414L: 'D', 4416415L: '\x0f'}}, 'disassembly': 'BSF R9D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_6(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239743L, 'RBP': 4782912L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_7(self):
''' Instruction BSF EDX, ECX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RCX': 4096L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248070L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 4096L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'text': '\x0f\xbc\xd1', 'pos': {'registers': {'RCX': 4096L, 'RDX': 12L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248073L, 'EDX': 12L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 4096L}, 'memory': {4248072L: '\xd1', 4248070L: '\x0f', 4248071L: '\xbc'}}, 'disassembly': 'BSF EDX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_8(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 32L, 'RIP': 4239763L, 'RBP': 140737488346472L}, 'memory': {4239763L: 'H', 4239764L: '\x0f', 4239765L: '\xbc', 4239766L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 5L, 'RIP': 4239767L, 'RBP': 140737488346472L}, 'memory': {4239763L: 'H', 4239764L: '\x0f', 4239765L: '\xbc', 4239766L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSF_9(self):
''' Instruction BSF RDX, RDX '''
test = {'mnemonic': 'BSF', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 2048L, 'RIP': 4239739L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'text': 'H\x0f\xbc\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 11L, 'RIP': 4239743L, 'RBP': 140737488346472L}, 'memory': {4239739L: 'H', 4239740L: '\x0f', 4239741L: '\xbc', 4239742L: '\xd2'}}, 'disassembly': 'BSF RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSR_1(self):
''' Instruction BSR EDX, EDX '''
test = {'mnemonic': 'BSR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 31L, 'RSI': 2048L, 'RDI': 140737488347360L, 'EDX': 2048L, 'RAX': 140737488347341L, 'RSP': 140737488346168L, 'RDX': 2048L, 'RIP': 4416431L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'text': '\x0f\xbd\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 2048L, 'RDI': 140737488347360L, 'EDX': 11L, 'RAX': 140737488347341L, 'RSP': 140737488346168L, 'RDX': 11L, 'RIP': 4416434L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'disassembly': 'BSR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSR_2(self):
''' Instruction BSR EDX, EDX '''
test = {'mnemonic': 'BSR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 31L, 'RSI': 8208L, 'RDI': 140737488347344L, 'EDX': 8208L, 'RAX': 140737488347324L, 'RSP': 140737488346168L, 'RDX': 8208L, 'RIP': 4416431L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'text': '\x0f\xbd\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 8208L, 'RDI': 140737488347344L, 'EDX': 13L, 'RAX': 140737488347324L, 'RSP': 140737488346168L, 'RDX': 13L, 'RIP': 4416434L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'disassembly': 'BSR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSR_3(self):
''' Instruction BSR EDX, EDX '''
test = {'mnemonic': 'BSR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 31L, 'RSI': 16L, 'RDI': 140737488347376L, 'EDX': 16L, 'RAX': 140737488347355L, 'RSP': 140737488346168L, 'RDX': 16L, 'RIP': 4416431L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'text': '\x0f\xbd\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 16L, 'RDI': 140737488347376L, 'EDX': 4L, 'RAX': 140737488347355L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4416434L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'disassembly': 'BSR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSR_4(self):
''' Instruction BSR EDX, EDX '''
test = {'mnemonic': 'BSR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'EDX': 0L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4416452L, 'RBP': 140737488347312L}, 'memory': {4416452L: '\x0f', 4416453L: '\xbd', 4416454L: '\xd2'}}, 'text': '\x0f\xbd\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'EDX': 0L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4416455L, 'RBP': 140737488347312L}, 'memory': {4416452L: '\x0f', 4416453L: '\xbd', 4416454L: '\xd2'}}, 'disassembly': 'BSR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSR_5(self):
''' Instruction BSR EDX, EDX '''
test = {'mnemonic': 'BSR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 31L, 'RSI': 4129L, 'RDI': 140737488347328L, 'EDX': 4129L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 4129L, 'RIP': 4416431L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'text': '\x0f\xbd\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 31L, 'RSI': 4129L, 'RDI': 140737488347328L, 'EDX': 12L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 12L, 'RIP': 4416434L, 'RBP': 140737488347312L}, 'memory': {4416432L: '\xbd', 4416433L: '\xd2', 4416431L: '\x0f'}}, 'disassembly': 'BSR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testBSR_6(self):
''' Instruction BSR ECX, R9D '''
test = {'mnemonic': 'BSR', 'pre': {'registers': {'RCX': 512L, 'RDX': 1L, 'RBP': 32768L, 'RDI': 2L, 'RSI': 4194304L, 'R9D': 15L, 'RIP': 4285468L, 'RSP': 140737488346144L, 'RFLAGS': 582L, 'RAX': 4L, 'ECX': 512L}, 'memory': {4285468L: 'A', 4285469L: '\x0f', 4285470L: '\xbd', 4285471L: '\xc9'}}, 'text': 'A\x0f\xbd\xc9', 'pos': {'registers': {'RCX': 3L, 'RDX': 1L, 'RBP': 32768L, 'RDI': 2L, 'RSI': 4194304L, 'R9D': 15L, 'RIP': 4285472L, 'RSP': 140737488346144L, 'RFLAGS': 518L, 'RAX': 4L, 'ECX': 3L}, 'memory': {4285468L: 'A', 4285469L: '\x0f', 4285470L: '\xbd', 4285471L: '\xc9'}}, 'disassembly': 'BSR ECX, R9D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x40, test['pos']['registers'][reg_name]&0x40, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_1(self):
''' Instruction CALL 0x40d1a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 37L, 'RDI': 4782997L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336221L, 'RBP': 140737488345936L}, 'memory': {140737488344247L: '\xff', 140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x01', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'text': '\xe8>\xa7\xfe\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 37L, 'RDI': 4782997L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247968L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x01', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'disassembly': 'CALL 0x40d1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_10(self):
''' Instruction CALL QWORD [RBX-0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4195008L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197581L, 'RBP': 9L}, 'memory': {4195051: '\x00', 4195020: '\x00', 4195030: '\x00', 140737488346197L: '\x00', 4195031: '\x00', 4195053: '\x00', 4195032: '\xe8', 4195043: '\x00', 4195021: '\x00', 4195035: '\x00', 4195015: '\x00', 4197583L: '\xf8', 4195046: '\x00', 4195016: '%', 4195059: '\x00', 4195038: '\x00', 4195017: '\x00', 4195000: '\xa0', 4195001: '\xb7', 4195002: '@', 4195003: '\x00', 4195004: '\x00', 4195005: '\x00', 4195006: '\x00', 4195007: '\x00', 4195008: '\xf0', 4195009: '\x88', 4195010: 'k', 4195011: '\x00', 4195012: '\x00', 4195013: '\x00', 4195014: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 4197581L: '\xff', 140737488346190L: '\x00', 140737488346189L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 4195028: '\x00', 4197582L: 'S', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4195033: '\x88', 4195034: 'k', 140737488346191L: '\x00', 4195036: '\x00', 4195037: '\x00', 4195023: '\x00', 4195039: '\x00', 4195040: '%', 4195024: '@', 4195042: '\x00', 4195022: '\x00', 4195044: '\x00', 4195045: '\x00', 4195019: '\x00', 4195025: 'J', 4195048: '\x00', 4195018: '\x00', 4195050: 'C', 4195047: '\x00', 4195052: '\x00', 4195026: 'C', 4195054: '\x00', 4195055: '\x00', 4195056: '\xe0', 4195057: '\x88', 4195058: 'k', 4195027: '\x00', 4195060: '\x00', 4195061: '\x00', 4195062: '\x00', 4195049: 'G', 140737488346196L: '\x00', 4195041: '\x00', 4195063: '\x00', 4195029: '\x00'}}, 'text': '\xffS\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4241312L, 'RBP': 9L}, 'memory': {140737488346175L: '\x00', 140737488346176L: '\x90', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4195023: '\x00', 4197581L: '\xff', 4195000: '\xa0', 4195001: '\xb7', 4195002: '@', 4195003: '\x00', 4195004: '\x00', 4195005: '\x00', 4195006: '\x00', 4195007: '\x00', 4195008: '\xf0', 4195009: '\x88', 4195010: 'k', 4195011: '\x00', 4195012: '\x00', 4195013: '\x00', 4195014: '\x00', 4195015: '\x00', 4195016: '%', 4195017: '\x00', 4195018: '\x00', 4195019: '\x00', 4195020: '\x00', 4195021: '\x00', 4197582L: 'S', 4197583L: '\xf8', 4195024: '@', 4195025: 'J', 4195026: 'C', 4195027: '\x00', 4195028: '\x00', 4195022: '\x00', 4195030: '\x00', 4195031: '\x00', 4195032: '\xe8', 4195033: '\x88', 4195034: 'k', 4195035: '\x00', 4195036: '\x00', 4195037: '\x00', 4195038: '\x00', 4195039: '\x00', 4195040: '%', 4195041: '\x00', 4195042: '\x00', 4195043: '\x00', 4195044: '\x00', 4195045: '\x00', 4195046: '\x00', 4195047: '\x00', 4195048: '\x00', 4195049: 'G', 4195050: 'C', 4195051: '\x00', 4195052: '\x00', 4195053: '\x00', 4195054: '\x00', 4195055: '\x00', 4195056: '\xe0', 4195057: '\x88', 4195058: 'k', 4195059: '\x00', 4195060: '\x00', 4195061: '\x00', 4195062: '\x00', 4195063: '\x00', 4195029: '\x00'}}, 'disassembly': 'CALL QWORD [RBX-0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_100(self):
''' Instruction CALL QWORD [RBX-0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4194984L, 'RDI': 6L, 'RAX': 4664208L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197581L, 'RBP': 8L}, 'memory': {4195020: '\x00', 4195030: '\x00', 140737488346197L: '\x00', 4195031: '\x00', 4195032: '\xe8', 4195039: '\x00', 140737488346189L: '\x00', 4194976: '0', 4194977: '\xbd', 4194978: 'C', 4194979: '\x00', 4194980: '\x00', 4194981: '\x00', 4194982: '\x00', 4194983: '\x00', 4194984: '\xf8', 4194985: '\x88', 4194986: 'k', 4194987: '\x00', 4194988: '\x00', 4194989: '\x00', 4194990: '\x00', 4194991: '\x00', 4194992: '%', 4194993: '\x00', 4194994: '\x00', 4194995: '\x00', 4194996: '\x00', 4194997: '\x00', 4194998: '\x00', 4194999: '\x00', 4195000: '\xa0', 4195001: '\xb7', 4195002: '@', 4195003: '\x00', 4195004: '\x00', 4195005: '\x00', 4195006: '\x00', 4195007: '\x00', 4195008: '\xf0', 4195009: '\x88', 4195010: 'k', 4195011: '\x00', 4195012: '\x00', 4195013: '\x00', 4195014: '\x00', 140737488346183L: '\x00', 4195016: '%', 4195017: '\x00', 140737488346186L: '@', 4195019: '\x00', 140737488346188L: '\x00', 4197581L: '\xff', 140737488346190L: '\x00', 140737488346191L: '\x00', 4195024: '@', 4195025: 'J', 4195026: 'C', 4195027: '\x00', 4195028: '\x00', 4197582L: 'S', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4195033: '\x88', 4195034: 'k', 4195023: '\x00', 4195036: '\x00', 4195037: '\x00', 4195038: '\x00', 4195035: '\x00', 140737488346192L: '\x90', 4195022: '\x00', 140737488346193L: '\r', 4195018: '\x00', 4197583L: '\xf8', 140737488346194L: '@', 4195015: '\x00', 140737488346184L: '\xd0', 140737488346187L: '\x00', 140737488346195L: '\x00', 140737488346185L: '\x0c', 140737488346196L: '\x00', 4195021: '\x00', 4195029: '\x00'}}, 'text': '\xffS\xf8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4664208L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4439344L, 'RBP': 8L}, 'memory': {140737488346175L: '\x00', 140737488346176L: '\x90', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4195023: '\x00', 4197581L: '\xff', 4194976: '0', 4194977: '\xbd', 4194978: 'C', 4194979: '\x00', 4194980: '\x00', 4194981: '\x00', 4194982: '\x00', 4194983: '\x00', 4194984: '\xf8', 4194985: '\x88', 4194986: 'k', 4194987: '\x00', 4194988: '\x00', 4194989: '\x00', 4194990: '\x00', 4194991: '\x00', 4194992: '%', 4194993: '\x00', 4194994: '\x00', 4194995: '\x00', 4194996: '\x00', 4194997: '\x00', 4194998: '\x00', 4194999: '\x00', 4195000: '\xa0', 4195001: '\xb7', 4195002: '@', 4195003: '\x00', 4195004: '\x00', 4195005: '\x00', 4195006: '\x00', 4195007: '\x00', 4195008: '\xf0', 4195009: '\x88', 4195010: 'k', 4195011: '\x00', 4195012: '\x00', 4195013: '\x00', 4195014: '\x00', 4195015: '\x00', 4195016: '%', 4195017: '\x00', 4195018: '\x00', 4195019: '\x00', 4195020: '\x00', 4195021: '\x00', 4197582L: 'S', 4197583L: '\xf8', 4195024: '@', 4195025: 'J', 4195026: 'C', 4195027: '\x00', 4195028: '\x00', 4195022: '\x00', 4195030: '\x00', 4195031: '\x00', 4195032: '\xe8', 4195033: '\x88', 4195034: 'k', 4195035: '\x00', 4195036: '\x00', 4195037: '\x00', 4195038: '\x00', 4195039: '\x00', 4195029: '\x00'}}, 'disassembly': 'CALL QWORD [RBX-0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_101(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_11(self):
''' Instruction CALL 0x40d1a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 37L, 'RDI': 4782888L, 'RAX': 140737488345984L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329674L, 'RBP': 140737488345936L}, 'memory': {140737488344247L: '\x00', 140737488344248L: '\x00', 140737488344249L: '\x00', 140737488344250L: '\x00', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x00', 4329674L: '\xe8', 4329675L: '\xd1', 4329676L: '\xc0', 4329677L: '\xfe', 4329678L: '\xff'}}, 'text': '\xe8\xd1\xc0\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 37L, 'RDI': 4782888L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247968L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\x00', 140737488344241L: '\x00', 140737488344242L: '\x00', 140737488344243L: '\x00', 140737488344244L: '\x00', 140737488344245L: '\x00', 140737488344246L: '\x00', 140737488344247L: '\x00', 140737488344248L: '\xcf', 140737488344249L: '\x10', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x00', 4329674L: '\xe8', 4329675L: '\xd1', 4329676L: '\xc0', 4329677L: '\xfe', 4329678L: '\xff'}}, 'disassembly': 'CALL 0x40d1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_12(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x02', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x02', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_13(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_14(self):
''' Instruction CALL 0x419b70 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346240L, 'RDX': 140737488346512L, 'RIP': 4196135L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4196135L: '\xe8', 4196136L: 'D', 4196137L: '\x94', 4196138L: '\x01', 4196139L: '\x00', 140737488346231L: '\x00', 140737488346232L: '3', 140737488346233L: '\x08', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xe8D\x94\x01\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346232L, 'RDX': 140737488346512L, 'RIP': 4299632L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4196135L: '\xe8', 4196136L: 'D', 4196137L: '\x94', 4196138L: '\x01', 4196139L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: ',', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'CALL 0x419b70', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_15(self):
''' Instruction CALL 0x419640 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7042728L, 'RSI': 0L, 'RDI': 0L, 'RAX': 7065368L, 'RSP': 140737488346080L, 'RDX': 7042720L, 'RIP': 4519970L, 'RBP': 140737488346112L}, 'memory': {4519970L: '\xe8', 4519971L: '\x19', 4519972L: '\x9e', 4519973L: '\xfc', 4519974L: '\xff', 140737488346071L: '\x00', 140737488346072L: 'q', 140737488346073L: ':', 140737488346074L: 'J', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00', 140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 140737488346084L: '\xff', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: 'q'}}, 'text': '\xe8\x19\x9e\xfc\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7042728L, 'RSI': 0L, 'RDI': 0L, 'RAX': 7065368L, 'RSP': 140737488346072L, 'RDX': 7042720L, 'RIP': 4298304L, 'RBP': 140737488346112L}, 'memory': {4519970L: '\xe8', 4519971L: '\x19', 4519972L: '\x9e', 4519973L: '\xfc', 4519974L: '\xff', 140737488346063L: '\x00', 140737488346064L: '\x00', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: "'", 140737488346073L: '\xf8', 140737488346074L: 'D', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00', 140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 140737488346084L: '\xff', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: 'q'}}, 'disassembly': 'CALL 0x419640', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_16(self):
''' Instruction CALL 0x420880 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\x87', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\x04'}}, 'text': '\xe89\xd9\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327552L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\x04'}}, 'disassembly': 'CALL 0x420880', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_17(self):
''' Instruction CALL 0x41edb0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283909L, 'RBP': 9L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'text': '\xe8\xa6\x8f\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'CALL 0x41edb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_18(self):
''' Instruction CALL QWORD [RSP+0x18] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346240L, 'RDX': 140737488346512L, 'RIP': 4196280L, 'RBP': 0L}, 'memory': {140737488346231L: '\x00', 140737488346232L: 's', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00', 140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 140737488346264: '\x0c', 140737488346265: '\x05', 140737488346266: '@', 140737488346267: '\x00', 140737488346268: '\x00', 140737488346269: '\x00', 140737488346270: '\x00', 140737488346271: '\x00', 140737488346272: '\x90', 140737488346273: '\r', 140737488346274: '@', 140737488346275: '\x00', 140737488346276: '\x00', 140737488346277: '\x00', 140737488346278: '\x00', 140737488346279: '\x00', 140737488346280: '\x00', 140737488346281: '\x00', 140737488346282: '\x00', 140737488346283: '\x00', 140737488346284: '\x00', 140737488346285: '\x00', 140737488346286: '\x00', 140737488346287: '\x00', 140737488346288: '\xf0', 140737488346289: '\x0c', 140737488346290: '@', 140737488346291: '\x00', 140737488346292: '\x00', 140737488346293: '\x00', 140737488346294: '\x00', 140737488346295: '\x00', 140737488346296: '\x07', 140737488346297: '\x00', 140737488346298: '\x00', 140737488346299: '\x00', 140737488346300: '\x00', 140737488346301: '\x00', 140737488346302: '\x00', 140737488346303: '\x00', 140737488346304: '\x00', 140737488346305: '\x00', 140737488346306: '\x00', 140737488346307: '\x00', 140737488346308: '\x00', 140737488346309: '\x00', 140737488346310: '\x00', 140737488346311: '\x00', 140737488346312: '\x00', 140737488346313: '\x00', 140737488346314: '\x00', 140737488346315: '\x00', 140737488346316: '\x00', 140737488346317: '\x00', 140737488346318: '\x00', 140737488346319: '\x00', 140737488346320: '\x00', 140737488346321: '\x00', 140737488346322: '\x00', 140737488346323: '\xb9', 140737488346324: '\xff', 140737488346325: '\xff', 140737488346326: '\xff', 140737488346327: '\xff', 4196280L: '\xff', 4196281L: 'T', 4196282L: '$', 4196283L: '\x18'}}, 'text': '\xffT$\x18', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346232L, 'RDX': 140737488346512L, 'RIP': 4195596L, 'RBP': 0L}, 'memory': {140737488346223L: '\x00', 140737488346224L: '\x90', 140737488346225L: '\r', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00', 140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 140737488346264: '\x0c', 140737488346265: '\x05', 140737488346266: '@', 140737488346267: '\x00', 140737488346268: '\x00', 140737488346269: '\x00', 140737488346270: '\x00', 140737488346271: '\x00', 140737488346272: '\x90', 140737488346273: '\r', 140737488346274: '@', 140737488346275: '\x00', 140737488346276: '\x00', 140737488346277: '\x00', 140737488346278: '\x00', 140737488346279: '\x00', 140737488346280: '\x00', 140737488346281: '\x00', 140737488346282: '\x00', 140737488346283: '\x00', 140737488346284: '\x00', 140737488346285: '\x00', 140737488346286: '\x00', 140737488346287: '\x00', 140737488346288: '\xf0', 140737488346289: '\x0c', 140737488346290: '@', 140737488346291: '\x00', 140737488346292: '\x00', 140737488346293: '\x00', 140737488346294: '\x00', 140737488346295: '\x00', 140737488346296: '\x07', 140737488346297: '\x00', 140737488346298: '\x00', 140737488346299: '\x00', 140737488346300: '\x00', 140737488346301: '\x00', 140737488346302: '\x00', 140737488346303: '\x00', 140737488346304: '\x00', 140737488346305: '\x00', 140737488346306: '\x00', 140737488346307: '\x00', 140737488346308: '\x00', 140737488346309: '\x00', 140737488346310: '\x00', 140737488346311: '\x00', 140737488346312: '\x00', 140737488346313: '\x00', 140737488346314: '\x00', 140737488346315: '\x00', 140737488346316: '\x00', 140737488346317: '\x00', 140737488346318: '\x00', 140737488346319: '\x00', 140737488346320: '\x00', 140737488346321: '\x00', 140737488346322: '\x00', 140737488346323: '\xb9', 140737488346324: '\xff', 140737488346325: '\xff', 140737488346326: '\xff', 140737488346327: '\xff', 4196280L: '\xff', 4196281L: 'T', 4196282L: '$', 4196283L: '\x18'}}, 'disassembly': 'CALL QWORD [RSP+0x18]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_19(self):
''' Instruction CALL 0x40d1a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 43L, 'RSI': 37L, 'RDI': 4783016L, 'RAX': 140737488345984L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329674L, 'RBP': 140737488345936L}, 'memory': {140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1', 4329674L: '\xe8', 4329675L: '\xd1', 4329676L: '\xc0', 4329677L: '\xfe', 4329678L: '\xff'}}, 'text': '\xe8\xd1\xc0\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 43L, 'RSI': 37L, 'RDI': 4783016L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247968L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xcf', 140737488344249L: '\x10', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1', 4329674L: '\xe8', 4329675L: '\xd1', 4329676L: '\xc0', 4329677L: '\xfe', 4329678L: '\xff'}}, 'disassembly': 'CALL 0x40d1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_2(self):
''' Instruction CALL 0x44bf60 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286563L, 'RBP': 4544L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\x9e', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4286563L: '\xe8', 4286564L: '\xf8', 4286565L: 'V', 4286566L: '\x03', 4286567L: '\x00'}}, 'text': '\xe8\xf8V\x03\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4505440L, 'RBP': 4544L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'h', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4286563L: '\xe8', 4286564L: '\xf8', 4286565L: 'V', 4286566L: '\x03', 4286567L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL 0x44bf60', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_20(self):
''' Instruction CALL 0x404040 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051336L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219775L, 'RBP': 7051232L}, 'memory': {4219776L: '\xbc', 4219777L: '\xdc', 4219778L: '\xff', 4219779L: '\xff', 140737488345815L: '\x00', 140737488345816L: '\x00', 140737488345817L: '\x00', 140737488345818L: '\x00', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00', 140737488345824L: '\x00', 140737488345825L: '\x00', 140737488345826L: '\x00', 140737488345827L: '\x00', 140737488345828L: '\x00', 140737488345829L: '\x00', 140737488345830L: '\x00', 140737488345831L: '\x00', 140737488345832L: '\x00', 4219775L: '\xe8'}}, 'text': '\xe8\xbc\xdc\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051336L, 'RSP': 140737488345816L, 'RDX': 2L, 'RIP': 4210752L, 'RBP': 7051232L}, 'memory': {4219776L: '\xbc', 4219777L: '\xdc', 4219778L: '\xff', 4219779L: '\xff', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\x84', 140737488345817L: 'c', 140737488345818L: '@', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00', 140737488345824L: '\x00', 140737488345825L: '\x00', 140737488345826L: '\x00', 140737488345827L: '\x00', 140737488345828L: '\x00', 140737488345829L: '\x00', 140737488345830L: '\x00', 140737488345831L: '\x00', 140737488345832L: '\x00', 4219775L: '\xe8'}}, 'disassembly': 'CALL 0x404040', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_21(self):
''' Instruction CALL 0x400f30 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 0L, 'RDI': 7049240L, 'RAX': 18446744073709551600L, 'RSP': 140737488346208L, 'RDX': 0L, 'RIP': 4198591L, 'RBP': 0L}, 'memory': {4198591L: '\xe8', 4198592L: 'l', 4198593L: '\xfe', 4198594L: '\xff', 4198595L: '\xff', 140737488346199L: '\x00', 140737488346200L: '\xea', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00'}}, 'text': '\xe8l\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 0L, 'RDI': 7049240L, 'RAX': 18446744073709551600L, 'RSP': 140737488346200L, 'RDX': 0L, 'RIP': 4198192L, 'RBP': 0L}, 'memory': {4198591L: '\xe8', 4198592L: 'l', 4198593L: '\xfe', 4198594L: '\xff', 4198595L: '\xff', 140737488346191L: '\x00', 140737488346192L: 'h', 140737488346193L: '\xdd', 140737488346194L: '\xff', 140737488346195L: '\xff', 140737488346196L: '\xff', 140737488346197L: '\x7f', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xc4', 140737488346201L: '\x10', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00'}}, 'disassembly': 'CALL 0x400f30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_22(self):
''' Instruction CALL 0x4090b0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4329920L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 4329920L: '\xe8', 4329921L: '\xeb', 4329922L: '~', 4329923L: '\xfe', 4329924L: '\xff', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca'}}, 'text': '\xe8\xeb~\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 30L, 'RIP': 4231344L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 4329920L: '\xe8', 4329921L: '\xeb', 4329922L: '~', 4329923L: '\xfe', 4329924L: '\xff', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca'}}, 'disassembly': 'CALL 0x4090b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_23(self):
''' Instruction CALL 0x417430 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 34L, 'RSI': 4096L, 'RDI': 0L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 3L, 'RIP': 4661233L, 'RBP': 4096L}, 'memory': {140737488343959L: '\x00', 140737488343960L: '\x84', 140737488343961L: ' ', 140737488343962L: 'G', 140737488343963L: '\x00', 140737488343964L: '\x00', 140737488343965L: '\x00', 140737488343966L: '\x00', 140737488343967L: '\x00', 140737488343968L: '\x05', 140737488343969L: '\x00', 140737488343970L: '\x00', 140737488343971L: '\x00', 140737488343972L: '\x00', 140737488343973L: '\x00', 140737488343974L: '\x00', 140737488343975L: '\x00', 140737488343976L: '\x05', 4661233L: '\xe8', 4661234L: ':', 4661235L: 'T', 4661236L: '\xfa', 4661237L: '\xff'}}, 'text': '\xe8:T\xfa\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 34L, 'RSI': 4096L, 'RDI': 0L, 'RAX': 4096L, 'RSP': 140737488343960L, 'RDX': 3L, 'RIP': 4289584L, 'RBP': 4096L}, 'memory': {140737488343951L: '\x00', 140737488343952L: '\x00', 140737488343953L: '\x00', 140737488343954L: '\x00', 140737488343955L: '\x00', 140737488343956L: '\x00', 140737488343957L: '\x00', 140737488343958L: '\x00', 140737488343959L: '\x00', 140737488343960L: '\xf6', 140737488343961L: '\x1f', 140737488343962L: 'G', 140737488343963L: '\x00', 140737488343964L: '\x00', 140737488343965L: '\x00', 140737488343966L: '\x00', 140737488343967L: '\x00', 140737488343968L: '\x05', 140737488343969L: '\x00', 140737488343970L: '\x00', 140737488343971L: '\x00', 140737488343972L: '\x00', 140737488343973L: '\x00', 140737488343974L: '\x00', 140737488343975L: '\x00', 140737488343976L: '\x05', 4661233L: '\xe8', 4661234L: ':', 4661235L: 'T', 4661236L: '\xfa', 4661237L: '\xff'}}, 'disassembly': 'CALL 0x417430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_24(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '$', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '$', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_25(self):
''' Instruction CALL 0x401210 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346176L, 'RDX': 79L, 'RIP': 4195681L, 'RBP': 140737488346224L}, 'memory': {140737488346167L: '\x00', 140737488346168L: 'Z', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4195681L: '\xe8', 4195682L: '\xaa', 4195683L: '\x0c', 4195684L: '\x00', 4195685L: '\x00'}}, 'text': '\xe8\xaa\x0c\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4198928L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'f', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4195681L: '\xe8', 4195682L: '\xaa', 4195683L: '\x0c', 4195684L: '\x00', 4195685L: '\x00'}}, 'disassembly': 'CALL 0x401210', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_26(self):
''' Instruction CALL 0x41edb0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283909L, 'RBP': 3L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'text': '\xe8\xa6\x8f\x00\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 3L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'CALL 0x41edb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_27(self):
''' Instruction CALL 0x419c30 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346184L, 'RDX': 12297829382473034411L, 'RIP': 4399977L, 'RBP': 1L}, 'memory': {140737488346175L: '\x00', 140737488346176L: '\x00', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 4399977L: '\xe8', 4399978L: '\xc2', 4399979L: 'x', 4399980L: '\xfe', 4399981L: '\xff'}}, 'text': '\xe8\xc2x\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346176L, 'RDX': 12297829382473034411L, 'RIP': 4299824L, 'RBP': 1L}, 'memory': {140737488346167L: '\x00', 140737488346168L: '\x00', 140737488346169L: '\x00', 140737488346170L: '\x00', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 4399977L: '\xe8', 4399978L: '\xc2', 4399979L: 'x', 4399980L: '\xfe', 4399981L: '\xff'}}, 'disassembly': 'CALL 0x419c30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_28(self):
''' Instruction CALL 0x420880 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 21L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\x87', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\t'}}, 'text': '\xe89\xd9\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 21L, 'RAX': 21L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327552L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\t'}}, 'disassembly': 'CALL 0x420880', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_29(self):
''' Instruction CALL 0x40c340 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392882L, 'RBP': 7049504L}, 'memory': {4392882L: '\xe8', 4392883L: '\x89', 4392884L: '\xbb', 4392885L: '\xfd', 4392886L: '\xff', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'text': '\xe8\x89\xbb\xfd\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244288L, 'RBP': 7049504L}, 'memory': {4392882L: '\xe8', 4392883L: '\x89', 4392884L: '\xbb', 4392885L: '\xfd', 4392886L: '\xff', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'disassembly': 'CALL 0x40c340', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_3(self):
''' Instruction CALL 0x400dd0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 140737488346272L, 'RAX': 524288L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196206L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4196206L: '\xe8', 4196207L: ']', 4196208L: '\x06', 4196209L: '\x00', 4196210L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xe8]\x06\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 140737488346272L, 'RAX': 524288L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4197840L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4196207L: ']', 4196208L: '\x06', 4196209L: '\x00', 140737488346226L: '\x00', 4196206L: '\xe8', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 4196210L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 's', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'CALL 0x400dd0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_30(self):
''' Instruction CALL 0x40d1a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 37L, 'RDI': 4783048L, 'RAX': 2147483619L, 'RSP': 140737488344256L, 'RDX': 28L, 'RIP': 4336221L, 'RBP': 140737488345936L}, 'memory': {140737488344247L: '\xff', 140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'text': '\xe8>\xa7\xfe\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 37L, 'RDI': 4783048L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247968L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'disassembly': 'CALL 0x40d1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_31(self):
''' Instruction CALL 0x48e270 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7049240L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4195548L, 'RBP': 140737488346144L}, 'memory': {140737488346135L: '\x00', 140737488346136L: 'P', 140737488346137L: '\x00', 140737488346138L: '\x00', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 4195548L: '\xe8', 4195549L: '\x8f', 4195550L: '\xdd', 4195551L: '\x08', 4195552L: '\x00'}}, 'text': '\xe8\x8f\xdd\x08\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7049240L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 140737488346512L, 'RIP': 4776560L, 'RBP': 140737488346144L}, 'memory': {140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: '\x04', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 4195548L: '\xe8', 4195549L: '\x8f', 4195550L: '\xdd', 4195551L: '\x08', 4195552L: '\x00'}}, 'disassembly': 'CALL 0x48e270', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_32(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346128L, 'RDX': 78L, 'RIP': 4199106L, 'RBP': 4782912L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 7041732: '\x00', 7041782: '\x00', 7041772: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 4199106L: '\xff', 4199107L: 'P', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041730: 'C', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041752: '@', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041731: '\x00', 7041783: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392432L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4199106L: '\xff', 4199107L: 'P', 7041732: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_33(self):
''' Instruction CALL 0x420880 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\x87', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\x04'}}, 'text': '\xe89\xd9\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327552L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\x04'}}, 'disassembly': 'CALL 0x420880', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_34(self):
''' Instruction CALL 0x401210 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 18L, 'RSP': 140737488346176L, 'RDX': 7059408L, 'RIP': 4195669L, 'RBP': 140737488346224L}, 'memory': {140737488346167L: '\x00', 140737488346168L: 'N', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4195669L: '\xe8', 4195670L: '\xb6', 4195671L: '\x0c', 4195672L: '\x00', 4195673L: '\x00'}}, 'text': '\xe8\xb6\x0c\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 18L, 'RSP': 140737488346168L, 'RDX': 7059408L, 'RIP': 4198928L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'Z', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4195669L: '\xe8', 4195670L: '\xb6', 4195671L: '\x0c', 4195672L: '\x00', 4195673L: '\x00'}}, 'disassembly': 'CALL 0x401210', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_35(self):
''' Instruction CALL 0x40c340 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392882L, 'RBP': 7049504L}, 'memory': {4392882L: '\xe8', 4392883L: '\x89', 4392884L: '\xbb', 4392885L: '\xfd', 4392886L: '\xff', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'text': '\xe8\x89\xbb\xfd\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244288L, 'RBP': 7049504L}, 'memory': {4392882L: '\xe8', 4392883L: '\x89', 4392884L: '\xbb', 4392885L: '\xfd', 4392886L: '\xff', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'disassembly': 'CALL 0x40c340', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_36(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_37(self):
''' Instruction CALL 0x41f430 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7065432L, 'RSP': 140737488346128L, 'RDX': 7074288L, 'RIP': 4297621L, 'RBP': 140737488346472L}, 'memory': {140737488346134L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'z', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 4297622L: '\x96', 140737488346135L: '\x00', 140737488346136L: 'P', 4297625L: '\x00', 4297623L: '`', 4297624L: '\x00', 4297621L: '\xe8'}}, 'text': '\xe8\x96`\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7065432L, 'RSP': 140737488346120L, 'RDX': 7074288L, 'RIP': 4322352L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: 'h', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346134L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x9a', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 4297622L: '\x96', 140737488346135L: '\x00', 4297624L: '\x00', 4297625L: '\x00', 140737488346117L: '\x7f', 140737488346136L: 'P', 4297623L: '`', 4297621L: '\xe8', 140737488346111L: '\x00'}}, 'disassembly': 'CALL 0x41f430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_38(self):
''' Instruction CALL 0x415d70 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346048L, 'RDX': 140737488346078L, 'RIP': 4284505L, 'RBP': 188L}, 'memory': {140737488346039L: '\x00', 140737488346040L: '\xd0', 140737488346041L: '\xf1', 140737488346042L: 'k', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 4284505L: '\xe8', 4284506L: '\x12', 4284507L: '\xfd', 4284508L: '\xff', 4284509L: '\xff'}}, 'text': '\xe8\x12\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346040L, 'RDX': 140737488346078L, 'RIP': 4283760L, 'RBP': 188L}, 'memory': {140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 4284505L: '\xe8', 4284506L: '\x12', 4284507L: '\xfd', 4284508L: '\xff', 4284509L: '\xff'}}, 'disassembly': 'CALL 0x415d70', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_39(self):
''' Instruction CALL 0x415d70 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488346048L, 'RDX': 140737488346078L, 'RIP': 4284525L, 'RBP': 194L}, 'memory': {140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 4284525L: '\xe8', 4284526L: '\xfe', 4284527L: '\xfc', 4284528L: '\xff', 4284529L: '\xff'}}, 'text': '\xe8\xfe\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488346040L, 'RDX': 140737488346078L, 'RIP': 4283760L, 'RBP': 194L}, 'memory': {140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 4284525L: '\xe8', 4284526L: '\xfe', 4284527L: '\xfc', 4284528L: '\xff', 4284529L: '\xff'}}, 'disassembly': 'CALL 0x415d70', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_4(self):
''' Instruction CALL 0x40b0e0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 18L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4198955L, 'RBP': 4782912L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4198955L: '\xe8', 4198956L: '\xb0', 4198957L: '\x9e', 4198958L: '\x00', 4198959L: '\x00'}}, 'text': '\xe8\xb0\x9e\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 18L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239584L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4198955L: '\xe8', 4198956L: '\xb0', 4198957L: '\x9e', 4198958L: '\x00', 4198959L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL 0x40b0e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_40(self):
''' Instruction CALL 0x41f430 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 7065352L, 'RSP': 140737488346128L, 'RDX': 50859318435822L, 'RIP': 4297545L, 'RBP': 140737488346472L}, 'memory': {140737488346119L: '\x00', 140737488346120L: 'h', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4297545L: '\xe8', 4297546L: '\xe2', 4297547L: '`', 4297548L: '\x00', 4297549L: '\x00'}}, 'text': '\xe8\xe2`\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 7065352L, 'RSP': 140737488346120L, 'RDX': 50859318435822L, 'RIP': 4322352L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'N', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4297545L: '\xe8', 4297546L: '\xe2', 4297547L: '`', 4297548L: '\x00', 4297549L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL 0x41f430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_41(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346128L, 'RDX': 78L, 'RIP': 4199106L, 'RBP': 4782912L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 7041732: '\x00', 7041782: '\x00', 7041772: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 4199106L: '\xff', 4199107L: 'P', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041730: 'C', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041752: '@', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041731: '\x00', 7041783: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392432L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4199106L: '\xff', 4199107L: 'P', 7041732: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_42(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x08', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x08', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_43(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x02', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x02', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_44(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_45(self):
''' Instruction CALL 0x420880 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\xc6'}}, 'text': '\xe89\xd9\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327552L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\xc6'}}, 'disassembly': 'CALL 0x420880', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_46(self):
''' Instruction CALL 0x436330 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1685382481L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4291398L, 'RBP': 140737488347312L}, 'memory': {140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x04', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 4291398L: '\xe8', 4291399L: '\xe5', 4291400L: '\xe7', 4291401L: '\x01', 4291402L: '\x00'}}, 'text': '\xe8\xe5\xe7\x01\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1685382481L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416304L, 'RBP': 140737488347312L}, 'memory': {140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'K', 140737488346169L: '{', 140737488346170L: 'A', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 4291398L: '\xe8', 4291399L: '\xe5', 4291400L: '\xe7', 4291401L: '\x01', 4291402L: '\x00', 140737488346184L: '\x04'}}, 'disassembly': 'CALL 0x436330', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_47(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_48(self):
''' Instruction CALL 0x416820 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 135168L, 'RAX': 1L, 'RSP': 140737488345808L, 'RDX': 131136L, 'RIP': 4239556L, 'RBP': 7051232L}, 'memory': {140737488345799L: '\x00', 140737488345800L: '\x00', 4239556L: '\xe8', 4239557L: 'W', 4239558L: '\xb7', 4239559L: '\x00', 4239560L: '\x00', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '('}}, 'text': '\xe8W\xb7\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 135168L, 'RAX': 1L, 'RSP': 140737488345800L, 'RDX': 131136L, 'RIP': 4286496L, 'RBP': 7051232L}, 'memory': {140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\xc9', 140737488345791L: '\x00', 140737488345792L: '\x07', 140737488345793L: '\x00', 140737488345794L: '\x00', 140737488345795L: '\x00', 4239556L: '\xe8', 4239557L: 'W', 4239558L: '\xb7', 4239559L: '\x00', 4239560L: '\x00', 140737488345801L: '\xb0', 140737488345802L: '@', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '('}}, 'disassembly': 'CALL 0x416820', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_49(self):
''' Instruction CALL 0x4190d0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346976L, 'RAX': 0L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195980L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4195980L: '\xe8', 4195981L: '?', 4195982L: '\x8a', 4195983L: '\x01', 4195984L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\x00', 140737488346233L: '\x00', 140737488346234L: '\x00', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xe8?\x8a\x01\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346976L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 140737488346456L, 'RIP': 4296912L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4195980L: '\xe8', 4195981L: '?', 4195982L: '\x8a', 4195983L: '\x01', 4195984L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\x91', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'CALL 0x4190d0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_5(self):
''' Instruction CALL 0x415d70 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346048L, 'RDX': 140737488346078L, 'RIP': 4284505L, 'RBP': 194L}, 'memory': {140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 4284505L: '\xe8', 4284506L: '\x12', 4284507L: '\xfd', 4284508L: '\xff', 4284509L: '\xff'}}, 'text': '\xe8\x12\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346040L, 'RDX': 140737488346078L, 'RIP': 4283760L, 'RBP': 194L}, 'memory': {140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 4284505L: '\xe8', 4284506L: '\x12', 4284507L: '\xfd', 4284508L: '\xff', 4284509L: '\xff'}}, 'disassembly': 'CALL 0x415d70', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_50(self):
''' Instruction CALL 0x4750a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488343888L, 'RDI': 1L, 'RAX': 4294967161L, 'RSP': 140737488343888L, 'RDX': 1L, 'RIP': 4673671L, 'RBP': 18446744073709551568L}, 'memory': {4673671L: '\xe8', 4673672L: '\x14', 4673673L: '\x00', 4673674L: '\x00', 4673675L: '\x00', 140737488343879L: '\x00', 140737488343880L: '\x00', 140737488343881L: '\x00', 140737488343882L: '\x00', 140737488343883L: '\x00', 140737488343884L: '\x00', 140737488343885L: '\x00', 140737488343886L: '\x00', 140737488343887L: '\x00', 140737488343888L: '\x00', 140737488343889L: '\x00', 140737488343890L: '\x00', 140737488343891L: '\x00', 140737488343892L: '\x00', 140737488343893L: '\x00', 140737488343894L: '\x00', 140737488343895L: '\x00', 140737488343896L: '\x00'}}, 'text': '\xe8\x14\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488343888L, 'RDI': 1L, 'RAX': 4294967161L, 'RSP': 140737488343880L, 'RDX': 1L, 'RIP': 4673696L, 'RBP': 18446744073709551568L}, 'memory': {4673671L: '\xe8', 4673672L: '\x14', 4673673L: '\x00', 4673674L: '\x00', 4673675L: '\x00', 140737488343871L: '\x00', 140737488343872L: '\x00', 140737488343873L: '\x00', 140737488343874L: '\x00', 140737488343875L: '\x00', 140737488343876L: '\x00', 140737488343877L: '\x00', 140737488343878L: '\x00', 140737488343879L: '\x00', 140737488343880L: '\x8c', 140737488343881L: 'P', 140737488343882L: 'G', 140737488343883L: '\x00', 140737488343884L: '\x00', 140737488343885L: '\x00', 140737488343886L: '\x00', 140737488343887L: '\x00', 140737488343888L: '\x00', 140737488343889L: '\x00', 140737488343890L: '\x00', 140737488343891L: '\x00', 140737488343892L: '\x00', 140737488343893L: '\x00', 140737488343894L: '\x00', 140737488343895L: '\x00', 140737488343896L: '\x00'}}, 'disassembly': 'CALL 0x4750a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_51(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_52(self):
''' Instruction CALL 0x416000 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 13L, 'RDI': 194L, 'RAX': 32768L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284892L, 'RBP': 32768L}, 'memory': {140737488346135L: '\x00', 140737488346136L: '\xd1', 140737488346137L: 'a', 140737488346138L: 'A', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x00', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x04', 4284892L: '\xe8', 4284893L: '\x1f', 4284894L: '\xfe', 4284895L: '\xff', 4284896L: '\xff'}}, 'text': '\xe8\x1f\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 13L, 'RDI': 194L, 'RAX': 32768L, 'RSP': 140737488346136L, 'RDX': 64L, 'RIP': 4284416L, 'RBP': 32768L}, 'memory': {140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: 'a', 140737488346138L: 'A', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x00', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x04', 4284892L: '\xe8', 4284893L: '\x1f', 4284894L: '\xfe', 4284895L: '\xff', 4284896L: '\xff'}}, 'disassembly': 'CALL 0x416000', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_53(self):
''' Instruction CALL 0x400430 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346160L, 'RDX': 7058304L, 'RIP': 4782860L, 'RBP': 7049240L}, 'memory': {4782860L: '\xe8', 4782861L: '\x1f', 4782862L: '\t', 4782863L: '\xf7', 4782864L: '\xff', 140737488346151L: '\x00', 140737488346152L: '\x00', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1'}}, 'text': '\xe8\x1f\t\xf7\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346152L, 'RDX': 7058304L, 'RIP': 4195376L, 'RBP': 7049240L}, 'memory': {4782860L: '\xe8', 4782861L: '\x1f', 4782862L: '\t', 4782863L: '\xf7', 4782864L: '\xff', 140737488346143L: '\x00', 140737488346144L: 'p', 140737488346145L: '\xdc', 140737488346146L: '\xff', 140737488346147L: '\xff', 140737488346148L: '\xff', 140737488346149L: '\x7f', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x11', 140737488346153L: '\xfb', 140737488346154L: 'H', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1'}}, 'disassembly': 'CALL 0x400430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_54(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346128L, 'RDX': 78L, 'RIP': 4199106L, 'RBP': 4782912L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 7041732: '\x00', 7041782: '\x00', 7041772: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 4199106L: '\xff', 4199107L: 'P', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041730: 'C', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041752: '@', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041731: '\x00', 7041783: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392432L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4199106L: '\xff', 4199107L: 'P', 7041732: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_55(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_56(self):
''' Instruction CALL 0x41edb0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283909L, 'RBP': 9L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'text': '\xe8\xa6\x8f\x00\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'CALL 0x41edb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_57(self):
''' Instruction CALL 0x420880 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 43L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\xc0'}}, 'text': '\xe89\xd9\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 43L, 'RAX': 43L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327552L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\xc0'}}, 'disassembly': 'CALL 0x420880', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_58(self):
''' Instruction CALL 0x40c340 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392882L, 'RBP': 7049504L}, 'memory': {4392882L: '\xe8', 4392883L: '\x89', 4392884L: '\xbb', 4392885L: '\xfd', 4392886L: '\xff', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'text': '\xe8\x89\xbb\xfd\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244288L, 'RBP': 7049504L}, 'memory': {4392882L: '\xe8', 4392883L: '\x89', 4392884L: '\xbb', 4392885L: '\xfd', 4392886L: '\xff', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'disassembly': 'CALL 0x40c340', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_59(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346128L, 'RDX': 78L, 'RIP': 4199106L, 'RBP': 4782912L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 7041732: '\x00', 7041782: '\x00', 7041772: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 4199106L: '\xff', 4199107L: 'P', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041730: 'C', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041752: '@', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041731: '\x00', 7041783: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392432L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4199106L: '\xff', 4199107L: 'P', 7041732: '\x00', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 4199108L: '8', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 7041736: '0', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_6(self):
''' Instruction CALL 0x44bf60 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 131136L, 'RIP': 4286563L, 'RBP': 135168L}, 'memory': {140737488345767L: '\x00', 140737488345768L: 'q', 140737488345769L: ':', 140737488345770L: 'J', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '8', 140737488345777L: '\x98', 140737488345778L: 'k', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\xe0', 4286563L: '\xe8', 4286564L: '\xf8', 4286565L: 'V', 4286566L: '\x03', 4286567L: '\x00'}}, 'text': '\xe8\xf8V\x03\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345768L, 'RDX': 131136L, 'RIP': 4505440L, 'RBP': 135168L}, 'memory': {140737488345759L: '\x00', 140737488345760L: '\x00', 140737488345761L: '\x00', 140737488345762L: '\x00', 140737488345763L: '\x00', 140737488345764L: '\x00', 140737488345765L: '\x00', 140737488345766L: '\x00', 140737488345767L: '\x00', 140737488345768L: 'h', 140737488345769L: 'h', 140737488345770L: 'A', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '8', 140737488345777L: '\x98', 140737488345778L: 'k', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\xe0', 4286563L: '\xe8', 4286564L: '\xf8', 4286565L: 'V', 4286566L: '\x03', 4286567L: '\x00'}}, 'disassembly': 'CALL 0x44bf60', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_60(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336944L, 'RBP': 140737488345936L}, 'memory': {7041728: '\xd0', 7041771: '\x00', 7041729: '\x02', 7041751: '\x00', 7041736: '0', 7041730: 'C', 7041783: '\x00', 7041731: '\x00', 7041732: '\x00', 7041775: '\x00', 7041733: '\x00', 7041776: '\x00', 7041734: '\x00', 7041735: '\x00', 7041757: '\x00', 4336944L: '\xff', 4336945L: 'P', 4336946L: '8', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x01', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041720: '\xf0', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041721: '\x05', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041722: 'C', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041723: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041745: '&', 7041768: '`', 7041724: '\x00', 7041770: 'G', 7041767: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041725: '\x00', 7041763: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041726: '\x00', 7041782: '\x00', 7041769: '\x1f', 140737488344255L: '\x00', 7041781: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4392432L, 'RBP': 140737488345936L}, 'memory': {140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 7041732: '\x00', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x01', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041736: '0', 4336944L: '\xff', 4336945L: 'P', 4336946L: '8'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_61(self):
''' Instruction CALL 0x40b0e0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4198955L, 'RBP': 4782912L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4198955L: '\xe8', 4198956L: '\xb0', 4198957L: '\x9e', 4198958L: '\x00', 4198959L: '\x00'}}, 'text': '\xe8\xb0\x9e\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239584L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4198955L: '\xe8', 4198956L: '\xb0', 4198957L: '\x9e', 4198958L: '\x00', 4198959L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL 0x40b0e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_62(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '+', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '+', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_63(self):
''' Instruction CALL QWORD [RBX-0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4195080L, 'RDI': 6L, 'RAX': 4465680L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197581L, 'RBP': 12L}, 'memory': {4195072: ' ', 4195073: 'g', 4195074: 'C', 4195075: '\x00', 4195076: '\x00', 4195077: '\x00', 4195078: '\x00', 4195079: '\x00', 4195080: 'H', 4195081: '\x83', 4195082: '\xec', 4195083: '\x08', 4195084: '\xe8', 4195085: '\xfb', 4195086: '\x00', 4195087: '\x00', 4195088: '\x00', 4195089: '\xe8', 4195090: '\xaa', 4195091: '\x01', 4195092: '\x00', 4195093: '\x00', 4195094: '\xe8', 4195095: '\x05', 4195096: '\xeb', 4195097: '\x08', 4195098: '\x00', 4195099: 'H', 4195100: '\x83', 4195101: '\xc4', 4195102: '\x08', 4195103: '\xc3', 4195104: '\xff', 4195105: '%', 4195106: '\xba', 4195107: '\x85', 4195108: '+', 4195109: '\x00', 4195110: 'h', 4195111: '\x00', 4195112: '\x00', 4195113: '\x00', 4195114: '\x00', 4195115: '\xe9', 4195116: '\x00', 4195117: '\x00', 4195118: '\x00', 4195119: '\x00', 4195120: '\xff', 4195121: '%', 4195122: '\xb2', 4195123: '\x85', 4195124: '+', 4195125: '\x00', 4195126: 'h', 4195127: '\x00', 4195128: '\x00', 4195129: '\x00', 4195130: '\x00', 4195131: '\xe9', 4195132: '\x00', 4195133: '\x00', 4195134: '\x00', 4195135: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4197583L: '\xf8', 4197582L: 'S', 4197581L: '\xff'}}, 'text': '\xffS\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4465680L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4417312L, 'RBP': 12L}, 'memory': {140737488346175L: '\x00', 140737488346176L: '\xc0', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4197581L: '\xff', 4197582L: 'S', 4197583L: '\xf8', 4195072: ' ', 4195073: 'g', 4195074: 'C', 4195075: '\x00', 4195076: '\x00', 4195077: '\x00', 4195078: '\x00', 4195079: '\x00', 4195080: 'H', 4195081: '\x83', 4195082: '\xec', 4195083: '\x08', 4195084: '\xe8', 4195085: '\xfb', 4195086: '\x00', 4195087: '\x00', 4195088: '\x00', 4195089: '\xe8', 4195090: '\xaa', 4195091: '\x01', 4195092: '\x00', 4195093: '\x00', 4195094: '\xe8', 4195095: '\x05', 4195096: '\xeb', 4195097: '\x08', 4195098: '\x00', 4195099: 'H', 4195100: '\x83', 4195101: '\xc4', 4195102: '\x08', 4195103: '\xc3', 4195104: '\xff', 4195105: '%', 4195106: '\xba', 4195107: '\x85', 4195108: '+', 4195109: '\x00', 4195110: 'h', 4195111: '\x00', 4195112: '\x00', 4195113: '\x00', 4195114: '\x00', 4195115: '\xe9', 4195116: '\x00', 4195117: '\x00', 4195118: '\x00', 4195119: '\x00', 4195120: '\xff', 4195121: '%', 4195122: '\xb2', 4195123: '\x85', 4195124: '+', 4195125: '\x00', 4195126: 'h', 4195127: '\x00', 4195128: '\x00', 4195129: '\x00', 4195130: '\x00', 4195131: '\xe9', 4195132: '\x00', 4195133: '\x00', 4195134: '\x00', 4195135: '\x00'}}, 'disassembly': 'CALL QWORD [RBX-0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_64(self):
''' Instruction CALL 0x40040c '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346160L, 'RDX': 140737488346512L, 'RIP': 4195084L, 'RBP': 4L}, 'memory': {4195084L: '\xe8', 4195085L: '\xfb', 4195086L: '\x00', 4195087L: '\x00', 4195088L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x04', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B'}}, 'text': '\xe8\xfb\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346152L, 'RDX': 140737488346512L, 'RIP': 4195340L, 'RBP': 4L}, 'memory': {4195084L: '\xe8', 4195085L: '\xfb', 4195086L: '\x00', 4195087L: '\x00', 4195088L: '\x00', 140737488346143L: '\x00', 140737488346144L: '0', 140737488346145L: '\xe8', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x11', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B'}}, 'disassembly': 'CALL 0x40040c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_65(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'Z', 140737488345913: '\x03', 140737488345914: 'v', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_66(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_67(self):
''' Instruction CALL QWORD [RAX+0x60] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4203859L, 'RBP': 0L}, 'memory': {7041792: '`', 7041793: '\xfd', 7041794: 'B', 7041795: '\x00', 7041796: '\x00', 7041797: '\x00', 7041798: '\x00', 7041799: '\x00', 7041800: '\xb0', 7041801: '\x08', 7041802: 'C', 7041803: '\x00', 7041804: '\x00', 7041805: '\x00', 7041806: '\x00', 7041807: '\x00', 7041808: '\xf0', 7041809: '\x08', 7041810: 'C', 7041811: '\x00', 7041812: '\x00', 7041813: '\x00', 7041814: '\x00', 7041815: '\x00', 7041816: '\x90', 7041817: '4', 7041818: '@', 7041819: '\x00', 7041820: '\x00', 7041821: '\x00', 7041822: '\x00', 7041823: '\x00', 7041791: '\x00', 7041779: '\x00', 7041787: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x00', 140737488346057L: '\x00', 140737488346058L: '\x00', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 140737488346065L: '\x91', 140737488346066L: 'k', 4203859L: '\xff', 4203860L: 'P', 4203861L: '`', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\x01', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 140737488346067L: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041784: '\x10', 140737488346068L: '\x00', 7041786: 'C', 7041785: '\x08', 7041788: '\x00', 7041789: '\x00', 7041790: '\x00', 140737488346069L: '\x00'}}, 'text': '\xffP`', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4394944L, 'RBP': 0L}, 'memory': {7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041784: '\x10', 7041785: '\x08', 7041786: 'C', 7041787: '\x00', 7041788: '\x00', 7041789: '\x00', 7041790: '\x00', 7041791: '\x00', 7041792: '`', 7041793: '\xfd', 7041794: 'B', 7041795: '\x00', 7041796: '\x00', 7041797: '\x00', 7041798: '\x00', 7041799: '\x00', 7041800: '\xb0', 7041801: '\x08', 7041802: 'C', 7041803: '\x00', 7041804: '\x00', 7041805: '\x00', 7041806: '\x00', 7041807: '\x00', 7041808: '\xf0', 7041809: '\x08', 7041810: 'C', 7041811: '\x00', 7041812: '\x00', 7041813: '\x00', 7041814: '\x00', 7041815: '\x00', 7041816: '\x90', 7041817: '4', 7041818: '@', 7041819: '\x00', 7041820: '\x00', 7041821: '\x00', 7041822: '\x00', 7041823: '\x00', 4203859L: '\xff', 4203860L: 'P', 4203861L: '`', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 140737488346065L: '\x91', 140737488346066L: 'k', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\x01'}}, 'disassembly': 'CALL QWORD [RAX+0x60]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_68(self):
''' Instruction CALL 0x400308 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197693L, 'RBP': 4L}, 'memory': {140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'K', 140737488346169L: '{', 140737488346170L: 'A', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 4197695L: '\xf5', 4197696L: '\xff', 4197697L: '\xff', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4197693L: '\xe8', 4197694L: '\xc6', 140737488346175L: '\x00'}}, 'text': '\xe8\xc6\xf5\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4195080L, 'RBP': 4L}, 'memory': {140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B', 140737488346169L: '\r', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 4197696L: '\xff', 4197697L: '\xff', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4197693L: '\xe8', 4197694L: '\xc6', 4197695L: '\xf5'}}, 'disassembly': 'CALL 0x400308', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_69(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336944L, 'RBP': 140737488345936L}, 'memory': {7041728: '\xd0', 7041771: '\x00', 7041729: '\x02', 7041751: '\x00', 7041736: '0', 7041730: 'C', 7041783: '\x00', 7041731: '\x00', 7041732: '\x00', 7041775: '\x00', 7041733: '\x00', 7041776: '\x00', 7041734: '\x00', 7041735: '\x00', 7041757: '\x00', 4336944L: '\xff', 4336945L: 'P', 4336946L: '8', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041720: '\xf0', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041721: '\x05', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041722: 'C', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041723: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041745: '&', 7041768: '`', 7041724: '\x00', 7041770: 'G', 7041767: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041725: '\x00', 7041763: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041726: '\x00', 7041782: '\x00', 7041769: '\x1f', 140737488344255L: '\x00', 7041781: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4392432L, 'RBP': 140737488345936L}, 'memory': {140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 7041732: '\x00', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041736: '0', 4336944L: '\xff', 4336945L: 'P', 4336946L: '8'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_7(self):
''' Instruction CALL 0x401210 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 32L, 'RSP': 140737488346176L, 'RDX': 7059408L, 'RIP': 4195781L, 'RBP': 140737488346224L}, 'memory': {140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346167L: '\x00', 140737488346168L: '\xbe', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 4195781L: '\xe8', 4195782L: 'F', 4195783L: '\x0c', 4195784L: '\x00', 4195785L: '\x00'}}, 'text': '\xe8F\x0c\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 32L, 'RSP': 140737488346168L, 'RDX': 7059408L, 'RIP': 4198928L, 'RBP': 140737488346224L}, 'memory': {140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xca', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 4195781L: '\xe8', 4195782L: 'F', 4195783L: '\x0c', 4195784L: '\x00', 4195785L: '\x00', 140737488346184L: '\x90'}}, 'disassembly': 'CALL 0x401210', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_70(self):
''' Instruction CALL 0x4090b0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4329920L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 4329920L: '\xe8', 4329921L: '\xeb', 4329922L: '~', 4329923L: '\xfe', 4329924L: '\xff', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1'}}, 'text': '\xe8\xeb~\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 5L, 'RIP': 4231344L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 4329920L: '\xe8', 4329921L: '\xeb', 4329922L: '~', 4329923L: '\xfe', 4329924L: '\xff', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1'}}, 'disassembly': 'CALL 0x4090b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_71(self):
''' Instruction CALL 0x41edb0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283909L, 'RBP': 3L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'text': '\xe8\xa6\x8f\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 3L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'CALL 0x41edb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_72(self):
''' Instruction CALL 0x41f430 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 7065440L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297581L, 'RBP': 140737488346472L}, 'memory': {140737488346119L: '\x00', 140737488346120L: 'N', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4297581L: '\xe8', 4297582L: '\xbe', 4297583L: '`', 4297584L: '\x00', 4297585L: '\x00'}}, 'text': '\xe8\xbe`\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 7065440L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4322352L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'r', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4297581L: '\xe8', 4297582L: '\xbe', 4297583L: '`', 4297584L: '\x00', 4297585L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'CALL 0x41f430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_73(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_74(self):
''' Instruction CALL 0x4090b0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 2147483642L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4329908L, 'RBP': 140737488345936L}, 'memory': {4329908L: '\xe8', 4329909L: '\xf7', 4329910L: '~', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1', 4329911L: '\xfe', 4329912L: '\xff'}}, 'text': '\xe8\xf7~\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 2147483642L, 'RSP': 140737488344248L, 'RDX': 5L, 'RIP': 4231344L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 4329910L: '~', 140737488344247L: '\xff', 4329912L: '\xff', 4329908L: '\xe8', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 4329909L: '\xf7', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1', 4329911L: '\xfe', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344255L: '\x00', 140737488344246L: '\xff'}}, 'disassembly': 'CALL 0x4090b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_75(self):
''' Instruction CALL 0x416820 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 7213056L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239556L, 'RBP': 7051232L}, 'memory': {140737488345799L: '\x00', 140737488345800L: '\xc9', 4239556L: '\xe8', 4239557L: 'W', 4239558L: '\xb7', 4239559L: '\x00', 4239560L: '\x00', 140737488345801L: '\xb0', 140737488345802L: '@', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\xa1'}}, 'text': '\xe8W\xb7\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 7213056L, 'RSP': 140737488345800L, 'RDX': 0L, 'RIP': 4286496L, 'RBP': 7051232L}, 'memory': {140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\xc9', 140737488345791L: '\x00', 140737488345792L: '8', 140737488345793L: '\x98', 140737488345794L: 'k', 140737488345795L: '\x00', 4239556L: '\xe8', 4239557L: 'W', 4239558L: '\xb7', 4239559L: '\x00', 4239560L: '\x00', 140737488345801L: '\xb0', 140737488345802L: '@', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\xa1'}}, 'disassembly': 'CALL 0x416820', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_76(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_77(self):
''' Instruction CALL 0x41edb0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283909L, 'RBP': 9L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'text': '\xe8\xa6\x8f\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'CALL 0x41edb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_78(self):
''' Instruction CALL 0x4004c0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 140737488346512L, 'RIP': 4195089L, 'RBP': 4L}, 'memory': {4195089L: '\xe8', 4195090L: '\xaa', 4195091L: '\x01', 4195092L: '\x00', 4195093L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x11', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B'}}, 'text': '\xe8\xaa\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 140737488346512L, 'RIP': 4195520L, 'RBP': 4L}, 'memory': {4195089L: '\xe8', 4195090L: '\xaa', 4195091L: '\x01', 4195092L: '\x00', 4195093L: '\x00', 140737488346143L: '\x00', 140737488346144L: '0', 140737488346145L: '\xe8', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B'}}, 'disassembly': 'CALL 0x4004c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_79(self):
''' Instruction CALL 0x40d1a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 37L, 'RDI': 4783036L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4336221L, 'RBP': 140737488345936L}, 'memory': {140737488344247L: '\xff', 140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x01', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'text': '\xe8>\xa7\xfe\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 37L, 'RDI': 4783036L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247968L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x01', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'disassembly': 'CALL 0x40d1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_8(self):
''' Instruction CALL 0x40d1a0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 37L, 'RDI': 4782899L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4336221L, 'RBP': 140737488345936L}, 'memory': {140737488344247L: '\xff', 140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'text': '\xe8>\xa7\xfe\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 37L, 'RDI': 4782899L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247968L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 4336221L: '\xe8', 4336222L: '>', 4336223L: '\xa7', 4336224L: '\xfe', 4336225L: '\xff'}}, 'disassembly': 'CALL 0x40d1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_80(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336288L, 'RBP': 140737488345936L}, 'memory': {7041728: '\xd0', 7041771: '\x00', 7041729: '\x02', 7041751: '\x00', 7041730: 'C', 7041776: '\x00', 7041783: '\x00', 7041731: '\x00', 7041732: '\x00', 7041775: '\x00', 7041733: '\x00', 4336288L: '\xff', 4336289L: 'P', 4336290L: '8', 7041734: '\x00', 7041735: '\x00', 7041757: '\x00', 7041736: '0', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041720: '\xf0', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041721: '\x05', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041722: 'C', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041723: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041745: '&', 7041768: '`', 7041724: '\x00', 7041770: 'G', 7041767: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041725: '\x00', 7041763: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041726: '\x00', 7041782: '\x00', 7041769: '\x1f', 140737488344255L: '\x00', 7041781: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4392432L, 'RBP': 140737488345936L}, 'memory': {140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 7041732: '\x00', 7041733: '\x00', 4336288L: '\xff', 4336289L: 'P', 4336290L: '8', 7041734: '\x00', 7041735: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041736: '0'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_81(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_82(self):
''' Instruction CALL 0x401160 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4L, 'RDI': 4782991L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 4L, 'RIP': 4195730L, 'RBP': 140737488346224L}, 'memory': {4195730L: '\xe8', 4195731L: '\xc9', 4195732L: '\x0b', 4195733L: '\x00', 4195734L: '\x00', 140737488346167L: '\x00', 140737488346168L: '~', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90'}}, 'text': '\xe8\xc9\x0b\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4L, 'RDI': 4782991L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4198752L, 'RBP': 140737488346224L}, 'memory': {4195730L: '\xe8', 4195731L: '\xc9', 4195732L: '\x0b', 4195733L: '\x00', 4195734L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x97', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90'}}, 'disassembly': 'CALL 0x401160', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_83(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '@', 140737488345881L: '\x06', 140737488345882L: '\x00', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_84(self):
''' Instruction CALL QWORD [RAX+0x78] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488345936L, 'RDX': 699L, 'RIP': 4392183L, 'RBP': 7049504L}, 'memory': {7041792: '`', 7041793: '\xfd', 7041794: 'B', 7041795: '\x00', 7041796: '\x00', 7041797: '\x00', 7041798: '\x00', 7041799: '\x00', 7041800: '\xb0', 7041801: '\x08', 7041802: 'C', 7041803: '\x00', 7041804: '\x00', 7041805: '\x00', 7041806: '\x00', 7041807: '\x00', 7041808: '\xf0', 7041809: '\x08', 7041810: 'C', 7041811: '\x00', 7041812: '\x00', 7041813: '\x00', 7041814: '\x00', 7041815: '\x00', 7041816: '\x90', 7041817: '4', 7041818: '@', 7041819: '\x00', 7041820: '\x00', 7041821: '\x00', 7041822: '\x00', 7041823: '\x00', 7041824: '\xa0', 7041825: '4', 7041826: '@', 7041827: '\x00', 7041828: '\x00', 7041829: '\x00', 7041830: '\x00', 7041831: '\x00', 7041832: '\x00', 7041833: '\x00', 7041834: '\x00', 7041835: '\x00', 7041836: '\x00', 7041837: '\x00', 7041838: '\x00', 7041839: '\x00', 7041840: '\x00', 7041841: '\x00', 7041842: '\x00', 7041843: '\x00', 7041844: '\x00', 7041845: '\x00', 7041846: '\x00', 7041847: '\x00', 7041784: '\x10', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xbb', 7041787: '\x00', 4392183L: '\xff', 4392184L: 'P', 4392185L: 'x', 7041786: 'C', 7041785: '\x08', 7041788: '\x00', 7041789: '\x00', 7041790: '\x00', 7041791: '\x00'}}, 'text': '\xffPx', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488345928L, 'RDX': 699L, 'RIP': 4392976L, 'RBP': 7049504L}, 'memory': {4392183L: '\xff', 4392184L: 'P', 7041785: '\x08', 7041786: 'C', 7041787: '\x00', 7041788: '\x00', 7041789: '\x00', 7041790: '\x00', 7041791: '\x00', 7041792: '`', 7041793: '\xfd', 7041794: 'B', 7041795: '\x00', 7041796: '\x00', 7041797: '\x00', 7041798: '\x00', 7041799: '\x00', 7041800: '\xb0', 7041801: '\x08', 7041802: 'C', 7041803: '\x00', 7041804: '\x00', 7041805: '\x00', 7041806: '\x00', 7041807: '\x00', 7041808: '\xf0', 7041809: '\x08', 7041810: 'C', 7041811: '\x00', 7041812: '\x00', 7041813: '\x00', 7041814: '\x00', 7041815: '\x00', 7041816: '\x90', 7041817: '4', 7041818: '@', 7041819: '\x00', 7041820: '\x00', 7041821: '\x00', 7041822: '\x00', 7041823: '\x00', 7041824: '\xa0', 7041825: '4', 7041826: '@', 7041827: '\x00', 7041828: '\x00', 7041829: '\x00', 7041830: '\x00', 7041831: '\x00', 7041832: '\x00', 7041833: '\x00', 7041834: '\x00', 7041835: '\x00', 7041836: '\x00', 7041837: '\x00', 7041838: '\x00', 7041839: '\x00', 7041840: '\x00', 7041841: '\x00', 7041842: '\x00', 7041843: '\x00', 7041844: '\x00', 7041845: '\x00', 7041846: '\x00', 7041847: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x00', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa', 140737488345929L: '\x04', 140737488345930L: 'C', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xbb', 7041784: '\x10', 4392185L: 'x'}}, 'disassembly': 'CALL QWORD [RAX+0x78]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_85(self):
''' Instruction CALL QWORD [RIP+0x2b23ff] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 7213056L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223899L, 'RBP': 7051232L}, 'memory': {7051189: '\x00', 7051195: '\x00', 140737488345815L: '\x00', 140737488345816L: '(', 140737488345817L: 'r', 140737488345818L: '@', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00', 140737488345824L: '\x00', 140737488345825L: '\x00', 140737488345826L: '\x00', 140737488345827L: '\x00', 140737488345828L: '\x00', 140737488345829L: '\x00', 140737488345830L: '\x00', 140737488345831L: '\x00', 140737488345832L: '\x00', 7051165: '\x00', 7051168: '\xc0', 7051162: '\x00', 4223899L: '\xff', 7051164: '\x00', 4223901L: '\xff', 4223902L: '#', 4223903L: '+', 4223904L: '\x00', 7051169: '\xb0', 7051170: '@', 7051163: '\x00', 7051172: '\x00', 7051173: '\x00', 7051174: '\x00', 7051175: '\x00', 7051176: '\x00', 7051177: '\x00', 7051178: '\x00', 7051179: '\x00', 7051180: '\x00', 7051181: '\x00', 7051182: '\x00', 7051183: '\x00', 7051184: '\x00', 7051185: '\x00', 7051186: '\x00', 7051187: '\x00', 7051188: '\x00', 7051166: '\x00', 7051190: '\x00', 7051191: '\x00', 7051192: '\x00', 7051193: '\x00', 7051194: '\x00', 7051167: '\x00', 7051196: '\x00', 7051197: '\x00', 7051198: '\x00', 7051199: '\x00', 7051200: '\x00', 7051201: '\x00', 7051202: '\x00', 7051203: '\x00', 7051204: '\x00', 7051205: '\x00', 7051206: '\x00', 7051207: '\x00', 7051208: ' ', 7051209: '\x94', 7051210: '@', 7051211: '\x00', 7051212: '\x00', 7051213: '\x00', 7051214: '\x00', 7051215: '\x00', 7051216: '\x10', 7051217: '\x97', 7051218: '@', 7051219: '\x00', 7051220: '\x00', 7051221: '\x00', 7051222: '\x00', 7051223: '\x00', 7051224: '\x00', 7051225: '\x00', 7051171: '\x00', 4223900L: '\x15'}}, 'text': '\xff\x15\xff#+\x00', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 7213056L, 'RSP': 140737488345816L, 'RDX': 0L, 'RIP': 4239552L, 'RBP': 7051232L}, 'memory': {7051183: '\x00', 7051201: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\xa1', 140737488345817L: 's', 140737488345818L: '@', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00', 140737488345824L: '\x00', 140737488345825L: '\x00', 140737488345826L: '\x00', 140737488345827L: '\x00', 140737488345828L: '\x00', 140737488345829L: '\x00', 140737488345830L: '\x00', 140737488345831L: '\x00', 140737488345832L: '\x00', 7051163: '\x00', 7051166: '\x00', 7051167: '\x00', 7051162: '\x00', 4223899L: '\xff', 7051164: '\x00', 7051165: '\x00', 4223902L: '#', 4223903L: '+', 7051168: '\xc0', 7051169: '\xb0', 7051170: '@', 7051171: '\x00', 7051172: '\x00', 7051173: '\x00', 7051174: '\x00', 7051175: '\x00', 7051176: '\x00', 7051177: '\x00', 7051178: '\x00', 7051179: '\x00', 7051180: '\x00', 7051181: '\x00', 7051182: '\x00', 4223901L: '\xff', 7051184: '\x00', 7051185: '\x00', 7051186: '\x00', 7051187: '\x00', 7051188: '\x00', 7051189: '\x00', 7051190: '\x00', 7051191: '\x00', 7051192: '\x00', 7051193: '\x00', 7051194: '\x00', 7051195: '\x00', 7051196: '\x00', 7051197: '\x00', 7051198: '\x00', 7051199: '\x00', 7051200: '\x00', 4223904L: '\x00', 7051202: '\x00', 7051203: '\x00', 7051204: '\x00', 7051205: '\x00', 7051206: '\x00', 7051207: '\x00', 7051208: ' ', 7051209: '\x94', 7051210: '@', 7051211: '\x00', 7051212: '\x00', 7051213: '\x00', 7051214: '\x00', 7051215: '\x00', 7051216: '\x10', 7051217: '\x97', 7051218: '@', 7051219: '\x00', 7051220: '\x00', 7051221: '\x00', 7051222: '\x00', 7051223: '\x00', 7051224: '\x00', 7051225: '\x00', 4223900L: '\x15'}}, 'disassembly': 'CALL QWORD [RIP+0x2b23ff]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_86(self):
''' Instruction CALL QWORD [RBX-0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4194936L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197581L, 'RBP': 6L}, 'memory': {4194944: '%', 4194945: '\x00', 4194946: '\x00', 4194947: '\x00', 4194948: '\x00', 4194949: '\x00', 4194950: '\x00', 4194951: '\x00', 4194952: '\xc0', 4194953: 'C', 4194954: 'D', 4194955: '\x00', 4194956: '\x00', 4194957: '\x00', 4194958: '\x00', 4194959: '\x00', 4194960: '\x00', 4194961: '\x89', 4194962: 'k', 4194963: '\x00', 4194964: '\x00', 4194965: '\x00', 4194966: '\x00', 4194967: '\x00', 4194968: '%', 4194969: '\x00', 4194970: '\x00', 4194971: '\x00', 4194972: '\x00', 4194973: '\x00', 4194974: '\x00', 4194975: '\x00', 4194976: '0', 4194977: '\xbd', 4194978: 'C', 4194979: '\x00', 4194980: '\x00', 4194981: '\x00', 4194982: '\x00', 4194983: '\x00', 4194984: '\xf8', 4194985: '\x88', 4194986: 'k', 4194987: '\x00', 4194988: '\x00', 4194989: '\x00', 4194990: '\x00', 4194991: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 4197581L: '\xff', 4197582L: 'S', 140737488346189L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346190L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 140737488346191L: '\x00', 4194943: '\x00', 4197583L: '\xf8', 4194928: '\xc0', 4194929: '\xb1', 4194930: '@', 4194931: '\x00', 4194932: '\x00', 4194933: '\x00', 4194934: '\x00', 4194935: '\x00', 4194936: '\x08', 4194937: '\x89', 4194938: 'k', 4194939: '\x00', 4194940: '\x00', 4194941: '\x00', 4194942: '\x00', 140737488346197L: '\x00'}}, 'text': '\xffS\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239808L, 'RBP': 6L}, 'memory': {140737488346175L: '\x00', 140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4194928: '\xc0', 4194929: '\xb1', 4194930: '@', 4194931: '\x00', 4194932: '\x00', 4194933: '\x00', 4194934: '\x00', 4194935: '\x00', 4194936: '\x08', 4194937: '\x89', 4194938: 'k', 4194939: '\x00', 4194940: '\x00', 4194941: '\x00', 4194942: '\x00', 4194943: '\x00', 4194944: '%', 4194945: '\x00', 4194946: '\x00', 4194947: '\x00', 4194948: '\x00', 4194949: '\x00', 4194950: '\x00', 4194951: '\x00', 4194952: '\xc0', 4194953: 'C', 4194954: 'D', 4194955: '\x00', 4194956: '\x00', 4194957: '\x00', 4194958: '\x00', 4194959: '\x00', 4194960: '\x00', 4194961: '\x89', 4194962: 'k', 4194963: '\x00', 4194964: '\x00', 4194965: '\x00', 4194966: '\x00', 4194967: '\x00', 4194968: '%', 4194969: '\x00', 4194970: '\x00', 4194971: '\x00', 4194972: '\x00', 4194973: '\x00', 4194974: '\x00', 4194975: '\x00', 4194976: '0', 4194977: '\xbd', 4194978: 'C', 4194979: '\x00', 4194980: '\x00', 4194981: '\x00', 4194982: '\x00', 4194983: '\x00', 4194984: '\xf8', 4194985: '\x88', 4194986: 'k', 4194987: '\x00', 4194988: '\x00', 4194989: '\x00', 4194990: '\x00', 4194991: '\x00', 4197581L: '\xff', 4197582L: 'S', 4197583L: '\xf8'}}, 'disassembly': 'CALL QWORD [RBX-0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_87(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336944L, 'RBP': 140737488345936L}, 'memory': {7041728: '\xd0', 7041771: '\x00', 7041729: '\x02', 7041751: '\x00', 7041736: '0', 7041730: 'C', 7041783: '\x00', 7041731: '\x00', 7041732: '\x00', 7041775: '\x00', 7041733: '\x00', 7041776: '\x00', 7041734: '\x00', 7041735: '\x00', 7041757: '\x00', 4336944L: '\xff', 4336945L: 'P', 4336946L: '8', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041720: '\xf0', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041721: '\x05', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041722: 'C', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041723: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041745: '&', 7041768: '`', 7041724: '\x00', 7041770: 'G', 7041767: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041725: '\x00', 7041763: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041726: '\x00', 7041782: '\x00', 7041769: '\x1f', 140737488344255L: '\x00', 7041781: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4392432L, 'RBP': 140737488345936L}, 'memory': {140737488344248L: '3', 140737488344249L: '-', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 7041732: '\x00', 7041733: '\x00', 7041734: '\x00', 7041735: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041736: '0', 4336944L: '\xff', 4336945L: 'P', 4336946L: '8'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_88(self):
''' Instruction CALL 0x420880 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 3L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\xba'}}, 'text': '\xe89\xd9\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 3L, 'RAX': 3L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327552L, 'RBP': 140737488345936L}, 'memory': {140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 4337474L: '\xe8', 4337475L: '9', 4337476L: '\xd9', 4337477L: '\xff', 4337478L: '\xff', 140737488344263L: '\x00', 140737488344264L: '\xba'}}, 'disassembly': 'CALL 0x420880', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_89(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_9(self):
''' Instruction CALL 0x417b20 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 6L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299749L, 'RBP': 140737488346472L}, 'memory': {140737488346205L: '\x00', 140737488346207L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xdd', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346214L: '\x00', 140737488346206L: '\x00', 140737488346213L: '\x00', 140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 4299749L: '\xe8', 4299750L: '6', 140737488346215L: '\x00', 140737488346216L: '\x00', 4299753L: '\xff', 4299751L: '\xdf', 4299752L: '\xff'}}, 'text': '\xe86\xdf\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 6L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4291360L, 'RBP': 140737488346472L}, 'memory': {4299750L: '6', 140737488346213L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xea', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 4299749L: '\xe8', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 4299753L: '\xff', 4299751L: '\xdf', 4299752L: '\xff'}}, 'disassembly': 'CALL 0x417b20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_90(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '"', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '"', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_91(self):
''' Instruction CALL 0x4023b0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392605L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 140737488344193L: '\x00', 140737488344194L: '\x00', 140737488344195L: '\x00', 140737488344196L: '\x00', 140737488344197L: '\x00', 140737488344198L: '\x00', 140737488344199L: '\x00', 140737488344200L: ' ', 4392605L: '\xe8', 4392606L: '\x0e', 4392607L: '\x1d', 4392608L: '\xfd', 4392609L: '\xff', 140737488344183L: '\x00', 140737488344184L: ']', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'text': '\xe8\x0e\x1d\xfd\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344184L, 'RDX': 9L, 'RIP': 4203440L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 140737488344193L: '\x00', 140737488344194L: '\x00', 140737488344195L: '\x00', 140737488344196L: '\x00', 140737488344197L: '\x00', 140737488344198L: '\x00', 140737488344199L: '\x00', 140737488344200L: ' ', 4392605L: '\xe8', 4392606L: '\x0e', 4392607L: '\x1d', 4392608L: '\xfd', 4392609L: '\xff', 140737488344175L: '\x00', 140737488344176L: '\t', 140737488344177L: '\x00', 140737488344178L: '\x00', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: '\xa2', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'disassembly': 'CALL 0x4023b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_92(self):
''' Instruction CALL QWORD [RBP+0x0] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197994L, 'RBP': 7054832L}, 'memory': {7054848: '\xc0', 7054849: '\xee', 7054850: 'H', 7054851: '\x00', 7054852: '\x00', 7054853: '\x00', 7054854: '\x00', 7054855: '\x00', 7054856: '\x90', 7054857: '\xef', 7054858: 'H', 7054859: '\x00', 7054860: '\x00', 7054861: '\x00', 7054862: '\x00', 7054863: '\x00', 7054864: '\x80', 7054865: '\xf1', 7054866: 'H', 7054867: '\x00', 7054868: '\x00', 7054869: '\x00', 7054870: '\x00', 7054871: '\x00', 7054872: '\xb0', 7054873: '\xf1', 7054874: 'H', 7054875: '\x00', 7054876: '\x00', 7054877: '\x00', 7054878: '\x00', 7054879: '\x00', 7054880: ' ', 7054881: '\xf2', 7054882: 'H', 7054883: '\x00', 7054884: '\x00', 7054885: '\x00', 7054886: '\x00', 7054887: '\x00', 7054888: '\xc0', 7054889: '\xf2', 7054890: 'H', 7054891: '\x00', 7054892: '\x00', 7054893: '\x00', 7054894: '\x00', 7054895: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4197994L: '\xff', 4197995L: 'U', 4197996L: '\x00', 7054832: '\xa0', 7054833: ',', 7054834: '@', 7054835: '\x00', 7054836: '\x00', 7054837: '\x00', 7054838: '\x00', 7054839: '\x00', 7054840: '`', 7054841: '\xee', 7054842: 'H', 7054843: '\x00', 7054844: '\x00', 7054845: '\x00', 7054846: '\x00', 7054847: '\x00'}}, 'text': '\xffU\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4205728L, 'RBP': 7054832L}, 'memory': {7054848: '\xc0', 7054849: '\xee', 7054850: 'H', 7054851: '\x00', 7054852: '\x00', 7054853: '\x00', 7054854: '\x00', 7054855: '\x00', 7054856: '\x90', 7054857: '\xef', 7054858: 'H', 7054859: '\x00', 7054860: '\x00', 7054861: '\x00', 7054862: '\x00', 7054863: '\x00', 7054864: '\x80', 7054865: '\xf1', 7054866: 'H', 7054867: '\x00', 7054868: '\x00', 7054869: '\x00', 7054870: '\x00', 7054871: '\x00', 7054872: '\xb0', 7054873: '\xf1', 7054874: 'H', 7054875: '\x00', 7054876: '\x00', 7054877: '\x00', 7054878: '\x00', 7054879: '\x00', 7054880: ' ', 7054881: '\xf2', 7054882: 'H', 7054883: '\x00', 7054884: '\x00', 7054885: '\x00', 7054886: '\x00', 7054887: '\x00', 7054888: '\xc0', 7054889: '\xf2', 7054890: 'H', 7054891: '\x00', 7054892: '\x00', 7054893: '\x00', 7054894: '\x00', 7054895: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'm', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4197994L: '\xff', 4197995L: 'U', 4197996L: '\x00', 140737488346159L: '\x00', 7054832: '\xa0', 7054833: ',', 7054834: '@', 7054835: '\x00', 7054836: '\x00', 7054837: '\x00', 7054838: '\x00', 7054839: '\x00', 7054840: '`', 7054841: '\xee', 7054842: 'H', 7054843: '\x00', 7054844: '\x00', 7054845: '\x00', 7054846: '\x00', 7054847: '\x00'}}, 'disassembly': 'CALL QWORD [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_93(self):
''' Instruction CALL QWORD [RAX+0x38] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 12L, 'RIP': 4336288L, 'RBP': 140737488345936L}, 'memory': {7041728: '\xd0', 7041771: '\x00', 7041729: '\x02', 7041751: '\x00', 7041730: 'C', 7041776: '\x00', 7041783: '\x00', 7041731: '\x00', 7041732: '\x00', 7041775: '\x00', 7041733: '\x00', 4336288L: '\xff', 4336289L: 'P', 4336290L: '8', 7041734: '\x00', 7041735: '\x00', 7041757: '\x00', 7041736: '0', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xba', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041720: '\xf0', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041721: '\x05', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041722: 'C', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041723: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041745: '&', 7041768: '`', 7041724: '\x00', 7041770: 'G', 7041767: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041725: '\x00', 7041763: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041726: '\x00', 7041782: '\x00', 7041769: '\x1f', 140737488344255L: '\x00', 7041781: '\x00'}}, 'text': '\xffP8', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 12L, 'RIP': 4392432L, 'RBP': 140737488345936L}, 'memory': {140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 7041727: '\x00', 7041728: '\xd0', 7041729: '\x02', 7041730: 'C', 7041731: '\x00', 7041732: '\x00', 7041733: '\x00', 4336288L: '\xff', 4336289L: 'P', 4336290L: '8', 7041734: '\x00', 7041735: '\x00', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 7041720: '\xf0', 7041721: '\x05', 7041722: 'C', 7041723: '\x00', 7041724: '\x00', 7041725: '\x00', 7041726: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xba', 7041737: '\t', 7041738: 'C', 7041739: '\x00', 7041740: '\x00', 7041741: '\x00', 7041742: '\x00', 7041743: '\x00', 7041744: '\x00', 7041745: '&', 7041746: '@', 7041747: '\x00', 7041748: '\x00', 7041749: '\x00', 7041750: '\x00', 7041751: '\x00', 7041752: '@', 7041753: '\r', 7041754: 'C', 7041755: '\x00', 7041756: '\x00', 7041757: '\x00', 7041758: '\x00', 7041759: '\x00', 7041760: '\xc0', 7041761: '\x0f', 7041762: 'C', 7041763: '\x00', 7041764: '\x00', 7041765: '\x00', 7041766: '\x00', 7041767: '\x00', 7041768: '`', 7041769: '\x1f', 7041770: 'G', 7041771: '\x00', 7041772: '\x00', 7041773: '\x00', 7041774: '\x00', 7041775: '\x00', 7041776: '\x00', 7041777: '\t', 7041778: 'C', 7041779: '\x00', 7041780: '\x00', 7041781: '\x00', 7041782: '\x00', 7041783: '\x00', 7041736: '0'}}, 'disassembly': 'CALL QWORD [RAX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_94(self):
''' Instruction CALL 0x48ee20 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4195094L, 'RBP': 4L}, 'memory': {4195094L: '\xe8', 4195095L: '\x05', 4195096L: '\xeb', 4195097L: '\x08', 4195098L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B'}}, 'text': '\xe8\x05\xeb\x08\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 0L, 'RIP': 4779552L, 'RBP': 4L}, 'memory': {4195094L: '\xe8', 4195095L: '\x05', 4195096L: '\xeb', 4195097L: '\x08', 4195098L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x1b', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'B'}}, 'disassembly': 'CALL 0x48ee20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_95(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_96(self):
''' Instruction CALL QWORD [RSP+0x8] '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'text': '\xffT$\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4320774L: '\xff', 4320775L: 'T', 4320776L: '$', 4320777L: '\x08', 140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345952: '\xde', 140737488345953: '\xdb', 140737488345954: '\xff', 140737488345955: '\xff', 140737488345956: '\xff', 140737488345957: '\x7f', 140737488345958: '\x00', 140737488345959: '\x00'}}, 'disassembly': 'CALL QWORD [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_97(self):
''' Instruction CALL 0x416630 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393038L, 'RBP': 140737354125312L}, 'memory': {140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: ' ', 4393038L: '\xe8', 4393039L: '\xdd', 4393040L: ']', 4393041L: '\xfe', 4393042L: '\xff'}}, 'text': '\xe8\xdd]\xfe\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 699L, 'RIP': 4286000L, 'RBP': 140737354125312L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: 'S', 140737488345881L: '\x08', 140737488345882L: 'C', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: ' ', 4393038L: '\xe8', 4393039L: '\xdd', 4393040L: ']', 4393041L: '\xfe', 4393042L: '\xff'}}, 'disassembly': 'CALL 0x416630', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_98(self):
''' Instruction CALL 0x40b0e0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4322389L, 'RBP': 140737488346472L}, 'memory': {140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: 'q', 140737488346055L: '\x00', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 4322390L: '\x86', 4322391L: '\xbc', 4322392L: '\xfe', 4322393L: '\xff', 4322389L: '\xe8'}}, 'text': '\xe8\x86\xbc\xfe\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239584L, 'RBP': 140737488346472L}, 'memory': {140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: 'q', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 4322390L: '\x86', 4322391L: '\xbc', 4322392L: '\xfe', 4322393L: '\xff', 4322389L: '\xe8'}}, 'disassembly': 'CALL 0x40b0e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCALL_99(self):
''' Instruction CALL 0x41edb0 '''
test = {'mnemonic': 'CALL', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283909L, 'RBP': 3L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'text': '\xe8\xa6\x8f\x00\x00', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 3L}, 'memory': {4283909L: '\xe8', 4283910L: '\xa6', 4283911L: '\x8f', 4283912L: '\x00', 4283913L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'CALL 0x41edb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVAE_1(self):
''' Instruction CMOVAE R12, RSI '''
test = {'mnemonic': 'CMOVAE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'R12': 8L, 'RAX': 4194536L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196876L, 'RBP': 80L}, 'memory': {4196876L: 'L', 4196877L: '\x0f', 4196878L: 'C', 4196879L: '\xe6'}}, 'text': 'L\x0fC\xe6', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'R12': 64L, 'RAX': 4194536L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196880L, 'RBP': 80L}, 'memory': {4196876L: 'L', 4196877L: '\x0f', 4196878L: 'C', 4196879L: '\xe6'}}, 'disassembly': 'CMOVAE R12, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVAE_2(self):
''' Instruction CMOVAE RAX, R12 '''
test = {'mnemonic': 'CMOVAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'R12': 64L, 'RAX': 64L, 'RSP': 140737488346160L, 'RDX': 7065176L, 'RIP': 4197291L, 'RBP': 10L}, 'memory': {4197291L: 'I', 4197292L: '\x0f', 4197293L: 'C', 4197294L: '\xc4'}}, 'text': 'I\x0fC\xc4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'R12': 64L, 'RAX': 64L, 'RSP': 140737488346160L, 'RDX': 7065176L, 'RIP': 4197295L, 'RBP': 10L}, 'memory': {4197291L: 'I', 4197292L: '\x0f', 4197293L: 'C', 4197294L: '\xc4'}}, 'disassembly': 'CMOVAE RAX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_1(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'R13': 2L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'R13': 2L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_10(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'R13': 78L, 'RAX': 3476L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'R13': 78L, 'RAX': 3476L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_11(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'R13': 78L, 'RAX': 3555L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'R13': 78L, 'RAX': 3555L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_12(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354126011L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354126011L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_13(self):
''' Instruction CMOVBE R13, RBX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RCX': 4096L, 'RBX': 9L, 'RDX': 9L, 'RBP': 7049504L, 'RDI': 140737354125312L, 'R13': 4096L, 'RSI': 4782888L, 'RIP': 4203491L, 'RSP': 140737488344144L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4203491L: 'L', 4203492L: '\x0f', 4203493L: 'F', 4203494L: '\xeb'}}, 'text': 'L\x0fF\xeb', 'pos': {'registers': {'RCX': 4096L, 'RBX': 9L, 'RDX': 9L, 'RBP': 7049504L, 'RDI': 140737354125312L, 'R13': 9L, 'RSI': 4782888L, 'RIP': 4203495L, 'RSP': 140737488344144L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4203491L: 'L', 4203492L: '\x0f', 4203493L: 'F', 4203494L: '\xeb'}}, 'disassembly': 'CMOVBE R13, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_14(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125567L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125567L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_15(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'R13': 12L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'R13': 12L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_16(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125409L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125409L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_17(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 140737354125668L, 'R13': 12L, 'RAX': 3740L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 140737354125668L, 'R13': 12L, 'RAX': 3740L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_18(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'R13': 1L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'R13': 1L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_19(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'R13': 4L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'R13': 4L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_2(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125646L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125646L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_20(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125853L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125853L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_21(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'R13': 4L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'R13': 4L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_22(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'R13': 4L, 'RAX': 3727L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'R13': 4L, 'RAX': 3727L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_23(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'R13': 2L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'R13': 2L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_24(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125650L, 'R13': 1L, 'RAX': 3758L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125650L, 'R13': 1L, 'RAX': 3758L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_25(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'R13': 4L, 'RAX': 4083L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'R13': 4L, 'RAX': 4083L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_26(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'R13': 78L, 'RAX': 3999L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'R13': 78L, 'RAX': 3999L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_27(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'R13': 78L, 'RAX': 3841L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'R13': 78L, 'RAX': 3841L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_28(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'R13': 1L, 'RAX': 3728L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'R13': 1L, 'RAX': 3728L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_29(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'R13': 1L, 'RAX': 4079L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'R13': 1L, 'RAX': 4079L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_3(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125488L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125488L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_30(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125685L, 'R13': 2L, 'RAX': 3723L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125685L, 'R13': 2L, 'RAX': 3723L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_31(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'R13': 2L, 'RAX': 3715L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'R13': 2L, 'RAX': 3715L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_32(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 140737354125646L, 'R13': 4L, 'RAX': 3762L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 140737354125646L, 'R13': 4L, 'RAX': 3762L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_33(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'R13': 78L, 'RAX': 4078L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'R13': 78L, 'RAX': 4078L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_4(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'R13': 78L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'R13': 78L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_5(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125774L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125774L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_6(self):
''' Instruction CMOVBE RDX, R12 '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125932L, 'RSP': 140737488346128L, 'RDX': 2147483647L, 'RIP': 4199289L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'text': 'I\x0fF\xd4', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'R12': 79L, 'RAX': 140737354125932L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199289L: 'I', 4199290L: '\x0f', 4199291L: 'F', 4199292L: '\xd4'}}, 'disassembly': 'CMOVBE RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_7(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'R13': 78L, 'RAX': 3713L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'R13': 78L, 'RAX': 3713L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_8(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'R13': 2L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'R13': 2L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVBE_9(self):
''' Instruction CMOVBE R13, RAX '''
test = {'mnemonic': 'CMOVBE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'R13': 78L, 'RAX': 3920L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392649L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'text': 'L\x0fF\xe8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'R13': 78L, 'RAX': 3920L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392649L: 'L', 4392650L: '\x0f', 4392651L: 'F', 4392652L: '\xe8'}}, 'disassembly': 'CMOVBE R13, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVB_1(self):
''' Instruction CMOVB RDX, [RSP+0x18] '''
test = {'mnemonic': 'CMOVB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219376L, 'RBP': 7051232L}, 'memory': {140737488345856: '\xff', 140737488345857: '\x0f', 140737488345858: '\x00', 140737488345859: '\x00', 140737488345860: '\x00', 140737488345861: '\x00', 140737488345862: '\x00', 140737488345863: '\x00', 140737488345864: '\xc0', 140737488345865: '\xf1', 140737488345866: 'k', 140737488345867: '\x00', 140737488345868: '\x00', 140737488345869: '\x00', 140737488345870: '\x00', 140737488345871: '\x00', 140737488345872: '\x00', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 140737488345880: '@', 140737488345881: '\x06', 140737488345882: '\x00', 140737488345883: '\x00', 140737488345884: '\x00', 140737488345885: '\x00', 140737488345886: '\x00', 140737488345887: '\x00', 140737488345888: '\x00', 140737488345889: '\xf0', 140737488345890: '\xff', 140737488345891: '\xff', 140737488345892: '\xff', 140737488345893: '\xff', 140737488345894: '\xff', 140737488345895: '\xff', 140737488345896: '\x01', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: '@', 140737488345905: '\x00', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 4219376L: 'H', 4219377L: '\x0f', 4219378L: 'B', 4219379L: 'T', 4219380L: '$', 4219381L: '\x18', 140737488345848: ' ', 140737488345849: '\x00', 140737488345850: '\x00', 140737488345851: '\x00', 140737488345852: '\x00', 140737488345853: '\x00', 140737488345854: '\x00', 140737488345855: '\x00'}}, 'text': 'H\x0fBT$\x18', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219382L, 'RBP': 7051232L}, 'memory': {140737488345856: '\xff', 140737488345857: '\x0f', 140737488345858: '\x00', 140737488345859: '\x00', 140737488345860: '\x00', 140737488345861: '\x00', 140737488345862: '\x00', 140737488345863: '\x00', 140737488345864: '\xc0', 140737488345865: '\xf1', 140737488345866: 'k', 140737488345867: '\x00', 140737488345868: '\x00', 140737488345869: '\x00', 140737488345870: '\x00', 140737488345871: '\x00', 140737488345872: '\x00', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 140737488345880: '@', 140737488345881: '\x06', 140737488345882: '\x00', 140737488345883: '\x00', 140737488345884: '\x00', 140737488345885: '\x00', 140737488345886: '\x00', 140737488345887: '\x00', 140737488345888: '\x00', 140737488345889: '\xf0', 140737488345890: '\xff', 140737488345891: '\xff', 140737488345892: '\xff', 140737488345893: '\xff', 140737488345894: '\xff', 140737488345895: '\xff', 140737488345896: '\x01', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: '@', 140737488345905: '\x00', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 4219376L: 'H', 4219377L: '\x0f', 4219378L: 'B', 4219379L: 'T', 4219380L: '$', 4219381L: '\x18', 140737488345848: ' ', 140737488345849: '\x00', 140737488345850: '\x00', 140737488345851: '\x00', 140737488345852: '\x00', 140737488345853: '\x00', 140737488345854: '\x00', 140737488345855: '\x00'}}, 'disassembly': 'CMOVB RDX, [RSP+0x18]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVB_2(self):
''' Instruction CMOVB RDX, [RSP+0x18] '''
test = {'mnemonic': 'CMOVB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219376L, 'RBP': 7051232L}, 'memory': {140737488345856: '\x00', 140737488345857: '\x00', 140737488345858: '3', 140737488345859: '.', 140737488345860: '1', 140737488345861: '0', 140737488345862: '.', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 140737488345866: 'e', 140737488345867: 'n', 140737488345868: 't', 140737488345869: 'o', 140737488345870: 'o', 140737488345871: '-', 140737488345872: 'r', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 140737488345880: '\x18', 140737488345881: '\x00', 140737488345882: '\x00', 140737488345883: '\x00', 140737488345884: '\x00', 140737488345885: '\x00', 140737488345886: '\x00', 140737488345887: '\x00', 140737488345888: '\x00', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\x00', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: '\x00', 140737488345905: '\x00', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 4219376L: 'H', 4219377L: '\x0f', 4219378L: 'B', 4219379L: 'T', 4219380L: '$', 4219381L: '\x18', 140737488345848: ' ', 140737488345849: '\x00', 140737488345850: '\x00', 140737488345851: '\x00', 140737488345852: '\x00', 140737488345853: '\x00', 140737488345854: '\x00', 140737488345855: '\x00'}}, 'text': 'H\x0fBT$\x18', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219382L, 'RBP': 7051232L}, 'memory': {140737488345856: '\x00', 140737488345857: '\x00', 140737488345858: '3', 140737488345859: '.', 140737488345860: '1', 140737488345861: '0', 140737488345862: '.', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 140737488345866: 'e', 140737488345867: 'n', 140737488345868: 't', 140737488345869: 'o', 140737488345870: 'o', 140737488345871: '-', 140737488345872: 'r', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 140737488345880: '\x18', 140737488345881: '\x00', 140737488345882: '\x00', 140737488345883: '\x00', 140737488345884: '\x00', 140737488345885: '\x00', 140737488345886: '\x00', 140737488345887: '\x00', 140737488345888: '\x00', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\x00', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: '\x00', 140737488345905: '\x00', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 4219376L: 'H', 4219377L: '\x0f', 4219378L: 'B', 4219379L: 'T', 4219380L: '$', 4219381L: '\x18', 140737488345848: ' ', 140737488345849: '\x00', 140737488345850: '\x00', 140737488345851: '\x00', 140737488345852: '\x00', 140737488345853: '\x00', 140737488345854: '\x00', 140737488345855: '\x00'}}, 'disassembly': 'CMOVB RDX, [RSP+0x18]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVNZ_1(self):
''' Instruction CMOVNZ RAX, [RIP+0x27499e] '''
test = {'mnemonic': 'CMOVNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4472928L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4473818L, 'RBP': 7L}, 'memory': {7048576: '\x90', 7048577: '+', 7048578: 'G', 7048579: '\x00', 7048580: '\x00', 7048581: '\x00', 7048582: '\x00', 7048583: '\x00', 7048584: '!', 7048585: ':', 7048586: 'I', 7048587: '\x00', 7048588: '\x00', 7048589: '\x00', 7048590: '\x00', 7048591: '\x00', 7048592: '\xc0', 7048593: '\xd0', 7048594: 'k', 7048595: '\x00', 7048596: '\x00', 7048597: '\x00', 7048598: '\x00', 7048599: '\x00', 7048600: '\x81', 7048601: "'", 7048602: 'I', 7048603: '\x00', 7048604: '\x00', 7048605: '\x00', 7048606: '\x00', 7048607: '\x00', 7048608: '`', 7048609: '\x85', 7048610: 'k', 7048611: '\x00', 7048612: '\x00', 7048613: '\x00', 7048614: '\x00', 7048615: '\x00', 7048616: '@', 7048617: 'Y', 7048618: 'E', 7048619: '\x00', 7048620: '\x00', 7048621: '\x00', 7048622: '\x00', 7048623: '\x00', 7048624: '\x10', 7048625: '\xd1', 7048626: 'k', 7048627: '\x00', 7048628: '\x00', 7048629: '\x00', 7048630: '\x00', 7048631: '\x00', 4473818L: 'H', 4473819L: '\x0f', 4473820L: 'E', 4473821L: '\x05', 4473822L: '\x9e', 4473823L: 'I', 4473824L: "'", 4473825L: '\x00', 7048568: 'L', 7048569: '\xcf', 7048570: 'k', 7048571: '\x00', 7048572: '\x00', 7048573: '\x00', 7048574: '\x00', 7048575: '\x00'}}, 'text': "H\x0fE\x05\x9eI'\x00", 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4664208L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4473826L, 'RBP': 7L}, 'memory': {7048576: '\x90', 7048577: '+', 7048578: 'G', 7048579: '\x00', 7048580: '\x00', 7048581: '\x00', 7048582: '\x00', 7048583: '\x00', 7048584: '!', 7048585: ':', 7048586: 'I', 7048587: '\x00', 7048588: '\x00', 7048589: '\x00', 7048590: '\x00', 7048591: '\x00', 7048592: '\xc0', 7048593: '\xd0', 7048594: 'k', 7048595: '\x00', 7048596: '\x00', 7048597: '\x00', 7048598: '\x00', 7048599: '\x00', 7048600: '\x81', 7048601: "'", 7048602: 'I', 7048603: '\x00', 7048604: '\x00', 7048605: '\x00', 7048606: '\x00', 7048607: '\x00', 7048608: '`', 7048609: '\x85', 7048610: 'k', 7048611: '\x00', 7048612: '\x00', 7048613: '\x00', 7048614: '\x00', 7048615: '\x00', 7048616: '@', 7048617: 'Y', 7048618: 'E', 7048619: '\x00', 7048620: '\x00', 7048621: '\x00', 7048622: '\x00', 7048623: '\x00', 7048624: '\x10', 7048625: '\xd1', 7048626: 'k', 7048627: '\x00', 7048628: '\x00', 7048629: '\x00', 7048630: '\x00', 7048631: '\x00', 4473818L: 'H', 4473819L: '\x0f', 4473820L: 'E', 4473821L: '\x05', 4473822L: '\x9e', 4473823L: 'I', 4473824L: "'", 4473825L: '\x00', 7048568: 'L', 7048569: '\xcf', 7048570: 'k', 7048571: '\x00', 7048572: '\x00', 7048573: '\x00', 7048574: '\x00', 7048575: '\x00'}}, 'disassembly': 'CMOVNZ RAX, [RIP+0x27499e]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVNZ_2(self):
''' Instruction CMOVNZ RCX, RBX '''
test = {'mnemonic': 'CMOVNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RBX': 4793637L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7065280L, 'RIP': 4297783L, 'RBP': 140737488346472L}, 'memory': {4297784L: '\x0f', 4297785L: 'E', 4297786L: '\xcb', 4297783L: 'H'}}, 'text': 'H\x0fE\xcb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RBX': 4793637L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7065280L, 'RIP': 4297787L, 'RBP': 140737488346472L}, 'memory': {4297784L: '\x0f', 4297785L: 'E', 4297786L: '\xcb', 4297783L: 'H'}}, 'disassembly': 'CMOVNZ RCX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_1(self):
''' Instruction CMOVS RBX, RAX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RBX': 7209408L, 'RDI': 7213056L, 'RAX': 18446744073709551615L, 'RSP': 140737488345776L, 'RDX': 7213056L, 'RIP': 4286577L, 'RBP': 3648L}, 'memory': {4286577L: 'H', 4286578L: '\x0f', 4286579L: 'H', 4286580L: '\xd8'}}, 'text': 'H\x0fH\xd8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RBX': 7209408L, 'RDI': 7213056L, 'RAX': 18446744073709551615L, 'RSP': 140737488345776L, 'RDX': 7213056L, 'RIP': 4286581L, 'RBP': 3648L}, 'memory': {4286577L: 'H', 4286578L: '\x0f', 4286579L: 'H', 4286580L: '\xd8'}}, 'disassembly': 'CMOVS RBX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_2(self):
''' Instruction CMOVS RAX, RDX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'text': 'H\x0fH\xc2', 'pos': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336657L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'disassembly': 'CMOVS RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_3(self):
''' Instruction CMOVS RAX, RDX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'text': 'H\x0fH\xc2', 'pos': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336657L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'disassembly': 'CMOVS RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_4(self):
''' Instruction CMOVS RBX, RAX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RBX': 7074240L, 'RDI': 7209408L, 'RAX': 18446744073709551615L, 'RSP': 140737488345776L, 'RDX': 7209408L, 'RIP': 4286577L, 'RBP': 135168L}, 'memory': {4286577L: 'H', 4286578L: '\x0f', 4286579L: 'H', 4286580L: '\xd8'}}, 'text': 'H\x0fH\xd8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RBX': 7074240L, 'RDI': 7209408L, 'RAX': 18446744073709551615L, 'RSP': 140737488345776L, 'RDX': 7209408L, 'RIP': 4286581L, 'RBP': 135168L}, 'memory': {4286577L: 'H', 4286578L: '\x0f', 4286579L: 'H', 4286580L: '\xd8'}}, 'disassembly': 'CMOVS RBX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_5(self):
''' Instruction CMOVS RAX, RDX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 18446744073709551615L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'text': 'H\x0fH\xc2', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336657L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'disassembly': 'CMOVS RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_6(self):
''' Instruction CMOVS RAX, RDX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 18446744073709551615L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'text': 'H\x0fH\xc2', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336657L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'disassembly': 'CMOVS RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_7(self):
''' Instruction CMOVS RAX, RDX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'text': 'H\x0fH\xc2', 'pos': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336657L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'disassembly': 'CMOVS RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_8(self):
''' Instruction CMOVS RAX, RDX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 18446744073709551615L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'text': 'H\x0fH\xc2', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336657L, 'RBP': 140737488345936L}, 'memory': {4336656L: '\xc2', 4336653L: 'H', 4336654L: '\x0f', 4336655L: 'H'}}, 'disassembly': 'CMOVS RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVS_9(self):
''' Instruction CMOVS RBX, RAX '''
test = {'mnemonic': 'CMOVS', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RBX': 7069696L, 'RDI': 7074240L, 'RAX': 18446744073709551615L, 'RSP': 140737488346128L, 'RDX': 7074240L, 'RIP': 4286577L, 'RBP': 4544L}, 'memory': {4286577L: 'H', 4286578L: '\x0f', 4286579L: 'H', 4286580L: '\xd8'}}, 'text': 'H\x0fH\xd8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RBX': 7069696L, 'RDI': 7074240L, 'RAX': 18446744073709551615L, 'RSP': 140737488346128L, 'RDX': 7074240L, 'RIP': 4286581L, 'RBP': 4544L}, 'memory': {4286577L: 'H', 4286578L: '\x0f', 4286579L: 'H', 4286580L: '\xd8'}}, 'disassembly': 'CMOVS RBX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_1(self):
''' Instruction CMOVZ RAX, RBX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 4864625L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4297708L, 'RBP': 140737488346472L}, 'memory': {4297708L: 'H', 4297709L: '\x0f', 4297710L: 'D', 4297711L: '\xc3'}}, 'text': 'H\x0fD\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RBX': 4864625L, 'RDI': 4793989L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4297712L, 'RBP': 140737488346472L}, 'memory': {4297708L: 'H', 4297709L: '\x0f', 4297710L: 'D', 4297711L: '\xc3'}}, 'disassembly': 'CMOVZ RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_10(self):
''' Instruction CMOVZ RAX, RDX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 531L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7074240L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239570L, 'RBP': 7051232L}, 'memory': {4239570L: 'H', 4239571L: '\x0f', 4239572L: 'D', 4239573L: '\xc2'}}, 'text': 'H\x0fD\xc2', 'pos': {'registers': {'RFLAGS': 531L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7074240L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239574L, 'RBP': 7051232L}, 'memory': {4239570L: 'H', 4239571L: '\x0f', 4239572L: 'D', 4239573L: '\xc2'}}, 'disassembly': 'CMOVZ RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_11(self):
''' Instruction CMOVZ RCX, [RIP+0x298437] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795936L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327561L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'text': 'H\x0fD\r7\x84)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'disassembly': 'CMOVZ RCX, [RIP+0x298437]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_12(self):
''' Instruction CMOVZ RDX, RCX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 131136L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223487L, 'RBP': 7051232L}, 'memory': {4223488L: '\x0f', 4223489L: 'D', 4223490L: '\xd1', 4223487L: 'H'}}, 'text': 'H\x0fD\xd1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 131136L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223491L, 'RBP': 7051232L}, 'memory': {4223488L: '\x0f', 4223489L: 'D', 4223490L: '\xd1', 4223487L: 'H'}}, 'disassembly': 'CMOVZ RDX, RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_13(self):
''' Instruction CMOVZ RAX, RBX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RBX': 4864625L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297672L, 'RBP': 140737488346472L}, 'memory': {4297672L: 'H', 4297673L: '\x0f', 4297674L: 'D', 4297675L: '\xc3'}}, 'text': 'H\x0fD\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RBX': 4864625L, 'RDI': 4793973L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297676L, 'RBP': 140737488346472L}, 'memory': {4297672L: 'H', 4297673L: '\x0f', 4297674L: 'D', 4297675L: '\xc3'}}, 'disassembly': 'CMOVZ RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_14(self):
''' Instruction CMOVZ R13D, EAX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RCX': 18446744073709551615L, 'RDX': 18446744073709551615L, 'RBP': 7049504L, 'RDI': 0L, 'RSI': 4294967295L, 'RIP': 4205414L, 'EAX': 0L, 'R13D': 0L, 'RSP': 140737488346000L, 'RFLAGS': 531L, 'RAX': 0L}, 'memory': {4205416L: 'D', 4205417L: '\xe8', 4205414L: 'D', 4205415L: '\x0f'}}, 'text': 'D\x0fD\xe8', 'pos': {'registers': {'RCX': 18446744073709551615L, 'RDX': 18446744073709551615L, 'RBP': 7049504L, 'RDI': 0L, 'RSI': 4294967295L, 'RIP': 4205418L, 'EAX': 0L, 'R13D': 0L, 'RSP': 140737488346000L, 'RFLAGS': 531L, 'RAX': 0L}, 'memory': {4205416L: 'D', 4205417L: '\xe8', 4205414L: 'D', 4205415L: '\x0f'}}, 'disassembly': 'CMOVZ R13D, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_15(self):
''' Instruction CMOVZ RCX, [RIP+0x298437] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795936L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327561L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'text': 'H\x0fD\r7\x84)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'disassembly': 'CMOVZ RCX, [RIP+0x298437]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_2(self):
''' Instruction CMOVZ RAX, RBX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RBX': 4864625L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297636L, 'RBP': 140737488346472L}, 'memory': {4297636L: 'H', 4297637L: '\x0f', 4297638L: 'D', 4297639L: '\xc3'}}, 'text': 'H\x0fD\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RBX': 4864625L, 'RDI': 4793961L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297640L, 'RBP': 140737488346472L}, 'memory': {4297636L: 'H', 4297637L: '\x0f', 4297638L: 'D', 4297639L: '\xc3'}}, 'disassembly': 'CMOVZ RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_3(self):
''' Instruction CMOVZ RCX, [RIP+0x298437] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795936L, 'RSI': 140737488345640L, 'RDI': 43L, 'RAX': 43L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327561L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'text': 'H\x0fD\r7\x84)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 43L, 'RAX': 43L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'disassembly': 'CMOVZ RCX, [RIP+0x298437]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_4(self):
''' Instruction CMOVZ RCX, [RIP+0x298437] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795936L, 'RSI': 140737488345640L, 'RDI': 21L, 'RAX': 21L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327561L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'text': 'H\x0fD\r7\x84)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 21L, 'RAX': 21L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'disassembly': 'CMOVZ RCX, [RIP+0x298437]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_5(self):
''' Instruction CMOVZ RAX, RDX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 531L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 7209408L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239570L, 'RBP': 7051232L}, 'memory': {4239570L: 'H', 4239571L: '\x0f', 4239572L: 'D', 4239573L: '\xc2'}}, 'text': 'H\x0fD\xc2', 'pos': {'registers': {'RFLAGS': 531L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 7209408L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239574L, 'RBP': 7051232L}, 'memory': {4239570L: 'H', 4239571L: '\x0f', 4239572L: 'D', 4239573L: '\xc2'}}, 'disassembly': 'CMOVZ RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_6(self):
''' Instruction CMOVZ RAX, RBX '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 4864625L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7L, 'RIP': 4297560L, 'RBP': 140737488346472L}, 'memory': {4297560L: 'H', 4297561L: '\x0f', 4297562L: 'D', 4297563L: '\xc3'}}, 'text': 'H\x0fD\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 4864625L, 'RDI': 4793933L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 7L, 'RIP': 4297564L, 'RBP': 140737488346472L}, 'memory': {4297560L: 'H', 4297561L: '\x0f', 4297562L: 'D', 4297563L: '\xc3'}}, 'disassembly': 'CMOVZ RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_7(self):
''' Instruction CMOVZ RCX, [RIP+0x298437] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795936L, 'RSI': 140737488345640L, 'RDI': 3L, 'RAX': 3L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327561L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'text': 'H\x0fD\r7\x84)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 3L, 'RAX': 3L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'disassembly': 'CMOVZ RCX, [RIP+0x298437]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_8(self):
''' Instruction CMOVZ RCX, [RIP+0x298437] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795936L, 'RSI': 140737488345640L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327561L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'text': 'H\x0fD\r7\x84)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327561L: 'H', 4327562L: '\x0f', 4327563L: 'D', 4327564L: '\r', 4327565L: '7', 4327566L: '\x84', 4327567L: ')', 4327568L: '\x00', 7048384: '\x00', 7048385: '\x00', 7048386: '\x00', 7048387: '\x00', 7048388: '\x00', 7048389: '\x00', 7048390: '\x00', 7048391: '\x00', 7048392: '\xe0', 7048393: '-', 7048394: 'I', 7048395: '\x00', 7048396: '\x00', 7048397: '\x00', 7048398: '\x00', 7048399: '\x00', 7048400: '(', 7048401: 'Y', 7048402: 'k', 7048403: '\x00', 7048404: '\x00', 7048405: '\x00', 7048406: '\x00', 7048407: '\x00', 7048408: '\x80', 7048409: 'm', 7048410: 'k', 7048411: '\x00', 7048412: '\x00', 7048413: '\x00', 7048414: '\x00', 7048415: '\x00', 7048416: '0', 7048417: '\xcf', 7048418: 'k', 7048419: '\x00', 7048420: '\x00', 7048421: '\x00', 7048422: '\x00', 7048423: '\x00', 7048424: '\xf0', 7048425: '\x0c', 7048426: '@', 7048427: '\x00', 7048428: '\x00', 7048429: '\x00', 7048430: '\x00', 7048431: '\x00', 7048432: 'h', 7048433: 'm', 7048434: 'k', 7048435: '\x00', 7048436: '\x00', 7048437: '\x00', 7048438: '\x00', 7048439: '\x00', 7048440: '\x80', 7048441: '\xc7', 7048442: 'k', 7048443: '\x00', 7048444: '\x00', 7048445: '\x00', 7048446: '\x00', 7048447: '\x00'}}, 'disassembly': 'CMOVZ RCX, [RIP+0x298437]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMOVZ_9(self):
''' Instruction CMOVZ RAX, [RIP+0x2ad25a] '''
test = {'mnemonic': 'CMOVZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4264928L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4241350L, 'RBP': 9L}, 'memory': {7047756: '\x00', 7047755: '\x00', 7047712: '\x00', 7047713: '\x00', 7047714: '\x00', 7047715: '\x00', 7047716: '\x00', 7047717: '\x00', 7047718: '\x00', 7047719: '\x00', 7047720: '`', 7047721: '\xe8', 7047722: '@', 7047723: '\x00', 7047724: '\x00', 7047725: '\x00', 7047726: '\x00', 7047727: '\x00', 7047728: '\x00', 7047729: '\x00', 7047730: '\x00', 7047731: '\x00', 7047732: '\x00', 7047733: '\x00', 7047734: '\x00', 7047735: '\x00', 7047736: 'H', 7047737: '\xd1', 7047738: 'k', 7047739: '\x00', 7047740: '\x00', 7047741: '\x00', 7047742: '\x00', 7047743: '\x00', 7047744: '\x00', 7047745: '\x00', 7047746: '\x00', 7047747: '\x00', 7047748: '\x00', 7047749: '\x00', 7047750: '\x00', 4241351L: '\x0f', 7047752: '\x80', 7047753: '\xb2', 7047754: 'B', 4241355L: '\xd2', 4241356L: '*', 7047757: '\x00', 7047758: '\x00', 7047759: '\x00', 7047760: '\xe0', 7047761: '\xce', 7047762: 'k', 7047763: '\x00', 7047764: '\x00', 7047765: '\x00', 7047766: '\x00', 7047767: '\x00', 7047768: 'P', 7047769: '\xce', 7047770: 'k', 7047771: '\x00', 7047772: '\x00', 7047773: '\x00', 7047774: '\x00', 7047775: '\x00', 7047751: '\x00', 4241353L: '\x05', 4241357L: '\x00', 4241354L: 'Z', 4241350L: 'H', 4241352L: 'D'}}, 'text': 'H\x0fD\x05Z\xd2*\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4264928L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4241358L, 'RBP': 9L}, 'memory': {4241356L: '*', 4241355L: '\xd2', 4241351L: '\x0f', 7047712: '\x00', 7047713: '\x00', 7047714: '\x00', 7047715: '\x00', 7047716: '\x00', 7047717: '\x00', 7047718: '\x00', 7047719: '\x00', 7047720: '`', 7047721: '\xe8', 7047722: '@', 7047723: '\x00', 7047724: '\x00', 7047725: '\x00', 7047726: '\x00', 7047727: '\x00', 7047728: '\x00', 7047729: '\x00', 7047730: '\x00', 7047731: '\x00', 7047732: '\x00', 7047733: '\x00', 7047734: '\x00', 7047735: '\x00', 7047736: 'H', 7047737: '\xd1', 7047738: 'k', 7047739: '\x00', 7047740: '\x00', 7047741: '\x00', 7047742: '\x00', 7047743: '\x00', 7047744: '\x00', 7047745: '\x00', 7047746: '\x00', 7047747: '\x00', 7047748: '\x00', 7047749: '\x00', 7047750: '\x00', 7047751: '\x00', 7047752: '\x80', 7047753: '\xb2', 7047754: 'B', 7047755: '\x00', 7047756: '\x00', 7047757: '\x00', 7047758: '\x00', 7047759: '\x00', 7047760: '\xe0', 7047761: '\xce', 7047762: 'k', 7047763: '\x00', 7047764: '\x00', 7047765: '\x00', 7047766: '\x00', 7047767: '\x00', 7047768: 'P', 7047769: '\xce', 7047770: 'k', 7047771: '\x00', 7047772: '\x00', 7047773: '\x00', 7047774: '\x00', 7047775: '\x00', 4241353L: '\x05', 4241357L: '\x00', 4241354L: 'Z', 4241350L: 'H', 4241352L: 'D'}}, 'disassembly': 'CMOVZ RAX, [RIP+0x2ad25a]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_1(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_10(self):
''' Instruction CMPXCHG [RDX], RDI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 7065872L, 'RIP': 4292581L, 'RBP': 140737488346112L}, 'memory': {7065872: '\x00', 7065873: '\x00', 7065874: '\x00', 7065875: '\x00', 7065876: '\x00', 7065877: '\x00', 7065878: '\x00', 7065879: '\x00', 7065880: '\x00', 7065881: '\x00', 7065882: '\x00', 7065883: '\x00', 7065884: '\x00', 7065885: '\x00', 7065886: '\x00', 7065887: '\x00', 7065888: '\x00', 7065889: '\x00', 7065890: '\x00', 7065891: '\x00', 7065892: '\x00', 7065893: '\x00', 7065894: '\x00', 7065895: '\x00', 7065896: '\x00', 7065897: '\x00', 7065898: '\x00', 7065899: '\x00', 7065900: '\x00', 7065901: '\x00', 7065902: '\x00', 7065903: '\x00', 7065904: '\x00', 7065905: '\x00', 7065906: '\x00', 7065907: '\x00', 7065908: '\x00', 7065909: '\x00', 7065910: '\x00', 7065911: '\x00', 7065912: '\x00', 7065913: '\x00', 7065914: '\x00', 7065915: '\x00', 7065916: '\x00', 7065917: '\x00', 7065918: '\x00', 7065919: '\x00', 7065920: '\x00', 7065921: '\x00', 7065922: '\x00', 7065923: '\x00', 7065924: '\x00', 7065925: '\x00', 7065926: '\x00', 7065927: '\x00', 7065928: '\x00', 7065929: '\x00', 7065930: '\x00', 7065931: '\x00', 7065932: '\x00', 7065933: '\x00', 7065934: '\x00', 7065935: '\x00', 4292581L: 'H', 4292582L: '\x0f', 4292583L: '\xb1', 4292584L: ':'}}, 'text': 'H\x0f\xb1:', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 7065872L, 'RIP': 4292585L, 'RBP': 140737488346112L}, 'memory': {7065872: '@', 7065873: '\xb8', 7065874: 'k', 7065875: '\x00', 7065876: '\x00', 7065877: '\x00', 7065878: '\x00', 7065879: '\x00', 7065880: '\x00', 7065881: '\x00', 7065882: '\x00', 7065883: '\x00', 7065884: '\x00', 7065885: '\x00', 7065886: '\x00', 7065887: '\x00', 7065888: '\x00', 7065889: '\x00', 7065890: '\x00', 7065891: '\x00', 7065892: '\x00', 7065893: '\x00', 7065894: '\x00', 7065895: '\x00', 7065896: '\x00', 7065897: '\x00', 7065898: '\x00', 7065899: '\x00', 7065900: '\x00', 7065901: '\x00', 7065902: '\x00', 7065903: '\x00', 7065904: '\x00', 7065905: '\x00', 7065906: '\x00', 7065907: '\x00', 7065908: '\x00', 7065909: '\x00', 7065910: '\x00', 7065911: '\x00', 7065912: '\x00', 7065913: '\x00', 7065914: '\x00', 7065915: '\x00', 7065916: '\x00', 7065917: '\x00', 7065918: '\x00', 7065919: '\x00', 7065920: '\x00', 7065921: '\x00', 7065922: '\x00', 7065923: '\x00', 7065924: '\x00', 7065925: '\x00', 7065926: '\x00', 7065927: '\x00', 7065928: '\x00', 7065929: '\x00', 7065930: '\x00', 7065931: '\x00', 7065932: '\x00', 7065933: '\x00', 7065934: '\x00', 7065935: '\x00', 4292581L: 'H', 4292582L: '\x0f', 4292583L: '\xb1', 4292584L: ':'}}, 'disassembly': 'CMPXCHG [RDX], RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_11(self):
''' Instruction CMPXCHG [RIP+0x2ba405], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049240L, 'RAX': 0L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4198228L, 'RBP': 0L}, 'memory': {7058265: '\x00', 4198228L: '\x0f', 4198229L: '\xb1', 4198230L: '5', 4198231L: '\x05', 4198232L: '\xa4', 4198233L: '+', 4198234L: '\x00', 7058267: '\x00', 7058268: '\x00', 7058266: '\x00', 7058270: '\x00', 7058271: '\x00', 7058272: '\x00', 7058273: '\x00', 7058274: '\x00', 7058275: '\x00', 7058276: '\x00', 7058277: '\x00', 7058278: '\x00', 7058279: '\x00', 7058280: '\x00', 7058281: '\x00', 7058282: '\x00', 7058283: '\x00', 7058284: '\x00', 7058285: '\x00', 7058286: '\x00', 7058269: '\x00', 7058288: '\x00', 7058289: '\x00', 7058290: '\x00', 7058291: '\x00', 7058292: '\x00', 7058293: '\x00', 7058294: '\x00', 7058295: '\x00', 7058296: '\x00', 7058287: '\x00'}}, 'text': '\x0f\xb15\x05\xa4+\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049240L, 'RAX': 0L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4198235L, 'RBP': 0L}, 'memory': {7058286: '\x00', 4198228L: '\x0f', 4198229L: '\xb1', 4198230L: '5', 4198231L: '\x05', 4198232L: '\xa4', 7058265: '\x00', 7058266: '\x00', 7058267: '\x00', 7058268: '\x00', 4198234L: '\x00', 7058270: '\x00', 7058271: '\x00', 7058272: '\x01', 7058273: '\x00', 7058274: '\x00', 7058275: '\x00', 7058276: '\x00', 7058277: '\x00', 7058278: '\x00', 7058279: '\x00', 7058280: '\x00', 7058281: '\x00', 7058282: '\x00', 7058283: '\x00', 7058284: '\x00', 7058285: '\x00', 4198233L: '+', 7058269: '\x00', 7058288: '\x00', 7058289: '\x00', 7058290: '\x00', 7058291: '\x00', 7058292: '\x00', 7058293: '\x00', 7058294: '\x00', 7058295: '\x00', 7058296: '\x00', 7058287: '\x00'}}, 'disassembly': 'CMPXCHG [RIP+0x2ba405], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_12(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_13(self):
''' Instruction CMPXCHG [RDX], EBP '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'EBP': 1L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4205869L, 'RBP': 1L}, 'memory': {7059439: '\x00', 7059437: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 4205869L: '\x0f', 4205870L: '\xb1', 4205871L: '*', 7059438: '\x00'}}, 'text': '\x0f\xb1*', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'EBP': 1L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4205872L, 'RBP': 1L}, 'memory': {7059439: '\x00', 7059437: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 4205869L: '\x0f', 4205870L: '\xb1', 4205871L: '*', 7059438: '\x00'}}, 'disassembly': 'CMPXCHG [RDX], EBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_14(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 1L, 'ESI': 1L, 'RDI': 4783024L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329790L, 'RBP': 140737488345936L}, 'memory': {4329792L: '2', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4329790L: '\x0f', 4329791L: '\xb1'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 1L, 'ESI': 1L, 'RDI': 4783024L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329793L, 'RBP': 140737488345936L}, 'memory': {4329792L: '2', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4329790L: '\x0f', 4329791L: '\xb1'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_15(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_16(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 1L, 'ESI': 1L, 'RDI': 4783008L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329790L, 'RBP': 140737488345936L}, 'memory': {4329792L: '2', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4329790L: '\x0f', 4329791L: '\xb1'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 1L, 'ESI': 1L, 'RDI': 4783008L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329793L, 'RBP': 140737488345936L}, 'memory': {4329792L: '2', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4329790L: '\x0f', 4329791L: '\xb1'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_2(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_3(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_4(self):
''' Instruction CMPXCHG [RBP+0x0], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 24L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 7065872L, 'RIP': 4230127L, 'RBP': 7051232L}, 'memory': {7051249: '\x00', 7051250: '\x00', 7051247: '\x00', 7051248: '\x00', 7051232: '\x00', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x00', 7051237: '\x00', 7051238: '\x00', 7051239: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051243: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 4230127L: '\x0f', 4230128L: '\xb1', 4230129L: 'u', 4230130L: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051257: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'text': '\x0f\xb1u\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 24L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 7065872L, 'RIP': 4230131L, 'RBP': 7051232L}, 'memory': {4230130L: '\x00', 4230128L: '\xb1', 4230129L: 'u', 4230127L: '\x0f', 7051232: '\x01', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x00', 7051237: '\x00', 7051238: '\x00', 7051239: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051243: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 7051247: '\x00', 7051248: '\x00', 7051249: '\x00', 7051250: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051257: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'disassembly': 'CMPXCHG [RBP+0x0], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_5(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_6(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 1L, 'ESI': 1L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329790L, 'RBP': 140737488345936L}, 'memory': {4329792L: '2', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4329790L: '\x0f', 4329791L: '\xb1'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 1L, 'ESI': 1L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329793L, 'RBP': 140737488345936L}, 'memory': {4329792L: '2', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4329790L: '\x0f', 4329791L: '\xb1'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_7(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_8(self):
''' Instruction CMPXCHG [RBP+0x0], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1L, 'ESI': 1L, 'RDI': 1600L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230127L, 'RBP': 7051232L}, 'memory': {7051249: '\x00', 7051250: '\x00', 7051247: '\x00', 7051248: '\x00', 7051232: '\x00', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01', 7051237: '\x00', 7051238: '\x00', 7051239: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051243: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 4230127L: '\x0f', 4230128L: '\xb1', 4230129L: 'u', 4230130L: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051257: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'text': '\x0f\xb1u\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1L, 'ESI': 1L, 'RDI': 1600L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230131L, 'RBP': 7051232L}, 'memory': {4230130L: '\x00', 4230128L: '\xb1', 4230129L: 'u', 4230127L: '\x0f', 7051232: '\x01', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01', 7051237: '\x00', 7051238: '\x00', 7051239: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051243: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 7051247: '\x00', 7051248: '\x00', 7051249: '\x00', 7051250: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051257: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'disassembly': 'CMPXCHG [RBP+0x0], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMPXCHG_9(self):
''' Instruction CMPXCHG [RDX], ESI '''
test = {'mnemonic': 'CMPXCHG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199034L, 'RBP': 4782912L}, 'memory': {7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'text': '\x0f\xb12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'ESI': 1L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199037L, 'RBP': 4782912L}, 'memory': {7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 4199034L: '\x0f', 4199035L: '\xb1', 4199036L: '2'}}, 'disassembly': 'CMPXCHG [RDX], ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_1(self):
''' Instruction CMP R13, 0x14 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'R13': 1L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392656L: '\x14', 4392653L: 'I', 4392654L: '\x83', 4392655L: '\xfd'}}, 'text': 'I\x83\xfd\x14', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'R13': 1L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392656L: '\x14', 4392653L: 'I', 4392654L: '\x83', 4392655L: '\xfd'}}, 'disassembly': 'CMP R13, 0x14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_10(self):
''' Instruction CMP DWORD [RIP+0x2b42c0], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1L, 'RDI': 1600L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230105L, 'RBP': 7051232L}, 'memory': {4230110L: '\x00', 4230109L: '+', 4230107L: '\xc0', 4230106L: '=', 4230105L: '\x83', 7065241: '\x00', 7065242: '\x00', 7065243: '\x00', 7065244: '\x00', 7065245: '\x00', 7065246: '\x00', 7065247: '\x00', 7065248: '\x00', 7065249: '\x00', 7065250: '\x00', 7065251: '\x00', 7065252: '\x00', 7065253: '\x00', 7065254: '\x00', 7065255: '\x00', 7065256: '\x00', 7065257: '\x00', 7065258: '\x00', 7065259: '\x00', 7065260: '\x00', 7065261: '\x00', 7065262: '\x00', 7065263: '\x00', 7065264: '\x00', 7065265: '\x00', 7065266: '\x00', 7065267: '\x00', 7065268: '\x00', 7065269: '\x00', 7065270: '\x00', 7065271: '\x00', 7065272: '\x00', 4230111L: '\x00', 4230108L: 'B'}}, 'text': '\x83=\xc0B+\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1L, 'RDI': 1600L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230112L, 'RBP': 7051232L}, 'memory': {4230110L: '\x00', 4230109L: '+', 4230107L: '\xc0', 4230106L: '=', 4230105L: '\x83', 7065241: '\x00', 7065242: '\x00', 7065243: '\x00', 7065244: '\x00', 7065245: '\x00', 7065246: '\x00', 7065247: '\x00', 7065248: '\x00', 7065249: '\x00', 7065250: '\x00', 7065251: '\x00', 7065252: '\x00', 7065253: '\x00', 7065254: '\x00', 7065255: '\x00', 7065256: '\x00', 7065257: '\x00', 7065258: '\x00', 7065259: '\x00', 7065260: '\x00', 7065261: '\x00', 7065262: '\x00', 7065263: '\x00', 7065264: '\x00', 7065265: '\x00', 7065266: '\x00', 7065267: '\x00', 7065268: '\x00', 7065269: '\x00', 7065270: '\x00', 7065271: '\x00', 7065272: '\x00', 4230111L: '\x00', 4230108L: 'B'}}, 'disassembly': 'CMP DWORD [RIP+0x2b42c0], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_100(self):
''' Instruction CMP EAX, 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'text': '\x83\xf8\x00', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'disassembly': 'CMP EAX, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_101(self):
''' Instruction CMP R8, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'R8': 4L, 'RAX': 2147483634L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4346951L, 'RBP': 140737488345936L}, 'memory': {4346952L: '9', 4346953L: '\xc0', 4346951L: 'I'}}, 'text': 'I9\xc0', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'R8': 4L, 'RAX': 2147483634L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4346954L, 'RBP': 140737488345936L}, 'memory': {4346952L: '9', 4346953L: '\xc0', 4346951L: 'I'}}, 'disassembly': 'CMP R8, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_11(self):
''' Instruction CMP DWORD [RBP-0x5d0], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338784L, 'RBP': 140737488345936L}, 'memory': {140737488344448: '\x00', 140737488344449: '\x00', 140737488344450: '\x00', 140737488344451: '\x00', 140737488344452: '\xff', 140737488344453: '\xff', 140737488344454: '\xff', 140737488344455: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 4338784L: '\x83', 4338785L: '\xbd', 4338786L: '0', 4338787L: '\xfa', 4338788L: '\xff', 4338789L: '\xff', 4338790L: '\x00'}}, 'text': '\x83\xbd0\xfa\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338791L, 'RBP': 140737488345936L}, 'memory': {140737488344448: '\x00', 140737488344449: '\x00', 140737488344450: '\x00', 140737488344451: '\x00', 140737488344452: '\xff', 140737488344453: '\xff', 140737488344454: '\xff', 140737488344455: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 4338784L: '\x83', 4338785L: '\xbd', 4338786L: '0', 4338787L: '\xfa', 4338788L: '\xff', 4338789L: '\xff', 4338790L: '\x00'}}, 'disassembly': 'CMP DWORD [RBP-0x5d0], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_12(self):
''' Instruction CMP [RDI], DL '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 6L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {140737488345968: '\x00', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'text': '8\x17', 'pos': {'registers': {'RFLAGS': 663L, 'DL': 6L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {140737488345968: '\x00', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'disassembly': 'CMP [RDI], DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_13(self):
''' Instruction CMP R10D, 0x3 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4194304L, 'RAX': 4194304L, 'RDI': 4L, 'R10D': 13L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284923L, 'RBP': 32768L}, 'memory': {4284923L: 'A', 4284924L: '\x83', 4284925L: '\xfa', 4284926L: '\x03'}}, 'text': 'A\x83\xfa\x03', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4194304L, 'RAX': 4194304L, 'RDI': 4L, 'R10D': 13L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284927L, 'RBP': 32768L}, 'memory': {4284923L: 'A', 4284924L: '\x83', 4284925L: '\xfa', 4284926L: '\x03'}}, 'disassembly': 'CMP R10D, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_14(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350498L}, 'memory': {4322496L: 'f', 4322497L: 'D', 140737488350498: 'J', 140737488350499: 'D', 140737488350500: 'K', 140737488350501: '_', 140737488350502: 'H', 140737488350503: 'O', 140737488350504: 'M', 140737488350505: 'E', 140737488350506: '=', 140737488350507: '/', 140737488350508: 'e', 140737488350509: 't', 140737488350510: 'c', 140737488350511: '/', 140737488350512: 'j', 140737488350513: 'a', 4322499L: 'm', 4322500L: '\x00', 4322498L: ';'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488350498L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350501: '_', 140737488350502: 'H', 140737488350503: 'O', 140737488350504: 'M', 140737488350505: 'E', 140737488350506: '=', 140737488350507: '/', 140737488350508: 'e', 140737488350498: 'J', 140737488350510: 'c', 140737488350509: 't', 140737488350512: 'j', 140737488350513: 'a', 140737488350499: 'D', 140737488350500: 'K', 140737488350511: '/'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_15(self):
''' Instruction CMP BYTE [RAX], 0x4d '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350473L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {140737488350473: 'G', 140737488350474: 'D', 140737488350475: 'M', 140737488350476: 'S', 140737488350477: 'E', 140737488350478: 'S', 140737488350479: 'S', 4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488350480: 'I'}}, 'text': '\x808M', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350473L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {140737488350473: 'G', 140737488350474: 'D', 140737488350475: 'M', 140737488350476: 'S', 140737488350477: 'E', 140737488350478: 'S', 140737488350479: 'S', 140737488350480: 'I', 4212881L: '8', 4212882L: 'M', 4212880L: '\x80'}}, 'disassembly': 'CMP BYTE [RAX], 0x4d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_16(self):
''' Instruction CMP DWORD [R13+0x8], 0x25 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'R13': 4195032L, 'RAX': 4409968L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197567L, 'RBP': 10L}, 'memory': {4197568L: '\x83', 4197569L: '}', 4197570L: '\x08', 4197571L: '%', 4195071: '\x00', 4195040: '%', 4195041: '\x00', 4195042: '\x00', 4195043: '\x00', 4195044: '\x00', 4195045: '\x00', 4195046: '\x00', 4195047: '\x00', 4195048: '\x00', 4195049: 'G', 4195050: 'C', 4195051: '\x00', 4195052: '\x00', 4195053: '\x00', 4195054: '\x00', 4195055: '\x00', 4195056: '\xe0', 4195057: '\x88', 4195058: 'k', 4195059: '\x00', 4195060: '\x00', 4195061: '\x00', 4195062: '\x00', 4195063: '\x00', 4195064: '%', 4195065: '\x00', 4195066: '\x00', 4195067: '\x00', 4195068: '\x00', 4195069: '\x00', 4195070: '\x00', 4197567L: 'A'}}, 'text': 'A\x83}\x08%', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4409968L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197572L, 'RBP': 10L}, 'memory': {4197568L: '\x83', 4197569L: '}', 4197570L: '\x08', 4197571L: '%', 4195071: '\x00', 4195040: '%', 4195041: '\x00', 4195042: '\x00', 4195043: '\x00', 4195044: '\x00', 4195045: '\x00', 4195046: '\x00', 4195047: '\x00', 4195048: '\x00', 4195049: 'G', 4195050: 'C', 4195051: '\x00', 4195052: '\x00', 4195053: '\x00', 4195054: '\x00', 4195055: '\x00', 4195056: '\xe0', 4195057: '\x88', 4195058: 'k', 4195059: '\x00', 4195060: '\x00', 4195061: '\x00', 4195062: '\x00', 4195063: '\x00', 4195064: '%', 4195065: '\x00', 4195066: '\x00', 4195067: '\x00', 4195068: '\x00', 4195069: '\x00', 4195070: '\x00', 4197567L: 'A'}}, 'disassembly': 'CMP DWORD [R13+0x8], 0x25', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_17(self):
''' Instruction CMP EAX, 0xa00 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 2048L, 'RFLAGS': 518L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392496L, 'RBP': 7049504L}, 'memory': {4392496L: '=', 4392497L: '\x00', 4392498L: '\n', 4392499L: '\x00', 4392500L: '\x00'}}, 'text': '=\x00\n\x00\x00', 'pos': {'registers': {'EAX': 2048L, 'RFLAGS': 647L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392501L, 'RBP': 7049504L}, 'memory': {4392496L: '=', 4392497L: '\x00', 4392498L: '\n', 4392499L: '\x00', 4392500L: '\x00'}}, 'disassembly': 'CMP EAX, 0xa00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_18(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488349498L}, 'memory': {140737488349504: 'L', 140737488349505: 'O', 140737488349506: 'A', 140737488349507: 'D', 140737488349508: '_', 140737488349509: 'P', 140737488349510: 'A', 140737488349511: 'T', 140737488349512: 'H', 140737488349513: '=', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488349498: 'G', 140737488349499: 'U', 140737488349500: 'I', 140737488349501: 'L', 140737488349502: 'E', 140737488349503: '_'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488349498L}, 'memory': {140737488349504: 'L', 140737488349505: 'O', 140737488349506: 'A', 140737488349507: 'D', 140737488349508: '_', 140737488349509: 'P', 140737488349510: 'A', 140737488349511: 'T', 140737488349512: 'H', 140737488349513: '=', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488349498: 'G', 140737488349499: 'U', 140737488349500: 'I', 140737488349501: 'L', 140737488349502: 'E', 140737488349503: '_'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_19(self):
''' Instruction CMP EAX, 0x1 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4284816L, 'RBP': 4L}, 'memory': {4284816L: '\x83', 4284817L: '\xf8', 4284818L: '\x01'}}, 'text': '\x83\xf8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4284819L, 'RBP': 4L}, 'memory': {4284816L: '\x83', 4284817L: '\xf8', 4284818L: '\x01'}}, 'disassembly': 'CMP EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_2(self):
''' Instruction CMP RAX, 0x1e '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296948L: 'H', 4296949L: '\x83', 4296950L: '\xf8', 4296951L: '\x1e'}}, 'text': 'H\x83\xf8\x1e', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296948L: 'H', 4296949L: '\x83', 4296950L: '\xf8', 4296951L: '\x1e'}}, 'disassembly': 'CMP RAX, 0x1e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_20(self):
''' Instruction CMP RAX, 0x1e '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 2L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296948L: 'H', 4296949L: '\x83', 4296950L: '\xf8', 4296951L: '\x1e'}}, 'text': 'H\x83\xf8\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 2L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296948L: 'H', 4296949L: '\x83', 4296950L: '\xf8', 4296951L: '\x1e'}}, 'disassembly': 'CMP RAX, 0x1e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_21(self):
''' Instruction CMP RCX, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 7065872L, 'RIP': 4292585L, 'RBP': 140737488346112L}, 'memory': {4292585L: 'H', 4292586L: '9', 4292587L: '\xc1'}}, 'text': 'H9\xc1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 7065872L, 'RIP': 4292588L, 'RBP': 140737488346112L}, 'memory': {4292585L: 'H', 4292586L: '9', 4292587L: '\xc1'}}, 'disassembly': 'CMP RCX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_22(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488350181L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350181: 'H', 140737488350182: 'G', 140737488350183: '=', 140737488350184: '/', 140737488350185: 'u', 140737488350186: 's', 140737488350187: 'r', 140737488350188: '/', 140737488350189: 'b', 140737488350190: 'i', 140737488350191: 'n', 140737488350192: '/', 140737488350193: 'h', 140737488350194: 'g', 140737488350195: '\x00', 140737488350196: 'G'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 643L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488350181L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350181: 'H', 140737488350182: 'G', 140737488350183: '=', 140737488350184: '/', 140737488350185: 'u', 140737488350186: 's', 140737488350187: 'r', 140737488350188: '/', 140737488350189: 'b', 140737488350190: 'i', 140737488350191: 'n', 140737488350192: '/', 140737488350193: 'h', 140737488350194: 'g', 140737488350195: '\x00', 140737488350196: 'G'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_23(self):
''' Instruction CMP RAX, 0xfffffffffffff001 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 4783074L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 7065176L, 'RIP': 4285824L, 'RBP': 0L}, 'memory': {4285824L: 'H', 4285825L: '=', 4285826L: '\x01', 4285827L: '\xf0', 4285828L: '\xff', 4285829L: '\xff'}}, 'text': 'H=\x01\xf0\xff\xff', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 4783074L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 7065176L, 'RIP': 4285830L, 'RBP': 0L}, 'memory': {4285824L: 'H', 4285825L: '=', 4285826L: '\x01', 4285827L: '\xf0', 4285828L: '\xff', 4285829L: '\xff'}}, 'disassembly': 'CMP RAX, 0xfffffffffffff001', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_24(self):
''' Instruction CMP QWORD [RSP+0x18], 0x3ff '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 119L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 1648L, 'RIP': 4220944L, 'RBP': 7051232L}, 'memory': {140737488345856: '\xff', 140737488345857: '\x0f', 140737488345858: '\x00', 140737488345859: '\x00', 140737488345860: '\x00', 140737488345861: '\x00', 140737488345862: '\x00', 140737488345863: '\x00', 140737488345864: 'H', 140737488345865: '\x98', 140737488345866: 'k', 140737488345867: '\x00', 140737488345868: '\x00', 140737488345869: '\x00', 140737488345870: '\x00', 140737488345871: '\x00', 140737488345872: '\x00', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 140737488345880: '@', 140737488345881: '\x06', 140737488345882: '\x00', 140737488345883: '\x00', 140737488345884: '\x00', 140737488345885: '\x00', 140737488345886: '\x00', 140737488345887: '\x00', 140737488345888: 'I', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\xff', 140737488345893: '\xff', 140737488345894: '\xff', 140737488345895: '\xff', 140737488345896: '\x19', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345855: '\x00', 140737488345848: 'P', 140737488345849: '\x06', 4220950L: '\x03', 4220944L: 'H', 4220945L: '\x81', 4220952L: '\x00', 4220946L: '|', 4220947L: '$', 4220951L: '\x00', 4220948L: '\x18', 140737488345850: '\x00', 140737488345851: '\x00', 140737488345852: '\x00', 140737488345853: '\x00', 140737488345854: '\x00', 4220949L: '\xff'}}, 'text': 'H\x81|$\x18\xff\x03\x00\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 119L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 1648L, 'RIP': 4220953L, 'RBP': 7051232L}, 'memory': {140737488345856: '\xff', 140737488345857: '\x0f', 140737488345858: '\x00', 140737488345859: '\x00', 140737488345860: '\x00', 140737488345861: '\x00', 140737488345862: '\x00', 140737488345863: '\x00', 140737488345864: 'H', 140737488345865: '\x98', 140737488345866: 'k', 140737488345867: '\x00', 140737488345868: '\x00', 140737488345869: '\x00', 140737488345870: '\x00', 140737488345871: '\x00', 140737488345872: '\x00', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 140737488345880: '@', 140737488345881: '\x06', 140737488345882: '\x00', 140737488345883: '\x00', 140737488345884: '\x00', 140737488345885: '\x00', 140737488345886: '\x00', 140737488345887: '\x00', 140737488345888: 'I', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\xff', 140737488345893: '\xff', 140737488345894: '\xff', 140737488345895: '\xff', 140737488345896: '\x19', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345855: '\x00', 140737488345848: 'P', 140737488345849: '\x06', 4220950L: '\x03', 4220944L: 'H', 4220945L: '\x81', 4220952L: '\x00', 4220946L: '|', 4220947L: '$', 4220951L: '\x00', 4220948L: '\x18', 140737488345850: '\x00', 140737488345851: '\x00', 140737488345852: '\x00', 140737488345853: '\x00', 140737488345854: '\x00', 4220949L: '\xff'}}, 'disassembly': 'CMP QWORD [RSP+0x18], 0x3ff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_25(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488350989L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350989: 'O', 140737488350990: 'P', 140737488350991: 'E', 140737488350992: 'N', 140737488350993: 'G', 140737488350994: 'L', 140737488350995: '_', 140737488350996: 'P', 140737488350997: 'R', 140737488350998: 'O', 140737488350999: 'F', 140737488351000: 'I', 140737488351001: 'L', 140737488351002: 'E', 140737488351003: '=', 140737488351004: 'x'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 659L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488350989L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350989: 'O', 140737488350990: 'P', 140737488350991: 'E', 140737488350992: 'N', 140737488350993: 'G', 140737488350994: 'L', 140737488350995: '_', 140737488350996: 'P', 140737488350997: 'R', 140737488350998: 'O', 140737488350999: 'F', 140737488351000: 'I', 140737488351001: 'L', 140737488351002: 'E', 140737488351003: '=', 140737488351004: 'x'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_26(self):
''' Instruction CMP R8, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R8': 7051232L, 'RAX': 7051232L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211168L, 'RBP': 7051232L}, 'memory': {4211168L: 'I', 4211169L: '9', 4211170L: '\xc0'}}, 'text': 'I9\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R8': 7051232L, 'RAX': 7051232L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211171L, 'RBP': 7051232L}, 'memory': {4211168L: 'I', 4211169L: '9', 4211170L: '\xc0'}}, 'disassembly': 'CMP R8, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_27(self):
''' Instruction CMP RAX, RSI '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 97L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 140737354125683L, 'RSP': 140737488344192L, 'RDX': 4783038L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'text': 'H9\xf0', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 97L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 140737354125683L, 'RSP': 140737488344192L, 'RDX': 4783038L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'disassembly': 'CMP RAX, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_28(self):
''' Instruction CMP [RDI], DL '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 96L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {140737488345968: 'Z', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'text': '8\x17', 'pos': {'registers': {'RFLAGS': 647L, 'DL': 96L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {140737488345968: 'Z', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'disassembly': 'CMP [RDI], DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_29(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488350464L}, 'memory': {140737488350464: 'L', 140737488350465: 'I', 140737488350466: 'N', 140737488350467: 'E', 140737488350468: 'S', 140737488350469: '=', 140737488350470: '2', 140737488350471: '4', 140737488350472: '\x00', 140737488350473: 'G', 140737488350474: 'D', 140737488350475: 'M', 140737488350476: 'S', 140737488350477: 'E', 140737488350478: 'S', 140737488350479: 'S', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 4322496L: 'f', 4322498L: ';'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322501L, 'RBP': 140737488350464L}, 'memory': {140737488350464: 'L', 140737488350465: 'I', 140737488350466: 'N', 140737488350467: 'E', 140737488350468: 'S', 140737488350469: '=', 140737488350470: '2', 140737488350471: '4', 140737488350472: '\x00', 140737488350473: 'G', 140737488350474: 'D', 140737488350475: 'M', 140737488350476: 'S', 140737488350477: 'E', 140737488350478: 'S', 140737488350479: 'S', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 4322496L: 'f', 4322498L: ';'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_3(self):
''' Instruction CMP RAX, 0x1e '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 6L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296948L: 'H', 4296949L: '\x83', 4296950L: '\xf8', 4296951L: '\x1e'}}, 'text': 'H\x83\xf8\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 6L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296948L: 'H', 4296949L: '\x83', 4296950L: '\xf8', 4296951L: '\x1e'}}, 'disassembly': 'CMP RAX, 0x1e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_30(self):
''' Instruction CMP RDX, 0x7e0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 624L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'text': 'H\x81\xfa\xe0\x07\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 624L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'disassembly': 'CMP RDX, 0x7e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_31(self):
''' Instruction CMP DWORD [RIP+0x2b4289], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346032L, 'RDX': 1617L, 'RIP': 4230160L, 'RBP': 7051232L}, 'memory': {4230160L: '\x83', 4230161L: '=', 4230162L: '\x89', 4230163L: 'B', 4230164L: '+', 4230165L: '\x00', 4230166L: '\x00', 7065241: '\x00', 7065242: '\x00', 7065243: '\x00', 7065244: '\x00', 7065245: '\x00', 7065246: '\x00', 7065247: '\x00', 7065248: '\x00', 7065249: '\x00', 7065250: '\x00', 7065251: '\x00', 7065252: '\x00', 7065253: '\x00', 7065254: '\x00', 7065255: '\x00', 7065256: '\x00', 7065257: '\x00', 7065258: '\x00', 7065259: '\x00', 7065260: '\x00', 7065261: '\x00', 7065262: '\x00', 7065263: '\x00', 7065264: '\x00', 7065265: '\x00', 7065266: '\x00', 7065267: '\x00', 7065268: '\x00', 7065269: '\x00', 7065270: '\x00', 7065271: '\x00', 7065272: '\x00'}}, 'text': '\x83=\x89B+\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346032L, 'RDX': 1617L, 'RIP': 4230167L, 'RBP': 7051232L}, 'memory': {4230160L: '\x83', 4230161L: '=', 4230162L: '\x89', 4230163L: 'B', 4230164L: '+', 4230165L: '\x00', 4230166L: '\x00', 7065241: '\x00', 7065242: '\x00', 7065243: '\x00', 7065244: '\x00', 7065245: '\x00', 7065246: '\x00', 7065247: '\x00', 7065248: '\x00', 7065249: '\x00', 7065250: '\x00', 7065251: '\x00', 7065252: '\x00', 7065253: '\x00', 7065254: '\x00', 7065255: '\x00', 7065256: '\x00', 7065257: '\x00', 7065258: '\x00', 7065259: '\x00', 7065260: '\x00', 7065261: '\x00', 7065262: '\x00', 7065263: '\x00', 7065264: '\x00', 7065265: '\x00', 7065266: '\x00', 7065267: '\x00', 7065268: '\x00', 7065269: '\x00', 7065270: '\x00', 7065271: '\x00', 7065272: '\x00'}}, 'disassembly': 'CMP DWORD [RIP+0x2b4289], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_32(self):
''' Instruction CMP R8, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'R8': 2L, 'RAX': 2L, 'RSP': 140737488344256L, 'RDX': 4783050L, 'RIP': 4336312L, 'RBP': 140737488345936L}, 'memory': {4336312L: 'I', 4336313L: '9', 4336314L: '\xc0'}}, 'text': 'I9\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'R8': 2L, 'RAX': 2L, 'RSP': 140737488344256L, 'RDX': 4783050L, 'RIP': 4336315L, 'RBP': 140737488345936L}, 'memory': {4336312L: 'I', 4336313L: '9', 4336314L: '\xc0'}}, 'disassembly': 'CMP R8, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_33(self):
''' Instruction CMP RDX, 0x7e0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052056L, 'RSP': 140737488345712L, 'RDX': 736L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'text': 'H\x81\xfa\xe0\x07\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052056L, 'RSP': 140737488345712L, 'RDX': 736L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'disassembly': 'CMP RDX, 0x7e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_34(self):
''' Instruction CMP R8, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'R8': 12L, 'RAX': 12L, 'RSP': 140737488344256L, 'RDX': 4783034L, 'RIP': 4336312L, 'RBP': 140737488345936L}, 'memory': {4336312L: 'I', 4336313L: '9', 4336314L: '\xc0'}}, 'text': 'I9\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'R8': 12L, 'RAX': 12L, 'RSP': 140737488344256L, 'RDX': 4783034L, 'RIP': 4336315L, 'RBP': 140737488345936L}, 'memory': {4336312L: 'I', 4336313L: '9', 4336314L: '\xc0'}}, 'disassembly': 'CMP R8, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_35(self):
''' Instruction CMP EAX, 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'text': '\x83\xf8\x00', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'disassembly': 'CMP EAX, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_36(self):
''' Instruction CMP [RDI], DL '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 102L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {140737488345968: 'Z', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'text': '8\x17', 'pos': {'registers': {'RFLAGS': 643L, 'DL': 102L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {140737488345968: 'Z', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'disassembly': 'CMP [RDI], DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_37(self):
''' Instruction CMP DWORD [RIP+0x2bbb90], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199177L, 'RBP': 4782912L}, 'memory': {4199177L: '\x83', 4199178L: '=', 4199179L: '\x90', 4199180L: '\xbb', 4199181L: '+', 4199182L: '\x00', 4199183L: '\x00', 7065241: '\x00', 7065242: '\x00', 7065243: '\x00', 7065244: '\x00', 7065245: '\x00', 7065246: '\x00', 7065247: '\x00', 7065248: '\x00', 7065249: '\x00', 7065250: '\x00', 7065251: '\x00', 7065252: '\x00', 7065253: '\x00', 7065254: '\x00', 7065255: '\x00', 7065256: '\x00', 7065257: '\x00', 7065258: '\x00', 7065259: '\x00', 7065260: '\x00', 7065261: '\x00', 7065262: '\x00', 7065263: '\x00', 7065264: '\x00', 7065265: '\x00', 7065266: '\x00', 7065267: '\x00', 7065268: '\x00', 7065269: '\x00', 7065270: '\x00', 7065271: '\x00', 7065272: '\x00'}}, 'text': '\x83=\x90\xbb+\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199184L, 'RBP': 4782912L}, 'memory': {4199177L: '\x83', 4199178L: '=', 4199179L: '\x90', 4199180L: '\xbb', 4199181L: '+', 4199182L: '\x00', 4199183L: '\x00', 7065241: '\x00', 7065242: '\x00', 7065243: '\x00', 7065244: '\x00', 7065245: '\x00', 7065246: '\x00', 7065247: '\x00', 7065248: '\x00', 7065249: '\x00', 7065250: '\x00', 7065251: '\x00', 7065252: '\x00', 7065253: '\x00', 7065254: '\x00', 7065255: '\x00', 7065256: '\x00', 7065257: '\x00', 7065258: '\x00', 7065259: '\x00', 7065260: '\x00', 7065261: '\x00', 7065262: '\x00', 7065263: '\x00', 7065264: '\x00', 7065265: '\x00', 7065266: '\x00', 7065267: '\x00', 7065268: '\x00', 7065269: '\x00', 7065270: '\x00', 7065271: '\x00', 7065272: '\x00'}}, 'disassembly': 'CMP DWORD [RIP+0x2bbb90], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_38(self):
''' Instruction CMP BYTE [RBP-0x610], 0x20 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336755L, 'RBP': 140737488345936L}, 'memory': {140737488344384: ' ', 140737488344385: '\x00', 140737488344386: '\x00', 140737488344387: '\x00', 140737488344388: '\x00', 140737488344389: '\x00', 140737488344390: '\x00', 140737488344391: '\x00', 4336755L: '\x80', 4336756L: '\xbd', 4336757L: '\xf0', 4336758L: '\xf9', 4336759L: '\xff', 4336760L: '\xff', 4336761L: ' '}}, 'text': '\x80\xbd\xf0\xf9\xff\xff ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336762L, 'RBP': 140737488345936L}, 'memory': {140737488344384: ' ', 140737488344385: '\x00', 140737488344386: '\x00', 140737488344387: '\x00', 140737488344388: '\x00', 140737488344389: '\x00', 140737488344390: '\x00', 140737488344391: '\x00', 4336755L: '\x80', 4336756L: '\xbd', 4336757L: '\xf0', 4336758L: '\xf9', 4336759L: '\xff', 4336760L: '\xff', 4336761L: ' '}}, 'disassembly': 'CMP BYTE [RBP-0x610], 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_39(self):
''' Instruction CMP RAX, RSI '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737354125691L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'text': 'H9\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737354125691L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'disassembly': 'CMP RAX, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_4(self):
''' Instruction CMP EAX, 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'text': '\x83\xf8\x00', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'disassembly': 'CMP EAX, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_40(self):
''' Instruction CMP BYTE [RAX], 0x4d '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350562L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488350562: 'G', 140737488350563: 'N', 140737488350564: 'O', 140737488350565: 'M', 140737488350566: 'E', 140737488350567: '_', 140737488350568: 'D', 140737488350569: 'E'}}, 'text': '\x808M', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350562L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488350562: 'G', 140737488350563: 'N', 140737488350564: 'O', 140737488350565: 'M', 140737488350566: 'E', 140737488350567: '_', 140737488350568: 'D', 140737488350569: 'E'}}, 'disassembly': 'CMP BYTE [RAX], 0x4d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_41(self):
''' Instruction CMP R8, [RDX+0x8] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'R8': 7071872L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199002L, 'RBP': 4782912L}, 'memory': {7059456: '\x00', 7059457: '\x00', 7059458: '\x00', 7059459: '\x00', 7059460: '\x00', 7059461: '\x00', 7059462: '\x00', 7059463: '\x00', 7059464: '\x00', 7059465: '\x00', 7059466: '\x00', 7059467: '\x00', 7059468: '\x00', 7059469: '\x00', 7059470: '\x00', 7059471: '\x00', 7059472: '\x00', 7059473: '\x00', 7059474: '\x00', 7059475: '\x00', 7059476: '\x00', 7059477: '\x00', 7059478: '\x00', 7059479: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059416: '\x00', 7059417: '\x00', 4199002L: 'L', 4199003L: ';', 4199004L: 'B', 4199005L: '\x08', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 7059440: '\x00', 7059441: '\x00', 7059442: '\x00', 7059443: '\x00', 7059444: '\x00', 7059445: '\x00', 7059446: '\x00', 7059447: '\x00', 7059448: '\x00', 7059449: '\x00', 7059450: '\x00', 7059451: '\x00', 7059452: '\x00', 7059453: '\x00', 7059454: '\x00', 7059455: '\x00'}}, 'text': 'L;B\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 7049504L, 'R8': 7071872L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199006L, 'RBP': 4782912L}, 'memory': {7059456: '\x00', 7059457: '\x00', 7059458: '\x00', 7059459: '\x00', 7059460: '\x00', 7059461: '\x00', 7059462: '\x00', 7059463: '\x00', 7059464: '\x00', 7059465: '\x00', 7059466: '\x00', 7059467: '\x00', 7059468: '\x00', 7059469: '\x00', 7059470: '\x00', 7059471: '\x00', 7059472: '\x00', 7059473: '\x00', 7059474: '\x00', 7059475: '\x00', 7059476: '\x00', 7059477: '\x00', 7059478: '\x00', 7059479: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059416: '\x00', 7059417: '\x00', 4199002L: 'L', 4199003L: ';', 4199004L: 'B', 4199005L: '\x08', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 7059440: '\x00', 7059441: '\x00', 7059442: '\x00', 7059443: '\x00', 7059444: '\x00', 7059445: '\x00', 7059446: '\x00', 7059447: '\x00', 7059448: '\x00', 7059449: '\x00', 7059450: '\x00', 7059451: '\x00', 7059452: '\x00', 7059453: '\x00', 7059454: '\x00', 7059455: '\x00'}}, 'disassembly': 'CMP R8, [RDX+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_42(self):
''' Instruction CMP RAX, RSI '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 49L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 140737354125323L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'text': 'H9\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 49L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 140737354125323L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'disassembly': 'CMP RAX, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_43(self):
''' Instruction CMP ESI, 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'ESI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283785L, 'RBP': 194L}, 'memory': {4283785L: '\x83', 4283786L: '\xfe', 4283787L: '\x00'}}, 'text': '\x83\xfe\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'ESI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283788L, 'RBP': 194L}, 'memory': {4283785L: '\x83', 4283786L: '\xfe', 4283787L: '\x00'}}, 'disassembly': 'CMP ESI, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_44(self):
''' Instruction CMP DWORD [RBP-0x5d0], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338784L, 'RBP': 140737488345936L}, 'memory': {140737488344448: '\x00', 140737488344449: '\x00', 140737488344450: '\x00', 140737488344451: '\x00', 140737488344452: '\xff', 140737488344453: '\xff', 140737488344454: '\xff', 140737488344455: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 4338784L: '\x83', 4338785L: '\xbd', 4338786L: '0', 4338787L: '\xfa', 4338788L: '\xff', 4338789L: '\xff', 4338790L: '\x00'}}, 'text': '\x83\xbd0\xfa\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338791L, 'RBP': 140737488345936L}, 'memory': {140737488344448: '\x00', 140737488344449: '\x00', 140737488344450: '\x00', 140737488344451: '\x00', 140737488344452: '\xff', 140737488344453: '\xff', 140737488344454: '\xff', 140737488344455: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 4338784L: '\x83', 4338785L: '\xbd', 4338786L: '0', 4338787L: '\xfa', 4338788L: '\xff', 4338789L: '\xff', 4338790L: '\x00'}}, 'disassembly': 'CMP DWORD [RBP-0x5d0], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_45(self):
''' Instruction CMP RAX, RSI '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 52L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 140737354125651L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'text': 'H9\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 52L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 140737354125651L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'disassembly': 'CMP RAX, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_46(self):
''' Instruction CMP BYTE [RAX+0x1], 0x41 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488349535L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4213091L, 'RBP': 0L}, 'memory': {4213094L: 'A', 4213091L: '\x80', 4213092L: 'x', 4213093L: '\x01', 140737488349536: 'U', 140737488349537: 'L', 140737488349538: 'T', 140737488349539: 'I', 140737488349540: 'O', 140737488349541: 'S', 140737488349542: 'D', 140737488349543: 'I'}}, 'text': '\x80x\x01A', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488349535L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4213095L, 'RBP': 0L}, 'memory': {4213094L: 'A', 4213091L: '\x80', 4213092L: 'x', 4213093L: '\x01', 140737488349536: 'U', 140737488349537: 'L', 140737488349538: 'T', 140737488349539: 'I', 140737488349540: 'O', 140737488349541: 'S', 140737488349542: 'D', 140737488349543: 'I'}}, 'disassembly': 'CMP BYTE [RAX+0x1], 0x41', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_47(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488347858L}, 'memory': {140737488347872: '/', 140737488347873: 'o', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 140737488347858: 'V', 140737488347859: 'B', 140737488347860: 'O', 140737488347861: 'X', 140737488347862: '_', 140737488347863: 'A', 140737488347864: 'P', 140737488347865: 'P', 140737488347866: '_', 140737488347867: 'H', 140737488347868: 'O', 140737488347869: 'M', 140737488347870: 'E', 140737488347871: '='}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488347858L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488347873: 'o', 140737488347872: '/', 140737488347858: 'V', 140737488347859: 'B', 140737488347860: 'O', 140737488347861: 'X', 140737488347862: '_', 140737488347863: 'A', 140737488347864: 'P', 140737488347865: 'P', 140737488347866: '_', 140737488347867: 'H', 140737488347868: 'O', 140737488347869: 'M', 140737488347870: 'E', 140737488347871: '='}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_48(self):
''' Instruction CMP BYTE [R15], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 4793933L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322456L, 'RBP': 140737488346472L}, 'memory': {4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4322456L: 'A', 4322457L: '\x80', 4322458L: '?', 4322459L: '\x00'}}, 'text': 'A\x80?\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322460L, 'RBP': 140737488346472L}, 'memory': {4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4322456L: 'A', 4322457L: '\x80', 4322458L: '?', 4322459L: '\x00'}}, 'disassembly': 'CMP BYTE [R15], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_49(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488351047L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488351047: 'C', 140737488351048: 'O', 140737488351049: 'N', 140737488351050: 'F', 140737488351051: 'I', 140737488351052: 'G', 140737488351053: '_', 140737488351054: 'P', 140737488351055: 'R', 140737488351056: 'O', 140737488351057: 'T', 140737488351058: 'E', 140737488351059: 'C', 140737488351060: 'T', 140737488351061: '=', 140737488351062: '/'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322501L, 'RBP': 140737488351047L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488351047: 'C', 140737488351048: 'O', 140737488351049: 'N', 140737488351050: 'F', 140737488351051: 'I', 140737488351052: 'G', 140737488351053: '_', 140737488351054: 'P', 140737488351055: 'R', 140737488351056: 'O', 140737488351057: 'T', 140737488351058: 'E', 140737488351059: 'C', 140737488351060: 'T', 140737488351061: '=', 140737488351062: '/'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_5(self):
''' Instruction CMP R8, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'R8': 12L, 'RAX': 2147483642L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4338842L, 'RBP': 140737488345936L}, 'memory': {4338842L: 'I', 4338843L: '9', 4338844L: '\xc0'}}, 'text': 'I9\xc0', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'R8': 12L, 'RAX': 2147483642L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4338845L, 'RBP': 140737488345936L}, 'memory': {4338842L: 'I', 4338843L: '9', 4338844L: '\xc0'}}, 'disassembly': 'CMP R8, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_50(self):
''' Instruction CMP RDX, 0x7e0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051528L, 'RSP': 140737488345712L, 'RDX': 208L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'text': 'H\x81\xfa\xe0\x07\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051528L, 'RSP': 140737488345712L, 'RDX': 208L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'disassembly': 'CMP RDX, 0x7e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_51(self):
''' Instruction CMP EDX, 0x30 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'EDX': 16L, 'RAX': 4340492L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4340496L, 'RBP': 140737488345936L}, 'memory': {4340496L: '\x83', 4340497L: '\xfa', 4340498L: '0'}}, 'text': '\x83\xfa0', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'EDX': 16L, 'RAX': 4340492L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4340499L, 'RBP': 140737488345936L}, 'memory': {4340496L: '\x83', 4340497L: '\xfa', 4340498L: '0'}}, 'disassembly': 'CMP EDX, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_52(self):
''' Instruction CMP SIL, 0x9 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'SIL': 254L, 'RDI': 1L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 10L, 'RIP': 4299468L, 'RBP': 0L}, 'memory': {4299468L: '@', 4299469L: '\x80', 4299470L: '\xfe', 4299471L: '\t'}}, 'text': '@\x80\xfe\t', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'SIL': 254L, 'RDI': 1L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 10L, 'RIP': 4299472L, 'RBP': 0L}, 'memory': {4299468L: '@', 4299469L: '\x80', 4299470L: '\xfe', 4299471L: '\t'}}, 'disassembly': 'CMP SIL, 0x9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_53(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488347684L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 140737488347684: 'G', 140737488347685: 'P', 140737488347686: 'G', 140737488347687: '_', 140737488347688: 'A', 140737488347689: 'G', 140737488347690: 'E', 140737488347691: 'N', 140737488347692: 'T', 140737488347693: '_', 140737488347694: 'I', 140737488347695: 'N', 140737488347696: 'F', 140737488347697: 'O', 140737488347698: '=', 140737488347699: '/', 4322500L: '\x00'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488347684L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488347685: 'P', 140737488347686: 'G', 140737488347687: '_', 140737488347688: 'A', 140737488347689: 'G', 140737488347690: 'E', 140737488347691: 'N', 140737488347692: 'T', 140737488347693: '_', 140737488347694: 'I', 140737488347695: 'N', 140737488347696: 'F', 140737488347697: 'O', 140737488347698: '=', 140737488347699: '/', 140737488347684: 'G'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_54(self):
''' Instruction CMP RDX, 0x7e0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053336L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'text': 'H\x81\xfa\xe0\x07\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053336L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'disassembly': 'CMP RDX, 0x7e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_55(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488347858L}, 'memory': {140737488347872: '/', 140737488347873: 'o', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 140737488347858: 'V', 140737488347859: 'B', 140737488347860: 'O', 140737488347861: 'X', 140737488347862: '_', 140737488347863: 'A', 140737488347864: 'P', 140737488347865: 'P', 140737488347866: '_', 140737488347867: 'H', 140737488347868: 'O', 140737488347869: 'M', 140737488347870: 'E', 140737488347871: '='}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322501L, 'RBP': 140737488347858L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488347873: 'o', 140737488347872: '/', 140737488347858: 'V', 140737488347859: 'B', 140737488347860: 'O', 140737488347861: 'X', 140737488347862: '_', 140737488347863: 'A', 140737488347864: 'P', 140737488347865: 'P', 140737488347866: '_', 140737488347867: 'H', 140737488347868: 'O', 140737488347869: 'M', 140737488347870: 'E', 140737488347871: '='}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_56(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350544L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350544: 'H', 140737488350545: 'O', 140737488350546: 'M', 140737488350547: 'E', 140737488350548: '=', 140737488350549: '/', 140737488350550: 'h', 140737488350551: 'o', 140737488350552: 'm', 140737488350553: 'e', 140737488350554: '/', 140737488350555: 'f', 140737488350556: 'e', 140737488350557: 'l', 140737488350558: 'i', 140737488350559: 'p'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 643L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488350544L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350544: 'H', 140737488350545: 'O', 140737488350546: 'M', 140737488350547: 'E', 140737488350548: '=', 140737488350549: '/', 140737488350550: 'h', 140737488350551: 'o', 140737488350552: 'm', 140737488350553: 'e', 140737488350554: '/', 140737488350555: 'f', 140737488350556: 'e', 140737488350557: 'l', 140737488350558: 'i', 140737488350559: 'p'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_57(self):
''' Instruction CMP EAX, 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'text': '\x83\xf8\x00', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320778L: '\x83', 4320779L: '\xf8', 4320780L: '\x00'}}, 'disassembly': 'CMP EAX, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_58(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488350035L}, 'memory': {140737488350048: 'a', 140737488350049: 'l', 140737488350050: '/', 4322499L: 'm', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 140737488350035: 'P', 140737488350036: 'A', 140737488350037: 'T', 140737488350038: 'H', 140737488350039: '=', 140737488350040: '/', 140737488350041: 'u', 140737488350042: 's', 140737488350043: 'r', 140737488350044: '/', 140737488350045: 'l', 140737488350046: 'o', 140737488350047: 'c'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350035L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350049: 'l', 140737488350048: 'a', 140737488350050: '/', 140737488350035: 'P', 140737488350036: 'A', 140737488350037: 'T', 140737488350038: 'H', 140737488350039: '=', 140737488350040: '/', 140737488350041: 'u', 140737488350042: 's', 140737488350043: 'r', 140737488350044: '/', 140737488350045: 'l', 140737488350046: 'o', 140737488350047: 'c'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_59(self):
''' Instruction CMP DWORD [RBP-0x590], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336380L, 'RBP': 140737488345936L}, 'memory': {4336384L: '\xff', 4336385L: '\xff', 4336386L: '\x00', 140737488344515: '\x00', 140737488344516: '\x00', 140737488344517: '\x00', 140737488344518: '\x00', 140737488344513: '\x00', 140737488344520: '\x00', 140737488344521: '\x00', 140737488344522: '\x00', 140737488344523: '\x00', 140737488344524: '\x00', 140737488344514: '\x00', 140737488344526: '\x00', 140737488344525: '\x00', 140737488344528: '\xff', 140737488344529: '\xff', 140737488344530: '\xff', 140737488344531: '\xff', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344527: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344539: '\x00', 140737488344519: '\x00', 140737488344512: '\x00', 4336380L: '\x83', 4336381L: '\xbd', 4336382L: 'p', 4336383L: '\xfa'}}, 'text': '\x83\xbdp\xfa\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336387L, 'RBP': 140737488345936L}, 'memory': {4336384L: '\xff', 4336385L: '\xff', 4336386L: '\x00', 140737488344515: '\x00', 140737488344516: '\x00', 140737488344517: '\x00', 140737488344518: '\x00', 140737488344513: '\x00', 140737488344520: '\x00', 140737488344521: '\x00', 140737488344522: '\x00', 140737488344523: '\x00', 140737488344524: '\x00', 140737488344514: '\x00', 140737488344526: '\x00', 140737488344525: '\x00', 140737488344528: '\xff', 140737488344529: '\xff', 140737488344530: '\xff', 140737488344531: '\xff', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344527: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344539: '\x00', 140737488344519: '\x00', 140737488344512: '\x00', 4336380L: '\x83', 4336381L: '\xbd', 4336382L: 'p', 4336383L: '\xfa'}}, 'disassembly': 'CMP DWORD [RBP-0x590], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_6(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488351013L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488351013: 'R', 140737488351014: 'U', 140737488351015: 'B', 140737488351016: 'Y', 140737488351017: 'O', 140737488351018: 'P', 140737488351019: 'T', 140737488351020: '=', 140737488351021: '-', 140737488351022: 'r', 140737488351023: 'a', 140737488351024: 'u', 140737488351025: 't', 140737488351026: 'o', 140737488351027: '_', 140737488351028: 'g'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488351013L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488351013: 'R', 140737488351014: 'U', 140737488351015: 'B', 140737488351016: 'Y', 140737488351017: 'O', 140737488351018: 'P', 140737488351019: 'T', 140737488351020: '=', 140737488351021: '-', 140737488351022: 'r', 140737488351023: 'a', 140737488351024: 'u', 140737488351025: 't', 140737488351026: 'o', 140737488351027: '_', 140737488351028: 'g'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_60(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488349498L}, 'memory': {140737488349504: 'L', 140737488349505: 'O', 140737488349506: 'A', 140737488349507: 'D', 140737488349508: '_', 140737488349509: 'P', 140737488349510: 'A', 140737488349511: 'T', 140737488349512: 'H', 140737488349513: '=', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488349498: 'G', 140737488349499: 'U', 140737488349500: 'I', 140737488349501: 'L', 140737488349502: 'E', 140737488349503: '_'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488349498L}, 'memory': {140737488349504: 'L', 140737488349505: 'O', 140737488349506: 'A', 140737488349507: 'D', 140737488349508: '_', 140737488349509: 'P', 140737488349510: 'A', 140737488349511: 'T', 140737488349512: 'H', 140737488349513: '=', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488349498: 'G', 140737488349499: 'U', 140737488349500: 'I', 140737488349501: 'L', 140737488349502: 'E', 140737488349503: '_'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_61(self):
''' Instruction CMP RDX, 0x7e0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052296L, 'RSP': 140737488345712L, 'RDX': 976L, 'RIP': 4211144L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'text': 'H\x81\xfa\xe0\x07\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052296L, 'RSP': 140737488345712L, 'RDX': 976L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {4211144L: 'H', 4211145L: '\x81', 4211146L: '\xfa', 4211147L: '\xe0', 4211148L: '\x07', 4211149L: '\x00', 4211150L: '\x00'}}, 'disassembly': 'CMP RDX, 0x7e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_62(self):
''' Instruction CMP BYTE [RAX], 0x4d '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488347727L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {140737488347727: 'X', 4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488347731: 'M', 140737488347732: 'E', 140737488347733: 'N', 140737488347734: 'U', 140737488347728: 'D', 140737488347729: 'G', 140737488347730: '_'}}, 'text': '\x808M', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488347727L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {140737488347727: 'X', 140737488347728: 'D', 140737488347729: 'G', 140737488347730: '_', 140737488347731: 'M', 140737488347732: 'E', 140737488347733: 'N', 140737488347734: 'U', 4212880L: '\x80', 4212881L: '8', 4212882L: 'M'}}, 'disassembly': 'CMP BYTE [RAX], 0x4d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_63(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488350830L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350830: 'W', 140737488350831: 'I', 140737488350832: 'N', 140737488350833: 'D', 140737488350834: 'O', 140737488350835: 'W', 140737488350836: 'P', 140737488350837: 'A', 140737488350838: 'T', 140737488350839: 'H', 140737488350840: '=', 140737488350841: '7', 140737488350842: '\x00', 140737488350843: 'I', 140737488350844: 'N', 140737488350845: 'F'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350830L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350830: 'W', 140737488350831: 'I', 140737488350832: 'N', 140737488350833: 'D', 140737488350834: 'O', 140737488350835: 'W', 140737488350836: 'P', 140737488350837: 'A', 140737488350838: 'T', 140737488350839: 'H', 140737488350840: '=', 140737488350841: '7', 140737488350842: '\x00', 140737488350843: 'I', 140737488350844: 'N', 140737488350845: 'F'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_64(self):
''' Instruction CMP DWORD [RAX], 0x7 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194424L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196849L, 'RBP': 0L}, 'memory': {4194432: '\x00', 4194433: 'Y', 4194434: '\x0b', 4194435: '\x00', 4194436: '\x00', 4194437: '\x00', 4194438: '\x00', 4194439: '\x00', 4194440: '\x00', 4194441: 'Y', 4194442: 'k', 4194443: '\x00', 4194444: '\x00', 4194445: '\x00', 4194446: '\x00', 4194447: '\x00', 4194448: '\x00', 4194449: 'Y', 4194450: 'k', 4194451: '\x00', 4194452: '\x00', 4194453: '\x00', 4194454: '\x00', 4194455: '\x00', 4196849L: '\x83', 4196850L: '8', 4196851L: '\x07', 4194424: '\x01', 4194425: '\x00', 4194426: '\x00', 4194427: '\x00', 4194428: '\x06', 4194429: '\x00', 4194430: '\x00', 4194431: '\x00'}}, 'text': '\x838\x07', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194424L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196852L, 'RBP': 0L}, 'memory': {4194432: '\x00', 4194433: 'Y', 4194434: '\x0b', 4194435: '\x00', 4194436: '\x00', 4194437: '\x00', 4194438: '\x00', 4194439: '\x00', 4194440: '\x00', 4194441: 'Y', 4194442: 'k', 4194443: '\x00', 4194444: '\x00', 4194445: '\x00', 4194446: '\x00', 4194447: '\x00', 4194448: '\x00', 4194449: 'Y', 4194450: 'k', 4194451: '\x00', 4194452: '\x00', 4194453: '\x00', 4194454: '\x00', 4194455: '\x00', 4196849L: '\x83', 4196850L: '8', 4196851L: '\x07', 4194424: '\x01', 4194425: '\x00', 4194426: '\x00', 4194427: '\x00', 4194428: '\x06', 4194429: '\x00', 4194430: '\x00', 4194431: '\x00'}}, 'disassembly': 'CMP DWORD [RAX], 0x7', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_65(self):
''' Instruction CMP [RDI], DL '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 120L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {140737488345968: 'v', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'text': '8\x17', 'pos': {'registers': {'RFLAGS': 659L, 'DL': 120L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {140737488345968: 'v', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'disassembly': 'CMP [RDI], DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_66(self):
''' Instruction CMP BYTE [RAX], 0x4d '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488351013L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488351013: 'R', 140737488351014: 'U', 140737488351015: 'B', 140737488351016: 'Y', 140737488351017: 'O', 140737488351018: 'P', 140737488351019: 'T', 140737488351020: '='}}, 'text': '\x808M', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488351013L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488351013: 'R', 140737488351014: 'U', 140737488351015: 'B', 140737488351016: 'Y', 140737488351017: 'O', 140737488351018: 'P', 140737488351019: 'T', 140737488351020: '='}}, 'disassembly': 'CMP BYTE [RAX], 0x4d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_67(self):
''' Instruction CMP R14, [RSP] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 646L, 'R14': 0L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x04', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320740L: 'L', 4320741L: ';', 4320742L: '4', 4320743L: '$'}}, 'text': 'L;4$', 'pos': {'registers': {'RFLAGS': 663L, 'R14': 0L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x04', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320740L: 'L', 4320741L: ';', 4320742L: '4', 4320743L: '$'}}, 'disassembly': 'CMP R14, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_68(self):
''' Instruction CMP R13, 0x14 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'R13': 12L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392653L, 'RBP': 7049504L}, 'memory': {4392656L: '\x14', 4392653L: 'I', 4392654L: '\x83', 4392655L: '\xfd'}}, 'text': 'I\x83\xfd\x14', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'R13': 12L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392656L: '\x14', 4392653L: 'I', 4392654L: '\x83', 4392655L: '\xfd'}}, 'disassembly': 'CMP R13, 0x14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_69(self):
''' Instruction CMP QWORD [RBP-0x5b8], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337479L, 'RBP': 140737488345936L}, 'memory': {140737488344524: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x01', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\n', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00', 140737488344512: '\x03', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 140737488344516: '\x00', 140737488344517: '\x00', 140737488344518: '\x00', 140737488344519: '\x00', 140737488344520: '\x00', 4337481L: '\xbd', 140737488344522: '\x00', 140737488344523: '\x00', 4337484L: '\xff', 4337485L: '\xff', 140737488344526: '\x00', 140737488344525: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344521: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344527: '\x00', 4337486L: '\x00', 4337482L: 'H', 4337480L: '\x83', 4337479L: 'H', 4337483L: '\xfa', 140737488344533: '\x00'}}, 'text': 'H\x83\xbdH\xfa\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337487L, 'RBP': 140737488345936L}, 'memory': {140737488344524: '\x00', 140737488344519: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x01', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\n', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00', 140737488344512: '\x03', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 140737488344516: '\x00', 140737488344517: '\x00', 140737488344518: '\x00', 4337479L: 'H', 4337480L: '\x83', 4337481L: '\xbd', 4337482L: 'H', 4337483L: '\xfa', 4337484L: '\xff', 4337485L: '\xff', 4337486L: '\x00', 140737488344525: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344520: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344521: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344526: '\x00', 140737488344527: '\x00', 140737488344522: '\x00', 140737488344530: '\x00', 140737488344523: '\x00', 140737488344533: '\x00'}}, 'disassembly': 'CMP QWORD [RBP-0x5b8], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_7(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488350013L}, 'memory': {140737488350016: 'K', 140737488350017: 'T', 140737488350018: 'O', 140737488350019: 'P', 140737488350020: '_', 140737488350021: 'S', 140737488350022: 'E', 140737488350023: 'S', 140737488350024: 'S', 140737488350025: 'I', 140737488350026: 'O', 140737488350027: 'N', 140737488350028: '=', 4322498L: ';', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 4322496L: 'f', 140737488350013: 'D', 140737488350014: 'E', 140737488350015: 'S'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488350013L}, 'memory': {140737488350016: 'K', 140737488350017: 'T', 140737488350018: 'O', 140737488350019: 'P', 140737488350020: '_', 140737488350021: 'S', 140737488350022: 'E', 140737488350023: 'S', 140737488350024: 'S', 140737488350025: 'I', 140737488350026: 'O', 140737488350027: 'N', 140737488350028: '=', 4322498L: ';', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 4322496L: 'f', 140737488350013: 'D', 140737488350014: 'E', 140737488350015: 'S'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_70(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350751L}, 'memory': {140737488350752: 'D', 140737488350753: 'G', 140737488350754: '_', 140737488350755: 'D', 140737488350756: 'A', 140737488350757: 'T', 140737488350758: 'A', 140737488350759: '_', 140737488350760: 'D', 140737488350761: 'I', 140737488350762: 'R', 140737488350763: 'S', 140737488350764: '=', 140737488350765: '/', 140737488350766: 'u', 4322498L: ';', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 4322496L: 'f', 140737488350751: 'X'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 643L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488350751L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350757: 'T', 140737488350758: 'A', 140737488350753: 'G', 140737488350760: 'D', 140737488350761: 'I', 140737488350762: 'R', 140737488350759: '_', 140737488350764: '=', 140737488350754: '_', 140737488350766: 'u', 140737488350765: '/', 140737488350755: 'D', 140737488350752: 'D', 140737488350756: 'A', 140737488350763: 'S', 140737488350751: 'X'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_71(self):
''' Instruction CMP DWORD [RBP-0x63c], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4338307L, 'RBP': 140737488345936L}, 'memory': {4338307L: '\x83', 4338308L: '\xbd', 4338309L: '\xc4', 4338310L: '\xf9', 4338311L: '\xff', 4338312L: '\xff', 4338313L: '\x00', 140737488344340: '\x00', 140737488344341: '\x00', 140737488344342: '\x00', 140737488344343: '\x00', 140737488344344: '\x00', 140737488344345: '\x00', 140737488344346: '\x00', 140737488344347: '\x00', 140737488344348: '\x00', 140737488344349: '\x00', 140737488344350: '\x00', 140737488344351: '\x00', 140737488344352: '\x00', 140737488344353: '\x00', 140737488344354: '\x00', 140737488344355: '\x00', 140737488344356: '\x00', 140737488344357: '\x00', 140737488344358: '\x00', 140737488344359: '\x00', 140737488344360: '\x00', 140737488344361: '\x00', 140737488344362: '\x00', 140737488344363: '\x00', 140737488344364: '\x00', 140737488344365: '\x00', 140737488344366: '\x00', 140737488344367: '\x00', 140737488344368: '\x00', 140737488344369: '\x00', 140737488344370: '\x00', 140737488344371: '\x00'}}, 'text': '\x83\xbd\xc4\xf9\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4338314L, 'RBP': 140737488345936L}, 'memory': {4338307L: '\x83', 4338308L: '\xbd', 4338309L: '\xc4', 4338310L: '\xf9', 4338311L: '\xff', 4338312L: '\xff', 4338313L: '\x00', 140737488344340: '\x00', 140737488344341: '\x00', 140737488344342: '\x00', 140737488344343: '\x00', 140737488344344: '\x00', 140737488344345: '\x00', 140737488344346: '\x00', 140737488344347: '\x00', 140737488344348: '\x00', 140737488344349: '\x00', 140737488344350: '\x00', 140737488344351: '\x00', 140737488344352: '\x00', 140737488344353: '\x00', 140737488344354: '\x00', 140737488344355: '\x00', 140737488344356: '\x00', 140737488344357: '\x00', 140737488344358: '\x00', 140737488344359: '\x00', 140737488344360: '\x00', 140737488344361: '\x00', 140737488344362: '\x00', 140737488344363: '\x00', 140737488344364: '\x00', 140737488344365: '\x00', 140737488344366: '\x00', 140737488344367: '\x00', 140737488344368: '\x00', 140737488344369: '\x00', 140737488344370: '\x00', 140737488344371: '\x00'}}, 'disassembly': 'CMP DWORD [RBP-0x63c], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_72(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350196L}, 'memory': {140737488350208: 'L', 140737488350209: 'O', 140737488350210: 'C', 140737488350211: 'A', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 140737488350196: 'G', 140737488350197: 'D', 140737488350198: 'M', 140737488350199: '_', 140737488350200: 'X', 140737488350201: 'S', 140737488350202: 'E', 140737488350203: 'R', 140737488350204: 'V', 140737488350205: 'E', 140737488350206: 'R', 140737488350207: '_'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488350196L}, 'memory': {140737488350208: 'L', 140737488350209: 'O', 140737488350210: 'C', 140737488350211: 'A', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 140737488350196: 'G', 140737488350197: 'D', 140737488350198: 'M', 140737488350199: '_', 140737488350200: 'X', 140737488350201: 'S', 140737488350202: 'E', 140737488350203: 'R', 140737488350204: 'V', 140737488350205: 'E', 140737488350206: 'R', 140737488350207: '_'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_73(self):
''' Instruction CMP RAX, RSI '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 115L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737354125678L, 'RSP': 140737488344192L, 'RDX': 4783032L, 'RIP': 4392701L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'text': 'H9\xf0', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 115L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737354125678L, 'RSP': 140737488344192L, 'RDX': 4783032L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392701L: 'H', 4392702L: '9', 4392703L: '\xf0'}}, 'disassembly': 'CMP RAX, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_74(self):
''' Instruction CMP BYTE [R15], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 4794037L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322456L, 'RBP': 140737488346472L}, 'memory': {4322456L: 'A', 4322457L: '\x80', 4322458L: '?', 4322459L: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M'}}, 'text': 'A\x80?\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322460L, 'RBP': 140737488346472L}, 'memory': {4322456L: 'A', 4322457L: '\x80', 4322458L: '?', 4322459L: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M'}}, 'disassembly': 'CMP BYTE [R15], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_75(self):
''' Instruction CMP QWORD [RBP-0x5b8], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337479L, 'RBP': 140737488345936L}, 'memory': {140737488344524: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x03', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\n', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00', 140737488344512: ',', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 140737488344516: '\x00', 140737488344517: '\x00', 140737488344518: '\x00', 140737488344519: '\x00', 140737488344520: '\x00', 4337481L: '\xbd', 140737488344522: '\x00', 140737488344523: '\x00', 4337484L: '\xff', 4337485L: '\xff', 140737488344526: '\x00', 140737488344525: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344521: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344527: '\x00', 4337486L: '\x00', 4337482L: 'H', 4337480L: '\x83', 4337479L: 'H', 4337483L: '\xfa', 140737488344533: '\x00'}}, 'text': 'H\x83\xbdH\xfa\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337487L, 'RBP': 140737488345936L}, 'memory': {140737488344524: '\x00', 140737488344519: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x03', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\n', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00', 140737488344512: ',', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 140737488344516: '\x00', 140737488344517: '\x00', 140737488344518: '\x00', 4337479L: 'H', 4337480L: '\x83', 4337481L: '\xbd', 4337482L: 'H', 4337483L: '\xfa', 4337484L: '\xff', 4337485L: '\xff', 4337486L: '\x00', 140737488344525: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344520: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344521: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344526: '\x00', 140737488344527: '\x00', 140737488344522: '\x00', 140737488344530: '\x00', 140737488344523: '\x00', 140737488344533: '\x00'}}, 'disassembly': 'CMP QWORD [RBP-0x5b8], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_76(self):
''' Instruction CMP AL, 0x2e '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RAX': 46L, 'RDI': 1L, 'RBP': 0L, 'RSP': 140737488345728L, 'AL': 46L, 'RIP': 4299482L, 'RDX': 3L}, 'memory': {4299482L: '<', 4299483L: '.'}}, 'text': '<.', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RAX': 46L, 'RDI': 1L, 'RBP': 0L, 'RSP': 140737488345728L, 'AL': 46L, 'RIP': 4299484L, 'RDX': 3L}, 'memory': {4299482L: '<', 4299483L: '.'}}, 'disassembly': 'CMP AL, 0x2e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_77(self):
''' Instruction CMP EAX, 0x3 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'EAX': 3L, 'RFLAGS': 514L, 'RCX': 4095L, 'RSI': 62914623L, 'RDI': 4L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284048L, 'RBP': 9L}, 'memory': {4284048L: '\x83', 4284049L: '\xf8', 4284050L: '\x03'}}, 'text': '\x83\xf8\x03', 'pos': {'registers': {'EAX': 3L, 'RFLAGS': 582L, 'RCX': 4095L, 'RSI': 62914623L, 'RDI': 4L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284051L, 'RBP': 9L}, 'memory': {4284048L: '\x83', 4284049L: '\xf8', 4284050L: '\x03'}}, 'disassembly': 'CMP EAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_78(self):
''' Instruction CMP [RDI], DL '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 134L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {140737488345968: 'v', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'text': '8\x17', 'pos': {'registers': {'RFLAGS': 2695L, 'DL': 134L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {140737488345968: 'v', 140737488345969: '\x00', 140737488345970: '\x00', 140737488345971: '\x00', 140737488345972: '\x00', 4283333L: '8', 4283334L: '\x17', 140737488345975: '\x00', 140737488345974: '\x00', 140737488345973: '\x00'}}, 'disassembly': 'CMP [RDI], DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_79(self):
''' Instruction CMP R15D, 0x3 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R15D': 1L, 'RFLAGS': 514L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221044L, 'RBP': 7051232L}, 'memory': {4221044L: 'A', 4221045L: '\x83', 4221046L: '\xff', 4221047L: '\x03'}}, 'text': 'A\x83\xff\x03', 'pos': {'registers': {'R15D': 1L, 'RFLAGS': 659L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221048L, 'RBP': 7051232L}, 'memory': {4221044L: 'A', 4221045L: '\x83', 4221046L: '\xff', 4221047L: '\x03'}}, 'disassembly': 'CMP R15D, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_8(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488347766L}, 'memory': {140737488347776: '\x00', 140737488347777: 'X', 140737488347778: 'D', 140737488347779: 'G', 140737488347780: '_', 140737488347781: 'S', 4322497L: 'D', 140737488347772: 't', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 140737488347766: 'T', 140737488347767: 'E', 140737488347768: 'R', 4322500L: '\x00', 140737488347770: '=', 140737488347771: 'x', 140737488347769: 'M', 140737488347773: 'e', 140737488347774: 'r', 140737488347775: 'm'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 643L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488347766L}, 'memory': {140737488347776: '\x00', 140737488347777: 'X', 140737488347778: 'D', 140737488347779: 'G', 140737488347780: '_', 140737488347781: 'S', 4322497L: 'D', 140737488347772: 't', 4322496L: 'f', 4322498L: ';', 4322499L: 'm', 140737488347766: 'T', 140737488347767: 'E', 140737488347768: 'R', 4322500L: '\x00', 140737488347770: '=', 140737488347771: 'x', 140737488347769: 'M', 140737488347773: 'e', 140737488347774: 'r', 140737488347775: 'm'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_80(self):
''' Instruction CMP RSI, -0x41 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219332L, 'RBP': 7051232L}, 'memory': {4219332L: 'H', 4219333L: '\x83', 4219334L: '\xfe', 4219335L: '\xbf'}}, 'text': 'H\x83\xfe\xbf', 'pos': {'registers': {'RFLAGS': 535L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219336L, 'RBP': 7051232L}, 'memory': {4219332L: 'H', 4219333L: '\x83', 4219334L: '\xfe', 4219335L: '\xbf'}}, 'disassembly': 'CMP RSI, -0x41', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_81(self):
''' Instruction CMP DWORD [RIP+0x2b1e99], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239808L, 'RBP': 6L}, 'memory': {4239808L: '\x83', 4239809L: '=', 4239810L: '\x99', 4239811L: '\x1e', 4239812L: '+', 4239813L: '\x00', 4239814L: '\x00', 7065689: '\x00', 7065690: '\x00', 7065691: '\x00', 7065692: '\x00', 7065693: '\x00', 7065694: '\x00', 7065695: '\x00', 7065696: '\x01', 7065697: '\x00', 7065698: '\x00', 7065699: '\x00', 7065700: '\r', 7065701: '\x00', 7065702: '\x00', 7065703: '\x00', 7065704: '\xa7', 7065705: '\x06', 7065706: '\x02', 7065707: '\x00', 7065708: '\x00', 7065709: '\x08', 7065710: '\x10', 7065711: '\x02', 7065712: '\xff', 7065713: '\xe3', 7065714: '\xba', 7065715: '\x1f', 7065716: '\xff', 7065717: '\xfb', 7065718: '\xeb', 7065719: '\xbf', 7065720: '\x00'}}, 'text': '\x83=\x99\x1e+\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239815L, 'RBP': 6L}, 'memory': {4239808L: '\x83', 4239809L: '=', 4239810L: '\x99', 4239811L: '\x1e', 4239812L: '+', 4239813L: '\x00', 4239814L: '\x00', 7065689: '\x00', 7065690: '\x00', 7065691: '\x00', 7065692: '\x00', 7065693: '\x00', 7065694: '\x00', 7065695: '\x00', 7065696: '\x01', 7065697: '\x00', 7065698: '\x00', 7065699: '\x00', 7065700: '\r', 7065701: '\x00', 7065702: '\x00', 7065703: '\x00', 7065704: '\xa7', 7065705: '\x06', 7065706: '\x02', 7065707: '\x00', 7065708: '\x00', 7065709: '\x08', 7065710: '\x10', 7065711: '\x02', 7065712: '\xff', 7065713: '\xe3', 7065714: '\xba', 7065715: '\x1f', 7065716: '\xff', 7065717: '\xfb', 7065718: '\xeb', 7065719: '\xbf', 7065720: '\x00'}}, 'disassembly': 'CMP DWORD [RIP+0x2b1e99], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_82(self):
''' Instruction CMP EBP, 0x3 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'EBP': 3L, 'RAX': 1L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284106L, 'RBP': 3L}, 'memory': {4284106L: '\x83', 4284107L: '\xfd', 4284108L: '\x03'}}, 'text': '\x83\xfd\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'EBP': 3L, 'RAX': 1L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284109L, 'RBP': 3L}, 'memory': {4284106L: '\x83', 4284107L: '\xfd', 4284108L: '\x03'}}, 'disassembly': 'CMP EBP, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_83(self):
''' Instruction CMP EDX, 0xa '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 43L, 'EDX': 10L, 'RAX': 43L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327569L, 'RBP': 140737488345936L}, 'memory': {4327569L: '\x83', 4327570L: '\xfa', 4327571L: '\n'}}, 'text': '\x83\xfa\n', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 43L, 'EDX': 10L, 'RAX': 43L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327572L, 'RBP': 140737488345936L}, 'memory': {4327569L: '\x83', 4327570L: '\xfa', 4327571L: '\n'}}, 'disassembly': 'CMP EDX, 0xa', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_84(self):
''' Instruction CMP ECX, 0x30 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'ECX': 5L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239596L: '\x83', 4239597L: '\xf9', 4239598L: '0'}}, 'text': '\x83\xf90', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'ECX': 5L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239599L, 'RBP': 140737488346472L}, 'memory': {4239596L: '\x83', 4239597L: '\xf9', 4239598L: '0'}}, 'disassembly': 'CMP ECX, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_85(self):
''' Instruction CMP BYTE [RAX], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297566L, 'RBP': 140737488346472L}, 'memory': {4297566L: '\x80', 4297567L: '8', 4297568L: '\x00', 4864625: '\x00', 4864626: '\x02', 4864627: '\x00', 4864628: '%', 4864629: 'a', 4864630: ' ', 4864631: '%', 4864632: 'b'}}, 'text': '\x808\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297569L, 'RBP': 140737488346472L}, 'memory': {4297566L: '\x80', 4297567L: '8', 4297568L: '\x00', 4864625: '\x00', 4864626: '\x02', 4864627: '\x00', 4864628: '%', 4864629: 'a', 4864630: ' ', 4864631: '%', 4864632: 'b'}}, 'disassembly': 'CMP BYTE [RAX], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_86(self):
''' Instruction CMP RAX, -0x1 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 7209408L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239566L, 'RBP': 7051232L}, 'memory': {4239568L: '\xf8', 4239569L: '\xff', 4239566L: 'H', 4239567L: '\x83'}}, 'text': 'H\x83\xf8\xff', 'pos': {'registers': {'RFLAGS': 531L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 7209408L, 'RSP': 140737488345808L, 'RDX': 0L, 'RIP': 4239570L, 'RBP': 7051232L}, 'memory': {4239568L: '\xf8', 4239569L: '\xff', 4239566L: 'H', 4239567L: '\x83'}}, 'disassembly': 'CMP RAX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_87(self):
''' Instruction CMP DWORD [R13+0x8], 0x25 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'R13': 4194960L, 'RAX': 4664208L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197567L, 'RBP': 7L}, 'memory': {4197568L: '\x83', 4197569L: '}', 4197570L: '\x08', 4197571L: '%', 4194968: '%', 4194969: '\x00', 4194970: '\x00', 4194971: '\x00', 4194972: '\x00', 4194973: '\x00', 4194974: '\x00', 4194975: '\x00', 4194976: '0', 4194977: '\xbd', 4194978: 'C', 4194979: '\x00', 4194980: '\x00', 4194981: '\x00', 4194982: '\x00', 4194983: '\x00', 4194984: '\xf8', 4194985: '\x88', 4194986: 'k', 4194987: '\x00', 4194988: '\x00', 4194989: '\x00', 4194990: '\x00', 4194991: '\x00', 4194992: '%', 4194993: '\x00', 4194994: '\x00', 4194995: '\x00', 4194996: '\x00', 4194997: '\x00', 4194998: '\x00', 4194999: '\x00', 4197567L: 'A'}}, 'text': 'A\x83}\x08%', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4664208L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197572L, 'RBP': 7L}, 'memory': {4197568L: '\x83', 4197569L: '}', 4197570L: '\x08', 4197571L: '%', 4194968: '%', 4194969: '\x00', 4194970: '\x00', 4194971: '\x00', 4194972: '\x00', 4194973: '\x00', 4194974: '\x00', 4194975: '\x00', 4194976: '0', 4194977: '\xbd', 4194978: 'C', 4194979: '\x00', 4194980: '\x00', 4194981: '\x00', 4194982: '\x00', 4194983: '\x00', 4194984: '\xf8', 4194985: '\x88', 4194986: 'k', 4194987: '\x00', 4194988: '\x00', 4194989: '\x00', 4194990: '\x00', 4194991: '\x00', 4194992: '%', 4194993: '\x00', 4194994: '\x00', 4194995: '\x00', 4194996: '\x00', 4194997: '\x00', 4194998: '\x00', 4194999: '\x00', 4197567L: 'A'}}, 'disassembly': 'CMP DWORD [R13+0x8], 0x25', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_88(self):
''' Instruction CMP R14, [RSP] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 646L, 'R14': 35L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {140737488345888: "'", 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320740L: 'L', 4320741L: ';', 4320742L: '4', 4320743L: '$'}}, 'text': 'L;4$', 'pos': {'registers': {'RFLAGS': 663L, 'R14': 35L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {140737488345888: "'", 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: 'v', 140737488345913: '\x00', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320740L: 'L', 4320741L: ';', 4320742L: '4', 4320743L: '$'}}, 'disassembly': 'CMP R14, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_89(self):
''' Instruction CMP R14, [RSP] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 646L, 'R14': 0L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x02', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320740L: 'L', 4320741L: ';', 4320742L: '4', 4320743L: '$'}}, 'text': 'L;4$', 'pos': {'registers': {'RFLAGS': 659L, 'R14': 0L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x02', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320740L: 'L', 4320741L: ';', 4320742L: '4', 4320743L: '$'}}, 'disassembly': 'CMP R14, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_9(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488350642L}, 'memory': {140737488350656: 'S', 140737488350657: '_', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 140737488350642: 'G', 140737488350643: 'C', 140737488350644: 'C', 140737488350645: '_', 140737488350646: 'S', 140737488350647: 'P', 140737488350648: 'E', 140737488350649: 'C', 140737488350650: 'S', 140737488350651: '=', 140737488350652: '\x00', 140737488350653: 'D', 140737488350654: 'B', 140737488350655: 'U'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350642L}, 'memory': {140737488350656: 'S', 140737488350657: '_', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 4322497L: 'D', 4322496L: 'f', 140737488350642: 'G', 140737488350643: 'C', 140737488350644: 'C', 140737488350645: '_', 140737488350646: 'S', 140737488350647: 'P', 140737488350648: 'E', 140737488350649: 'C', 140737488350650: 'S', 140737488350651: '=', 140737488350652: '\x00', 140737488350653: 'D', 140737488350654: 'B', 140737488350655: 'U'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_90(self):
''' Instruction CMP RDX, 0x400 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244464L, 'RBP': 7049504L}, 'memory': {4244464L: 'H', 4244465L: '\x81', 4244466L: '\xfa', 4244467L: '\x00', 4244468L: '\x04', 4244469L: '\x00', 4244470L: '\x00'}}, 'text': 'H\x81\xfa\x00\x04\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244471L, 'RBP': 7049504L}, 'memory': {4244464L: 'H', 4244465L: '\x81', 4244466L: '\xfa', 4244467L: '\x00', 4244468L: '\x04', 4244469L: '\x00', 4244470L: '\x00'}}, 'disassembly': 'CMP RDX, 0x400', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_91(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322496L, 'RBP': 140737488350381L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350381: 'E', 140737488350382: 'D', 140737488350383: 'I', 140737488350384: 'T', 140737488350385: 'O', 140737488350386: 'R', 140737488350387: '=', 140737488350388: '/', 140737488350389: 'b', 140737488350390: 'i', 140737488350391: 'n', 140737488350392: '/', 140737488350393: 'n', 140737488350394: 'a', 140737488350395: 'n', 140737488350396: 'o'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322501L, 'RBP': 140737488350381L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350381: 'E', 140737488350382: 'D', 140737488350383: 'I', 140737488350384: 'T', 140737488350385: 'O', 140737488350386: 'R', 140737488350387: '=', 140737488350388: '/', 140737488350389: 'b', 140737488350390: 'i', 140737488350391: 'n', 140737488350392: '/', 140737488350393: 'n', 140737488350394: 'a', 140737488350395: 'n', 140737488350396: 'o'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_92(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350843L}, 'memory': {140737488350848: 'A', 140737488350849: 'T', 140737488350850: 'H', 140737488350851: '=', 140737488350852: '/', 140737488350853: 'u', 140737488350854: 's', 140737488350855: 'r', 140737488350856: '/', 140737488350857: 's', 140737488350858: 'h', 4322496L: 'f', 4322498L: ';', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 140737488350843: 'I', 140737488350844: 'N', 140737488350845: 'F', 140737488350846: 'O', 140737488350847: 'P'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 647L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488350843L}, 'memory': {140737488350848: 'A', 140737488350849: 'T', 140737488350850: 'H', 140737488350851: '=', 140737488350852: '/', 140737488350853: 'u', 140737488350854: 's', 140737488350855: 'r', 140737488350856: '/', 140737488350857: 's', 140737488350858: 'h', 4322496L: 'f', 4322498L: ';', 4322497L: 'D', 4322499L: 'm', 4322500L: '\x00', 140737488350843: 'I', 140737488350844: 'N', 140737488350845: 'F', 140737488350846: 'O', 140737488350847: 'P'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_93(self):
''' Instruction CMP R13W, [RBP+0x0] '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488350381L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350381: 'E', 140737488350382: 'D', 140737488350383: 'I', 140737488350384: 'T', 140737488350385: 'O', 140737488350386: 'R', 140737488350387: '=', 140737488350388: '/', 140737488350389: 'b', 140737488350390: 'i', 140737488350391: 'n', 140737488350392: '/', 140737488350393: 'n', 140737488350394: 'a', 140737488350395: 'n', 140737488350396: 'o'}}, 'text': 'fD;m\x00', 'pos': {'registers': {'R13W': 17484L, 'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488350381L}, 'memory': {4322496L: 'f', 4322497L: 'D', 4322498L: ';', 4322499L: 'm', 4322500L: '\x00', 140737488350381: 'E', 140737488350382: 'D', 140737488350383: 'I', 140737488350384: 'T', 140737488350385: 'O', 140737488350386: 'R', 140737488350387: '=', 140737488350388: '/', 140737488350389: 'b', 140737488350390: 'i', 140737488350391: 'n', 140737488350392: '/', 140737488350393: 'n', 140737488350394: 'a', 140737488350395: 'n', 140737488350396: 'o'}}, 'disassembly': 'CMP R13W, [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_94(self):
''' Instruction CMP RBX, RAX '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RBX': 699L, 'RDI': 0L, 'RAX': 699L, 'RSP': 140737488345984L, 'RDX': 18446744073709551615L, 'RIP': 4394917L, 'RBP': 7049504L}, 'memory': {4394917L: 'H', 4394918L: '9', 4394919L: '\xc3'}}, 'text': 'H9\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RBX': 699L, 'RDI': 0L, 'RAX': 699L, 'RSP': 140737488345984L, 'RDX': 18446744073709551615L, 'RIP': 4394920L, 'RBP': 7049504L}, 'memory': {4394917L: 'H', 4394918L: '9', 4394919L: '\xc3'}}, 'disassembly': 'CMP RBX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_95(self):
''' Instruction CMP RAX, RDI '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392518L, 'RBP': 7049504L}, 'memory': {4392520L: '\xf8', 4392518L: 'H', 4392519L: '9'}}, 'text': 'H9\xf8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392520L: '\xf8', 4392518L: 'H', 4392519L: '9'}}, 'disassembly': 'CMP RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_96(self):
''' Instruction CMP DWORD [RBP-0x590], 0x0 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4782905L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339585L, 'RBP': 140737488345936L}, 'memory': {140737488344512: '\x00', 4339585L: '\x83', 4339586L: '\xbd', 4339587L: 'p', 4339588L: '\xfa', 4339589L: '\xff', 4339590L: '\xff', 4339591L: '\x00', 140737488344520: '\x00', 140737488344521: '\x00', 140737488344522: '\x00', 140737488344523: '\x00', 140737488344524: '\x00', 140737488344514: '\x00', 140737488344526: '\x00', 140737488344525: '\x00', 140737488344528: '\xff', 140737488344529: '\xff', 140737488344513: '\x00', 140737488344515: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344516: '\x00', 140737488344538: '\x00', 140737488344527: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344517: '\x00', 140737488344537: '\x00', 140737488344539: '\x00', 140737488344518: '\x00', 140737488344519: '\x00', 140737488344530: '\xff', 140737488344531: '\xff', 140737488344543: '\x00'}}, 'text': '\x83\xbdp\xfa\xff\xff\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4782905L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339592L, 'RBP': 140737488345936L}, 'memory': {140737488344512: '\x00', 4339585L: '\x83', 4339586L: '\xbd', 4339587L: 'p', 4339588L: '\xfa', 4339589L: '\xff', 4339590L: '\xff', 4339591L: '\x00', 140737488344520: '\x00', 140737488344521: '\x00', 140737488344522: '\x00', 140737488344523: '\x00', 140737488344524: '\x00', 140737488344514: '\x00', 140737488344526: '\x00', 140737488344525: '\x00', 140737488344528: '\xff', 140737488344529: '\xff', 140737488344513: '\x00', 140737488344515: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344516: '\x00', 140737488344538: '\x00', 140737488344527: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344517: '\x00', 140737488344537: '\x00', 140737488344539: '\x00', 140737488344518: '\x00', 140737488344519: '\x00', 140737488344530: '\xff', 140737488344531: '\xff', 140737488344543: '\x00'}}, 'disassembly': 'CMP DWORD [RBP-0x590], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_97(self):
''' Instruction CMP BYTE [RAX], 0x4d '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350498L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488350498: 'J', 140737488350499: 'D', 140737488350500: 'K', 140737488350501: '_', 140737488350502: 'H', 140737488350503: 'O', 140737488350504: 'M', 140737488350505: 'E'}}, 'text': '\x808M', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350498L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212880L: '\x80', 4212881L: '8', 4212882L: 'M', 140737488350498: 'J', 140737488350499: 'D', 140737488350500: 'K', 140737488350501: '_', 140737488350502: 'H', 140737488350503: 'O', 140737488350504: 'M', 140737488350505: 'E'}}, 'disassembly': 'CMP BYTE [RAX], 0x4d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_98(self):
''' Instruction CMP RAX, 0x20 '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219372L, 'RBP': 7051232L}, 'memory': {4219372L: 'H', 4219373L: '\x83', 4219374L: '\xf8', 4219375L: ' '}}, 'text': 'H\x83\xf8 ', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219376L, 'RBP': 7051232L}, 'memory': {4219372L: 'H', 4219373L: '\x83', 4219374L: '\xf8', 4219375L: ' '}}, 'disassembly': 'CMP RAX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testCMP_99(self):
''' Instruction CMP R10D, 0xa '''
test = {'mnemonic': 'CMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4095L, 'RSI': 4194304L, 'RAX': 28687L, 'RDI': 0L, 'R10D': 13L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4284998L, 'RBP': 32768L}, 'memory': {4285000L: '\xfa', 4285001L: '\n', 4284998L: 'A', 4284999L: '\x83'}}, 'text': 'A\x83\xfa\n', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4095L, 'RSI': 4194304L, 'RAX': 28687L, 'RDI': 0L, 'R10D': 13L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4285002L, 'RBP': 32768L}, 'memory': {4285000L: '\xfa', 4285001L: '\n', 4284998L: 'A', 4284999L: '\x83'}}, 'disassembly': 'CMP R10D, 0xa', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_1(self):
''' Instruction DEC DWORD [RDX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329994L, 'RBP': 140737488345936L}, 'memory': {4329994L: '\xff', 4329995L: '\n', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'text': '\xff\n', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329996L, 'RBP': 140737488345936L}, 'memory': {4329994L: '\xff', 4329995L: '\n', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'disassembly': 'DEC DWORD [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_10(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125727L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125727L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_11(self):
''' Instruction DEC DWORD [RDX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4206155L, 'RBP': 1L}, 'memory': {4206155L: '\xff', 4206156L: '\n', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'text': '\xff\n', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4206157L, 'RBP': 1L}, 'memory': {4206155L: '\xff', 4206156L: '\n', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'disassembly': 'DEC DWORD [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_12(self):
''' Instruction DEC DWORD [RBP+0x0] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346032L, 'RDX': 1617L, 'RIP': 4230181L, 'RBP': 7051232L}, 'memory': {7051243: '\x00', 7051257: '\x00', 7051237: '\x00', 7051232: '\x01', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01', 4230181L: '\xff', 4230182L: 'M', 4230183L: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051239: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 7051247: '\x00', 7051248: '\x00', 7051249: '\x00', 7051250: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051238: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'text': '\xffM\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346032L, 'RDX': 1617L, 'RIP': 4230184L, 'RBP': 7051232L}, 'memory': {7051243: '\x00', 7051257: '\x00', 7051237: '\x00', 7051232: '\x00', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01', 4230181L: '\xff', 4230182L: 'M', 4230183L: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051239: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 7051247: '\x00', 7051248: '\x00', 7051249: '\x00', 7051250: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051238: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'disassembly': 'DEC DWORD [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_13(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125964L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125964L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_14(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125885L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125885L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_15(self):
''' Instruction DEC DWORD [RDX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329994L, 'RBP': 140737488345936L}, 'memory': {4329994L: '\xff', 4329995L: '\n', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'text': '\xff\n', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329996L, 'RBP': 140737488345936L}, 'memory': {4329994L: '\xff', 4329995L: '\n', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'disassembly': 'DEC DWORD [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_16(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 7035136L, 'ECX': 1L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245632L, 'RBP': 80L}, 'memory': {4245632L: '\xff', 4245633L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035136L, 'ECX': 0L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245634L, 'RBP': 80L}, 'memory': {4245632L: '\xff', 4245633L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_17(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_18(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125806L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125806L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_19(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_2(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_20(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_21(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_22(self):
''' Instruction DEC DWORD [RDX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329994L, 'RBP': 140737488345936L}, 'memory': {4329994L: '\xff', 4329995L: '\n', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'text': '\xff\n', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329996L, 'RBP': 140737488345936L}, 'memory': {4329994L: '\xff', 4329995L: '\n', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00'}}, 'disassembly': 'DEC DWORD [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_23(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125362L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125362L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_24(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_25(self):
''' Instruction DEC DWORD [RIP+0x2ba33e] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'RDI': 0L, 'RAX': 7065224L, 'RSP': 140737488346192L, 'RDX': 7058320L, 'RIP': 4198428L, 'RBP': 0L}, 'memory': {7058272: '\x01', 7058273: '\x00', 7058287: '\x00', 7058295: '\x00', 7058266: '\x00', 7058267: '\x00', 4198428L: '\xff', 4198429L: '\r', 4198430L: '>', 4198431L: '\xa3', 4198432L: '+', 4198433L: '\x00', 7058274: '\x00', 7058275: '\x00', 7058276: '\x00', 7058277: '\x00', 7058278: '\x00', 7058279: '\x00', 7058280: '\x00', 7058268: '\x00', 7058282: '\x00', 7058283: '\x00', 7058284: '\x00', 7058285: '\x00', 7058286: '\x00', 7058269: '\x00', 7058288: '\x00', 7058289: '\x00', 7058290: '\x00', 7058291: '\x00', 7058292: '\x00', 7058270: '\x00', 7058294: '\x00', 7058281: '\x00', 7058296: '\x00', 7058297: '\x00', 7058271: '\x00', 7058293: '\x00'}}, 'text': '\xff\r>\xa3+\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'RDI': 0L, 'RAX': 7065224L, 'RSP': 140737488346192L, 'RDX': 7058320L, 'RIP': 4198434L, 'RBP': 0L}, 'memory': {7058272: '\x00', 7058273: '\x00', 7058287: '\x00', 7058295: '\x00', 7058266: '\x00', 7058267: '\x00', 4198428L: '\xff', 4198429L: '\r', 4198430L: '>', 4198431L: '\xa3', 4198432L: '+', 4198433L: '\x00', 7058274: '\x00', 7058275: '\x00', 7058276: '\x00', 7058277: '\x00', 7058278: '\x00', 7058279: '\x00', 7058280: '\x00', 7058268: '\x00', 7058282: '\x00', 7058283: '\x00', 7058284: '\x00', 7058285: '\x00', 7058286: '\x00', 7058269: '\x00', 7058288: '\x00', 7058289: '\x00', 7058290: '\x00', 7058291: '\x00', 7058292: '\x00', 7058270: '\x00', 7058294: '\x00', 7058281: '\x00', 7058296: '\x00', 7058297: '\x00', 7058271: '\x00', 7058293: '\x00'}}, 'disassembly': 'DEC DWORD [RIP+0x2ba33e]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_26(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125520L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125520L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_27(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125441L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125441L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_28(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_29(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_3(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_30(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_31(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'ECX': 1L, 'RDI': 140737354125599L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'ECX': 0L, 'RDI': 140737354125599L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244524L, 'RBP': 7049504L}, 'memory': {4244522L: '\xff', 4244523L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_32(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_4(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_5(self):
''' Instruction DEC ECX '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'text': '\xff\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'ECX': 1L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244482L, 'RBP': 7049504L}, 'memory': {4244480L: '\xff', 4244481L: '\xc9'}}, 'disassembly': 'DEC ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_6(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_7(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_8(self):
''' Instruction DEC DWORD [RBP+0x0] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488346032L, 'RDX': 33L, 'RIP': 4230181L, 'RBP': 7051232L}, 'memory': {7051243: '\x00', 7051257: '\x00', 7051237: '\x00', 7051232: '\x01', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01', 4230181L: '\xff', 4230182L: 'M', 4230183L: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051239: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 7051247: '\x00', 7051248: '\x00', 7051249: '\x00', 7051250: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051238: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'text': '\xffM\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488346032L, 'RDX': 33L, 'RIP': 4230184L, 'RBP': 7051232L}, 'memory': {7051243: '\x00', 7051257: '\x00', 7051237: '\x00', 7051232: '\x00', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01', 4230181L: '\xff', 4230182L: 'M', 4230183L: '\x00', 7051240: '\x00', 7051241: '\x00', 7051242: '\x00', 7051239: '\x00', 7051244: '\x00', 7051245: '\x00', 7051246: '\x00', 7051247: '\x00', 7051248: '\x00', 7051249: '\x00', 7051250: '\x00', 7051251: '\x00', 7051252: '\x00', 7051253: '\x00', 7051254: '\x00', 7051255: '\x00', 7051256: '\x00', 7051238: '\x00', 7051258: '\x00', 7051259: '\x00', 7051260: '\x00', 7051261: '\x00', 7051262: '\x00', 7051263: '\x00'}}, 'disassembly': 'DEC DWORD [RBP+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDEC_9(self):
''' Instruction DEC DWORD [RBX] '''
test = {'mnemonic': 'DEC', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199197L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x01', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'text': '\xff\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199199L, 'RBP': 4782912L}, 'memory': {7059439: '\x00', 7059408: '\x00', 7059409: '\x00', 7059410: '\x00', 7059411: '\x00', 7059412: '\x00', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x00', 7059417: '\x00', 7059418: '\x00', 7059419: '\x00', 7059420: '\x00', 4199197L: '\xff', 4199198L: '\x0b', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 7059431: '\x00', 7059432: '\x00', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059421: '\x00', 7059422: '\x00'}}, 'disassembly': 'DEC DWORD [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d4, test['pos']['registers'][reg_name]&0x8d4, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDIV_1(self):
''' Instruction DIV RSI '''
test = {'mnemonic': 'DIV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2368L, 'RAX': 2191L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4196922L, 'RBP': 80L}, 'memory': {4196922L: 'H', 4196923L: '\xf7', 4196924L: '\xf6'}}, 'text': 'H\xf7\xf6', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2368L, 'RAX': 34L, 'RSP': 140737488346160L, 'RDX': 15L, 'RIP': 4196925L, 'RBP': 80L}, 'memory': {4196922L: 'H', 4196923L: '\xf7', 4196924L: '\xf6'}}, 'disassembly': 'DIV RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDIV_2(self):
''' Instruction DIV RCX '''
test = {'mnemonic': 'DIV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 9L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392571L, 'RBP': 7049504L}, 'memory': {4392571L: 'H', 4392572L: '\xf7', 4392573L: '\xf1'}}, 'text': 'H\xf7\xf1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392574L, 'RBP': 7049504L}, 'memory': {4392571L: 'H', 4392572L: '\xf7', 4392573L: '\xf1'}}, 'disassembly': 'DIV RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDIV_3(self):
''' Instruction DIV RBX '''
test = {'mnemonic': 'DIV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7069696L, 'RSI': 64L, 'RBX': 8L, 'RDI': 2176L, 'RAX': 87L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4197086L, 'RBP': 80L}, 'memory': {4197088L: '\xf3', 4197086L: 'H', 4197087L: '\xf7'}}, 'text': 'H\xf7\xf3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7069696L, 'RSI': 64L, 'RBX': 8L, 'RDI': 2176L, 'RAX': 10L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4197089L, 'RBP': 80L}, 'memory': {4197088L: '\xf3', 4197086L: 'H', 4197087L: '\xf7'}}, 'disassembly': 'DIV RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testDIV_4(self):
''' Instruction DIV RBX '''
test = {'mnemonic': 'DIV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RBX': 8L, 'RDI': 4098L, 'RAX': 87L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4197226L, 'RBP': 80L}, 'memory': {4197226L: 'H', 4197227L: '\xf7', 4197228L: '\xf3'}}, 'text': 'H\xf7\xf3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RBX': 8L, 'RDI': 4098L, 'RAX': 10L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4197229L, 'RBP': 80L}, 'memory': {4197226L: 'H', 4197227L: '\xf7', 4197228L: '\xf3'}}, 'disassembly': 'DIV RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testFLDCW_1(self):
''' Instruction FLDCW [RSP-0x2] '''
test = {'mnemonic': 'FLDCW', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 64L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4319833L, 'RBP': 140737488346472L}, 'memory': {4319833L: '\xd9', 4319834L: 'l', 4319835L: '$', 4319836L: '\xfe'}}, 'text': '\xd9l$\xfe', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 64L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4319837L, 'RBP': 140737488346472L}, 'memory': {4319833L: '\xd9', 4319834L: 'l', 4319835L: '$', 4319836L: '\xfe'}}, 'disassembly': 'FLDCW [RSP-0x2]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIDIV_1(self):
''' Instruction IDIV R11 '''
test = {'mnemonic': 'IDIV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 4194304L, 'R11': 4L, 'RDI': 2L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285157L, 'RBP': 32768L}, 'memory': {4285157L: 'I', 4285158L: '\xf7', 4285159L: '\xfb'}}, 'text': 'I\xf7\xfb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 4194304L, 'R11': 4L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285160L, 'RBP': 32768L}, 'memory': {4285157L: 'I', 4285158L: '\xf7', 4285159L: '\xfb'}}, 'disassembly': 'IDIV R11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_1(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 4L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 32L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_10(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 17L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 136L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_11(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 1L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_12(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 64L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_13(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 38L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 304L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_14(self):
''' Instruction IMUL EDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 15774463L, 'RDI': 188L, 'EDX': 1431655766L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 188L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'text': '\xf7\xea', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 0L, 'RSI': 15774463L, 'RDI': 188L, 'EDX': 1L, 'RAX': 2L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4283819L, 'RBP': 188L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'disassembly': 'IMUL EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_15(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 3L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 3L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_16(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 43L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 344L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_17(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 90L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 90L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_18(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 2L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 16L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_19(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 583L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_2(self):
''' Instruction IMUL EAX, ESI '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 4096L, 'RDX': 64L, 'RBP': 9L, 'RDI': 4L, 'ESI': 1L, 'RSI': 1L, 'RIP': 4284277L, 'EAX': 4194304L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 4194304L}, 'memory': {4284277L: '\x0f', 4284278L: '\xaf', 4284279L: '\xc6'}}, 'text': '\x0f\xaf\xc6', 'pos': {'registers': {'RCX': 4096L, 'RDX': 64L, 'RBP': 9L, 'RDI': 4L, 'ESI': 1L, 'RSI': 1L, 'RIP': 4284280L, 'EAX': 4194304L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 4194304L}, 'memory': {4284277L: '\x0f', 4284278L: '\xaf', 4284279L: '\xc6'}}, 'disassembly': 'IMUL EAX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_20(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 1L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_21(self):
''' Instruction IMUL EDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 188L, 'EDX': 1431655766L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 188L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'text': '\xf7\xea', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 188L, 'EDX': 1L, 'RAX': 2L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4283819L, 'RBP': 188L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'disassembly': 'IMUL EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_22(self):
''' Instruction IMUL R14, RDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 36L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346208L, 'RDX': 12297829382473034411L, 'RIP': 4197525L, 'RBP': 0L}, 'memory': {4197528L: '\xf2', 4197525L: 'L', 4197526L: '\x0f', 4197527L: '\xaf'}}, 'text': 'L\x0f\xaf\xf2', 'pos': {'registers': {'RFLAGS': 2567L, 'R14': 12L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346208L, 'RDX': 12297829382473034411L, 'RIP': 4197529L, 'RBP': 0L}, 'memory': {4197528L: '\xf2', 4197525L: 'L', 4197526L: '\x0f', 4197527L: '\xaf'}}, 'disassembly': 'IMUL R14, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_23(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 39L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 312L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_24(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 43L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 344L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_25(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 1L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_26(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 64L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_27(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 3L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 3L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_28(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 43L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 344L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_29(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 37L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 296L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_3(self):
''' Instruction IMUL EDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 194L, 'EDX': 1431655766L, 'RAX': 9L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 194L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'text': '\xf7\xea', 'pos': {'registers': {'RFLAGS': 2567L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 194L, 'EDX': 3L, 'RAX': 6L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4283819L, 'RBP': 194L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'disassembly': 'IMUL EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_30(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 90L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 90L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_31(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 17L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 136L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_32(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 37L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 296L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_33(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 583L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_34(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_35(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 51L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 519L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 408L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_36(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 118L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 118L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_37(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 2L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 16L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_38(self):
''' Instruction IMUL EAX, ECX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 4096L, 'RDX': 64L, 'RBP': 9L, 'RDI': 4L, 'RSI': 1L, 'RIP': 4284274L, 'EAX': 1024L, 'RSP': 140737488345968L, 'RFLAGS': 514L, 'RAX': 1024L, 'ECX': 4096L}, 'memory': {4284274L: '\x0f', 4284275L: '\xaf', 4284276L: '\xc1'}}, 'text': '\x0f\xaf\xc1', 'pos': {'registers': {'RCX': 4096L, 'RDX': 64L, 'RBP': 9L, 'RDI': 4L, 'RSI': 1L, 'RIP': 4284277L, 'EAX': 4194304L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 4194304L, 'ECX': 4096L}, 'memory': {4284274L: '\x0f', 4284275L: '\xaf', 4284276L: '\xc1'}}, 'disassembly': 'IMUL EAX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_39(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 583L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_4(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 1L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 9L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792432L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_40(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 4L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 32L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_41(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 51L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 519L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 408L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_42(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 36L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 288L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_43(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_44(self):
''' Instruction IMUL RBX, RBP '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RBX': 8L, 'RDI': 4098L, 'RAX': 10L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4197232L, 'RBP': 10L}, 'memory': {4197232L: 'H', 4197233L: '\x0f', 4197234L: '\xaf', 4197235L: '\xdd'}}, 'text': 'H\x0f\xaf\xdd', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RBX': 80L, 'RDI': 4098L, 'RAX': 10L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4197236L, 'RBP': 10L}, 'memory': {4197232L: 'H', 4197233L: '\x0f', 4197234L: '\xaf', 4197235L: '\xdd'}}, 'disassembly': 'IMUL RBX, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_45(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 4L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 32L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_46(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 4L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 34L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 32L, 'R12': 8L, 'RSI': 4792480L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_47(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 2L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 16L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_48(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 17L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 136L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_49(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 102L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 35L, 'R12': 8L, 'RSI': 4792704L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 102L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 280L, 'R12': 8L, 'RSI': 4792704L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_5(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 36L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 288L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_50(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 102L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 35L, 'R12': 8L, 'RSI': 4792704L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 102L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 280L, 'R12': 8L, 'RSI': 4792704L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_51(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 51L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 519L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 408L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_52(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 43L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 344L, 'R12': 8L, 'RSI': 4792824L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_53(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 51L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 519L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 408L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_54(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 39L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 312L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_55(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 39L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 312L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_56(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 2L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 12L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 16L, 'R12': 8L, 'RSI': 4792448L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_57(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 37L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 296L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_58(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 34L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 118L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 68L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 272L, 'R12': 8L, 'RSI': 4792416L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 118L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_59(self):
''' Instruction IMUL EAX, EDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 64L, 'RDX': 64L, 'RBP': 3L, 'RDI': 4L, 'RSI': 0L, 'RIP': 4284268L, 'EAX': 8L, 'EDX': 64L, 'RSP': 140737488345968L, 'RFLAGS': 582L, 'RAX': 8L}, 'memory': {4284268L: '\x0f', 4284269L: '\xaf', 4284270L: '\xc2'}}, 'text': '\x0f\xaf\xc2', 'pos': {'registers': {'RCX': 64L, 'RDX': 64L, 'RBP': 3L, 'RDI': 4L, 'RSI': 0L, 'RIP': 4284271L, 'EAX': 512L, 'EDX': 64L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 512L}, 'memory': {4284268L: '\x0f', 4284269L: '\xaf', 4284270L: '\xc2'}}, 'disassembly': 'IMUL EAX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_6(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 583L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 0L, 'R12': 8L, 'RSI': 4792424L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_60(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 64L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_61(self):
''' Instruction IMUL RAX, RBX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7069696L, 'RSI': 64L, 'RBX': 8L, 'RDI': 2176L, 'RAX': 10L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4197089L, 'RBP': 80L}, 'memory': {4197089L: 'H', 4197090L: '\x0f', 4197091L: '\xaf', 4197092L: '\xc3'}}, 'text': 'H\x0f\xaf\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7069696L, 'RSI': 64L, 'RBX': 8L, 'RDI': 2176L, 'RAX': 80L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4197093L, 'RBP': 80L}, 'memory': {4197089L: 'H', 4197090L: '\x0f', 4197091L: '\xaf', 4197092L: '\xc3'}}, 'disassembly': 'IMUL RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_62(self):
''' Instruction IMUL EAX, EDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 4096L, 'RDX': 64L, 'RBP': 9L, 'RDI': 4L, 'RSI': 0L, 'RIP': 4284268L, 'EAX': 16L, 'EDX': 64L, 'RSP': 140737488345968L, 'RFLAGS': 582L, 'RAX': 16L}, 'memory': {4284268L: '\x0f', 4284269L: '\xaf', 4284270L: '\xc2'}}, 'text': '\x0f\xaf\xc2', 'pos': {'registers': {'RCX': 4096L, 'RDX': 64L, 'RBP': 9L, 'RDI': 4L, 'RSI': 0L, 'RIP': 4284271L, 'EAX': 1024L, 'EDX': 64L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 1024L}, 'memory': {4284268L: '\x0f', 4284269L: '\xaf', 4284270L: '\xc2'}}, 'disassembly': 'IMUL EAX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_63(self):
''' Instruction IMUL EAX, ECX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 64L, 'RDX': 64L, 'RBP': 3L, 'RDI': 4L, 'RSI': 1L, 'RIP': 4284274L, 'EAX': 512L, 'RSP': 140737488345968L, 'RFLAGS': 514L, 'RAX': 512L, 'ECX': 64L}, 'memory': {4284274L: '\x0f', 4284275L: '\xaf', 4284276L: '\xc1'}}, 'text': '\x0f\xaf\xc1', 'pos': {'registers': {'RCX': 64L, 'RDX': 64L, 'RBP': 3L, 'RDI': 4L, 'RSI': 1L, 'RIP': 4284277L, 'EAX': 32768L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 32768L, 'ECX': 64L}, 'memory': {4284274L: '\x0f', 4284275L: '\xaf', 4284276L: '\xc1'}}, 'disassembly': 'IMUL EAX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_64(self):
''' Instruction IMUL EAX, ESI '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 64L, 'RDX': 64L, 'RBP': 3L, 'RDI': 4L, 'ESI': 1L, 'RSI': 1L, 'RIP': 4284277L, 'EAX': 32768L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 32768L}, 'memory': {4284277L: '\x0f', 4284278L: '\xaf', 4284279L: '\xc6'}}, 'text': '\x0f\xaf\xc6', 'pos': {'registers': {'RCX': 64L, 'RDX': 64L, 'RBP': 3L, 'RDI': 4L, 'ESI': 1L, 'RSI': 1L, 'RIP': 4284280L, 'EAX': 32768L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 32768L}, 'memory': {4284277L: '\x0f', 4284278L: '\xaf', 4284279L: '\xc6'}}, 'disassembly': 'IMUL EAX, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_65(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 37L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 120L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 296L, 'R12': 8L, 'RSI': 4792728L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_66(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 39L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 124L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 312L, 'R12': 8L, 'RSI': 4792760L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_67(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 17L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 78L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 136L, 'R12': 8L, 'RSI': 4792688L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_68(self):
''' Instruction IMUL R15, RSI '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 34L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2368L, 'RAX': 34L, 'RSP': 140737488346160L, 'RDX': 15L, 'RIP': 4196928L, 'RBP': 80L}, 'memory': {4196928L: 'L', 4196929L: '\x0f', 4196930L: '\xaf', 4196931L: '\xfe'}}, 'text': 'L\x0f\xaf\xfe', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 2176L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2368L, 'RAX': 34L, 'RSP': 140737488346160L, 'RDX': 15L, 'RIP': 4196932L, 'RBP': 80L}, 'memory': {4196928L: 'L', 4196929L: '\x0f', 4196930L: '\xaf', 4196931L: '\xfe'}}, 'disassembly': 'IMUL R15, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_7(self):
''' Instruction IMUL EDX '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 15774463L, 'RDI': 194L, 'EDX': 1431655766L, 'RAX': 9L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 194L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'text': '\xf7\xea', 'pos': {'registers': {'RFLAGS': 2567L, 'RCX': 0L, 'RSI': 15774463L, 'RDI': 194L, 'EDX': 3L, 'RAX': 6L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4283819L, 'RBP': 194L}, 'memory': {4283817L: '\xf7', 4283818L: '\xea'}}, 'disassembly': 'IMUL EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_8(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 38L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 304L, 'R12': 8L, 'RSI': 4792712L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 1L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testIMUL_9(self):
''' Instruction IMUL R15, R12 '''
test = {'mnemonic': 'IMUL', 'pre': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 8L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 515L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'text': 'M\x0f\xaf\xfc', 'pos': {'registers': {'RCX': 8L, 'RDX': 60L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R15': 64L, 'R12': 8L, 'RSI': 4792552L, 'RIP': 4320766L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 4294967295L}, 'memory': {4320762L: 'M', 4320763L: '\x0f', 4320764L: '\xaf', 4320765L: '\xfc'}}, 'disassembly': 'IMUL R15, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_1(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_10(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_11(self):
''' Instruction JAE 0x406f92 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 10L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221255L, 'RBP': 7051232L}, 'memory': {4221255L: '\x0f', 4221256L: '\x83', 4221257L: 'E', 4221258L: '\x06', 4221259L: '\x00', 4221260L: '\x00'}}, 'text': '\x0f\x83E\x06\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 10L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4222866L, 'RBP': 7051232L}, 'memory': {4221255L: '\x0f', 4221256L: '\x83', 4221257L: 'E', 4221258L: '\x06', 4221259L: '\x00', 4221260L: '\x00'}}, 'disassembly': 'JAE 0x406f92', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_12(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_13(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_14(self):
''' Instruction JAE 0x42354c '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338804L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'text': '\x0f\x83\xd2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338810L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'disassembly': 'JAE 0x42354c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_15(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_16(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_17(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_18(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_19(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_2(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_20(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354126010L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354126010L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_21(self):
''' Instruction JAE 0x417443 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 535L, 'RCX': 18446744073709551615L, 'RSI': 4096L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343960L, 'RDX': 3L, 'RIP': 4289600L, 'RBP': 4096L}, 'memory': {4289600L: 's', 4289601L: '\x01'}}, 'text': 's\x01', 'pos': {'registers': {'RFLAGS': 535L, 'RCX': 18446744073709551615L, 'RSI': 4096L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343960L, 'RDX': 3L, 'RIP': 4289602L, 'RBP': 4096L}, 'memory': {4289600L: 's', 4289601L: '\x01'}}, 'disassembly': 'JAE 0x417443', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_22(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_23(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125487L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125487L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_24(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_25(self):
''' Instruction JAE 0x44a470 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 535L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 140737488345728L, 'RAX': 0L, 'RSP': 140737488345720L, 'RDX': 0L, 'RIP': 4498541L, 'RBP': 0L}, 'memory': {4498541L: 's', 4498542L: '\x01'}}, 'text': 's\x01', 'pos': {'registers': {'RFLAGS': 535L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 140737488345728L, 'RAX': 0L, 'RSP': 140737488345720L, 'RDX': 0L, 'RIP': 4498543L, 'RBP': 0L}, 'memory': {4498541L: 's', 4498542L: '\x01'}}, 'disassembly': 'JAE 0x44a470', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_26(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125773L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125773L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_27(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_28(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125645L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125645L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_29(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_3(self):
''' Instruction JAE 0x42354c '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338804L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'text': '\x0f\x83\xd2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338810L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'disassembly': 'JAE 0x42354c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_30(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_31(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_32(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_33(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_34(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_35(self):
''' Instruction JAE 0x40241e '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488344144L, 'RDX': 9L, 'RIP': 4203483L, 'RBP': 7049504L}, 'memory': {4203483L: 's', 4203484L: 'A'}}, 'text': 'sA', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488344144L, 'RDX': 9L, 'RIP': 4203485L, 'RBP': 7049504L}, 'memory': {4203483L: 's', 4203484L: 'A'}}, 'disassembly': 'JAE 0x40241e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_36(self):
''' Instruction JAE 0x406f92 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221255L, 'RBP': 7051232L}, 'memory': {4221255L: '\x0f', 4221256L: '\x83', 4221257L: 'E', 4221258L: '\x06', 4221259L: '\x00', 4221260L: '\x00'}}, 'text': '\x0f\x83E\x06\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221261L, 'RBP': 7051232L}, 'memory': {4221255L: '\x0f', 4221256L: '\x83', 4221257L: 'E', 4221258L: '\x06', 4221259L: '\x00', 4221260L: '\x00'}}, 'disassembly': 'JAE 0x406f92', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_37(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_38(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_39(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_4(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_40(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_41(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125408L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125408L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_42(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_43(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_44(self):
''' Instruction JAE 0x4165b9 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 4783074L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 7065176L, 'RIP': 4285830L, 'RBP': 0L}, 'memory': {4285830L: 's', 4285831L: '1'}}, 'text': 's1', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 4783074L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 7065176L, 'RIP': 4285832L, 'RBP': 0L}, 'memory': {4285830L: 's', 4285831L: '1'}}, 'disassembly': 'JAE 0x4165b9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_45(self):
''' Instruction JAE 0x416679 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345880L, 'RDX': 699L, 'RIP': 4286022L, 'RBP': 140737354125312L}, 'memory': {4286022L: 's', 4286023L: '1'}}, 'text': 's1', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345880L, 'RDX': 699L, 'RIP': 4286024L, 'RBP': 140737354125312L}, 'memory': {4286022L: 's', 4286023L: '1'}}, 'disassembly': 'JAE 0x416679', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_46(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_47(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_48(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_49(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125931L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125931L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_5(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_50(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_51(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_52(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_53(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_54(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_55(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_56(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125566L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125566L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_57(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_58(self):
''' Instruction JAE 0x40c3c0 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244292L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'text': 'sz', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244416L, 'RBP': 7049504L}, 'memory': {4244292L: 's', 4244293L: 'z'}}, 'disassembly': 'JAE 0x40c3c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_59(self):
''' Instruction JAE 0x400e76 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197992L, 'RBP': 7054832L}, 'memory': {4197992L: 's', 4197993L: '\x0c'}}, 'text': 's\x0c', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197994L, 'RBP': 7054832L}, 'memory': {4197992L: 's', 4197993L: '\x0c'}}, 'disassembly': 'JAE 0x400e76', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_6(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_60(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_61(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_62(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_63(self):
''' Instruction JAE 0x42354c '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338804L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'text': '\x0f\x83\xd2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338810L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'disassembly': 'JAE 0x42354c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_64(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_65(self):
''' Instruction JAE 0x4013d2 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125852L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199260L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'text': 'st', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125852L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199262L, 'RBP': 4782912L}, 'memory': {4199260L: 's', 4199261L: 't'}}, 'disassembly': 'JAE 0x4013d2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_66(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_67(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_68(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_69(self):
''' Instruction JAE 0x42354c '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338804L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'text': '\x0f\x83\xd2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338810L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'disassembly': 'JAE 0x42354c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_7(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_70(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_71(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_72(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_73(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_74(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_75(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_76(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_77(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_78(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_79(self):
''' Instruction JAE 0x40049b '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4195449L, 'RBP': 140737488346144L}, 'memory': {4195449L: 's', 4195450L: ' '}}, 'text': 's ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4195483L, 'RBP': 140737488346144L}, 'memory': {4195449L: 's', 4195450L: ' '}}, 'disassembly': 'JAE 0x40049b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_8(self):
''' Instruction JAE 0x416619 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 140737488346385L, 'RDI': 7L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 7L, 'RIP': 4285926L, 'RBP': 0L}, 'memory': {4285926L: 's', 4285927L: '1'}}, 'text': 's1', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 140737488346385L, 'RDI': 7L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 7L, 'RIP': 4285928L, 'RBP': 0L}, 'memory': {4285926L: 's', 4285927L: '1'}}, 'disassembly': 'JAE 0x416619', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_80(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_81(self):
''' Instruction JAE 0x423b68 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4340492L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4340499L, 'RBP': 140737488345936L}, 'memory': {4340499L: 's', 4340500L: 'S'}}, 'text': 'sS', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4340492L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4340501L, 'RBP': 140737488345936L}, 'memory': {4340499L: 's', 4340500L: 'S'}}, 'disassembly': 'JAE 0x423b68', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_82(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_83(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_84(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_85(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_86(self):
''' Instruction JAE 0x41ee28 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320744L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'text': 's>', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320744L: 's', 4320745L: '>'}}, 'disassembly': 'JAE 0x41ee28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_87(self):
''' Instruction JAE 0x40c830 '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7069696L, 'RSI': 7035136L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245431L, 'RBP': 80L}, 'memory': {4245432L: 'w', 4245431L: 's'}}, 'text': 'sw', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7069696L, 'RSI': 7035136L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245552L, 'RBP': 80L}, 'memory': {4245432L: 'w', 4245431L: 's'}}, 'disassembly': 'JAE 0x40c830', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_88(self):
''' Instruction JAE 0x42354c '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338804L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'text': '\x0f\x83\xd2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4338810L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'disassembly': 'JAE 0x42354c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJAE_9(self):
''' Instruction JAE 0x42354c '''
test = {'mnemonic': 'JAE', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338804L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'text': '\x0f\x83\xd2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338810L, 'RBP': 140737488345936L}, 'memory': {4338804L: '\x0f', 4338805L: '\x83', 4338806L: '\xd2', 4338807L: '\x00', 4338808L: '\x00', 4338809L: '\x00'}}, 'disassembly': 'JAE 0x42354c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_1(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_10(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347008L, 'RAX': 3L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347008L, 'RAX': 3L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_100(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347040L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347040L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_101(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 8L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 8L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_11(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392872L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_12(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_13(self):
''' Instruction JA 0x406930 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221048L, 'RBP': 7051232L}, 'memory': {4221048L: '\x0f', 4221049L: '\x87', 4221050L: '\xb2', 4221051L: '\x00', 4221052L: '\x00', 4221053L: '\x00'}}, 'text': '\x0f\x87\xb2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221054L, 'RBP': 7051232L}, 'memory': {4221048L: '\x0f', 4221049L: '\x87', 4221050L: '\xb2', 4221051L: '\x00', 4221052L: '\x00', 4221053L: '\x00'}}, 'disassembly': 'JA 0x406930', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_14(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_15(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239599L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_16(self):
''' Instruction JA 0x40c470 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244471L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244473L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'disassembly': 'JA 0x40c470', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_17(self):
''' Instruction JA 0x44bf88 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 7069696L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4505470L, 'RBP': 4544L}, 'memory': {4505470L: 'w', 4505471L: '\x08'}}, 'text': 'w\x08', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 7069696L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4505472L, 'RBP': 4544L}, 'memory': {4505470L: 'w', 4505471L: '\x08'}}, 'disassembly': 'JA 0x44bf88', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_18(self):
''' Instruction JA 0x406a15 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 119L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 64L, 'RIP': 4220953L, 'RBP': 7051232L}, 'memory': {4220953L: '\x0f', 4220954L: '\x87', 4220955L: '\xf6', 4220956L: '\x01', 4220957L: '\x00', 4220958L: '\x00'}}, 'text': '\x0f\x87\xf6\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 119L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 64L, 'RIP': 4220959L, 'RBP': 7051232L}, 'memory': {4220953L: '\x0f', 4220954L: '\x87', 4220955L: '\xf6', 4220956L: '\x01', 4220957L: '\x00', 4220958L: '\x00'}}, 'disassembly': 'JA 0x406a15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_19(self):
''' Instruction JA 0x406340 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219577L, 'RBP': 7051232L}, 'memory': {4219577L: '\x0f', 4219578L: '\x87', 4219579L: '\x81', 4219580L: '\x00', 4219581L: '\x00', 4219582L: '\x00'}}, 'text': '\x0f\x87\x81\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219712L, 'RBP': 7051232L}, 'memory': {4219577L: '\x0f', 4219578L: '\x87', 4219579L: '\x81', 4219580L: '\x00', 4219581L: '\x00', 4219582L: '\x00'}}, 'disassembly': 'JA 0x406340', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_2(self):
''' Instruction JA 0x4234e2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 2147483636L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4338845L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'text': 'wC', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 2147483636L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4338847L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'disassembly': 'JA 0x4234e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_20(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_21(self):
''' Instruction JA 0x402b51 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205616L, 'RBP': 7049280L}, 'memory': {4205616L: '\x0f', 4205617L: '\x87', 4205618L: '\x1b', 4205619L: '\xff', 4205620L: '\xff', 4205621L: '\xff'}}, 'text': '\x0f\x87\x1b\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205622L, 'RBP': 7049280L}, 'memory': {4205616L: '\x0f', 4205617L: '\x87', 4205618L: '\x1b', 4205619L: '\xff', 4205620L: '\xff', 4205621L: '\xff'}}, 'disassembly': 'JA 0x402b51', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_22(self):
''' Instruction JA 0x431030 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346048L, 'RDX': 140737354125312L, 'RIP': 4394959L, 'RBP': 0L}, 'memory': {4394960L: '_', 4394959L: 'w'}}, 'text': 'w_', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346048L, 'RDX': 140737354125312L, 'RIP': 4394961L, 'RBP': 0L}, 'memory': {4394960L: '_', 4394959L: 'w'}}, 'disassembly': 'JA 0x431030', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_23(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_24(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392872L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_25(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 140737354125646L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 140737354125646L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_26(self):
''' Instruction JA 0x4062b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219394L, 'RBP': 7051232L}, 'memory': {4219394L: '\x0f', 4219395L: '\x87', 4219396L: '\xa8', 4219397L: '\x00', 4219398L: '\x00', 4219399L: '\x00'}}, 'text': '\x0f\x87\xa8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219568L, 'RBP': 7051232L}, 'memory': {4219394L: '\x0f', 4219395L: '\x87', 4219396L: '\xa8', 4219397L: '\x00', 4219398L: '\x00', 4219399L: '\x00'}}, 'disassembly': 'JA 0x4062b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_27(self):
''' Instruction JA 0x419ad2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 2L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299439L, 'RBP': 0L}, 'memory': {4299440L: '!', 4299439L: 'w'}}, 'text': 'w!', 'pos': {'registers': {'RFLAGS': 642L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 2L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299474L, 'RBP': 0L}, 'memory': {4299440L: '!', 4299439L: 'w'}}, 'disassembly': 'JA 0x419ad2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_28(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_29(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_3(self):
''' Instruction JA 0x44f8f8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 0L, 'RDI': 4807352L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 1L, 'RIP': 4520199L, 'RBP': 140737488346112L}, 'memory': {4520200L: '\xef', 4520199L: 'w'}}, 'text': 'w\xef', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 0L, 'RDI': 4807352L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 1L, 'RIP': 4520201L, 'RBP': 140737488346112L}, 'memory': {4520200L: '\xef', 4520199L: 'w'}}, 'disassembly': 'JA 0x44f8f8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_30(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_31(self):
''' Instruction JA 0x4211ad '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4783020L, 'RIP': 4330127L, 'RBP': 140737488345936L}, 'memory': {4330127L: '\x0f', 4330128L: '\x87', 4330129L: '\x18', 4330130L: '\xff', 4330131L: '\xff', 4330132L: '\xff'}}, 'text': '\x0f\x87\x18\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4783020L, 'RIP': 4330133L, 'RBP': 140737488345936L}, 'memory': {4330127L: '\x0f', 4330128L: '\x87', 4330129L: '\x18', 4330130L: '\xff', 4330131L: '\xff', 4330132L: '\xff'}}, 'disassembly': 'JA 0x4211ad', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_32(self):
''' Instruction JA 0x4009f1 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194368L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196829L, 'RBP': 0L}, 'memory': {4196829L: 'w', 4196830L: '\x12'}}, 'text': 'w\x12', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194368L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196849L, 'RBP': 0L}, 'memory': {4196829L: 'w', 4196830L: '\x12'}}, 'disassembly': 'JA 0x4009f1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_33(self):
''' Instruction JA 0x44bf88 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7209408L, 'RSP': 140737488345768L, 'RDX': 7209408L, 'RIP': 4505470L, 'RBP': 135168L}, 'memory': {4505470L: 'w', 4505471L: '\x08'}}, 'text': 'w\x08', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7209408L, 'RSP': 140737488345768L, 'RDX': 7209408L, 'RIP': 4505472L, 'RBP': 135168L}, 'memory': {4505470L: 'w', 4505471L: '\x08'}}, 'disassembly': 'JA 0x44bf88', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_34(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_35(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'RAX': 3728L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'RAX': 3728L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_36(self):
''' Instruction JA 0x419ae9 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488345728L, 'RDX': 49L, 'RIP': 4299413L, 'RBP': 0L}, 'memory': {4299413L: 'w', 4299414L: 'R'}}, 'text': 'wR', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488345728L, 'RDX': 49L, 'RIP': 4299415L, 'RBP': 0L}, 'memory': {4299413L: 'w', 4299414L: 'R'}}, 'disassembly': 'JA 0x419ae9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_37(self):
''' Instruction JA 0x4234e2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 2147483642L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4338845L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'text': 'wC', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 2147483642L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4338847L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'disassembly': 'JA 0x4234e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_38(self):
''' Instruction JA 0x4211ad '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4330127L, 'RBP': 140737488345936L}, 'memory': {4330127L: '\x0f', 4330128L: '\x87', 4330129L: '\x18', 4330130L: '\xff', 4330131L: '\xff', 4330132L: '\xff'}}, 'text': '\x0f\x87\x18\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4330133L, 'RBP': 140737488345936L}, 'memory': {4330127L: '\x0f', 4330128L: '\x87', 4330129L: '\x18', 4330130L: '\xff', 4330131L: '\xff', 4330132L: '\xff'}}, 'disassembly': 'JA 0x4211ad', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_39(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'RAX': 4079L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'RAX': 4079L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_4(self):
''' Instruction JA 0x475136 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 18446744073709551591L, 'RSP': 140737488343880L, 'RDX': 140737488343824L, 'RIP': 4673725L, 'RBP': 18446744073709551568L}, 'memory': {4673725L: 'w', 4673726L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 18446744073709551591L, 'RSP': 140737488343880L, 'RDX': 140737488343824L, 'RIP': 4673846L, 'RBP': 18446744073709551568L}, 'memory': {4673725L: 'w', 4673726L: 'w'}}, 'disassembly': 'JA 0x475136', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_40(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 53L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239599L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 53L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239626L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_41(self):
''' Instruction JA 0x402b51 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205616L, 'RBP': 7049728L}, 'memory': {4205616L: '\x0f', 4205617L: '\x87', 4205618L: '\x1b', 4205619L: '\xff', 4205620L: '\xff', 4205621L: '\xff'}}, 'text': '\x0f\x87\x1b\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205622L, 'RBP': 7049728L}, 'memory': {4205616L: '\x0f', 4205617L: '\x87', 4205618L: '\x1b', 4205619L: '\xff', 4205620L: '\xff', 4205621L: '\xff'}}, 'disassembly': 'JA 0x402b51', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_42(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347248L, 'RAX': 18446744073709551614L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 642L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347248L, 'RAX': 18446744073709551614L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296984L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_43(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_44(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347088L, 'RAX': 4L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347088L, 'RAX': 4L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_45(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_46(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_47(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392523L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_48(self):
''' Instruction JA 0x40c470 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244471L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244473L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'disassembly': 'JA 0x40c470', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_49(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 2L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 2L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_5(self):
''' Instruction JA 0x4062b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219394L, 'RBP': 7051232L}, 'memory': {4219394L: '\x0f', 4219395L: '\x87', 4219396L: '\xa8', 4219397L: '\x00', 4219398L: '\x00', 4219399L: '\x00'}}, 'text': '\x0f\x87\xa8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1623L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219568L, 'RBP': 7051232L}, 'memory': {4219394L: '\x0f', 4219395L: '\x87', 4219396L: '\xa8', 4219397L: '\x00', 4219398L: '\x00', 4219399L: '\x00'}}, 'disassembly': 'JA 0x4062b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_50(self):
''' Instruction JA 0x4234e2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4783040L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 2147483629L, 'RSP': 140737488344256L, 'RDX': 18L, 'RIP': 4338845L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'text': 'wC', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4783040L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 2147483629L, 'RSP': 140737488344256L, 'RDX': 18L, 'RIP': 4338847L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'disassembly': 'JA 0x4234e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_51(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_52(self):
''' Instruction JA 0x402b51 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 140737354125312L, 'RIP': 4205616L, 'RBP': 7049504L}, 'memory': {4205616L: '\x0f', 4205617L: '\x87', 4205618L: '\x1b', 4205619L: '\xff', 4205620L: '\xff', 4205621L: '\xff'}}, 'text': '\x0f\x87\x1b\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 140737354125312L, 'RIP': 4205393L, 'RBP': 7049504L}, 'memory': {4205616L: '\x0f', 4205617L: '\x87', 4205618L: '\x1b', 4205619L: '\xff', 4205620L: '\xff', 4205621L: '\xff'}}, 'disassembly': 'JA 0x402b51', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_53(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 13L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 13L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_54(self):
''' Instruction JA 0x406930 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221048L, 'RBP': 7051232L}, 'memory': {4221048L: '\x0f', 4221049L: '\x87', 4221050L: '\xb2', 4221051L: '\x00', 4221052L: '\x00', 4221053L: '\x00'}}, 'text': '\x0f\x87\xb2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221054L, 'RBP': 7051232L}, 'memory': {4221048L: '\x0f', 4221049L: '\x87', 4221050L: '\xb2', 4221051L: '\x00', 4221052L: '\x00', 4221053L: '\x00'}}, 'disassembly': 'JA 0x406930', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_55(self):
''' Instruction JA 0x4211ad '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4782995L, 'RIP': 4330127L, 'RBP': 140737488345936L}, 'memory': {4330127L: '\x0f', 4330128L: '\x87', 4330129L: '\x18', 4330130L: '\xff', 4330131L: '\xff', 4330132L: '\xff'}}, 'text': '\x0f\x87\x18\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4782995L, 'RIP': 4330133L, 'RBP': 140737488345936L}, 'memory': {4330127L: '\x0f', 4330128L: '\x87', 4330129L: '\x18', 4330130L: '\xff', 4330131L: '\xff', 4330132L: '\xff'}}, 'disassembly': 'JA 0x4211ad', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_56(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239599L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_57(self):
''' Instruction JA 0x419ae9 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 2L, 'RAX': 5L, 'RSP': 140737488345728L, 'RDX': 53L, 'RIP': 4299413L, 'RBP': 0L}, 'memory': {4299413L: 'w', 4299414L: 'R'}}, 'text': 'wR', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 2L, 'RAX': 5L, 'RSP': 140737488345728L, 'RDX': 53L, 'RIP': 4299415L, 'RBP': 0L}, 'memory': {4299413L: 'w', 4299414L: 'R'}}, 'disassembly': 'JA 0x419ae9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_58(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 3713L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392872L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_59(self):
''' Instruction JA 0x4234e2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 2147483617L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4338845L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'text': 'wC', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 2147483617L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4338847L, 'RBP': 140737488345936L}, 'memory': {4338845L: 'w', 4338846L: 'C'}}, 'disassembly': 'JA 0x4234e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_6(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_60(self):
''' Instruction JA 0x44bf88 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 7074240L, 'RSP': 140737488346120L, 'RDX': 7074240L, 'RIP': 4505470L, 'RBP': 4544L}, 'memory': {4505470L: 'w', 4505471L: '\x08'}}, 'text': 'w\x08', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 7074240L, 'RSP': 140737488346120L, 'RDX': 7074240L, 'RIP': 4505472L, 'RBP': 4544L}, 'memory': {4505470L: 'w', 4505471L: '\x08'}}, 'disassembly': 'JA 0x44bf88', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_61(self):
''' Instruction JA 0x416554 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285754L, 'RBP': 8192L}, 'memory': {4285754L: 'w', 4285755L: '\x18'}}, 'text': 'w\x18', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285756L, 'RBP': 8192L}, 'memory': {4285754L: 'w', 4285755L: '\x18'}}, 'disassembly': 'JA 0x416554', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_62(self):
''' Instruction JA 0x419ad2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 0L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299439L, 'RBP': 0L}, 'memory': {4299440L: '!', 4299439L: 'w'}}, 'text': 'w!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 0L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299474L, 'RBP': 0L}, 'memory': {4299440L: '!', 4299439L: 'w'}}, 'disassembly': 'JA 0x419ad2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_63(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_64(self):
''' Instruction JA 0x44bf9d '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 64L, 'RDI': 0L, 'RAX': 7069696L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4505456L, 'RBP': 4544L}, 'memory': {4505456L: 'w', 4505457L: '+'}}, 'text': 'w+', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 64L, 'RDI': 0L, 'RAX': 7069696L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4505458L, 'RBP': 4544L}, 'memory': {4505456L: 'w', 4505457L: '+'}}, 'disassembly': 'JA 0x44bf9d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_65(self):
''' Instruction JA 0x44bf9d '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7209408L, 'RSP': 140737488345768L, 'RDX': 7209408L, 'RIP': 4505456L, 'RBP': 135168L}, 'memory': {4505456L: 'w', 4505457L: '+'}}, 'text': 'w+', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7209408L, 'RSP': 140737488345768L, 'RDX': 7209408L, 'RIP': 4505458L, 'RBP': 135168L}, 'memory': {4505456L: 'w', 4505457L: '+'}}, 'disassembly': 'JA 0x44bf9d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_66(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'RAX': 3715L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'RAX': 3715L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_67(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 1000L, 'RDI': 140737488347152L, 'RAX': 9L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 1000L, 'RDI': 140737488347152L, 'RAX': 9L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_68(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'RAX': 3727L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'RAX': 3727L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_69(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239599L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_7(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 30L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 30L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_70(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 4083L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 4083L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_71(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239599L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239626L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_72(self):
''' Instruction JA 0x40c470 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244471L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244473L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'disassembly': 'JA 0x40c470', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_73(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 11L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 11L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_74(self):
''' Instruction JA 0x406b34 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 535L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 7065872L, 'RIP': 4219341L, 'RBP': 7051232L}, 'memory': {4219341L: '\x0f', 4219342L: '\x87', 4219343L: 'a', 4219344L: '\t', 4219345L: '\x00', 4219346L: '\x00'}}, 'text': '\x0f\x87a\t\x00\x00', 'pos': {'registers': {'RFLAGS': 535L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 7065872L, 'RIP': 4219347L, 'RBP': 7051232L}, 'memory': {4219341L: '\x0f', 4219342L: '\x87', 4219343L: 'a', 4219344L: '\t', 4219345L: '\x00', 4219346L: '\x00'}}, 'disassembly': 'JA 0x406b34', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_75(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_76(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_77(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_78(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239599L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_79(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_8(self):
''' Instruction JA 0x419ad2 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345861L, 'RSI': 0L, 'RDI': 1L, 'RAX': 48L, 'RSP': 140737488345728L, 'RDX': 1L, 'RIP': 4299439L, 'RBP': 0L}, 'memory': {4299440L: '!', 4299439L: 'w'}}, 'text': 'w!', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345861L, 'RSI': 0L, 'RDI': 1L, 'RAX': 48L, 'RSP': 140737488345728L, 'RDX': 1L, 'RIP': 4299441L, 'RBP': 0L}, 'memory': {4299440L: '!', 4299439L: 'w'}}, 'disassembly': 'JA 0x419ad2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_80(self):
''' Instruction JA 0x416540 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 1L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285733L, 'RBP': 8192L}, 'memory': {4285733L: 'w', 4285734L: '\x19'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 1L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285735L, 'RBP': 8192L}, 'memory': {4285733L: 'w', 4285734L: '\x19'}}, 'disassembly': 'JA 0x416540', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_81(self):
''' Instruction JA 0x402448 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488344144L, 'RDX': 9L, 'RIP': 4203499L, 'RBP': 7049504L}, 'memory': {4203499L: 'w', 4203500L: '['}}, 'text': 'w[', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488344144L, 'RDX': 9L, 'RIP': 4203501L, 'RBP': 7049504L}, 'memory': {4203499L: 'w', 4203500L: '['}}, 'disassembly': 'JA 0x402448', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_82(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 6L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 6L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_83(self):
''' Instruction JA 0x419ae9 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 3L, 'RSP': 140737488345728L, 'RDX': 51L, 'RIP': 4299413L, 'RBP': 0L}, 'memory': {4299413L: 'w', 4299414L: 'R'}}, 'text': 'wR', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 3L, 'RSP': 140737488345728L, 'RDX': 51L, 'RIP': 4299415L, 'RBP': 0L}, 'memory': {4299413L: 'w', 4299414L: 'R'}}, 'disassembly': 'JA 0x419ae9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_84(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 50859318435822L, 'RIP': 4239599L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 50859318435822L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_85(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392872L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_86(self):
''' Instruction JA 0x40c8f0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 7035136L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245623L, 'RBP': 80L}, 'memory': {4245624L: 'w', 4245623L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 7035136L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245625L, 'RBP': 80L}, 'memory': {4245624L: 'w', 4245623L: 'w'}}, 'disassembly': 'JA 0x40c8f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_87(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347104L, 'RAX': 5L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347104L, 'RAX': 5L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_88(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 15L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 20L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 15L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 20L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_89(self):
''' Instruction JA 0x40c470 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244471L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244473L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'disassembly': 'JA 0x40c470', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_9(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_90(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239599L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_91(self):
''' Instruction JA 0x4307a8 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392657L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'text': '\x0f\x87\xd1\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392663L, 'RBP': 7049504L}, 'memory': {4392657L: '\x0f', 4392658L: '\x87', 4392659L: '\xd1', 4392660L: '\x00', 4392661L: '\x00', 4392662L: '\x00'}}, 'disassembly': 'JA 0x4307a8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_92(self):
''' Instruction JA 0x406b34 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7074240L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 138816L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4222761L, 'RBP': 7051232L}, 'memory': {4222761L: '\x0f', 4222762L: '\x87', 4222763L: '\x05', 4222764L: '\xfc', 4222765L: '\xff', 4222766L: '\xff'}}, 'text': '\x0f\x87\x05\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7074240L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 138816L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4222767L, 'RBP': 7051232L}, 'memory': {4222761L: '\x0f', 4222762L: '\x87', 4222763L: '\x05', 4222764L: '\xfc', 4222765L: '\xff', 4222766L: '\xff'}}, 'disassembly': 'JA 0x406b34', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_93(self):
''' Instruction JA 0x44bf9d '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 7074240L, 'RSP': 140737488346120L, 'RDX': 7074240L, 'RIP': 4505456L, 'RBP': 4544L}, 'memory': {4505456L: 'w', 4505457L: '+'}}, 'text': 'w+', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 7074240L, 'RSP': 140737488346120L, 'RDX': 7074240L, 'RIP': 4505458L, 'RBP': 4544L}, 'memory': {4505456L: 'w', 4505457L: '+'}}, 'disassembly': 'JA 0x44bf9d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_94(self):
''' Instruction JA 0x40c470 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244471L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'text': 'ww', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244473L, 'RBP': 7049504L}, 'memory': {4244472L: 'w', 4244471L: 'w'}}, 'disassembly': 'JA 0x40c470', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_95(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_96(self):
''' Instruction JA 0x419118 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 10L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296952L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'text': 'w\x1e', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 10L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296952L: 'w', 4296953L: '\x1e'}}, 'disassembly': 'JA 0x419118', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_97(self):
''' Instruction JA 0x40b10a '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239599L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'text': 'w\x19', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4239600L: '\x19', 4239599L: 'w'}}, 'disassembly': 'JA 0x40b10a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_98(self):
''' Instruction JA 0x406930 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221048L, 'RBP': 7051232L}, 'memory': {4221048L: '\x0f', 4221049L: '\x87', 4221050L: '\xb2', 4221051L: '\x00', 4221052L: '\x00', 4221053L: '\x00'}}, 'text': '\x0f\x87\xb2\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221232L, 'RBP': 7051232L}, 'memory': {4221048L: '\x0f', 4221049L: '\x87', 4221050L: '\xb2', 4221051L: '\x00', 4221052L: '\x00', 4221053L: '\x00'}}, 'disassembly': 'JA 0x406930', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJA_99(self):
''' Instruction JA 0x4306b0 '''
test = {'mnemonic': 'JA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392521L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'text': 'we', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125932L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392521L: 'w', 4392522L: 'e'}}, 'disassembly': 'JA 0x4306b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_1(self):
''' Instruction JBE 0x422a2d '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 2L, 'RSI': 140737354125693L, 'RDI': 140737354125691L, 'RAX': 2147483619L, 'RSP': 140737488344256L, 'RDX': 28L, 'RIP': 4337025L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'text': '\x0f\x86\xa6\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 2L, 'RSI': 140737354125693L, 'RDI': 140737354125691L, 'RAX': 2147483619L, 'RSP': 140737488344256L, 'RDX': 28L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'disassembly': 'JBE 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_10(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_11(self):
''' Instruction JBE 0x422a2d '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 2L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'RAX': 2147483625L, 'RSP': 140737488344256L, 'RDX': 22L, 'RIP': 4337025L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'text': '\x0f\x86\xa6\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 2L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'RAX': 2147483625L, 'RSP': 140737488344256L, 'RDX': 22L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'disassembly': 'JBE 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_12(self):
''' Instruction JBE 0x400a18 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194480L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196847L, 'RBP': 0L}, 'memory': {4196848L: "'", 4196847L: 'v'}}, 'text': "v'", 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194480L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196849L, 'RBP': 0L}, 'memory': {4196848L: "'", 4196847L: 'v'}}, 'disassembly': 'JBE 0x400a18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_13(self):
''' Instruction JBE 0x422a2d '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 1L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4337025L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'text': '\x0f\x86\xa6\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 1L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'disassembly': 'JBE 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_14(self):
''' Instruction JBE 0x422a2d '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4337025L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'text': '\x0f\x86\xa6\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'disassembly': 'JBE 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_15(self):
''' Instruction JBE 0x4068b0 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221032L, 'RBP': 7051232L}, 'memory': {4221032L: 'v', 4221033L: 'F'}}, 'text': 'vF', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4221034L, 'RBP': 7051232L}, 'memory': {4221032L: 'v', 4221033L: 'F'}}, 'disassembly': 'JBE 0x4068b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_16(self):
''' Instruction JBE 0x4160ef '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 13L, 'RDI': 194L, 'RAX': 32768L, 'RSP': 140737488346048L, 'RDX': 64L, 'RIP': 4284435L, 'RBP': 194L}, 'memory': {4284435L: '\x0f', 4284436L: '\x86', 4284437L: '\xd6', 4284438L: '\x00', 4284439L: '\x00', 4284440L: '\x00'}}, 'text': '\x0f\x86\xd6\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 13L, 'RDI': 194L, 'RAX': 32768L, 'RSP': 140737488346048L, 'RDX': 64L, 'RIP': 4284441L, 'RBP': 194L}, 'memory': {4284435L: '\x0f', 4284436L: '\x86', 4284437L: '\xd6', 4284438L: '\x00', 4284439L: '\x00', 4284440L: '\x00'}}, 'disassembly': 'JBE 0x4160ef', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_17(self):
''' Instruction JBE 0x4068b0 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 2L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221032L, 'RBP': 7051232L}, 'memory': {4221032L: 'v', 4221033L: 'F'}}, 'text': 'vF', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 2L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4221034L, 'RBP': 7051232L}, 'memory': {4221032L: 'v', 4221033L: 'F'}}, 'disassembly': 'JBE 0x4068b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_18(self):
''' Instruction JBE 0x422a2d '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4337025L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'text': '\x0f\x86\xa6\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'disassembly': 'JBE 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_19(self):
''' Instruction JBE 0x419e00 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 32L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300208L, 'RBP': 1L}, 'memory': {4300208L: 'v', 4300209L: 'N'}}, 'text': 'vN', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 32L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300288L, 'RBP': 1L}, 'memory': {4300208L: 'v', 4300209L: 'N'}}, 'disassembly': 'JBE 0x419e00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_2(self):
''' Instruction JBE 0x400a18 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194424L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196847L, 'RBP': 0L}, 'memory': {4196848L: "'", 4196847L: 'v'}}, 'text': "v'", 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194424L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196849L, 'RBP': 0L}, 'memory': {4196848L: "'", 4196847L: 'v'}}, 'disassembly': 'JBE 0x400a18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_20(self):
''' Instruction JBE 0x406b28 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 25L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219725L, 'RBP': 7051232L}, 'memory': {4219725L: '\x0f', 4219726L: '\x86', 4219727L: '\xd5', 4219728L: '\x07', 4219729L: '\x00', 4219730L: '\x00'}}, 'text': '\x0f\x86\xd5\x07\x00\x00', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 25L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4221736L, 'RBP': 7051232L}, 'memory': {4219725L: '\x0f', 4219726L: '\x86', 4219727L: '\xd5', 4219728L: '\x07', 4219729L: '\x00', 4219730L: '\x00'}}, 'disassembly': 'JBE 0x406b28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_21(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_22(self):
''' Instruction JBE 0x400a18 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194536L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196847L, 'RBP': 0L}, 'memory': {4196848L: "'", 4196847L: 'v'}}, 'text': "v'", 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194536L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196849L, 'RBP': 0L}, 'memory': {4196848L: "'", 4196847L: 'v'}}, 'disassembly': 'JBE 0x400a18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_23(self):
''' Instruction JBE 0x422a2d '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4337025L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'text': '\x0f\x86\xa6\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4337025L: '\x0f', 4337026L: '\x86', 4337027L: '\xa6', 4337028L: '\xfc', 4337029L: '\xff', 4337030L: '\xff'}}, 'disassembly': 'JBE 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_24(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_25(self):
''' Instruction JBE 0x406f18 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 138816L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4222735L, 'RBP': 7051232L}, 'memory': {4222736L: '\x07', 4222735L: 'v'}}, 'text': 'v\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 138816L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4222737L, 'RBP': 7051232L}, 'memory': {4222736L: '\x07', 4222735L: 'v'}}, 'disassembly': 'JBE 0x406f18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_3(self):
''' Instruction JBE 0x4160ef '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 13L, 'RDI': 188L, 'RAX': 1L, 'RSP': 140737488346048L, 'RDX': 140737488346512L, 'RIP': 4284435L, 'RBP': 188L}, 'memory': {4284435L: '\x0f', 4284436L: '\x86', 4284437L: '\xd6', 4284438L: '\x00', 4284439L: '\x00', 4284440L: '\x00'}}, 'text': '\x0f\x86\xd6\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 13L, 'RDI': 188L, 'RAX': 1L, 'RSP': 140737488346048L, 'RDX': 140737488346512L, 'RIP': 4284441L, 'RBP': 188L}, 'memory': {4284435L: '\x0f', 4284436L: '\x86', 4284437L: '\xd6', 4284438L: '\x00', 4284439L: '\x00', 4284440L: '\x00'}}, 'disassembly': 'JBE 0x4160ef', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_4(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_5(self):
''' Instruction JBE 0x43067e '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392564L, 'RBP': 7049504L}, 'memory': {4392564L: 'v', 4392565L: '\x08'}}, 'text': 'v\x08', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392566L, 'RBP': 7049504L}, 'memory': {4392564L: 'v', 4392565L: '\x08'}}, 'disassembly': 'JBE 0x43067e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_6(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_7(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 83L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 83L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_8(self):
''' Instruction JBE 0x421430 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330432L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'text': 'vn', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330544L, 'RBP': 140737488345936L}, 'memory': {4330432L: 'v', 4330433L: 'n'}}, 'disassembly': 'JBE 0x421430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJBE_9(self):
''' Instruction JBE 0x419ab8 '''
test = {'mnemonic': 'JBE', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 10L, 'RIP': 4299472L, 'RBP': 0L}, 'memory': {4299472L: 'v', 4299473L: '\xe6'}}, 'text': 'v\xe6', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 10L, 'RIP': 4299474L, 'RBP': 0L}, 'memory': {4299472L: 'v', 4299473L: '\xe6'}}, 'disassembly': 'JBE 0x419ab8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_1(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4241440L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 4L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4241440L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 4L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_10(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4248080L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 6L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4248080L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 6L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_11(self):
''' Instruction JB 0x419590 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 1L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194480L, 'RSP': 140737488346128L, 'RDX': 2L, 'RIP': 4298152L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'text': 'r\xe6', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 1L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194480L, 'RSP': 140737488346128L, 'RDX': 2L, 'RIP': 4298128L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'disassembly': 'JB 0x419590', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_12(self):
''' Instruction JB 0x4168b0 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 131136L, 'RIP': 4286561L, 'RBP': 135168L}, 'memory': {4286561L: 'r', 4286562L: 'M'}}, 'text': 'rM', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 131136L, 'RIP': 4286563L, 'RBP': 135168L}, 'memory': {4286561L: 'r', 4286562L: 'M'}}, 'disassembly': 'JB 0x4168b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_13(self):
''' Instruction JB 0x400e6a '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 7059408L, 'RIP': 4198004L, 'RBP': 7054840L}, 'memory': {4198004L: 'r', 4198005L: '\xf4'}}, 'text': 'r\xf4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 7059408L, 'RIP': 4198006L, 'RBP': 7054840L}, 'memory': {4198004L: 'r', 4198005L: '\xf4'}}, 'disassembly': 'JB 0x400e6a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_14(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4264928L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 9L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4264928L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 9L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_15(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4409968L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 10L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4409968L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 10L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_16(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4405584L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 3L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4405584L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 3L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_17(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4400160L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 1L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4400160L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 1L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_18(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 5L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 5L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_19(self):
''' Instruction JB 0x419590 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194536L, 'RSP': 140737488346128L, 'RDX': 3L, 'RIP': 4298152L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'text': 'r\xe6', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194536L, 'RSP': 140737488346128L, 'RDX': 3L, 'RIP': 4298128L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'disassembly': 'JB 0x419590', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_2(self):
''' Instruction JB 0x4168b0 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286561L, 'RBP': 4544L}, 'memory': {4286561L: 'r', 4286562L: 'M'}}, 'text': 'rM', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286563L, 'RBP': 4544L}, 'memory': {4286561L: 'r', 4286562L: 'M'}}, 'disassembly': 'JB 0x4168b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_20(self):
''' Instruction JB 0x4168b0 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 0L, 'RIP': 4286561L, 'RBP': 3648L}, 'memory': {4286561L: 'r', 4286562L: 'M'}}, 'text': 'rM', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 0L, 'RIP': 4286563L, 'RBP': 3648L}, 'memory': {4286561L: 'r', 4286562L: 'M'}}, 'disassembly': 'JB 0x4168b0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_21(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4465680L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 11L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4465680L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 11L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_22(self):
''' Instruction JB 0x419590 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 18446744073704757637L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194424L, 'RSP': 140737488346128L, 'RDX': 1L, 'RIP': 4298152L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'text': 'r\xe6', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 18446744073704757637L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194424L, 'RSP': 140737488346128L, 'RDX': 1L, 'RIP': 4298128L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'disassembly': 'JB 0x419590', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_3(self):
''' Instruction JB 0x400d60 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197747L, 'RBP': 4L}, 'memory': {4197747L: 'r', 4197748L: '\xeb'}}, 'text': 'r\xeb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197749L, 'RBP': 4L}, 'memory': {4197747L: 'r', 4197748L: '\xeb'}}, 'disassembly': 'JB 0x400d60', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_4(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 8L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 8L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_5(self):
''' Instruction JB 0x406de8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4222380L, 'RBP': 7051232L}, 'memory': {4222380L: 'r', 4222381L: ':'}}, 'text': 'r:', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4222440L, 'RBP': 7051232L}, 'memory': {4222380L: 'r', 4222381L: ':'}}, 'disassembly': 'JB 0x406de8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_6(self):
''' Instruction JB 0x419590 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 7L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194592L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4298152L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'text': 'r\xe6', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 7L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194592L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4298128L, 'RBP': 0L}, 'memory': {4298152L: 'r', 4298153L: '\xe6'}}, 'disassembly': 'JB 0x419590', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_7(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4467264L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 12L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4467264L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197593L, 'RBP': 12L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_8(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4716400L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 2L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4716400L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 2L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJB_9(self):
''' Instruction JB 0x400cb8 '''
test = {'mnemonic': 'JB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4664208L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197591L, 'RBP': 7L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'text': 'r\xdf', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4664208L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197560L, 'RBP': 7L}, 'memory': {4197592L: '\xdf', 4197591L: 'r'}}, 'disassembly': 'JB 0x400cb8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_1(self):
''' Instruction JG 0x4163f0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 0L, 'RAX': 28687L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4285008L, 'RBP': 32768L}, 'memory': {4285008L: '\x0f', 4285009L: '\x8f', 4285010L: '\x9a', 4285011L: '\x01', 4285012L: '\x00', 4285013L: '\x00'}}, 'text': '\x0f\x8f\x9a\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 0L, 'RAX': 28687L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4285424L, 'RBP': 32768L}, 'memory': {4285008L: '\x0f', 4285009L: '\x8f', 4285010L: '\x9a', 4285011L: '\x01', 4285012L: '\x00', 4285013L: '\x00'}}, 'disassembly': 'JG 0x4163f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_10(self):
''' Instruction JG 0x422bf0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336576L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'text': '\x7f.', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336578L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'disassembly': 'JG 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_2(self):
''' Instruction JG 0x4162d8 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285027L, 'RBP': 32768L}, 'memory': {4285027L: '\x7f', 4285028L: 's'}}, 'text': '\x7fs', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285144L, 'RBP': 32768L}, 'memory': {4285027L: '\x7f', 4285028L: 's'}}, 'disassembly': 'JG 0x4162d8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_3(self):
''' Instruction JG 0x422bf0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336576L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'text': '\x7f.', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336578L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'disassembly': 'JG 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_4(self):
''' Instruction JG 0x422bf0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336576L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'text': '\x7f.', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336578L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'disassembly': 'JG 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_5(self):
''' Instruction JG 0x422bf0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336576L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'text': '\x7f.', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336578L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'disassembly': 'JG 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_6(self):
''' Instruction JG 0x431a36 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 4222429316L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397768L, 'RBP': 4294967295L}, 'memory': {4397768L: '\x0f', 4397769L: '\x8f', 4397770L: 'h', 4397771L: '\xff', 4397772L: '\xff', 4397773L: '\xff'}}, 'text': '\x0f\x8fh\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 4222429316L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397774L, 'RBP': 4294967295L}, 'memory': {4397768L: '\x0f', 4397769L: '\x8f', 4397770L: 'h', 4397771L: '\xff', 4397772L: '\xff', 4397773L: '\xff'}}, 'disassembly': 'JG 0x431a36', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_7(self):
''' Instruction JG 0x422bf0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336576L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'text': '\x7f.', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336578L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'disassembly': 'JG 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_8(self):
''' Instruction JG 0x422bf0 '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336576L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'text': '\x7f.', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336578L, 'RBP': 140737488345936L}, 'memory': {4336576L: '\x7f', 4336577L: '.'}}, 'disassembly': 'JG 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJG_9(self):
''' Instruction JG 0x419afe '''
test = {'mnemonic': 'JG', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299500L, 'RBP': 0L}, 'memory': {4299500L: '\x7f', 4299501L: '\x10'}}, 'text': '\x7f\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299518L, 'RBP': 0L}, 'memory': {4299500L: '\x7f', 4299501L: '\x10'}}, 'disassembly': 'JG 0x419afe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_1(self):
''' Instruction JLE 0x422ecd '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337180L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'text': '\x0f\x8e\xab\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'disassembly': 'JLE 0x422ecd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_10(self):
''' Instruction JLE 0x4168c0 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286553L, 'RBP': 4544L}, 'memory': {4286553L: '~', 4286554L: 'e'}}, 'text': '~e', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286555L, 'RBP': 4544L}, 'memory': {4286553L: '~', 4286554L: 'e'}}, 'disassembly': 'JLE 0x4168c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_11(self):
''' Instruction JLE 0x4007c8 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346240L, 'RDX': 7065480L, 'RIP': 4196042L, 'RBP': 0L}, 'memory': {4196042L: '\x0f', 4196043L: '\x8e', 4196044L: '\xf8', 4196045L: '\x00', 4196046L: '\x00', 4196047L: '\x00'}}, 'text': '\x0f\x8e\xf8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346240L, 'RDX': 7065480L, 'RIP': 4196048L, 'RBP': 0L}, 'memory': {4196042L: '\x0f', 4196043L: '\x8e', 4196044L: '\xf8', 4196045L: '\x00', 4196046L: '\x00', 4196047L: '\x00'}}, 'disassembly': 'JLE 0x4007c8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_12(self):
''' Instruction JLE 0x422cfe '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336849L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'text': '~+', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'disassembly': 'JLE 0x422cfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_13(self):
''' Instruction JLE 0x422ecd '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337180L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'text': '\x0f\x8e\xab\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'disassembly': 'JLE 0x422ecd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_14(self):
''' Instruction JLE 0x402c28 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 7058288L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205370L, 'RBP': 7049504L}, 'memory': {4205370L: '\x0f', 4205371L: '\x8e', 4205372L: '\xe8', 4205373L: '\x00', 4205374L: '\x00', 4205375L: '\x00'}}, 'text': '\x0f\x8e\xe8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 7058288L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205608L, 'RBP': 7049504L}, 'memory': {4205370L: '\x0f', 4205371L: '\x8e', 4205372L: '\xe8', 4205373L: '\x00', 4205374L: '\x00', 4205375L: '\x00'}}, 'disassembly': 'JLE 0x402c28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_15(self):
''' Instruction JLE 0x416390 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4194304L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284927L, 'RBP': 32768L}, 'memory': {4284928L: '\x8e', 4284929L: '\x8b', 4284930L: '\x01', 4284931L: '\x00', 4284932L: '\x00', 4284927L: '\x0f'}}, 'text': '\x0f\x8e\x8b\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4194304L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284933L, 'RBP': 32768L}, 'memory': {4284928L: '\x8e', 4284929L: '\x8b', 4284930L: '\x01', 4284931L: '\x00', 4284932L: '\x00', 4284927L: '\x0f'}}, 'disassembly': 'JLE 0x416390', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_16(self):
''' Instruction JLE 0x402c28 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205370L, 'RBP': 7049728L}, 'memory': {4205370L: '\x0f', 4205371L: '\x8e', 4205372L: '\xe8', 4205373L: '\x00', 4205374L: '\x00', 4205375L: '\x00'}}, 'text': '\x0f\x8e\xe8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205608L, 'RBP': 7049728L}, 'memory': {4205370L: '\x0f', 4205371L: '\x8e', 4205372L: '\xe8', 4205373L: '\x00', 4205374L: '\x00', 4205375L: '\x00'}}, 'disassembly': 'JLE 0x402c28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_17(self):
''' Instruction JLE 0x422ecd '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337180L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'text': '\x0f\x8e\xab\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'disassembly': 'JLE 0x422ecd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_18(self):
''' Instruction JLE 0x416299 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285035L, 'RBP': 32768L}, 'memory': {4285035L: '~', 4285036L: ','}}, 'text': '~,', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285037L, 'RBP': 32768L}, 'memory': {4285035L: '~', 4285036L: ','}}, 'disassembly': 'JLE 0x416299', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_19(self):
''' Instruction JLE 0x471fd9 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661190L, 'RBP': 8192L}, 'memory': {4661190L: '~', 4661191L: '\x11'}}, 'text': '~\x11', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661192L, 'RBP': 8192L}, 'memory': {4661190L: '~', 4661191L: '\x11'}}, 'disassembly': 'JLE 0x471fd9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_2(self):
''' Instruction JLE 0x422cfe '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336849L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'text': '~+', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'disassembly': 'JLE 0x422cfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_20(self):
''' Instruction JLE 0x422ecd '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337180L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'text': '\x0f\x8e\xab\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'disassembly': 'JLE 0x422ecd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_21(self):
''' Instruction JLE 0x402e00 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7049504L, 'RSP': 140737488346112L, 'RDX': 7049636L, 'RIP': 4205937L, 'RBP': 1L}, 'memory': {4205937L: '\x0f', 4205938L: '\x8e', 4205939L: '\x89', 4205940L: '\x00', 4205941L: '\x00', 4205942L: '\x00'}}, 'text': '\x0f\x8e\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7049504L, 'RSP': 140737488346112L, 'RDX': 7049636L, 'RIP': 4206080L, 'RBP': 1L}, 'memory': {4205937L: '\x0f', 4205938L: '\x8e', 4205939L: '\x89', 4205940L: '\x00', 4205941L: '\x00', 4205942L: '\x00'}}, 'disassembly': 'JLE 0x402e00', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_22(self):
''' Instruction JLE 0x422cfe '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336849L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'text': '~+', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'disassembly': 'JLE 0x422cfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_23(self):
''' Instruction JLE 0x422cfe '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336849L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'text': '~+', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'disassembly': 'JLE 0x422cfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_24(self):
''' Instruction JLE 0x4305d0 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392237L, 'RBP': 699L}, 'memory': {4392237L: '\x0f', 4392238L: '\x8e', 4392239L: '\x9d', 4392240L: '\x00', 4392241L: '\x00', 4392242L: '\x00'}}, 'text': '\x0f\x8e\x9d\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392400L, 'RBP': 699L}, 'memory': {4392237L: '\x0f', 4392238L: '\x8e', 4392239L: '\x9d', 4392240L: '\x00', 4392241L: '\x00', 4392242L: '\x00'}}, 'disassembly': 'JLE 0x4305d0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_25(self):
''' Instruction JLE 0x407296 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223517L, 'RBP': 7051232L}, 'memory': {4223517L: '~', 4223518L: 'w'}}, 'text': '~w', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223519L, 'RBP': 7051232L}, 'memory': {4223517L: '~', 4223518L: 'w'}}, 'disassembly': 'JLE 0x407296', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_26(self):
''' Instruction JLE 0x422ecd '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337180L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'text': '\x0f\x8e\xab\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'disassembly': 'JLE 0x422ecd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_27(self):
''' Instruction JLE 0x430863 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393000L, 'RBP': 140737354125312L}, 'memory': {4393000L: '~', 4393001L: '9'}}, 'text': '~9', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393002L, 'RBP': 140737354125312L}, 'memory': {4393000L: '~', 4393001L: '9'}}, 'disassembly': 'JLE 0x430863', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_28(self):
''' Instruction JLE 0x422cfe '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336849L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'text': '~+', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'disassembly': 'JLE 0x422cfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_29(self):
''' Instruction JLE 0x4168c0 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 135168L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 131136L, 'RIP': 4286553L, 'RBP': 135168L}, 'memory': {4286553L: '~', 4286554L: 'e'}}, 'text': '~e', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 135168L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 131136L, 'RIP': 4286555L, 'RBP': 135168L}, 'memory': {4286553L: '~', 4286554L: 'e'}}, 'disassembly': 'JLE 0x4168c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_3(self):
''' Instruction JLE 0x41619e '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 16384L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285084L, 'RBP': 32768L}, 'memory': {4285088L: '\xff', 4285089L: '\xff', 4285084L: '\x0f', 4285085L: '\x8e', 4285086L: '\xfc', 4285087L: '\xfe'}}, 'text': '\x0f\x8e\xfc\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 16384L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285090L, 'RBP': 32768L}, 'memory': {4285088L: '\xff', 4285089L: '\xff', 4285084L: '\x0f', 4285085L: '\x8e', 4285086L: '\xfc', 4285087L: '\xfe'}}, 'disassembly': 'JLE 0x41619e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_4(self):
''' Instruction JLE 0x402c28 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 18446744073709551615L, 'RIP': 4205370L, 'RBP': 7049280L}, 'memory': {4205370L: '\x0f', 4205371L: '\x8e', 4205372L: '\xe8', 4205373L: '\x00', 4205374L: '\x00', 4205375L: '\x00'}}, 'text': '\x0f\x8e\xe8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 18446744073709551615L, 'RIP': 4205608L, 'RBP': 7049280L}, 'memory': {4205370L: '\x0f', 4205371L: '\x8e', 4205372L: '\xe8', 4205373L: '\x00', 4205374L: '\x00', 4205375L: '\x00'}}, 'disassembly': 'JLE 0x402c28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_5(self):
''' Instruction JLE 0x430890 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393014L, 'RBP': 140737354125312L}, 'memory': {4393014L: '~', 4393015L: 'X'}}, 'text': '~X', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393104L, 'RBP': 140737354125312L}, 'memory': {4393014L: '~', 4393015L: 'X'}}, 'disassembly': 'JLE 0x430890', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_6(self):
''' Instruction JLE 0x422cfe '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336849L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'text': '~+', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336849L: '~', 4336850L: '+'}}, 'disassembly': 'JLE 0x422cfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_7(self):
''' Instruction JLE 0x416448 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4194304L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284909L, 'RBP': 32768L}, 'memory': {4284909L: '\x0f', 4284910L: '\x8e', 4284911L: 'U', 4284912L: '\x02', 4284913L: '\x00', 4284914L: '\x00'}}, 'text': '\x0f\x8eU\x02\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4194304L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 64L, 'RIP': 4284915L, 'RBP': 32768L}, 'memory': {4284909L: '\x0f', 4284910L: '\x8e', 4284911L: 'U', 4284912L: '\x02', 4284913L: '\x00', 4284914L: '\x00'}}, 'disassembly': 'JLE 0x416448', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_8(self):
''' Instruction JLE 0x422ecd '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337180L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'text': '\x0f\x8e\xab\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337184L: '\x00', 4337185L: '\x00', 4337180L: '\x0f', 4337181L: '\x8e', 4337182L: '\xab', 4337183L: '\x00'}}, 'disassembly': 'JLE 0x422ecd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJLE_9(self):
''' Instruction JLE 0x4168c0 '''
test = {'mnemonic': 'JLE', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 0L, 'RIP': 4286553L, 'RBP': 3648L}, 'memory': {4286553L: '~', 4286554L: 'e'}}, 'text': '~e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 0L, 'RIP': 4286555L, 'RBP': 3648L}, 'memory': {4286553L: '~', 4286554L: 'e'}}, 'disassembly': 'JLE 0x4168c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_1(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_10(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_11(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_12(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_13(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_14(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_15(self):
''' Instruction JL 0x415e40 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283788L, 'RBP': 188L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'text': '\x0f\x8c\xae\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283794L, 'RBP': 188L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'disassembly': 'JL 0x415e40', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_16(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_17(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_18(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_19(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_2(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_20(self):
''' Instruction JL 0x415e40 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283788L, 'RBP': 188L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'text': '\x0f\x8c\xae\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283794L, 'RBP': 188L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'disassembly': 'JL 0x415e40', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_21(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_22(self):
''' Instruction JL 0x423396 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4336464L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'text': '\x0f\x8c@\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'disassembly': 'JL 0x423396', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_23(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_24(self):
''' Instruction JL 0x415e40 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283788L, 'RBP': 194L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'text': '\x0f\x8c\xae\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283794L, 'RBP': 194L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'disassembly': 'JL 0x415e40', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_25(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_26(self):
''' Instruction JL 0x423396 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336464L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'text': '\x0f\x8c@\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'disassembly': 'JL 0x423396', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_27(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_28(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_29(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_3(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_30(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_31(self):
''' Instruction JL 0x423396 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336464L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'text': '\x0f\x8c@\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'disassembly': 'JL 0x423396', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_32(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_33(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_34(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_35(self):
''' Instruction JL 0x423396 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4336464L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'text': '\x0f\x8c@\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'disassembly': 'JL 0x423396', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_36(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_37(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_38(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_39(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_4(self):
''' Instruction JL 0x423396 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336464L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'text': '\x0f\x8c@\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'disassembly': 'JL 0x423396', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_40(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_41(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_42(self):
''' Instruction JL 0x415e40 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283788L, 'RBP': 194L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'text': '\x0f\x8c\xae\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283794L, 'RBP': 194L}, 'memory': {4283788L: '\x0f', 4283789L: '\x8c', 4283790L: '\xae', 4283791L: '\x00', 4283792L: '\x00', 4283793L: '\x00'}}, 'disassembly': 'JL 0x415e40', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_43(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_44(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_45(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_46(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_47(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_48(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_49(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_5(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_50(self):
''' Instruction JL 0x423396 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4336464L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'text': '\x0f\x8c@\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {4336464L: '\x0f', 4336465L: '\x8c', 4336466L: '@', 4336467L: '\x08', 4336468L: '\x00', 4336469L: '\x00'}}, 'disassembly': 'JL 0x423396', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_51(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_52(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_53(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x1, test['pos']['registers'][reg_name]&0x1, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name)&1, test['pos']['registers'][reg_name]&1))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_54(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_55(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_56(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_57(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_58(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_59(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_6(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_60(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_61(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_62(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_63(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_64(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_7(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_8(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJL_9(self):
''' Instruction JL 0x41ee30 '''
test = {'mnemonic': 'JL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320781L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'text': '|!', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {4320781L: '|', 4320782L: '!'}}, 'disassembly': 'JL 0x41ee30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_1(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_10(self):
''' Instruction JMP 0x430712 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125931L, 'RAX': 140737354125931L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392891L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'text': '\xe9R\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125931L, 'RAX': 140737354125931L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392722L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'disassembly': 'JMP 0x430712', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_100(self):
''' Instruction JMP 0x430727 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344192L, 'RDX': 32L, 'RIP': 4392613L, 'RBP': 7049504L}, 'memory': {4392616L: '\x00', 4392617L: '\x00', 4392613L: '\xe9', 4392614L: '}', 4392615L: '\x00'}}, 'text': '\xe9}\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344192L, 'RDX': 32L, 'RIP': 4392743L, 'RBP': 7049504L}, 'memory': {4392616L: '\x00', 4392617L: '\x00', 4392613L: '\xe9', 4392614L: '}', 4392615L: '\x00'}}, 'disassembly': 'JMP 0x430727', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_101(self):
''' Instruction JMP 0x422c80 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337359L, 'RBP': 140737488345936L}, 'memory': {4337360L: '\xac', 4337361L: '\xfd', 4337362L: '\xff', 4337363L: '\xff', 4337359L: '\xe9'}}, 'text': '\xe9\xac\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336768L, 'RBP': 140737488345936L}, 'memory': {4337360L: '\xac', 4337361L: '\xfd', 4337362L: '\xff', 4337363L: '\xff', 4337359L: '\xe9'}}, 'disassembly': 'JMP 0x422c80', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_11(self):
''' Instruction JMP 0x430712 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'RAX': 140737354126010L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392891L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'text': '\xe9R\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'RAX': 140737354126010L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392722L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'disassembly': 'JMP 0x430712', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_12(self):
''' Instruction JMP 0x47c8c0 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346136L, 'RDX': 7058304L, 'RIP': 4705447L, 'RBP': 7035176L}, 'memory': {4705448L: '\x14', 4705449L: '\xfc', 4705450L: '\xff', 4705451L: '\xff', 4705447L: '\xe9'}}, 'text': '\xe9\x14\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346136L, 'RDX': 7058304L, 'RIP': 4704448L, 'RBP': 7035176L}, 'memory': {4705448L: '\x14', 4705449L: '\xfc', 4705450L: '\xff', 4705451L: '\xff', 4705447L: '\xe9'}}, 'disassembly': 'JMP 0x47c8c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_13(self):
''' Instruction JMP 0x422a2d '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'RAX': 2147483634L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4346963L, 'RBP': 140737488345936L}, 'memory': {4346963L: '\xe9', 4346964L: '\xd5', 4346965L: '\xd5', 4346966L: '\xff', 4346967L: '\xff'}}, 'text': '\xe9\xd5\xd5\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'RAX': 2147483634L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4336173L, 'RBP': 140737488345936L}, 'memory': {4346963L: '\xe9', 4346964L: '\xd5', 4346965L: '\xd5', 4346966L: '\xff', 4346967L: '\xff'}}, 'disassembly': 'JMP 0x422a2d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_14(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_15(self):
''' Instruction JMP 0x48e360 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7058304L, 'RIP': 4777056L, 'RBP': 140737488346144L}, 'memory': {4777056L: '\xe9', 4777057L: '\xfb', 4777058L: '\xfe', 4777059L: '\xff', 4777060L: '\xff'}}, 'text': '\xe9\xfb\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7058304L, 'RIP': 4776800L, 'RBP': 140737488346144L}, 'memory': {4777056L: '\xe9', 4777057L: '\xfb', 4777058L: '\xfe', 4777059L: '\xff', 4777060L: '\xff'}}, 'disassembly': 'JMP 0x48e360', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_16(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330575L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336380L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_17(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 4230816L, 'RSP': 140737488346072L, 'RDX': 7042720L, 'RIP': 4230614L, 'RBP': 140737488346112L}, 'memory': {4230614L: '\xff', 4230615L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 4230816L, 'RSP': 140737488346072L, 'RDX': 7042720L, 'RIP': 4230816L, 'RBP': 140737488346112L}, 'memory': {4230614L: '\xff', 4230615L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_18(self):
''' Instruction JMP 0x48e452 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 20L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4776868L, 'RBP': 4881624L}, 'memory': {4776872L: '\x00', 4776868L: '\xe9', 4776869L: '\xa9', 4776870L: '\x00', 4776871L: '\x00'}}, 'text': '\xe9\xa9\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 20L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4777042L, 'RBP': 4881624L}, 'memory': {4776872L: '\x00', 4776868L: '\xe9', 4776869L: '\xa9', 4776870L: '\x00', 4776871L: '\x00'}}, 'disassembly': 'JMP 0x48e452', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_19(self):
''' Instruction JMP 0x422b26 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'text': '\xe9\x97\xf6\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4336422L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'disassembly': 'JMP 0x422b26', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_2(self):
''' Instruction JMP 0x416268 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285163L, 'RBP': 32768L}, 'memory': {4285163L: '\xe9', 4285164L: 'x', 4285165L: '\xff', 4285166L: '\xff', 4285167L: '\xff'}}, 'text': '\xe9x\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285032L, 'RBP': 32768L}, 'memory': {4285163L: '\xe9', 4285164L: 'x', 4285165L: '\xff', 4285166L: '\xff', 4285167L: '\xff'}}, 'disassembly': 'JMP 0x416268', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_20(self):
''' Instruction JMP 0x48e1e0 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4776564L, 'RBP': 140737488346144L}, 'memory': {4776568L: '\xff', 4776564L: '\xe9', 4776565L: 'g', 4776566L: '\xff', 4776567L: '\xff'}}, 'text': '\xe9g\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4776416L, 'RBP': 140737488346144L}, 'memory': {4776568L: '\xff', 4776564L: '\xe9', 4776565L: 'g', 4776566L: '\xff', 4776567L: '\xff'}}, 'disassembly': 'JMP 0x48e1e0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_21(self):
''' Instruction JMP 0x402b6a '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205622L, 'RBP': 7049280L}, 'memory': {4205624L: '\xff', 4205625L: '\xff', 4205626L: '\xff', 4205622L: '\xe9', 4205623L: '/'}}, 'text': '\xe9/\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205418L, 'RBP': 7049280L}, 'memory': {4205624L: '\xff', 4205625L: '\xff', 4205626L: '\xff', 4205622L: '\xe9', 4205623L: '/'}}, 'disassembly': 'JMP 0x402b6a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_22(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_23(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 15L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 4297080L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 15L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 4297080L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297080L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_24(self):
''' Instruction JMP 0x41edea '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'text': '\xeb\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'disassembly': 'JMP 0x41edea', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_25(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330575L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336380L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_26(self):
''' Instruction JMP 0x415eb6 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284040L, 'RBP': 3L}, 'memory': {4284040L: '\xeb', 4284041L: ','}}, 'text': '\xeb,', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284086L, 'RBP': 3L}, 'memory': {4284040L: '\xeb', 4284041L: ','}}, 'disassembly': 'JMP 0x415eb6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_27(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_28(self):
''' Instruction JMP 0x41edea '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'text': '\xeb\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'disassembly': 'JMP 0x41edea', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_29(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 4297136L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 4297136L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297136L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_3(self):
''' Instruction JMP 0x416853 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286630L, 'RBP': 4544L}, 'memory': {4286630L: '\xeb', 4286631L: '\xab'}}, 'text': '\xeb\xab', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286547L, 'RBP': 4544L}, 'memory': {4286630L: '\xeb', 4286631L: '\xab'}}, 'disassembly': 'JMP 0x416853', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_30(self):
''' Instruction JMP 0x415e42 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4284280L, 'RBP': 3L}, 'memory': {4284280L: '\xe9', 4284281L: '\xc5', 4284282L: '\xfe', 4284283L: '\xff', 4284284L: '\xff'}}, 'text': '\xe9\xc5\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488345968L, 'RDX': 64L, 'RIP': 4283970L, 'RBP': 3L}, 'memory': {4284280L: '\xe9', 4284281L: '\xc5', 4284282L: '\xfe', 4284283L: '\xff', 4284284L: '\xff'}}, 'disassembly': 'JMP 0x415e42', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_31(self):
''' Instruction JMP 0x422b49 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338617L: '\xe9', 4338618L: '\x8b', 4338619L: '\xf7', 4338620L: '\xff', 4338621L: '\xff'}}, 'text': '\xe9\x8b\xf7\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4336457L, 'RBP': 140737488345936L}, 'memory': {4338617L: '\xe9', 4338618L: '\x8b', 4338619L: '\xf7', 4338620L: '\xff', 4338621L: '\xff'}}, 'disassembly': 'JMP 0x422b49', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_32(self):
''' Instruction JMP 0x431a8f '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 531L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 4222427268L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397962L, 'RBP': 4294967295L}, 'memory': {4397962L: '\xe9', 4397963L: '\x00', 4397964L: '\xff', 4397965L: '\xff', 4397966L: '\xff'}}, 'text': '\xe9\x00\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 531L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 4222427268L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397711L, 'RBP': 4294967295L}, 'memory': {4397962L: '\xe9', 4397963L: '\x00', 4397964L: '\xff', 4397965L: '\xff', 4397966L: '\xff'}}, 'disassembly': 'JMP 0x431a8f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_33(self):
''' Instruction JMP 0x406484 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 119L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 1648L, 'RIP': 4219929L, 'RBP': 7051232L}, 'memory': {4219929L: '\xeb', 4219930L: 'i'}}, 'text': '\xebi', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 119L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 1648L, 'RIP': 4220036L, 'RBP': 7051232L}, 'memory': {4219929L: '\xeb', 4219930L: 'i'}}, 'disassembly': 'JMP 0x406484', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_34(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_35(self):
''' Instruction JMP 0x4012d8 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354126011L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'text': '\xe9V\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354126011L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199128L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'disassembly': 'JMP 0x4012d8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_36(self):
''' Instruction JMP 0x419a8b '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299495L, 'RBP': 0L}, 'memory': {4299496L: '\xa2', 4299495L: '\xeb'}}, 'text': '\xeb\xa2', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299403L, 'RBP': 0L}, 'memory': {4299496L: '\xa2', 4299495L: '\xeb'}}, 'disassembly': 'JMP 0x419a8b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_37(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_38(self):
''' Instruction JMP 0x415eb6 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284040L, 'RBP': 9L}, 'memory': {4284040L: '\xeb', 4284041L: ','}}, 'text': '\xeb,', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284086L, 'RBP': 9L}, 'memory': {4284040L: '\xeb', 4284041L: ','}}, 'disassembly': 'JMP 0x415eb6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_39(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 4297176L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 4297176L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297176L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_4(self):
''' Instruction JMP 0x422c80 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337359L, 'RBP': 140737488345936L}, 'memory': {4337360L: '\xac', 4337361L: '\xfd', 4337362L: '\xff', 4337363L: '\xff', 4337359L: '\xe9'}}, 'text': '\xe9\xac\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336768L, 'RBP': 140737488345936L}, 'memory': {4337360L: '\xac', 4337361L: '\xfd', 4337362L: '\xff', 4337363L: '\xff', 4337359L: '\xe9'}}, 'disassembly': 'JMP 0x422c80', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_40(self):
''' Instruction JMP 0x41f46e '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322544L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'text': '\xe9y\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322414L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'disassembly': 'JMP 0x41f46e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_41(self):
''' Instruction JMP 0x422c80 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337359L, 'RBP': 140737488345936L}, 'memory': {4337360L: '\xac', 4337361L: '\xfd', 4337362L: '\xff', 4337363L: '\xff', 4337359L: '\xe9'}}, 'text': '\xe9\xac\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336768L, 'RBP': 140737488345936L}, 'memory': {4337360L: '\xac', 4337361L: '\xfd', 4337362L: '\xff', 4337363L: '\xff', 4337359L: '\xe9'}}, 'disassembly': 'JMP 0x422c80', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_42(self):
''' Instruction JMP 0x422b49 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338617L: '\xe9', 4338618L: '\x8b', 4338619L: '\xf7', 4338620L: '\xff', 4338621L: '\xff'}}, 'text': '\xe9\x8b\xf7\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336457L, 'RBP': 140737488345936L}, 'memory': {4338617L: '\xe9', 4338618L: '\x8b', 4338619L: '\xf7', 4338620L: '\xff', 4338621L: '\xff'}}, 'disassembly': 'JMP 0x422b49', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_43(self):
''' Instruction JMP 0x422b26 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'text': '\xe9\x97\xf6\xff\xff', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336422L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'disassembly': 'JMP 0x422b26', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_44(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330575L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336380L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_45(self):
''' Instruction JMP 0x4211ad '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 2147483617L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4338878L, 'RBP': 140737488345936L}, 'memory': {4338880L: '\xdc', 4338881L: '\xff', 4338882L: '\xff', 4338878L: '\xe9', 4338879L: '\xea'}}, 'text': '\xe9\xea\xdc\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 2147483617L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4329901L, 'RBP': 140737488345936L}, 'memory': {4338880L: '\xdc', 4338881L: '\xff', 4338882L: '\xff', 4338878L: '\xe9', 4338879L: '\xea'}}, 'disassembly': 'JMP 0x4211ad', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_46(self):
''' Instruction JMP 0x430712 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125408L, 'RAX': 140737354125408L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392891L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'text': '\xe9R\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125408L, 'RAX': 140737354125408L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392722L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'disassembly': 'JMP 0x430712', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_47(self):
''' Instruction JMP 0x4012d8 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125853L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'text': '\xe9V\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125853L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199128L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'disassembly': 'JMP 0x4012d8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_48(self):
''' Instruction JMP 0x416520 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 9L, 'RSI': 1L, 'RDI': 1L, 'RAX': 7041664L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4393211L, 'RBP': 8192L}, 'memory': {4393211L: '\xe9', 4393212L: ' ', 4393213L: '\\', 4393214L: '\xfe', 4393215L: '\xff'}}, 'text': '\xe9 \\\xfe\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 9L, 'RSI': 1L, 'RDI': 1L, 'RAX': 7041664L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285728L, 'RBP': 8192L}, 'memory': {4393211L: '\xe9', 4393212L: ' ', 4393213L: '\\', 4393214L: '\xfe', 4393215L: '\xff'}}, 'disassembly': 'JMP 0x416520', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_49(self):
''' Instruction JMP 0x416260 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285350L, 'RBP': 32768L}, 'memory': {4285352L: '\xfe', 4285353L: '\xff', 4285354L: '\xff', 4285350L: '\xe9', 4285351L: '\xb5'}}, 'text': '\xe9\xb5\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285024L, 'RBP': 32768L}, 'memory': {4285352L: '\xfe', 4285353L: '\xff', 4285354L: '\xff', 4285350L: '\xe9', 4285351L: '\xb5'}}, 'disassembly': 'JMP 0x416260', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_5(self):
''' Instruction JMP 0x4012d8 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125646L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'text': '\xe9V\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125646L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199128L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'disassembly': 'JMP 0x4012d8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_50(self):
''' Instruction JMP 0x41f46e '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322544L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'text': '\xe9y\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322414L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'disassembly': 'JMP 0x41f46e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_51(self):
''' Instruction JMP 0x41ee11 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'text': '\xeb\xe4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320785L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'disassembly': 'JMP 0x41ee11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_52(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 4297016L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 4297016L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297016L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_53(self):
''' Instruction JMP 0x4012d8 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125774L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'text': '\xe9V\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125774L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199128L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'disassembly': 'JMP 0x4012d8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_54(self):
''' Instruction JMP 0x41619e '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285134L, 'RBP': 32768L}, 'memory': {4285136L: '\xfe', 4285137L: '\xff', 4285138L: '\xff', 4285134L: '\xe9', 4285135L: '\xcb'}}, 'text': '\xe9\xcb\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4284830L, 'RBP': 32768L}, 'memory': {4285136L: '\xfe', 4285137L: '\xff', 4285138L: '\xff', 4285134L: '\xe9', 4285135L: '\xcb'}}, 'disassembly': 'JMP 0x41619e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_55(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 4297248L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 4297248L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297248L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_56(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 4297216L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 4297216L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297216L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_57(self):
''' Instruction JMP 0x422b49 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338617L: '\xe9', 4338618L: '\x8b', 4338619L: '\xf7', 4338620L: '\xff', 4338621L: '\xff'}}, 'text': '\xe9\x8b\xf7\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336457L, 'RBP': 140737488345936L}, 'memory': {4338617L: '\xe9', 4338618L: '\x8b', 4338619L: '\xf7', 4338620L: '\xff', 4338621L: '\xff'}}, 'disassembly': 'JMP 0x422b49', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_58(self):
''' Instruction JMP 0x407356 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4224091L, 'RBP': 7051232L}, 'memory': {4224091L: '\xe9', 4224092L: '\xf6', 4224093L: '\xfe', 4224094L: '\xff', 4224095L: '\xff'}}, 'text': '\xe9\xf6\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223830L, 'RBP': 7051232L}, 'memory': {4224091L: '\xe9', 4224092L: '\xf6', 4224093L: '\xfe', 4224094L: '\xff', 4224095L: '\xff'}}, 'disassembly': 'JMP 0x407356', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_59(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_6(self):
''' Instruction JMP 0x41a080 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347312L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4299772L, 'RBP': 0L}, 'memory': {4299776L: '\x00', 4299772L: '\xe9', 4299773L: '\x7f', 4299774L: '\x04', 4299775L: '\x00'}}, 'text': '\xe9\x7f\x04\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347312L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4300928L, 'RBP': 0L}, 'memory': {4299776L: '\x00', 4299772L: '\xe9', 4299773L: '\x7f', 4299774L: '\x04', 4299775L: '\x00'}}, 'disassembly': 'JMP 0x41a080', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_60(self):
''' Instruction JMP 0x4041ec '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211269L, 'RBP': 7051232L}, 'memory': {4211269L: '\xeb', 4211270L: '\xa5'}}, 'text': '\xeb\xa5', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211180L, 'RBP': 7051232L}, 'memory': {4211269L: '\xeb', 4211270L: '\xa5'}}, 'disassembly': 'JMP 0x4041ec', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_61(self):
''' Instruction JMP 0x422b26 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'text': '\xe9\x97\xf6\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4336422L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'disassembly': 'JMP 0x422b26', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_62(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_63(self):
''' Instruction JMP 0x400a25 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194536L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196880L, 'RBP': 80L}, 'memory': {4196880L: '\xeb', 4196881L: '\x13'}}, 'text': '\xeb\x13', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194536L, 'RSP': 140737488346160L, 'RDX': 4194760L, 'RIP': 4196901L, 'RBP': 80L}, 'memory': {4196880L: '\xeb', 4196881L: '\x13'}}, 'disassembly': 'JMP 0x400a25', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_64(self):
''' Instruction JMP 0x422f1b '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338592L, 'RBP': 140737488345936L}, 'memory': {4338592L: '\xe9', 4338593L: 'v', 4338594L: '\xfb', 4338595L: '\xff', 4338596L: '\xff'}}, 'text': '\xe9v\xfb\xff\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4337435L, 'RBP': 140737488345936L}, 'memory': {4338592L: '\xe9', 4338593L: 'v', 4338594L: '\xfb', 4338595L: '\xff', 4338596L: '\xff'}}, 'disassembly': 'JMP 0x422f1b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_65(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330575L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336380L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_66(self):
''' Instruction JMP 0x41f46e '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322544L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'text': '\xe9y\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322414L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'disassembly': 'JMP 0x41f46e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_67(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_68(self):
''' Instruction JMP 0x41ee11 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'text': '\xeb\xe4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320785L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'disassembly': 'JMP 0x41ee11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_69(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_7(self):
''' Instruction JMP 0x422b26 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'text': '\xe9\x97\xf6\xff\xff', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336422L, 'RBP': 140737488345936L}, 'memory': {4338826L: '\xe9', 4338827L: '\x97', 4338828L: '\xf6', 4338829L: '\xff', 4338830L: '\xff'}}, 'disassembly': 'JMP 0x422b26', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_70(self):
''' Instruction JMP 0x4211ad '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 140737354125329L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4338878L, 'RBP': 140737488345936L}, 'memory': {4338880L: '\xdc', 4338881L: '\xff', 4338882L: '\xff', 4338878L: '\xe9', 4338879L: '\xea'}}, 'text': '\xe9\xea\xdc\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 140737354125329L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4329901L, 'RBP': 140737488345936L}, 'memory': {4338880L: '\xdc', 4338881L: '\xff', 4338882L: '\xff', 4338878L: '\xe9', 4338879L: '\xea'}}, 'disassembly': 'JMP 0x4211ad', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_71(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_72(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 4782991L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 140737488346159L, 'RIP': 4198812L, 'RBP': 140737488346224L}, 'memory': {4198812L: '\xff', 4198813L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 4782991L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 140737488346159L, 'RIP': 4198854L, 'RBP': 140737488346224L}, 'memory': {4198812L: '\xff', 4198813L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_73(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347056L, 'RAX': 4296984L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347056L, 'RAX': 4296984L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296984L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_74(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_75(self):
''' Instruction JMP 0x430533 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392412L, 'RBP': 699L}, 'memory': {4392416L: '\xff', 4392412L: '\xe9', 4392413L: 'R', 4392414L: '\xff', 4392415L: '\xff'}}, 'text': '\xe9R\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392243L, 'RBP': 699L}, 'memory': {4392416L: '\xff', 4392412L: '\xe9', 4392413L: 'R', 4392414L: '\xff', 4392415L: '\xff'}}, 'disassembly': 'JMP 0x430533', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_76(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_77(self):
''' Instruction JMP 0x41f46e '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322544L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'text': '\xe9y\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322414L, 'RBP': 0L}, 'memory': {4322544L: '\xe9', 4322545L: 'y', 4322546L: '\xff', 4322547L: '\xff', 4322548L: '\xff'}}, 'disassembly': 'JMP 0x41f46e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_78(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782888L, 'RDI': 4782888L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 140737488346159L, 'RIP': 4198812L, 'RBP': 140737488346224L}, 'memory': {4198812L: '\xff', 4198813L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782888L, 'RDI': 4782888L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 140737488346159L, 'RIP': 4198854L, 'RBP': 140737488346224L}, 'memory': {4198812L: '\xff', 4198813L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_79(self):
''' Instruction JMP 0x41edea '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'text': '\xeb\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'disassembly': 'JMP 0x41edea', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_8(self):
''' Instruction JMP 0x41edea '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'text': '\xeb\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {4320731L: '\xeb', 4320732L: '\r'}}, 'disassembly': 'JMP 0x41edea', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_80(self):
''' Instruction JMP 0x4164a0 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 60L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4285573L, 'RBP': 7054840L}, 'memory': {4285573L: '\xeb', 4285574L: '\x19'}}, 'text': '\xeb\x19', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 60L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4285600L, 'RBP': 7054840L}, 'memory': {4285573L: '\xeb', 4285574L: '\x19'}}, 'disassembly': 'JMP 0x4164a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_81(self):
''' Instruction JMP 0x4012d8 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125567L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199293L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'text': '\xe9V\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 140737354125567L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199128L, 'RBP': 4782912L}, 'memory': {4199296L: '\xff', 4199297L: '\xff', 4199293L: '\xe9', 4199294L: 'V', 4199295L: '\xff'}}, 'disassembly': 'JMP 0x4012d8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_82(self):
''' Instruction JMP 0x41ee11 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'text': '\xeb\xe4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320785L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'disassembly': 'JMP 0x41ee11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_83(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 4296984L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 4296984L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296984L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_84(self):
''' Instruction JMP 0x41ee11 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'text': '\xeb\xe4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320785L, 'RBP': 4792416L}, 'memory': {4320811L: '\xeb', 4320812L: '\xe4'}}, 'disassembly': 'JMP 0x41ee11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_85(self):
''' Instruction JMP 0x422f1b '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338592L, 'RBP': 140737488345936L}, 'memory': {4338592L: '\xe9', 4338593L: 'v', 4338594L: '\xfb', 4338595L: '\xff', 4338596L: '\xff'}}, 'text': '\xe9v\xfb\xff\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4337435L, 'RBP': 140737488345936L}, 'memory': {4338592L: '\xe9', 4338593L: 'v', 4338594L: '\xfb', 4338595L: '\xff', 4338596L: '\xff'}}, 'disassembly': 'JMP 0x422f1b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_86(self):
''' Instruction JMP 0x402d5c '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'RAX': 4096L, 'RSP': 140737488346112L, 'RDX': 140737354125312L, 'RIP': 4206075L, 'RBP': 1L}, 'memory': {4206075L: '\xe9', 4206076L: '\\', 4206077L: '\xff', 4206078L: '\xff', 4206079L: '\xff'}}, 'text': '\xe9\\\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'RAX': 4096L, 'RSP': 140737488346112L, 'RDX': 140737354125312L, 'RIP': 4205916L, 'RBP': 1L}, 'memory': {4206075L: '\xe9', 4206076L: '\\', 4206077L: '\xff', 4206078L: '\xff', 4206079L: '\xff'}}, 'disassembly': 'JMP 0x402d5c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_87(self):
''' Instruction JMP 0x40064c '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'RAX': 0L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196310L, 'RBP': 0L}, 'memory': {4196312L: '\xfe', 4196313L: '\xff', 4196314L: '\xff', 4196310L: '\xe9', 4196311L: 'q'}}, 'text': '\xe9q\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'RAX': 0L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4195916L, 'RBP': 0L}, 'memory': {4196312L: '\xfe', 4196313L: '\xff', 4196314L: '\xff', 4196310L: '\xe9', 4196311L: 'q'}}, 'disassembly': 'JMP 0x40064c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_88(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_89(self):
''' Instruction JMP 0x48e402 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 7064712L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4777049L, 'RBP': 4881624L}, 'memory': {4777049L: '\xeb', 4777050L: '\xa7'}}, 'text': '\xeb\xa7', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 7064712L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4776962L, 'RBP': 4881624L}, 'memory': {4777049L: '\xeb', 4777050L: '\xa7'}}, 'disassembly': 'JMP 0x48e402', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_9(self):
''' Instruction JMP 0x402d80 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4206163L, 'RBP': 1L}, 'memory': {4206163L: '\xe9', 4206164L: '(', 4206165L: '\xff', 4206166L: '\xff', 4206167L: '\xff'}}, 'text': '\xe9(\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4205952L, 'RBP': 1L}, 'memory': {4206163L: '\xe9', 4206164L: '(', 4206165L: '\xff', 4206166L: '\xff', 4206167L: '\xff'}}, 'disassembly': 'JMP 0x402d80', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_90(self):
''' Instruction JMP 0x43637c '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 31L, 'RSI': 4129L, 'RDI': 140737488347328L, 'RAX': 140737488347324L, 'RSP': 140737488346168L, 'RDX': 12L, 'RIP': 4416441L, 'RBP': 140737488347312L}, 'memory': {4416441L: '\xeb', 4416442L: '\xc1'}}, 'text': '\xeb\xc1', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 31L, 'RSI': 4129L, 'RDI': 140737488347328L, 'RAX': 140737488347324L, 'RSP': 140737488346168L, 'RDX': 12L, 'RIP': 4416380L, 'RBP': 140737488347312L}, 'memory': {4416441L: '\xeb', 4416442L: '\xc1'}}, 'disassembly': 'JMP 0x43637c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_91(self):
''' Instruction JMP 0x41604f '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 13L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346048L, 'RDX': 1L, 'RIP': 4284601L, 'RBP': 194L}, 'memory': {4284601L: '\xeb', 4284602L: '\x94'}}, 'text': '\xeb\x94', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 13L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346048L, 'RDX': 1L, 'RIP': 4284495L, 'RBP': 194L}, 'memory': {4284601L: '\xeb', 4284602L: '\x94'}}, 'disassembly': 'JMP 0x41604f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_92(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330575L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336380L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_93(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_94(self):
''' Instruction JMP 0x40b127 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239624L: '\xeb', 4239625L: '\x1d'}}, 'text': '\xeb\x1d', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239624L: '\xeb', 4239625L: '\x1d'}}, 'disassembly': 'JMP 0x40b127', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_95(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 4297312L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296961L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 4297312L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297312L, 'RBP': 0L}, 'memory': {4296961L: '\xff', 4296962L: '\xe0'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_96(self):
''' Instruction JMP 0x430712 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125645L, 'RAX': 140737354125645L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392891L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'text': '\xe9R\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125645L, 'RAX': 140737354125645L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392722L, 'RBP': 7049504L}, 'memory': {4392891L: '\xe9', 4392892L: 'R', 4392893L: '\xff', 4392894L: '\xff', 4392895L: '\xff'}}, 'disassembly': 'JMP 0x430712', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_97(self):
''' Instruction JMP 0x40b127 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239624L, 'RBP': 4782912L}, 'memory': {4239624L: '\xeb', 4239625L: '\x1d'}}, 'text': '\xeb\x1d', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239624L: '\xeb', 4239625L: '\x1d'}}, 'disassembly': 'JMP 0x40b127', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_98(self):
''' Instruction JMP RAX '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4340492L, 'RSP': 140737488344256L, 'RDX': 21L, 'RIP': 4330575L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'text': '\xff\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4340492L, 'RSP': 140737488344256L, 'RDX': 21L, 'RIP': 4340492L, 'RBP': 140737488345936L}, 'memory': {4330576L: '\xe0', 4330575L: '\xff'}}, 'disassembly': 'JMP RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJMP_99(self):
''' Instruction JMP 0x41ede4 '''
test = {'mnemonic': 'JMP', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'text': '\xeb\xae', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320820L: '\xeb', 4320821L: '\xae'}}, 'disassembly': 'JMP 0x41ede4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_1(self):
''' Instruction JNS 0x407398 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7213056L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223863L, 'RBP': 7051232L}, 'memory': {4223864L: '\x1f', 4223863L: 'y'}}, 'text': 'y\x1f', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7213056L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223896L, 'RBP': 7051232L}, 'memory': {4223864L: '\x1f', 4223863L: 'y'}}, 'disassembly': 'JNS 0x407398', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_2(self):
''' Instruction JNS 0x4233a5 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'text': '\x0f\x89v\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338597L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'disassembly': 'JNS 0x4233a5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_3(self):
''' Instruction JNS 0x4233a5 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'text': '\x0f\x89v\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338597L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'disassembly': 'JNS 0x4233a5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_4(self):
''' Instruction JNS 0x4233a5 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'text': '\x0f\x89v\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4338597L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'disassembly': 'JNS 0x4233a5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_5(self):
''' Instruction JNS 0x4233a5 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'text': '\x0f\x89v\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338597L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'disassembly': 'JNS 0x4233a5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_6(self):
''' Instruction JNS 0x4233a5 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'text': '\x0f\x89v\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338597L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'disassembly': 'JNS 0x4233a5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_7(self):
''' Instruction JNS 0x4233a5 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'text': '\x0f\x89v\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338597L, 'RBP': 140737488345936L}, 'memory': {4336425L: '\x0f', 4336426L: '\x89', 4336427L: 'v', 4336428L: '\x08', 4336429L: '\x00', 4336430L: '\x00'}}, 'disassembly': 'JNS 0x4233a5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNS_8(self):
''' Instruction JNS 0x430830 '''
test = {'mnemonic': 'JNS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393046L, 'RBP': 140737354125312L}, 'memory': {4393046L: 'y', 4393047L: '\xd8'}}, 'text': 'y\xd8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393008L, 'RBP': 140737354125312L}, 'memory': {4393046L: 'y', 4393047L: '\xd8'}}, 'disassembly': 'JNS 0x430830', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_1(self):
''' Instruction JNZ 0x404890 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350989L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'text': 'u\xeb', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350989L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'disassembly': 'JNZ 0x404890', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_10(self):
''' Instruction JNZ 0x40b1a0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239704L, 'RBP': 4782912L}, 'memory': {4239704L: 'u', 4239705L: 'F'}}, 'text': 'uF', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239704L: 'u', 4239705L: 'F'}}, 'disassembly': 'JNZ 0x40b1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_100(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488347906L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488347906L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_101(self):
''' Instruction JNZ 0x401325 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199153L, 'RBP': 4782912L}, 'memory': {4199153L: 'u', 4199154L: '2'}}, 'text': 'u2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199155L, 'RBP': 4782912L}, 'memory': {4199153L: 'u', 4199154L: '2'}}, 'disassembly': 'JNZ 0x401325', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_11(self):
''' Instruction JNZ 0x409132 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 30L, 'RIP': 4231357L, 'RBP': 140737488345936L}, 'memory': {4231357L: 'u', 4231358L: 's'}}, 'text': 'us', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 30L, 'RIP': 4231359L, 'RBP': 140737488345936L}, 'memory': {4231357L: 'u', 4231358L: 's'}}, 'disassembly': 'JNZ 0x409132', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_12(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488347906L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488347906L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_13(self):
''' Instruction JNZ 0x4041c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052376L, 'RSP': 140737488345712L, 'RDX': 1056L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'text': 'u\xe7', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052376L, 'RSP': 140737488345712L, 'RDX': 1056L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'disassembly': 'JNZ 0x4041c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_14(self):
''' Instruction JNZ 0x41f498 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322412L, 'RBP': 140737488346472L}, 'memory': {4322412L: 'u', 4322413L: '*'}}, 'text': 'u*', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322456L, 'RBP': 140737488346472L}, 'memory': {4322412L: 'u', 4322413L: '*'}}, 'disassembly': 'JNZ 0x41f498', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_15(self):
''' Instruction JNZ 0x41ede0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320783L, 'RBP': 4792416L}, 'memory': {4320784L: '\xcf', 4320783L: 'u'}}, 'text': 'u\xcf', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320736L, 'RBP': 4792416L}, 'memory': {4320784L: '\xcf', 4320783L: 'u'}}, 'disassembly': 'JNZ 0x41ede0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_16(self):
''' Instruction JNZ 0x40b1a0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239704L, 'RBP': 4782912L}, 'memory': {4239704L: 'u', 4239705L: 'F'}}, 'text': 'uF', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239704L: 'u', 4239705L: 'F'}}, 'disassembly': 'JNZ 0x40b1a0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_17(self):
''' Instruction JNZ 0x420920 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 2L, 'RAX': 49L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327748L, 'RBP': 140737488345936L}, 'memory': {4327748L: 'u', 4327749L: '\xda'}}, 'text': 'u\xda', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 2L, 'RAX': 49L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327712L, 'RBP': 140737488345936L}, 'memory': {4327748L: 'u', 4327749L: '\xda'}}, 'disassembly': 'JNZ 0x420920', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_18(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488347948L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488347948L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_19(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488350490L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488350490L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_2(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322501L, 'RBP': 140737488350453L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350453L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_20(self):
''' Instruction JNZ 0x408db9 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 1600L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230072L, 'RBP': 140737488346112L}, 'memory': {4230072L: '\x0f', 4230073L: '\x85', 4230074L: '\xfb', 4230075L: '\x01', 4230076L: '\x00', 4230077L: '\x00'}}, 'text': '\x0f\x85\xfb\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 1600L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230078L, 'RBP': 140737488346112L}, 'memory': {4230072L: '\x0f', 4230073L: '\x85', 4230074L: '\xfb', 4230075L: '\x01', 4230076L: '\x00', 4230077L: '\x00'}}, 'disassembly': 'JNZ 0x408db9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_21(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488350328L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488350328L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_22(self):
''' Instruction JNZ 0x421400 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 4294967040L, 'RDI': 4782912L, 'RAX': 4782897L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4329713L, 'RBP': 140737488345936L}, 'memory': {4329713L: '\x0f', 4329714L: '\x85', 4329715L: '\t', 4329716L: '\x03', 4329717L: '\x00', 4329718L: '\x00'}}, 'text': '\x0f\x85\t\x03\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 4294967040L, 'RDI': 4782912L, 'RAX': 4782897L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4329719L, 'RBP': 140737488345936L}, 'memory': {4329713L: '\x0f', 4329714L: '\x85', 4329715L: '\t', 4329716L: '\x03', 4329717L: '\x00', 4329718L: '\x00'}}, 'disassembly': 'JNZ 0x421400', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_23(self):
''' Instruction JNZ 0x400680 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346920L, 'RAX': 140737488350976L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'text': 'u\xf4', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346920L, 'RAX': 140737488350976L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'disassembly': 'JNZ 0x400680', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_24(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488347727L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488347727L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_25(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488350405L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488350405L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_26(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488347727L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488347727L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_27(self):
''' Instruction JNZ 0x43064b '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 51L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'text': '\x0f\x85$\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 51L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392743L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'disassembly': 'JNZ 0x43064b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_28(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322501L, 'RBP': 140737488347684L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488347684L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_29(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488350181L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488350181L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_3(self):
''' Instruction JNZ 0x404890 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488347948L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'text': 'u\xeb', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488347948L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'disassembly': 'JNZ 0x404890', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_30(self):
''' Instruction JNZ 0x4041c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053160L, 'RSP': 140737488345712L, 'RDX': 1840L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'text': 'u\xe7', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053160L, 'RSP': 140737488345712L, 'RDX': 1840L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'disassembly': 'JNZ 0x4041c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_31(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488349968L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488349968L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_32(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488351032L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488351032L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_33(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488347630L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488347630L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_34(self):
''' Instruction JNZ 0x40b17b '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239615L, 'RBP': 140737488346472L}, 'memory': {4239616L: 'z', 4239615L: 'u'}}, 'text': 'uz', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239617L, 'RBP': 140737488346472L}, 'memory': {4239616L: 'z', 4239615L: 'u'}}, 'disassembly': 'JNZ 0x40b17b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_35(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488347858L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488347858L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_36(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488349565L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488349565L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_37(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350163L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350163L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_38(self):
''' Instruction JNZ 0x4190f0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 11L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296994L, 'RBP': 0L}, 'memory': {4296994L: 'u', 4296995L: '\xcc'}}, 'text': 'u\xcc', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 11L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296994L: 'u', 4296995L: '\xcc'}}, 'disassembly': 'JNZ 0x4190f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_39(self):
''' Instruction JNZ 0x43064b '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783040L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'text': '\x0f\x85$\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783040L, 'RIP': 4392743L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'disassembly': 'JNZ 0x43064b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_4(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322501L, 'RBP': 140737488347777L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322530L, 'RBP': 140737488347777L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_40(self):
''' Instruction JNZ 0x40c346 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125917L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244579L, 'RBP': 7049504L}, 'memory': {4244579L: '\x0f', 4244580L: '\x85', 4244581L: '\xdd', 4244582L: '\xfe', 4244583L: '\xff', 4244584L: '\xff'}}, 'text': '\x0f\x85\xdd\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125917L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244294L, 'RBP': 7049504L}, 'memory': {4244579L: '\x0f', 4244580L: '\x85', 4244581L: '\xdd', 4244582L: '\xfe', 4244583L: '\xff', 4244584L: '\xff'}}, 'disassembly': 'JNZ 0x40c346', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_41(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350035L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350035L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_42(self):
''' Instruction JNZ 0x423774 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4782905L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4340532L, 'RBP': 140737488345936L}, 'memory': {4340532L: '\x0f', 4340533L: '\x85', 4340534L: ':', 4340535L: '\xfc', 4340536L: '\xff', 4340537L: '\xff'}}, 'text': '\x0f\x85:\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4782905L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339572L, 'RBP': 140737488345936L}, 'memory': {4340532L: '\x0f', 4340533L: '\x85', 4340534L: ':', 4340535L: '\xfc', 4340536L: '\xff', 4340537L: '\xff'}}, 'disassembly': 'JNZ 0x423774', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_43(self):
''' Instruction JNZ 0x4041c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052088L, 'RSP': 140737488345712L, 'RDX': 768L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'text': 'u\xe7', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052088L, 'RSP': 140737488345712L, 'RDX': 768L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'disassembly': 'JNZ 0x4041c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_44(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322501L, 'RBP': 140737488350405L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488350405L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_45(self):
''' Instruction JNZ 0x4306f0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125663L, 'RDI': 140737354125651L, 'RAX': 140737354125652L, 'RSP': 140737488344192L, 'RDX': 4782998L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392704L: 'u', 4392705L: '\xee'}}, 'text': 'u\xee', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125663L, 'RDI': 140737354125651L, 'RAX': 140737354125652L, 'RSP': 140737488344192L, 'RDX': 4782998L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392704L: 'u', 4392705L: '\xee'}}, 'disassembly': 'JNZ 0x4306f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_46(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488349535L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488349535L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_47(self):
''' Instruction JNZ 0x402db0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4205874L, 'RBP': 1L}, 'memory': {4205874L: 'u', 4205875L: '|'}}, 'text': 'u|', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4205876L, 'RBP': 1L}, 'memory': {4205874L: 'u', 4205875L: '|'}}, 'disassembly': 'JNZ 0x402db0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_48(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350398L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350398L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_49(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488350163L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488350163L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_5(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488347397L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322530L, 'RBP': 140737488347397L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_50(self):
''' Instruction JNZ 0x400680 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346880L, 'RAX': 140737488350653L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'text': 'u\xf4', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346880L, 'RAX': 140737488350653L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'disassembly': 'JNZ 0x400680', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_51(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488349720L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488349720L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_52(self):
''' Instruction JNZ 0x4041c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 624L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'text': 'u\xe7', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 624L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'disassembly': 'JNZ 0x4041c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_53(self):
''' Instruction JNZ 0x40b178 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239653L, 'RBP': 140737488346472L}, 'memory': {4239653L: 'u', 4239654L: 'Q'}}, 'text': 'uQ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 140737488346472L}, 'memory': {4239653L: 'u', 4239654L: 'Q'}}, 'disassembly': 'JNZ 0x40b178', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_54(self):
''' Instruction JNZ 0x430898 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393025L, 'RBP': 140737354125312L}, 'memory': {4393025L: 'u', 4393026L: 'U'}}, 'text': 'uU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4393027L, 'RBP': 140737354125312L}, 'memory': {4393025L: 'u', 4393026L: 'U'}}, 'disassembly': 'JNZ 0x430898', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_55(self):
''' Instruction JNZ 0x4041c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052952L, 'RSP': 140737488345712L, 'RDX': 1632L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'text': 'u\xe7', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052952L, 'RSP': 140737488345712L, 'RDX': 1632L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'disassembly': 'JNZ 0x4041c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_56(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488350163L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488350163L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_57(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350544L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350544L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_58(self):
''' Instruction JNZ 0x43064b '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783020L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'text': '\x0f\x85$\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783020L, 'RIP': 4392743L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'disassembly': 'JNZ 0x43064b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_59(self):
''' Instruction JNZ 0x40b190 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239691L, 'RBP': 4782912L}, 'memory': {4239691L: 'u', 4239692L: 'C'}}, 'text': 'uC', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239691L: 'u', 4239692L: 'C'}}, 'disassembly': 'JNZ 0x40b190', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_6(self):
''' Instruction JNZ 0x400680 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346808L, 'RAX': 140737488350464L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'text': 'u\xf4', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346808L, 'RAX': 140737488350464L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'disassembly': 'JNZ 0x400680', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_60(self):
''' Instruction JNZ 0x422ba8 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337514L, 'RBP': 140737488345936L}, 'memory': {4337514L: '\x0f', 4337515L: '\x85', 4337516L: '8', 4337517L: '\xfc', 4337518L: '\xff', 4337519L: '\xff'}}, 'text': '\x0f\x858\xfc\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337520L, 'RBP': 140737488345936L}, 'memory': {4337514L: '\x0f', 4337515L: '\x85', 4337516L: '8', 4337517L: '\xfc', 4337518L: '\xff', 4337519L: '\xff'}}, 'disassembly': 'JNZ 0x422ba8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_61(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488347664L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488347664L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_62(self):
''' Instruction JNZ 0x40b178 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239653L, 'RBP': 140737488346472L}, 'memory': {4239653L: 'u', 4239654L: 'Q'}}, 'text': 'uQ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 140737488346472L}, 'memory': {4239653L: 'u', 4239654L: 'Q'}}, 'disassembly': 'JNZ 0x40b178', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_63(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322501L, 'RBP': 140737488350223L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322530L, 'RBP': 140737488350223L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_64(self):
''' Instruction JNZ 0x43064b '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783034L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'text': '\x0f\x85$\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783034L, 'RIP': 4392743L, 'RBP': 7049504L}, 'memory': {4392737L: '\x0f', 4392738L: '\x85', 4392739L: '$', 4392740L: '\xff', 4392741L: '\xff', 4392742L: '\xff'}}, 'disassembly': 'JNZ 0x43064b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_65(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488347664L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488347664L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_66(self):
''' Instruction JNZ 0x4007db '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196022L, 'RBP': 0L}, 'memory': {4196022L: '\x0f', 4196023L: '\x85', 4196024L: '\x1f', 4196025L: '\x01', 4196026L: '\x00', 4196027L: '\x00'}}, 'text': '\x0f\x85\x1f\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196028L, 'RBP': 0L}, 'memory': {4196022L: '\x0f', 4196023L: '\x85', 4196024L: '\x1f', 4196025L: '\x01', 4196026L: '\x00', 4196027L: '\x00'}}, 'disassembly': 'JNZ 0x4007db', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_67(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322501L, 'RBP': 140737488347630L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488347630L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_68(self):
''' Instruction JNZ 0x401340 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 0L, 'RSI': 1L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199077L, 'RBP': 4782912L}, 'memory': {4199077L: '\x0f', 4199078L: '\x85', 4199079L: '\x95', 4199080L: '\x00', 4199081L: '\x00', 4199082L: '\x00'}}, 'text': '\x0f\x85\x95\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 0L, 'RSI': 1L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199232L, 'RBP': 4782912L}, 'memory': {4199077L: '\x0f', 4199078L: '\x85', 4199079L: '\x95', 4199080L: '\x00', 4199081L: '\x00', 4199082L: '\x00'}}, 'disassembly': 'JNZ 0x401340', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_69(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488347906L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322530L, 'RBP': 140737488347906L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_7(self):
''' Instruction JNZ 0x404890 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350830L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'text': 'u\xeb', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350830L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'disassembly': 'JNZ 0x404890', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_70(self):
''' Instruction JNZ 0x4306f0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 116L, 'RSI': 140737354125663L, 'RDI': 140737354125651L, 'RAX': 140737354125660L, 'RSP': 140737488344192L, 'RDX': 4783006L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392704L: 'u', 4392705L: '\xee'}}, 'text': 'u\xee', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 116L, 'RSI': 140737354125663L, 'RDI': 140737354125651L, 'RAX': 140737354125660L, 'RSP': 140737488344192L, 'RDX': 4783006L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392704L: 'u', 4392705L: '\xee'}}, 'disassembly': 'JNZ 0x4306f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_71(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350473L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322496L, 'RBP': 140737488350473L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_72(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322501L, 'RBP': 140737488350013L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322530L, 'RBP': 140737488350013L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_73(self):
''' Instruction JNZ 0x400680 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346528L, 'RAX': 140737488347630L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'text': 'u\xf4', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346528L, 'RAX': 140737488347630L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'disassembly': 'JNZ 0x400680', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_74(self):
''' Instruction JNZ 0x4306f0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 109L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737354125674L, 'RSP': 140737488344192L, 'RDX': 4783028L, 'RIP': 4392704L, 'RBP': 7049504L}, 'memory': {4392704L: 'u', 4392705L: '\xee'}}, 'text': 'u\xee', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 109L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737354125674L, 'RSP': 140737488344192L, 'RDX': 4783028L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392704L: 'u', 4392705L: '\xee'}}, 'disassembly': 'JNZ 0x4306f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_75(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488347766L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488347766L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_76(self):
''' Instruction JNZ 0x404890 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350035L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'text': 'u\xeb', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350035L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'disassembly': 'JNZ 0x404890', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_77(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488349565L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322496L, 'RBP': 140737488349565L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_78(self):
''' Instruction JNZ 0x400680 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346728L, 'RAX': 140737488350181L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'text': 'u\xf4', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346728L, 'RAX': 140737488350181L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'disassembly': 'JNZ 0x400680', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_79(self):
''' Instruction JNZ 0x419ae9 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299484L, 'RBP': 0L}, 'memory': {4299484L: 'u', 4299485L: '\x0b'}}, 'text': 'u\x0b', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299497L, 'RBP': 0L}, 'memory': {4299484L: 'u', 4299485L: '\x0b'}}, 'disassembly': 'JNZ 0x419ae9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_8(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488350405L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488350405L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_80(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488349619L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488349619L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_81(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488350976L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488350976L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_82(self):
''' Instruction JNZ 0x421270 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329627L, 'RBP': 140737488345936L}, 'memory': {4329632L: '\x00', 4329627L: '\x0f', 4329628L: '\x85', 4329629L: '\xcf', 4329630L: '\x01', 4329631L: '\x00'}}, 'text': '\x0f\x85\xcf\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329633L, 'RBP': 140737488345936L}, 'memory': {4329632L: '\x00', 4329627L: '\x0f', 4329628L: '\x85', 4329629L: '\xcf', 4329630L: '\x01', 4329631L: '\x00'}}, 'disassembly': 'JNZ 0x421270', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_83(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322540L, 'RBP': 140737488347888L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322496L, 'RBP': 140737488347888L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_84(self):
''' Instruction JNZ 0x400ce2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4241440L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197572L, 'RBP': 4L}, 'memory': {4197572L: 'u', 4197573L: '\x1c'}}, 'text': 'u\x1c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4241440L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197574L, 'RBP': 4L}, 'memory': {4197572L: 'u', 4197573L: '\x1c'}}, 'disassembly': 'JNZ 0x400ce2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_85(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488347960L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488347960L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_86(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350976L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350976L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_87(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488349498L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322496L, 'RBP': 140737488349498L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_88(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322540L, 'RBP': 140737488350544L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322496L, 'RBP': 140737488350544L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_89(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488350196L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322496L, 'RBP': 140737488350196L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_9(self):
''' Instruction JNZ 0x404890 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350328L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'text': 'u\xeb', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350328L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212880L, 'RBP': 0L}, 'memory': {4212899L: 'u', 4212900L: '\xeb'}}, 'disassembly': 'JNZ 0x404890', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_90(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488349565L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488349565L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_91(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488349619L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488349619L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_92(self):
''' Instruction JNZ 0x41f4c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488350989L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'text': 'u\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322496L, 'RBP': 140737488350989L}, 'memory': {4322540L: 'u', 4322541L: '\xd2'}}, 'disassembly': 'JNZ 0x41f4c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_93(self):
''' Instruction JNZ 0x4041c0 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051320L, 'RSP': 140737488345712L, 'RDX': 0L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'text': 'u\xe7', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051320L, 'RSP': 140737488345712L, 'RDX': 0L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211160L: '\xe7', 4211159L: 'u'}}, 'disassembly': 'JNZ 0x4041c0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_94(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322501L, 'RBP': 140737488350989L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322530L, 'RBP': 140737488350989L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_95(self):
''' Instruction JNZ 0x415db8 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4283952L, 'RBP': 3L}, 'memory': {4283952L: 'u', 4283953L: '\x86'}}, 'text': 'u\x86', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4283832L, 'RBP': 3L}, 'memory': {4283952L: 'u', 4283953L: '\x86'}}, 'disassembly': 'JNZ 0x415db8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_96(self):
''' Instruction JNZ 0x400680 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346712L, 'RAX': 140737488350035L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'text': 'u\xf4', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346712L, 'RAX': 140737488350035L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {4195978L: 'u', 4195979L: '\xf4'}}, 'disassembly': 'JNZ 0x400680', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_97(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322501L, 'RBP': 140737488347630L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322530L, 'RBP': 140737488347630L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_98(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488350989L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488350989L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJNZ_99(self):
''' Instruction JNZ 0x41f4e2 '''
test = {'mnemonic': 'JNZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322501L, 'RBP': 140737488348069L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'text': 'u\x1b', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322530L, 'RBP': 140737488348069L}, 'memory': {4322501L: 'u', 4322502L: '\x1b'}}, 'disassembly': 'JNZ 0x41f4e2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_1(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1088L, 'RSI': 4294967292L, 'RDI': 4783056L, 'RAX': 4783046L, 'RSP': 140737488344256L, 'RDX': 6L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1088L, 'RSI': 4294967292L, 'RDI': 4783056L, 'RAX': 4783046L, 'RSP': 140737488344256L, 'RDX': 6L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_10(self):
''' Instruction JS 0x422d90 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'text': '\x0f\x88\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'disassembly': 'JS 0x422d90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_11(self):
''' Instruction JS 0x43087c '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345888L, 'RDX': 18446744073709551615L, 'RIP': 4393070L, 'RBP': 140737354125312L}, 'memory': {4393070L: 'x', 4393071L: '\x0c'}}, 'text': 'x\x0c', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345888L, 'RDX': 18446744073709551615L, 'RIP': 4393084L, 'RBP': 140737354125312L}, 'memory': {4393070L: 'x', 4393071L: '\x0c'}}, 'disassembly': 'JS 0x43087c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_12(self):
''' Instruction JS 0x400844 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 4783074L, 'RAX': 7L, 'RSP': 140737488346240L, 'RDX': 7065176L, 'RIP': 4196381L, 'RBP': 0L}, 'memory': {4196381L: 'x', 4196382L: '%'}}, 'text': 'x%', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 4783074L, 'RAX': 7L, 'RSP': 140737488346240L, 'RDX': 7065176L, 'RIP': 4196383L, 'RBP': 0L}, 'memory': {4196381L: 'x', 4196382L: '%'}}, 'disassembly': 'JS 0x400844', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_13(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294950912L, 'RDI': 4783040L, 'RAX': 4783034L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294950912L, 'RDI': 4783040L, 'RAX': 4783034L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_14(self):
''' Instruction JS 0x416875 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286624L, 'RBP': 4544L}, 'memory': {4286624L: 'x', 4286625L: '\xd3'}}, 'text': 'x\xd3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286626L, 'RBP': 4544L}, 'memory': {4286624L: 'x', 4286625L: '\xd3'}}, 'disassembly': 'JS 0x416875', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_15(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294967040L, 'RDI': 4783056L, 'RAX': 4783050L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294967040L, 'RDI': 4783056L, 'RAX': 4783050L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_16(self):
''' Instruction JS 0x422d90 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'text': '\x0f\x88\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'disassembly': 'JS 0x422d90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_17(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 57600L, 'RSI': 4294967168L, 'RDI': 4782912L, 'RAX': 4782904L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 57600L, 'RSI': 4294967168L, 'RDI': 4782912L, 'RAX': 4782904L, 'RSP': 140737488344256L, 'RDX': 8L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_18(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1089L, 'RSI': 4294963200L, 'RDI': 4783056L, 'RAX': 4783040L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1089L, 'RSI': 4294963200L, 'RDI': 4783056L, 'RAX': 4783040L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_19(self):
''' Instruction JS 0x4047f8 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346016L, 'RDX': 7042720L, 'RIP': 4212708L, 'RBP': 140737488346112L}, 'memory': {4212708L: 'x', 4212709L: '\x12'}}, 'text': 'x\x12', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346016L, 'RDX': 7042720L, 'RIP': 4212728L, 'RBP': 140737488346112L}, 'memory': {4212708L: 'x', 4212709L: '\x12'}}, 'disassembly': 'JS 0x4047f8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_2(self):
''' Instruction JS 0x422d90 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'text': '\x0f\x88\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'disassembly': 'JS 0x422d90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_20(self):
''' Instruction JS 0x422d90 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'text': '\x0f\x88\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'disassembly': 'JS 0x422d90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_21(self):
''' Instruction JS 0x422d90 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'text': '\x0f\x88\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'disassembly': 'JS 0x422d90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_22(self):
''' Instruction JS 0x471fd9 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343968L, 'RDX': 140737488343968L, 'RIP': 4661149L, 'RBP': 8192L}, 'memory': {4661149L: 'x', 4661150L: ':'}}, 'text': 'x:', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343968L, 'RDX': 140737488343968L, 'RIP': 4661151L, 'RBP': 8192L}, 'memory': {4661149L: 'x', 4661150L: ':'}}, 'disassembly': 'JS 0x471fd9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_3(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4350L, 'RSI': 4294967264L, 'RDI': 4783024L, 'RAX': 4783009L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4350L, 'RSI': 4294967264L, 'RDI': 4783024L, 'RAX': 4783009L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_4(self):
''' Instruction JS 0x422d90 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'text': '\x0f\x88\x89\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336897L: '\x0f', 4336898L: '\x88', 4336899L: '\x89', 4336900L: '\x00', 4336901L: '\x00', 4336902L: '\x00'}}, 'disassembly': 'JS 0x422d90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_5(self):
''' Instruction JS 0x42541d '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4294967292L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339878L, 'RBP': 140737488345936L}, 'memory': {4339878L: '\x0f', 4339879L: '\x88', 4339880L: 'q', 4339881L: '\x1b', 4339882L: '\x00', 4339883L: '\x00'}}, 'text': '\x0f\x88q\x1b\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4294967292L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339884L, 'RBP': 140737488345936L}, 'memory': {4339878L: '\x0f', 4339879L: '\x88', 4339880L: 'q', 4339881L: '\x1b', 4339882L: '\x00', 4339883L: '\x00'}}, 'disassembly': 'JS 0x42541d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_6(self):
''' Instruction JS 0x4007e8 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346240L, 'RDX': 5L, 'RIP': 4196005L, 'RBP': 0L}, 'memory': {4196005L: '\x0f', 4196006L: '\x88', 4196007L: '=', 4196008L: '\x01', 4196009L: '\x00', 4196010L: '\x00'}}, 'text': '\x0f\x88=\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346240L, 'RDX': 5L, 'RIP': 4196011L, 'RBP': 0L}, 'memory': {4196005L: '\x0f', 4196006L: '\x88', 4196007L: '=', 4196008L: '\x01', 4196009L: '\x00', 4196010L: '\x00'}}, 'disassembly': 'JS 0x4007e8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_7(self):
''' Instruction JS 0x4234c3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 57632L, 'RSI': 4294967288L, 'RDI': 4782912L, 'RAX': 4782901L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4336239L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'text': '\x0f\x88N\n\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 57632L, 'RSI': 4294967288L, 'RDI': 4782912L, 'RAX': 4782901L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4336245L, 'RBP': 140737488345936L}, 'memory': {4336239L: '\x0f', 4336240L: '\x88', 4336241L: 'N', 4336242L: '\n', 4336243L: '\x00', 4336244L: '\x00'}}, 'disassembly': 'JS 0x4234c3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_8(self):
''' Instruction JS 0x4238a3 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4294967292L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339679L, 'RBP': 140737488345936L}, 'memory': {4339680L: '\x88', 4339681L: '\xbe', 4339682L: '\x00', 4339683L: '\x00', 4339684L: '\x00', 4339679L: '\x0f'}}, 'text': '\x0f\x88\xbe\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4294967292L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339875L, 'RBP': 140737488345936L}, 'memory': {4339680L: '\x88', 4339681L: '\xbe', 4339682L: '\x00', 4339683L: '\x00', 4339684L: '\x00', 4339679L: '\x0f'}}, 'disassembly': 'JS 0x4238a3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJS_9(self):
''' Instruction JS 0x471fd9 '''
test = {'mnemonic': 'JS', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 9L, 'RSI': 4294967295L, 'RDI': 7049504L, 'RAX': 1L, 'RSP': 140737488343968L, 'RDX': 9L, 'RIP': 4661129L, 'RBP': 8192L}, 'memory': {4661129L: 'x', 4661130L: 'N'}}, 'text': 'xN', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 9L, 'RSI': 4294967295L, 'RDI': 7049504L, 'RAX': 1L, 'RSP': 140737488343968L, 'RDX': 9L, 'RIP': 4661131L, 'RBP': 8192L}, 'memory': {4661129L: 'x', 4661130L: 'N'}}, 'disassembly': 'JS 0x471fd9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_1(self):
''' Instruction JZ 0x415f7d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4095L, 'RSI': 62914623L, 'RDI': 4L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284051L, 'RBP': 9L}, 'memory': {4284051L: '\x0f', 4284052L: '\x84', 4284053L: '\xe4', 4284054L: '\x00', 4284055L: '\x00', 4284056L: '\x00'}}, 'text': '\x0f\x84\xe4\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4095L, 'RSI': 62914623L, 'RDI': 4L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284285L, 'RBP': 9L}, 'memory': {4284051L: '\x0f', 4284052L: '\x84', 4284053L: '\xe4', 4284054L: '\x00', 4284055L: '\x00', 4284056L: '\x00'}}, 'disassembly': 'JZ 0x415f7d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_10(self):
''' Instruction JZ 0x4012b5 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199235L, 'RBP': 4782912L}, 'memory': {4199235L: '\x0f', 4199236L: '\x84', 4199237L: 'l', 4199238L: '\xff', 4199239L: '\xff', 4199240L: '\xff'}}, 'text': '\x0f\x84l\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199093L, 'RBP': 4782912L}, 'memory': {4199235L: '\x0f', 4199236L: '\x84', 4199237L: 'l', 4199238L: '\xff', 4199239L: '\xff', 4199240L: '\xff'}}, 'disassembly': 'JZ 0x4012b5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_100(self):
''' Instruction JZ 0x415e40 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 194L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284031L, 'RBP': 9L}, 'memory': {4284032L: '\xbf', 4284031L: 't'}}, 'text': 't\xbf', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 194L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284033L, 'RBP': 9L}, 'memory': {4284032L: '\xbf', 4284031L: 't'}}, 'disassembly': 'JZ 0x415e40', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_101(self):
''' Instruction JZ 0x419558 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 5L, 'RIP': 4298055L, 'RBP': 0L}, 'memory': {4298056L: '\x0f', 4298055L: 't'}}, 'text': 't\x0f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 5L, 'RIP': 4298072L, 'RBP': 0L}, 'memory': {4298056L: '\x0f', 4298055L: 't'}}, 'disassembly': 'JZ 0x419558', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_11(self):
''' Instruction JZ 0x423460 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338646L, 'RBP': 140737488345936L}, 'memory': {4338646L: '\x0f', 4338647L: '\x84', 4338648L: '\x84', 4338649L: '\x00', 4338650L: '\x00', 4338651L: '\x00'}}, 'text': '\x0f\x84\x84\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338784L, 'RBP': 140737488345936L}, 'memory': {4338646L: '\x0f', 4338647L: '\x84', 4338648L: '\x84', 4338649L: '\x00', 4338650L: '\x00', 4338651L: '\x00'}}, 'disassembly': 'JZ 0x423460', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_12(self):
''' Instruction JZ 0x400af8 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4197062L, 'RBP': 80L}, 'memory': {4197062L: 't', 4197063L: '0'}}, 'text': 't0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4197112L, 'RBP': 80L}, 'memory': {4197062L: 't', 4197063L: '0'}}, 'disassembly': 'JZ 0x400af8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_13(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_14(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_15(self):
''' Instruction JZ 0x48e430 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 20L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4776820L, 'RBP': 4881624L}, 'memory': {4776820L: '\x0f', 4776821L: '\x84', 4776822L: '\xb6', 4776823L: '\x00', 4776824L: '\x00', 4776825L: '\x00'}}, 'text': '\x0f\x84\xb6\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 20L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4776826L, 'RBP': 4881624L}, 'memory': {4776820L: '\x0f', 4776821L: '\x84', 4776822L: '\xb6', 4776823L: '\x00', 4776824L: '\x00', 4776825L: '\x00'}}, 'disassembly': 'JZ 0x48e430', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_16(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_17(self):
''' Instruction JZ 0x402b32 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 18446744073709551615L, 'RIP': 4205280L, 'RBP': 7049280L}, 'memory': {4205280L: 't', 4205281L: 'P'}}, 'text': 'tP', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 18446744073709551615L, 'RIP': 4205362L, 'RBP': 7049280L}, 'memory': {4205280L: 't', 4205281L: 'P'}}, 'disassembly': 'JZ 0x402b32', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_18(self):
''' Instruction JZ 0x420910 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327572L, 'RBP': 140737488345936L}, 'memory': {4327572L: 't', 4327573L: 'z'}}, 'text': 'tz', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327696L, 'RBP': 140737488345936L}, 'memory': {4327572L: 't', 4327573L: 'z'}}, 'disassembly': 'JZ 0x420910', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_19(self):
''' Instruction JZ 0x43071b '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392638L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'text': 't[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392640L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'disassembly': 'JZ 0x43071b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_2(self):
''' Instruction JZ 0x41f4f8 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322467L, 'RBP': 140737488346472L}, 'memory': {4322467L: 't', 4322468L: 'S'}}, 'text': 'tS', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322469L, 'RBP': 140737488346472L}, 'memory': {4322467L: 't', 4322468L: 'S'}}, 'disassembly': 'JZ 0x41f4f8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_20(self):
''' Instruction JZ 0x44f928 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 0L, 'RDI': 4807352L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 1L, 'RIP': 4520209L, 'RBP': 140737488346112L}, 'memory': {4520209L: 't', 4520210L: '\x15'}}, 'text': 't\x15', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 0L, 'RDI': 4807352L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 1L, 'RIP': 4520211L, 'RBP': 140737488346112L}, 'memory': {4520209L: 't', 4520210L: '\x15'}}, 'disassembly': 'JZ 0x44f928', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_21(self):
''' Instruction JZ 0x43071b '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392638L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'text': 't[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392640L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'disassembly': 'JZ 0x43071b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_22(self):
''' Instruction JZ 0x40c390 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354125400L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244349L, 'RBP': 7049504L}, 'memory': {4244349L: 't', 4244350L: '\x11'}}, 'text': 't\x11', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354125400L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244351L, 'RBP': 7049504L}, 'memory': {4244349L: 't', 4244350L: '\x11'}}, 'disassembly': 'JZ 0x40c390', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_23(self):
''' Instruction JZ 0x4048b2 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 7059656L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212859L, 'RBP': 140737488346112L}, 'memory': {4212859L: 't', 4212860L: '5'}}, 'text': 't5', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 7059656L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212861L, 'RBP': 140737488346112L}, 'memory': {4212859L: 't', 4212860L: '5'}}, 'disassembly': 'JZ 0x4048b2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_24(self):
''' Instruction JZ 0x40c460 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244478L: 't', 4244479L: '`'}}, 'text': 't`', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244478L: 't', 4244479L: '`'}}, 'disassembly': 'JZ 0x40c460', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_25(self):
''' Instruction JZ 0x404963 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488349498L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'text': '\x0f\x84\xca\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488349498L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'disassembly': 'JZ 0x404963', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_26(self):
''' Instruction JZ 0x430750 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392501L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'text': '\x0f\x84\x15\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392507L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'disassembly': 'JZ 0x430750', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_27(self):
''' Instruction JZ 0x40c460 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244478L: 't', 4244479L: '`'}}, 'text': 't`', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244478L: 't', 4244479L: '`'}}, 'disassembly': 'JZ 0x40c460', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_28(self):
''' Instruction JZ 0x422cc9 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336826L, 'RBP': 140737488345936L}, 'memory': {4336826L: 't', 4336827L: '\r'}}, 'text': 't\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336841L, 'RBP': 140737488345936L}, 'memory': {4336826L: 't', 4336827L: '\r'}}, 'disassembly': 'JZ 0x422cc9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_29(self):
''' Instruction JZ 0x40c460 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125885L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244520L, 'RBP': 7049504L}, 'memory': {4244520L: 't', 4244521L: '6'}}, 'text': 't6', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125885L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244522L, 'RBP': 7049504L}, 'memory': {4244520L: 't', 4244521L: '6'}}, 'disassembly': 'JZ 0x40c460', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_3(self):
''' Instruction JZ 0x407454 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223807L, 'RBP': 7051232L}, 'memory': {4223808L: '\x84', 4223809L: '\x0f', 4223810L: '\x01', 4223811L: '\x00', 4223812L: '\x00', 4223807L: '\x0f'}}, 'text': '\x0f\x84\x0f\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4224084L, 'RBP': 7051232L}, 'memory': {4223808L: '\x84', 4223809L: '\x0f', 4223810L: '\x01', 4223811L: '\x00', 4223812L: '\x00', 4223807L: '\x0f'}}, 'disassembly': 'JZ 0x407454', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_30(self):
''' Instruction JZ 0x42543c '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4782909L, 'RIP': 4339924L, 'RBP': 140737488345936L}, 'memory': {4339924L: '\x0f', 4339925L: '\x84', 4339926L: 'b', 4339927L: '\x1b', 4339928L: '\x00', 4339929L: '\x00'}}, 'text': '\x0f\x84b\x1b\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4782909L, 'RIP': 4346940L, 'RBP': 140737488345936L}, 'memory': {4339924L: '\x0f', 4339925L: '\x84', 4339926L: 'b', 4339927L: '\x1b', 4339928L: '\x00', 4339929L: '\x00'}}, 'disassembly': 'JZ 0x42543c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_31(self):
''' Instruction JZ 0x40629b '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 1617L, 'RIP': 4222941L, 'RBP': 7051232L}, 'memory': {4222944L: '\xf2', 4222945L: '\xff', 4222946L: '\xff', 4222941L: '\x0f', 4222942L: '\x84', 4222943L: '\xb8'}}, 'text': '\x0f\x84\xb8\xf2\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 1617L, 'RIP': 4219547L, 'RBP': 7051232L}, 'memory': {4222944L: '\xf2', 4222945L: '\xff', 4222946L: '\xff', 4222941L: '\x0f', 4222942L: '\x84', 4222943L: '\xb8'}}, 'disassembly': 'JZ 0x40629b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_32(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_33(self):
''' Instruction JZ 0x43071b '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392638L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'text': 't[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392640L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'disassembly': 'JZ 0x43071b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_34(self):
''' Instruction JZ 0x40b1f6 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239852L, 'RBP': 6L}, 'memory': {4239852L: 't', 4239853L: '\x08'}}, 'text': 't\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239854L, 'RBP': 6L}, 'memory': {4239852L: 't', 4239853L: '\x08'}}, 'disassembly': 'JZ 0x40b1f6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_35(self):
''' Instruction JZ 0x430750 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392501L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'text': '\x0f\x84\x15\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392507L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'disassembly': 'JZ 0x430750', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_36(self):
''' Instruction JZ 0x42120a '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329981L, 'RBP': 140737488345936L}, 'memory': {4329981L: 't', 4329982L: '\x0b'}}, 'text': 't\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329994L, 'RBP': 140737488345936L}, 'memory': {4329981L: 't', 4329982L: '\x0b'}}, 'disassembly': 'JZ 0x42120a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_37(self):
''' Instruction JZ 0x400d3d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197662L, 'RBP': 4L}, 'memory': {4197662L: 't', 4197663L: '\x1d'}}, 'text': 't\x1d', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197693L, 'RBP': 4L}, 'memory': {4197662L: 't', 4197663L: '\x1d'}}, 'disassembly': 'JZ 0x400d3d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_38(self):
''' Instruction JZ 0x422a43 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336181L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4336195L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'disassembly': 'JZ 0x422a43', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_39(self):
''' Instruction JZ 0x4363ce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4416455L, 'RBP': 140737488347312L}, 'memory': {4416456L: '\x05', 4416455L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4416462L, 'RBP': 140737488347312L}, 'memory': {4416456L: '\x05', 4416455L: 't'}}, 'disassembly': 'JZ 0x4363ce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_4(self):
''' Instruction JZ 0x43071b '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125685L, 'RAX': 3723L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392638L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'text': 't[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125685L, 'RAX': 3723L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392640L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'disassembly': 'JZ 0x43071b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_40(self):
''' Instruction JZ 0x430750 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392501L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'text': '\x0f\x84\x15\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392507L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'disassembly': 'JZ 0x430750', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_41(self):
''' Instruction JZ 0x4161c4 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4284819L, 'RBP': 4L}, 'memory': {4284819L: 't', 4284820L: '/'}}, 'text': 't/', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4284868L, 'RBP': 4L}, 'memory': {4284819L: 't', 4284820L: '/'}}, 'disassembly': 'JZ 0x4161c4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_42(self):
''' Instruction JZ 0x43072d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392480L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'text': '\x0f\x84\x07\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392486L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'disassembly': 'JZ 0x43072d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_43(self):
''' Instruction JZ 0x404963 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350544L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'text': '\x0f\x84\xca\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350544L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'disassembly': 'JZ 0x404963', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_44(self):
''' Instruction JZ 0x416268 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285344L, 'RBP': 32768L}, 'memory': {4285344L: '\x0f', 4285345L: '\x84', 4285346L: '\xc2', 4285347L: '\xfe', 4285348L: '\xff', 4285349L: '\xff'}}, 'text': '\x0f\x84\xc2\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285350L, 'RBP': 32768L}, 'memory': {4285344L: '\x0f', 4285345L: '\x84', 4285346L: '\xc2', 4285347L: '\xfe', 4285348L: '\xff', 4285349L: '\xff'}}, 'disassembly': 'JZ 0x416268', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_45(self):
''' Instruction JZ 0x408c73 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 33L, 'RSP': 140737488346032L, 'RDX': 7051232L, 'RIP': 4230226L, 'RBP': 7051232L}, 'memory': {4230226L: 't', 4230227L: '\x1f'}}, 'text': 't\x1f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 33L, 'RSP': 140737488346032L, 'RDX': 7051232L, 'RIP': 4230259L, 'RBP': 7051232L}, 'memory': {4230226L: 't', 4230227L: '\x1f'}}, 'disassembly': 'JZ 0x408c73', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_46(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_47(self):
''' Instruction JZ 0x44f909 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4807364L, 'RAX': 7074368L, 'RSP': 140737488346080L, 'RDX': 0L, 'RIP': 4520179L, 'RBP': 140737488346112L}, 'memory': {4520179L: 't', 4520180L: '\x14'}}, 'text': 't\x14', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4807364L, 'RAX': 7074368L, 'RSP': 140737488346080L, 'RDX': 0L, 'RIP': 4520181L, 'RBP': 140737488346112L}, 'memory': {4520179L: 't', 4520180L: '\x14'}}, 'disassembly': 'JZ 0x44f909', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_48(self):
''' Instruction JZ 0x41ee11 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320722L, 'RBP': 4792416L}, 'memory': {4320722L: 't', 4320723L: '='}}, 'text': 't=', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320724L, 'RBP': 4792416L}, 'memory': {4320722L: 't', 4320723L: '='}}, 'disassembly': 'JZ 0x41ee11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_49(self):
''' Instruction JZ 0x40c460 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244478L: 't', 4244479L: '`'}}, 'text': 't`', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244480L, 'RBP': 7049504L}, 'memory': {4244478L: 't', 4244479L: '`'}}, 'disassembly': 'JZ 0x40c460', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_5(self):
''' Instruction JZ 0x415f90 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 2L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284060L, 'RBP': 9L}, 'memory': {4284064L: '\x00', 4284065L: '\x00', 4284060L: '\x0f', 4284061L: '\x84', 4284062L: '\xee', 4284063L: '\x00'}}, 'text': '\x0f\x84\xee\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 2L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284066L, 'RBP': 9L}, 'memory': {4284064L: '\x00', 4284065L: '\x00', 4284060L: '\x0f', 4284061L: '\x84', 4284062L: '\xee', 4284063L: '\x00'}}, 'disassembly': 'JZ 0x415f90', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_50(self):
''' Instruction JZ 0x422e8c '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337129L, 'RBP': 140737488345936L}, 'memory': {4337129L: '\x0f', 4337130L: '\x84', 4337131L: '\x9d', 4337132L: '\x00', 4337133L: '\x00', 4337134L: '\x00'}}, 'text': '\x0f\x84\x9d\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337292L, 'RBP': 140737488345936L}, 'memory': {4337129L: '\x0f', 4337130L: '\x84', 4337131L: '\x9d', 4337132L: '\x00', 4337133L: '\x00', 4337134L: '\x00'}}, 'disassembly': 'JZ 0x422e8c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_51(self):
''' Instruction JZ 0x404963 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350490L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'text': '\x0f\x84\xca\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350490L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'disassembly': 'JZ 0x404963', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_52(self):
''' Instruction JZ 0x430750 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392501L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'text': '\x0f\x84\x15\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392507L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'disassembly': 'JZ 0x430750', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_53(self):
''' Instruction JZ 0x422cc9 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336826L, 'RBP': 140737488345936L}, 'memory': {4336826L: 't', 4336827L: '\r'}}, 'text': 't\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336841L, 'RBP': 140737488345936L}, 'memory': {4336826L: 't', 4336827L: '\r'}}, 'disassembly': 'JZ 0x422cc9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_54(self):
''' Instruction JZ 0x40d1e6 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294950912L, 'RDI': 4783040L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 1024L, 'RIP': 4248068L, 'RBP': 140737488345936L}, 'memory': {4248068L: 't', 4248069L: '\xe0'}}, 'text': 't\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294950912L, 'RDI': 4783040L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 1024L, 'RIP': 4248070L, 'RBP': 140737488345936L}, 'memory': {4248068L: 't', 4248069L: '\xe0'}}, 'disassembly': 'JZ 0x40d1e6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_55(self):
''' Instruction JZ 0x402bfe '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205545L, 'RBP': 0L}, 'memory': {4205545L: 't', 4205546L: '\x13'}}, 'text': 't\x13', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205566L, 'RBP': 0L}, 'memory': {4205545L: 't', 4205546L: '\x13'}}, 'disassembly': 'JZ 0x402bfe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_56(self):
''' Instruction JZ 0x4233cf '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336387L, 'RBP': 140737488345936L}, 'memory': {4336387L: '\x0f', 4336388L: '\x84', 4336389L: '\xc6', 4336390L: '\x08', 4336391L: '\x00', 4336392L: '\x00'}}, 'text': '\x0f\x84\xc6\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338639L, 'RBP': 140737488345936L}, 'memory': {4336387L: '\x0f', 4336388L: '\x84', 4336389L: '\xc6', 4336390L: '\x08', 4336391L: '\x00', 4336392L: '\x00'}}, 'disassembly': 'JZ 0x4233cf', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_57(self):
''' Instruction JZ 0x400eb0 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 4L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197936L, 'RBP': 7049240L}, 'memory': {4197936L: 't', 4197937L: '~'}}, 'text': 't~', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 4L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4198064L, 'RBP': 7049240L}, 'memory': {4197936L: 't', 4197937L: '~'}}, 'disassembly': 'JZ 0x400eb0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_58(self):
''' Instruction JZ 0x43072d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392480L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'text': '\x0f\x84\x07\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392486L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'disassembly': 'JZ 0x43072d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_59(self):
''' Instruction JZ 0x404963 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350405L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'text': '\x0f\x84\xca\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350405L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'disassembly': 'JZ 0x404963', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_6(self):
''' Instruction JZ 0x43072d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392480L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'text': '\x0f\x84\x07\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392486L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'disassembly': 'JZ 0x43072d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_60(self):
''' Instruction JZ 0x404963 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488351129L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'text': '\x0f\x84\xca\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488351129L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'disassembly': 'JZ 0x404963', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_61(self):
''' Instruction JZ 0x419b9d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299669L, 'RBP': 140737488346472L}, 'memory': {4299669L: 't', 4299670L: '\x06'}}, 'text': 't\x06', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299677L, 'RBP': 140737488346472L}, 'memory': {4299669L: 't', 4299670L: '\x06'}}, 'disassembly': 'JZ 0x419b9d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_62(self):
''' Instruction JZ 0x42120a '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329981L, 'RBP': 140737488345936L}, 'memory': {4329981L: 't', 4329982L: '\x0b'}}, 'text': 't\x0b', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 7059408L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329994L, 'RBP': 140737488345936L}, 'memory': {4329981L: 't', 4329982L: '\x0b'}}, 'disassembly': 'JZ 0x42120a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_63(self):
''' Instruction JZ 0x415e40 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283794L, 'RBP': 188L}, 'memory': {4283794L: '\x0f', 4283795L: '\x84', 4283796L: '\xa8', 4283797L: '\x00', 4283798L: '\x00', 4283799L: '\x00'}}, 'text': '\x0f\x84\xa8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283800L, 'RBP': 188L}, 'memory': {4283794L: '\x0f', 4283795L: '\x84', 4283796L: '\xa8', 4283797L: '\x00', 4283798L: '\x00', 4283799L: '\x00'}}, 'disassembly': 'JZ 0x415e40', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_64(self):
''' Instruction JZ 0x416875 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 0L, 'RIP': 4286551L, 'RBP': 3648L}, 'memory': {4286552L: '\x1c', 4286551L: 't'}}, 'text': 't\x1c', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 3648L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 0L, 'RIP': 4286553L, 'RBP': 3648L}, 'memory': {4286552L: '\x1c', 4286551L: 't'}}, 'disassembly': 'JZ 0x416875', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_65(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_66(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_67(self):
''' Instruction JZ 0x4012b5 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199235L, 'RBP': 4782912L}, 'memory': {4199235L: '\x0f', 4199236L: '\x84', 4199237L: 'l', 4199238L: '\xff', 4199239L: '\xff', 4199240L: '\xff'}}, 'text': '\x0f\x84l\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4199093L, 'RBP': 4782912L}, 'memory': {4199235L: '\x0f', 4199236L: '\x84', 4199237L: 'l', 4199238L: '\xff', 4199239L: '\xff', 4199240L: '\xff'}}, 'disassembly': 'JZ 0x4012b5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_68(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_69(self):
''' Instruction JZ 0x422bf0 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336585L, 'RBP': 140737488345936L}, 'memory': {4336585L: 't', 4336586L: '%'}}, 'text': 't%', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336624L, 'RBP': 140737488345936L}, 'memory': {4336585L: 't', 4336586L: '%'}}, 'disassembly': 'JZ 0x422bf0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_7(self):
''' Instruction JZ 0x402d80 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7049636L, 'RIP': 4206090L, 'RBP': 1L}, 'memory': {4206090L: '\x0f', 4206091L: '\x84', 4206092L: 'p', 4206093L: '\xff', 4206094L: '\xff', 4206095L: '\xff'}}, 'text': '\x0f\x84p\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7049636L, 'RIP': 4206096L, 'RBP': 1L}, 'memory': {4206090L: '\x0f', 4206091L: '\x84', 4206092L: 'p', 4206093L: '\xff', 4206094L: '\xff', 4206095L: '\xff'}}, 'disassembly': 'JZ 0x402d80', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_70(self):
''' Instruction JZ 0x422a43 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'RAX': 2147483634L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4336181L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'RAX': 2147483634L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4336195L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'disassembly': 'JZ 0x422a43', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_71(self):
''' Instruction JZ 0x40c390 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354126002L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244349L, 'RBP': 7049504L}, 'memory': {4244349L: 't', 4244350L: '\x11'}}, 'text': 't\x11', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354126002L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244351L, 'RBP': 7049504L}, 'memory': {4244349L: 't', 4244350L: '\x11'}}, 'disassembly': 'JZ 0x40c390', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_72(self):
''' Instruction JZ 0x422a43 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4336181L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4336195L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'disassembly': 'JZ 0x422a43', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_73(self):
''' Instruction JZ 0x42113e '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 1L, 'RDI': 4783008L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329776L, 'RBP': 140737488345936L}, 'memory': {4329776L: 't', 4329777L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 1L, 'RDI': 4783008L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329790L, 'RBP': 140737488345936L}, 'memory': {4329776L: 't', 4329777L: '\x0c'}}, 'disassembly': 'JZ 0x42113e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_74(self):
''' Instruction JZ 0x421081 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 43L, 'RSI': 4783016L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4330035L, 'RBP': 140737488345936L}, 'memory': {4330035L: '\x0f', 4330036L: '\x84', 4330037L: 'H', 4330038L: '\xfe', 4330039L: '\xff', 4330040L: '\xff'}}, 'text': '\x0f\x84H\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 43L, 'RSI': 4783016L, 'RDI': 7049504L, 'RAX': 4294967295L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329601L, 'RBP': 140737488345936L}, 'memory': {4330035L: '\x0f', 4330036L: '\x84', 4330037L: 'H', 4330038L: '\xfe', 4330039L: '\xff', 4330040L: '\xff'}}, 'disassembly': 'JZ 0x421081', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_75(self):
''' Instruction JZ 0x41f46e '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322460L, 'RBP': 140737488346472L}, 'memory': {4322460L: 't', 4322461L: '\xd0'}}, 'text': 't\xd0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322462L, 'RBP': 140737488346472L}, 'memory': {4322460L: 't', 4322461L: '\xd0'}}, 'disassembly': 'JZ 0x41f46e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_76(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_77(self):
''' Instruction JZ 0x422d70 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4336957L, 'RBP': 140737488345936L}, 'memory': {4336957L: 't', 4336958L: '1'}}, 'text': 't1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4336957L: 't', 4336958L: '1'}}, 'disassembly': 'JZ 0x422d70', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_78(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_79(self):
''' Instruction JZ 0x43637c '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 16L, 'RDI': 140737488347376L, 'RAX': 140737488347355L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4416434L, 'RBP': 140737488347312L}, 'memory': {4416434L: 't', 4416435L: '\xc8'}}, 'text': 't\xc8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 16L, 'RDI': 140737488347376L, 'RAX': 140737488347355L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4416436L, 'RBP': 140737488347312L}, 'memory': {4416434L: 't', 4416435L: '\xc8'}}, 'disassembly': 'JZ 0x43637c', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_8(self):
''' Instruction JZ 0x4233cf '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4336387L, 'RBP': 140737488345936L}, 'memory': {4336387L: '\x0f', 4336388L: '\x84', 4336389L: '\xc6', 4336390L: '\x08', 4336391L: '\x00', 4336392L: '\x00'}}, 'text': '\x0f\x84\xc6\x08\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338639L, 'RBP': 140737488345936L}, 'memory': {4336387L: '\x0f', 4336388L: '\x84', 4336389L: '\xc6', 4336390L: '\x08', 4336391L: '\x00', 4336392L: '\x00'}}, 'disassembly': 'JZ 0x4233cf', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_80(self):
''' Instruction JZ 0x422c5e '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336719L, 'RBP': 140737488345936L}, 'memory': {4336720L: '\r', 4336719L: 't'}}, 'text': 't\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336734L, 'RBP': 140737488345936L}, 'memory': {4336720L: '\r', 4336719L: 't'}}, 'disassembly': 'JZ 0x422c5e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_81(self):
''' Instruction JZ 0x43071b '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392638L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'text': 't[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392640L, 'RBP': 7049504L}, 'memory': {4392638L: 't', 4392639L: '['}}, 'disassembly': 'JZ 0x43071b', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_82(self):
''' Instruction JZ 0x430750 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392501L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'text': '\x0f\x84\x15\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 7049504L, 'RAX': 2048L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392507L, 'RBP': 7049504L}, 'memory': {4392501L: '\x0f', 4392502L: '\x84', 4392503L: '\x15', 4392504L: '\x01', 4392505L: '\x00', 4392506L: '\x00'}}, 'disassembly': 'JZ 0x430750', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_83(self):
''' Instruction JZ 0x4192d0 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347264L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297003L, 'RBP': 0L}, 'memory': {4297003L: '\x0f', 4297004L: '\x84', 4297005L: '\x9f', 4297006L: '\x01', 4297007L: '\x00', 4297008L: '\x00'}}, 'text': '\x0f\x84\x9f\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347264L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297009L, 'RBP': 0L}, 'memory': {4297003L: '\x0f', 4297004L: '\x84', 4297005L: '\x9f', 4297006L: '\x01', 4297007L: '\x00', 4297008L: '\x00'}}, 'disassembly': 'JZ 0x4192d0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_84(self):
''' Instruction JZ 0x422a43 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4336181L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125681L, 'RDI': 140737354125680L, 'RAX': 2147483630L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4336195L, 'RBP': 140737488345936L}, 'memory': {4336181L: 't', 4336182L: '\x0c'}}, 'disassembly': 'JZ 0x422a43', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_85(self):
''' Instruction JZ 0x423460 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338646L, 'RBP': 140737488345936L}, 'memory': {4338646L: '\x0f', 4338647L: '\x84', 4338648L: '\x84', 4338649L: '\x00', 4338650L: '\x00', 4338651L: '\x00'}}, 'text': '\x0f\x84\x84\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4336380L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4338784L, 'RBP': 140737488345936L}, 'memory': {4338646L: '\x0f', 4338647L: '\x84', 4338648L: '\x84', 4338649L: '\x00', 4338650L: '\x00', 4338651L: '\x00'}}, 'disassembly': 'JZ 0x423460', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_86(self):
''' Instruction JZ 0x42123f '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330010L, 'RBP': 140737488345936L}, 'memory': {4330010L: 't', 4330011L: '#'}}, 'text': 't#', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330047L, 'RBP': 140737488345936L}, 'memory': {4330010L: 't', 4330011L: '#'}}, 'disassembly': 'JZ 0x42123f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_87(self):
''' Instruction JZ 0x422c5e '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336719L, 'RBP': 140737488345936L}, 'memory': {4336720L: '\r', 4336719L: 't'}}, 'text': 't\r', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336734L, 'RBP': 140737488345936L}, 'memory': {4336720L: '\r', 4336719L: 't'}}, 'disassembly': 'JZ 0x422c5e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_88(self):
''' Instruction JZ 0x404963 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350035L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212883L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'text': '\x0f\x84\xca\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350035L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212889L, 'RBP': 0L}, 'memory': {4212883L: '\x0f', 4212884L: '\x84', 4212885L: '\xca', 4212886L: '\x00', 4212887L: '\x00', 4212888L: '\x00'}}, 'disassembly': 'JZ 0x404963', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_89(self):
''' Instruction JZ 0x43072d '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392480L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'text': '\x0f\x84\x07\x01\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392486L, 'RBP': 7049504L}, 'memory': {4392480L: '\x0f', 4392481L: '\x84', 4392482L: '\x07', 4392483L: '\x01', 4392484L: '\x00', 4392485L: '\x00'}}, 'disassembly': 'JZ 0x43072d', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_9(self):
''' Instruction JZ 0x41eadf '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346224L, 'RDX': 18446744072518369280L, 'RIP': 4319944L, 'RBP': 0L}, 'memory': {4319944L: 't', 4319945L: '\x15'}}, 'text': 't\x15', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346224L, 'RDX': 18446744072518369280L, 'RIP': 4319967L, 'RBP': 0L}, 'memory': {4319944L: 't', 4319945L: '\x15'}}, 'disassembly': 'JZ 0x41eadf', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_90(self):
''' Instruction JZ 0x42113e '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 1L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329776L, 'RBP': 140737488345936L}, 'memory': {4329776L: 't', 4329777L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 1L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329790L, 'RBP': 140737488345936L}, 'memory': {4329776L: 't', 4329777L: '\x0c'}}, 'disassembly': 'JZ 0x42113e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_91(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_92(self):
''' Instruction JZ 0x40c37a '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782978L, 'RDI': 140737354125396L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244332L, 'RBP': 7049504L}, 'memory': {4244332L: 't', 4244333L: '\x0c'}}, 'text': 't\x0c', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782978L, 'RDI': 140737354125396L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244334L, 'RBP': 7049504L}, 'memory': {4244332L: 't', 4244333L: '\x0c'}}, 'disassembly': 'JZ 0x40c37a', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_93(self):
''' Instruction JZ 0x415bce '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283335L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283336L: '\x05', 4283335L: 't'}}, 'disassembly': 'JZ 0x415bce', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_94(self):
''' Instruction JZ 0x431ae8 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 4294967295L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488345968L, 'RDX': 140737354126011L, 'RIP': 4397625L, 'RBP': 4294967295L}, 'memory': {4397625L: '\x0f', 4397626L: '\x84', 4397627L: '\xa9', 4397628L: '\x00', 4397629L: '\x00', 4397630L: '\x00'}}, 'text': '\x0f\x84\xa9\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 4294967295L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488345968L, 'RDX': 140737354126011L, 'RIP': 4397800L, 'RBP': 4294967295L}, 'memory': {4397625L: '\x0f', 4397626L: '\x84', 4397627L: '\xa9', 4397628L: '\x00', 4397629L: '\x00', 4397630L: '\x00'}}, 'disassembly': 'JZ 0x431ae8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_95(self):
''' Instruction JZ 0x4022b2 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343920L, 'RDX': 140737354129408L, 'RIP': 4203179L, 'RBP': 140737354125312L}, 'memory': {4203179L: 't', 4203180L: '\x05'}}, 'text': 't\x05', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343920L, 'RDX': 140737354129408L, 'RIP': 4203186L, 'RBP': 140737354125312L}, 'memory': {4203179L: 't', 4203180L: '\x05'}}, 'disassembly': 'JZ 0x4022b2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_96(self):
''' Instruction JZ 0x41f46e '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322460L, 'RBP': 140737488346472L}, 'memory': {4322460L: 't', 4322461L: '\xd0'}}, 'text': 't\xd0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322462L, 'RBP': 140737488346472L}, 'memory': {4322460L: 't', 4322461L: '\xd0'}}, 'disassembly': 'JZ 0x41f46e', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_97(self):
''' Instruction JZ 0x409130 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231362L, 'RBP': 140737488345936L}, 'memory': {4231362L: 't', 4231363L: 'l'}}, 'text': 'tl', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231472L, 'RBP': 140737488345936L}, 'memory': {4231362L: 't', 4231363L: 'l'}}, 'disassembly': 'JZ 0x409130', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_98(self):
''' Instruction JZ 0x430d70 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7049504L, 'RSP': 140737488346096L, 'RDX': 7049636L, 'RIP': 4394316L, 'RBP': 1L}, 'memory': {4394316L: 't', 4394317L: '"'}}, 'text': 't"', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7049504L, 'RSP': 140737488346096L, 'RDX': 7049636L, 'RIP': 4394318L, 'RBP': 1L}, 'memory': {4394316L: 't', 4394317L: '"'}}, 'disassembly': 'JZ 0x430d70', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testJZ_99(self):
''' Instruction JZ 0x40c3f0 '''
test = {'mnemonic': 'JZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244421L, 'RBP': 7049504L}, 'memory': {4244421L: 't', 4244422L: ')'}}, 'text': 't)', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244464L, 'RBP': 7049504L}, 'memory': {4244421L: 't', 4244422L: ')'}}, 'disassembly': 'JZ 0x40c3f0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEAVE_1(self):
''' Instruction LEAVE '''
test = {'mnemonic': 'LEAVE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4807364L, 'RAX': 7074368L, 'RSP': 140737488346112L, 'RDX': 1L, 'RIP': 4520289L, 'RBP': 140737488346112L}, 'memory': {140737488346112L: 'h', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'z', 4520289L: '\xc9', 140737488346103L: '\x00', 140737488346104L: '\x07', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': '\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4807364L, 'RAX': 7074368L, 'RSP': 140737488346120L, 'RDX': 1L, 'RIP': 4520290L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: 'h', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'z', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346465L: '\x00', 140737488346463L: '\x00', 140737488346464L: '\x04', 4520289L: '\xc9', 140737488346466L: '\x00', 140737488346467L: '\x00', 140737488346468L: '\x00', 140737488346469L: '\x00', 140737488346470L: '\x00', 140737488346471L: '\x00', 140737488346472L: '\xb0', 140737488346473L: '\xe0', 140737488346474L: '\xff', 140737488346475L: '\xff', 140737488346476L: '\xff', 140737488346477L: '\x7f', 140737488346478L: '\x00', 140737488346479L: '\x00', 140737488346480L: '\xf6', 140737488346103L: '\x00', 140737488346104L: '\x07', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'LEAVE', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEAVE_2(self):
''' Instruction LEAVE '''
test = {'mnemonic': 'LEAVE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 32L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330070L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 4330070L: '\xc9', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488344263L: '\x00', 140737488344264L: '\xca', 140737488345942L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 32L, 'RSP': 140737488345944L, 'RDX': 7059408L, 'RIP': 4330071L, 'RBP': 140737488346224L}, 'memory': {4330070L: '\xc9', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '(', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: 'g', 140737488346218L: '5', 140737488346219L: 'i', 140737488346220L: ':', 140737488346221L: 'J', 140737488346222L: 's', 140737488346223L: '\x89', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca'}}, 'disassembly': 'LEAVE', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEAVE_3(self):
''' Instruction LEAVE '''
test = {'mnemonic': 'LEAVE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 18L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330070L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 4330070L: '\xc9', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488344263L: '\x00', 140737488344264L: '8', 140737488345942L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 18L, 'RSP': 140737488345944L, 'RDX': 7059408L, 'RIP': 4330071L, 'RBP': 140737488346224L}, 'memory': {4330070L: '\xc9', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\x18', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: 'g', 140737488346218L: '5', 140737488346219L: 'i', 140737488346220L: ':', 140737488346221L: 'J', 140737488346222L: 's', 140737488346223L: '\x89', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '8'}}, 'disassembly': 'LEAVE', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEAVE_4(self):
''' Instruction LEAVE '''
test = {'mnemonic': 'LEAVE', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 17L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330070L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 4330070L: '\xc9', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488344263L: '\x00', 140737488344264L: '\xa1', 140737488345942L: '\x00', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 17L, 'RSP': 140737488345944L, 'RDX': 7059408L, 'RIP': 4330071L, 'RBP': 140737488346224L}, 'memory': {4330070L: '\xc9', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\x10', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: 'g', 140737488346218L: '5', 140737488346219L: 'i', 140737488346220L: ':', 140737488346221L: 'J', 140737488346222L: 's', 140737488346223L: '\x89', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1'}}, 'disassembly': 'LEAVE', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_1(self):
''' Instruction LEA RSI, [RSI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244512L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'text': 'H\x8dv ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125409L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'disassembly': 'LEA RSI, [RSI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_10(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 16L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792432L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_100(self):
''' Instruction LEA RAX, [RIP+0x146b] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4716400L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4400350L, 'RBP': 3L}, 'memory': {4400352L: '\x05', 4400353L: 'k', 4400354L: '\x14', 4400355L: '\x00', 4400356L: '\x00', 4400350L: 'H', 4400351L: '\x8d'}}, 'text': 'H\x8d\x05k\x14\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4405584L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4400357L, 'RBP': 3L}, 'memory': {4400352L: '\x05', 4400353L: 'k', 4400354L: '\x14', 4400355L: '\x00', 4400356L: '\x00', 4400350L: 'H', 4400351L: '\x8d'}}, 'disassembly': 'LEA RAX, [RIP+0x146b]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_101(self):
''' Instruction LEA R8, [RDI+R8] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'R8': 4L, 'RAX': 140737354125329L, 'RSP': 140737488344192L, 'RDX': 4782909L, 'RIP': 4392714L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'text': 'N\x8d\x04\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 83L, 'RSI': 140737354125329L, 'RDI': 140737354125325L, 'R8': 140737354125329L, 'RAX': 140737354125329L, 'RSP': 140737488344192L, 'RDX': 4782909L, 'RIP': 4392718L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'disassembly': 'LEA R8, [RDI+R8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_11(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051976L, 'RSP': 140737488345712L, 'RDX': 656L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051992L, 'RSP': 140737488345712L, 'RDX': 656L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_12(self):
''' Instruction LEA RSI, [RDI+R8+0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'R8': 3L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 4783042L, 'RIP': 4392673L, 'RBP': 7049504L}, 'memory': {4392673L: 'J', 4392674L: '\x8d', 4392675L: 't', 4392676L: '\x07', 4392677L: '\x01'}}, 'text': 'J\x8dt\x07\x01', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 1088L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 4783042L, 'RIP': 4392678L, 'RBP': 7049504L}, 'memory': {4392673L: 'J', 4392674L: '\x8d', 4392675L: 't', 4392676L: '\x07', 4392677L: '\x01'}}, 'disassembly': 'LEA RSI, [RDI+R8+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_13(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 408L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792824L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_14(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 8L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792424L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_15(self):
''' Instruction LEA RSI, [RSI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244512L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'text': 'H\x8dv ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125488L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'disassembly': 'LEA RSI, [RSI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_16(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052632L, 'RSP': 140737488345712L, 'RDX': 1312L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052648L, 'RSP': 140737488345712L, 'RDX': 1312L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_17(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051928L, 'RSP': 140737488345712L, 'RDX': 608L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051944L, 'RSP': 140737488345712L, 'RDX': 608L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_18(self):
''' Instruction LEA RDI, [RDI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035168L, 'RDI': 7071792L, 'RAX': 7054432L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245668L, 'RBP': 80L}, 'memory': {4245668L: 'H', 4245669L: '\x8d', 4245670L: '\x7f', 4245671L: ' '}}, 'text': 'H\x8d\x7f ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035168L, 'RDI': 7071824L, 'RAX': 7054432L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245672L, 'RBP': 80L}, 'memory': {4245668L: 'H', 4245669L: '\x8d', 4245670L: '\x7f', 4245671L: ' '}}, 'disassembly': 'LEA RDI, [RDI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_19(self):
''' Instruction LEA RBP, [RAX+0xfff] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661192L, 'RBP': 8192L}, 'memory': {4661192L: 'H', 4661193L: '\x8d', 4661194L: '\xa8', 4661195L: '\xff', 4661196L: '\x0f', 4661197L: '\x00', 4661198L: '\x00'}}, 'text': 'H\x8d\xa8\xff\x0f\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661199L, 'RBP': 8191L}, 'memory': {4661192L: 'H', 4661193L: '\x8d', 4661194L: '\xa8', 4661195L: '\xff', 4661196L: '\x0f', 4661197L: '\x00', 4661198L: '\x00'}}, 'disassembly': 'LEA RBP, [RAX+0xfff]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_2(self):
''' Instruction LEA R12, [RCX+0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'R12': 140737488345858L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299491L, 'RBP': 0L}, 'memory': {4299491L: 'L', 4299492L: '\x8d', 4299493L: 'a', 4299494L: '\x01'}}, 'text': 'L\x8da\x01', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'R12': 140737488345860L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299495L, 'RBP': 0L}, 'memory': {4299491L: 'L', 4299492L: '\x8d', 4299493L: 'a', 4299494L: '\x01'}}, 'disassembly': 'LEA R12, [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_20(self):
''' Instruction LEA R8, [RDI+R8] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'R8': 4L, 'RAX': 140737354125691L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392714L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'text': 'N\x8d\x04\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'R8': 140737354125691L, 'RAX': 140737354125691L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392718L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'disassembly': 'LEA R8, [RDI+R8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_21(self):
''' Instruction LEA RAX, [RBX+0x38] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757637L, 'RSI': 7L, 'RBX': 4194368L, 'RDI': 0L, 'RAX': 7065448L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4298110L, 'RBP': 0L}, 'memory': {4298112L: 'C', 4298113L: '8', 4298110L: 'H', 4298111L: '\x8d'}}, 'text': 'H\x8dC8', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 18446744073704757637L, 'RSI': 7L, 'RDI': 0L, 'RAX': 4194424L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4298114L, 'RBP': 0L}, 'memory': {4298112L: 'C', 4298113L: '8', 4298110L: 'H', 4298111L: '\x8d'}}, 'disassembly': 'LEA RAX, [RBX+0x38]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_22(self):
''' Instruction LEA RDI, [RIP+0x79299] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4297701L, 'RBP': 140737488346472L}, 'memory': {4297701L: 'H', 4297702L: '\x8d', 4297703L: '=', 4297704L: '\x99', 4297705L: '\x92', 4297706L: '\x07', 4297707L: '\x00'}}, 'text': 'H\x8d=\x99\x92\x07\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4297708L, 'RBP': 140737488346472L}, 'memory': {4297701L: 'H', 4297702L: '\x8d', 4297703L: '=', 4297704L: '\x99', 4297705L: '\x92', 4297706L: '\x07', 4297707L: '\x00'}}, 'disassembly': 'LEA RDI, [RIP+0x79299]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_23(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051384L, 'RSP': 140737488345712L, 'RDX': 64L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051400L, 'RSP': 140737488345712L, 'RDX': 64L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_24(self):
''' Instruction LEA RAX, [RDI+RDX-0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4350L, 'RSI': 4294967264L, 'RDI': 4783024L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4248073L, 'RBP': 140737488345936L}, 'memory': {4248073L: 'H', 4248074L: '\x8d', 4248075L: 'D', 4248076L: '\x17', 4248077L: '\xf0'}}, 'text': 'H\x8dD\x17\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4350L, 'RSI': 4294967264L, 'RDI': 4783024L, 'RAX': 4783009L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4248078L, 'RBP': 140737488345936L}, 'memory': {4248073L: 'H', 4248074L: '\x8d', 4248075L: 'D', 4248076L: '\x17', 4248077L: '\xf0'}}, 'disassembly': 'LEA RAX, [RDI+RDX-0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_25(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 16L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792432L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_26(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 280L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4792696L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_27(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052440L, 'RSP': 140737488345712L, 'RDX': 1120L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052456L, 'RSP': 140737488345712L, 'RDX': 1120L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_28(self):
''' Instruction LEA RSI, [RCX+RSI] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 32L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222797L, 'RBP': 7051232L}, 'memory': {4222800L: '1', 4222797L: 'H', 4222798L: '\x8d', 4222799L: '4'}}, 'text': 'H\x8d41', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222801L, 'RBP': 7051232L}, 'memory': {4222800L: '1', 4222797L: 'H', 4222798L: '\x8d', 4222799L: '4'}}, 'disassembly': 'LEA RSI, [RCX+RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_29(self):
''' Instruction LEA RDX, [RIP+0x461f9] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7074272L, 'RSI': 0L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 7065472L, 'RIP': 4520112L, 'RBP': 140737488346112L}, 'memory': {4520112L: 'H', 4520113L: '\x8d', 4520114L: '\x15', 4520115L: '\xf9', 4520116L: 'a', 4520117L: '\x04', 4520118L: '\x00'}}, 'text': 'H\x8d\x15\xf9a\x04\x00', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7074272L, 'RSI': 0L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 4807344L, 'RIP': 4520119L, 'RBP': 140737488346112L}, 'memory': {4520112L: 'H', 4520113L: '\x8d', 4520114L: '\x15', 4520115L: '\xf9', 4520116L: 'a', 4520117L: '\x04', 4520118L: '\x00'}}, 'disassembly': 'LEA RDX, [RIP+0x461f9]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_3(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052888L, 'RSP': 140737488345712L, 'RDX': 1568L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052904L, 'RSP': 140737488345712L, 'RDX': 1568L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_30(self):
''' Instruction LEA RDI, [RDI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125409L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'text': 'H\x8d\x7f ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125441L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244520L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'disassembly': 'LEA RDI, [RDI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_31(self):
''' Instruction LEA RDX, [RBP-0x128] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783020L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4783021L, 'RSP': 140737488344256L, 'RDX': 4783020L, 'RIP': 4330256L, 'RBP': 140737488345936L}, 'memory': {4330256L: 'H', 4330257L: '\x8d', 4330258L: '\x95', 4330259L: '\xd8', 4330260L: '\xfe', 4330261L: '\xff', 4330262L: '\xff'}}, 'text': 'H\x8d\x95\xd8\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783020L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4783021L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330263L, 'RBP': 140737488345936L}, 'memory': {4330256L: 'H', 4330257L: '\x8d', 4330258L: '\x95', 4330259L: '\xd8', 4330260L: '\xfe', 4330261L: '\xff', 4330262L: '\xff'}}, 'disassembly': 'LEA RDX, [RBP-0x128]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_32(self):
''' Instruction LEA RAX, [RDI+RDX-0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 57600L, 'RSI': 4294967168L, 'RDI': 4782912L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 8L, 'RIP': 4248073L, 'RBP': 140737488345936L}, 'memory': {4248073L: 'H', 4248074L: '\x8d', 4248075L: 'D', 4248076L: '\x17', 4248077L: '\xf0'}}, 'text': 'H\x8dD\x17\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 57600L, 'RSI': 4294967168L, 'RDI': 4782912L, 'RAX': 4782904L, 'RSP': 140737488344248L, 'RDX': 8L, 'RIP': 4248078L, 'RBP': 140737488345936L}, 'memory': {4248073L: 'H', 4248074L: '\x8d', 4248075L: 'D', 4248076L: '\x17', 4248077L: '\xf0'}}, 'disassembly': 'LEA RAX, [RDI+RDX-0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_33(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052968L, 'RSP': 140737488345712L, 'RDX': 1648L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052984L, 'RSP': 140737488345712L, 'RDX': 1648L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_34(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052456L, 'RSP': 140737488345712L, 'RDX': 1136L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052472L, 'RSP': 140737488345712L, 'RDX': 1136L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_35(self):
''' Instruction LEA RAX, [RDX+RDX*4] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327728L: '\x04', 4327729L: '\x92', 4327726L: 'H', 4327727L: '\x8d'}}, 'text': 'H\x8d\x04\x92', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327730L, 'RBP': 140737488345936L}, 'memory': {4327728L: '\x04', 4327729L: '\x92', 4327726L: 'H', 4327727L: '\x8d'}}, 'disassembly': 'LEA RAX, [RDX+RDX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_36(self):
''' Instruction LEA RDI, [RDI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125330L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'text': 'H\x8d\x7f ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125362L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244520L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'disassembly': 'LEA RDI, [RDI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_37(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051416L, 'RSP': 140737488345712L, 'RDX': 96L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051432L, 'RSP': 140737488345712L, 'RDX': 96L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_38(self):
''' Instruction LEA RSI, [RSI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'RDI': 140737354125695L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244512L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'text': 'H\x8dv ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125695L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'disassembly': 'LEA RSI, [RSI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_39(self):
''' Instruction LEA RSI, [RSI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782944L, 'RDI': 140737354125441L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244554L, 'RBP': 7049504L}, 'memory': {4244554L: 'H', 4244555L: '\x8d', 4244556L: 'v', 4244557L: ' '}}, 'text': 'H\x8dv ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125441L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244558L, 'RBP': 7049504L}, 'memory': {4244554L: 'H', 4244555L: '\x8d', 4244556L: 'v', 4244557L: ' '}}, 'disassembly': 'LEA RSI, [RSI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_4(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 408L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792824L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_40(self):
''' Instruction LEA RSI, [RIP+0x7c26b] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283886L, 'RBP': 9L}, 'memory': {4283886L: 'H', 4283887L: '\x8d', 4283888L: '5', 4283889L: 'k', 4283890L: '\xc2', 4283891L: '\x07', 4283892L: '\x00'}}, 'text': 'H\x8d5k\xc2\x07\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283893L, 'RBP': 9L}, 'memory': {4283886L: 'H', 4283887L: '\x8d', 4283888L: '5', 4283889L: 'k', 4283890L: '\xc2', 4283891L: '\x07', 4283892L: '\x00'}}, 'disassembly': 'LEA RSI, [RIP+0x7c26b]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_41(self):
''' Instruction LEA R13, [RCX+RAX*8-0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R13': 7051320L, 'RAX': 4L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4220990L, 'RBP': 7051232L}, 'memory': {4220992L: 'l', 4220993L: '\xc1', 4220994L: '\xf0', 4220990L: 'L', 4220991L: '\x8d'}}, 'text': 'L\x8dl\xc1\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R13': 7051352L, 'RAX': 4L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4220995L, 'RBP': 7051232L}, 'memory': {4220992L: 'l', 4220993L: '\xc1', 4220994L: '\xf0', 4220990L: 'L', 4220991L: '\x8d'}}, 'disassembly': 'LEA R13, [RCX+RAX*8-0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_42(self):
''' Instruction LEA RDI, [RDI+0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4248010L, 'RBP': 140737488345936L}, 'memory': {4248010L: 'H', 4248011L: '\x8d', 4248012L: '\x7f', 4248013L: '\x10'}}, 'text': 'H\x8d\x7f\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 4294967295L, 'RDI': 4782912L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4248014L, 'RBP': 140737488345936L}, 'memory': {4248010L: 'H', 4248011L: '\x8d', 4248012L: '\x7f', 4248013L: '\x10'}}, 'disassembly': 'LEA RDI, [RDI+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_43(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052232L, 'RSP': 140737488345712L, 'RDX': 912L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052248L, 'RSP': 140737488345712L, 'RDX': 912L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_44(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052616L, 'RSP': 140737488345712L, 'RDX': 1296L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052632L, 'RSP': 140737488345712L, 'RDX': 1296L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_45(self):
''' Instruction LEA RAX, [RIP+0x294b35] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330564L, 'RBP': 140737488345936L}, 'memory': {4330564L: 'H', 4330565L: '\x8d', 4330566L: '\x05', 4330567L: '5', 4330568L: 'K', 4330569L: ')', 4330570L: '\x00'}}, 'text': 'H\x8d\x055K)\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 7036800L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330571L, 'RBP': 140737488345936L}, 'memory': {4330564L: 'H', 4330565L: '\x8d', 4330566L: '\x05', 4330567L: '5', 4330568L: 'K', 4330569L: ')', 4330570L: '\x00'}}, 'disassembly': 'LEA RAX, [RIP+0x294b35]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_46(self):
''' Instruction LEA RDI, [RDI+0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4294934528L, 'RDI': 4782992L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4248042L, 'RBP': 140737488345936L}, 'memory': {4248042L: 'H', 4248043L: '\x8d', 4248044L: '\x7f', 4248045L: '\x10'}}, 'text': 'H\x8d\x7f\x10', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4294934528L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4248046L, 'RBP': 140737488345936L}, 'memory': {4248042L: 'H', 4248043L: '\x8d', 4248044L: '\x7f', 4248045L: '\x10'}}, 'disassembly': 'LEA RDI, [RDI+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_47(self):
''' Instruction LEA R8, [RIP-0x22e] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R8': 4283328L, 'RAX': 118L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283879L, 'RBP': 3L}, 'memory': {4283879L: 'L', 4283880L: '\x8d', 4283881L: '\x05', 4283882L: '\xd2', 4283883L: '\xfd', 4283884L: '\xff', 4283885L: '\xff'}}, 'text': 'L\x8d\x05\xd2\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R8': 4283328L, 'RAX': 118L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283886L, 'RBP': 3L}, 'memory': {4283879L: 'L', 4283880L: '\x8d', 4283881L: '\x05', 4283882L: '\xd2', 4283883L: '\xfd', 4283884L: '\xff', 4283885L: '\xff'}}, 'disassembly': 'LEA R8, [RIP-0x22e]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_48(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4792416L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_49(self):
''' Instruction LEA RAX, [RCX+0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 2147483636L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4330252L, 'RBP': 140737488345936L}, 'memory': {4330252L: 'H', 4330253L: '\x8d', 4330254L: 'A', 4330255L: '\x01'}}, 'text': 'H\x8dA\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 4782902L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4330256L, 'RBP': 140737488345936L}, 'memory': {4330252L: 'H', 4330253L: '\x8d', 4330254L: 'A', 4330255L: '\x01'}}, 'disassembly': 'LEA RAX, [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_5(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052680L, 'RSP': 140737488345712L, 'RDX': 1360L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052696L, 'RSP': 140737488345712L, 'RDX': 1360L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_50(self):
''' Instruction LEA RAX, [RSP+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 4782991L, 'RAX': 140737488346176L, 'RSP': 140737488345952L, 'RDX': 140737488345952L, 'RIP': 4198885L, 'RBP': 140737488346224L}, 'memory': {4198888L: '$', 4198889L: ' ', 4198885L: 'H', 4198886L: '\x8d', 4198887L: 'D'}}, 'text': 'H\x8dD$ ', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 4782991L, 'RAX': 140737488345984L, 'RSP': 140737488345952L, 'RDX': 140737488345952L, 'RIP': 4198890L, 'RBP': 140737488346224L}, 'memory': {4198888L: '$', 4198889L: ' ', 4198885L: 'H', 4198886L: '\x8d', 4198887L: 'D'}}, 'disassembly': 'LEA RAX, [RSP+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_51(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052024L, 'RSP': 140737488345712L, 'RDX': 704L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052040L, 'RSP': 140737488345712L, 'RDX': 704L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_52(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 272L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792688L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_53(self):
''' Instruction LEA EAX, [RDX+RDX-0x2] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'EAX': 47L, 'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219599L, 'RBP': 7051232L}, 'memory': {4219600L: 'D', 4219601L: '\x12', 4219602L: '\xfe', 4219599L: '\x8d'}}, 'text': '\x8dD\x12\xfe', 'pos': {'registers': {'EAX': 2L, 'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 2L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219603L, 'RBP': 7051232L}, 'memory': {4219600L: 'D', 4219601L: '\x12', 4219602L: '\xfe', 4219599L: '\x8d'}}, 'disassembly': 'LEA EAX, [RDX+RDX-0x2]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_54(self):
''' Instruction LEA R8D, [R13-0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RCX': 1024L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125693L, 'R13': 2L, 'RSI': 4783048L, 'R8D': 2L, 'RIP': 4392663L, 'RSP': 140737488344192L, 'RFLAGS': 663L, 'RAX': 3715L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'text': 'E\x8dE\xff', 'pos': {'registers': {'R8D': 1L, 'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'RAX': 3715L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392667L, 'RBP': 7049504L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'disassembly': 'LEA R8D, [R13-0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_55(self):
''' Instruction LEA R8D, [R13-0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RCX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125663L, 'R13': 4L, 'RSI': 4783016L, 'R8D': 7071872L, 'RIP': 4392663L, 'RSP': 140737488344192L, 'RFLAGS': 647L, 'RAX': 3745L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'text': 'E\x8dE\xff', 'pos': {'registers': {'R8D': 3L, 'RFLAGS': 647L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392667L, 'RBP': 7049504L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'disassembly': 'LEA R8D, [R13-0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_56(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052712L, 'RSP': 140737488345712L, 'RDX': 1392L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052728L, 'RSP': 140737488345712L, 'RDX': 1392L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_57(self):
''' Instruction LEA RAX, [RCX+RAX*8-0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 7051336L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 144L, 'RSP': 140737488345824L, 'RDX': 73L, 'RIP': 4221476L, 'RBP': 7051232L}, 'memory': {4221480L: '\xf0', 4221476L: 'H', 4221477L: '\x8d', 4221478L: 'D', 4221479L: '\xc1'}}, 'text': 'H\x8dD\xc1\xf0', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 7051336L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7052472L, 'RSP': 140737488345824L, 'RDX': 73L, 'RIP': 4221481L, 'RBP': 7051232L}, 'memory': {4221480L: '\xf0', 4221476L: 'H', 4221477L: '\x8d', 4221478L: 'D', 4221479L: '\xc1'}}, 'disassembly': 'LEA RAX, [RCX+RAX*8-0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_58(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 312L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792728L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_59(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053224L, 'RSP': 140737488345712L, 'RDX': 1904L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7053240L, 'RSP': 140737488345712L, 'RDX': 1904L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_6(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052952L, 'RSP': 140737488345712L, 'RDX': 1632L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052968L, 'RSP': 140737488345712L, 'RDX': 1632L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_60(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4792416L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_61(self):
''' Instruction LEA R14, [R13+0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RCX': 8L, 'RDX': 103L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 37L, 'R14': 35L, 'RSI': 4792712L, 'RIP': 4320736L, 'RSP': 140737488345888L, 'RFLAGS': 514L, 'RAX': 1L}, 'memory': {4320736L: 'M', 4320737L: '\x8d', 4320738L: 'u', 4320739L: '\x01'}}, 'text': 'M\x8du\x01', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 38L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320740L, 'RBP': 4792416L}, 'memory': {4320736L: 'M', 4320737L: '\x8d', 4320738L: 'u', 4320739L: '\x01'}}, 'disassembly': 'LEA R14, [R13+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_62(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052696L, 'RSP': 140737488345712L, 'RDX': 1376L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052712L, 'RSP': 140737488345712L, 'RDX': 1376L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_63(self):
''' Instruction LEA R13, [RCX+RAX*8-0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 1600L, 'RDI': 7051232L, 'R13': 7051320L, 'RAX': 146L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4220990L, 'RBP': 7051232L}, 'memory': {4220992L: 'l', 4220993L: '\xc1', 4220994L: '\xf0', 4220990L: 'L', 4220991L: '\x8d'}}, 'text': 'L\x8dl\xc1\xf0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 1600L, 'RDI': 7051232L, 'R13': 7052488L, 'RAX': 146L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4220995L, 'RBP': 7051232L}, 'memory': {4220992L: 'l', 4220993L: '\xc1', 4220994L: '\xf0', 4220990L: 'L', 4220991L: '\x8d'}}, 'disassembly': 'LEA R13, [RCX+RAX*8-0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_64(self):
''' Instruction LEA RSI, [RDI+R8+0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'R8': 0L, 'RAX': 140737354125329L, 'RSP': 140737488344192L, 'RDX': 4782903L, 'RIP': 4392673L, 'RBP': 7049504L}, 'memory': {4392673L: 'J', 4392674L: '\x8d', 4392675L: 't', 4392676L: '\x07', 4392677L: '\x01'}}, 'text': 'J\x8dt\x07\x01', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 57600L, 'RSI': 140737354125330L, 'RDI': 140737354125329L, 'RAX': 140737354125329L, 'RSP': 140737488344192L, 'RDX': 4782903L, 'RIP': 4392678L, 'RBP': 7049504L}, 'memory': {4392673L: 'J', 4392674L: '\x8d', 4392675L: 't', 4392676L: '\x07', 4392677L: '\x01'}}, 'disassembly': 'LEA RSI, [RDI+R8+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_65(self):
''' Instruction LEA R8, [RDI+R8] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 52L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'R8': 1L, 'RAX': 140737354125668L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392714L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'text': 'N\x8d\x04\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 52L, 'RSI': 140737354125668L, 'RDI': 140737354125667L, 'R8': 140737354125668L, 'RAX': 140737354125668L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392718L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'disassembly': 'LEA R8, [RDI+R8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_66(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052552L, 'RSP': 140737488345712L, 'RDX': 1232L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052568L, 'RSP': 140737488345712L, 'RDX': 1232L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_67(self):
''' Instruction LEA R8, [RIP-0x22e] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 188L, 'R8': 7058304L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4283879L, 'RBP': 3L}, 'memory': {4283879L: 'L', 4283880L: '\x8d', 4283881L: '\x05', 4283882L: '\xd2', 4283883L: '\xfd', 4283884L: '\xff', 4283885L: '\xff'}}, 'text': 'L\x8d\x05\xd2\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 1979931136L, 'RDI': 188L, 'R8': 4283328L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4283886L, 'RBP': 3L}, 'memory': {4283879L: 'L', 4283880L: '\x8d', 4283881L: '\x05', 4283882L: '\xd2', 4283883L: '\xfd', 4283884L: '\xff', 4283885L: '\xff'}}, 'disassembly': 'LEA R8, [RIP-0x22e]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_68(self):
''' Instruction LEA RDI, [RDI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125727L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244558L, 'RBP': 7049504L}, 'memory': {4244560L: '\x7f', 4244561L: ' ', 4244558L: 'H', 4244559L: '\x8d'}}, 'text': 'H\x8d\x7f ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125759L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244562L, 'RBP': 7049504L}, 'memory': {4244560L: '\x7f', 4244561L: ' ', 4244558L: 'H', 4244559L: '\x8d'}}, 'disassembly': 'LEA RDI, [RDI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_69(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 272L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792688L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_7(self):
''' Instruction LEA RDX, [RIP+0x267ea1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7042728L, 'RSI': 140737488346472L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 15L, 'RIP': 4519928L, 'RBP': 140737488346472L}, 'memory': {4519928L: 'H', 4519929L: '\x8d', 4519930L: '\x15', 4519931L: '\xa1', 4519932L: '~', 4519933L: '&', 4519934L: '\x00'}}, 'text': 'H\x8d\x15\xa1~&\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7042728L, 'RSI': 140737488346472L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7042720L, 'RIP': 4519935L, 'RBP': 140737488346472L}, 'memory': {4519928L: 'H', 4519929L: '\x8d', 4519930L: '\x15', 4519931L: '\xa1', 4519932L: '~', 4519933L: '&', 4519934L: '\x00'}}, 'disassembly': 'LEA RDX, [RIP+0x267ea1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_70(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 272L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792688L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_71(self):
''' Instruction LEA RAX, [RIP+0x201b] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239854L, 'RBP': 6L}, 'memory': {4239854L: 'H', 4239855L: '\x8d', 4239856L: '\x05', 4239857L: '\x1b', 4239858L: ' ', 4239859L: '\x00', 4239860L: '\x00'}}, 'text': 'H\x8d\x05\x1b \x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4248080L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4239861L, 'RBP': 6L}, 'memory': {4239854L: 'H', 4239855L: '\x8d', 4239856L: '\x05', 4239857L: '\x1b', 4239858L: ' ', 4239859L: '\x00', 4239860L: '\x00'}}, 'disassembly': 'LEA RAX, [RIP+0x201b]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_72(self):
''' Instruction LEA R8D, [R13-0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RCX': 1024L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125668L, 'R13': 12L, 'RSI': 4783022L, 'R8D': 12L, 'RIP': 4392663L, 'RSP': 140737488344192L, 'RFLAGS': 643L, 'RAX': 3740L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'text': 'E\x8dE\xff', 'pos': {'registers': {'R8D': 11L, 'RFLAGS': 643L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 140737354125668L, 'RAX': 3740L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392667L, 'RBP': 7049504L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'disassembly': 'LEA R8D, [R13-0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_73(self):
''' Instruction LEA RBX, [RIP+0x790f2] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RBX': 4864625L, 'RDI': 4793989L, 'RAX': 7040368L, 'RSP': 140737488346128L, 'RDX': 7065280L, 'RIP': 4297772L, 'RBP': 140737488346472L}, 'memory': {4297772L: 'H', 4297773L: '\x8d', 4297774L: '\x1d', 4297775L: '\xf2', 4297776L: '\x90', 4297777L: '\x07', 4297778L: '\x00'}}, 'text': 'H\x8d\x1d\xf2\x90\x07\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RBX': 4793637L, 'RDI': 4793989L, 'RAX': 7040368L, 'RSP': 140737488346128L, 'RDX': 7065280L, 'RIP': 4297779L, 'RBP': 140737488346472L}, 'memory': {4297772L: 'H', 4297773L: '\x8d', 4297774L: '\x1d', 4297775L: '\xf2', 4297776L: '\x90', 4297777L: '\x07', 4297778L: '\x00'}}, 'disassembly': 'LEA RBX, [RIP+0x790f2]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_74(self):
''' Instruction LEA RCX, [RBX-0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074256L, 'RSI': 7074272L, 'RBX': 7074256L, 'RDI': 7213056L, 'RAX': 33L, 'RSP': 140737488346032L, 'RDX': 33L, 'RIP': 4230194L, 'RBP': 7051232L}, 'memory': {4230194L: 'H', 4230195L: '\x8d', 4230196L: 'K', 4230197L: '\xf0'}}, 'text': 'H\x8dK\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 33L, 'RSP': 140737488346032L, 'RDX': 33L, 'RIP': 4230198L, 'RBP': 7051232L}, 'memory': {4230194L: 'H', 4230195L: '\x8d', 4230196L: 'K', 4230197L: '\xf0'}}, 'disassembly': 'LEA RCX, [RBX-0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_75(self):
''' Instruction LEA RDI, [RDI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125774L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'text': 'H\x8d\x7f ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125806L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244520L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'disassembly': 'LEA RDI, [RDI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_76(self):
''' Instruction LEA RSI, [RSI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244512L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'text': 'H\x8dv ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125330L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244512L: 'H', 4244513L: '\x8d', 4244514L: 'v', 4244515L: ' '}}, 'disassembly': 'LEA RSI, [RSI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_77(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051848L, 'RSP': 140737488345712L, 'RDX': 528L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051864L, 'RSP': 140737488345712L, 'RDX': 528L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_78(self):
''' Instruction LEA RDI, [RIP+0x79303] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 7065352L, 'RSP': 140737488346128L, 'RDX': 50859318435822L, 'RIP': 4297531L, 'RBP': 140737488346472L}, 'memory': {4297536L: '\x07', 4297537L: '\x00', 4297531L: 'H', 4297532L: '\x8d', 4297533L: '=', 4297534L: '\x03', 4297535L: '\x93'}}, 'text': 'H\x8d=\x03\x93\x07\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 7065352L, 'RSP': 140737488346128L, 'RDX': 50859318435822L, 'RIP': 4297538L, 'RBP': 140737488346472L}, 'memory': {4297536L: '\x07', 4297537L: '\x00', 4297531L: 'H', 4297532L: '\x8d', 4297533L: '=', 4297534L: '\x03', 4297535L: '\x93'}}, 'disassembly': 'LEA RDI, [RIP+0x79303]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_79(self):
''' Instruction LEA RDX, [RSP+0xcf] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782888L, 'RDI': 4782888L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 0L, 'RIP': 4198794L, 'RBP': 140737488346224L}, 'memory': {4198800L: '\x00', 4198801L: '\x00', 4198794L: 'H', 4198795L: '\x8d', 4198796L: '\x94', 4198797L: '$', 4198798L: '\xcf', 4198799L: '\x00'}}, 'text': 'H\x8d\x94$\xcf\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782888L, 'RDI': 4782888L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 140737488346159L, 'RIP': 4198802L, 'RBP': 140737488346224L}, 'memory': {4198800L: '\x00', 4198801L: '\x00', 4198794L: 'H', 4198795L: '\x8d', 4198796L: '\x94', 4198797L: '$', 4198798L: '\xcf', 4198799L: '\x00'}}, 'disassembly': 'LEA RDX, [RSP+0xcf]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_8(self):
''' Instruction LEA R8, [RDI+R8] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R8': 2L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392714L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'text': 'N\x8d\x04\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R8': 140737354125687L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392718L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'disassembly': 'LEA R8, [RDI+R8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_80(self):
''' Instruction LEA RDX, [RBP-0x128] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782995L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4782996L, 'RSP': 140737488344256L, 'RDX': 4782995L, 'RIP': 4330256L, 'RBP': 140737488345936L}, 'memory': {4330256L: 'H', 4330257L: '\x8d', 4330258L: '\x95', 4330259L: '\xd8', 4330260L: '\xfe', 4330261L: '\xff', 4330262L: '\xff'}}, 'text': 'H\x8d\x95\xd8\xfe\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782995L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4782996L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330263L, 'RBP': 140737488345936L}, 'memory': {4330256L: 'H', 4330257L: '\x8d', 4330258L: '\x95', 4330259L: '\xd8', 4330260L: '\xfe', 4330261L: '\xff', 4330262L: '\xff'}}, 'disassembly': 'LEA RDX, [RBP-0x128]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_81(self):
''' Instruction LEA RDI, [RDI+0x20] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125932L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244516L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'text': 'H\x8d\x7f ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 4782944L, 'RDI': 140737354125964L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244520L, 'RBP': 7049504L}, 'memory': {4244516L: 'H', 4244517L: '\x8d', 4244518L: '\x7f', 4244519L: ' '}}, 'disassembly': 'LEA RDI, [RDI+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_82(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 304L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4792720L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_83(self):
''' Instruction LEA R8, [RIP-0x22e] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R8': 4283328L, 'RAX': 90L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283879L, 'RBP': 9L}, 'memory': {4283879L: 'L', 4283880L: '\x8d', 4283881L: '\x05', 4283882L: '\xd2', 4283883L: '\xfd', 4283884L: '\xff', 4283885L: '\xff'}}, 'text': 'L\x8d\x05\xd2\xfd\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R8': 4283328L, 'RAX': 90L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283886L, 'RBP': 9L}, 'memory': {4283879L: 'L', 4283880L: '\x8d', 4283881L: '\x05', 4283882L: '\xd2', 4283883L: '\xfd', 4283884L: '\xff', 4283885L: '\xff'}}, 'disassembly': 'LEA R8, [RIP-0x22e]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_84(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051544L, 'RSP': 140737488345712L, 'RDX': 224L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051560L, 'RSP': 140737488345712L, 'RDX': 224L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_85(self):
''' Instruction LEA RAX, [RIP+0x4c] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 21L, 'RDI': 4782888L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 0L, 'RIP': 4198771L, 'RBP': 140737488346224L}, 'memory': {4198771L: 'H', 4198772L: '\x8d', 4198773L: '\x05', 4198774L: 'L', 4198775L: '\x00', 4198776L: '\x00', 4198777L: '\x00'}}, 'text': 'H\x8d\x05L\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 21L, 'RDI': 4782888L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 0L, 'RIP': 4198778L, 'RBP': 140737488346224L}, 'memory': {4198771L: 'H', 4198772L: '\x8d', 4198773L: '\x05', 4198774L: 'L', 4198775L: '\x00', 4198776L: '\x00', 4198777L: '\x00'}}, 'disassembly': 'LEA RAX, [RIP+0x4c]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_86(self):
''' Instruction LEA RSI, [RDI+R8+0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'R8': 1L, 'RAX': 140737354125693L, 'RSP': 140737488344192L, 'RDX': 4783048L, 'RIP': 4392673L, 'RBP': 7049504L}, 'memory': {4392673L: 'J', 4392674L: '\x8d', 4392675L: 't', 4392676L: '\x07', 4392677L: '\x01'}}, 'text': 'J\x8dt\x07\x01', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 140737354125693L, 'RSP': 140737488344192L, 'RDX': 4783048L, 'RIP': 4392678L, 'RBP': 7049504L}, 'memory': {4392673L: 'J', 4392674L: '\x8d', 4392675L: 't', 4392676L: '\x07', 4392677L: '\x01'}}, 'disassembly': 'LEA RSI, [RDI+R8+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_87(self):
''' Instruction LEA R8D, [R13-0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RCX': 4350L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125651L, 'R13': 12L, 'RSI': 4782997L, 'R8D': 12L, 'RIP': 4392663L, 'RSP': 140737488344192L, 'RFLAGS': 643L, 'RAX': 3757L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'text': 'E\x8dE\xff', 'pos': {'registers': {'R8D': 11L, 'RFLAGS': 643L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392667L, 'RBP': 7049504L}, 'memory': {4392664L: '\x8d', 4392665L: 'E', 4392666L: '\xff', 4392663L: 'E'}}, 'disassembly': 'LEA R8D, [R13-0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_88(self):
''' Instruction LEA R8, [RCX-0x1] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'R8': 2L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4346539L, 'RBP': 140737488345936L}, 'memory': {4346539L: 'L', 4346540L: '\x8d', 4346541L: 'A', 4346542L: '\xff'}}, 'text': 'L\x8dA\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'R8': 4L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4346543L, 'RBP': 140737488345936L}, 'memory': {4346539L: 'L', 4346540L: '\x8d', 4346541L: 'A', 4346542L: '\xff'}}, 'disassembly': 'LEA R8, [RCX-0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_89(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052328L, 'RSP': 140737488345712L, 'RDX': 1008L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052344L, 'RSP': 140737488345712L, 'RDX': 1008L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_9(self):
''' Instruction LEA RAX, [RDX+RDX*4] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327728L: '\x04', 4327729L: '\x92', 4327726L: 'H', 4327727L: '\x8d'}}, 'text': 'H\x8d\x04\x92', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327730L, 'RBP': 140737488345936L}, 'memory': {4327728L: '\x04', 4327729L: '\x92', 4327726L: 'H', 4327727L: '\x8d'}}, 'disassembly': 'LEA RAX, [RDX+RDX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_90(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 136L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4792552L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_91(self):
''' Instruction LEA RDI, [RIP+0x792ad] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297665L, 'RBP': 140737488346472L}, 'memory': {4297665L: 'H', 4297666L: '\x8d', 4297667L: '=', 4297668L: '\xad', 4297669L: '\x92', 4297670L: '\x07', 4297671L: '\x00'}}, 'text': 'H\x8d=\xad\x92\x07\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297672L, 'RBP': 140737488346472L}, 'memory': {4297665L: 'H', 4297666L: '\x8d', 4297667L: '=', 4297668L: '\xad', 4297669L: '\x92', 4297670L: '\x07', 4297671L: '\x00'}}, 'disassembly': 'LEA RDI, [RIP+0x792ad]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_92(self):
''' Instruction LEA R15, [R12+R13] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RCX': 0L, 'RDX': 78L, 'RBP': 7049504L, 'RDI': 140737354125409L, 'R13': 78L, 'R15': 4782912L, 'R12': 4782912L, 'RSI': 4782912L, 'RIP': 4392878L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3999L}, 'memory': {4392880L: '<', 4392881L: ',', 4392878L: 'O', 4392879L: '\x8d'}}, 'text': 'O\x8d<,', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4782990L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392882L, 'RBP': 7049504L}, 'memory': {4392880L: '<', 4392881L: ',', 4392878L: 'O', 4392879L: '\x8d'}}, 'disassembly': 'LEA R15, [R12+R13]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_93(self):
''' Instruction LEA RDI, [RDI+0x10] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 8208L, 'RDI': 140737488347344L, 'RAX': 140737488347341L, 'RSP': 140737488346168L, 'RDX': 13L, 'RIP': 4416384L, 'RBP': 140737488347312L}, 'memory': {4416384L: 'H', 4416385L: '\x8d', 4416386L: '\x7f', 4416387L: '\x10'}}, 'text': 'H\x8d\x7f\x10', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 31L, 'RSI': 8208L, 'RDI': 140737488347360L, 'RAX': 140737488347341L, 'RSP': 140737488346168L, 'RDX': 13L, 'RIP': 4416388L, 'RBP': 140737488347312L}, 'memory': {4416384L: 'H', 4416385L: '\x8d', 4416386L: '\x7f', 4416387L: '\x10'}}, 'disassembly': 'LEA RDI, [RDI+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_94(self):
''' Instruction LEA ESI, [RAX-0x30] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967294L, 'ESI': 4294967294L, 'RDI': 2L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299432L, 'RBP': 0L}, 'memory': {4299432L: '\x8d', 4299433L: 'p', 4299434L: '\xd0'}}, 'text': '\x8dp\xd0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'ESI': 4294967293L, 'RDI': 2L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299435L, 'RBP': 0L}, 'memory': {4299432L: '\x8d', 4299433L: 'p', 4299434L: '\xd0'}}, 'disassembly': 'LEA ESI, [RAX-0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_95(self):
''' Instruction LEA R8, [RDI+R8] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 49L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'R8': 2L, 'RAX': 140737354125323L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392714L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'text': 'N\x8d\x04\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 49L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'R8': 140737354125323L, 'RAX': 140737354125323L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392718L, 'RBP': 7049504L}, 'memory': {4392714L: 'N', 4392715L: '\x8d', 4392716L: '\x04', 4392717L: '\x07'}}, 'disassembly': 'LEA R8, [RDI+R8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_96(self):
''' Instruction LEA RAX, [RIP+0x2b296d] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 7051320L, 'RIP': 4222572L, 'RBP': 7051232L}, 'memory': {4222572L: 'H', 4222573L: '\x8d', 4222574L: '\x05', 4222575L: 'm', 4222576L: ')', 4222577L: '+', 4222578L: '\x00'}}, 'text': 'H\x8d\x05m)+\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051232L, 'RSP': 140737488345824L, 'RDX': 7051320L, 'RIP': 4222579L, 'RBP': 7051232L}, 'memory': {4222572L: 'H', 4222573L: '\x8d', 4222574L: '\x05', 4222575L: 'm', 4222576L: ')', 4222577L: '+', 4222578L: '\x00'}}, 'disassembly': 'LEA RAX, [RIP+0x2b296d]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_97(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052312L, 'RSP': 140737488345712L, 'RDX': 992L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052328L, 'RSP': 140737488345712L, 'RDX': 992L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_98(self):
''' Instruction LEA R15, [RBP+R15+0x0] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 136L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320766L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'text': 'N\x8d|=\x00', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4792552L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320768L: '|', 4320769L: '=', 4320770L: '\x00', 4320766L: 'N', 4320767L: '\x8d'}}, 'disassembly': 'LEA R15, [RBP+R15+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testLEA_99(self):
''' Instruction LEA RAX, [RCX+RDX] '''
test = {'mnemonic': 'LEA', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051640L, 'RSP': 140737488345712L, 'RDX': 320L, 'RIP': 4211136L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'text': 'H\x8d\x04\x11', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051656L, 'RSP': 140737488345712L, 'RDX': 320L, 'RIP': 4211140L, 'RBP': 7051232L}, 'memory': {4211136L: 'H', 4211137L: '\x8d', 4211138L: '\x04', 4211139L: '\x11'}}, 'disassembly': 'LEA RAX, [RCX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_1(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 308276084001730439550074880L, 'XMM0': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 101360535869359638812712377514826163237L, 'XMM0': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_10(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248046L, 'XMM3': 1324035698926381045275276563951124480L, 'XMM0': 61743963450839848825131331291115975791L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248050L, 'XMM3': 61743963450839848825131331291115975791L, 'XMM0': 61743963450839848825131331291115975791L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_11(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 71776119061217535, 'RCX': 4783042L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783152: 'c', 4783153: 'a', 4783154: 'n', 4783155: 'n', 4783156: 'o', 4783157: 't', 4783158: ' ', 4783159: 's', 4783160: 'e', 4783161: 't', 4783162: ' ', 4783163: '%', 4783164: 'f', 4783165: 's', 4783166: ' ', 4783167: 'b', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 101360535869359638812712377514826163237L, 'RCX': 4783042L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783152: 'c', 4783153: 'a', 4783154: 'n', 4783155: 'n', 4783156: 'o', 4783157: 't', 4783158: ' ', 4783159: 's', 4783160: 'e', 4783161: 't', 4783162: ' ', 4783163: '%', 4783164: 'f', 4783165: 's', 4783166: ' ', 4783167: 'b', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_12(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 78918677504442992524819169280L, 'RCX': 31L, 'RSI': 2048L, 'RDI': 140737488347360L, 'RAX': 140737488347355L, 'RSP': 140737488346168L, 'RDX': 11L, 'RIP': 4416380L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 140737488347456: '/', 140737488347457: 's', 140737488347458: 'h', 140737488347459: 'a', 140737488347460: 'r', 140737488347461: 'e', 140737488347462: '/', 140737488347463: 'm', 140737488347464: 'a', 140737488347465: 'n', 140737488347466: ':', 140737488347467: '/', 140737488347468: 'u', 140737488347469: 's', 140737488347470: 'r', 140737488347471: '/', 140737488347472: 's', 140737488347473: 'h', 140737488347474: 'a', 140737488347475: 'r', 140737488347476: 'e', 140737488347477: '/', 140737488347478: 'm', 140737488347479: 'a', 140737488347480: 'n', 140737488347481: ':', 140737488347482: '/', 140737488347483: 'u', 140737488347484: 's', 140737488347485: 'r', 140737488347486: '/', 140737488347487: 's', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 154696462191076794052440873859912395888L, 'RCX': 31L, 'RSI': 2048L, 'RDI': 140737488347360L, 'RAX': 140737488347355L, 'RSP': 140737488346168L, 'RDX': 11L, 'RIP': 4416384L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 140737488347456: '/', 140737488347457: 's', 140737488347458: 'h', 140737488347459: 'a', 140737488347460: 'r', 140737488347461: 'e', 140737488347462: '/', 140737488347463: 'm', 140737488347464: 'a', 140737488347465: 'n', 140737488347466: ':', 140737488347467: '/', 140737488347468: 'u', 140737488347469: 's', 140737488347470: 'r', 140737488347471: '/', 140737488347472: 's', 140737488347473: 'h', 140737488347474: 'a', 140737488347475: 'r', 140737488347476: 'e', 140737488347477: '/', 140737488347478: 'm', 140737488347479: 'a', 140737488347480: 'n', 140737488347481: ':', 140737488347482: '/', 140737488347483: 'u', 140737488347484: 's', 140737488347485: 'r', 140737488347486: '/', 140737488347487: 's', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_13(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782976L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 1324035698926381045275276563951124480L, 'XMM0': 94376511227379241736154044347596226881L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782976L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 94376511227379241736154044347596226881L, 'XMM0': 94376511227379241736154044347596226881L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_14(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248046L, 'XMM3': 0, 'XMM0': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248050L, 'XMM3': 129103300273056613552361913363439026186L, 'XMM0': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_15(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 340282346638528864515623922280452587520L, 'XMM0': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 6596154662119929836862747976992L, 'XMM0': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_16(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347312L, 'RSI': 4294967295L, 'RIP': 4416342L, 'XMM3': 0, 'XMM0': 132098688466593534319927079450625140783L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416344L: 'o', 4416345L: '\xd8', 4416342L: 'f', 4416343L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347312L, 'RSI': 4294967295L, 'RIP': 4416346L, 'XMM3': 132098688466593534319927079450625140783L, 'XMM0': 132098688466593534319927079450625140783L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416344L: 'o', 4416345L: '\xd8', 4416342L: 'f', 4416343L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_17(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4294967040L, 'RDI': 4782896L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4248038L, 'RBP': 140737488345936L}, 'memory': {4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 6596154662119929836862747976992L, 'RCX': 0L, 'RSI': 4294967040L, 'RDI': 4782896L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4248042L, 'RBP': 140737488345936L}, 'memory': {4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_18(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 20203181441137406086353707335680L, 'RCX': 4783016L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 129103300273056613552361913363439026186L, 'RCX': 4783016L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_19(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 308276084001730439550074880L, 'RCX': 4783036L, 'RSI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 43040918620421324091436533114482288498L, 'RCX': 4783036L, 'RSI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_2(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 20203181441137406086353707335680L, 'RCX': 4783022L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 129103300273056613552361913363439026186L, 'RCX': 4783022L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_20(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 308276084001730439550074880L, 'XMM0': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 101360535869359638812712377514826163237L, 'XMM0': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_21(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248046L, 'XMM3': 18446744073709551360L, 'XMM0': 43040918620421324091436533114482288498L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248050L, 'XMM3': 43040918620421324091436533114482288498L, 'XMM0': 43040918620421324091436533114482288498L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_22(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 0, 'XMM0': 61743963450839848825131331291115975791L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 61743963450839848825131331291115975791L, 'XMM0': 61743963450839848825131331291115975791L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_23(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 4278190080, 'RCX': 4782997L, 'RSI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 61743963450839848825131331291115975791L, 'RCX': 4782997L, 'RSI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_24(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 4278190080, 'RCX': 0L, 'RSI': 4294967264L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 8L, 'RIP': 4248038L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 129103300273056613552361913363439026186L, 'RCX': 0L, 'RSI': 4294967264L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 8L, 'RIP': 4248042L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_25(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416388L, 'XMM3': 0, 'XMM0': 154696462191076794052440873859912395888L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416392L, 'XMM3': 154696462191076794052440873859912395888L, 'XMM0': 154696462191076794052440873859912395888L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_26(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416388L, 'XMM3': 0, 'XMM0': 145391946241709797809872351733278401133L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416392L, 'XMM3': 145391946241709797809872351733278401133L, 'XMM0': 145391946241709797809872351733278401133L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_27(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 0, 'RCX': 4782888L, 'RSI': 4294967295L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4782880: '\x01', 4782881: '\x00', 4782882: '\x02', 4782883: '\x00', 4782884: '\x00', 4782885: '\x00', 4782886: '\x00', 4782887: '\x00', 4782888: 'A', 4782889: 'r', 4782890: 'g', 4782891: 'u', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 154763657361063560226840681733874122753L, 'RCX': 4782888L, 'RSI': 4294967295L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4782880: '\x01', 4782881: '\x00', 4782882: '\x02', 4782883: '\x00', 4782884: '\x00', 4782885: '\x00', 4782886: '\x00', 4782887: '\x00', 4782888: 'A', 4782889: 'r', 4782890: 'g', 4782891: 'u', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_28(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 1095216660480, 'RCX': 31L, 'RSI': 16L, 'RDI': 140737488347376L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4416380L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 140737488347456: '/', 140737488347457: 's', 140737488347458: 'h', 140737488347459: 'a', 140737488347460: 'r', 140737488347461: 'e', 140737488347462: '/', 140737488347463: 'm', 140737488347464: 'a', 140737488347465: 'n', 140737488347466: ':', 140737488347467: '/', 140737488347468: 'u', 140737488347469: 's', 140737488347470: 'r', 140737488347471: '/', 140737488347472: 's', 140737488347473: 'h', 140737488347474: 'a', 140737488347475: 'r', 140737488347476: 'e', 140737488347477: '/', 140737488347478: 'm', 140737488347479: 'a', 140737488347480: 'n', 140737488347481: ':', 140737488347482: '/', 140737488347483: 'u', 140737488347484: 's', 140737488347485: 'r', 140737488347486: '/', 140737488347487: 's', 140737488347488: 'h', 140737488347489: 'a', 140737488347490: 'r', 140737488347491: 'e', 140737488347492: '/', 140737488347493: 'g', 140737488347494: 'c', 140737488347495: 'c', 140737488347496: '-', 140737488347497: 'd', 140737488347498: 'a', 140737488347499: 't', 140737488347500: 'a', 140737488347501: '/', 140737488347502: 'x', 140737488347503: '8', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 261712993146723386499317935668814697L, 'RCX': 31L, 'RSI': 16L, 'RDI': 140737488347376L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4416384L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 140737488347456: '/', 140737488347457: 's', 140737488347458: 'h', 140737488347459: 'a', 140737488347460: 'r', 140737488347461: 'e', 140737488347462: '/', 140737488347463: 'm', 140737488347464: 'a', 140737488347465: 'n', 140737488347466: ':', 140737488347467: '/', 140737488347468: 'u', 140737488347469: 's', 140737488347470: 'r', 140737488347471: '/', 140737488347472: 's', 140737488347473: 'h', 140737488347474: 'a', 140737488347475: 'r', 140737488347476: 'e', 140737488347477: '/', 140737488347478: 'm', 140737488347479: 'a', 140737488347480: 'n', 140737488347481: ':', 140737488347482: '/', 140737488347483: 'u', 140737488347484: 's', 140737488347485: 'r', 140737488347486: '/', 140737488347487: 's', 140737488347488: 'h', 140737488347489: 'a', 140737488347490: 'r', 140737488347491: 'e', 140737488347492: '/', 140737488347493: 'g', 140737488347494: 'c', 140737488347495: 'c', 140737488347496: '-', 140737488347497: 'd', 140737488347498: 'a', 140737488347499: 't', 140737488347500: 'a', 140737488347501: '/', 140737488347502: 'x', 140737488347503: '8', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_29(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 5172014448931175958107644294594560L, 'RCX': 31L, 'RSI': 8208L, 'RDI': 140737488347344L, 'RAX': 140737488347341L, 'RSP': 140737488346168L, 'RDX': 13L, 'RIP': 4416380L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 140737488347456: '/', 140737488347457: 's', 140737488347458: 'h', 140737488347459: 'a', 140737488347460: 'r', 140737488347461: 'e', 140737488347462: '/', 140737488347463: 'm', 140737488347464: 'a', 140737488347465: 'n', 140737488347466: ':', 140737488347467: '/', 140737488347468: 'u', 140737488347469: 's', 140737488347470: 'r', 140737488347471: '/', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347344: 'm', 140737488347345: 'b', 140737488347346: 'e', 140737488347347: 'm', 140737488347348: 'u', 140737488347349: '-', 140737488347350: 'c', 140737488347351: 'l', 140737488347352: 'e', 140737488347353: 'a', 140737488347354: 'n', 140737488347355: '/', 140737488347356: 'e', 140737488347357: 'x', 140737488347358: 'a', 140737488347359: 'm', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 145391946241709797809872351733278401133L, 'RCX': 31L, 'RSI': 8208L, 'RDI': 140737488347344L, 'RAX': 140737488347341L, 'RSP': 140737488346168L, 'RDX': 13L, 'RIP': 4416384L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 140737488347456: '/', 140737488347457: 's', 140737488347458: 'h', 140737488347459: 'a', 140737488347460: 'r', 140737488347461: 'e', 140737488347462: '/', 140737488347463: 'm', 140737488347464: 'a', 140737488347465: 'n', 140737488347466: ':', 140737488347467: '/', 140737488347468: 'u', 140737488347469: 's', 140737488347470: 'r', 140737488347471: '/', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347344: 'm', 140737488347345: 'b', 140737488347346: 'e', 140737488347347: 'm', 140737488347348: 'u', 140737488347349: '-', 140737488347350: 'c', 140737488347351: 'l', 140737488347352: 'e', 140737488347353: 'a', 140737488347354: 'n', 140737488347355: '/', 140737488347356: 'e', 140737488347357: 'x', 140737488347358: 'a', 140737488347359: 'm', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_3(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 0, 'RCX': 4782991L, 'RSI': 4294967295L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 94376511227379241736154044347596226881L, 'RCX': 4782991L, 'RSI': 4294967295L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_30(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 280375465082880, 'RCX': 140737488347312L, 'RSI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416330L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 4416330L: 'f', 4416331L: '\x0f', 4416332L: 'o', 4416333L: '\x07', 140737488347312: '/', 140737488347313: 'h', 140737488347314: 'o', 140737488347315: 'm', 140737488347316: 'e', 140737488347317: '/', 140737488347318: 'f', 140737488347319: 'e', 140737488347320: 'l', 140737488347321: 'i', 140737488347322: 'p', 140737488347323: 'e', 140737488347324: '/', 140737488347325: 'H', 140737488347326: 'a', 140737488347327: 'c', 140737488347328: 'k', 140737488347329: 'i', 140737488347330: 'n', 140737488347331: 'g', 140737488347332: '/', 140737488347333: 'P', 140737488347334: 'r', 140737488347335: 'o', 140737488347336: 'j', 140737488347337: 'e', 140737488347338: 'c', 140737488347339: 't', 140737488347340: 's', 140737488347341: '/', 140737488347342: 's', 140737488347343: 'y', 140737488347344: 'm', 140737488347345: 'b', 140737488347346: 'e', 140737488347347: 'm', 140737488347348: 'u', 140737488347349: '-', 140737488347350: 'c', 140737488347351: 'l', 140737488347352: 'e', 140737488347353: 'a', 140737488347354: 'n', 140737488347355: '/', 140737488347356: 'e', 140737488347357: 'x', 140737488347358: 'a', 140737488347359: 'm', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 132098688466593534319927079450625140783L, 'RCX': 140737488347312L, 'RSI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416334L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 4416330L: 'f', 4416331L: '\x0f', 4416332L: 'o', 4416333L: '\x07', 140737488347312: '/', 140737488347313: 'h', 140737488347314: 'o', 140737488347315: 'm', 140737488347316: 'e', 140737488347317: '/', 140737488347318: 'f', 140737488347319: 'e', 140737488347320: 'l', 140737488347321: 'i', 140737488347322: 'p', 140737488347323: 'e', 140737488347324: '/', 140737488347325: 'H', 140737488347326: 'a', 140737488347327: 'c', 140737488347328: 'k', 140737488347329: 'i', 140737488347330: 'n', 140737488347331: 'g', 140737488347332: '/', 140737488347333: 'P', 140737488347334: 'r', 140737488347335: 'o', 140737488347336: 'j', 140737488347337: 'e', 140737488347338: 'c', 140737488347339: 't', 140737488347340: 's', 140737488347341: '/', 140737488347342: 's', 140737488347343: 'y', 140737488347344: 'm', 140737488347345: 'b', 140737488347346: 'e', 140737488347347: 'm', 140737488347348: 'u', 140737488347349: '-', 140737488347350: 'c', 140737488347351: 'l', 140737488347352: 'e', 140737488347353: 'a', 140737488347354: 'n', 140737488347355: '/', 140737488347356: 'e', 140737488347357: 'x', 140737488347358: 'a', 140737488347359: 'm', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_31(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 280375465148160, 'RCX': 4782899L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 6596154662119929836862747976992L, 'RCX': 4782899L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_32(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416388L, 'XMM3': 0, 'XMM0': 161434664049216810285368497307980294507L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416392L, 'XMM3': 161434664049216810285368497307980294507L, 'XMM0': 161434664049216810285368497307980294507L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_33(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4294934528L, 'RDI': 4782992L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4248038L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 61743963450839848825131331291115975791L, 'RCX': 0L, 'RSI': 4294934528L, 'RDI': 4782992L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4248042L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_34(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 18446744073709551360L, 'XMM0': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 129103300273056613552361913363439026186L, 'XMM0': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_35(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 308276084001730439550074880L, 'RCX': 0L, 'RSI': 4294963200L, 'RDI': 4783040L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 1024L, 'RIP': 4248038L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783152: 'c', 4783153: 'a', 4783154: 'n', 4783155: 'n', 4783156: 'o', 4783157: 't', 4783158: ' ', 4783159: 's', 4783160: 'e', 4783161: 't', 4783162: ' ', 4783163: '%', 4783164: 'f', 4783165: 's', 4783166: ' ', 4783167: 'b', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 101360535869359638812712377514826163237L, 'RCX': 0L, 'RSI': 4294963200L, 'RDI': 4783040L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 1024L, 'RIP': 4248042L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783152: 'c', 4783153: 'a', 4783154: 'n', 4783155: 'n', 4783156: 'o', 4783157: 't', 4783158: ' ', 4783159: 's', 4783160: 'e', 4783161: 't', 4783162: ' ', 4783163: '%', 4783164: 'f', 4783165: 's', 4783166: ' ', 4783167: 'b', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_36(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 280375465148160, 'RCX': 4782903L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 6596154662119929836862747976992L, 'RCX': 4782903L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00', 4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_37(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248046L, 'XMM3': 0, 'XMM0': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248050L, 'XMM3': 101360535869359638812712377514826163237L, 'XMM0': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_38(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248046L, 'XMM3': 18446744073692839680L, 'XMM0': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248050L, 'XMM3': 6596154662119929836862747976992L, 'XMM0': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248048L: 'o', 4248049L: '\xd8', 4248046L: 'f', 4248047L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_39(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 20203181441137406086353707335680L, 'RCX': 0L, 'RSI': 4294950912L, 'RDI': 4783024L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4096L, 'RIP': 4248038L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 43040918620421324091436533114482288498L, 'RCX': 0L, 'RSI': 4294950912L, 'RDI': 4783024L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4096L, 'RIP': 4248042L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4248038L: 'f', 4248039L: '\x0f', 4248040L: 'o', 4248041L: '\x07', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_4(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 0, 'XMM0': 43040918620421324091436533114482288498L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 43040918620421324091436533114482288498L, 'XMM0': 43040918620421324091436533114482288498L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_40(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 518L, 'XMM0': 20203181441137406366729172418815L, 'RCX': 31L, 'RSI': 4129L, 'RDI': 140737488347328L, 'RAX': 140737488347324L, 'RSP': 140737488346168L, 'RDX': 12L, 'RIP': 4416380L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347328: 'k', 140737488347329: 'i', 140737488347330: 'n', 140737488347331: 'g', 140737488347332: '/', 140737488347333: 'P', 140737488347334: 'r', 140737488347335: 'o', 140737488347336: 'j', 140737488347337: 'e', 140737488347338: 'c', 140737488347339: 't', 140737488347340: 's', 140737488347341: '/', 140737488347342: 's', 140737488347343: 'y', 140737488347344: 'm', 140737488347345: 'b', 140737488347346: 'e', 140737488347347: 'm', 140737488347348: 'u', 140737488347349: '-', 140737488347350: 'c', 140737488347351: 'l', 140737488347352: 'e', 140737488347353: 'a', 140737488347354: 'n', 140737488347355: '/', 140737488347356: 'e', 140737488347357: 'x', 140737488347358: 'a', 140737488347359: 'm', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 518L, 'XMM0': 161434664049216810285368497307980294507L, 'RCX': 31L, 'RSI': 4129L, 'RDI': 140737488347328L, 'RAX': 140737488347324L, 'RSP': 140737488346168L, 'RDX': 12L, 'RIP': 4416384L, 'RBP': 140737488347312L}, 'memory': {140737488347392: 'a', 140737488347393: 'r', 140737488347394: 'g', 140737488347395: '3', 140737488347396: '\x00', 140737488347397: 'M', 140737488347398: 'A', 140737488347399: 'N', 140737488347400: 'P', 140737488347401: 'A', 140737488347402: 'T', 140737488347403: 'H', 140737488347404: '=', 140737488347405: '/', 140737488347406: 'e', 140737488347407: 't', 140737488347408: 'c', 140737488347409: '/', 140737488347410: 'j', 140737488347411: 'a', 140737488347412: 'v', 140737488347413: 'a', 140737488347414: '-', 140737488347415: 'c', 140737488347416: 'o', 140737488347417: 'n', 140737488347418: 'f', 140737488347419: 'i', 140737488347420: 'g', 140737488347421: '-', 140737488347422: '2', 140737488347423: '/', 140737488347424: 'c', 140737488347425: 'u', 140737488347426: 'r', 140737488347427: 'r', 140737488347428: 'e', 140737488347429: 'n', 140737488347430: 't', 140737488347431: '-', 140737488347432: 's', 140737488347433: 'y', 140737488347434: 's', 140737488347435: 't', 140737488347436: 'e', 140737488347437: 'm', 140737488347438: '-', 140737488347439: 'v', 140737488347440: 'm', 140737488347441: '/', 140737488347442: 'm', 140737488347443: 'a', 140737488347444: 'n', 140737488347445: ':', 140737488347446: '/', 140737488347447: 'u', 140737488347448: 's', 140737488347449: 'r', 140737488347450: '/', 140737488347451: 'l', 140737488347452: 'o', 140737488347453: 'c', 140737488347454: 'a', 140737488347455: 'l', 4416380L: 'f', 4416381L: '\x0f', 4416382L: 'o', 4416383L: '\x07', 140737488347328: 'k', 140737488347329: 'i', 140737488347330: 'n', 140737488347331: 'g', 140737488347332: '/', 140737488347333: 'P', 140737488347334: 'r', 140737488347335: 'o', 140737488347336: 'j', 140737488347337: 'e', 140737488347338: 'c', 140737488347339: 't', 140737488347340: 's', 140737488347341: '/', 140737488347342: 's', 140737488347343: 'y', 140737488347344: 'm', 140737488347345: 'b', 140737488347346: 'e', 140737488347347: 'm', 140737488347348: 'u', 140737488347349: '-', 140737488347350: 'c', 140737488347351: 'l', 140737488347352: 'e', 140737488347353: 'a', 140737488347354: 'n', 140737488347355: '/', 140737488347356: 'e', 140737488347357: 'x', 140737488347358: 'a', 140737488347359: 'm', 140737488347360: 'p', 140737488347361: 'l', 140737488347362: 'e', 140737488347363: 's', 140737488347364: '/', 140737488347365: 't', 140737488347366: 'o', 140737488347367: 'y', 140737488347368: '0', 140737488347369: '0', 140737488347370: '9', 140737488347371: '-', 140737488347372: 's', 140737488347373: 't', 140737488347374: 'a', 140737488347375: 't', 140737488347376: 'i', 140737488347377: 'c', 140737488347378: '-', 140737488347379: '6', 140737488347380: '4', 140737488347381: '\x00', 140737488347382: 'a', 140737488347383: 'r', 140737488347384: 'g', 140737488347385: '1', 140737488347386: '\x00', 140737488347387: 'a', 140737488347388: 'r', 140737488347389: 'g', 140737488347390: '2', 140737488347391: '\x00'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_5(self):
''' Instruction MOVDQA XMM0, [RDI] '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RFLAGS': 646L, 'XMM0': 71776119061217535, 'RCX': 4783048L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783152: 'c', 4783153: 'a', 4783154: 'n', 4783155: 'n', 4783156: 'o', 4783157: 't', 4783158: ' ', 4783159: 's', 4783160: 'e', 4783161: 't', 4783162: ' ', 4783163: '%', 4783164: 'f', 4783165: 's', 4783166: ' ', 4783167: 'b', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0fo\x07', 'pos': {'registers': {'RFLAGS': 646L, 'XMM0': 101360535869359638812712377514826163237L, 'RCX': 4783048L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4783104: 't', 4783105: 'e', 4783106: 'r', 4783107: 'm', 4783108: 'i', 4783109: 'n', 4783110: 'e', 4783111: ' ', 4783112: 'k', 4783113: 'e', 4783114: 'r', 4783115: 'n', 4783116: 'e', 4783117: 'l', 4783118: ' ', 4783119: 'v', 4783120: 'e', 4783121: 'r', 4783122: 's', 4783123: 'i', 4783124: 'o', 4783125: 'n', 4783126: '\n', 4783127: '\x00', 4783128: '/', 4783129: 'd', 4783130: 'e', 4783131: 'v', 4783132: '/', 4783133: 'f', 4783134: 'u', 4783135: 'l', 4783136: 'l', 4783137: '\x00', 4783138: '/', 4783139: 'd', 4783140: 'e', 4783141: 'v', 4783142: '/', 4783143: 'n', 4783144: 'u', 4783145: 'l', 4783146: 'l', 4783147: '\x00', 4783148: '\x00', 4783149: '\x00', 4783150: '\x00', 4783151: '\x00', 4783152: 'c', 4783153: 'a', 4783154: 'n', 4783155: 'n', 4783156: 'o', 4783157: 't', 4783158: ' ', 4783159: 's', 4783160: 'e', 4783161: 't', 4783162: ' ', 4783163: '%', 4783164: 'f', 4783165: 's', 4783166: ' ', 4783167: 'b', 4247994L: 'f', 4247995L: '\x0f', 4247996L: 'o', 4247997L: '\x07', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'MOVDQA XMM0, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_6(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782880L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 338953138925461823674472811186503024640L, 'XMM0': 154763657361063560226840681733874122753L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782880L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 154763657361063560226840681733874122753L, 'XMM0': 154763657361063560226840681733874122753L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_7(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 18446744073709551360L, 'XMM0': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 129103300273056613552361913363439026186L, 'XMM0': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_8(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248006L, 'XMM3': 340282346638528864515623922280452587520L, 'XMM0': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248010L, 'XMM3': 6596154662119929836862747976992L, 'XMM0': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248008L: 'o', 4248009L: '\xd8', 4248006L: 'f', 4248007L: '\x0f'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQA_9(self):
''' Instruction MOVDQA XMM3, XMM0 '''
test = {'mnemonic': 'MOVDQA', 'pre': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416388L, 'XMM3': 0, 'XMM0': 261712993146723386499317935668814697L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'text': 'f\x0fo\xd8', 'pos': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416392L, 'XMM3': 261712993146723386499317935668814697L, 'XMM0': 261712993146723386499317935668814697L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416388L: 'f', 4416389L: '\x0f', 4416390L: 'o', 4416391L: '\xd8'}}, 'disassembly': 'MOVDQA XMM3, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_1(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_10(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_11(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_12(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 647L, 'XMM1': 86826932514745123378012629685768242252L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4793941: 'R', 4793942: 'Y', 4793943: '_', 4793944: 'P', 4793945: 'A', 4793946: 'T', 4793947: 'H', 4793948: '\x00', 4793949: 'L', 4793950: 'D', 4793951: '_', 4793952: 'B', 4793953: 'I', 4793954: 'N', 4793955: 'D', 4793956: '_', 4793957: 'N', 4793958: 'O', 4793959: 'W', 4793960: '\x00', 4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 647L, 'XMM1': 375554270925848303279633040492414028L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239605L, 'RBP': 140737488346472L}, 'memory': {4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4793941: 'R', 4793942: 'Y', 4793943: '_', 4793944: 'P', 4793945: 'A', 4793946: 'T', 4793947: 'H', 4793948: '\x00', 4793949: 'L', 4793950: 'D', 4793951: '_', 4793952: 'B', 4793953: 'I', 4793954: 'N', 4793955: 'D', 4793956: '_', 4793957: 'N', 4793958: 'O', 4793959: 'W', 4793960: '\x00', 4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_13(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_2(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4239603L: 'o', 4239602L: '\x0f', 4239601L: '\xf3', 4239604L: '\x0f', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 113401473871765646839159859486903977036L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239605L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4239603L: 'o', 4239602L: '\x0f', 4239601L: '\xf3', 4239604L: '\x0f', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_3(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 647L, 'XMM1': 375554270925848303279633040492414028L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7074288L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4793949: 'L', 4793950: 'D', 4793951: '_', 4793952: 'B', 4793953: 'I', 4793954: 'N', 4793955: 'D', 4793956: '_', 4793957: 'N', 4793958: 'O', 4793959: 'W', 4793960: '\x00', 4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 647L, 'XMM1': 88223701148664206693009503650295268428L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7074288L, 'RIP': 4239605L, 'RBP': 140737488346472L}, 'memory': {4793949: 'L', 4793950: 'D', 4793951: '_', 4793952: 'B', 4793953: 'I', 4793954: 'N', 4793955: 'D', 4793956: '_', 4793957: 'N', 4793958: 'O', 4793959: 'W', 4793960: '\x00', 4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_4(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_5(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 50859318435822L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4793925: 'L', 4793926: 'D', 4793927: '_', 4793928: 'W', 4793929: 'A', 4793930: 'R', 4793931: 'N', 4793932: '\x00', 4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4793941: 'R', 4793942: 'Y', 4793943: '_', 4793944: 'P', 4793945: 'A', 4793946: 'T', 4793947: 'H', 4793948: '\x00', 4793949: 'L', 4793950: 'D', 4793951: '_', 4793952: 'B', 4793953: 'I', 4793954: 'N', 4793955: 'D', 4793956: '_', 4793957: 'N', 4793958: 'O', 4793959: 'W', 4793960: '\x00', 4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86826932514745123378012629685768242252L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 50859318435822L, 'RIP': 4239605L, 'RBP': 140737488346472L}, 'memory': {4793925: 'L', 4793926: 'D', 4793927: '_', 4793928: 'W', 4793929: 'A', 4793930: 'R', 4793931: 'N', 4793932: '\x00', 4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4793941: 'R', 4793942: 'Y', 4793943: '_', 4793944: 'P', 4793945: 'A', 4793946: 'T', 4793947: 'H', 4793948: '\x00', 4793949: 'L', 4793950: 'D', 4793951: '_', 4793952: 'B', 4793953: 'I', 4793954: 'N', 4793955: 'D', 4793956: '_', 4793957: 'N', 4793958: 'O', 4793959: 'W', 4793960: '\x00', 4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_6(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_7(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_8(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 647L, 'XMM1': 88223701148664206693009503650295268428L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239601L, 'RBP': 140737488346472L}, 'memory': {4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 647L, 'XMM1': 90882157140230411661358273883331839052L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239605L, 'RBP': 140737488346472L}, 'memory': {4793961: 'L', 4793962: 'D', 4793963: '_', 4793964: 'B', 4793965: 'I', 4793966: 'N', 4793967: 'D', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVDQU_9(self):
''' Instruction MOVDQU XMM1, [RDI] '''
test = {'mnemonic': 'MOVDQU', 'pre': {'registers': {'RFLAGS': 643L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239601L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'text': '\xf3\x0fo\x0f', 'pos': {'registers': {'RFLAGS': 643L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239605L, 'RBP': 4782912L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4782917: 'A', 4782918: 'A', 4782919: 'A', 4782920: 'A', 4782921: 'A', 4782922: 'A', 4782923: 'A', 4782924: 'A', 4782925: 'A', 4782926: 'A', 4782927: 'A', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4239601L: '\xf3', 4239602L: '\x0f', 4239603L: 'o', 4239604L: '\x0f'}}, 'disassembly': 'MOVDQU XMM1, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_1(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 1L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4782997L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 1L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4782997L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_10(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 1L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783022L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 1L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783022L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_11(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 1685382481L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347312L, 'ESI': 47L, 'RSI': 47L, 'RIP': 4416304L, 'XMM1': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 6L}, 'memory': {4416304L: 'f', 4416305L: '\x0f', 4416306L: 'n', 4416307L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 1685382481L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347312L, 'ESI': 47L, 'RSI': 47L, 'RIP': 4416308L, 'XMM1': 47, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 6L}, 'memory': {4416304L: 'f', 4416305L: '\x0f', 4416306L: 'n', 4416307L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_2(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 83L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782903L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 83L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782903L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_3(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 1L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783036L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483630L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 1L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783036L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483630L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_4(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 7059408L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782991L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 7059408L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782991L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_5(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 4L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782888L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 4L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782888L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_6(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 2L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782899L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 2L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782899L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_7(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783042L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783042L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_8(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 2L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783048L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 2L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783048L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVD_9(self):
''' Instruction MOVD XMM1, ESI '''
test = {'mnemonic': 'MOVD', 'pre': {'registers': {'RCX': 43L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783016L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247968L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'text': 'f\x0fn\xce', 'pos': {'registers': {'RCX': 43L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783016L, 'ESI': 37L, 'RSI': 37L, 'RIP': 4247972L, 'XMM1': 37, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4247968L: 'f', 4247969L: '\x0f', 4247970L: 'n', 4247971L: '\xce'}}, 'disassembly': 'MOVD XMM1, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_1(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347088L, 'RAX': 4L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347088L, 'RAX': 18446744073709055096L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_10(self):
''' Instruction MOVSXD RAX, DWORD [RAX] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 140737488345992L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338823L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x04', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\xd0', 140737488346009: '\xb7', 140737488346010: 'k', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: 'A', 140737488346017: 'A', 140737488346018: 'A', 140737488346019: 'A', 140737488346020: 'A', 140737488346021: 'A', 140737488346022: 'A', 140737488346023: 'A', 4338824L: 'c', 4338825L: '\x00'}}, 'text': 'Hc\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x04', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\xd0', 140737488346009: '\xb7', 140737488346010: 'k', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: 'A', 140737488346017: 'A', 140737488346018: 'A', 140737488346019: 'A', 140737488346020: 'A', 140737488346021: 'A', 140737488346022: 'A', 140737488346023: 'A', 4338824L: 'c', 4338825L: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_11(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347008L, 'RAX': 3L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4296954L: 'H', 4296955L: 'c', 4296957L: '\x82', 4296956L: '\x04', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347008L, 'RAX': 18446744073709055080L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4296954L: 'H', 4296955L: 'c', 4296957L: '\x82', 4296956L: '\x04', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_12(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 13L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4793576: 'x', 4793577: 'l', 4793578: '\xf8', 4793579: '\xff', 4793580: 'x', 4793581: 'l', 4793582: '\xf8', 4793583: '\xff', 4793584: '\xd8', 4793585: 'l', 4793586: '\xf8', 4793587: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 18446744073709055288L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4793576: 'x', 4793577: 'l', 4793578: '\xf8', 4793579: '\xff', 4793580: 'x', 4793581: 'l', 4793582: '\xf8', 4793583: '\xff', 4793584: '\xd8', 4793585: 'l', 4793586: '\xf8', 4793587: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_13(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RAX': 2L, 'RDI': 140737354125693L, 'R12D': 30L, 'RSP': 140737488344256L, 'RDX': 4783050L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RAX': 2L, 'RDI': 140737354125693L, 'R12D': 30L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_14(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125853L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3555L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125853L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3555L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_15(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1089L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125681L, 'R14': 0L, 'RSI': 4783036L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3727L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1089L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125681L, 'R14': 0L, 'RSI': 4783036L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3727L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_16(self):
''' Instruction MOVSXD RDX, EDI '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RAX': 0L, 'RDI': 0L, 'EDI': 0L, 'RSP': 140737488346168L, 'RDX': 7059408L, 'RIP': 4285552L, 'RBP': 7054840L}, 'memory': {4285552L: 'H', 4285553L: 'c', 4285554L: '\xd7'}}, 'text': 'Hc\xd7', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RAX': 0L, 'RDI': 0L, 'EDI': 0L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4285555L, 'RBP': 7054840L}, 'memory': {4285552L: 'H', 4285553L: 'c', 4285554L: '\xd7'}}, 'disassembly': 'MOVSXD RDX, EDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_17(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125687L, 'RAX': 2L, 'RDI': 140737354125685L, 'R12D': 22L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125687L, 'RAX': 2L, 'RDI': 140737354125685L, 'R12D': 22L, 'RSP': 140737488344256L, 'RDX': 22L, 'RIP': 4337011L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_18(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 1000L, 'RDI': 140737488347152L, 'RAX': 9L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 1000L, 'RDI': 140737488347152L, 'RAX': 18446744073709055392L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_19(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_2(self):
''' Instruction MOVSXD RDI, EDI '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RAX': 4294967161L, 'RDI': 1L, 'EDI': 1L, 'RSP': 140737488343880L, 'RDX': 140737488343824L, 'RIP': 4673709L, 'RBP': 18446744073709551568L}, 'memory': {4673709L: 'H', 4673710L: 'c', 4673711L: '\xff'}}, 'text': 'Hc\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RAX': 4294967161L, 'RDI': 1L, 'EDI': 1L, 'RSP': 140737488343880L, 'RDX': 140737488343824L, 'RIP': 4673712L, 'RBP': 18446744073709551568L}, 'memory': {4673709L: 'H', 4673710L: 'c', 4673711L: '\xff'}}, 'disassembly': 'MOVSXD RDI, EDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_20(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 57632L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125323L, 'R14': 0L, 'RSI': 4782899L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 4085L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 57632L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125323L, 'R14': 0L, 'RSI': 4782899L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 4085L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_21(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125681L, 'RAX': 1L, 'RDI': 140737354125680L, 'R12D': 17L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125681L, 'RAX': 1L, 'RDI': 140737354125680L, 'R12D': 17L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4337011L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_22(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347104L, 'RAX': 5L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347104L, 'RAX': 18446744073709055096L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_23(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 30L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793624: '\x98', 4793625: 'l', 4793626: '\xf8', 4793627: '\xff', 4793628: '/', 4793629: 'v', 4793630: 'a', 4793631: 'r', 4793632: '/', 4793633: 't', 4793634: 'm', 4793635: 'p', 4793636: '\x00', 4793637: '/', 4793638: 'v', 4793639: 'a', 4793640: 'r', 4793641: '/', 4793642: 'p', 4793643: 'r', 4793644: 'o', 4793645: 'f', 4793646: 'i', 4793647: 'l', 4793648: 'e', 4793649: '\x00', 4793650: '\x00', 4793651: '\x00', 4793652: '\x00', 4793653: '\x00', 4793654: '\x00', 4793655: '\x00', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 18446744073709055128L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793624: '\x98', 4793625: 'l', 4793626: '\xf8', 4793627: '\xff', 4793628: '/', 4793629: 'v', 4793630: 'a', 4793631: 'r', 4793632: '/', 4793633: 't', 4793634: 'm', 4793635: 'p', 4793636: '\x00', 4793637: '/', 4793638: 'v', 4793639: 'a', 4793640: 'r', 4793641: '/', 4793642: 'p', 4793643: 'r', 4793644: 'o', 4793645: 'f', 4793646: 'i', 4793647: 'l', 4793648: 'e', 4793649: '\x00', 4793650: '\x00', 4793651: '\x00', 4793652: '\x00', 4793653: '\x00', 4793654: '\x00', 4793655: '\x00', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_24(self):
''' Instruction MOVSXD RDI, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 9L, 'RSI': 1L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285735L, 'RBP': 8192L}, 'memory': {4285736L: 'c', 4285737L: '\xf8', 4285735L: 'H'}}, 'text': 'Hc\xf8', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 9L, 'RSI': 1L, 'RDI': 1L, 'RAX': 1L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285738L, 'RBP': 8192L}, 'memory': {4285736L: 'c', 4285737L: '\xf8', 4285735L: 'H'}}, 'disassembly': 'MOVSXD RDI, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_25(self):
''' Instruction MOVSXD RAX, DWORD [RAX] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 140737488345992L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338823L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 140737488345992: '\x15', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '9', 140737488346001: '\xfb', 140737488346002: 'H', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\x04', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: '\x0b', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 4338824L: 'c', 4338825L: '\x00'}}, 'text': 'Hc\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 140737488345992: '\x15', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '9', 140737488346001: '\xfb', 140737488346002: 'H', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\x04', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: '\x0b', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 4338824L: 'c', 4338825L: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_26(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125695L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3713L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125695L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3713L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_27(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783040L, 'RSI': 140737354125685L, 'RAX': 4L, 'RDI': 140737354125681L, 'R12D': 18L, 'RSP': 140737488344256L, 'RDX': 4783040L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783040L, 'RSI': 140737354125685L, 'RAX': 4L, 'RDI': 140737354125681L, 'R12D': 18L, 'RSP': 140737488344256L, 'RDX': 18L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_28(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 83L, 'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 83L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 83L, 'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 83L, 'RSP': 140737488344256L, 'RDX': 83L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_29(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4793576: 'x', 4793577: 'l', 4793578: '\xf8', 4793579: '\xff', 4793580: 'x', 4793581: 'l', 4793582: '\xf8', 4793583: '\xff', 4793584: '\xd8', 4793585: 'l', 4793586: '\xf8', 4793587: '\xff', 4793588: 'x', 4793589: 'l', 4793590: '\xf8', 4793591: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347024L, 'RAX': 18446744073709055248L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4793576: 'x', 4793577: 'l', 4793578: '\xf8', 4793579: '\xff', 4793580: 'x', 4793581: 'l', 4793582: '\xf8', 4793583: '\xff', 4793584: '\xd8', 4793585: 'l', 4793586: '\xf8', 4793587: '\xff', 4793588: 'x', 4793589: 'l', 4793590: '\xf8', 4793591: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_3(self):
''' Instruction MOVSXD RAX, DWORD [RBP-0x580] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336552L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'text': 'Hc\x85\x80\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336559L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RBP-0x580]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_30(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 83L, 'RSI': 140737354125329L, 'RAX': 4L, 'RDI': 140737354125325L, 'R12D': 13L, 'RSP': 140737488344256L, 'RDX': 4782909L, 'RIP': 4346940L, 'RBP': 140737488345936L}, 'memory': {4346940L: 'I', 4346941L: 'c', 4346942L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 83L, 'RSI': 140737354125329L, 'RAX': 4L, 'RDI': 140737354125325L, 'R12D': 13L, 'RSP': 140737488344256L, 'RDX': 13L, 'RIP': 4346943L, 'RBP': 140737488345936L}, 'memory': {4346940L: 'I', 4346941L: 'c', 4346942L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_31(self):
''' Instruction MOVSXD RAX, DWORD [RBP-0x580] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336552L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'text': 'Hc\x85\x80\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336559L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RBP-0x580]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_32(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 2L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125691L, 'R14': 0L, 'RSI': 140737488345638L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3717L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 2L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125691L, 'R14': 0L, 'RSI': 140737488345638L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3717L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_33(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_34(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 8L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347136L, 'RAX': 18446744073709055424L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_35(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1024L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125693L, 'R14': 0L, 'RSI': 4783048L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3715L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1024L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125693L, 'R14': 0L, 'RSI': 4783048L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3715L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_36(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 4294967292L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125325L, 'R14': 0L, 'RSI': 4782905L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 4083L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 4294967292L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125325L, 'R14': 0L, 'RSI': 4782905L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 4083L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_37(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_38(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 11L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4793576: 'x', 4793577: 'l', 4793578: '\xf8', 4793579: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 18446744073709055328L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4793576: 'x', 4793577: 'l', 4793578: '\xf8', 4793579: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_39(self):
''' Instruction MOVSXD RDI, R13D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 519L, 'R13D': 7L, 'RCX': 18446744073709551615L, 'RSI': 140737488346385L, 'RDI': 7L, 'RAX': 7L, 'RSP': 140737488346240L, 'RDX': 7L, 'RIP': 4196403L, 'RBP': 0L}, 'memory': {4196403L: 'I', 4196404L: 'c', 4196405L: '\xfd'}}, 'text': 'Ic\xfd', 'pos': {'registers': {'RFLAGS': 519L, 'R13D': 7L, 'RCX': 18446744073709551615L, 'RSI': 140737488346385L, 'RDI': 7L, 'RAX': 7L, 'RSP': 140737488346240L, 'RDX': 7L, 'RIP': 4196406L, 'RBP': 0L}, 'memory': {4196403L: 'I', 4196404L: 'c', 4196405L: '\xfd'}}, 'disassembly': 'MOVSXD RDI, R13D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_4(self):
''' Instruction MOVSXD RAX, DWORD [RBP-0x580] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336552L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'text': 'Hc\x85\x80\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336559L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RBP-0x580]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_40(self):
''' Instruction MOVSXD RAX, DWORD [RSP+0xc] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'RAX': 7053688L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4195925L, 'RBP': 0L}, 'memory': {4195929L: '\x0c', 4195926L: 'c', 4195928L: '$', 4195927L: 'D', 140737488346252: '\x04', 140737488346253: '\x00', 140737488346254: '\x00', 140737488346255: '\x00', 140737488346256: 'h', 140737488346257: '\xdd', 140737488346258: '\xff', 140737488346259: '\xff', 140737488346260: '\xff', 140737488346261: '\x7f', 140737488346262: '\x00', 140737488346263: '\x00', 140737488346264: '\x0c', 140737488346265: '\x05', 140737488346266: '@', 140737488346267: '\x00', 140737488346268: '\x00', 140737488346269: '\x00', 140737488346270: '\x00', 140737488346271: '\x00', 140737488346272: '\x00', 140737488346273: '\x00', 140737488346274: '\x00', 140737488346275: '\x00', 140737488346276: '\x00', 140737488346277: '\x00', 140737488346278: '\x00', 140737488346279: '\x00', 140737488346280: '\x00', 140737488346281: '\x00', 140737488346282: '\x00', 140737488346283: '\x00', 4195925L: 'H'}}, 'text': 'HcD$\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'RAX': 4L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4195930L, 'RBP': 0L}, 'memory': {4195929L: '\x0c', 4195926L: 'c', 4195928L: '$', 4195927L: 'D', 140737488346252: '\x04', 140737488346253: '\x00', 140737488346254: '\x00', 140737488346255: '\x00', 140737488346256: 'h', 140737488346257: '\xdd', 140737488346258: '\xff', 140737488346259: '\xff', 140737488346260: '\xff', 140737488346261: '\x7f', 140737488346262: '\x00', 140737488346263: '\x00', 140737488346264: '\x0c', 140737488346265: '\x05', 140737488346266: '@', 140737488346267: '\x00', 140737488346268: '\x00', 140737488346269: '\x00', 140737488346270: '\x00', 140737488346271: '\x00', 140737488346272: '\x00', 140737488346273: '\x00', 140737488346274: '\x00', 140737488346275: '\x00', 140737488346276: '\x00', 140737488346277: '\x00', 140737488346278: '\x00', 140737488346279: '\x00', 140737488346280: '\x00', 140737488346281: '\x00', 140737488346282: '\x00', 140737488346283: '\x00', 4195925L: 'H'}}, 'disassembly': 'MOVSXD RAX, DWORD [RSP+0xc]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_41(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125323L, 'RAX': 2L, 'RDI': 140737354125321L, 'R12D': 9L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125323L, 'RAX': 2L, 'RDI': 140737354125321L, 'R12D': 9L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4337011L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_42(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 2L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4296956L: '\x04', 4296954L: 'H', 4296955L: 'c', 4296957L: '\x82', 4793512: '\xe0', 4793513: 'm', 4793514: '\xf8', 4793515: '\xff', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347072L, 'RAX': 18446744073709055456L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4296956L: '\x04', 4296954L: 'H', 4296955L: 'c', 4296957L: '\x82', 4793512: '\xe0', 4793513: 'm', 4793514: '\xf8', 4793515: '\xff', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_43(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125646L, 'R14': 0L, 'RSI': 4782991L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3762L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125646L, 'R14': 0L, 'RSI': 4782991L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3762L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_44(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125330L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 4078L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125330L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 4078L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_45(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1088L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125687L, 'R14': 0L, 'RSI': 4783042L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3721L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1088L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125687L, 'R14': 0L, 'RSI': 4783042L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3721L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_46(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RAX': 12L, 'RDI': 140737354125651L, 'R12D': 5L, 'RSP': 140737488344256L, 'RDX': 4783009L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RAX': 12L, 'RDI': 140737354125651L, 'R12D': 5L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_47(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347040L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4296957L: '\x82', 4296956L: '\x04', 4296955L: 'c', 4296954L: 'H', 4793504: '\x08', 4793505: 'n', 4793506: '\xf8', 4793507: '\xff', 4793508: 'x', 4793509: 'l', 4793510: '\xf8', 4793511: '\xff', 4793512: '\xe0', 4793513: 'm', 4793514: '\xf8', 4793515: '\xff', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347040L, 'RAX': 18446744073709055496L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4296957L: '\x82', 4296956L: '\x04', 4296955L: 'c', 4296954L: 'H', 4793504: '\x08', 4793505: 'n', 4793506: '\xf8', 4793507: '\xff', 4793508: 'x', 4793509: 'l', 4793510: '\xf8', 4793511: '\xff', 4793512: '\xe0', 4793513: 'm', 4793514: '\xf8', 4793515: '\xff', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_48(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125693L, 'RAX': 2L, 'RDI': 140737354125691L, 'R12D': 28L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737354125693L, 'RAX': 2L, 'RDI': 140737354125691L, 'R12D': 28L, 'RSP': 140737488344256L, 'RDX': 28L, 'RIP': 4337011L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_49(self):
''' Instruction MOVSXD RAX, DWORD [RAX] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 140737488346008L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338823L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 4338824L: 'c', 4338825L: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00'}}, 'text': 'Hc\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 4338824L: 'c', 4338825L: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_5(self):
''' Instruction MOVSXD RAX, DWORD [RAX] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 140737488345992L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338823L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 4338824L: 'c', 4338825L: '\x00'}}, 'text': 'Hc\x00', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 4338824L: 'c', 4338825L: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_50(self):
''' Instruction MOVSXD RAX, DWORD [RAX] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 140737488346000L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338823L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 4338824L: 'c', 4338825L: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00'}}, 'text': 'Hc\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 4338824L: 'c', 4338825L: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '+', 140737488346009: '\x00', 140737488346010: '\x00', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_51(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RAX': 2L, 'RDI': 140737354125323L, 'R12D': 11L, 'RSP': 140737488344256L, 'RDX': 4782901L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'RAX': 2L, 'RDI': 140737354125323L, 'R12D': 11L, 'RSP': 140737488344256L, 'RDX': 11L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_52(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 2L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125685L, 'R14': 0L, 'RSI': 140737488345638L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3723L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 2L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125685L, 'R14': 0L, 'RSI': 140737488345638L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3723L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_53(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125409L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3999L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125409L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3999L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_54(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125650L, 'R14': 0L, 'RSI': 140737488345639L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3758L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125650L, 'R14': 0L, 'RSI': 140737488345639L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3758L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_55(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_56(self):
''' Instruction MOVSXD RAX, DWORD [RBP-0x580] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336552L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'text': 'Hc\x85\x80\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336559L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RBP-0x580]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_57(self):
''' Instruction MOVSXD RAX, DWORD [RBP-0x580] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336552L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'text': 'Hc\x85\x80\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336559L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RBP-0x580]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_58(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125567L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3841L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125567L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3841L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_59(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125667L, 'R14': 0L, 'RSI': 140737488345639L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3741L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125667L, 'R14': 0L, 'RSI': 140737488345639L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3741L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_6(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 10L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 18446744073709055360L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4793560: '\x10', 4793561: 'm', 4793562: '\xf8', 4793563: '\xff', 4793564: 'x', 4793565: 'l', 4793566: '\xf8', 4793567: '\xff', 4793568: 'x', 4793569: 'l', 4793570: '\xf8', 4793571: '\xff', 4793572: 'x', 4793573: 'l', 4793574: '\xf8', 4793575: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_60(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 57600L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125329L, 'R14': 0L, 'RSI': 4782903L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 4079L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 57600L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125329L, 'R14': 0L, 'RSI': 4782903L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 4079L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_61(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783046L, 'RSI': 140737354125691L, 'RAX': 4L, 'RDI': 140737354125687L, 'R12D': 24L, 'RSP': 140737488344256L, 'RDX': 4783046L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783046L, 'RSI': 140737354125691L, 'RAX': 4L, 'RDI': 140737354125687L, 'R12D': 24L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_62(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125932L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3476L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125932L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3476L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_63(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125774L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3634L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125774L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 514L, 'RAX': 3634L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_64(self):
''' Instruction MOVSXD RAX, DWORD [RBP-0x580] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336552L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'text': 'Hc\x85\x80\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336559L, 'RBP': 140737488345936L}, 'memory': {140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 140737488344534: '\x00', 140737488344535: '\x00', 140737488344536: '\x00', 140737488344537: '\x00', 140737488344538: '\x00', 140737488344539: '\x00', 140737488344540: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344543: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 4336552L: 'H', 4336553L: 'c', 4336554L: '\x85', 4336555L: '\x80', 4336556L: '\xfa', 4336557L: '\xff', 4336558L: '\xff', 140737488344559: '\x00', 140737488344552: '\x00', 140737488344558: '\x00', 140737488344553: '\x00', 140737488344554: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RBP-0x580]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_65(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RAX': 1L, 'RDI': 140737354125329L, 'R12D': 17L, 'RSP': 140737488344256L, 'RDX': 4782904L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RAX': 1L, 'RDI': 140737354125329L, 'R12D': 17L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_66(self):
''' Instruction MOVSXD RAX, DWORD [RAX] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 140737488346016L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4338823L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 4338824L: 'c', 4338825L: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00', 140737488346040: 'r', 140737488346041: '`', 140737488346042: 'A', 140737488346043: '\x00', 140737488346044: '\x00', 140737488346045: '\x00', 140737488346046: '\x00', 140737488346047: '\x00'}}, 'text': 'Hc\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 40L, 'RIP': 4338826L, 'RBP': 140737488345936L}, 'memory': {4338823L: 'H', 4338824L: 'c', 4338825L: '\x00', 140737488346016: ',', 140737488346017: '\x00', 140737488346018: '\x00', 140737488346019: '\x00', 140737488346020: '\x00', 140737488346021: '\x00', 140737488346022: '\x00', 140737488346023: '\x00', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00', 140737488346040: 'r', 140737488346041: '`', 140737488346042: 'A', 140737488346043: '\x00', 140737488346044: '\x00', 140737488346045: '\x00', 140737488346046: '\x00', 140737488346047: '\x00'}}, 'disassembly': 'MOVSXD RAX, DWORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_67(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125668L, 'RAX': 1L, 'RDI': 140737354125667L, 'R12D': 4L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125668L, 'RAX': 1L, 'RDI': 140737354125667L, 'R12D': 4L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4337011L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_68(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125663L, 'R14': 0L, 'RSI': 4783016L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3745L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125663L, 'R14': 0L, 'RSI': 4783016L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3745L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_69(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_7(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125680L, 'R14': 0L, 'RSI': 140737488345639L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3728L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125680L, 'R14': 0L, 'RSI': 140737488345639L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3728L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_70(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 15L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 20L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793600: 'x', 4793601: 'l', 4793602: '\xf8', 4793603: '\xff', 4793604: 'x', 4793605: 'l', 4793606: '\xf8', 4793607: '\xff', 4793608: 'x', 4793609: 'l', 4793610: '\xf8', 4793611: '\xff', 4793612: 'x', 4793613: 'l', 4793614: '\xf8', 4793615: '\xff', 4793594: '\xf8', 4793595: '\xff', 4793596: 'x', 4793597: 'l', 4793584: '\xd8', 4793585: 'l', 4793586: '\xf8', 4793587: '\xff', 4793588: 'x', 4793589: 'l', 4793590: '\xf8', 4793591: '\xff', 4793592: '\xb8', 4793593: 'l', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793598: '\xf8', 4793599: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 15L, 'RSI': 0L, 'RDI': 140737488347200L, 'RAX': 18446744073709055192L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793600: 'x', 4793601: 'l', 4793602: '\xf8', 4793603: '\xff', 4793604: 'x', 4793605: 'l', 4793606: '\xf8', 4793607: '\xff', 4793608: 'x', 4793609: 'l', 4793610: '\xf8', 4793611: '\xff', 4793612: 'x', 4793613: 'l', 4793614: '\xf8', 4793615: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793584: '\xd8', 4793585: 'l', 4793586: '\xf8', 4793587: '\xff', 4793588: 'x', 4793589: 'l', 4793590: '\xf8', 4793591: '\xff', 4793592: '\xb8', 4793593: 'l', 4793594: '\xf8', 4793595: '\xff', 4793596: 'x', 4793597: 'l', 4793598: '\xf8', 4793599: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_71(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 1024L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125668L, 'R14': 0L, 'RSI': 4783022L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3740L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 1024L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125668L, 'R14': 0L, 'RSI': 4783022L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3740L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_72(self):
''' Instruction MOVSXD RDX, EAX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'text': 'Hc\xd0', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330553L, 'RBP': 140737488345936L}, 'memory': {4330552L: '\xd0', 4330550L: 'H', 4330551L: 'c'}}, 'disassembly': 'MOVSXD RDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_73(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125488L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3920L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125488L, 'R14': 0L, 'RSI': 4782912L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 3920L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_74(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 4350L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125651L, 'R14': 0L, 'RSI': 4782997L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3757L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 4350L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125651L, 'R14': 0L, 'RSI': 4782997L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 3757L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_75(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RAX': 12L, 'RDI': 140737354125668L, 'R12D': 5L, 'RSP': 140737488344256L, 'RDX': 4783034L, 'RIP': 4338831L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'RAX': 12L, 'RDI': 140737354125668L, 'R12D': 5L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4338834L, 'RBP': 140737488345936L}, 'memory': {4338832L: 'c', 4338833L: '\xd4', 4338831L: 'I'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_76(self):
''' Instruction MOVSXD RDX, R12D '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125651L, 'RAX': 1L, 'RDI': 140737354125650L, 'R12D': 4L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4337008L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'text': 'Ic\xd4', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737354125651L, 'RAX': 1L, 'RDI': 140737354125650L, 'R12D': 4L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4337011L, 'RBP': 140737488345936L}, 'memory': {4337008L: 'I', 4337009L: 'c', 4337010L: '\xd4'}}, 'disassembly': 'MOVSXD RDX, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_77(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347056L, 'RAX': 1L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4296957L: '\x82', 4296956L: '\x04', 4296954L: 'H', 4296955L: 'c', 4793508: 'x', 4793509: 'l', 4793510: '\xf8', 4793511: '\xff', 4793512: '\xe0', 4793513: 'm', 4793514: '\xf8', 4793515: '\xff', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347056L, 'RAX': 18446744073709055096L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4296957L: '\x82', 4296956L: '\x04', 4296954L: 'H', 4296955L: 'c', 4793508: 'x', 4793509: 'l', 4793510: '\xf8', 4793511: '\xff', 4793512: '\xe0', 4793513: 'm', 4793514: '\xf8', 4793515: '\xff', 4793516: 'h', 4793517: 'l', 4793518: '\xf8', 4793519: '\xff', 4793520: 'x', 4793521: 'l', 4793522: '\xf8', 4793523: '\xff', 4793524: 'x', 4793525: 'l', 4793526: '\xf8', 4793527: '\xff', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_8(self):
''' Instruction MOVSXD RAX, DWORD [RDX+RAX*4] '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 6L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296954L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'text': 'Hc\x04\x82', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347120L, 'RAX': 18446744073709055096L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296958L, 'RBP': 0L}, 'memory': {4793536: '\xc0', 4793537: 'm', 4793538: '\xf8', 4793539: '\xff', 4793540: '\xa0', 4793541: 'm', 4793542: '\xf8', 4793543: '\xff', 4793544: '\x80', 4793545: 'm', 4793546: '\xf8', 4793547: '\xff', 4793548: '`', 4793549: 'm', 4793550: '\xf8', 4793551: '\xff', 4793552: 'x', 4793553: 'l', 4793554: '\xf8', 4793555: '\xff', 4793556: '8', 4793557: 'm', 4793558: '\xf8', 4793559: '\xff', 4296954L: 'H', 4296955L: 'c', 4296956L: '\x04', 4296957L: '\x82', 4793528: 'x', 4793529: 'l', 4793530: '\xf8', 4793531: '\xff', 4793532: 'x', 4793533: 'l', 4793534: '\xf8', 4793535: '\xff'}}, 'disassembly': 'MOVSXD RAX, DWORD [RDX+RAX*4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSXD_9(self):
''' Instruction MOVSXD R14, EDX '''
test = {'mnemonic': 'MOVSXD', 'pre': {'registers': {'RCX': 2L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125321L, 'R14': 0L, 'RSI': 140737488345638L, 'RIP': 4392640L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 4087L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'text': 'Lc\xf2', 'pos': {'registers': {'RCX': 2L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125321L, 'R14': 0L, 'RSI': 140737488345638L, 'RIP': 4392643L, 'EDX': 0L, 'RSP': 140737488344192L, 'RFLAGS': 514L, 'RAX': 4087L}, 'memory': {4392640L: 'L', 4392641L: 'c', 4392642L: '\xf2'}}, 'disassembly': 'MOVSXD R14, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_1(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125687L, 'RSI': 140737354125691L, 'RIP': 4330544L, 'EAX': 68L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 68L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125687L, 'RSI': 140737354125691L, 'RIP': 4330547L, 'EAX': 100L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 100L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_10(self):
''' Instruction MOVSX EAX, AL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 140737488345861L, 'RDX': 5L, 'AL': 48L, 'RBP': 0L, 'RDI': 1L, 'RSI': 0L, 'RIP': 4299451L, 'EAX': 48L, 'RSP': 140737488345728L, 'RFLAGS': 659L, 'RAX': 48L}, 'memory': {4299451L: '\x0f', 4299452L: '\xbe', 4299453L: '\xc0'}}, 'text': '\x0f\xbe\xc0', 'pos': {'registers': {'RCX': 140737488345861L, 'RDX': 5L, 'AL': 48L, 'RBP': 0L, 'RDI': 1L, 'RSI': 0L, 'RIP': 4299454L, 'EAX': 48L, 'RSP': 140737488345728L, 'RFLAGS': 659L, 'RAX': 48L}, 'memory': {4299451L: '\x0f', 4299452L: '\xbe', 4299453L: '\xc0'}}, 'disassembly': 'MOVSX EAX, AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_11(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 7065768L, 'RSI': 4782888L, 'RIP': 4330544L, 'EAX': 68L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 68L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 7065768L, 'RSI': 4782888L, 'RIP': 4330547L, 'EAX': 100L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 100L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_2(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 7065768L, 'RSI': 140737354125650L, 'RIP': 4330544L, 'EAX': 68L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 68L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 7065768L, 'RSI': 140737354125650L, 'RIP': 4330547L, 'EAX': 100L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 100L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_3(self):
''' Instruction MOVSX EDX, DL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'DL': 51L, 'RCX': 18446744073709551615L, 'RDX': 51L, 'RBP': 0L, 'RDI': 0L, 'RSI': 0L, 'RIP': 4299421L, 'EDX': 51L, 'RSP': 140737488345728L, 'RFLAGS': 663L, 'RAX': 46L}, 'memory': {4299421L: '\x0f', 4299422L: '\xbe', 4299423L: '\xd2'}}, 'text': '\x0f\xbe\xd2', 'pos': {'registers': {'DL': 51L, 'RCX': 18446744073709551615L, 'RDX': 51L, 'RBP': 0L, 'RDI': 0L, 'RSI': 0L, 'RIP': 4299424L, 'EDX': 51L, 'RSP': 140737488345728L, 'RFLAGS': 663L, 'RAX': 46L}, 'memory': {4299421L: '\x0f', 4299422L: '\xbe', 4299423L: '\xd2'}}, 'disassembly': 'MOVSX EDX, DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_4(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 115L, 'CL': 115L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125323L, 'RSI': 140737354125325L, 'RIP': 4330544L, 'EAX': 83L, 'RSP': 140737488344256L, 'RFLAGS': 663L, 'RAX': 83L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 115L, 'CL': 115L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125323L, 'RSI': 140737354125325L, 'RIP': 4330547L, 'EAX': 115L, 'RSP': 140737488344256L, 'RFLAGS': 663L, 'RAX': 115L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_5(self):
''' Instruction MOVSX EDX, DL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'DL': 49L, 'RCX': 140737488345859L, 'RDX': 49L, 'RBP': 0L, 'RDI': 1L, 'RSI': 4294967294L, 'RIP': 4299421L, 'EDX': 49L, 'RSP': 140737488345728L, 'RFLAGS': 659L, 'RAX': 48L}, 'memory': {4299421L: '\x0f', 4299422L: '\xbe', 4299423L: '\xd2'}}, 'text': '\x0f\xbe\xd2', 'pos': {'registers': {'DL': 49L, 'RCX': 140737488345859L, 'RDX': 49L, 'RBP': 0L, 'RDI': 1L, 'RSI': 4294967294L, 'RIP': 4299424L, 'EDX': 49L, 'RSP': 140737488345728L, 'RFLAGS': 659L, 'RAX': 48L}, 'memory': {4299421L: '\x0f', 4299422L: '\xbe', 4299423L: '\xd2'}}, 'disassembly': 'MOVSX EDX, DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_6(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125668L, 'RSI': 140737354125680L, 'RIP': 4330544L, 'EAX': 68L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 68L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125668L, 'RSI': 140737354125680L, 'RIP': 4330547L, 'EAX': 100L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 100L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_7(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125681L, 'RSI': 140737354125685L, 'RIP': 4330544L, 'EAX': 68L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 68L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 140737354125681L, 'RSI': 140737354125685L, 'RIP': 4330547L, 'EAX': 100L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 100L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_8(self):
''' Instruction MOVSX EDX, DL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'DL': 53L, 'RCX': 140737488345862L, 'RDX': 53L, 'RBP': 0L, 'RDI': 2L, 'RSI': 4294967294L, 'RIP': 4299421L, 'EDX': 53L, 'RSP': 140737488345728L, 'RFLAGS': 663L, 'RAX': 45L}, 'memory': {4299421L: '\x0f', 4299422L: '\xbe', 4299423L: '\xd2'}}, 'text': '\x0f\xbe\xd2', 'pos': {'registers': {'DL': 53L, 'RCX': 140737488345862L, 'RDX': 53L, 'RBP': 0L, 'RDI': 2L, 'RSI': 4294967294L, 'RIP': 4299424L, 'EDX': 53L, 'RSP': 140737488345728L, 'RFLAGS': 663L, 'RAX': 45L}, 'memory': {4299421L: '\x0f', 4299422L: '\xbe', 4299423L: '\xd2'}}, 'disassembly': 'MOVSX EDX, DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVSX_9(self):
''' Instruction MOVSX EAX, CL '''
test = {'mnemonic': 'MOVSX', 'pre': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 7065768L, 'RSI': 140737354125667L, 'RIP': 4330544L, 'EAX': 68L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 68L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'text': '\x0f\xbe\xc1', 'pos': {'registers': {'RCX': 100L, 'CL': 100L, 'RDX': 140737488345640L, 'RBP': 140737488345936L, 'RDI': 7065768L, 'RSI': 140737354125667L, 'RIP': 4330547L, 'EAX': 100L, 'RSP': 140737488344256L, 'RFLAGS': 659L, 'RAX': 100L}, 'memory': {4330544L: '\x0f', 4330545L: '\xbe', 4330546L: '\xc1'}}, 'disassembly': 'MOVSX EAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_1(self):
''' Instruction MOVZX EAX, BYTE [RCX+RDI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327739L, 'RBP': 140737488345936L}, 'memory': {4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4795883: 'b', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'text': '\x0f\xb6\x049', 'pos': {'registers': {'EAX': 52L, 'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 52L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327743L, 'RBP': 140737488345936L}, 'memory': {4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4795883: 'b', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'disassembly': 'MOVZX EAX, BYTE [RCX+RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_10(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 65L, 'RSI': 140737354125329L, 'ECX': 65L, 'RDI': 140737354125325L, 'RAX': 140737354125326L, 'RSP': 140737488344192L, 'RDX': 4782906L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4782912: 'A', 4782913: 'A', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 83L, 'RSI': 140737354125329L, 'ECX': 83L, 'RDI': 140737354125325L, 'RAX': 140737354125326L, 'RSP': 140737488344192L, 'RDX': 4782906L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4782912: 'A', 4782913: 'A', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_100(self):
''' Instruction MOVZX EDX, BYTE [RAX+RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'EDX': 68L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330560L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796356: '\x0f', 4796357: '\x13', 4796358: '\x13', 4796359: '\x13', 4796360: '\n', 4796361: '\x0f', 4796362: '\x1c', 4796363: '\x00'}}, 'text': '\x0f\xb6\x14\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'EDX': 15L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330564L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796356: '\x0f', 4796357: '\x13', 4796358: '\x13', 4796359: '\x13', 4796360: '\n', 4796361: '\x0f', 4796362: '\x1c', 4796363: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RAX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_101(self):
''' Instruction MOVZX ECX, WORD [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'ECX': 0L, 'RDI': 140737354125394L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244315L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'text': '\x0f\xb7\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782976L, 'ECX': 16705L, 'RDI': 140737354125394L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244318L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'disassembly': 'MOVZX ECX, WORD [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_11(self):
''' Instruction MOVZX EDX, BYTE [R12] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 18446744073709551615L, 'RDX': 0L, 'RBP': 0L, 'RDI': 0L, 'R12': 140737488345858L, 'RSI': 0L, 'RIP': 4299403L, 'EDX': 0L, 'RSP': 140737488345728L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {140737488345858: '3', 140737488345859: '.', 140737488345860: '1', 140737488345861: '0', 140737488345862: '.', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 4299403L: 'A', 4299404L: '\x0f', 4299405L: '\xb6', 4299406L: '\x14', 4299407L: '$'}}, 'text': 'A\x0f\xb6\x14$', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'EDX': 51L, 'RAX': 0L, 'RSP': 140737488345728L, 'RDX': 51L, 'RIP': 4299408L, 'RBP': 0L}, 'memory': {140737488345858: '3', 140737488345859: '.', 140737488345860: '1', 140737488345861: '0', 140737488345862: '.', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 4299403L: 'A', 4299404L: '\x0f', 4299405L: '\xb6', 4299406L: '\x14', 4299407L: '$'}}, 'disassembly': 'MOVZX EDX, BYTE [R12]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_12(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737354125651L, 'ECX': 1L, 'RDI': 140737354125650L, 'RAX': 140737354125650L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {140737488345639: '4', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 140737488345646: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 52L, 'RSI': 140737354125651L, 'ECX': 52L, 'RDI': 140737354125650L, 'RAX': 140737354125650L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {140737488345639: '4', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 140737488345646: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_13(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 32L, 'RSI': 140737354125691L, 'ECX': 32L, 'RDI': 140737354125687L, 'RAX': 140737354125688L, 'RSP': 140737488344192L, 'RDX': 4783043L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 32L, 'RSI': 140737354125691L, 'ECX': 32L, 'RDI': 140737354125687L, 'RAX': 140737354125688L, 'RSP': 140737488344192L, 'RDX': 4783043L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_14(self):
''' Instruction MOVZX EAX, BL '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 8L, 'BL': 118L, 'RDX': 6L, 'RBP': 3L, 'RDI': 140737488345968L, 'RSI': 4792416L, 'RIP': 4283946L, 'EAX': 0L, 'RSP': 140737488345968L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'text': '\x0f\xb6\xc3', 'pos': {'registers': {'RCX': 8L, 'BL': 118L, 'RDX': 6L, 'RBP': 3L, 'RDI': 140737488345968L, 'RSI': 4792416L, 'RIP': 4283949L, 'EAX': 118L, 'RSP': 140737488345968L, 'RFLAGS': 514L, 'RAX': 118L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'disassembly': 'MOVZX EAX, BL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_15(self):
''' Instruction MOVZX ECX, BYTE [RCX+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783020L, 'RSI': 140737354125667L, 'ECX': 4783020L, 'RDI': 7065768L, 'RAX': 4783021L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330270L, 'RBP': 140737488345936L}, 'memory': {4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e'}}, 'text': '\x0f\xb6I\x01', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125667L, 'ECX': 100L, 'RDI': 7065768L, 'RAX': 4783021L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330274L, 'RBP': 140737488345936L}, 'memory': {4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e'}}, 'disassembly': 'MOVZX ECX, BYTE [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_16(self):
''' Instruction MOVZX EDX, AL '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 0L, 'RDX': 13238272L, 'AL': 1L, 'RBP': 188L, 'RDI': 188L, 'RSI': 13L, 'RIP': 4284592L, 'EDX': 13238272L, 'RSP': 140737488346048L, 'RFLAGS': 582L, 'RAX': 1979931137L}, 'memory': {4284592L: '\x0f', 4284593L: '\xb6', 4284594L: '\xd0'}}, 'text': '\x0f\xb6\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 1L, 'AL': 1L, 'RBP': 188L, 'RDI': 188L, 'RSI': 13L, 'RIP': 4284595L, 'EDX': 1L, 'RSP': 140737488346048L, 'RFLAGS': 582L, 'RAX': 1979931137L}, 'memory': {4284592L: '\x0f', 4284593L: '\xb6', 4284594L: '\xd0'}}, 'disassembly': 'MOVZX EDX, AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_17(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792728: 'x', 4792729: '\x08', 4792730: '@', 4792731: '\x06', 4792732: '\x00', 4792733: '\x00', 4792734: '\x10', 4792735: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792728: 'x', 4792729: '\x08', 4792730: '@', 4792731: '\x06', 4792732: '\x00', 4792733: '\x00', 4792734: '\x10', 4792735: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_18(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EDX': 8L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792416: '\x06', 4792417: '\x04', 4792418: ' ', 4792419: '\x00', 4792420: '\x00', 4792421: ' ', 4792422: '\x00', 4792423: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EDX': 6L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792416: '\x06', 4792417: '\x04', 4792418: ' ', 4792419: '\x00', 4792420: '\x00', 4792421: ' ', 4792422: '\x00', 4792423: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_19(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_2(self):
''' Instruction MOVZX R13D, WORD [R15] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 5L, 'RDX': 7L, 'RBP': 140737488347397L, 'RDI': 4793925L, 'R15': 4793925L, 'RSI': 140737488346472L, 'RIP': 4322472L, 'R13D': 7L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4793931: 'N', 4793925: 'L', 4793926: 'D', 4793927: '_', 4793928: 'W', 4793929: 'A', 4793930: 'R', 4322475L: '/', 4793932: '\x00', 4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4322473L: '\x0f', 4322472L: 'E', 4322474L: '\xb7'}}, 'text': 'E\x0f\xb7/', 'pos': {'registers': {'RFLAGS': 518L, 'R13D': 17484L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322476L, 'RBP': 140737488347397L}, 'memory': {4322475L: '/', 4793925: 'L', 4793926: 'D', 4793927: '_', 4793928: 'W', 4793929: 'A', 4793930: 'R', 4793931: 'N', 4793932: '\x00', 4793933: 'L', 4793934: 'D', 4793935: '_', 4793936: 'L', 4793937: 'I', 4793938: 'B', 4793939: 'R', 4793940: 'A', 4322473L: '\x0f', 4322472L: 'E', 4322474L: '\xb7'}}, 'disassembly': 'MOVZX R13D, WORD [R15]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_20(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'EDX': 60L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792480: '"', 4792481: '\x04', 4792482: '@', 4792483: '\t', 4792484: '\x00', 4792485: '\x00', 4792486: '\x08', 4792487: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'EDX': 34L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792480: '"', 4792481: '\x04', 4792482: '@', 4792483: '\t', 4792484: '\x00', 4792485: '\x00', 4792486: '\x08', 4792487: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_21(self):
''' Instruction MOVZX EDX, BYTE [RAX+RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'EDX': 68L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330560L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796356: '\x0f', 4796357: '\x13', 4796358: '\x13', 4796359: '\x13', 4796360: '\n', 4796361: '\x0f', 4796362: '\x1c', 4796363: '\x00'}}, 'text': '\x0f\xb6\x14\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'EDX': 15L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330564L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796356: '\x0f', 4796357: '\x13', 4796358: '\x13', 4796359: '\x13', 4796360: '\n', 4796361: '\x0f', 4796362: '\x1c', 4796363: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RAX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_22(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'EDX': 34L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4792448: '\x0c', 4792449: '\x04', 4792450: ' ', 4792451: '\x03', 4792452: '\x00', 4792453: '@', 4792454: '\x00', 4792455: '\x00', 4283330L: '\x16', 4283329L: '\xb6', 4283328L: '\x0f'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'EDX': 12L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4792448: '\x0c', 4792449: '\x04', 4792450: ' ', 4792451: '\x03', 4792452: '\x00', 4792453: '@', 4792454: '\x00', 4792455: '\x00', 4283330L: '\x16', 4283329L: '\xb6', 4283328L: '\x0f'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_23(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'EDX': 12L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792432: '\t', 4792433: '\x04', 4792434: ' ', 4792435: '\x00', 4792436: '\x00', 4792437: '\x80', 4792438: '\x00', 4792439: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'EDX': 9L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792432: '\t', 4792433: '\x04', 4792434: ' ', 4792435: '\x00', 4792436: '\x00', 4792437: '\x80', 4792438: '\x00', 4792439: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_24(self):
''' Instruction MOVZX EAX, BYTE [RCX+RDI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327739L, 'RBP': 140737488345936L}, 'memory': {4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4795883: 'b', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'text': '\x0f\xb6\x049', 'pos': {'registers': {'EAX': 52L, 'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 52L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327743L, 'RBP': 140737488345936L}, 'memory': {4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4795883: 'b', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'disassembly': 'MOVZX EAX, BYTE [RCX+RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_25(self):
''' Instruction MOVZX R13D, WORD [R15] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 5L, 'RDX': 6L, 'RBP': 140737488347397L, 'RDI': 4793989L, 'R15': 4793989L, 'RSI': 4294967264L, 'RIP': 4322472L, 'R13D': 7L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4793995: 'F', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4322475L: '/', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4322473L: '\x0f', 4322472L: 'E', 4322474L: '\xb7'}}, 'text': 'E\x0f\xb7/', 'pos': {'registers': {'RFLAGS': 518L, 'R13D': 17484L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322476L, 'RBP': 140737488347397L}, 'memory': {4322475L: '/', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4322473L: '\x0f', 4322472L: 'E', 4322474L: '\xb7'}}, 'disassembly': 'MOVZX R13D, WORD [R15]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_26(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'EDX': 9L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792424: '\x08', 4792425: '\x04', 4792426: ' ', 4792427: '\x00', 4792428: '\x00', 4792429: '@', 4792430: '\x00', 4792431: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'EDX': 8L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792424: '\x08', 4792425: '\x04', 4792426: ' ', 4792427: '\x00', 4792428: '\x00', 4792429: '@', 4792430: '\x00', 4792431: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_27(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 83L, 'RSI': 140737354125329L, 'ECX': 83L, 'RDI': 140737354125325L, 'RAX': 140737354125327L, 'RSP': 140737488344192L, 'RDX': 4782907L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 65L, 'RSI': 140737354125329L, 'ECX': 65L, 'RDI': 140737354125325L, 'RAX': 140737354125327L, 'RSP': 140737488344192L, 'RDX': 4782907L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_28(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 46L, 'RSI': 140737354125680L, 'ECX': 46L, 'RDI': 140737354125668L, 'RAX': 140737354125679L, 'RSP': 140737488344192L, 'RDX': 4783033L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783040: '%', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' '}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 32L, 'RSI': 140737354125680L, 'ECX': 32L, 'RDI': 140737354125668L, 'RAX': 140737354125679L, 'RSP': 140737488344192L, 'RDX': 4783033L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783040: '%', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' '}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_29(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 1088L, 'RSI': 140737354125691L, 'ECX': 1088L, 'RDI': 140737354125687L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 4783042L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 32L, 'RSI': 140737354125691L, 'ECX': 32L, 'RDI': 140737354125687L, 'RAX': 140737354125687L, 'RSP': 140737488344192L, 'RDX': 4783042L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_3(self):
''' Instruction MOVZX EDX, BYTE [R12] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 140737488345862L, 'RDX': 10L, 'RBP': 0L, 'RDI': 2L, 'R12': 140737488345863L, 'RSI': 4294967294L, 'RIP': 4299403L, 'EDX': 10L, 'RSP': 140737488345728L, 'RFLAGS': 663L, 'RAX': 46L}, 'memory': {4299404L: '\x0f', 4299403L: 'A', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 140737488345866: 'e', 140737488345867: 'n', 140737488345868: 't', 140737488345869: 'o', 140737488345870: 'o', 4299405L: '\xb6', 4299406L: '\x14', 4299407L: '$'}}, 'text': 'A\x0f\xb6\x14$', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 2L, 'EDX': 53L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 53L, 'RIP': 4299408L, 'RBP': 0L}, 'memory': {140737488345867: 'n', 140737488345868: 't', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 140737488345866: 'e', 4299403L: 'A', 4299404L: '\x0f', 140737488345869: 'o', 140737488345870: 'o', 4299405L: '\xb6', 4299406L: '\x14', 4299407L: '$'}}, 'disassembly': 'MOVZX EDX, BYTE [R12]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_30(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_31(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 115L, 'RSI': 140737354125691L, 'ECX': 115L, 'RDI': 140737354125687L, 'RAX': 140737354125690L, 'RSP': 140737488344192L, 'RDX': 4783045L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125691L, 'ECX': 32L, 'RDI': 140737354125687L, 'RAX': 140737354125690L, 'RSP': 140737488344192L, 'RDX': 4783045L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_32(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_33(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_34(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'EDX': 34L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4792448: '\x0c', 4792449: '\x04', 4792450: ' ', 4792451: '\x03', 4792452: '\x00', 4792453: '@', 4792454: '\x00', 4792455: '\x00', 4283330L: '\x16', 4283329L: '\xb6', 4283328L: '\x0f'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'EDX': 12L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4792448: '\x0c', 4792449: '\x04', 4792450: ' ', 4792451: '\x03', 4792452: '\x00', 4792453: '@', 4792454: '\x00', 4792455: '\x00', 4283330L: '\x16', 4283329L: '\xb6', 4283328L: '\x0f'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_35(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 111L, 'RSI': 140737354125650L, 'ECX': 111L, 'RDI': 140737354125646L, 'RAX': 140737354125648L, 'RSP': 140737488344192L, 'RDX': 4782993L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 116L, 'RSI': 140737354125650L, 'ECX': 116L, 'RDI': 140737354125646L, 'RAX': 140737354125648L, 'RSP': 140737488344192L, 'RDX': 4782993L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_36(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_37(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1L, 'RSI': 140737354125681L, 'ECX': 1L, 'RDI': 140737354125680L, 'RAX': 140737354125680L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {140737488345639: '3', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 140737488345646: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 51L, 'RSI': 140737354125681L, 'ECX': 51L, 'RDI': 140737354125680L, 'RAX': 140737354125680L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {140737488345639: '3', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 140737488345646: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_38(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 116L, 'RSI': 140737354125667L, 'ECX': 116L, 'RDI': 140737354125663L, 'RAX': 140737354125666L, 'RSP': 140737488344192L, 'RDX': 4783019L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783021: 'd', 4783024: 'r', 4783025: 'g', 4783019: ' ', 4783020: '%', 4392690L: '\n', 4783022: ' ', 4783023: 'a', 4392688L: '\x0f', 4392689L: '\xb6', 4783026: 'u'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125667L, 'ECX': 32L, 'RDI': 140737354125663L, 'RAX': 140737354125666L, 'RSP': 140737488344192L, 'RDX': 4783019L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783021: 'd', 4392688L: '\x0f', 4392689L: '\xb6', 4783019: ' ', 4783020: '%', 4392690L: '\n', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_39(self):
''' Instruction MOVZX ECX, BYTE [RCX+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783034L, 'RSI': 140737354125680L, 'ECX': 4783034L, 'RDI': 140737354125668L, 'RAX': 4783035L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330270L, 'RBP': 140737488345936L}, 'memory': {4783040: '%', 4783041: 'd', 4783042: ' ', 4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' '}}, 'text': '\x0f\xb6I\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125680L, 'ECX': 100L, 'RDI': 140737354125668L, 'RAX': 4783035L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330274L, 'RBP': 140737488345936L}, 'memory': {4783040: '%', 4783041: 'd', 4783042: ' ', 4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' '}}, 'disassembly': 'MOVZX ECX, BYTE [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_4(self):
''' Instruction MOVZX ECX, WORD [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'ECX': 0L, 'RDI': 140737354125838L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244315L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'text': '\x0f\xb7\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782976L, 'ECX': 16705L, 'RDI': 140737354125838L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244318L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'disassembly': 'MOVZX ECX, WORD [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_40(self):
''' Instruction MOVZX EAX, BYTE [R12+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 140737488345859L, 'RDX': 49L, 'RBP': 0L, 'RDI': 1L, 'R12': 140737488345860L, 'RSI': 4294967294L, 'RIP': 4299415L, 'EAX': 1L, 'RSP': 140737488345728L, 'RFLAGS': 659L, 'RAX': 1L}, 'memory': {140737488345861: '0', 140737488345862: '.', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 140737488345866: 'e', 140737488345867: 'n', 140737488345868: 't', 4299415L: 'A', 4299416L: '\x0f', 4299417L: '\xb6', 4299418L: 'D', 4299419L: '$', 4299420L: '\x01'}}, 'text': 'A\x0f\xb6D$\x01', 'pos': {'registers': {'EAX': 48L, 'RFLAGS': 659L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 1L, 'RAX': 48L, 'RSP': 140737488345728L, 'RDX': 49L, 'RIP': 4299421L, 'RBP': 0L}, 'memory': {140737488345861: '0', 140737488345862: '.', 140737488345863: '5', 140737488345864: '-', 140737488345865: 'g', 140737488345866: 'e', 140737488345867: 'n', 140737488345868: 't', 4299415L: 'A', 4299416L: '\x0f', 4299417L: '\xb6', 4299418L: 'D', 4299419L: '$', 4299420L: '\x01'}}, 'disassembly': 'MOVZX EAX, BYTE [R12+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_41(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 97L, 'RSI': 140737354125663L, 'ECX': 97L, 'RDI': 140737354125651L, 'RAX': 140737354125653L, 'RSP': 140737488344192L, 'RDX': 4782999L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 114L, 'RSI': 140737354125663L, 'ECX': 114L, 'RDI': 140737354125651L, 'RAX': 140737354125653L, 'RSP': 140737488344192L, 'RDX': 4782999L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_42(self):
''' Instruction MOVZX EDX, BYTE [RAX+RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'EDX': 68L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 68L, 'RIP': 4330560L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796356: '\x0f', 4796357: '\x13', 4796358: '\x13', 4796359: '\x13', 4796360: '\n', 4796361: '\x0f', 4796362: '\x1c', 4796363: '\x00'}}, 'text': '\x0f\xb6\x14\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'EDX': 15L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 15L, 'RIP': 4330564L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796356: '\x0f', 4796357: '\x13', 4796358: '\x13', 4796359: '\x13', 4796360: '\n', 4796361: '\x0f', 4796362: '\x1c', 4796363: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RAX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_43(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'EDX': 60L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792480: '"', 4792481: '\x04', 4792482: '@', 4792483: '\t', 4792484: '\x00', 4792485: '\x00', 4792486: '\x08', 4792487: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'EDX': 34L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792480: '"', 4792481: '\x04', 4792482: '@', 4792483: '\t', 4792484: '\x00', 4792485: '\x00', 4792486: '\x08', 4792487: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_44(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4L, 'RSI': 140737354125667L, 'ECX': 4L, 'RDI': 140737354125663L, 'RAX': 140737354125663L, 'RSP': 140737488344192L, 'RDX': 4783016L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 71L, 'RSI': 140737354125667L, 'ECX': 71L, 'RDI': 140737354125663L, 'RAX': 140737354125663L, 'RSP': 140737488344192L, 'RDX': 4783016L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_45(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_46(self):
''' Instruction MOVZX EAX, AL '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 18446744073709551615L, 'RDX': 18446744073709551615L, 'AL': 1L, 'RBP': 7049504L, 'RDI': 0L, 'RSI': 4294967295L, 'RIP': 4394923L, 'EAX': 513L, 'RSP': 140737488345984L, 'RFLAGS': 582L, 'RAX': 513L}, 'memory': {4394923L: '\x0f', 4394924L: '\xb6', 4394925L: '\xc0'}}, 'text': '\x0f\xb6\xc0', 'pos': {'registers': {'RCX': 18446744073709551615L, 'RDX': 18446744073709551615L, 'AL': 1L, 'RBP': 7049504L, 'RDI': 0L, 'RSI': 4294967295L, 'RIP': 4394926L, 'EAX': 1L, 'RSP': 140737488345984L, 'RFLAGS': 582L, 'RAX': 1L}, 'memory': {4394923L: '\x0f', 4394924L: '\xb6', 4394925L: '\xc0'}}, 'disassembly': 'MOVZX EAX, AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_47(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 114L, 'RSI': 140737354125680L, 'ECX': 114L, 'RDI': 140737354125668L, 'RAX': 140737354125671L, 'RSP': 140737488344192L, 'RDX': 4783025L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783025: 'g', 4783026: 'u', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 103L, 'RSI': 140737354125680L, 'ECX': 103L, 'RDI': 140737354125668L, 'RAX': 140737354125671L, 'RSP': 140737488344192L, 'RDX': 4783025L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392689L: '\xb6', 4392690L: '\n', 4392688L: '\x0f', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_48(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 68L, 'RAX': 90L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 90L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_49(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 109L, 'RSI': 140737354125680L, 'ECX': 109L, 'RDI': 140737354125668L, 'RAX': 140737354125674L, 'RSP': 140737488344192L, 'RDX': 4783028L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 101L, 'RSI': 140737354125680L, 'ECX': 101L, 'RDI': 140737354125668L, 'RAX': 140737354125674L, 'RSP': 140737488344192L, 'RDX': 4783028L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_5(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 109L, 'RSI': 140737354125663L, 'ECX': 109L, 'RDI': 140737354125651L, 'RAX': 140737354125657L, 'RSP': 140737488344192L, 'RDX': 4783003L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 101L, 'RSI': 140737354125663L, 'ECX': 101L, 'RDI': 140737354125651L, 'RAX': 140737354125657L, 'RSP': 140737488344192L, 'RDX': 4783003L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_50(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 116L, 'RSI': 140737354125680L, 'ECX': 116L, 'RDI': 140737354125668L, 'RAX': 140737354125677L, 'RSP': 140737488344192L, 'RDX': 4783031L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 115L, 'RSI': 140737354125680L, 'ECX': 115L, 'RDI': 140737354125668L, 'RAX': 140737354125677L, 'RSP': 140737488344192L, 'RDX': 4783031L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_51(self):
''' Instruction MOVZX EDX, BYTE [R12] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 4782897L, 'RDX': 103L, 'RBP': 7049504L, 'RDI': 140737354125312L, 'R12': 4782891L, 'RSI': 4782888L, 'RIP': 4203520L, 'EDX': 103L, 'RSP': 140737488344144L, 'RFLAGS': 647L, 'RAX': 140737354125315L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782891: 'u', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd'}}, 'text': 'A\x0f\xb6\x14$', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'EDX': 117L, 'RAX': 140737354125315L, 'RSP': 140737488344144L, 'RDX': 117L, 'RIP': 4203525L, 'RBP': 7049504L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782891: 'u', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd'}}, 'disassembly': 'MOVZX EDX, BYTE [R12]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_52(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_53(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 115L, 'RSI': 140737354125663L, 'ECX': 115L, 'RDI': 140737354125651L, 'RAX': 140737354125661L, 'RSP': 140737488344192L, 'RDX': 4783007L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 46L, 'RSI': 140737354125663L, 'ECX': 46L, 'RDI': 140737354125651L, 'RAX': 140737354125661L, 'RSP': 140737488344192L, 'RDX': 4783007L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_54(self):
''' Instruction MOVZX EAX, BL '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 8L, 'BL': 90L, 'RDX': 6L, 'RBP': 3L, 'RDI': 140737488345968L, 'RSI': 4792416L, 'RIP': 4283946L, 'EAX': 0L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'text': '\x0f\xb6\xc3', 'pos': {'registers': {'RCX': 8L, 'BL': 90L, 'RDX': 6L, 'RBP': 3L, 'RDI': 140737488345968L, 'RSI': 4792416L, 'RIP': 4283949L, 'EAX': 90L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 90L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'disassembly': 'MOVZX EAX, BL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_55(self):
''' Instruction MOVZX EAX, BYTE [RCX+RDI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 3L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327739L, 'RBP': 140737488345936L}, 'memory': {4795875: '3', 4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'text': '\x0f\xb6\x049', 'pos': {'registers': {'EAX': 51L, 'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 3L, 'RAX': 51L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327743L, 'RBP': 140737488345936L}, 'memory': {4795875: '3', 4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'disassembly': 'MOVZX EAX, BYTE [RCX+RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_56(self):
''' Instruction MOVZX EAX, BL '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 8L, 'BL': 90L, 'RDX': 6L, 'RBP': 9L, 'RDI': 140737488345968L, 'RSI': 4792416L, 'RIP': 4283946L, 'EAX': 0L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'text': '\x0f\xb6\xc3', 'pos': {'registers': {'RCX': 8L, 'BL': 90L, 'RDX': 6L, 'RBP': 9L, 'RDI': 140737488345968L, 'RSI': 4792416L, 'RIP': 4283949L, 'EAX': 90L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 90L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'disassembly': 'MOVZX EAX, BL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_57(self):
''' Instruction MOVZX ECX, BYTE [RCX+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782901L, 'RSI': 140737354125325L, 'ECX': 4782901L, 'RDI': 140737354125323L, 'RAX': 4782902L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330270L, 'RBP': 140737488345936L}, 'memory': {4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00'}}, 'text': '\x0f\xb6I\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 115L, 'RSI': 140737354125325L, 'ECX': 115L, 'RDI': 140737354125323L, 'RAX': 4782902L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330274L, 'RBP': 140737488345936L}, 'memory': {4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00'}}, 'disassembly': 'MOVZX ECX, BYTE [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_58(self):
''' Instruction MOVZX EDI, WORD [RAX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RAX': 7053712L, 'RDI': 4L, 'EDI': 4L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299694L, 'RBP': 140737488346472L}, 'memory': {7053712: '\x7f', 4299694L: '\x0f', 4299695L: '\xb7', 4299696L: '8', 7053713: '\x03', 7053714: '\x00', 7053715: '\x00', 7053716: '\x08', 7053717: '\x00', 7053718: '\x00', 7053719: '\x00', 7053720: '\x00', 7053721: '\x00', 7053722: '\x00', 7053723: '\x00', 7053724: '\x00', 7053725: '\x00', 7053726: '\x00', 7053727: '\x00'}}, 'text': '\x0f\xb78', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RAX': 7053712L, 'RDI': 895L, 'EDI': 895L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299697L, 'RBP': 140737488346472L}, 'memory': {4299696L: '8', 4299694L: '\x0f', 4299695L: '\xb7', 7053712: '\x7f', 7053713: '\x03', 7053714: '\x00', 7053715: '\x00', 7053716: '\x08', 7053717: '\x00', 7053718: '\x00', 7053719: '\x00', 7053720: '\x00', 7053721: '\x00', 7053722: '\x00', 7053723: '\x00', 7053724: '\x00', 7053725: '\x00', 7053726: '\x00', 7053727: '\x00'}}, 'disassembly': 'MOVZX EDI, WORD [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_59(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 111L, 'RSI': 140737354125667L, 'ECX': 111L, 'RDI': 140737354125663L, 'RAX': 140737354125665L, 'RSP': 140737488344192L, 'RDX': 4783018L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783024: 'r', 4783025: 'g', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 116L, 'RSI': 140737354125667L, 'ECX': 116L, 'RDI': 140737354125663L, 'RAX': 140737354125665L, 'RSP': 140737488344192L, 'RDX': 4783018L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_6(self):
''' Instruction MOVZX EDX, BYTE [R12] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 4782897L, 'RDX': 117L, 'RBP': 7049504L, 'RDI': 140737354125312L, 'R12': 4782892L, 'RSI': 4782888L, 'RIP': 4203520L, 'EDX': 117L, 'RSP': 140737488344144L, 'RFLAGS': 643L, 'RAX': 140737354125316L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':'}}, 'text': 'A\x0f\xb6\x14$', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'EDX': 109L, 'RAX': 140737354125316L, 'RSP': 140737488344144L, 'RDX': 109L, 'RIP': 4203525L, 'RBP': 7049504L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':'}}, 'disassembly': 'MOVZX EDX, BYTE [R12]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_60(self):
''' Instruction MOVZX EAX, BYTE [RCX+RDI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'EAX': 20L, 'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 1L, 'RAX': 20L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327739L, 'RBP': 140737488345936L}, 'memory': {4795873: '1', 4795874: '2', 4795875: '3', 4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'text': '\x0f\xb6\x049', 'pos': {'registers': {'EAX': 49L, 'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 1L, 'RAX': 49L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327743L, 'RBP': 140737488345936L}, 'memory': {4795873: '1', 4795874: '2', 4795875: '3', 4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'disassembly': 'MOVZX EAX, BYTE [RCX+RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_61(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 71L, 'RSI': 140737354125667L, 'ECX': 71L, 'RDI': 140737354125663L, 'RAX': 140737354125664L, 'RSP': 140737488344192L, 'RDX': 4783017L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783024: 'r', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 111L, 'RSI': 140737354125667L, 'ECX': 111L, 'RDI': 140737354125663L, 'RAX': 140737354125664L, 'RSP': 140737488344192L, 'RDX': 4783017L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_62(self):
''' Instruction MOVZX ECX, WORD [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'ECX': 0L, 'RDI': 140737354125917L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244315L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'text': '\x0f\xb7\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782976L, 'ECX': 16705L, 'RDI': 140737354125917L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244318L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'disassembly': 'MOVZX ECX, WORD [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_63(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_64(self):
''' Instruction MOVZX ECX, WORD [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'ECX': 0L, 'RDI': 140737354125996L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244315L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'text': '\x0f\xb7\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782976L, 'ECX': 16705L, 'RDI': 140737354125996L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244318L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'disassembly': 'MOVZX ECX, WORD [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_65(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'EDX': 12L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792432: '\t', 4792433: '\x04', 4792434: ' ', 4792435: '\x00', 4792436: '\x00', 4792437: '\x80', 4792438: '\x00', 4792439: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'EDX': 9L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792432: '\t', 4792433: '\x04', 4792434: ' ', 4792435: '\x00', 4792436: '\x00', 4792437: '\x80', 4792438: '\x00', 4792439: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_66(self):
''' Instruction MOVZX EDX, BYTE [R12] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 4782897L, 'RDX': 65L, 'RBP': 7049504L, 'RDI': 140737354125312L, 'R12': 4782889L, 'RSI': 4782888L, 'RIP': 4203520L, 'EDX': 65L, 'RSP': 140737488344144L, 'RFLAGS': 643L, 'RAX': 140737354125313L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782889: 'r', 4782890: 'g', 4782891: 'u', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' '}}, 'text': 'A\x0f\xb6\x14$', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'EDX': 114L, 'RAX': 140737354125313L, 'RSP': 140737488344144L, 'RDX': 114L, 'RIP': 4203525L, 'RBP': 7049504L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782889: 'r', 4782890: 'g', 4782891: 'u', 4782892: 'm', 4782893: 'e', 4782894: 'n', 4782895: 't', 4782896: ' '}}, 'disassembly': 'MOVZX EDX, BYTE [R12]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_67(self):
''' Instruction MOVZX EDX, BYTE [RAX+RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'EDX': 83L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 83L, 'RIP': 4330560L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796371: '\x15', 4796372: '\x1b', 4796373: '\x10', 4796374: '\x00', 4796375: '\x00', 4796376: '\x12', 4796377: '\x00', 4796378: '\r'}}, 'text': '\x0f\xb6\x14\x10', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'EDX': 21L, 'RAX': 4796288L, 'RSP': 140737488344256L, 'RDX': 21L, 'RIP': 4330564L, 'RBP': 140737488345936L}, 'memory': {4330560L: '\x0f', 4330561L: '\xb6', 4330562L: '\x14', 4330563L: '\x10', 4796371: '\x15', 4796372: '\x1b', 4796373: '\x10', 4796374: '\x00', 4796375: '\x00', 4796376: '\x12', 4796377: '\x00', 4796378: '\r'}}, 'disassembly': 'MOVZX EDX, BYTE [RAX+RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_68(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EDX': 8L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792416: '\x06', 4792417: '\x04', 4792418: ' ', 4792419: '\x00', 4792420: '\x00', 4792421: ' ', 4792422: '\x00', 4792423: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EDX': 6L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792416: '\x06', 4792417: '\x04', 4792418: ' ', 4792419: '\x00', 4792420: '\x00', 4792421: ' ', 4792422: '\x00', 4792423: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_69(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 68L, 'RAX': 90L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 90L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_7(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 52L, 'RSI': 140737354125693L, 'ECX': 52L, 'RDI': 140737354125691L, 'RAX': 140737354125692L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {140737488345639: '4', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 140737488345646: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 52L, 'RSI': 140737354125693L, 'ECX': 52L, 'RDI': 140737354125691L, 'RAX': 140737354125692L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {140737488345639: '4', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 140737488345646: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_70(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792728: 'x', 4792729: '\x08', 4792730: '@', 4792731: '\x06', 4792732: '\x00', 4792733: '\x00', 4792734: '\x10', 4792735: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792728: 'x', 4792729: '\x08', 4792730: '@', 4792731: '\x06', 4792732: '\x00', 4792733: '\x00', 4792734: '\x10', 4792735: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_71(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 115L, 'RSI': 140737354125680L, 'ECX': 115L, 'RDI': 140737354125668L, 'RAX': 140737354125678L, 'RSP': 140737488344192L, 'RDX': 4783032L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' '}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 46L, 'RSI': 140737354125680L, 'ECX': 46L, 'RDI': 140737354125668L, 'RAX': 140737354125678L, 'RSP': 140737488344192L, 'RDX': 4783032L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' '}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_72(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792720: 'h', 4792721: '\x04', 4792722: '@', 4792723: '\x03', 4792724: '\x00', 4792725: '\x80', 4792726: '\x00', 4792727: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'EDX': 104L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792720: 'h', 4792721: '\x04', 4792722: '@', 4792723: '\x03', 4792724: '\x00', 4792725: '\x80', 4792726: '\x00', 4792727: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_73(self):
''' Instruction MOVZX EAX, BL '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 8L, 'BL': 3L, 'RDX': 96L, 'RBP': 9L, 'RDI': 140737488345968L, 'RSI': 4792696L, 'RIP': 4283946L, 'EAX': 0L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'text': '\x0f\xb6\xc3', 'pos': {'registers': {'RCX': 8L, 'BL': 3L, 'RDX': 96L, 'RBP': 9L, 'RDI': 140737488345968L, 'RSI': 4792696L, 'RIP': 4283949L, 'EAX': 3L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 3L}, 'memory': {4283946L: '\x0f', 4283947L: '\xb6', 4283948L: '\xc3'}}, 'disassembly': 'MOVZX EAX, BL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_74(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 68L, 'RAX': 3L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 3L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_75(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 68L, 'RAX': 3L, 'RSP': 140737488345880L, 'RDX': 68L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 3L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792688: 'N', 4792689: '\x18', 4792690: '@', 4792691: '\x06', 4792692: '\x00', 4792693: '\x00', 4792694: '`', 4792695: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_76(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 58L, 'RSI': 140737354125325L, 'ECX': 58L, 'RDI': 140737354125323L, 'RAX': 140737354125324L, 'RSP': 140737488344192L, 'RDX': 4782900L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125325L, 'ECX': 32L, 'RDI': 140737354125323L, 'RAX': 140737354125324L, 'RSP': 140737488344192L, 'RDX': 4782900L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A', 4782906: 'S', 4782907: 'A'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_77(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792712: 'g', 4792713: '\x04', 4792714: '@', 4792715: '\x03', 4792716: '\x00', 4792717: '@', 4792718: '\x00', 4792719: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_78(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 2L, 'RSI': 140737354125687L, 'ECX': 2L, 'RDI': 140737354125685L, 'RAX': 140737354125685L, 'RSP': 140737488344192L, 'RDX': 140737488345638L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {140737488345638: '4', 140737488345639: '3', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 52L, 'RSI': 140737354125687L, 'ECX': 52L, 'RDI': 140737354125685L, 'RAX': 140737354125685L, 'RSP': 140737488344192L, 'RDX': 140737488345638L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {140737488345638: '4', 140737488345639: '3', 140737488345640: '\x00', 140737488345641: '\x00', 140737488345642: '\x00', 140737488345643: '\x00', 140737488345644: '\x00', 140737488345645: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_79(self):
''' Instruction MOVZX EAX, BYTE [RCX+RDI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'EAX': 40L, 'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 40L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327739L, 'RBP': 140737488345936L}, 'memory': {4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4795883: 'b', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'text': '\x0f\xb6\x049', 'pos': {'registers': {'EAX': 52L, 'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 52L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327743L, 'RBP': 140737488345936L}, 'memory': {4795876: '4', 4795877: '5', 4795878: '6', 4795879: '7', 4795880: '8', 4795881: '9', 4795882: 'a', 4795883: 'b', 4327739L: '\x0f', 4327740L: '\xb6', 4327741L: '\x04', 4327742L: '9'}}, 'disassembly': 'MOVZX EAX, BYTE [RCX+RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_8(self):
''' Instruction MOVZX ECX, WORD [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'ECX': 0L, 'RDI': 140737354125552L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244315L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'text': '\x0f\xb7\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782976L, 'ECX': 16705L, 'RDI': 140737354125552L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244318L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'disassembly': 'MOVZX ECX, WORD [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_80(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792552: '<', 4792553: '\x04', 4792554: '@', 4792555: '\x06', 4792556: '\x00', 4792557: '\x00', 4792558: '\x04', 4792559: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'EDX': 60L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792552: '<', 4792553: '\x04', 4792554: '@', 4792555: '\x06', 4792556: '\x00', 4792557: '\x00', 4792558: '\x04', 4792559: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_81(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 32L, 'RSI': 140737354125680L, 'ECX': 32L, 'RDI': 140737354125668L, 'RAX': 140737354125669L, 'RSP': 140737488344192L, 'RDX': 4783023L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783024: 'r', 4783025: 'g', 4783026: 'u', 4783023: 'a', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 97L, 'RSI': 140737354125680L, 'ECX': 97L, 'RDI': 140737354125668L, 'RAX': 140737354125669L, 'RSP': 140737488344192L, 'RDX': 4783023L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_82(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'EDX': 9L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792424: '\x08', 4792425: '\x04', 4792426: ' ', 4792427: '\x00', 4792428: '\x00', 4792429: '@', 4792430: '\x00', 4792431: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'EDX': 8L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792424: '\x08', 4792425: '\x04', 4792426: ' ', 4792427: '\x00', 4792428: '\x00', 4792429: '@', 4792430: '\x00', 4792431: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_83(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_84(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792720: 'h', 4792721: '\x04', 4792722: '@', 4792723: '\x03', 4792724: '\x00', 4792725: '\x80', 4792726: '\x00', 4792727: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'EDX': 104L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792720: 'h', 4792721: '\x04', 4792722: '@', 4792723: '\x03', 4792724: '\x00', 4792725: '\x80', 4792726: '\x00', 4792727: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_85(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 116L, 'RSI': 140737354125663L, 'ECX': 116L, 'RDI': 140737354125651L, 'RAX': 140737354125660L, 'RSP': 140737488344192L, 'RDX': 4783006L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 115L, 'RSI': 140737354125663L, 'ECX': 115L, 'RDI': 140737354125651L, 'RAX': 140737354125660L, 'RSP': 140737488344192L, 'RDX': 4783006L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_86(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792728: 'x', 4792729: '\x08', 4792730: '@', 4792731: '\x06', 4792732: '\x00', 4792733: '\x00', 4792734: '\x10', 4792735: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'EDX': 120L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792728: 'x', 4792729: '\x08', 4792730: '@', 4792731: '\x06', 4792732: '\x00', 4792733: '\x00', 4792734: '\x10', 4792735: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_87(self):
''' Instruction MOVZX ECX, WORD [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782976L, 'ECX': 0L, 'RDI': 140737354125473L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244315L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'text': '\x0f\xb7\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782976L, 'ECX': 16705L, 'RDI': 140737354125473L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244318L, 'RBP': 7049504L}, 'memory': {4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4244315L: '\x0f', 4244316L: '\xb7', 4244317L: '\x0e'}}, 'disassembly': 'MOVZX ECX, WORD [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_88(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'EDX': 103L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4792704: 'f', 4792705: '\x04', 4792706: '@', 4792707: '\x03', 4792708: '\x00', 4792709: ' ', 4792710: '\x00', 4792711: '\x00', 4283330L: '\x16', 4283329L: '\xb6', 4283328L: '\x0f'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'EDX': 102L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4792704: 'f', 4792705: '\x04', 4792706: '@', 4792707: '\x03', 4792708: '\x00', 4792709: ' ', 4792710: '\x00', 4792711: '\x00', 4283330L: '\x16', 4283329L: '\xb6', 4283328L: '\x0f'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_89(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125663L, 'ECX': 32L, 'RDI': 140737354125651L, 'RAX': 140737354125652L, 'RSP': 140737488344192L, 'RDX': 4782998L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 97L, 'RSI': 140737354125663L, 'ECX': 97L, 'RDI': 140737354125651L, 'RAX': 140737354125652L, 'RSP': 140737488344192L, 'RDX': 4782998L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_9(self):
''' Instruction MOVZX EDX, BYTE [R12] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 4782897L, 'RDX': 101L, 'RBP': 7049504L, 'RDI': 140737354125312L, 'R12': 4782894L, 'RSI': 4782888L, 'RIP': 4203520L, 'EDX': 101L, 'RSP': 140737488344144L, 'RFLAGS': 643L, 'RAX': 140737354125318L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%'}}, 'text': 'A\x0f\xb6\x14$', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'EDX': 110L, 'RAX': 140737354125318L, 'RSP': 140737488344144L, 'RDX': 110L, 'RIP': 4203525L, 'RBP': 7049504L}, 'memory': {4203520L: 'A', 4203521L: '\x0f', 4203522L: '\xb6', 4203523L: '\x14', 4203524L: '$', 4782894: 'n', 4782895: 't', 4782896: ' ', 4782897: '%', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%'}}, 'disassembly': 'MOVZX EDX, BYTE [R12]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_90(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'EDX': 9L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792424: '\x08', 4792425: '\x04', 4792426: ' ', 4792427: '\x00', 4792428: '\x00', 4792429: '@', 4792430: '\x00', 4792431: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'EDX': 8L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792424: '\x08', 4792425: '\x04', 4792426: ' ', 4792427: '\x00', 4792428: '\x00', 4792429: '@', 4792430: '\x00', 4792431: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_91(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 78L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792824: '\x86', 4792825: '\x04', 4792826: '@', 4792827: '\x06', 4792828: '\x00', 4792829: '\x00', 4792830: '\x08', 4792831: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_92(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 134L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'EDX': 124L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792760: '|', 4792761: '\x08', 4792762: '@', 4792763: '\x06', 4792764: '\x00', 4792765: '\x00', 4792766: '\x10', 4792767: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_93(self):
''' Instruction MOVZX R13D, WORD [R15] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RCX': 18446744073704757701L, 'RDX': 4L, 'RBP': 140737488347397L, 'RDI': 4793973L, 'R15': 4793973L, 'RSI': 4294967264L, 'RIP': 4322472L, 'R13D': 7L, 'RSP': 140737488346064L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4322472L: 'E', 4322473L: '\x0f', 4322474L: '\xb7', 4322475L: '/', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_'}}, 'text': 'E\x0f\xb7/', 'pos': {'registers': {'RFLAGS': 518L, 'R13D': 17484L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322476L, 'RBP': 140737488347397L}, 'memory': {4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4322472L: 'E', 4322473L: '\x0f', 4322474L: '\xb7', 4322475L: '/', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_'}}, 'disassembly': 'MOVZX R13D, WORD [R15]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_94(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EDX': 102L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792696: '`', 4792697: '\x08', 4792698: '@', 4792699: '\x03', 4792700: '\x00', 4792701: '@', 4792702: '\x00', 4792703: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EDX': 96L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792696: '`', 4792697: '\x08', 4792698: '@', 4792699: '\x03', 4792700: '\x00', 4792701: '@', 4792702: '\x00', 4792703: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_95(self):
''' Instruction MOVZX EDX, BYTE [RSI] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EDX': 102L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283328L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792696: '`', 4792697: '\x08', 4792698: '@', 4792699: '\x03', 4792700: '\x00', 4792701: '@', 4792702: '\x00', 4792703: '\x00'}}, 'text': '\x0f\xb6\x16', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EDX': 96L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283328L: '\x0f', 4283329L: '\xb6', 4283330L: '\x16', 4792696: '`', 4792697: '\x08', 4792698: '@', 4792699: '\x03', 4792700: '\x00', 4792701: '@', 4792702: '\x00', 4792703: '\x00'}}, 'disassembly': 'MOVZX EDX, BYTE [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_96(self):
''' Instruction MOVZX ECX, BYTE [RCX+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782897L, 'RSI': 4782888L, 'ECX': 4782897L, 'RDI': 7065768L, 'RAX': 4782898L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330270L, 'RBP': 140737488345936L}, 'memory': {4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A'}}, 'text': '\x0f\xb6I\x01', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 4782888L, 'ECX': 100L, 'RDI': 7065768L, 'RAX': 4782898L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330274L, 'RBP': 140737488345936L}, 'memory': {4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01', 4782898: 'd', 4782899: ':', 4782900: ' ', 4782901: '%', 4782902: 's', 4782903: '\n', 4782904: '\x00', 4782905: 'A'}}, 'disassembly': 'MOVZX ECX, BYTE [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_97(self):
''' Instruction MOVZX ECX, BYTE [RCX+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783046L, 'RSI': 140737354125691L, 'ECX': 4783046L, 'RDI': 140737354125687L, 'RAX': 4783047L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330270L, 'RBP': 140737488345936L}, 'memory': {4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01'}}, 'text': '\x0f\xb6I\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125691L, 'ECX': 100L, 'RDI': 140737354125687L, 'RAX': 4783047L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330274L, 'RBP': 140737488345936L}, 'memory': {4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01'}}, 'disassembly': 'MOVZX ECX, BYTE [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_98(self):
''' Instruction MOVZX ECX, BYTE [RCX+0x1] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782995L, 'RSI': 140737354125650L, 'ECX': 4782995L, 'RDI': 7065768L, 'RAX': 4782996L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330270L, 'RBP': 140737488345936L}, 'memory': {4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01'}}, 'text': '\x0f\xb6I\x01', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'ECX': 100L, 'RDI': 7065768L, 'RAX': 4782996L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330274L, 'RBP': 140737488345936L}, 'memory': {4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4330270L: '\x0f', 4330271L: '\xb6', 4330272L: 'I', 4330273L: '\x01'}}, 'disassembly': 'MOVZX ECX, BYTE [RCX+0x1]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOVZX_99(self):
''' Instruction MOVZX ECX, BYTE [RDX] '''
test = {'mnemonic': 'MOVZX', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 140737354125695L, 'ECX': 1024L, 'RDI': 140737354125693L, 'RAX': 140737354125693L, 'RSP': 140737488344192L, 'RDX': 4783048L, 'RIP': 4392688L, 'RBP': 7049504L}, 'memory': {4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'text': '\x0f\xb6\n', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 32L, 'RSI': 140737354125695L, 'ECX': 32L, 'RDI': 140737354125693L, 'RAX': 140737354125693L, 'RSP': 140737488344192L, 'RDX': 4783048L, 'RIP': 4392691L, 'RBP': 7049504L}, 'memory': {4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4392688L: '\x0f', 4392689L: '\xb6', 4392690L: '\n'}}, 'disassembly': 'MOVZX ECX, BYTE [RDX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_1(self):
''' Instruction MOV RAX, [RBX+0x40] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 4294967295L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 140737354125312L, 'RIP': 4206061L, 'RBP': 1L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 7049608: '@', 7049609: '\x90', 7049610: 'k', 7049611: '\x00', 7049612: '\x00', 7049613: '\x00', 7049614: '\x00', 7049615: '\x00', 7049616: '\x01', 7049617: '\x00', 7049618: '\x00', 7049619: '\x00', 7049620: '\x00', 7049621: '\x00', 7049622: '\x00', 7049623: '\x00', 7049624: '\xff', 7049625: '\xff', 7049626: '\xff', 7049627: '\xff', 7049628: '\xff', 7049629: '\xff', 7049630: '\xff', 7049631: '\xff', 7049584: '\x00', 7049589: '\x00', 7049583: '\x00', 7049581: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 4206061L: 'H', 4206062L: '\x8b', 4206063L: 'C', 4206064L: '@', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049582: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'text': 'H\x8bC@', 'pos': {'registers': {'RFLAGS': 642L, 'RCX': 0L, 'RSI': 0L, 'RDI': 4294967295L, 'RAX': 140737354129408L, 'RSP': 140737488346112L, 'RDX': 140737354125312L, 'RIP': 4206065L, 'RBP': 1L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 7049608: '@', 7049609: '\x90', 7049610: 'k', 7049611: '\x00', 7049612: '\x00', 7049613: '\x00', 7049614: '\x00', 7049615: '\x00', 7049616: '\x01', 7049617: '\x00', 7049618: '\x00', 7049619: '\x00', 7049620: '\x00', 7049621: '\x00', 7049622: '\x00', 7049623: '\x00', 7049624: '\xff', 7049625: '\xff', 7049626: '\xff', 7049627: '\xff', 7049628: '\xff', 7049629: '\xff', 7049630: '\xff', 7049631: '\xff', 4206064L: '@', 4206061L: 'H', 4206062L: '\x8b', 4206063L: 'C', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'disassembly': 'MOV RAX, [RBX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_10(self):
''' Instruction MOV RCX, [RSP+0x8] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035168L, 'RDI': 7071824L, 'RAX': 7071792L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4197020L, 'RBP': 80L}, 'memory': {4197020L: 'H', 4197021L: '\x8b', 4197022L: 'L', 4197023L: '$', 4197024L: '\x08', 140737488346168: '\x00', 140737488346169: '\xe0', 140737488346170: 'k', 140737488346171: '\x00', 140737488346172: '\x00', 140737488346173: '\x00', 140737488346174: '\x00', 140737488346175: '\x00', 140737488346176: '\xc0', 140737488346177: '\x02', 140737488346178: '@', 140737488346179: '\x00', 140737488346180: '\x00', 140737488346181: '\x00', 140737488346182: '\x00', 140737488346183: '\x00', 140737488346184: '\x90', 140737488346185: '\r', 140737488346186: '@', 140737488346187: '\x00', 140737488346188: '\x00', 140737488346189: '\x00', 140737488346190: '\x00', 140737488346191: '\x00', 140737488346192: '\x00', 140737488346193: '\x00', 140737488346194: '\x00', 140737488346195: '\x00', 140737488346196: '\x00', 140737488346197: '\x00', 140737488346198: '\x00', 140737488346199: '\x00', 140737488346200: '\xf0', 140737488346201: '\x0c', 140737488346202: '@', 140737488346203: '\x00', 140737488346204: '\x00', 140737488346205: '\x00', 140737488346206: '\x00', 140737488346207: '\x00', 140737488346208: '\x00', 140737488346209: '\x00', 140737488346210: '\x00', 140737488346211: '\x00', 140737488346212: '\x00', 140737488346213: '\x00', 140737488346214: '\x00', 140737488346215: '\x00', 140737488346216: '\x00', 140737488346217: '\x00', 140737488346218: '\x00', 140737488346219: '\x00', 140737488346220: '\x00', 140737488346221: '\x00', 140737488346222: '\x00', 140737488346223: '\x00', 140737488346224: '\x00', 140737488346225: '\x00', 140737488346226: '\x00', 140737488346227: '\x00', 140737488346228: '\x00', 140737488346229: '\x00', 140737488346230: '\x00', 140737488346231: '\x00'}}, 'text': 'H\x8bL$\x08', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7069696L, 'RSI': 7035168L, 'RDI': 7071824L, 'RAX': 7071792L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4197025L, 'RBP': 80L}, 'memory': {4197020L: 'H', 4197021L: '\x8b', 4197022L: 'L', 4197023L: '$', 4197024L: '\x08', 140737488346168: '\x00', 140737488346169: '\xe0', 140737488346170: 'k', 140737488346171: '\x00', 140737488346172: '\x00', 140737488346173: '\x00', 140737488346174: '\x00', 140737488346175: '\x00', 140737488346176: '\xc0', 140737488346177: '\x02', 140737488346178: '@', 140737488346179: '\x00', 140737488346180: '\x00', 140737488346181: '\x00', 140737488346182: '\x00', 140737488346183: '\x00', 140737488346184: '\x90', 140737488346185: '\r', 140737488346186: '@', 140737488346187: '\x00', 140737488346188: '\x00', 140737488346189: '\x00', 140737488346190: '\x00', 140737488346191: '\x00', 140737488346192: '\x00', 140737488346193: '\x00', 140737488346194: '\x00', 140737488346195: '\x00', 140737488346196: '\x00', 140737488346197: '\x00', 140737488346198: '\x00', 140737488346199: '\x00', 140737488346200: '\xf0', 140737488346201: '\x0c', 140737488346202: '@', 140737488346203: '\x00', 140737488346204: '\x00', 140737488346205: '\x00', 140737488346206: '\x00', 140737488346207: '\x00', 140737488346208: '\x00', 140737488346209: '\x00', 140737488346210: '\x00', 140737488346211: '\x00', 140737488346212: '\x00', 140737488346213: '\x00', 140737488346214: '\x00', 140737488346215: '\x00', 140737488346216: '\x00', 140737488346217: '\x00', 140737488346218: '\x00', 140737488346219: '\x00', 140737488346220: '\x00', 140737488346221: '\x00', 140737488346222: '\x00', 140737488346223: '\x00', 140737488346224: '\x00', 140737488346225: '\x00', 140737488346226: '\x00', 140737488346227: '\x00', 140737488346228: '\x00', 140737488346229: '\x00', 140737488346230: '\x00', 140737488346231: '\x00'}}, 'disassembly': 'MOV RCX, [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_100(self):
''' Instruction MOV RAX, [RDI] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 7065424L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297034L, 'RBP': 0L}, 'memory': {140737488347008: '\x06', 140737488347009: '\x00', 140737488347010: '\x00', 140737488347011: '\x00', 140737488347012: '\x00', 140737488347013: '\x00', 140737488347014: '\x00', 140737488347015: '\x00', 140737488347016: '\x00', 140737488347017: '\x10', 140737488347018: '\x00', 140737488347019: '\x00', 140737488347020: '\x00', 140737488347021: '\x00', 140737488347022: '\x00', 140737488347023: '\x00', 140737488347024: '\x11', 140737488347025: '\x00', 140737488347026: '\x00', 140737488347027: '\x00', 140737488347028: '\x00', 140737488347029: '\x00', 140737488347030: '\x00', 140737488347031: '\x00', 140737488347032: 'd', 140737488347033: '\x00', 140737488347034: '\x00', 140737488347035: '\x00', 140737488347036: '\x00', 140737488347037: '\x00', 140737488347038: '\x00', 140737488347039: '\x00', 140737488347040: '\x03', 140737488347041: '\x00', 140737488347042: '\x00', 140737488347043: '\x00', 140737488347044: '\x00', 140737488347045: '\x00', 140737488347046: '\x00', 140737488347047: '\x00', 140737488347048: '@', 140737488347049: '\x00', 140737488347050: '@', 140737488347051: '\x00', 140737488347052: '\x00', 140737488347053: '\x00', 140737488347054: '\x00', 140737488347055: '\x00', 4297034L: 'H', 4297035L: '\x8b', 4297036L: '\x07', 140737488346992: '\x10', 140737488346993: '\x00', 140737488346994: '\x00', 140737488346995: '\x00', 140737488346996: '\x00', 140737488346997: '\x00', 140737488346998: '\x00', 140737488346999: '\x00', 140737488347000: '\xff', 140737488347001: '\xfb', 140737488347002: '\xeb', 140737488347003: '\xbf', 140737488347004: '\x00', 140737488347005: '\x00', 140737488347006: '\x00', 140737488347007: '\x00'}}, 'text': 'H\x8b\x07', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346992L, 'RAX': 16L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297037L, 'RBP': 0L}, 'memory': {140737488347008: '\x06', 140737488347009: '\x00', 140737488347010: '\x00', 140737488347011: '\x00', 140737488347012: '\x00', 140737488347013: '\x00', 140737488347014: '\x00', 140737488347015: '\x00', 140737488347016: '\x00', 140737488347017: '\x10', 140737488347018: '\x00', 140737488347019: '\x00', 140737488347020: '\x00', 140737488347021: '\x00', 140737488347022: '\x00', 140737488347023: '\x00', 140737488347024: '\x11', 140737488347025: '\x00', 140737488347026: '\x00', 140737488347027: '\x00', 140737488347028: '\x00', 140737488347029: '\x00', 140737488347030: '\x00', 140737488347031: '\x00', 140737488347032: 'd', 140737488347033: '\x00', 140737488347034: '\x00', 140737488347035: '\x00', 140737488347036: '\x00', 140737488347037: '\x00', 140737488347038: '\x00', 140737488347039: '\x00', 140737488347040: '\x03', 140737488347041: '\x00', 140737488347042: '\x00', 140737488347043: '\x00', 140737488347044: '\x00', 140737488347045: '\x00', 140737488347046: '\x00', 140737488347047: '\x00', 140737488347048: '@', 140737488347049: '\x00', 140737488347050: '@', 140737488347051: '\x00', 140737488347052: '\x00', 140737488347053: '\x00', 140737488347054: '\x00', 140737488347055: '\x00', 4297034L: 'H', 4297035L: '\x8b', 4297036L: '\x07', 140737488346992: '\x10', 140737488346993: '\x00', 140737488346994: '\x00', 140737488346995: '\x00', 140737488346996: '\x00', 140737488346997: '\x00', 140737488346998: '\x00', 140737488346999: '\x00', 140737488347000: '\xff', 140737488347001: '\xfb', 140737488347002: '\xeb', 140737488347003: '\xbf', 140737488347004: '\x00', 140737488347005: '\x00', 140737488347006: '\x00', 140737488347007: '\x00'}}, 'disassembly': 'MOV RAX, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_101(self):
''' Instruction MOV RCX, [RBP-0x538] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336903L, 'RBP': 140737488345936L}, 'memory': {4336903L: 'H', 4336904L: '\x8b', 4336905L: '\x8d', 4336906L: '\xc8', 4336907L: '\xfa', 4336908L: '\xff', 4336909L: '\xff', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\x93', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00'}}, 'text': 'H\x8b\x8d\xc8\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345640L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336910L, 'RBP': 140737488345936L}, 'memory': {4336903L: 'H', 4336904L: '\x8b', 4336905L: '\x8d', 4336906L: '\xc8', 4336907L: '\xfa', 4336908L: '\xff', 4336909L: '\xff', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\x93', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00'}}, 'disassembly': 'MOV RCX, [RBP-0x538]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_11(self):
''' Instruction MOV [RAX+0x10], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052216L, 'RSP': 140737488345712L, 'RDX': 896L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7052288: '\x00', 7052289: '\x00', 7052290: '\x00', 7052291: '\x00', 7052292: '\x00', 7052293: '\x00', 7052294: '\x00', 7052295: '\x00', 7052281: '\x00', 7052280: '\x00', 7052275: '\x00', 7052287: '\x00', 7052232: '\x00', 7052233: '\x00', 7052234: '\x00', 7052235: '\x00', 7052236: '\x00', 7052237: '\x00', 7052238: '\x00', 7052239: '\x00', 7052240: '\xb8', 7052241: '\x9b', 7052242: 'k', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7052247: '\x00', 7052248: '\x00', 7052249: '\x00', 7052250: '\x00', 7052251: '\x00', 7052252: '\x00', 7052253: '\x00', 7052254: '\x00', 7052255: '\x00', 7052256: '\x00', 7052257: '\x00', 7052258: '\x00', 7052259: '\x00', 7052260: '\x00', 7052261: '\x00', 7052262: '\x00', 7052263: '\x00', 7052264: '\x00', 7052265: '\x00', 7052266: '\x00', 7052267: '\x00', 7052268: '\x00', 7052269: '\x00', 7052270: '\x00', 7052271: '\x00', 7052272: '\x00', 7052273: '\x00', 7052274: '\x00', 7052243: '\x00', 7052276: '\x00', 7052277: '\x00', 7052278: '\x00', 7052279: '\x00', 7052246: '\x00', 7052244: '\x00', 7052282: '\x00', 7052283: '\x00', 7052284: '\x00', 7052285: '\x00', 7052286: '\x00', 7052245: '\x00'}}, 'text': 'H\x89@\x10', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052216L, 'RSP': 140737488345712L, 'RDX': 896L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {7052288: '\x00', 7052289: '\x00', 7052290: '\x00', 7052291: '\x00', 7052292: '\x00', 7052293: '\x00', 7052294: '\x00', 7052295: '\x00', 7052243: '\x00', 7052245: '\x00', 7052244: '\x00', 7052246: '\x00', 7052232: '\xb8', 7052233: '\x9b', 7052234: 'k', 7052235: '\x00', 7052236: '\x00', 7052237: '\x00', 7052238: '\x00', 7052239: '\x00', 7052240: '\xb8', 7052241: '\x9b', 7052242: 'k', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7052247: '\x00', 7052248: '\x00', 7052249: '\x00', 7052250: '\x00', 7052251: '\x00', 7052252: '\x00', 7052253: '\x00', 7052254: '\x00', 7052255: '\x00', 7052256: '\x00', 7052257: '\x00', 7052258: '\x00', 7052259: '\x00', 7052260: '\x00', 7052261: '\x00', 7052262: '\x00', 7052263: '\x00', 7052264: '\x00', 7052265: '\x00', 7052266: '\x00', 7052267: '\x00', 7052268: '\x00', 7052269: '\x00', 7052270: '\x00', 7052271: '\x00', 7052272: '\x00', 7052273: '\x00', 7052274: '\x00', 7052275: '\x00', 7052276: '\x00', 7052277: '\x00', 7052278: '\x00', 7052279: '\x00', 7052280: '\x00', 7052281: '\x00', 7052282: '\x00', 7052283: '\x00', 7052284: '\x00', 7052285: '\x00', 7052286: '\x00', 7052287: '\x00'}}, 'disassembly': 'MOV [RAX+0x10], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_12(self):
''' Instruction MOV RDX, 0xcccccccccccccccd '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 1L, 'RSP': 140737488346080L, 'RDX': 7051232L, 'RIP': 4520018L, 'RBP': 140737488346112L}, 'memory': {4520018L: 'H', 4520019L: '\xba', 4520020L: '\xcd', 4520021L: '\xcc', 4520022L: '\xcc', 4520023L: '\xcc', 4520024L: '\xcc', 4520025L: '\xcc', 4520026L: '\xcc', 4520027L: '\xcc'}}, 'text': 'H\xba\xcd\xcc\xcc\xcc\xcc\xcc\xcc\xcc', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 1L, 'RSP': 140737488346080L, 'RDX': 14757395258967641293L, 'RIP': 4520028L, 'RBP': 140737488346112L}, 'memory': {4520018L: 'H', 4520019L: '\xba', 4520020L: '\xcd', 4520021L: '\xcc', 4520022L: '\xcc', 4520023L: '\xcc', 4520024L: '\xcc', 4520025L: '\xcc', 4520026L: '\xcc', 4520027L: '\xcc'}}, 'disassembly': 'MOV RDX, 0xcccccccccccccccd', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_13(self):
''' Instruction MOV R13, RBX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 4L, 'RBX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125646L, 'R13': 4L, 'RSI': 4782991L, 'RIP': 4392635L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3762L}, 'memory': {4392635L: 'I', 4392636L: '\x89', 4392637L: '\xdd'}}, 'text': 'I\x89\xdd', 'pos': {'registers': {'RCX': 4L, 'RBX': 4L, 'RDX': 0L, 'RBP': 7049504L, 'RDI': 140737354125646L, 'R13': 4L, 'RSI': 4782991L, 'RIP': 4392638L, 'RSP': 140737488344192L, 'RFLAGS': 518L, 'RAX': 3762L}, 'memory': {4392635L: 'I', 4392636L: '\x89', 4392637L: '\xdd'}}, 'disassembly': 'MOV R13, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_14(self):
''' Instruction MOV R13, [RSP] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x08', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'text': 'L\x8b,$', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320750L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x08', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'disassembly': 'MOV R13, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_15(self):
''' Instruction MOV RBX, [RBX+0x88] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199170L, 'RBP': 4782912L}, 'memory': {4199170L: 'H', 4199171L: '\x8b', 4199172L: '\x9b', 4199173L: '\x88', 4199174L: '\x00', 4199175L: '\x00', 4199176L: '\x00', 7049640: '\xd0', 7049641: '\xb7', 7049642: 'k', 7049643: '\x00', 7049644: '\x00', 7049645: '\x00', 7049646: '\x00', 7049647: '\x00', 7049648: '\xff', 7049649: '\xff', 7049650: '\xff', 7049651: '\xff', 7049652: '\xff', 7049653: '\xff', 7049654: '\xff', 7049655: '\xff', 7049656: '\x00', 7049657: '\x00', 7049658: '\x00', 7049659: '\x00', 7049660: '\x00', 7049661: '\x00', 7049662: '\x00', 7049663: '\x00', 7049664: '`', 7049665: '\x94', 7049666: 'k', 7049667: '\x00', 7049668: '\x00', 7049669: '\x00', 7049670: '\x00', 7049671: '\x00', 7049672: '\x00', 7049673: '\x00', 7049674: '\x00', 7049675: '\x00', 7049676: '\x00', 7049677: '\x00', 7049678: '\x00', 7049679: '\x00', 7049680: '\x00', 7049681: '\x00', 7049682: '\x00', 7049683: '\x00', 7049684: '\x00', 7049685: '\x00', 7049686: '\x00', 7049687: '\x00', 7049688: '\x00', 7049689: '\x00', 7049690: '\x00', 7049691: '\x00', 7049692: '\x00', 7049693: '\x00', 7049694: '\x00', 7049695: '\x00', 7049696: '\xff', 7049697: '\xff', 7049698: '\xff', 7049699: '\xff', 7049700: '\x00', 7049701: '\x00', 7049702: '\x00', 7049703: '\x00'}}, 'text': 'H\x8b\x9b\x88\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RBX': 7059408L, 'RDI': 7049504L, 'RAX': 7059408L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199177L, 'RBP': 4782912L}, 'memory': {4199170L: 'H', 4199171L: '\x8b', 4199172L: '\x9b', 4199173L: '\x88', 4199174L: '\x00', 4199175L: '\x00', 4199176L: '\x00', 7049640: '\xd0', 7049641: '\xb7', 7049642: 'k', 7049643: '\x00', 7049644: '\x00', 7049645: '\x00', 7049646: '\x00', 7049647: '\x00', 7049648: '\xff', 7049649: '\xff', 7049650: '\xff', 7049651: '\xff', 7049652: '\xff', 7049653: '\xff', 7049654: '\xff', 7049655: '\xff', 7049656: '\x00', 7049657: '\x00', 7049658: '\x00', 7049659: '\x00', 7049660: '\x00', 7049661: '\x00', 7049662: '\x00', 7049663: '\x00', 7049664: '`', 7049665: '\x94', 7049666: 'k', 7049667: '\x00', 7049668: '\x00', 7049669: '\x00', 7049670: '\x00', 7049671: '\x00', 7049672: '\x00', 7049673: '\x00', 7049674: '\x00', 7049675: '\x00', 7049676: '\x00', 7049677: '\x00', 7049678: '\x00', 7049679: '\x00', 7049680: '\x00', 7049681: '\x00', 7049682: '\x00', 7049683: '\x00', 7049684: '\x00', 7049685: '\x00', 7049686: '\x00', 7049687: '\x00', 7049688: '\x00', 7049689: '\x00', 7049690: '\x00', 7049691: '\x00', 7049692: '\x00', 7049693: '\x00', 7049694: '\x00', 7049695: '\x00', 7049696: '\xff', 7049697: '\xff', 7049698: '\xff', 7049699: '\xff', 7049700: '\x00', 7049701: '\x00', 7049702: '\x00', 7049703: '\x00'}}, 'disassembly': 'MOV RBX, [RBX+0x88]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_16(self):
''' Instruction MOV [RAX+0x10], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052392L, 'RSP': 140737488345712L, 'RDX': 1072L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7052416: 'h', 7052417: '\x9c', 7052418: 'k', 7052419: '\x00', 7052420: '\x00', 7052421: '\x00', 7052422: '\x00', 7052423: '\x00', 7052424: '\x00', 7052425: '\x00', 7052426: '\x00', 7052427: '\x00', 7052428: '\x00', 7052429: '\x00', 7052430: '\x00', 7052431: '\x00', 7052432: '\x00', 7052433: '\x00', 7052434: '\x00', 7052435: '\x00', 7052436: '\x00', 7052437: '\x00', 7052438: '\x00', 7052439: '\x00', 7052440: '\x00', 7052441: '\x00', 7052442: '\x00', 7052443: '\x00', 7052444: '\x00', 7052445: '\x00', 7052446: '\x00', 7052447: '\x00', 7052448: '\x00', 7052449: '\x00', 7052450: '\x00', 7052451: '\x00', 7052452: '\x00', 7052453: '\x00', 7052454: '\x00', 7052455: '\x00', 7052456: '\x00', 7052457: '\x00', 7052458: '\x00', 7052459: '\x00', 7052460: '\x00', 7052461: '\x00', 7052462: '\x00', 7052463: '\x00', 7052464: '\x00', 7052465: '\x00', 7052466: '\x00', 7052467: '\x00', 7052468: '\x00', 7052469: '\x00', 7052470: '\x00', 7052471: '\x00', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7052408: '\x00', 7052409: '\x00', 7052410: '\x00', 7052411: '\x00', 7052412: '\x00', 7052413: '\x00', 7052414: '\x00', 7052415: '\x00'}}, 'text': 'H\x89@\x10', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052392L, 'RSP': 140737488345712L, 'RDX': 1072L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {7052416: 'h', 7052417: '\x9c', 7052418: 'k', 7052419: '\x00', 7052420: '\x00', 7052421: '\x00', 7052422: '\x00', 7052423: '\x00', 7052424: '\x00', 7052425: '\x00', 7052426: '\x00', 7052427: '\x00', 7052428: '\x00', 7052429: '\x00', 7052430: '\x00', 7052431: '\x00', 7052432: '\x00', 7052433: '\x00', 7052434: '\x00', 7052435: '\x00', 7052436: '\x00', 7052437: '\x00', 7052438: '\x00', 7052439: '\x00', 7052440: '\x00', 7052441: '\x00', 7052442: '\x00', 7052443: '\x00', 7052444: '\x00', 7052445: '\x00', 7052446: '\x00', 7052447: '\x00', 7052448: '\x00', 7052449: '\x00', 7052450: '\x00', 7052451: '\x00', 7052452: '\x00', 7052453: '\x00', 7052454: '\x00', 7052455: '\x00', 7052456: '\x00', 7052457: '\x00', 7052458: '\x00', 7052459: '\x00', 7052460: '\x00', 7052461: '\x00', 7052462: '\x00', 7052463: '\x00', 7052464: '\x00', 7052465: '\x00', 7052466: '\x00', 7052467: '\x00', 7052468: '\x00', 7052469: '\x00', 7052470: '\x00', 7052471: '\x00', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7052408: 'h', 7052409: '\x9c', 7052410: 'k', 7052411: '\x00', 7052412: '\x00', 7052413: '\x00', 7052414: '\x00', 7052415: '\x00'}}, 'disassembly': 'MOV [RAX+0x10], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_17(self):
''' Instruction MOV R15, RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392488L, 'RBP': 7049504L}, 'memory': {4392488L: 'I', 4392489L: '\x89', 4392490L: '\xf7'}}, 'text': 'I\x89\xf7', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 4782912L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392488L: 'I', 4392489L: '\x89', 4392490L: '\xf7'}}, 'disassembly': 'MOV R15, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_18(self):
''' Instruction MOV RDI, RBX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 1024L, 'RSI': 4783022L, 'RBX': 7049504L, 'RDI': 4783040L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 12L, 'RIP': 4336285L, 'RBP': 140737488345936L}, 'memory': {4336285L: 'H', 4336286L: '\x89', 4336287L: '\xdf'}}, 'text': 'H\x89\xdf', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 1024L, 'RSI': 4783022L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344256L, 'RDX': 12L, 'RIP': 4336288L, 'RBP': 140737488345936L}, 'memory': {4336285L: 'H', 4336286L: '\x89', 4336287L: '\xdf'}}, 'disassembly': 'MOV RDI, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_19(self):
''' Instruction MOV RDX, R12 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'R12': 140737488346512L, 'RAX': 6L, 'RSP': 140737488346208L, 'RDX': 4L, 'RIP': 4299741L, 'RBP': 140737488346472L}, 'memory': {4299741L: 'L', 4299742L: '\x89', 4299743L: '\xe2'}}, 'text': 'L\x89\xe2', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'R12': 140737488346512L, 'RAX': 6L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299744L, 'RBP': 140737488346472L}, 'memory': {4299741L: 'L', 4299742L: '\x89', 4299743L: '\xe2'}}, 'disassembly': 'MOV RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_2(self):
''' Instruction MOV RSI, R15 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 4792448L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320771L: 'L', 4320772L: '\x89', 4320773L: '\xfe'}}, 'text': 'L\x89\xfe', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792448L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320771L: 'L', 4320772L: '\x89', 4320773L: '\xfe'}}, 'disassembly': 'MOV RSI, R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_20(self):
''' Instruction MOV EAX, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 4782904L, 'RBX': 7049504L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737354125330L, 'RIP': 4329925L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4329925L: '\x8b', 4329926L: '\x03', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'text': '\x8b\x03', 'pos': {'registers': {'EAX': 4222429316L, 'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 4222429316L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4329927L, 'RBP': 140737488345936L}, 'memory': {4329925L: '\x8b', 4329926L: '\x03', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'MOV EAX, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_21(self):
''' Instruction MOV EAX, [RCX+0x4] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199142L, 'RBP': 4782912L}, 'memory': {7059435: '\x00', 7059412: '\x01', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x80', 7059417: '\xe8', 7059418: 'k', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 4199142L: '\x8b', 4199143L: 'A', 4199144L: '\x04', 7059433: '\x00', 7059434: '\x00', 7059431: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 7059440: '\x00', 7059432: '\x00', 7059442: '\x00', 7059443: '\x00', 7059430: '\x00', 7059441: '\x00'}}, 'text': '\x8bA\x04', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 1L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199145L, 'RBP': 4782912L}, 'memory': {4199142L: '\x8b', 7059412: '\x01', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x80', 7059417: '\xe8', 7059418: 'k', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 4199143L: 'A', 4199144L: '\x04', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 7059440: '\x00', 7059441: '\x00', 7059442: '\x00', 7059443: '\x00', 7059432: '\x00', 7059431: '\x00'}}, 'disassembly': 'MOV EAX, [RCX+0x4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_22(self):
''' Instruction MOV [RSP-0x28], RBP '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392437L, 'RBP': 4782912L}, 'memory': {140737488346112: '\x90', 140737488346113: '\xdd', 140737488346114: '\xff', 140737488346115: '\xff', 140737488346116: '\xff', 140737488346117: '\x7f', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xc5', 140737488346121: '\x12', 140737488346122: '@', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: ' ', 140737488346129: 'Y', 140737488346130: 'k', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: '\x90', 140737488346137: '\r', 140737488346138: '@', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: 'h', 140737488346105: '\xdd', 140737488346080: 'h', 140737488346081: '\xdd', 140737488346082: '\xff', 140737488346083: '\xff', 140737488346084: '\xff', 140737488346085: '\x7f', 140737488346086: '\x00', 140737488346087: '\x00', 140737488346088: '`', 140737488346089: '\xd0', 140737488346090: 'k', 140737488346091: '\x00', 140737488346092: '\x00', 140737488346093: '\x00', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x00', 140737488346097: '\x80', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 4392437L: 'H', 4392438L: '\x89', 4392439L: 'l', 4392440L: '$', 4392441L: '\xd8', 140737488346106: '\xff', 140737488346107: '\xff', 140737488346108: '\xff', 140737488346109: '\x7f', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'text': 'H\x89l$\xd8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392442L, 'RBP': 4782912L}, 'memory': {140737488346112: '\x90', 140737488346113: '\xdd', 140737488346114: '\xff', 140737488346115: '\xff', 140737488346116: '\xff', 140737488346117: '\x7f', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xc5', 140737488346121: '\x12', 140737488346122: '@', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: ' ', 140737488346129: 'Y', 140737488346130: 'k', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: '\x90', 140737488346137: '\r', 140737488346138: '@', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 4392437L: 'H', 4392438L: '\x89', 4392439L: 'l', 4392440L: '$', 4392441L: '\xd8', 140737488346080: '@', 140737488346081: '\xfb', 140737488346082: 'H', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00', 140737488346088: '`', 140737488346089: '\xd0', 140737488346090: 'k', 140737488346091: '\x00', 140737488346092: '\x00', 140737488346093: '\x00', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x00', 140737488346097: '\x80', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: 'h', 140737488346105: '\xdd', 140737488346106: '\xff', 140737488346107: '\xff', 140737488346108: '\xff', 140737488346109: '\x7f', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'disassembly': 'MOV [RSP-0x28], RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_23(self):
''' Instruction MOV [RAX+0x18], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051416L, 'RSP': 140737488345712L, 'RDX': 96L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {7051499: '\x00', 7051501: '\x00', 7051440: '\x00', 7051441: '\x00', 7051442: '\x00', 7051443: '\x00', 7051444: '\x00', 7051445: '\x00', 7051446: '\x00', 7051447: '\x00', 7051448: '\x00', 7051449: '\x00', 7051450: '\x00', 7051451: '\x00', 7051452: '\x00', 7051453: '\x00', 7051454: '\x00', 7051455: '\x00', 7051456: '\x00', 7051457: '\x00', 7051458: '\x00', 7051459: '\x00', 7051460: '\x00', 7051461: '\x00', 7051462: '\x00', 7051463: '\x00', 7051464: '\x00', 7051465: '\x00', 7051466: '\x00', 7051467: '\x00', 7051468: '\x00', 7051469: '\x00', 7051470: '\x00', 7051471: '\x00', 7051472: '\x00', 4211153L: '@', 4211154L: '\x18', 7051475: '\x00', 7051476: '\x00', 7051477: '\x00', 7051478: '\x00', 7051479: '\x00', 7051480: '\x00', 7051481: '\x00', 7051482: '\x00', 7051483: '\x00', 7051484: '\x00', 7051485: '\x00', 7051486: '\x00', 7051487: '\x00', 7051488: '\x00', 7051489: '\x00', 7051490: '\x00', 7051491: '\x00', 7051492: '\x00', 7051493: '\x00', 7051494: '\x00', 7051473: '\x00', 7051496: '\x00', 7051497: '\x00', 7051498: '\x00', 7051495: '\x00', 7051500: '\x00', 7051474: '\x00', 7051502: '\x00', 7051503: '\x00', 4211152L: '\x89', 4211151L: 'H'}}, 'text': 'H\x89@\x18', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051416L, 'RSP': 140737488345712L, 'RDX': 96L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7051473: '\x00', 7051503: '\x00', 7051483: '\x00', 7051489: '\x00', 7051440: '\x98', 7051441: '\x98', 7051442: 'k', 7051443: '\x00', 7051444: '\x00', 7051445: '\x00', 7051446: '\x00', 7051447: '\x00', 7051448: '\x00', 7051449: '\x00', 7051450: '\x00', 7051451: '\x00', 7051452: '\x00', 7051453: '\x00', 7051454: '\x00', 7051455: '\x00', 7051456: '\x00', 7051457: '\x00', 7051458: '\x00', 7051459: '\x00', 7051460: '\x00', 7051461: '\x00', 7051462: '\x00', 7051463: '\x00', 7051464: '\x00', 7051465: '\x00', 7051466: '\x00', 7051467: '\x00', 7051468: '\x00', 7051469: '\x00', 7051470: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7051475: '\x00', 7051476: '\x00', 7051477: '\x00', 7051478: '\x00', 7051479: '\x00', 7051480: '\x00', 7051481: '\x00', 7051482: '\x00', 7051471: '\x00', 7051484: '\x00', 7051485: '\x00', 7051486: '\x00', 7051487: '\x00', 7051488: '\x00', 7051472: '\x00', 7051490: '\x00', 7051491: '\x00', 7051492: '\x00', 7051493: '\x00', 7051494: '\x00', 7051495: '\x00', 7051496: '\x00', 7051497: '\x00', 7051498: '\x00', 7051499: '\x00', 7051500: '\x00', 7051501: '\x00', 7051502: '\x00', 7051474: '\x00'}}, 'disassembly': 'MOV [RAX+0x18], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_24(self):
''' Instruction MOV RCX, [RBP-0x530] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782995L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 7066112L, 'RSP': 140737488344256L, 'RDX': 4782995L, 'RIP': 4330203L, 'RBP': 140737488345936L}, 'memory': {140737488344669: '\x00', 140737488344608: '\x93', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 140737488344664: '\x00', 140737488344665: '\x00', 140737488344666: '\x00', 140737488344667: '\x00', 140737488344668: '\x00', 4330205L: '\x8d', 140737488344670: '\x00', 140737488344671: '\x00', 4330208L: '\xff', 4330207L: '\xfa', 4330203L: 'H', 4330204L: '\x8b', 4330206L: '\xd0', 4330209L: '\xff'}}, 'text': 'H\x8b\x8d\xd0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782995L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 7066112L, 'RSP': 140737488344256L, 'RDX': 4782995L, 'RIP': 4330210L, 'RBP': 140737488345936L}, 'memory': {4330205L: '\x8d', 140737488344608: '\x93', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 140737488344664: '\x00', 140737488344665: '\x00', 140737488344666: '\x00', 140737488344667: '\x00', 140737488344668: '\x00', 140737488344669: '\x00', 140737488344670: '\x00', 140737488344671: '\x00', 4330208L: '\xff', 4330207L: '\xfa', 4330203L: 'H', 4330204L: '\x8b', 4330206L: '\xd0', 4330209L: '\xff'}}, 'disassembly': 'MOV RCX, [RBP-0x530]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_25(self):
''' Instruction MOV RSI, RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 535L, 'RCX': 18446744073709551615L, 'RSI': 4096L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343968L, 'RDX': 3L, 'RIP': 4661238L, 'RBP': 4096L}, 'memory': {4661240L: '\xc6', 4661238L: 'H', 4661239L: '\x89'}}, 'text': 'H\x89\xc6', 'pos': {'registers': {'RFLAGS': 535L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343968L, 'RDX': 3L, 'RIP': 4661241L, 'RBP': 4096L}, 'memory': {4661240L: '\xc6', 4661238L: 'H', 4661239L: '\x89'}}, 'disassembly': 'MOV RSI, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_26(self):
''' Instruction MOV R15, RDX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283762L, 'RBP': 188L}, 'memory': {4283762L: 'I', 4283763L: '\x89', 4283764L: '\xd7'}}, 'text': 'I\x89\xd7', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 140737488346078L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283765L, 'RBP': 188L}, 'memory': {4283762L: 'I', 4283763L: '\x89', 4283764L: '\xd7'}}, 'disassembly': 'MOV R15, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_27(self):
''' Instruction MOV ESI, 0xffffffffffffffff '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4782888L, 'ESI': 4782888L, 'RDI': 0L, 'RAX': 7041664L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392530L, 'RBP': 7049504L}, 'memory': {4392530L: '\xbe', 4392531L: '\xff', 4392532L: '\xff', 4392533L: '\xff', 4392534L: '\xff'}}, 'text': '\xbe\xff\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 0L, 'RAX': 7041664L, 'RSP': 140737488344192L, 'RDX': 9L, 'RIP': 4392535L, 'RBP': 7049504L}, 'memory': {4392530L: '\xbe', 4392531L: '\xff', 4392532L: '\xff', 4392533L: '\xff', 4392534L: '\xff'}}, 'disassembly': 'MOV ESI, 0xffffffffffffffff', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_28(self):
''' Instruction MOV [RSP+0x48], R9 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 43L, 'RSI': 4783016L, 'RAX': 4198854L, 'RDI': 4783016L, 'RBP': 140737488346224L, 'RSP': 140737488345952L, 'R9': 4783009L, 'RIP': 4198807L, 'RDX': 140737488346159L}, 'memory': {4198807L: 'L', 4198808L: '\x89', 4198809L: 'L', 4198810L: '$', 4198811L: 'H', 140737488346024: 'A', 140737488346025: 'A', 140737488346026: 'A', 140737488346027: 'A', 140737488346028: 'A', 140737488346029: 'A', 140737488346030: 'A', 140737488346031: 'A', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00', 140737488346040: 'r', 140737488346041: '`', 140737488346042: 'A', 140737488346043: '\x00', 140737488346044: '\x00', 140737488346045: '\x00', 140737488346046: '\x00', 140737488346047: '\x00', 140737488346048: '\x00', 140737488346049: '\xdc', 140737488346050: '\xff', 140737488346051: '\xff', 140737488346052: '\xff', 140737488346053: '\x7f', 140737488346054: '\x00', 140737488346055: '\x00', 140737488346056: '\xb7', 140737488346057: '\x07', 140737488346058: 'C', 140737488346059: '\x00', 140737488346060: '\x00', 140737488346061: '\x00', 140737488346062: '\x00', 140737488346063: '\x00', 140737488346064: '\n', 140737488346065: '\x00', 140737488346066: '\x00', 140737488346067: '\x00', 140737488346068: '\x00', 140737488346069: '\x00', 140737488346070: '\x00', 140737488346071: '\x00', 140737488346072: ' ', 140737488346073: '\x91', 140737488346074: 'k', 140737488346075: '\x00', 140737488346076: '\x00', 140737488346077: '\x00', 140737488346078: '\x00', 140737488346079: '\x00', 140737488346080: '@', 140737488346081: '\xfb', 140737488346082: 'H', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00'}}, 'text': 'L\x89L$H', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 43L, 'RSI': 4783016L, 'RAX': 4198854L, 'RDI': 4783016L, 'RBP': 140737488346224L, 'RSP': 140737488345952L, 'R9': 4783009L, 'RIP': 4198812L, 'RDX': 140737488346159L}, 'memory': {4198807L: 'L', 4198808L: '\x89', 4198809L: 'L', 4198810L: '$', 4198811L: 'H', 140737488346024: '\xa1', 140737488346025: '\xfb', 140737488346026: 'H', 140737488346027: '\x00', 140737488346028: '\x00', 140737488346029: '\x00', 140737488346030: '\x00', 140737488346031: '\x00', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00', 140737488346040: 'r', 140737488346041: '`', 140737488346042: 'A', 140737488346043: '\x00', 140737488346044: '\x00', 140737488346045: '\x00', 140737488346046: '\x00', 140737488346047: '\x00', 140737488346048: '\x00', 140737488346049: '\xdc', 140737488346050: '\xff', 140737488346051: '\xff', 140737488346052: '\xff', 140737488346053: '\x7f', 140737488346054: '\x00', 140737488346055: '\x00', 140737488346056: '\xb7', 140737488346057: '\x07', 140737488346058: 'C', 140737488346059: '\x00', 140737488346060: '\x00', 140737488346061: '\x00', 140737488346062: '\x00', 140737488346063: '\x00', 140737488346064: '\n', 140737488346065: '\x00', 140737488346066: '\x00', 140737488346067: '\x00', 140737488346068: '\x00', 140737488346069: '\x00', 140737488346070: '\x00', 140737488346071: '\x00', 140737488346072: ' ', 140737488346073: '\x91', 140737488346074: 'k', 140737488346075: '\x00', 140737488346076: '\x00', 140737488346077: '\x00', 140737488346078: '\x00', 140737488346079: '\x00', 140737488346080: '@', 140737488346081: '\xfb', 140737488346082: 'H', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00'}}, 'disassembly': 'MOV [RSP+0x48], R9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_29(self):
''' Instruction MOV [RAX], CL '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 52L, 'RSI': 140737354125693L, 'CL': 52L, 'RDI': 140737354125691L, 'RAX': 140737354125691L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392695L, 'RBP': 7049504L}, 'memory': {140737354125696: '\x00', 140737354125697: '\x00', 140737354125698: '\x00', 4392695L: '\x88', 4392696L: '\x08', 140737354125691: '\x00', 140737354125692: '\x00', 140737354125693: '\x00', 140737354125694: '\x00', 140737354125695: '\x00'}}, 'text': '\x88\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 52L, 'RSI': 140737354125693L, 'CL': 52L, 'RDI': 140737354125691L, 'RAX': 140737354125691L, 'RSP': 140737488344192L, 'RDX': 140737488345639L, 'RIP': 4392697L, 'RBP': 7049504L}, 'memory': {140737354125696: '\x00', 140737354125697: '\x00', 140737354125698: '\x00', 4392695L: '\x88', 4392696L: '\x08', 140737354125691: '4', 140737354125692: '\x00', 140737354125693: '\x00', 140737354125694: '\x00', 140737354125695: '\x00'}}, 'disassembly': 'MOV [RAX], CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_3(self):
''' Instruction MOV RBP, RDI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 32L, 'RSP': 140737488346168L, 'RDX': 7059408L, 'RIP': 4198938L, 'RBP': 140737488346224L}, 'memory': {4198938L: 'H', 4198939L: '\x89', 4198940L: '\xfd'}}, 'text': 'H\x89\xfd', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 32L, 'RSP': 140737488346168L, 'RDX': 7059408L, 'RIP': 4198941L, 'RBP': 4782912L}, 'memory': {4198938L: 'H', 4198939L: '\x89', 4198940L: '\xfd'}}, 'disassembly': 'MOV RBP, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_30(self):
''' Instruction MOV [RSP-0x18], R13 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'R13': 7051024L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392449L, 'RBP': 4782912L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xc5', 140737488346121: '\x12', 140737488346122: '@', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: ' ', 140737488346129: 'Y', 140737488346130: 'k', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: '\x90', 140737488346137: '\r', 140737488346138: '@', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346144: 'p', 140737488346145: '\xdc', 140737488346146: '\xff', 140737488346147: '\xff', 140737488346148: '\xff', 140737488346149: '\x7f', 140737488346150: '\x00', 140737488346151: '\x00', 140737488346152: '\xf0', 140737488346153: '\x0c', 140737488346154: '@', 140737488346155: '\x00', 140737488346156: '\x00', 140737488346157: '\x00', 140737488346158: '\x00', 140737488346159: '\x00', 140737488346098: 'k', 4392453L: '\xe8', 4392452L: '$', 4392449L: 'L', 4392451L: 'l', 140737488346096: '\x10', 140737488346097: '\x97', 4392450L: '\x89', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'text': 'L\x89l$\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'R13': 7051024L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392454L, 'RBP': 4782912L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xc5', 140737488346121: '\x12', 140737488346122: '@', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: ' ', 140737488346129: 'Y', 140737488346130: 'k', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: '\x90', 140737488346137: '\r', 140737488346138: '@', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346144: 'p', 140737488346145: '\xdc', 140737488346146: '\xff', 140737488346147: '\xff', 140737488346148: '\xff', 140737488346149: '\x7f', 140737488346150: '\x00', 140737488346151: '\x00', 140737488346152: '\xf0', 140737488346153: '\x0c', 140737488346154: '@', 140737488346155: '\x00', 140737488346156: '\x00', 140737488346157: '\x00', 140737488346158: '\x00', 140737488346159: '\x00', 140737488346098: 'k', 4392453L: '\xe8', 4392452L: '$', 4392449L: 'L', 4392451L: 'l', 140737488346096: '\x10', 140737488346097: '\x97', 4392450L: '\x89', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'disassembly': 'MOV [RSP-0x18], R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_31(self):
''' Instruction MOV R8, [RBP-0x680] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 140737354125663L, 'RDI': 140737354125651L, 'R8': 140737354125663L, 'RAX': 12L, 'RSP': 140737488344256L, 'RDX': 4783009L, 'RIP': 4336291L, 'RBP': 140737488345936L}, 'memory': {140737488344320: '\x00', 140737488344321: '\x00', 140737488344322: '\x00', 140737488344323: '\x00', 140737488344324: '\x00', 140737488344325: '\x00', 140737488344326: '\x00', 140737488344327: '\x00', 140737488344328: '\x00', 140737488344329: '\x00', 140737488344330: '\x00', 140737488344331: '\x00', 140737488344332: '\x00', 140737488344333: '\x00', 140737488344334: '\x00', 140737488344335: '\x00', 4336291L: 'L', 4336292L: '\x8b', 4336293L: '\x85', 4336294L: '\x80', 4336295L: '\xf9', 4336296L: '\xff', 4336297L: '\xff', 140737488344272: '\x0c', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 140737488344280: '\x00', 140737488344281: '\x00', 140737488344282: '\x00', 140737488344283: '\x00', 140737488344284: '\x00', 140737488344285: '\x00', 140737488344286: '\x00', 140737488344287: '\x00', 140737488344288: '\xa1', 140737488344289: '\xfb', 140737488344290: 'H', 140737488344291: '\x00', 140737488344292: '\x00', 140737488344293: '\x00', 140737488344294: '\x00', 140737488344295: '\x00', 140737488344296: '\x95', 140737488344297: '\xfb', 140737488344298: 'H', 140737488344299: '\x00', 140737488344300: '\x00', 140737488344301: '\x00', 140737488344302: '\x00', 140737488344303: '\x00', 140737488344304: '\x00', 140737488344305: '\x00', 140737488344306: '\x00', 140737488344307: '\x00', 140737488344308: '\x00', 140737488344309: '\x00', 140737488344310: '\x00', 140737488344311: '\x00', 140737488344312: '\x00', 140737488344313: '\x00', 140737488344314: '\x00', 140737488344315: '\x00', 140737488344316: '\x00', 140737488344317: '\x00', 140737488344318: '\x00', 140737488344319: '\x00'}}, 'text': 'L\x8b\x85\x80\xf9\xff\xff', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 140737354125663L, 'RDI': 140737354125651L, 'R8': 12L, 'RAX': 12L, 'RSP': 140737488344256L, 'RDX': 4783009L, 'RIP': 4336298L, 'RBP': 140737488345936L}, 'memory': {140737488344320: '\x00', 140737488344321: '\x00', 140737488344322: '\x00', 140737488344323: '\x00', 140737488344324: '\x00', 140737488344325: '\x00', 140737488344326: '\x00', 140737488344327: '\x00', 140737488344328: '\x00', 140737488344329: '\x00', 140737488344330: '\x00', 140737488344331: '\x00', 140737488344332: '\x00', 140737488344333: '\x00', 140737488344334: '\x00', 140737488344335: '\x00', 4336291L: 'L', 4336292L: '\x8b', 4336293L: '\x85', 4336294L: '\x80', 4336295L: '\xf9', 4336296L: '\xff', 4336297L: '\xff', 140737488344272: '\x0c', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 140737488344280: '\x00', 140737488344281: '\x00', 140737488344282: '\x00', 140737488344283: '\x00', 140737488344284: '\x00', 140737488344285: '\x00', 140737488344286: '\x00', 140737488344287: '\x00', 140737488344288: '\xa1', 140737488344289: '\xfb', 140737488344290: 'H', 140737488344291: '\x00', 140737488344292: '\x00', 140737488344293: '\x00', 140737488344294: '\x00', 140737488344295: '\x00', 140737488344296: '\x95', 140737488344297: '\xfb', 140737488344298: 'H', 140737488344299: '\x00', 140737488344300: '\x00', 140737488344301: '\x00', 140737488344302: '\x00', 140737488344303: '\x00', 140737488344304: '\x00', 140737488344305: '\x00', 140737488344306: '\x00', 140737488344307: '\x00', 140737488344308: '\x00', 140737488344309: '\x00', 140737488344310: '\x00', 140737488344311: '\x00', 140737488344312: '\x00', 140737488344313: '\x00', 140737488344314: '\x00', 140737488344315: '\x00', 140737488344316: '\x00', 140737488344317: '\x00', 140737488344318: '\x00', 140737488344319: '\x00'}}, 'disassembly': 'MOV R8, [RBP-0x680]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_32(self):
''' Instruction MOV RDI, RSP '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283903L, 'RBP': 3L}, 'memory': {4283904L: '\x89', 4283905L: '\xe7', 4283903L: 'H'}}, 'text': 'H\x89\xe7', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283906L, 'RBP': 3L}, 'memory': {4283904L: '\x89', 4283905L: '\xe7', 4283903L: 'H'}}, 'disassembly': 'MOV RDI, RSP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_33(self):
''' Instruction MOV RSI, [RBP-0x538] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337450L, 'RBP': 140737488345936L}, 'memory': {140737488344619: '\x00', 140737488344620: '\x00', 140737488344663: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '1', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 4337451L: '\x8b', 4337452L: '\xb5', 4337453L: '\xc8', 4337454L: '\xfa', 4337455L: '\xff', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344623: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344633: '\x00', 4337456L: '\xff', 4337450L: 'H'}}, 'text': 'H\x8b\xb5\xc8\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337457L, 'RBP': 140737488345936L}, 'memory': {4337451L: '\x8b', 4337452L: '\xb5', 4337453L: '\xc8', 4337454L: '\xfa', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '1', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 4337455L: '\xff', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344623: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 140737488344633: '\x00', 4337456L: '\xff', 4337450L: 'H'}}, 'disassembly': 'MOV RSI, [RBP-0x538]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_34(self):
''' Instruction MOV ECX, [RSI] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 16705L, 'RSI': 4782978L, 'ECX': 16705L, 'RDI': 140737354125998L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244334L, 'RBP': 7049504L}, 'memory': {4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4244334L: '\x8b', 4244335L: '\x0e'}}, 'text': '\x8b\x0e', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1094795585L, 'RSI': 4782978L, 'ECX': 1094795585L, 'RDI': 140737354125998L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244336L, 'RBP': 7049504L}, 'memory': {4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4244334L: '\x8b', 4244335L: '\x0e'}}, 'disassembly': 'MOV ECX, [RSI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_35(self):
''' Instruction MOV [RSP], R13 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320816L, 'RBP': 4792416L}, 'memory': {140737488345905: '\x06', 140737488345888: 'D', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 4320816L: 'L', 4320817L: '\x89', 4320818L: ',', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345906: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 140737488345915: '\x00', 4320819L: '$', 140737488345904: 'p'}}, 'text': 'L\x89,$', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320820L, 'RBP': 4792416L}, 'memory': {140737488345905: '\x06', 140737488345906: '\x00', 140737488345888: '"', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 4320816L: 'L', 4320817L: '\x89', 4320818L: ',', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\x03', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xbc', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320819L: '$', 140737488345904: 'p'}}, 'disassembly': 'MOV [RSP], R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_36(self):
''' Instruction MOV R13, RBX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 0L, 'RBX': 4195056L, 'RDX': 0L, 'RBP': 11L, 'RDI': 6L, 'R13': 4195032L, 'RSI': 7065696L, 'RIP': 4197578L, 'RSP': 140737488346192L, 'RFLAGS': 514L, 'RAX': 4409968L}, 'memory': {4197578L: 'I', 4197579L: '\x89', 4197580L: '\xdd'}}, 'text': 'I\x89\xdd', 'pos': {'registers': {'RCX': 0L, 'RBX': 4195056L, 'RDX': 0L, 'RBP': 11L, 'RDI': 6L, 'R13': 4195056L, 'RSI': 7065696L, 'RIP': 4197581L, 'RSP': 140737488346192L, 'RFLAGS': 514L, 'RAX': 4409968L}, 'memory': {4197578L: 'I', 4197579L: '\x89', 4197580L: '\xdd'}}, 'disassembly': 'MOV R13, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_37(self):
''' Instruction MOV [RBP+0x28], R8 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'R8': 140737354125650L, 'RAX': 140737354125650L, 'RSP': 140737488344192L, 'RDX': 4782995L, 'RIP': 4392718L, 'RBP': 7049504L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 4392718L: 'L', 4392719L: '\x89', 4392720L: 'E', 4392721L: '(', 7049544: 'N', 7049545: '\xd1', 7049546: '\xff', 7049547: '\xf7', 7049548: '\xff', 7049549: '\x7f', 7049550: '\x00', 7049551: '\x00', 7049552: '\x00', 7049553: '\xe0', 7049554: '\xff', 7049555: '\xf7', 7049556: '\xff', 7049557: '\x7f', 7049558: '\x00', 7049559: '\x00', 7049560: '\x00', 7049561: '\xd0', 7049562: '\xff', 7049563: '\xf7', 7049564: '\xff', 7049565: '\x7f', 7049566: '\x00', 7049567: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'text': 'L\x89E(', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'R8': 140737354125650L, 'RAX': 140737354125650L, 'RSP': 140737488344192L, 'RDX': 4782995L, 'RIP': 4392722L, 'RBP': 7049504L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 4392718L: 'L', 4392719L: '\x89', 4392720L: 'E', 4392721L: '(', 7049544: 'R', 7049545: '\xd1', 7049546: '\xff', 7049547: '\xf7', 7049548: '\xff', 7049549: '\x7f', 7049550: '\x00', 7049551: '\x00', 7049552: '\x00', 7049553: '\xe0', 7049554: '\xff', 7049555: '\xf7', 7049556: '\xff', 7049557: '\x7f', 7049558: '\x00', 7049559: '\x00', 7049560: '\x00', 7049561: '\xd0', 7049562: '\xff', 7049563: '\xf7', 7049564: '\xff', 7049565: '\x7f', 7049566: '\x00', 7049567: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'disassembly': 'MOV [RBP+0x28], R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_38(self):
''' Instruction MOV [RAX+0x10], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051624L, 'RSP': 140737488345712L, 'RDX': 304L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7051648: 'h', 7051649: '\x99', 7051650: 'k', 7051651: '\x00', 7051652: '\x00', 7051653: '\x00', 7051654: '\x00', 7051655: '\x00', 7051656: '\x00', 7051657: '\x00', 7051658: '\x00', 7051659: '\x00', 7051660: '\x00', 7051661: '\x00', 7051662: '\x00', 7051663: '\x00', 7051664: '\x00', 7051665: '\x00', 7051666: '\x00', 7051667: '\x00', 7051668: '\x00', 7051669: '\x00', 7051670: '\x00', 7051671: '\x00', 7051672: '\x00', 7051673: '\x00', 7051674: '\x00', 7051675: '\x00', 7051676: '\x00', 7051677: '\x00', 7051678: '\x00', 7051679: '\x00', 7051680: '\x00', 7051681: '\x00', 7051682: '\x00', 7051683: '\x00', 7051684: '\x00', 7051685: '\x00', 7051686: '\x00', 7051687: '\x00', 7051688: '\x00', 7051689: '\x00', 7051690: '\x00', 7051691: '\x00', 7051692: '\x00', 7051693: '\x00', 7051694: '\x00', 7051695: '\x00', 7051696: '\x00', 7051697: '\x00', 7051698: '\x00', 7051699: '\x00', 7051700: '\x00', 7051701: '\x00', 7051702: '\x00', 7051703: '\x00', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7051640: '\x00', 7051641: '\x00', 7051642: '\x00', 7051643: '\x00', 7051644: '\x00', 7051645: '\x00', 7051646: '\x00', 7051647: '\x00'}}, 'text': 'H\x89@\x10', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051624L, 'RSP': 140737488345712L, 'RDX': 304L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {7051648: 'h', 7051649: '\x99', 7051650: 'k', 7051651: '\x00', 7051652: '\x00', 7051653: '\x00', 7051654: '\x00', 7051655: '\x00', 7051656: '\x00', 7051657: '\x00', 7051658: '\x00', 7051659: '\x00', 7051660: '\x00', 7051661: '\x00', 7051662: '\x00', 7051663: '\x00', 7051664: '\x00', 7051665: '\x00', 7051666: '\x00', 7051667: '\x00', 7051668: '\x00', 7051669: '\x00', 7051670: '\x00', 7051671: '\x00', 7051672: '\x00', 7051673: '\x00', 7051674: '\x00', 7051675: '\x00', 7051676: '\x00', 7051677: '\x00', 7051678: '\x00', 7051679: '\x00', 7051680: '\x00', 7051681: '\x00', 7051682: '\x00', 7051683: '\x00', 7051684: '\x00', 7051685: '\x00', 7051686: '\x00', 7051687: '\x00', 7051688: '\x00', 7051689: '\x00', 7051690: '\x00', 7051691: '\x00', 7051692: '\x00', 7051693: '\x00', 7051694: '\x00', 7051695: '\x00', 7051696: '\x00', 7051697: '\x00', 7051698: '\x00', 7051699: '\x00', 7051700: '\x00', 7051701: '\x00', 7051702: '\x00', 7051703: '\x00', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7051640: 'h', 7051641: '\x99', 7051642: 'k', 7051643: '\x00', 7051644: '\x00', 7051645: '\x00', 7051646: '\x00', 7051647: '\x00'}}, 'disassembly': 'MOV [RAX+0x10], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_39(self):
''' Instruction MOV R15D, ECX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 0L, 'RDX': 13238272L, 'RBP': 188L, 'RDI': 188L, 'R15D': 7035168L, 'RSI': 13L, 'RIP': 4284490L, 'RSP': 140737488346048L, 'RFLAGS': 582L, 'RAX': 1979931137L, 'ECX': 0L}, 'memory': {4284490L: 'A', 4284491L: '\x89', 4284492L: '\xcf'}}, 'text': 'A\x89\xcf', 'pos': {'registers': {'RCX': 0L, 'RDX': 13238272L, 'RBP': 188L, 'RDI': 188L, 'R15D': 0L, 'RSI': 13L, 'RIP': 4284493L, 'RSP': 140737488346048L, 'RFLAGS': 582L, 'RAX': 1979931137L, 'ECX': 0L}, 'memory': {4284490L: 'A', 4284491L: '\x89', 4284492L: '\xcf'}}, 'disassembly': 'MOV R15D, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_4(self):
''' Instruction MOV RBP, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346720L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488350163L}, 'memory': {140737488346752: 'x', 140737488346753: '\xec', 140737488346754: '\xff', 140737488346755: '\xff', 140737488346756: '\xff', 140737488346757: '\x7f', 140737488346758: '\x00', 140737488346759: '\x00', 140737488346760: '\xad', 140737488346761: '\xec', 140737488346762: '\xff', 140737488346763: '\xff', 140737488346764: '\xff', 140737488346765: '\x7f', 140737488346766: '\x00', 140737488346767: '\x00', 140737488346768: '\xbe', 140737488346769: '\xec', 140737488346770: '\xff', 140737488346771: '\xff', 140737488346772: '\xff', 140737488346773: '\x7f', 140737488346774: '\x00', 140737488346775: '\x00', 140737488346776: '\xc5', 140737488346777: '\xec', 140737488346778: '\xff', 140737488346779: '\xff', 140737488346780: '\xff', 140737488346781: '\x7f', 140737488346782: '\x00', 140737488346783: '\x00', 140737488346731: '\xff', 140737488346737: '\xec', 140737488346733: '\x7f', 140737488346720: '\xe5', 140737488346721: '\xeb', 140737488346722: '\xff', 140737488346723: '\xff', 140737488346724: '\xff', 140737488346725: '\x7f', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346729: '\xeb', 140737488346730: '\xff', 140737488346727: '\x00', 140737488346732: '\xff', 140737488346726: '\x00', 140737488346734: '\x00', 140737488346735: '\x00', 140737488346736: '\x0f', 140737488346728: '\xf4', 140737488346738: '\xff', 140737488346739: '\xff', 140737488346740: '\xff', 140737488346741: '\x7f', 140737488346742: '\x00', 140737488346743: '\x00', 140737488346744: 'I', 140737488346745: '\xec', 140737488346746: '\xff', 140737488346747: '\xff', 140737488346748: '\xff', 140737488346749: '\x7f', 140737488346750: '\x00', 140737488346751: '\x00'}}, 'text': 'H\x8b+', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322537L, 'RBP': 140737488350181L}, 'memory': {140737488346752: 'x', 140737488346753: '\xec', 140737488346754: '\xff', 140737488346755: '\xff', 140737488346756: '\xff', 140737488346757: '\x7f', 140737488346758: '\x00', 140737488346759: '\x00', 140737488346760: '\xad', 140737488346761: '\xec', 140737488346762: '\xff', 140737488346763: '\xff', 140737488346764: '\xff', 140737488346765: '\x7f', 140737488346766: '\x00', 140737488346767: '\x00', 140737488346768: '\xbe', 140737488346769: '\xec', 140737488346770: '\xff', 140737488346771: '\xff', 140737488346772: '\xff', 140737488346773: '\x7f', 140737488346774: '\x00', 140737488346775: '\x00', 140737488346776: '\xc5', 140737488346777: '\xec', 140737488346778: '\xff', 140737488346779: '\xff', 140737488346780: '\xff', 140737488346781: '\x7f', 140737488346782: '\x00', 140737488346783: '\x00', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346720: '\xe5', 140737488346721: '\xeb', 140737488346722: '\xff', 140737488346723: '\xff', 140737488346724: '\xff', 140737488346725: '\x7f', 140737488346726: '\x00', 140737488346727: '\x00', 140737488346728: '\xf4', 140737488346729: '\xeb', 140737488346730: '\xff', 140737488346731: '\xff', 140737488346732: '\xff', 140737488346733: '\x7f', 140737488346734: '\x00', 140737488346735: '\x00', 140737488346736: '\x0f', 140737488346737: '\xec', 140737488346738: '\xff', 140737488346739: '\xff', 140737488346740: '\xff', 140737488346741: '\x7f', 140737488346742: '\x00', 140737488346743: '\x00', 140737488346744: 'I', 140737488346745: '\xec', 140737488346746: '\xff', 140737488346747: '\xff', 140737488346748: '\xff', 140737488346749: '\x7f', 140737488346750: '\x00', 140737488346751: '\x00'}}, 'disassembly': 'MOV RBP, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_40(self):
''' Instruction MOV EDX, 0x0 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 18446744073709551615L, 'RIP': 4336648L, 'RBP': 140737488345936L}, 'memory': {4336648L: '\xba', 4336649L: '\x00', 4336650L: '\x00', 4336651L: '\x00', 4336652L: '\x00'}}, 'text': '\xba\x00\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 599L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336653L, 'RBP': 140737488345936L}, 'memory': {4336648L: '\xba', 4336649L: '\x00', 4336650L: '\x00', 4336651L: '\x00', 4336652L: '\x00'}}, 'disassembly': 'MOV EDX, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_41(self):
''' Instruction MOV RBP, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346968L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488351129L}, 'memory': {140737488347008: '\x06', 140737488347009: '\x00', 140737488347010: '\x00', 140737488347011: '\x00', 140737488347012: '\x00', 140737488347013: '\x00', 140737488347014: '\x00', 140737488347015: '\x00', 140737488347016: '\x00', 140737488347017: '\x10', 140737488347018: '\x00', 140737488347019: '\x00', 140737488347020: '\x00', 140737488347021: '\x00', 140737488347022: '\x00', 140737488347023: '\x00', 140737488347024: '\x11', 140737488347025: '\x00', 140737488347026: '\x00', 140737488347027: '\x00', 140737488347028: '\x00', 140737488347029: '\x00', 140737488347030: '\x00', 140737488347031: '\x00', 140737488346993: '\x00', 140737488346987: '\xf7', 140737488346997: '\x00', 140737488346968: '\x00', 140737488346969: '\x00', 140737488346970: '\x00', 140737488346971: '\x00', 140737488346972: '\x00', 140737488346973: '\x00', 140737488346974: '\x00', 140737488346975: '\x00', 140737488346976: '!', 140737488346977: '\x00', 140737488346978: '\x00', 140737488346979: '\x00', 140737488346980: '\x00', 140737488346981: '\x00', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346985: '\xe0', 140737488346986: '\xff', 140737488346983: '\x00', 140737488346988: '\xff', 140737488346989: '\x7f', 140737488346990: '\x00', 140737488346991: '\x00', 140737488346992: '\x10', 140737488346984: '\x00', 140737488346994: '\x00', 140737488346995: '\x00', 140737488346996: '\x00', 140737488346982: '\x00', 140737488346998: '\x00', 140737488346999: '\x00', 140737488347000: '\xff', 140737488347001: '\xfb', 140737488347002: '\xeb', 140737488347003: '\xbf', 140737488347004: '\x00', 140737488347005: '\x00', 140737488347006: '\x00', 140737488347007: '\x00'}}, 'text': 'H\x8b+', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 0L}, 'memory': {140737488347008: '\x06', 140737488347009: '\x00', 140737488347010: '\x00', 140737488347011: '\x00', 140737488347012: '\x00', 140737488347013: '\x00', 140737488347014: '\x00', 140737488347015: '\x00', 140737488347016: '\x00', 140737488347017: '\x10', 140737488347018: '\x00', 140737488347019: '\x00', 140737488347020: '\x00', 140737488347021: '\x00', 140737488347022: '\x00', 140737488347023: '\x00', 140737488347024: '\x11', 140737488347025: '\x00', 140737488347026: '\x00', 140737488347027: '\x00', 140737488347028: '\x00', 140737488347029: '\x00', 140737488347030: '\x00', 140737488347031: '\x00', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346968: '\x00', 140737488346969: '\x00', 140737488346970: '\x00', 140737488346971: '\x00', 140737488346972: '\x00', 140737488346973: '\x00', 140737488346974: '\x00', 140737488346975: '\x00', 140737488346976: '!', 140737488346977: '\x00', 140737488346978: '\x00', 140737488346979: '\x00', 140737488346980: '\x00', 140737488346981: '\x00', 140737488346982: '\x00', 140737488346983: '\x00', 140737488346984: '\x00', 140737488346985: '\xe0', 140737488346986: '\xff', 140737488346987: '\xf7', 140737488346988: '\xff', 140737488346989: '\x7f', 140737488346990: '\x00', 140737488346991: '\x00', 140737488346992: '\x10', 140737488346993: '\x00', 140737488346994: '\x00', 140737488346995: '\x00', 140737488346996: '\x00', 140737488346997: '\x00', 140737488346998: '\x00', 140737488346999: '\x00', 140737488347000: '\xff', 140737488347001: '\xfb', 140737488347002: '\xeb', 140737488347003: '\xbf', 140737488347004: '\x00', 140737488347005: '\x00', 140737488347006: '\x00', 140737488347007: '\x00'}}, 'disassembly': 'MOV RBP, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_42(self):
''' Instruction MOV [RSP-0x20], R12 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 7049504L, 'R12': 4294967295L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4392444L, 'RBP': 140737488345936L}, 'memory': {4392448L: '\xe0', 140737488344216: '\x00', 140737488344217: '\x00', 140737488344218: '\x00', 140737488344219: '\x00', 140737488344220: '\x00', 140737488344221: '\x00', 140737488344222: '\x00', 140737488344223: '\x00', 140737488344224: '\x00', 140737488344225: '\x00', 140737488344226: '\x00', 140737488344227: '\x00', 140737488344228: '\x00', 140737488344229: '\x00', 140737488344230: '\x00', 140737488344231: '\x00', 140737488344232: '\x00', 140737488344233: '\x00', 140737488344234: '\x00', 140737488344235: '\x00', 140737488344236: '\x00', 140737488344237: '\x00', 140737488344238: '\x00', 140737488344239: '\x00', 140737488344240: '\x00', 140737488344241: '\x00', 140737488344242: '\x00', 140737488344243: '\x00', 140737488344244: '\x00', 140737488344245: '\x00', 140737488344246: '\x00', 140737488344247: '\x00', 140737488344248: '\x87', 140737488344249: '\x11', 140737488344250: 'B', 140737488344251: '\x00', 140737488344252: '\x00', 140737488344253: '\x00', 140737488344254: '\x00', 140737488344255: '\x00', 140737488344256: '\x00', 140737488344257: '\x00', 140737488344258: '\x00', 140737488344259: '\x00', 140737488344260: '\x00', 140737488344261: '\x00', 140737488344262: '\x00', 140737488344263: '\x00', 140737488344264: '\t', 140737488344265: '\x00', 140737488344266: '\x00', 140737488344267: '\x00', 140737488344268: '\x00', 140737488344269: '\x00', 140737488344270: '\x00', 140737488344271: '\x00', 140737488344272: '\x00', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 4392444L: 'L', 4392445L: '\x89', 4392446L: 'd', 4392447L: '$'}}, 'text': 'L\x89d$\xe0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4782888L, 'RDI': 7049504L, 'R12': 4294967295L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4392449L, 'RBP': 140737488345936L}, 'memory': {4392448L: '\xe0', 140737488344216: '\xff', 140737488344217: '\xff', 140737488344218: '\xff', 140737488344219: '\xff', 140737488344220: '\x00', 140737488344221: '\x00', 140737488344222: '\x00', 140737488344223: '\x00', 140737488344224: '\x00', 140737488344225: '\x00', 140737488344226: '\x00', 140737488344227: '\x00', 140737488344228: '\x00', 140737488344229: '\x00', 140737488344230: '\x00', 140737488344231: '\x00', 140737488344232: '\x00', 140737488344233: '\x00', 140737488344234: '\x00', 140737488344235: '\x00', 140737488344236: '\x00', 140737488344237: '\x00', 140737488344238: '\x00', 140737488344239: '\x00', 140737488344240: '\x00', 140737488344241: '\x00', 140737488344242: '\x00', 140737488344243: '\x00', 140737488344244: '\x00', 140737488344245: '\x00', 140737488344246: '\x00', 140737488344247: '\x00', 140737488344248: '\x87', 140737488344249: '\x11', 140737488344250: 'B', 140737488344251: '\x00', 140737488344252: '\x00', 140737488344253: '\x00', 140737488344254: '\x00', 140737488344255: '\x00', 140737488344256: '\x00', 140737488344257: '\x00', 140737488344258: '\x00', 140737488344259: '\x00', 140737488344260: '\x00', 140737488344261: '\x00', 140737488344262: '\x00', 140737488344263: '\x00', 140737488344264: '\t', 140737488344265: '\x00', 140737488344266: '\x00', 140737488344267: '\x00', 140737488344268: '\x00', 140737488344269: '\x00', 140737488344270: '\x00', 140737488344271: '\x00', 140737488344272: '\x00', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 4392444L: 'L', 4392445L: '\x89', 4392446L: 'd', 4392447L: '$'}}, 'disassembly': 'MOV [RSP-0x20], R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_43(self):
''' Instruction MOV RDI, [R13+0x0] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'R13': 7051024L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199248L, 'RBP': 4782912L}, 'memory': {7051024: ' ', 7051025: '\x91', 7051026: 'k', 7051027: '\x00', 7051028: '\x00', 7051029: '\x00', 7051030: '\x00', 7051031: '\x00', 7051032: '\x00', 7051033: '\x92', 7051034: 'k', 7051035: '\x00', 7051036: '\x00', 7051037: '\x00', 7051038: '\x00', 7051039: '\x00', 7051040: '\x01', 7051041: '\x00', 7051042: '\x00', 7051043: '\x00', 7051044: '\x03', 7051045: '\x00', 7051046: '\x00', 7051047: '\x00', 7051048: '\x00', 7051049: '\x00', 7051050: '\x00', 7051051: '\x00', 7051052: '\x00', 7051053: '\x00', 7051054: '\x00', 7051055: '\x00', 7051056: '\x00', 7051057: '\x00', 7051058: '\x00', 7051059: '\x00', 7051060: '\x00', 7051061: '\x00', 7051062: '\x00', 7051063: '\x00', 7051064: '\x00', 7051065: '\x00', 7051066: '\x00', 7051067: '\x00', 7051068: '\x00', 7051069: '\x00', 7051070: '\x00', 7051071: '\x00', 7051072: '\x00', 7051073: '\x00', 7051074: '\x02', 7051075: '\x00', 7051076: '\x00', 7051077: '\x00', 7051078: '\x00', 7051079: '\x00', 7051080: '\x00', 7051081: '\x00', 7051082: '\x02', 7051083: '\x00', 7051084: '\x00', 7051085: '\x00', 7051086: '\x00', 7051087: '\x00', 4199248L: 'I', 4199249L: '\x8b', 4199250L: '}', 4199251L: '\x00'}}, 'text': 'I\x8b}\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 4294967295L, 'RIP': 4199252L, 'RBP': 4782912L}, 'memory': {7051024: ' ', 7051025: '\x91', 7051026: 'k', 7051027: '\x00', 7051028: '\x00', 7051029: '\x00', 7051030: '\x00', 7051031: '\x00', 7051032: '\x00', 7051033: '\x92', 7051034: 'k', 7051035: '\x00', 7051036: '\x00', 7051037: '\x00', 7051038: '\x00', 7051039: '\x00', 7051040: '\x01', 7051041: '\x00', 7051042: '\x00', 7051043: '\x00', 7051044: '\x03', 7051045: '\x00', 7051046: '\x00', 7051047: '\x00', 7051048: '\x00', 7051049: '\x00', 7051050: '\x00', 7051051: '\x00', 7051052: '\x00', 7051053: '\x00', 7051054: '\x00', 7051055: '\x00', 7051056: '\x00', 7051057: '\x00', 7051058: '\x00', 7051059: '\x00', 7051060: '\x00', 7051061: '\x00', 7051062: '\x00', 7051063: '\x00', 7051064: '\x00', 7051065: '\x00', 7051066: '\x00', 7051067: '\x00', 7051068: '\x00', 7051069: '\x00', 7051070: '\x00', 7051071: '\x00', 7051072: '\x00', 7051073: '\x00', 7051074: '\x02', 7051075: '\x00', 7051076: '\x00', 7051077: '\x00', 7051078: '\x00', 7051079: '\x00', 7051080: '\x00', 7051081: '\x00', 7051082: '\x02', 7051083: '\x00', 7051084: '\x00', 7051085: '\x00', 7051086: '\x00', 7051087: '\x00', 4199248L: 'I', 4199249L: '\x8b', 4199250L: '}', 4199251L: '\x00'}}, 'disassembly': 'MOV RDI, [R13+0x0]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_44(self):
''' Instruction MOV R14, RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488345936L, 'RDX': 140737488345952L, 'RIP': 4329543L, 'RBP': 140737488345936L}, 'memory': {4329544L: '\x89', 4329545L: '\xf6', 4329543L: 'I'}}, 'text': 'I\x89\xf6', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 4782991L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488345936L, 'RDX': 140737488345952L, 'RIP': 4329546L, 'RBP': 140737488345936L}, 'memory': {4329544L: '\x89', 4329545L: '\xf6', 4329543L: 'I'}}, 'disassembly': 'MOV R14, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_45(self):
''' Instruction MOV RBP, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 140737488346472L, 'RBX': 140737488346864L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322534L, 'RBP': 140737488350621L}, 'memory': {140737488346880: '\x1f', 140737488346881: '\xee', 140737488346882: '\xff', 140737488346883: '\xff', 140737488346884: '\xff', 140737488346885: '\x7f', 140737488346886: '\x00', 140737488346887: '\x00', 140737488346888: 'X', 140737488346889: '\xee', 140737488346890: '\xff', 140737488346891: '\xff', 140737488346892: '\xff', 140737488346893: '\x7f', 140737488346894: '\x00', 140737488346895: '\x00', 140737488346896: 'n', 140737488346897: '\xee', 140737488346898: '\xff', 140737488346899: '\xff', 140737488346900: '\xff', 140737488346901: '\x7f', 140737488346902: '\x00', 140737488346903: '\x00', 140737488346904: '{', 140737488346905: '\xee', 140737488346906: '\xff', 140737488346907: '\xff', 140737488346908: '\xff', 140737488346909: '\x7f', 140737488346910: '\x00', 140737488346911: '\x00', 140737488346912: '\x00', 140737488346913: '\xef', 140737488346914: '\xff', 140737488346915: '\xff', 140737488346916: '\xff', 140737488346917: '\x7f', 140737488346918: '\x00', 140737488346919: '\x00', 140737488346920: '\r', 140737488346921: '\xef', 140737488346922: '\xff', 140737488346923: '\xff', 140737488346924: '\xff', 140737488346925: '\x7f', 140737488346926: '\x00', 140737488346927: '\x00', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346864: '\xb2', 140737488346865: '\xed', 140737488346866: '\xff', 140737488346867: '\xff', 140737488346868: '\xff', 140737488346869: '\x7f', 140737488346870: '\x00', 140737488346871: '\x00', 140737488346872: '\xbd', 140737488346873: '\xed', 140737488346874: '\xff', 140737488346875: '\xff', 140737488346876: '\xff', 140737488346877: '\x7f', 140737488346878: '\x00', 140737488346879: '\x00'}}, 'text': 'H\x8b+', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488350642L}, 'memory': {140737488346880: '\x1f', 140737488346881: '\xee', 140737488346882: '\xff', 140737488346883: '\xff', 140737488346884: '\xff', 140737488346885: '\x7f', 140737488346886: '\x00', 140737488346887: '\x00', 140737488346888: 'X', 140737488346889: '\xee', 140737488346890: '\xff', 140737488346891: '\xff', 140737488346892: '\xff', 140737488346893: '\x7f', 140737488346894: '\x00', 140737488346895: '\x00', 140737488346896: 'n', 140737488346897: '\xee', 140737488346898: '\xff', 140737488346899: '\xff', 140737488346900: '\xff', 140737488346901: '\x7f', 140737488346902: '\x00', 140737488346903: '\x00', 140737488346904: '{', 140737488346905: '\xee', 140737488346906: '\xff', 140737488346907: '\xff', 140737488346908: '\xff', 140737488346909: '\x7f', 140737488346910: '\x00', 140737488346911: '\x00', 140737488346912: '\x00', 140737488346913: '\xef', 140737488346914: '\xff', 140737488346915: '\xff', 140737488346916: '\xff', 140737488346917: '\x7f', 140737488346918: '\x00', 140737488346919: '\x00', 140737488346920: '\r', 140737488346921: '\xef', 140737488346922: '\xff', 140737488346923: '\xff', 140737488346924: '\xff', 140737488346925: '\x7f', 140737488346926: '\x00', 140737488346927: '\x00', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346864: '\xb2', 140737488346865: '\xed', 140737488346866: '\xff', 140737488346867: '\xff', 140737488346868: '\xff', 140737488346869: '\x7f', 140737488346870: '\x00', 140737488346871: '\x00', 140737488346872: '\xbd', 140737488346873: '\xed', 140737488346874: '\xff', 140737488346875: '\xff', 140737488346876: '\xff', 140737488346877: '\x7f', 140737488346878: '\x00', 140737488346879: '\x00'}}, 'disassembly': 'MOV RBP, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_46(self):
''' Instruction MOV EAX, [RDI] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392486L, 'RBP': 7049504L}, 'memory': {4392487L: '\x07', 4392486L: '\x8b', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'text': '\x8b\x07', 'pos': {'registers': {'EAX': 4222429316L, 'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392488L, 'RBP': 7049504L}, 'memory': {4392487L: '\x07', 4392486L: '\x8b', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'MOV EAX, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_47(self):
''' Instruction MOV R13, [RSP] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x04', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'text': 'L\x8b,$', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320750L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x04', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x00', 140737488345913: 'Z', 140737488345914: '\x03', 140737488345915: 'v', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'disassembly': 'MOV R13, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_48(self):
''' Instruction MOV R13, [RSP+0x20] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'R13': 17484L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322429L, 'RBP': 140737488346472L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xe2', 140737488346121: '\x93', 140737488346122: 'A', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: '\x08', 140737488346129: '\x00', 140737488346130: '\x00', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: 'P', 140737488346137: '\x00', 140737488346138: '\x00', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346144: '0', 140737488346145: '\xe8', 140737488346146: 'k', 140737488346147: '\x00', 140737488346148: '\x00', 140737488346149: '\x00', 140737488346150: '\x00', 140737488346151: '\x00', 140737488346152: '\x04', 140737488346153: '\x00', 140737488346154: '\x00', 140737488346155: '\x00', 140737488346156: '\x00', 140737488346157: '\x00', 140737488346158: '\x00', 140737488346159: '\x00', 140737488346110: '\x00', 140737488346111: '\x00', 4322433L: ' ', 4322432L: '$', 140737488346109: '\x00', 140737488346096: '\x07', 140737488346097: '\x00', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 4322429L: 'L', 4322430L: '\x8b', 4322431L: 'l'}}, 'text': 'L\x8bl$ ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'R13': 7L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322434L, 'RBP': 140737488346472L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xe2', 140737488346121: '\x93', 140737488346122: 'A', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: '\x08', 140737488346129: '\x00', 140737488346130: '\x00', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: 'P', 140737488346137: '\x00', 140737488346138: '\x00', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346144: '0', 140737488346145: '\xe8', 140737488346146: 'k', 140737488346147: '\x00', 140737488346148: '\x00', 140737488346149: '\x00', 140737488346150: '\x00', 140737488346151: '\x00', 140737488346152: '\x04', 140737488346153: '\x00', 140737488346154: '\x00', 140737488346155: '\x00', 140737488346156: '\x00', 140737488346157: '\x00', 140737488346158: '\x00', 140737488346159: '\x00', 140737488346110: '\x00', 140737488346111: '\x00', 4322433L: ' ', 4322432L: '$', 140737488346109: '\x00', 140737488346096: '\x07', 140737488346097: '\x00', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 4322429L: 'L', 4322430L: '\x8b', 4322431L: 'l'}}, 'disassembly': 'MOV R13, [RSP+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_49(self):
''' Instruction MOV DWORD [RBP-0x5ac], 0x0 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 7066112L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4330220L, 'RBP': 140737488345936L}, 'memory': {140737488344512: '\x00', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 4330220L: '\xc7', 4330225L: '\xff', 4330228L: '\x00', 4330221L: '\x85', 4330229L: '\x00', 4330222L: 'T', 4330227L: '\x00', 4330223L: '\xfa', 4330224L: '\xff', 4330226L: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\x00', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00'}}, 'text': '\xc7\x85T\xfa\xff\xff\x00\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 7066112L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4330230L, 'RBP': 140737488345936L}, 'memory': {140737488344512: '\x00', 140737488344513: '\x00', 140737488344514: '\x00', 140737488344515: '\x00', 4330220L: '\xc7', 4330225L: '\xff', 4330228L: '\x00', 4330221L: '\x85', 4330229L: '\x00', 4330222L: 'T', 4330227L: '\x00', 4330223L: '\xfa', 4330224L: '\xff', 4330226L: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 140737488344488: '\x00', 140737488344489: '\x00', 140737488344490: '\x00', 140737488344491: '\x00', 140737488344492: '\x00', 140737488344493: '\x00', 140737488344494: '\x00', 140737488344495: '\x00', 140737488344496: '\x00', 140737488344497: '\x00', 140737488344498: '\x00', 140737488344499: '\x00', 140737488344500: '\x00', 140737488344501: '\x00', 140737488344502: '\x00', 140737488344503: '\x00', 140737488344504: '\x00', 140737488344505: '\x00', 140737488344506: '\x00', 140737488344507: '\x00', 140737488344508: '\x00', 140737488344509: '\x00', 140737488344510: '\x00', 140737488344511: '\x00'}}, 'disassembly': 'MOV DWORD [RBP-0x5ac], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_5(self):
''' Instruction MOV R15, RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 18446744073709551568L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392488L, 'RBP': 7049504L}, 'memory': {4392488L: 'I', 4392489L: '\x89', 4392490L: '\xf7'}}, 'text': 'I\x89\xf7', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4782905L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392488L: 'I', 4392489L: '\x89', 4392490L: '\xf7'}}, 'disassembly': 'MOV R15, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_50(self):
''' Instruction MOV [RBP-0x548], CL '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 115L, 'RSI': 140737354125325L, 'CL': 115L, 'RDI': 140737354125323L, 'RAX': 115L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330334L, 'RBP': 140737488345936L}, 'memory': {140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 4330334L: '\x88', 4330335L: '\x8d', 4330336L: '\xb8', 4330337L: '\xfa', 4330338L: '\xff', 4330339L: '\xff'}}, 'text': '\x88\x8d\xb8\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 115L, 'RSI': 140737354125325L, 'CL': 115L, 'RDI': 140737354125323L, 'RAX': 115L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330340L, 'RBP': 140737488345936L}, 'memory': {140737488344584: 's', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 4330334L: '\x88', 4330335L: '\x8d', 4330336L: '\xb8', 4330337L: '\xfa', 4330338L: '\xff', 4330339L: '\xff'}}, 'disassembly': 'MOV [RBP-0x548], CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_51(self):
''' Instruction MOV [RSP+0x28], RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 43L, 'RSI': 4L, 'RDI': 4783016L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 0L, 'RIP': 4198778L, 'RBP': 140737488346224L}, 'memory': {140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\xd0', 140737488346009: '\xb7', 140737488346010: 'k', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: 'A', 140737488346017: 'A', 140737488346018: 'A', 140737488346019: 'A', 140737488346020: 'A', 140737488346021: 'A', 140737488346022: 'A', 140737488346023: 'A', 140737488346024: 'A', 140737488346025: 'A', 140737488346026: 'A', 140737488346027: 'A', 140737488346028: 'A', 140737488346029: 'A', 140737488346030: 'A', 140737488346031: 'A', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00', 140737488346040: 'r', 140737488346041: '`', 140737488346042: 'A', 140737488346043: '\x00', 140737488346044: '\x00', 140737488346045: '\x00', 140737488346046: '\x00', 140737488346047: '\x00', 140737488346048: '\x00', 140737488346049: '\xdc', 140737488346050: '\xff', 140737488346051: '\xff', 140737488346052: '\xff', 140737488346053: '\x7f', 140737488346054: '\x00', 140737488346055: '\x00', 4198778L: 'H', 4198779L: '\x89', 4198780L: 't', 4198781L: '$', 4198782L: '('}}, 'text': 'H\x89t$(', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 43L, 'RSI': 4L, 'RDI': 4783016L, 'RAX': 4198854L, 'RSP': 140737488345952L, 'RDX': 0L, 'RIP': 4198783L, 'RBP': 140737488346224L}, 'memory': {140737488345992: '\x04', 140737488345993: '\x00', 140737488345994: '\x00', 140737488345995: '\x00', 140737488345996: '\x00', 140737488345997: '\x00', 140737488345998: '\x00', 140737488345999: '\x00', 140737488346000: '\x03', 140737488346001: '\x00', 140737488346002: '\x00', 140737488346003: '\x00', 140737488346004: '\x00', 140737488346005: '\x00', 140737488346006: '\x00', 140737488346007: '\x00', 140737488346008: '\xd0', 140737488346009: '\xb7', 140737488346010: 'k', 140737488346011: '\x00', 140737488346012: '\x00', 140737488346013: '\x00', 140737488346014: '\x00', 140737488346015: '\x00', 140737488346016: 'A', 140737488346017: 'A', 140737488346018: 'A', 140737488346019: 'A', 140737488346020: 'A', 140737488346021: 'A', 140737488346022: 'A', 140737488346023: 'A', 140737488346024: 'A', 140737488346025: 'A', 140737488346026: 'A', 140737488346027: 'A', 140737488346028: 'A', 140737488346029: 'A', 140737488346030: 'A', 140737488346031: 'A', 140737488346032: '\x00', 140737488346033: '\x00', 140737488346034: '\x00', 140737488346035: '\x00', 140737488346036: '\x00', 140737488346037: '\x00', 140737488346038: '\x00', 140737488346039: '\x00', 140737488346040: 'r', 140737488346041: '`', 140737488346042: 'A', 140737488346043: '\x00', 140737488346044: '\x00', 140737488346045: '\x00', 140737488346046: '\x00', 140737488346047: '\x00', 140737488346048: '\x00', 140737488346049: '\xdc', 140737488346050: '\xff', 140737488346051: '\xff', 140737488346052: '\xff', 140737488346053: '\x7f', 140737488346054: '\x00', 140737488346055: '\x00', 4198778L: 'H', 4198779L: '\x89', 4198780L: 't', 4198781L: '$', 4198782L: '('}}, 'disassembly': 'MOV [RSP+0x28], RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_52(self):
''' Instruction MOV RAX, [RDI] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346584L, 'RAX': 140737488347858L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195968L, 'RBP': 0L}, 'memory': {140737488346624: ':', 140737488346625: '\xe9', 140737488346626: '\xff', 140737488346627: '\xff', 140737488346628: '\xff', 140737488346629: '\x7f', 140737488346630: '\x00', 140737488346631: '\x00', 140737488346632: '_', 140737488346633: '\xe9', 140737488346634: '\xff', 140737488346635: '\xff', 140737488346636: '\xff', 140737488346637: '\x7f', 140737488346638: '\x00', 140737488346639: '\x00', 140737488346640: '}', 140737488346641: '\xe9', 140737488346642: '\xff', 140737488346643: '\xff', 140737488346644: '\xff', 140737488346645: '\x7f', 140737488346646: '\x00', 140737488346647: '\x00', 4195968L: 'H', 140737488346584: '\xf0', 140737488346614: '\x00', 4195969L: '\x8b', 140737488346585: '\xe2', 140737488346586: '\xff', 140737488346587: '\xff', 140737488346588: '\xff', 140737488346589: '\x7f', 140737488346590: '\x00', 140737488346591: '\x00', 140737488346592: '\x02', 140737488346593: '\xe3', 140737488346594: '\xff', 140737488346595: '\xff', 140737488346596: '\xff', 140737488346597: '\x7f', 140737488346598: '\x00', 140737488346599: '\x00', 140737488346600: ',', 140737488346601: '\xe3', 140737488346602: '\xff', 140737488346603: '\xff', 140737488346604: '\xff', 140737488346605: '\x7f', 140737488346606: '\x00', 140737488346607: '\x00', 140737488346608: '8', 140737488346609: '\xe3', 140737488346610: '\xff', 140737488346611: '\xff', 140737488346612: '\xff', 140737488346613: '\x7f', 4195970L: '\x07', 140737488346615: '\x00', 140737488346616: '\xa5', 140737488346617: '\xe3', 140737488346618: '\xff', 140737488346619: '\xff', 140737488346620: '\xff', 140737488346621: '\x7f', 140737488346622: '\x00', 140737488346623: '\x00'}}, 'text': 'H\x8b\x07', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346584L, 'RAX': 140737488347888L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195971L, 'RBP': 0L}, 'memory': {140737488346624: ':', 140737488346625: '\xe9', 140737488346626: '\xff', 140737488346627: '\xff', 140737488346628: '\xff', 140737488346629: '\x7f', 140737488346630: '\x00', 140737488346631: '\x00', 140737488346632: '_', 140737488346633: '\xe9', 140737488346634: '\xff', 140737488346635: '\xff', 140737488346636: '\xff', 140737488346637: '\x7f', 140737488346638: '\x00', 140737488346639: '\x00', 140737488346640: '}', 140737488346641: '\xe9', 140737488346642: '\xff', 140737488346643: '\xff', 140737488346644: '\xff', 140737488346645: '\x7f', 140737488346646: '\x00', 140737488346647: '\x00', 4195968L: 'H', 140737488346584: '\xf0', 140737488346614: '\x00', 4195969L: '\x8b', 140737488346585: '\xe2', 140737488346586: '\xff', 140737488346587: '\xff', 140737488346588: '\xff', 140737488346589: '\x7f', 140737488346590: '\x00', 140737488346591: '\x00', 140737488346592: '\x02', 140737488346593: '\xe3', 140737488346594: '\xff', 140737488346595: '\xff', 140737488346596: '\xff', 140737488346597: '\x7f', 140737488346598: '\x00', 140737488346599: '\x00', 140737488346600: ',', 140737488346601: '\xe3', 140737488346602: '\xff', 140737488346603: '\xff', 140737488346604: '\xff', 140737488346605: '\x7f', 140737488346606: '\x00', 140737488346607: '\x00', 140737488346608: '8', 140737488346609: '\xe3', 140737488346610: '\xff', 140737488346611: '\xff', 140737488346612: '\xff', 140737488346613: '\x7f', 4195970L: '\x07', 140737488346615: '\x00', 140737488346616: '\xa5', 140737488346617: '\xe3', 140737488346618: '\xff', 140737488346619: '\xff', 140737488346620: '\xff', 140737488346621: '\x7f', 140737488346622: '\x00', 140737488346623: '\x00'}}, 'disassembly': 'MOV RAX, [RDI]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_53(self):
''' Instruction MOV RBX, [RAX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 24L, 'RDI': 7059520L, 'RAX': 7059656L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212853L, 'RBP': 140737488346112L}, 'memory': {7059712: '\x00', 7059713: '\x00', 7059714: '\x00', 7059715: '\x00', 7059716: '\x00', 7059717: '\x00', 7059718: '\x00', 7059719: '\x00', 7059703: '\x00', 7059701: '\x00', 7059702: '\x00', 7059656: '\x90', 7059657: '\xdd', 7059658: '\xff', 7059659: '\xff', 7059660: '\xff', 7059661: '\x7f', 7059662: '\x00', 7059663: '\x00', 7059664: '\x00', 7059665: '\x00', 7059666: '\x00', 7059667: '\x00', 7059668: '\x00', 7059669: '\x00', 7059670: '\x00', 7059671: '\x00', 7059672: '\x00', 7059673: '\x00', 7059674: '\x00', 7059675: '\x00', 7059676: '\x00', 7059677: '\x00', 7059678: '\x00', 7059679: '\x00', 7059680: '\x00', 7059681: '\x00', 7059682: '\x00', 7059683: '\x00', 7059684: '\x00', 7059685: '\x00', 7059686: '\x00', 7059687: '\x00', 7059688: '\x00', 7059689: '\x00', 7059690: '\x00', 7059691: '\x00', 7059692: '\x00', 7059693: '\x00', 7059694: '\x00', 7059695: '\x00', 7059696: '\x00', 7059697: '\x00', 7059698: '\x00', 7059699: '\x00', 7059700: '\x00', 4212853L: 'H', 4212854L: '\x8b', 4212855L: '\x18', 7059704: '\x00', 7059705: '\x00', 7059706: '\x00', 7059707: '\x00', 7059708: '\x00', 7059709: '\x00', 7059710: '\x00', 7059711: '\x00'}}, 'text': 'H\x8b\x18', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346512L, 'RDI': 7059520L, 'RAX': 7059656L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212856L, 'RBP': 140737488346112L}, 'memory': {7059712: '\x00', 7059713: '\x00', 7059714: '\x00', 7059715: '\x00', 7059716: '\x00', 7059717: '\x00', 7059718: '\x00', 7059719: '\x00', 7059703: '\x00', 7059701: '\x00', 7059702: '\x00', 7059656: '\x90', 7059657: '\xdd', 7059658: '\xff', 7059659: '\xff', 7059660: '\xff', 7059661: '\x7f', 7059662: '\x00', 7059663: '\x00', 7059664: '\x00', 7059665: '\x00', 7059666: '\x00', 7059667: '\x00', 7059668: '\x00', 7059669: '\x00', 7059670: '\x00', 7059671: '\x00', 7059672: '\x00', 7059673: '\x00', 7059674: '\x00', 7059675: '\x00', 7059676: '\x00', 7059677: '\x00', 7059678: '\x00', 7059679: '\x00', 7059680: '\x00', 7059681: '\x00', 7059682: '\x00', 7059683: '\x00', 7059684: '\x00', 7059685: '\x00', 7059686: '\x00', 7059687: '\x00', 7059688: '\x00', 7059689: '\x00', 7059690: '\x00', 7059691: '\x00', 7059692: '\x00', 7059693: '\x00', 7059694: '\x00', 7059695: '\x00', 7059696: '\x00', 7059697: '\x00', 7059698: '\x00', 7059699: '\x00', 7059700: '\x00', 4212853L: 'H', 4212854L: '\x8b', 4212855L: '\x18', 7059704: '\x00', 7059705: '\x00', 7059706: '\x00', 7059707: '\x00', 7059708: '\x00', 7059709: '\x00', 7059710: '\x00', 7059711: '\x00'}}, 'disassembly': 'MOV RBX, [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_54(self):
''' Instruction MOV RDI, [RIP+0x297b09] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783020L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4783020L, 'RIP': 4330152L, 'RBP': 140737488345936L}, 'memory': {4330152L: 'H', 4330153L: '\x8b', 4330154L: '=', 4330155L: '\t', 4330156L: '{', 4330157L: ')', 4330158L: '\x00', 7048625: '\xd1', 7048626: 'k', 7048627: '\x00', 7048628: '\x00', 7048629: '\x00', 7048630: '\x00', 7048631: '\x00', 7048632: '\xa8', 7048633: '\xd0', 7048634: 'k', 7048635: '\x00', 7048636: '\x00', 7048637: '\x00', 7048638: '\x00', 7048639: '\x00', 7048640: 'P', 7048641: '\xcf', 7048642: 'k', 7048643: '\x00', 7048644: '\x00', 7048645: '\x00', 7048646: '\x00', 7048647: '\x00', 7048648: '\xe0', 7048649: '\x84', 7048650: 'k', 7048651: '\x00', 7048652: '\x00', 7048653: '\x00', 7048654: '\x00', 7048655: '\x00', 7048656: '\x00', 7048657: '\x00', 7048658: '\x00', 7048659: '\x00', 7048660: '\x00', 7048661: '\x00', 7048662: '\x00', 7048663: '\x00', 7048664: '<', 7048665: 'F', 7048666: 'J', 7048667: '\x00', 7048668: '\x00', 7048669: '\x00', 7048670: '\x00', 7048671: '\x00', 7048672: 'p', 7048673: '\xd1', 7048674: 'k', 7048675: '\x00', 7048676: '\x00', 7048677: '\x00', 7048678: '\x00', 7048679: '\x00', 7048680: '\xa0', 7048681: '\xce', 7048682: 'k', 7048683: '\x00', 7048684: '\x00', 7048685: '\x00', 7048686: '\x00', 7048687: '\x00', 7048688: '`'}}, 'text': 'H\x8b=\t{)\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4783020L, 'RSI': 140737354125667L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4783020L, 'RIP': 4330159L, 'RBP': 140737488345936L}, 'memory': {4330152L: 'H', 4330153L: '\x8b', 4330154L: '=', 4330155L: '\t', 4330156L: '{', 4330157L: ')', 4330158L: '\x00', 7048625: '\xd1', 7048626: 'k', 7048627: '\x00', 7048628: '\x00', 7048629: '\x00', 7048630: '\x00', 7048631: '\x00', 7048632: '\xa8', 7048633: '\xd0', 7048634: 'k', 7048635: '\x00', 7048636: '\x00', 7048637: '\x00', 7048638: '\x00', 7048639: '\x00', 7048640: 'P', 7048641: '\xcf', 7048642: 'k', 7048643: '\x00', 7048644: '\x00', 7048645: '\x00', 7048646: '\x00', 7048647: '\x00', 7048648: '\xe0', 7048649: '\x84', 7048650: 'k', 7048651: '\x00', 7048652: '\x00', 7048653: '\x00', 7048654: '\x00', 7048655: '\x00', 7048656: '\x00', 7048657: '\x00', 7048658: '\x00', 7048659: '\x00', 7048660: '\x00', 7048661: '\x00', 7048662: '\x00', 7048663: '\x00', 7048664: '<', 7048665: 'F', 7048666: 'J', 7048667: '\x00', 7048668: '\x00', 7048669: '\x00', 7048670: '\x00', 7048671: '\x00', 7048672: 'p', 7048673: '\xd1', 7048674: 'k', 7048675: '\x00', 7048676: '\x00', 7048677: '\x00', 7048678: '\x00', 7048679: '\x00', 7048680: '\xa0', 7048681: '\xce', 7048682: 'k', 7048683: '\x00', 7048684: '\x00', 7048685: '\x00', 7048686: '\x00', 7048687: '\x00', 7048688: '`'}}, 'disassembly': 'MOV RDI, [RIP+0x297b09]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_55(self):
''' Instruction MOV RDI, [RDI+0x28] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 7049504L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392511L, 'RBP': 7049504L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 4392511L: 'H', 4392512L: '\x8b', 4392513L: '\x7f', 4392514L: '(', 7049544: '\r', 7049545: '\xd0', 7049546: '\xff', 7049547: '\xf7', 7049548: '\xff', 7049549: '\x7f', 7049550: '\x00', 7049551: '\x00', 7049552: '\x00', 7049553: '\xe0', 7049554: '\xff', 7049555: '\xf7', 7049556: '\xff', 7049557: '\x7f', 7049558: '\x00', 7049559: '\x00', 7049560: '\x00', 7049561: '\xd0', 7049562: '\xff', 7049563: '\xf7', 7049564: '\xff', 7049565: '\x7f', 7049566: '\x00', 7049567: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'text': 'H\x8b\x7f(', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392515L, 'RBP': 7049504L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 4392511L: 'H', 4392512L: '\x8b', 4392513L: '\x7f', 4392514L: '(', 7049544: '\r', 7049545: '\xd0', 7049546: '\xff', 7049547: '\xf7', 7049548: '\xff', 7049549: '\x7f', 7049550: '\x00', 7049551: '\x00', 7049552: '\x00', 7049553: '\xe0', 7049554: '\xff', 7049555: '\xf7', 7049556: '\xff', 7049557: '\x7f', 7049558: '\x00', 7049559: '\x00', 7049560: '\x00', 7049561: '\xd0', 7049562: '\xff', 7049563: '\xf7', 7049564: '\xff', 7049565: '\x7f', 7049566: '\x00', 7049567: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'disassembly': 'MOV RDI, [RDI+0x28]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_56(self):
''' Instruction MOV RAX, [RIP+0x2ad802] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4240896L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4241343L, 'RBP': 9L}, 'memory': {7049216: '\x00', 7049153: '\xa0', 7049154: 'k', 7049155: '\x00', 7049156: '\x00', 7049157: '\x00', 4241343L: 'H', 4241344L: '\x8b', 4241345L: '\x05', 4241346L: '\x02', 4241347L: '\xd8', 4241348L: '*', 4241349L: '\x00', 7049158: '\x00', 7049159: '\x00', 7049160: '\xe0', 7049161: '\x13', 7049162: 'A', 7049163: '\x00', 7049164: '\x00', 7049165: '\x00', 7049166: '\x00', 7049167: '\x00', 7049168: '\xe8', 7049169: '\xa0', 7049170: 'k', 7049171: '\x00', 7049172: '\x00', 7049173: '\x00', 7049174: '\x00', 7049175: '\x00', 7049176: '\xd0', 7049177: '\x97', 7049178: 'k', 7049179: '\x00', 7049180: '\x00', 7049181: '\x00', 7049182: '\x00', 7049183: '\x00', 7049184: '\xb0', 7049185: '\x90', 7049186: '@', 7049187: '\x00', 7049188: '\x00', 7049189: '\x00', 7049190: '\x00', 7049191: '\x00', 7049192: '\x00', 7049193: '\x00', 7049194: '\x00', 7049195: '\x00', 7049196: '\x00', 7049197: '\x00', 7049198: '\x00', 7049199: '\x00', 7049200: '\xc0', 7049201: '\x85', 7049202: 'k', 7049203: '\x00', 7049204: '\x00', 7049205: '\x00', 7049206: '\x00', 7049207: '\x00', 7049208: '\xa0', 7049209: '\xcf', 7049210: 'k', 7049211: '\x00', 7049212: '\x00', 7049213: '\x00', 7049214: '\x00', 7049215: '\x00'}}, 'text': 'H\x8b\x05\x02\xd8*\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4264928L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4241350L, 'RBP': 9L}, 'memory': {7049216: '\x00', 4241345L: '\x05', 4241346L: '\x02', 4241347L: '\xd8', 4241348L: '*', 4241349L: '\x00', 4241343L: 'H', 4241344L: '\x8b', 7049153: '\xa0', 7049154: 'k', 7049155: '\x00', 7049156: '\x00', 7049157: '\x00', 7049158: '\x00', 7049159: '\x00', 7049160: '\xe0', 7049161: '\x13', 7049162: 'A', 7049163: '\x00', 7049164: '\x00', 7049165: '\x00', 7049166: '\x00', 7049167: '\x00', 7049168: '\xe8', 7049169: '\xa0', 7049170: 'k', 7049171: '\x00', 7049172: '\x00', 7049173: '\x00', 7049174: '\x00', 7049175: '\x00', 7049176: '\xd0', 7049177: '\x97', 7049178: 'k', 7049179: '\x00', 7049180: '\x00', 7049181: '\x00', 7049182: '\x00', 7049183: '\x00', 7049184: '\xb0', 7049185: '\x90', 7049186: '@', 7049187: '\x00', 7049188: '\x00', 7049189: '\x00', 7049190: '\x00', 7049191: '\x00', 7049192: '\x00', 7049193: '\x00', 7049194: '\x00', 7049195: '\x00', 7049196: '\x00', 7049197: '\x00', 7049198: '\x00', 7049199: '\x00', 7049200: '\xc0', 7049201: '\x85', 7049202: 'k', 7049203: '\x00', 7049204: '\x00', 7049205: '\x00', 7049206: '\x00', 7049207: '\x00', 7049208: '\xa0', 7049209: '\xcf', 7049210: 'k', 7049211: '\x00', 7049212: '\x00', 7049213: '\x00', 7049214: '\x00', 7049215: '\x00'}}, 'disassembly': 'MOV RAX, [RIP+0x2ad802]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_57(self):
''' Instruction MOV R12, RCX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 3L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320699L, 'RBP': 3L}, 'memory': {4320699L: 'I', 4320700L: '\x89', 4320701L: '\xcc'}}, 'text': 'I\x89\xcc', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 8L, 'RAX': 3L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320702L, 'RBP': 3L}, 'memory': {4320699L: 'I', 4320700L: '\x89', 4320701L: '\xcc'}}, 'disassembly': 'MOV R12, RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_58(self):
''' Instruction MOV R12D, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 7059408L, 'RBX': 7049504L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 7049504L, 'RSI': 4782991L, 'RIP': 4329601L, 'R12D': 4197616L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 4294967295L}, 'memory': {4329601L: 'D', 4329602L: '\x8b', 4329603L: '#', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'text': 'D\x8b#', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782991L, 'RAX': 4294967295L, 'RDI': 7049504L, 'R12D': 4222429316L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329604L, 'RBP': 140737488345936L}, 'memory': {4329601L: 'D', 4329602L: '\x8b', 4329603L: '#', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'MOV R12D, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_59(self):
''' Instruction MOV RBX, [RIP+0x22e8ef] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 0L, 'RDI': 4881624L, 'RAX': 20L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4776850L, 'RBP': 4881624L}, 'memory': {7064705: '\x00', 7064706: '\x00', 7064707: '\x00', 7064708: '\x00', 7064709: '\x00', 7064710: '\x00', 7064711: '\x00', 7064712: '\x80', 7064713: '\xa6', 7064714: 'k', 7064715: '\x00', 7064716: '\x00', 7064717: '\x00', 7064718: '\x00', 7064719: '\x00', 7064720: '\x00', 7064721: '\x00', 7064722: '\x00', 7064723: '\x00', 7064724: '\x00', 7064725: '\x00', 7064726: '\x00', 7064727: '\x00', 7064728: '\x00', 7064729: '\x00', 7064730: '\x00', 7064731: '\x00', 7064732: '\x00', 7064733: '\x00', 7064734: '\x00', 7064735: '\x00', 7064736: '\x00', 7064737: '\x00', 7064738: '\x00', 7064739: '\x00', 7064740: '\x00', 7064741: '\x00', 7064742: '\x00', 7064743: '\x00', 7064744: '\x00', 7064745: '\x00', 7064746: '\x00', 7064747: '\x00', 7064748: '\x00', 7064749: '\x00', 7064750: '\x00', 7064751: '\x00', 7064752: '\x00', 7064753: '\x00', 7064754: '\x00', 7064755: '\x00', 7064756: '\x00', 7064757: '\x00', 7064758: '\x00', 7064759: '\x00', 7064760: '\x00', 7064761: '\x00', 7064762: '\x00', 7064763: '\x00', 7064764: '\x00', 7064765: '\x00', 7064766: '\x00', 7064767: '\x00', 7064768: '\x00', 4776854L: '\xe8', 4776855L: '"', 4776850L: 'H', 4776856L: '\x00', 4776851L: '\x8b', 4776852L: '\x1d', 4776853L: '\xef'}}, 'text': 'H\x8b\x1d\xef\xe8"\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 7054976L, 'RDI': 4881624L, 'RAX': 20L, 'RSP': 140737488346096L, 'RDX': 7058304L, 'RIP': 4776857L, 'RBP': 4881624L}, 'memory': {7064705: '\x00', 7064706: '\x00', 7064707: '\x00', 7064708: '\x00', 7064709: '\x00', 7064710: '\x00', 7064711: '\x00', 7064712: '\x80', 7064713: '\xa6', 7064714: 'k', 7064715: '\x00', 7064716: '\x00', 7064717: '\x00', 7064718: '\x00', 7064719: '\x00', 7064720: '\x00', 7064721: '\x00', 4776850L: 'H', 4776851L: '\x8b', 4776852L: '\x1d', 4776853L: '\xef', 7064726: '\x00', 7064727: '\x00', 7064728: '\x00', 7064729: '\x00', 7064730: '\x00', 7064731: '\x00', 7064732: '\x00', 7064733: '\x00', 7064734: '\x00', 7064735: '\x00', 7064736: '\x00', 7064737: '\x00', 7064738: '\x00', 7064739: '\x00', 7064740: '\x00', 7064741: '\x00', 7064742: '\x00', 7064743: '\x00', 7064744: '\x00', 7064745: '\x00', 7064746: '\x00', 7064747: '\x00', 7064748: '\x00', 7064749: '\x00', 7064750: '\x00', 7064751: '\x00', 7064752: '\x00', 7064753: '\x00', 7064754: '\x00', 7064755: '\x00', 7064756: '\x00', 7064757: '\x00', 7064758: '\x00', 7064759: '\x00', 7064760: '\x00', 7064761: '\x00', 7064762: '\x00', 7064763: '\x00', 7064764: '\x00', 7064765: '\x00', 7064766: '\x00', 7064767: '\x00', 7064768: '\x00', 4776854L: '\xe8', 4776855L: '"', 7064722: '\x00', 4776856L: '\x00', 7064723: '\x00', 7064724: '\x00', 7064725: '\x00'}}, 'disassembly': 'MOV RBX, [RIP+0x22e8ef]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_6(self):
''' Instruction MOV RBP, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 41L, 'RSI': 1L, 'RBX': 140737488346560L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322534L, 'RBP': 140737488347750L}, 'memory': {140737488346603: '\xff', 140737488346619: '\xff', 140737488346609: '\xe3', 140737488346560: 'v', 140737488346561: '\xe2', 140737488346562: '\xff', 140737488346563: '\xff', 140737488346564: '\xff', 140737488346565: '\x7f', 140737488346566: '\x00', 140737488346567: '\x00', 140737488346568: '\x81', 140737488346569: '\xe2', 140737488346570: '\xff', 140737488346571: '\xff', 140737488346572: '\xff', 140737488346573: '\x7f', 140737488346574: '\x00', 140737488346575: '\x00', 140737488346576: '\xd2', 140737488346577: '\xe2', 140737488346578: '\xff', 140737488346579: '\xff', 140737488346580: '\xff', 140737488346581: '\x7f', 140737488346582: '\x00', 140737488346583: '\x00', 140737488346584: '\xf0', 140737488346585: '\xe2', 140737488346586: '\xff', 140737488346587: '\xff', 140737488346588: '\xff', 140737488346589: '\x7f', 140737488346590: '\x00', 140737488346591: '\x00', 140737488346592: '\x02', 140737488346593: '\xe3', 140737488346594: '\xff', 140737488346595: '\xff', 140737488346596: '\xff', 140737488346597: '\x7f', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346598: '\x00', 140737488346602: '\xff', 140737488346599: '\x00', 140737488346604: '\xff', 140737488346605: '\x7f', 140737488346606: '\x00', 140737488346607: '\x00', 140737488346608: '8', 140737488346600: ',', 140737488346610: '\xff', 140737488346611: '\xff', 140737488346612: '\xff', 140737488346613: '\x7f', 140737488346614: '\x00', 140737488346601: '\xe3', 140737488346616: '\xa5', 140737488346617: '\xe3', 140737488346618: '\xff', 140737488346615: '\x00', 140737488346620: '\xff', 140737488346621: '\x7f', 140737488346622: '\x00', 140737488346623: '\x00'}}, 'text': 'H\x8b+', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488347766L}, 'memory': {140737488346603: '\xff', 4322534L: 'H', 140737488346609: '\xe3', 140737488346560: 'v', 140737488346561: '\xe2', 140737488346562: '\xff', 140737488346563: '\xff', 140737488346564: '\xff', 140737488346565: '\x7f', 140737488346566: '\x00', 140737488346567: '\x00', 140737488346568: '\x81', 140737488346569: '\xe2', 140737488346570: '\xff', 140737488346571: '\xff', 140737488346572: '\xff', 140737488346573: '\x7f', 140737488346574: '\x00', 140737488346575: '\x00', 140737488346576: '\xd2', 140737488346577: '\xe2', 140737488346578: '\xff', 140737488346579: '\xff', 140737488346580: '\xff', 140737488346581: '\x7f', 140737488346582: '\x00', 140737488346583: '\x00', 140737488346584: '\xf0', 140737488346585: '\xe2', 140737488346586: '\xff', 140737488346587: '\xff', 140737488346588: '\xff', 140737488346589: '\x7f', 140737488346590: '\x00', 140737488346591: '\x00', 140737488346592: '\x02', 140737488346593: '\xe3', 140737488346594: '\xff', 140737488346595: '\xff', 140737488346596: '\xff', 140737488346597: '\x7f', 140737488346598: '\x00', 140737488346599: '\x00', 140737488346600: ',', 140737488346601: '\xe3', 140737488346602: '\xff', 4322535L: '\x8b', 140737488346604: '\xff', 140737488346605: '\x7f', 140737488346606: '\x00', 140737488346607: '\x00', 140737488346608: '8', 4322536L: '+', 140737488346610: '\xff', 140737488346611: '\xff', 140737488346612: '\xff', 140737488346613: '\x7f', 140737488346614: '\x00', 140737488346615: '\x00', 140737488346616: '\xa5', 140737488346617: '\xe3', 140737488346618: '\xff', 140737488346619: '\xff', 140737488346620: '\xff', 140737488346621: '\x7f', 140737488346622: '\x00', 140737488346623: '\x00'}}, 'disassembly': 'MOV RBP, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_60(self):
''' Instruction MOV EAX, [RCX+0x4] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'EAX': 4222429316L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199142L, 'RBP': 4782912L}, 'memory': {7059435: '\x00', 7059412: '\x01', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x80', 7059417: '\xe8', 7059418: 'k', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 4199142L: '\x8b', 4199143L: 'A', 4199144L: '\x04', 7059433: '\x00', 7059434: '\x00', 7059431: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 7059440: '\x00', 7059432: '\x00', 7059442: '\x00', 7059443: '\x00', 7059430: '\x00', 7059441: '\x00'}}, 'text': '\x8bA\x04', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 1L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199145L, 'RBP': 4782912L}, 'memory': {4199142L: '\x8b', 7059412: '\x01', 7059413: '\x00', 7059414: '\x00', 7059415: '\x00', 7059416: '\x80', 7059417: '\xe8', 7059418: 'k', 7059419: '\x00', 7059420: '\x00', 7059421: '\x00', 7059422: '\x00', 7059423: '\x00', 7059424: '\x00', 7059425: '\x00', 7059426: '\x00', 7059427: '\x00', 7059428: '\x00', 7059429: '\x00', 7059430: '\x00', 4199143L: 'A', 4199144L: '\x04', 7059433: '\x00', 7059434: '\x00', 7059435: '\x00', 7059436: '\x00', 7059437: '\x00', 7059438: '\x00', 7059439: '\x00', 7059440: '\x00', 7059441: '\x00', 7059442: '\x00', 7059443: '\x00', 7059432: '\x00', 7059431: '\x00'}}, 'disassembly': 'MOV EAX, [RCX+0x4]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_61(self):
''' Instruction MOV DWORD [RBP-0x580], 0x1 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338582L, 'RBP': 140737488345936L}, 'memory': {140737488344538: '\x00', 140737488344536: '\x00', 140737488344534: '\x00', 140737488344559: '\x00', 140737488344535: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344528: '\xff', 140737488344529: '\xff', 140737488344530: '\xff', 140737488344531: '\xff', 140737488344532: '\x00', 140737488344533: '\x00', 4338582L: '\xc7', 4338583L: '\x85', 4338584L: '\x80', 4338585L: '\xfa', 4338586L: '\xff', 4338587L: '\xff', 4338588L: '\x01', 4338589L: '\x00', 4338590L: '\x00', 4338591L: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344537: '\x00', 140737488344539: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 140737488344552: '\x00', 140737488344540: '\x00', 140737488344554: '\x00', 140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344558: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344553: '\x00', 140737488344543: '\x00'}}, 'text': '\xc7\x85\x80\xfa\xff\xff\x01\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338592L, 'RBP': 140737488345936L}, 'memory': {140737488344538: '\x00', 140737488344536: '\x00', 140737488344534: '\x00', 140737488344559: '\x00', 140737488344535: '\x00', 140737488344546: '\x00', 140737488344547: '\x00', 140737488344528: '\x01', 140737488344529: '\x00', 140737488344530: '\x00', 140737488344531: '\x00', 140737488344532: '\x00', 140737488344533: '\x00', 4338582L: '\xc7', 4338583L: '\x85', 4338584L: '\x80', 4338585L: '\xfa', 4338586L: '\xff', 4338587L: '\xff', 4338588L: '\x01', 4338589L: '\x00', 4338590L: '\x00', 4338591L: '\x00', 140737488344544: '\x00', 140737488344545: '\x00', 140737488344537: '\x00', 140737488344539: '\x00', 140737488344548: '\x00', 140737488344549: '\x00', 140737488344550: '\x00', 140737488344551: '\x00', 140737488344552: '\x00', 140737488344540: '\x00', 140737488344554: '\x00', 140737488344555: '\x00', 140737488344556: '\x00', 140737488344557: '\x00', 140737488344558: '\x00', 140737488344541: '\x00', 140737488344542: '\x00', 140737488344553: '\x00', 140737488344543: '\x00'}}, 'disassembly': 'MOV DWORD [RBP-0x580], 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_62(self):
''' Instruction MOV R13, [RSP+0x20] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 52L, 'RSI': 140737354125693L, 'RDI': 140737354125691L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392764L, 'RBP': 140737488345936L}, 'memory': {140737488344256: '\x00', 140737488344224: '`', 140737488344225: '\xdb', 140737488344226: '\xff', 140737488344227: '\xff', 140737488344228: '\xff', 140737488344229: '\x7f', 140737488344230: '\x00', 140737488344231: '\x00', 140737488344232: '\xa8', 140737488344233: '\xfb', 140737488344234: 'H', 140737488344235: '\x00', 140737488344236: '\x00', 140737488344237: '\x00', 140737488344238: '\x00', 140737488344239: '\x00', 140737488344240: '\xd0', 140737488344241: '\xff', 140737488344242: '\xff', 140737488344243: '\xff', 140737488344244: '\xff', 140737488344245: '\xff', 140737488344246: '\xff', 140737488344247: '\xff', 140737488344248: '3', 140737488344249: '-', 140737488344250: 'B', 140737488344251: '\x00', 140737488344252: '\x00', 140737488344253: '\x00', 140737488344254: '\x00', 140737488344255: '\x00', 4392768L: ' ', 140737488344257: '\x00', 140737488344258: '\x00', 140737488344259: '\x00', 140737488344260: '\x00', 140737488344261: '\x00', 140737488344262: '\x00', 140737488344263: '\x00', 140737488344264: '\x02', 140737488344265: '\x00', 140737488344266: '\x00', 140737488344267: '\x00', 140737488344268: '\x00', 140737488344269: '\x00', 140737488344270: '\x00', 140737488344271: '\x00', 140737488344272: '\x00', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 140737488344280: '\x00', 140737488344281: '\x00', 140737488344282: '\x00', 140737488344283: '\x00', 140737488344284: '\x00', 140737488344285: '\x00', 140737488344286: '\x00', 140737488344287: '\x00', 4392764L: 'L', 4392765L: '\x8b', 4392766L: 'l', 4392767L: '$'}}, 'text': 'L\x8bl$ ', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 52L, 'RSI': 140737354125693L, 'RDI': 140737354125691L, 'R13': 140737488345952L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392769L, 'RBP': 140737488345936L}, 'memory': {140737488344256: '\x00', 140737488344224: '`', 140737488344225: '\xdb', 140737488344226: '\xff', 140737488344227: '\xff', 140737488344228: '\xff', 140737488344229: '\x7f', 140737488344230: '\x00', 140737488344231: '\x00', 140737488344232: '\xa8', 140737488344233: '\xfb', 140737488344234: 'H', 140737488344235: '\x00', 140737488344236: '\x00', 140737488344237: '\x00', 140737488344238: '\x00', 140737488344239: '\x00', 140737488344240: '\xd0', 140737488344241: '\xff', 140737488344242: '\xff', 140737488344243: '\xff', 140737488344244: '\xff', 140737488344245: '\xff', 140737488344246: '\xff', 140737488344247: '\xff', 140737488344248: '3', 140737488344249: '-', 140737488344250: 'B', 140737488344251: '\x00', 4392764L: 'L', 4392765L: '\x8b', 4392766L: 'l', 4392767L: '$', 4392768L: ' ', 140737488344257: '\x00', 140737488344258: '\x00', 140737488344259: '\x00', 140737488344260: '\x00', 140737488344261: '\x00', 140737488344262: '\x00', 140737488344263: '\x00', 140737488344264: '\x02', 140737488344265: '\x00', 140737488344266: '\x00', 140737488344267: '\x00', 140737488344268: '\x00', 140737488344269: '\x00', 140737488344270: '\x00', 140737488344271: '\x00', 140737488344272: '\x00', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 140737488344280: '\x00', 140737488344281: '\x00', 140737488344282: '\x00', 140737488344283: '\x00', 140737488344284: '\x00', 140737488344285: '\x00', 140737488344286: '\x00', 140737488344287: '\x00', 140737488344252: '\x00', 140737488344253: '\x00', 140737488344254: '\x00', 140737488344255: '\x00'}}, 'disassembly': 'MOV R13, [RSP+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_63(self):
''' Instruction MOV ESI, 0x2f '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1685382481L, 'RSI': 140737488346472L, 'ESI': 4294958440L, 'RDI': 4L, 'RAX': 6L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4291390L, 'RBP': 140737488347312L}, 'memory': {4291392L: '\x00', 4291393L: '\x00', 4291394L: '\x00', 4291390L: '\xbe', 4291391L: '/'}}, 'text': '\xbe/\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1685382481L, 'RSI': 47L, 'ESI': 47L, 'RDI': 4L, 'RAX': 6L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4291395L, 'RBP': 140737488347312L}, 'memory': {4291392L: '\x00', 4291393L: '\x00', 4291394L: '\x00', 4291390L: '\xbe', 4291391L: '/'}}, 'disassembly': 'MOV ESI, 0x2f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_64(self):
''' Instruction MOV [RBP-0x100], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 37L, 'RDI': 4782991L, 'RAX': 206158430216L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329645L, 'RBP': 140737488345936L}, 'memory': {140737488345728: 'L', 140737488345729: 'i', 140737488345730: 'n', 140737488345731: 'u', 140737488345732: 'x', 140737488345733: '\x00', 140737488345734: '\x00', 140737488345735: '\x00', 140737488345736: '\x00', 140737488345737: '\x00', 140737488345738: '\x00', 140737488345739: '\x00', 140737488345740: '\x00', 140737488345741: '\x00', 140737488345742: '\x00', 140737488345743: '\x00', 4329645L: 'H', 4329646L: '\x89', 4329647L: '\x85', 4329648L: '\x00', 4329649L: '\xff', 4329650L: '\xff', 4329651L: '\xff', 140737488345680: '\x08', 140737488345681: '\x00', 140737488345682: '\x00', 140737488345683: '\x00', 140737488345684: '0', 140737488345685: '\x00', 140737488345686: '\x00', 140737488345687: '\x00', 140737488345688: '@', 140737488345689: '\xdc', 140737488345690: '\xff', 140737488345691: '\xff', 140737488345692: '\xff', 140737488345693: '\x7f', 140737488345694: '\x00', 140737488345695: '\x00', 140737488345696: '\x80', 140737488345697: '\xdb', 140737488345698: '\xff', 140737488345699: '\xff', 140737488345700: '\xff', 140737488345701: '\x7f', 140737488345702: '\x00', 140737488345703: '\x00', 140737488345704: '\x00', 140737488345705: '\x00', 140737488345706: '\x00', 140737488345707: '\x00', 140737488345708: '\x00', 140737488345709: '\x00', 140737488345710: '\x00', 140737488345711: '\x00', 140737488345712: '\x00', 140737488345713: '\x00', 140737488345714: '\x00', 140737488345715: '\x00', 140737488345716: '\x00', 140737488345717: '\x00', 140737488345718: '\x00', 140737488345719: '\x00', 140737488345720: 'x', 140737488345721: '\x9a', 140737488345722: 'A', 140737488345723: '\x00', 140737488345724: '\x00', 140737488345725: '\x00', 140737488345726: '\x00', 140737488345727: '\x00'}}, 'text': 'H\x89\x85\x00\xff\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 37L, 'RDI': 4782991L, 'RAX': 206158430216L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329652L, 'RBP': 140737488345936L}, 'memory': {140737488345728: 'L', 140737488345729: 'i', 140737488345730: 'n', 140737488345731: 'u', 140737488345732: 'x', 140737488345733: '\x00', 140737488345734: '\x00', 140737488345735: '\x00', 140737488345736: '\x00', 140737488345737: '\x00', 140737488345738: '\x00', 140737488345739: '\x00', 140737488345740: '\x00', 140737488345741: '\x00', 140737488345742: '\x00', 140737488345743: '\x00', 4329645L: 'H', 4329646L: '\x89', 4329647L: '\x85', 4329648L: '\x00', 4329649L: '\xff', 4329650L: '\xff', 4329651L: '\xff', 140737488345680: '\x08', 140737488345681: '\x00', 140737488345682: '\x00', 140737488345683: '\x00', 140737488345684: '0', 140737488345685: '\x00', 140737488345686: '\x00', 140737488345687: '\x00', 140737488345688: '@', 140737488345689: '\xdc', 140737488345690: '\xff', 140737488345691: '\xff', 140737488345692: '\xff', 140737488345693: '\x7f', 140737488345694: '\x00', 140737488345695: '\x00', 140737488345696: '\x80', 140737488345697: '\xdb', 140737488345698: '\xff', 140737488345699: '\xff', 140737488345700: '\xff', 140737488345701: '\x7f', 140737488345702: '\x00', 140737488345703: '\x00', 140737488345704: '\x00', 140737488345705: '\x00', 140737488345706: '\x00', 140737488345707: '\x00', 140737488345708: '\x00', 140737488345709: '\x00', 140737488345710: '\x00', 140737488345711: '\x00', 140737488345712: '\x00', 140737488345713: '\x00', 140737488345714: '\x00', 140737488345715: '\x00', 140737488345716: '\x00', 140737488345717: '\x00', 140737488345718: '\x00', 140737488345719: '\x00', 140737488345720: 'x', 140737488345721: '\x9a', 140737488345722: 'A', 140737488345723: '\x00', 140737488345724: '\x00', 140737488345725: '\x00', 140737488345726: '\x00', 140737488345727: '\x00'}}, 'disassembly': 'MOV [RBP-0x100], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_65(self):
''' Instruction MOV EDI, EBX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 1685382481L, 'RDX': 140737488346512L, 'RBP': 140737488346472L, 'RDI': 0L, 'RSI': 140737488346472L, 'RSP': 140737488346208L, 'EDI': 0L, 'RIP': 4299747L, 'EBX': 4L, 'RFLAGS': 518L, 'RAX': 6L}, 'memory': {4299747L: '\x89', 4299748L: '\xdf'}}, 'text': '\x89\xdf', 'pos': {'registers': {'RCX': 1685382481L, 'RDX': 140737488346512L, 'RBP': 140737488346472L, 'RDI': 4L, 'RSI': 140737488346472L, 'RSP': 140737488346208L, 'EDI': 4L, 'RIP': 4299749L, 'EBX': 4L, 'RFLAGS': 518L, 'RAX': 6L}, 'memory': {4299747L: '\x89', 4299748L: '\xdf'}}, 'disassembly': 'MOV EDI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_66(self):
''' Instruction MOV [RSP-0x10], R14 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 4782888L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4392457L, 'RBP': 7049504L}, 'memory': {4392457L: 'L', 4392458L: '\x89', 4392459L: 't', 4392460L: '$', 4392461L: '\xf0', 140737488344232: '(', 140737488344233: '\xfb', 140737488344234: 'H', 140737488344235: '\x00', 140737488344236: '\x00', 140737488344237: '\x00', 140737488344238: '\x00', 140737488344239: '\x00', 140737488344240: '\xd0', 140737488344241: '\xff', 140737488344242: '\xff', 140737488344243: '\xff', 140737488344244: '\xff', 140737488344245: '\xff', 140737488344246: '\xff', 140737488344247: '\xff', 140737488344248: '\xa3', 140737488344249: '*', 140737488344250: 'B', 140737488344251: '\x00', 140737488344252: '\x00', 140737488344253: '\x00', 140737488344254: '\x00', 140737488344255: '\x00', 140737488344256: '\x00', 140737488344257: '\x00', 140737488344258: '\x00', 140737488344259: '\x00', 140737488344260: '\x00', 140737488344261: '\x00', 140737488344262: '\x00', 140737488344263: '\x00', 140737488344264: '5', 140737488344265: '\xfb', 140737488344266: 'H', 140737488344267: '\x00', 140737488344268: '\x00', 140737488344269: '\x00', 140737488344270: '\x00', 140737488344271: '\x00', 140737488344272: '\x02', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 140737488344280: '\x00', 140737488344281: '\x00', 140737488344282: '\x00', 140737488344283: '\x00', 140737488344284: '\x00', 140737488344285: '\x00', 140737488344286: '\x00', 140737488344287: '\x00', 140737488344288: '5', 140737488344289: '\xfb', 140737488344290: 'H', 140737488344291: '\x00', 140737488344292: '\x00', 140737488344293: '\x00', 140737488344294: '\x00', 140737488344295: '\x00'}}, 'text': 'L\x89t$\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 4782888L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4392462L, 'RBP': 7049504L}, 'memory': {4392457L: 'L', 4392458L: '\x89', 4392459L: 't', 4392460L: '$', 4392461L: '\xf0', 140737488344232: '(', 140737488344233: '\xfb', 140737488344234: 'H', 140737488344235: '\x00', 140737488344236: '\x00', 140737488344237: '\x00', 140737488344238: '\x00', 140737488344239: '\x00', 140737488344240: '\xd0', 140737488344241: '\xff', 140737488344242: '\xff', 140737488344243: '\xff', 140737488344244: '\xff', 140737488344245: '\xff', 140737488344246: '\xff', 140737488344247: '\xff', 140737488344248: '\xa3', 140737488344249: '*', 140737488344250: 'B', 140737488344251: '\x00', 140737488344252: '\x00', 140737488344253: '\x00', 140737488344254: '\x00', 140737488344255: '\x00', 140737488344256: '\x00', 140737488344257: '\x00', 140737488344258: '\x00', 140737488344259: '\x00', 140737488344260: '\x00', 140737488344261: '\x00', 140737488344262: '\x00', 140737488344263: '\x00', 140737488344264: '5', 140737488344265: '\xfb', 140737488344266: 'H', 140737488344267: '\x00', 140737488344268: '\x00', 140737488344269: '\x00', 140737488344270: '\x00', 140737488344271: '\x00', 140737488344272: '\x02', 140737488344273: '\x00', 140737488344274: '\x00', 140737488344275: '\x00', 140737488344276: '\x00', 140737488344277: '\x00', 140737488344278: '\x00', 140737488344279: '\x00', 140737488344280: '\x00', 140737488344281: '\x00', 140737488344282: '\x00', 140737488344283: '\x00', 140737488344284: '\x00', 140737488344285: '\x00', 140737488344286: '\x00', 140737488344287: '\x00', 140737488344288: '5', 140737488344289: '\xfb', 140737488344290: 'H', 140737488344291: '\x00', 140737488344292: '\x00', 140737488344293: '\x00', 140737488344294: '\x00', 140737488344295: '\x00'}}, 'disassembly': 'MOV [RSP-0x10], R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_67(self):
''' Instruction MOV RAX, RBX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125325L, 'RBX': 2L, 'RDI': 140737354125323L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4782901L, 'RIP': 4392743L, 'RBP': 7049504L}, 'memory': {4392744L: '\x89', 4392745L: '\xd8', 4392743L: 'H'}}, 'text': 'H\x89\xd8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125325L, 'RBX': 2L, 'RDI': 140737354125323L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 4782901L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392744L: '\x89', 4392745L: '\xd8', 4392743L: 'H'}}, 'disassembly': 'MOV RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_68(self):
''' Instruction MOV RBP, RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299660L, 'RBP': 0L}, 'memory': {4299660L: 'H', 4299661L: '\x89', 4299662L: '\xf5'}}, 'text': 'H\x89\xf5', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4299663L, 'RBP': 140737488346472L}, 'memory': {4299660L: 'H', 4299661L: '\x89', 4299662L: '\xf5'}}, 'disassembly': 'MOV RBP, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_69(self):
''' Instruction MOV RBP, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RBX': 140737488346560L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322534L, 'RBP': 140737488347750L}, 'memory': {140737488346603: '\xff', 140737488346619: '\xff', 140737488346609: '\xe3', 140737488346560: 'v', 140737488346561: '\xe2', 140737488346562: '\xff', 140737488346563: '\xff', 140737488346564: '\xff', 140737488346565: '\x7f', 140737488346566: '\x00', 140737488346567: '\x00', 140737488346568: '\x81', 140737488346569: '\xe2', 140737488346570: '\xff', 140737488346571: '\xff', 140737488346572: '\xff', 140737488346573: '\x7f', 140737488346574: '\x00', 140737488346575: '\x00', 140737488346576: '\xd2', 140737488346577: '\xe2', 140737488346578: '\xff', 140737488346579: '\xff', 140737488346580: '\xff', 140737488346581: '\x7f', 140737488346582: '\x00', 140737488346583: '\x00', 140737488346584: '\xf0', 140737488346585: '\xe2', 140737488346586: '\xff', 140737488346587: '\xff', 140737488346588: '\xff', 140737488346589: '\x7f', 140737488346590: '\x00', 140737488346591: '\x00', 140737488346592: '\x02', 140737488346593: '\xe3', 140737488346594: '\xff', 140737488346595: '\xff', 140737488346596: '\xff', 140737488346597: '\x7f', 4322534L: 'H', 4322535L: '\x8b', 4322536L: '+', 140737488346598: '\x00', 140737488346602: '\xff', 140737488346599: '\x00', 140737488346604: '\xff', 140737488346605: '\x7f', 140737488346606: '\x00', 140737488346607: '\x00', 140737488346608: '8', 140737488346600: ',', 140737488346610: '\xff', 140737488346611: '\xff', 140737488346612: '\xff', 140737488346613: '\x7f', 140737488346614: '\x00', 140737488346601: '\xe3', 140737488346616: '\xa5', 140737488346617: '\xe3', 140737488346618: '\xff', 140737488346615: '\x00', 140737488346620: '\xff', 140737488346621: '\x7f', 140737488346622: '\x00', 140737488346623: '\x00'}}, 'text': 'H\x8b+', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322537L, 'RBP': 140737488347766L}, 'memory': {140737488346603: '\xff', 4322534L: 'H', 140737488346609: '\xe3', 140737488346560: 'v', 140737488346561: '\xe2', 140737488346562: '\xff', 140737488346563: '\xff', 140737488346564: '\xff', 140737488346565: '\x7f', 140737488346566: '\x00', 140737488346567: '\x00', 140737488346568: '\x81', 140737488346569: '\xe2', 140737488346570: '\xff', 140737488346571: '\xff', 140737488346572: '\xff', 140737488346573: '\x7f', 140737488346574: '\x00', 140737488346575: '\x00', 140737488346576: '\xd2', 140737488346577: '\xe2', 140737488346578: '\xff', 140737488346579: '\xff', 140737488346580: '\xff', 140737488346581: '\x7f', 140737488346582: '\x00', 140737488346583: '\x00', 140737488346584: '\xf0', 140737488346585: '\xe2', 140737488346586: '\xff', 140737488346587: '\xff', 140737488346588: '\xff', 140737488346589: '\x7f', 140737488346590: '\x00', 140737488346591: '\x00', 140737488346592: '\x02', 140737488346593: '\xe3', 140737488346594: '\xff', 140737488346595: '\xff', 140737488346596: '\xff', 140737488346597: '\x7f', 140737488346598: '\x00', 140737488346599: '\x00', 140737488346600: ',', 140737488346601: '\xe3', 140737488346602: '\xff', 4322535L: '\x8b', 140737488346604: '\xff', 140737488346605: '\x7f', 140737488346606: '\x00', 140737488346607: '\x00', 140737488346608: '8', 4322536L: '+', 140737488346610: '\xff', 140737488346611: '\xff', 140737488346612: '\xff', 140737488346613: '\x7f', 140737488346614: '\x00', 140737488346615: '\x00', 140737488346616: '\xa5', 140737488346617: '\xe3', 140737488346618: '\xff', 140737488346619: '\xff', 140737488346620: '\xff', 140737488346621: '\x7f', 140737488346622: '\x00', 140737488346623: '\x00'}}, 'disassembly': 'MOV RBP, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_7(self):
''' Instruction MOV RBX, RDX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392477L, 'RBP': 7049504L}, 'memory': {4392477L: 'H', 4392478L: '\x89', 4392479L: '\xd3'}}, 'text': 'H\x89\xd3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RBX': 2L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392480L, 'RBP': 7049504L}, 'memory': {4392477L: 'H', 4392478L: '\x89', 4392479L: '\xd3'}}, 'disassembly': 'MOV RBX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_70(self):
''' Instruction MOV [RAX+0x18], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051544L, 'RSP': 140737488345712L, 'RDX': 224L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {7051627: '\x00', 7051629: '\x00', 7051568: '\x00', 7051569: '\x00', 7051570: '\x00', 7051571: '\x00', 7051572: '\x00', 7051573: '\x00', 7051574: '\x00', 7051575: '\x00', 7051576: '\x00', 7051577: '\x00', 7051578: '\x00', 7051579: '\x00', 7051580: '\x00', 7051581: '\x00', 7051582: '\x00', 7051583: '\x00', 7051584: '\x00', 7051585: '\x00', 7051586: '\x00', 7051587: '\x00', 7051588: '\x00', 7051589: '\x00', 7051590: '\x00', 7051591: '\x00', 7051592: '\x00', 7051593: '\x00', 7051594: '\x00', 7051595: '\x00', 7051596: '\x00', 7051597: '\x00', 7051598: '\x00', 7051599: '\x00', 7051600: '\x00', 4211153L: '@', 4211154L: '\x18', 7051603: '\x00', 7051604: '\x00', 7051605: '\x00', 7051606: '\x00', 7051607: '\x00', 7051608: '\x00', 7051609: '\x00', 7051610: '\x00', 7051611: '\x00', 7051612: '\x00', 7051613: '\x00', 7051614: '\x00', 7051615: '\x00', 7051616: '\x00', 7051617: '\x00', 7051618: '\x00', 7051619: '\x00', 7051620: '\x00', 7051621: '\x00', 7051622: '\x00', 7051601: '\x00', 7051624: '\x00', 7051625: '\x00', 7051626: '\x00', 7051623: '\x00', 7051628: '\x00', 7051602: '\x00', 7051630: '\x00', 7051631: '\x00', 4211152L: '\x89', 4211151L: 'H'}}, 'text': 'H\x89@\x18', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051544L, 'RSP': 140737488345712L, 'RDX': 224L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {4211154L: '\x18', 4211153L: '@', 7051568: '\x18', 7051569: '\x99', 7051570: 'k', 7051571: '\x00', 7051572: '\x00', 7051573: '\x00', 7051574: '\x00', 7051575: '\x00', 7051576: '\x00', 7051577: '\x00', 7051578: '\x00', 7051579: '\x00', 7051580: '\x00', 7051581: '\x00', 7051582: '\x00', 7051583: '\x00', 7051584: '\x00', 7051585: '\x00', 7051586: '\x00', 7051587: '\x00', 7051588: '\x00', 7051589: '\x00', 7051590: '\x00', 7051591: '\x00', 7051592: '\x00', 7051593: '\x00', 7051594: '\x00', 7051595: '\x00', 7051596: '\x00', 7051597: '\x00', 7051598: '\x00', 7051599: '\x00', 7051600: '\x00', 7051601: '\x00', 7051602: '\x00', 7051603: '\x00', 7051604: '\x00', 7051605: '\x00', 7051606: '\x00', 7051607: '\x00', 7051608: '\x00', 7051609: '\x00', 7051610: '\x00', 7051611: '\x00', 7051612: '\x00', 7051613: '\x00', 7051614: '\x00', 7051615: '\x00', 7051616: '\x00', 7051617: '\x00', 7051618: '\x00', 7051619: '\x00', 7051620: '\x00', 7051621: '\x00', 7051622: '\x00', 7051623: '\x00', 7051624: '\x00', 7051625: '\x00', 7051626: '\x00', 7051627: '\x00', 7051628: '\x00', 7051629: '\x00', 7051630: '\x00', 7051631: '\x00', 4211152L: '\x89', 4211151L: 'H'}}, 'disassembly': 'MOV [RAX+0x18], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_71(self):
''' Instruction MOV [RAX+0x18], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052984L, 'RSP': 140737488345712L, 'RDX': 1664L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {7053056: '\x00', 7053057: '\x00', 7053058: '\x00', 7053059: '\x00', 7053060: '\x00', 7053061: '\x00', 7053062: '\x00', 7053063: '\x00', 7053064: '\x00', 7053065: '\x00', 7053066: '\x00', 7053067: '\x00', 7053068: '\x00', 7053069: '\x00', 7053070: '\x00', 7053071: '\x00', 7053035: '\x00', 7053037: '\x00', 7053025: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7053011: '\x00', 7053012: '\x00', 7053013: '\x00', 7053014: '\x00', 7053015: '\x00', 7053016: '\x00', 7053017: '\x00', 7053018: '\x00', 7053019: '\x00', 7053020: '\x00', 7053021: '\x00', 7053022: '\x00', 7053023: '\x00', 7053024: '\x00', 7053008: '\x00', 7053026: '\x00', 7053027: '\x00', 7053028: '\x00', 7053029: '\x00', 7053030: '\x00', 7053009: '\x00', 7053032: '\x00', 7053033: '\x00', 7053034: '\x00', 7053031: '\x00', 7053036: '\x00', 7053010: '\x00', 7053038: '\x00', 7053039: '\x00', 7053040: '\x00', 7053041: '\x00', 7053042: '\x00', 7053043: '\x00', 7053044: '\x00', 7053045: '\x00', 7053046: '\x00', 7053047: '\x00', 7053048: '\x00', 7053049: '\x00', 7053050: '\x00', 7053051: '\x00', 7053052: '\x00', 7053053: '\x00', 7053054: '\x00', 7053055: '\x00'}}, 'text': 'H\x89@\x18', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052984L, 'RSP': 140737488345712L, 'RDX': 1664L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7053056: '\x00', 7053057: '\x00', 7053058: '\x00', 7053059: '\x00', 7053060: '\x00', 7053061: '\x00', 7053062: '\x00', 7053063: '\x00', 7053064: '\x00', 7053065: '\x00', 7053066: '\x00', 7053067: '\x00', 7053068: '\x00', 7053069: '\x00', 7053070: '\x00', 7053071: '\x00', 7053010: 'k', 7053008: '\xb8', 7053050: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7053011: '\x00', 7053012: '\x00', 7053013: '\x00', 7053014: '\x00', 7053015: '\x00', 7053016: '\x00', 7053017: '\x00', 7053018: '\x00', 7053019: '\x00', 7053020: '\x00', 7053021: '\x00', 7053022: '\x00', 7053023: '\x00', 7053024: '\x00', 7053025: '\x00', 7053026: '\x00', 7053027: '\x00', 7053028: '\x00', 7053029: '\x00', 7053030: '\x00', 7053031: '\x00', 7053032: '\x00', 7053033: '\x00', 7053034: '\x00', 7053035: '\x00', 7053036: '\x00', 7053037: '\x00', 7053038: '\x00', 7053039: '\x00', 7053040: '\x00', 7053041: '\x00', 7053042: '\x00', 7053043: '\x00', 7053044: '\x00', 7053045: '\x00', 7053046: '\x00', 7053047: '\x00', 7053048: '\x00', 7053049: '\x00', 7053009: '\x9e', 7053051: '\x00', 7053052: '\x00', 7053053: '\x00', 7053054: '\x00', 7053055: '\x00'}}, 'disassembly': 'MOV [RAX+0x18], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_72(self):
''' Instruction MOV [RAX+0x18], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052744L, 'RSP': 140737488345712L, 'RDX': 1424L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {7052800: '\x00', 7052801: '\x00', 7052802: '\x00', 7052803: '\x00', 7052804: '\x00', 7052805: '\x00', 7052806: '\x00', 7052807: '\x00', 7052808: '\x00', 7052809: '\x00', 7052810: '\x00', 7052811: '\x00', 7052812: '\x00', 7052813: '\x00', 7052814: '\x00', 7052815: '\x00', 7052816: '\x00', 7052817: '\x00', 7052818: '\x00', 7052819: '\x00', 7052820: '\x00', 7052821: '\x00', 7052822: '\x00', 7052823: '\x00', 7052824: '\x00', 7052825: '\x00', 7052826: '\x00', 7052827: '\x00', 7052828: '\x00', 7052829: '\x00', 7052830: '\x00', 7052831: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7052768: '\x00', 7052769: '\x00', 7052770: '\x00', 7052771: '\x00', 7052772: '\x00', 7052773: '\x00', 7052774: '\x00', 7052775: '\x00', 7052776: '\x00', 7052777: '\x00', 7052778: '\x00', 7052779: '\x00', 7052780: '\x00', 7052781: '\x00', 7052782: '\x00', 7052783: '\x00', 7052784: '\x00', 7052785: '\x00', 7052786: '\x00', 7052787: '\x00', 7052788: '\x00', 7052789: '\x00', 7052790: '\x00', 7052791: '\x00', 7052792: '\x00', 7052793: '\x00', 7052794: '\x00', 7052795: '\x00', 7052796: '\x00', 7052797: '\x00', 7052798: '\x00', 7052799: '\x00'}}, 'text': 'H\x89@\x18', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7052744L, 'RSP': 140737488345712L, 'RDX': 1424L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7052800: '\x00', 7052801: '\x00', 7052802: '\x00', 7052803: '\x00', 7052804: '\x00', 7052805: '\x00', 7052806: '\x00', 7052807: '\x00', 7052808: '\x00', 7052809: '\x00', 7052810: '\x00', 7052811: '\x00', 7052812: '\x00', 7052813: '\x00', 7052814: '\x00', 7052815: '\x00', 7052816: '\x00', 7052817: '\x00', 7052818: '\x00', 7052819: '\x00', 7052820: '\x00', 7052821: '\x00', 7052822: '\x00', 7052823: '\x00', 7052824: '\x00', 7052825: '\x00', 7052826: '\x00', 7052827: '\x00', 7052828: '\x00', 7052829: '\x00', 7052830: '\x00', 7052831: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7052768: '\xc8', 7052769: '\x9d', 7052770: 'k', 7052771: '\x00', 7052772: '\x00', 7052773: '\x00', 7052774: '\x00', 7052775: '\x00', 7052776: '\x00', 7052777: '\x00', 7052778: '\x00', 7052779: '\x00', 7052780: '\x00', 7052781: '\x00', 7052782: '\x00', 7052783: '\x00', 7052784: '\x00', 7052785: '\x00', 7052786: '\x00', 7052787: '\x00', 7052788: '\x00', 7052789: '\x00', 7052790: '\x00', 7052791: '\x00', 7052792: '\x00', 7052793: '\x00', 7052794: '\x00', 7052795: '\x00', 7052796: '\x00', 7052797: '\x00', 7052798: '\x00', 7052799: '\x00'}}, 'disassembly': 'MOV [RAX+0x18], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_73(self):
''' Instruction MOV RAX, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346760L, 'RDI': 7059520L, 'RAX': 140737488350328L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212893L, 'RBP': 0L}, 'memory': {140737488346760: '\xad', 140737488346761: '\xec', 140737488346762: '\xff', 140737488346763: '\xff', 140737488346764: '\xff', 140737488346765: '\x7f', 140737488346766: '\x00', 140737488346767: '\x00', 140737488346768: '\xbe', 140737488346769: '\xec', 140737488346770: '\xff', 140737488346771: '\xff', 140737488346772: '\xff', 140737488346773: '\x7f', 140737488346774: '\x00', 140737488346775: '\x00', 140737488346776: '\xc5', 140737488346777: '\xec', 140737488346778: '\xff', 140737488346779: '\xff', 140737488346780: '\xff', 4212893L: 'H', 140737488346782: '\x00', 140737488346783: '\x00', 140737488346784: '\xdd', 140737488346785: '\xec', 140737488346786: '\xff', 140737488346787: '\xff', 140737488346788: '\xff', 140737488346789: '\x7f', 140737488346790: '\x00', 140737488346791: '\x00', 140737488346792: '\xf5', 140737488346793: '\xec', 140737488346794: '\xff', 140737488346795: '\xff', 140737488346796: '\xff', 140737488346797: '\x7f', 140737488346798: '\x00', 140737488346781: '\x7f', 140737488346800: '\x00', 140737488346801: '\xed', 140737488346802: '\xff', 140737488346803: '\xff', 140737488346804: '\xff', 140737488346805: '\x7f', 140737488346806: '\x00', 140737488346807: '\x00', 140737488346808: '\t', 140737488346809: '\xed', 140737488346810: '\xff', 140737488346811: '\xff', 140737488346812: '\xff', 140737488346813: '\x7f', 140737488346814: '\x00', 140737488346815: '\x00', 140737488346816: '\x1a', 140737488346817: '\xed', 140737488346818: '\xff', 140737488346819: '\xff', 140737488346820: '\xff', 140737488346821: '\x7f', 140737488346822: '\x00', 140737488346823: '\x00', 4212894L: '\x8b', 4212895L: '\x03', 140737488346799: '\x00'}}, 'text': 'H\x8b\x03', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350381L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {140737488346760: '\xad', 140737488346761: '\xec', 140737488346762: '\xff', 140737488346763: '\xff', 140737488346764: '\xff', 140737488346765: '\x7f', 140737488346766: '\x00', 140737488346767: '\x00', 140737488346768: '\xbe', 140737488346769: '\xec', 140737488346770: '\xff', 140737488346771: '\xff', 140737488346772: '\xff', 140737488346773: '\x7f', 140737488346774: '\x00', 140737488346775: '\x00', 140737488346776: '\xc5', 140737488346777: '\xec', 140737488346778: '\xff', 140737488346779: '\xff', 140737488346780: '\xff', 4212893L: 'H', 140737488346782: '\x00', 140737488346783: '\x00', 140737488346784: '\xdd', 140737488346785: '\xec', 140737488346786: '\xff', 140737488346787: '\xff', 140737488346788: '\xff', 140737488346789: '\x7f', 140737488346790: '\x00', 140737488346791: '\x00', 140737488346792: '\xf5', 140737488346793: '\xec', 140737488346794: '\xff', 140737488346795: '\xff', 140737488346796: '\xff', 140737488346797: '\x7f', 140737488346798: '\x00', 140737488346799: '\x00', 140737488346800: '\x00', 140737488346801: '\xed', 140737488346802: '\xff', 140737488346803: '\xff', 140737488346804: '\xff', 140737488346805: '\x7f', 140737488346806: '\x00', 140737488346807: '\x00', 140737488346808: '\t', 140737488346809: '\xed', 140737488346810: '\xff', 140737488346811: '\xff', 140737488346812: '\xff', 140737488346813: '\x7f', 140737488346814: '\x00', 140737488346815: '\x00', 140737488346816: '\x1a', 140737488346817: '\xed', 140737488346818: '\xff', 140737488346819: '\xff', 140737488346820: '\xff', 140737488346821: '\x7f', 140737488346822: '\x00', 140737488346823: '\x00', 4212894L: '\x8b', 140737488346781: '\x7f', 4212895L: '\x03'}}, 'disassembly': 'MOV RAX, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_74(self):
''' Instruction MOV RDI, [RDI+0x28] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 7049504L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392511L, 'RBP': 7049504L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 4392511L: 'H', 4392512L: '\x8b', 4392513L: '\x7f', 4392514L: '(', 7049544: '\t', 7049545: '\xd0', 7049546: '\xff', 7049547: '\xf7', 7049548: '\xff', 7049549: '\x7f', 7049550: '\x00', 7049551: '\x00', 7049552: '\x00', 7049553: '\xe0', 7049554: '\xff', 7049555: '\xf7', 7049556: '\xff', 7049557: '\x7f', 7049558: '\x00', 7049559: '\x00', 7049560: '\x00', 7049561: '\xd0', 7049562: '\xff', 7049563: '\xf7', 7049564: '\xff', 7049565: '\x7f', 7049566: '\x00', 7049567: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'text': 'H\x8b\x7f(', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392515L, 'RBP': 7049504L}, 'memory': {7049600: '\x00', 7049601: '\x00', 7049602: '\x00', 7049603: '\x00', 7049604: '\x00', 7049605: '\x00', 7049606: '\x00', 7049607: '\x00', 4392511L: 'H', 4392512L: '\x8b', 4392513L: '\x7f', 4392514L: '(', 7049544: '\t', 7049545: '\xd0', 7049546: '\xff', 7049547: '\xf7', 7049548: '\xff', 7049549: '\x7f', 7049550: '\x00', 7049551: '\x00', 7049552: '\x00', 7049553: '\xe0', 7049554: '\xff', 7049555: '\xf7', 7049556: '\xff', 7049557: '\x7f', 7049558: '\x00', 7049559: '\x00', 7049560: '\x00', 7049561: '\xd0', 7049562: '\xff', 7049563: '\xf7', 7049564: '\xff', 7049565: '\x7f', 7049566: '\x00', 7049567: '\x00', 7049568: '\x00', 7049569: '\xe0', 7049570: '\xff', 7049571: '\xf7', 7049572: '\xff', 7049573: '\x7f', 7049574: '\x00', 7049575: '\x00', 7049576: '\x00', 7049577: '\x00', 7049578: '\x00', 7049579: '\x00', 7049580: '\x00', 7049581: '\x00', 7049582: '\x00', 7049583: '\x00', 7049584: '\x00', 7049585: '\x00', 7049586: '\x00', 7049587: '\x00', 7049588: '\x00', 7049589: '\x00', 7049590: '\x00', 7049591: '\x00', 7049592: '\x00', 7049593: '\x00', 7049594: '\x00', 7049595: '\x00', 7049596: '\x00', 7049597: '\x00', 7049598: '\x00', 7049599: '\x00'}}, 'disassembly': 'MOV RDI, [RDI+0x28]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_75(self):
''' Instruction MOV RDX, R13 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'R13': 78L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392872L, 'RBP': 7049504L}, 'memory': {4392872L: 'L', 4392873L: '\x89', 4392874L: '\xea'}}, 'text': 'L\x89\xea', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'R13': 78L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392875L, 'RBP': 7049504L}, 'memory': {4392872L: 'L', 4392873L: '\x89', 4392874L: '\xea'}}, 'disassembly': 'MOV RDX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_76(self):
''' Instruction MOV R15, RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 18446744073709551568L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392488L, 'RBP': 7049504L}, 'memory': {4392488L: 'I', 4392489L: '\x89', 4392490L: '\xf7'}}, 'text': 'I\x89\xf7', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4782991L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 4222429316L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392491L, 'RBP': 7049504L}, 'memory': {4392488L: 'I', 4392489L: '\x89', 4392490L: '\xf7'}}, 'disassembly': 'MOV R15, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_77(self):
''' Instruction MOV R13, [RSP] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 194L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {140737488345888: 'D', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'text': 'L\x8b,$', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320750L, 'RBP': 4792416L}, 'memory': {140737488345888: 'D', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'disassembly': 'MOV R13, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_78(self):
''' Instruction MOV RBX, [RSP+0x8] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RBX': 78L, 'RDI': 140737354125487L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xc5', 140737488346121: '\x12', 140737488346122: '@', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: ' ', 140737488346129: 'Y', 140737488346130: 'k', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 4392749L: 'H', 4392750L: '\x8b', 4392751L: '\\', 4392752L: '$', 4392753L: '\x08', 140737488346072: ' ', 140737488346073: '\x91', 140737488346074: 'k', 140737488346075: '\x00', 140737488346076: '\x00', 140737488346077: '\x00', 140737488346078: '\x00', 140737488346079: '\x00', 140737488346080: '@', 140737488346081: '\xfb', 140737488346082: 'H', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00', 140737488346088: 'N', 140737488346089: '\x00', 140737488346090: '\x00', 140737488346091: '\x00', 140737488346092: '\x00', 140737488346093: '\x00', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x10', 140737488346097: '\x97', 140737488346098: 'k', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'text': 'H\x8b\\$\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RBX': 7049504L, 'RDI': 140737354125487L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392754L, 'RBP': 7049504L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: '\xc5', 140737488346121: '\x12', 140737488346122: '@', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: ' ', 140737488346129: 'Y', 140737488346130: 'k', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 4392749L: 'H', 4392750L: '\x8b', 4392751L: '\\', 4392752L: '$', 4392753L: '\x08', 140737488346072: ' ', 140737488346073: '\x91', 140737488346074: 'k', 140737488346075: '\x00', 140737488346076: '\x00', 140737488346077: '\x00', 140737488346078: '\x00', 140737488346079: '\x00', 140737488346080: '@', 140737488346081: '\xfb', 140737488346082: 'H', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00', 140737488346088: 'N', 140737488346089: '\x00', 140737488346090: '\x00', 140737488346091: '\x00', 140737488346092: '\x00', 140737488346093: '\x00', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x10', 140737488346097: '\x97', 140737488346098: 'k', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'disassembly': 'MOV RBX, [RSP+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_79(self):
''' Instruction MOV [RSP-0x20], R12 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'R12': 140737488346512L, 'RAX': 7065440L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4322357L, 'RBP': 140737488346472L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: 'r', 140737488346121: '\x93', 140737488346122: 'A', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: '\x08', 140737488346129: '\x00', 140737488346130: '\x00', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: 'P', 140737488346137: '\x00', 140737488346138: '\x00', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346144: '0', 140737488346145: '\xe8', 140737488346146: 'k', 140737488346147: '\x00', 140737488346148: '\x00', 140737488346149: '\x00', 140737488346150: '\x00', 140737488346151: '\x00', 4322357L: 'L', 4322358L: '\x89', 4322359L: 'd', 4322360L: '$', 4322361L: '\xe0', 140737488346088: '\x90', 140737488346089: '\xdd', 140737488346090: '\xff', 140737488346091: '\xff', 140737488346092: '\xff', 140737488346093: '\x7f', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x07', 140737488346097: '\x00', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'text': 'L\x89d$\xe0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'R12': 140737488346512L, 'RAX': 7065440L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4322362L, 'RBP': 140737488346472L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: 'r', 140737488346121: '\x93', 140737488346122: 'A', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: '\x08', 140737488346129: '\x00', 140737488346130: '\x00', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 140737488346136: 'P', 140737488346137: '\x00', 140737488346138: '\x00', 140737488346139: '\x00', 140737488346140: '\x00', 140737488346141: '\x00', 140737488346142: '\x00', 140737488346143: '\x00', 140737488346144: '0', 140737488346145: '\xe8', 140737488346146: 'k', 140737488346147: '\x00', 140737488346148: '\x00', 140737488346149: '\x00', 140737488346150: '\x00', 140737488346151: '\x00', 4322357L: 'L', 4322358L: '\x89', 4322359L: 'd', 4322360L: '$', 4322361L: '\xe0', 140737488346088: '\x90', 140737488346089: '\xdd', 140737488346090: '\xff', 140737488346091: '\xff', 140737488346092: '\xff', 140737488346093: '\x7f', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x07', 140737488346097: '\x00', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'disassembly': 'MOV [RSP-0x20], R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_8(self):
''' Instruction MOV DWORD [RBP-0x644], 0x0 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330385L, 'RBP': 140737488345936L}, 'memory': {140737488344342: '\x00', 140737488344343: '\x00', 140737488344332: '\x00', 140737488344333: '\x00', 140737488344334: '\x00', 140737488344335: '\x00', 140737488344336: '\x00', 140737488344337: '\x00', 140737488344338: '\x00', 140737488344339: '\x00', 140737488344340: '\x00', 140737488344341: '\x00', 4330390L: '\xff', 4330391L: '\x00', 140737488344344: '\x00', 140737488344345: '\x00', 140737488344346: '\x00', 140737488344347: '\x00', 140737488344348: '\x00', 140737488344349: '\x00', 140737488344350: '\x00', 140737488344351: '\x00', 140737488344352: '\x00', 140737488344353: '\x00', 140737488344354: '\x00', 140737488344355: '\x00', 140737488344356: '\x00', 140737488344357: '\x00', 140737488344358: '\x00', 140737488344359: '\x00', 140737488344360: '\x00', 140737488344361: '\x00', 140737488344362: '\x00', 140737488344363: '\x00', 4330386L: '\x85', 4330394L: '\x00', 4330392L: '\x00', 4330387L: '\xbc', 4330393L: '\x00', 4330388L: '\xf9', 4330385L: '\xc7', 4330389L: '\xff'}}, 'text': '\xc7\x85\xbc\xf9\xff\xff\x00\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330395L, 'RBP': 140737488345936L}, 'memory': {4330390L: '\xff', 4330391L: '\x00', 140737488344332: '\x00', 140737488344333: '\x00', 140737488344334: '\x00', 140737488344335: '\x00', 140737488344336: '\x00', 140737488344337: '\x00', 140737488344338: '\x00', 140737488344339: '\x00', 140737488344340: '\x00', 140737488344341: '\x00', 140737488344342: '\x00', 140737488344343: '\x00', 140737488344344: '\x00', 140737488344345: '\x00', 140737488344346: '\x00', 140737488344347: '\x00', 140737488344348: '\x00', 140737488344349: '\x00', 140737488344350: '\x00', 140737488344351: '\x00', 140737488344352: '\x00', 140737488344353: '\x00', 140737488344354: '\x00', 140737488344355: '\x00', 140737488344356: '\x00', 140737488344357: '\x00', 140737488344358: '\x00', 140737488344359: '\x00', 140737488344360: '\x00', 140737488344361: '\x00', 140737488344362: '\x00', 140737488344363: '\x00', 4330386L: '\x85', 4330394L: '\x00', 4330392L: '\x00', 4330387L: '\xbc', 4330393L: '\x00', 4330388L: '\xf9', 4330385L: '\xc7', 4330389L: '\xff'}}, 'disassembly': 'MOV DWORD [RBP-0x644], 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_80(self):
''' Instruction MOV RAX, RSI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 52L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327750L, 'RBP': 140737488345936L}, 'memory': {4327752L: '\xf0', 4327750L: 'H', 4327751L: '\x89'}}, 'text': 'H\x89\xf0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327753L, 'RBP': 140737488345936L}, 'memory': {4327752L: '\xf0', 4327750L: 'H', 4327751L: '\x89'}}, 'disassembly': 'MOV RAX, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_81(self):
''' Instruction MOV RDX, R12 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'R12': 4783048L, 'RAX': 140737354125693L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392670L, 'RBP': 7049504L}, 'memory': {4392672L: '\xe2', 4392670L: 'L', 4392671L: '\x89'}}, 'text': 'L\x89\xe2', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 1024L, 'RSI': 4783048L, 'RDI': 140737354125693L, 'R12': 4783048L, 'RAX': 140737354125693L, 'RSP': 140737488344192L, 'RDX': 4783048L, 'RIP': 4392673L, 'RBP': 7049504L}, 'memory': {4392672L: '\xe2', 4392670L: 'L', 4392671L: '\x89'}}, 'disassembly': 'MOV RDX, R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_82(self):
''' Instruction MOV RDX, [RBX+0x88] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RBX': 7049504L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 0L, 'RIP': 4206128L, 'RBP': 1L}, 'memory': {7049687: '\x00', 7049669: '\x00', 7049648: '\xff', 7049649: '\xff', 7049640: '\xd0', 7049641: '\xb7', 7049642: 'k', 7049643: '\x00', 7049644: '\x00', 7049645: '\x00', 7049646: '\x00', 7049647: '\x00', 4206128L: 'H', 4206129L: '\x8b', 7049650: '\xff', 7049651: '\xff', 4206132L: '\x00', 7049653: '\xff', 4206134L: '\x00', 7049655: '\xff', 7049656: '\x00', 7049652: '\xff', 7049658: '\x00', 7049659: '\x00', 7049660: '\x00', 7049661: '\x00', 7049662: '\x00', 7049663: '\x00', 7049664: '`', 7049665: '\x94', 7049666: 'k', 7049667: '\x00', 7049668: '\x00', 7049654: '\xff', 7049670: '\x00', 7049671: '\x00', 7049672: '\x00', 7049673: '\x00', 7049674: '\x00', 7049675: '\x00', 7049676: '\x00', 7049677: '\x00', 7049678: '\x00', 7049679: '\x00', 7049680: '\x00', 7049681: '\xd0', 7049682: '\xff', 7049683: '\xf7', 7049684: '\xff', 7049685: '\x7f', 7049686: '\x00', 7049657: '\x00', 7049688: '\x00', 7049689: '\x10', 7049690: '\x00', 7049691: '\x00', 7049692: '\x00', 7049693: '\x00', 7049694: '\x00', 7049695: '\x00', 7049696: '\xff', 7049697: '\xff', 7049698: '\xff', 7049699: '\xff', 7049700: '\x00', 7049701: '\x00', 7049702: '\x00', 7049703: '\x00', 4206133L: '\x00', 4206131L: '\x88', 4206130L: '\x93'}}, 'text': 'H\x8b\x93\x88\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7059408L, 'RSP': 140737488346112L, 'RDX': 7059408L, 'RIP': 4206135L, 'RBP': 1L}, 'memory': {7049687: '\x00', 7049651: '\xff', 7049669: '\x00', 7049648: '\xff', 7049649: '\xff', 7049640: '\xd0', 7049641: '\xb7', 7049642: 'k', 7049643: '\x00', 7049644: '\x00', 7049645: '\x00', 7049646: '\x00', 7049647: '\x00', 4206128L: 'H', 4206129L: '\x8b', 4206130L: '\x93', 4206131L: '\x88', 4206132L: '\x00', 4206133L: '\x00', 4206134L: '\x00', 7049655: '\xff', 7049656: '\x00', 7049652: '\xff', 7049658: '\x00', 7049659: '\x00', 7049660: '\x00', 7049661: '\x00', 7049662: '\x00', 7049653: '\xff', 7049664: '`', 7049665: '\x94', 7049666: 'k', 7049667: '\x00', 7049668: '\x00', 7049654: '\xff', 7049670: '\x00', 7049671: '\x00', 7049672: '\x00', 7049673: '\x00', 7049674: '\x00', 7049675: '\x00', 7049676: '\x00', 7049677: '\x00', 7049678: '\x00', 7049679: '\x00', 7049680: '\x00', 7049681: '\xd0', 7049682: '\xff', 7049683: '\xf7', 7049684: '\xff', 7049685: '\x7f', 7049686: '\x00', 7049657: '\x00', 7049688: '\x00', 7049689: '\x10', 7049690: '\x00', 7049691: '\x00', 7049692: '\x00', 7049693: '\x00', 7049694: '\x00', 7049695: '\x00', 7049696: '\xff', 7049697: '\xff', 7049698: '\xff', 7049699: '\xff', 7049700: '\x00', 7049701: '\x00', 7049702: '\x00', 7049703: '\x00', 7049650: '\xff', 7049663: '\x00'}}, 'disassembly': 'MOV RDX, [RBX+0x88]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_83(self):
''' Instruction MOV [RSP-0x30], RBX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RBX': 4864625L, 'RDI': 4793925L, 'RAX': 7065352L, 'RSP': 140737488346120L, 'RDX': 50859318435822L, 'RIP': 4322352L, 'RBP': 140737488346472L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: 'N', 140737488346121: '\x93', 140737488346122: 'A', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: '\x08', 140737488346129: '\x00', 140737488346130: '\x00', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 4322352L: 'H', 4322353L: '\x89', 4322354L: '\\', 4322355L: '$', 4322356L: '\xd0', 140737488346072: '\x00', 140737488346073: '\x00', 140737488346074: '\x00', 140737488346075: '\x00', 140737488346076: '\x00', 140737488346077: '\x00', 140737488346078: '\x00', 140737488346079: '\x00', 140737488346080: '\x00', 140737488346081: '\x00', 140737488346082: '\x00', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00', 140737488346088: '\x00', 140737488346089: '\x00', 140737488346090: '\x00', 140737488346091: '\x00', 140737488346092: '\x00', 140737488346093: '\x00', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x00', 140737488346097: '\x00', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'text': 'H\x89\\$\xd0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RBX': 4864625L, 'RDI': 4793925L, 'RAX': 7065352L, 'RSP': 140737488346120L, 'RDX': 50859318435822L, 'RIP': 4322357L, 'RBP': 140737488346472L}, 'memory': {140737488346112: '\x00', 140737488346113: '\x00', 140737488346114: '\x00', 140737488346115: '\x00', 140737488346116: '\x00', 140737488346117: '\x00', 140737488346118: '\x00', 140737488346119: '\x00', 140737488346120: 'N', 140737488346121: '\x93', 140737488346122: 'A', 140737488346123: '\x00', 140737488346124: '\x00', 140737488346125: '\x00', 140737488346126: '\x00', 140737488346127: '\x00', 140737488346128: '\x08', 140737488346129: '\x00', 140737488346130: '\x00', 140737488346131: '\x00', 140737488346132: '\x00', 140737488346133: '\x00', 140737488346134: '\x00', 140737488346135: '\x00', 4322352L: 'H', 4322353L: '\x89', 4322354L: '\\', 4322355L: '$', 4322356L: '\xd0', 140737488346072: 'q', 140737488346073: ':', 140737488346074: 'J', 140737488346075: '\x00', 140737488346076: '\x00', 140737488346077: '\x00', 140737488346078: '\x00', 140737488346079: '\x00', 140737488346080: '\x00', 140737488346081: '\x00', 140737488346082: '\x00', 140737488346083: '\x00', 140737488346084: '\x00', 140737488346085: '\x00', 140737488346086: '\x00', 140737488346087: '\x00', 140737488346088: '\x00', 140737488346089: '\x00', 140737488346090: '\x00', 140737488346091: '\x00', 140737488346092: '\x00', 140737488346093: '\x00', 140737488346094: '\x00', 140737488346095: '\x00', 140737488346096: '\x00', 140737488346097: '\x00', 140737488346098: '\x00', 140737488346099: '\x00', 140737488346100: '\x00', 140737488346101: '\x00', 140737488346102: '\x00', 140737488346103: '\x00', 140737488346104: '\x00', 140737488346105: '\x00', 140737488346106: '\x00', 140737488346107: '\x00', 140737488346108: '\x00', 140737488346109: '\x00', 140737488346110: '\x00', 140737488346111: '\x00'}}, 'disassembly': 'MOV [RSP-0x30], RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_84(self):
''' Instruction MOV [RAX+0x10], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051368L, 'RSP': 140737488345712L, 'RDX': 48L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7051392: 'h', 7051393: '\x98', 7051394: 'k', 7051395: '\x00', 7051396: '\x00', 7051397: '\x00', 7051398: '\x00', 7051399: '\x00', 7051400: '\x00', 7051401: '\x00', 7051402: '\x00', 7051403: '\x00', 7051404: '\x00', 7051405: '\x00', 7051406: '\x00', 7051407: '\x00', 7051408: '\x00', 7051409: '\x00', 7051410: '\x00', 7051411: '\x00', 7051412: '\x00', 7051413: '\x00', 7051414: '\x00', 7051415: '\x00', 7051416: '\x00', 7051417: '\x00', 7051418: '\x00', 7051419: '\x00', 7051420: '\x00', 7051421: '\x00', 7051422: '\x00', 7051423: '\x00', 7051424: '\x00', 7051425: '\x00', 7051426: '\x00', 7051427: '\x00', 7051428: '\x00', 7051429: '\x00', 7051430: '\x00', 7051431: '\x00', 7051432: '\x00', 7051433: '\x00', 7051434: '\x00', 7051435: '\x00', 7051436: '\x00', 7051437: '\x00', 7051438: '\x00', 7051439: '\x00', 7051440: '\x00', 7051441: '\x00', 7051442: '\x00', 7051443: '\x00', 7051444: '\x00', 7051445: '\x00', 7051446: '\x00', 7051447: '\x00', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7051384: '\x00', 7051385: '\x00', 7051386: '\x00', 7051387: '\x00', 7051388: '\x00', 7051389: '\x00', 7051390: '\x00', 7051391: '\x00'}}, 'text': 'H\x89@\x10', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051368L, 'RSP': 140737488345712L, 'RDX': 48L, 'RIP': 4211159L, 'RBP': 7051232L}, 'memory': {7051392: 'h', 7051393: '\x98', 7051394: 'k', 7051395: '\x00', 7051396: '\x00', 7051397: '\x00', 7051398: '\x00', 7051399: '\x00', 7051400: '\x00', 7051401: '\x00', 7051402: '\x00', 7051403: '\x00', 7051404: '\x00', 7051405: '\x00', 7051406: '\x00', 7051407: '\x00', 7051408: '\x00', 7051409: '\x00', 7051410: '\x00', 7051411: '\x00', 7051412: '\x00', 7051413: '\x00', 7051414: '\x00', 7051415: '\x00', 7051416: '\x00', 7051417: '\x00', 7051418: '\x00', 7051419: '\x00', 7051420: '\x00', 7051421: '\x00', 7051422: '\x00', 7051423: '\x00', 7051424: '\x00', 7051425: '\x00', 7051426: '\x00', 7051427: '\x00', 7051428: '\x00', 7051429: '\x00', 7051430: '\x00', 7051431: '\x00', 7051432: '\x00', 7051433: '\x00', 7051434: '\x00', 7051435: '\x00', 7051436: '\x00', 7051437: '\x00', 7051438: '\x00', 7051439: '\x00', 7051440: '\x00', 7051441: '\x00', 7051442: '\x00', 7051443: '\x00', 7051444: '\x00', 7051445: '\x00', 7051446: '\x00', 7051447: '\x00', 4211155L: 'H', 4211156L: '\x89', 4211157L: '@', 4211158L: '\x10', 7051384: 'h', 7051385: '\x98', 7051386: 'k', 7051387: '\x00', 7051388: '\x00', 7051389: '\x00', 7051390: '\x00', 7051391: '\x00'}}, 'disassembly': 'MOV [RAX+0x10], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_85(self):
''' Instruction MOV RDI, [RBP-0x520] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4329913L, 'RBP': 140737488345936L}, 'memory': {140737488344687: '\x00', 4329913L: 'H', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 4329916L: '\xe0', 4329917L: '\xfa', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 140737488344664: '\x00', 140737488344665: '\x00', 140737488344666: '\x00', 140737488344667: '\x00', 140737488344668: '\x00', 140737488344669: '\x00', 140737488344670: '\x00', 140737488344671: '\x00', 140737488344672: '\x00', 140737488344673: '\x00', 140737488344674: '\x00', 140737488344675: '\x00', 140737488344676: '\x00', 140737488344677: '\x00', 140737488344678: '\x00', 140737488344679: '\x00', 140737488344680: '\x00', 140737488344636: '\x00', 140737488344682: '\x00', 140737488344683: '\x00', 140737488344684: '\x00', 140737488344685: '\x00', 140737488344686: '\x00', 140737488344637: '\x00', 4329918L: '\xff', 140737488344681: '\x00', 4329919L: '\xff', 4329915L: '\xbd', 4329914L: '\x8b'}}, 'text': 'H\x8b\xbd\xe0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4329920L, 'RBP': 140737488345936L}, 'memory': {4329916L: '\xe0', 4329917L: '\xfa', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 140737488344664: '\x00', 140737488344665: '\x00', 140737488344666: '\x00', 140737488344667: '\x00', 140737488344668: '\x00', 140737488344669: '\x00', 140737488344670: '\x00', 140737488344671: '\x00', 140737488344672: '\x00', 140737488344673: '\x00', 140737488344674: '\x00', 140737488344675: '\x00', 140737488344676: '\x00', 140737488344677: '\x00', 140737488344678: '\x00', 140737488344679: '\x00', 140737488344680: '\x00', 140737488344681: '\x00', 140737488344682: '\x00', 140737488344683: '\x00', 140737488344684: '\x00', 140737488344685: '\x00', 140737488344686: '\x00', 140737488344687: '\x00', 4329918L: '\xff', 4329913L: 'H', 4329919L: '\xff', 4329915L: '\xbd', 4329914L: '\x8b'}}, 'disassembly': 'MOV RDI, [RBP-0x520]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_86(self):
''' Instruction MOV RSI, R15 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 4792824L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320771L: 'L', 4320772L: '\x89', 4320773L: '\xfe'}}, 'text': 'L\x89\xfe', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792824L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320771L: 'L', 4320772L: '\x89', 4320773L: '\xfe'}}, 'disassembly': 'MOV RSI, R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_87(self):
''' Instruction MOV RAX, [RIP+0x29fab6] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7065472L, 'RSP': 140737488346128L, 'RDX': 7074288L, 'RIP': 4297611L, 'RBP': 140737488346472L}, 'memory': {7048832: '\x00', 4297611L: 'H', 4297612L: '\x8b', 4297613L: '\x05', 4297614L: '\xb6', 4297615L: '\xfa', 4297616L: ')', 4297617L: '\x00', 7048769: '\x97', 7048770: 'k', 7048771: '\x00', 7048772: '\x00', 7048773: '\x00', 7048774: '\x00', 7048775: '\x00', 7048776: 'X', 7048777: '\xcf', 7048778: 'k', 7048779: '\x00', 7048780: '\x00', 7048781: '\x00', 7048782: '\x00', 7048783: '\x00', 7048784: '\x80', 7048785: '\xce', 7048786: 'k', 7048787: '\x00', 7048788: '\x00', 7048789: '\x00', 7048790: '\x00', 7048791: '\x00', 7048792: '`', 7048793: '~', 7048794: 'E', 7048795: '\x00', 7048796: '\x00', 7048797: '\x00', 7048798: '\x00', 7048799: '\x00', 7048800: '\x08', 7048801: '\xc8', 7048802: 'k', 7048803: '\x00', 7048804: '\x00', 7048805: '\x00', 7048806: '\x00', 7048807: '\x00', 7048808: '\x98', 7048809: 'f', 7048810: 'J', 7048811: '\x00', 7048812: '\x00', 7048813: '\x00', 7048814: '\x00', 7048815: '\x00', 7048816: '\x00', 7048817: '\x7f', 7048818: 'k', 7048819: '\x00', 7048820: '\x00', 7048821: '\x00', 7048822: '\x00', 7048823: '\x00', 7048824: ' ', 7048825: '.', 7048826: 'I', 7048827: '\x00', 7048828: '\x00', 7048829: '\x00', 7048830: '\x00', 7048831: '\x00'}}, 'text': 'H\x8b\x05\xb6\xfa)\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7065432L, 'RSP': 140737488346128L, 'RDX': 7074288L, 'RIP': 4297618L, 'RBP': 140737488346472L}, 'memory': {7048832: '\x00', 4297611L: 'H', 4297612L: '\x8b', 4297613L: '\x05', 4297614L: '\xb6', 4297615L: '\xfa', 4297616L: ')', 4297617L: '\x00', 7048769: '\x97', 7048770: 'k', 7048771: '\x00', 7048772: '\x00', 7048773: '\x00', 7048774: '\x00', 7048775: '\x00', 7048776: 'X', 7048777: '\xcf', 7048778: 'k', 7048779: '\x00', 7048780: '\x00', 7048781: '\x00', 7048782: '\x00', 7048783: '\x00', 7048784: '\x80', 7048785: '\xce', 7048786: 'k', 7048787: '\x00', 7048788: '\x00', 7048789: '\x00', 7048790: '\x00', 7048791: '\x00', 7048792: '`', 7048793: '~', 7048794: 'E', 7048795: '\x00', 7048796: '\x00', 7048797: '\x00', 7048798: '\x00', 7048799: '\x00', 7048800: '\x08', 7048801: '\xc8', 7048802: 'k', 7048803: '\x00', 7048804: '\x00', 7048805: '\x00', 7048806: '\x00', 7048807: '\x00', 7048808: '\x98', 7048809: 'f', 7048810: 'J', 7048811: '\x00', 7048812: '\x00', 7048813: '\x00', 7048814: '\x00', 7048815: '\x00', 7048816: '\x00', 7048817: '\x7f', 7048818: 'k', 7048819: '\x00', 7048820: '\x00', 7048821: '\x00', 7048822: '\x00', 7048823: '\x00', 7048824: ' ', 7048825: '.', 7048826: 'I', 7048827: '\x00', 7048828: '\x00', 7048829: '\x00', 7048830: '\x00', 7048831: '\x00'}}, 'disassembly': 'MOV RAX, [RIP+0x29fab6]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_88(self):
''' Instruction MOV R13, R15 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 18446744073709547520L, 'RDX': 131136L, 'RBP': 7051232L, 'RDI': 7051232L, 'R13': 7051352L, 'R15': 135168L, 'RSI': 24L, 'RIP': 4223514L, 'RSP': 140737488345824L, 'RFLAGS': 518L, 'RAX': 1L}, 'memory': {4223514L: 'M', 4223515L: '\x89', 4223516L: '\xfd'}}, 'text': 'M\x89\xfd', 'pos': {'registers': {'RCX': 18446744073709547520L, 'RDX': 131136L, 'RBP': 7051232L, 'RDI': 7051232L, 'R13': 135168L, 'R15': 135168L, 'RSI': 24L, 'RIP': 4223517L, 'RSP': 140737488345824L, 'RFLAGS': 518L, 'RAX': 1L}, 'memory': {4223514L: 'M', 4223515L: '\x89', 4223516L: '\xfd'}}, 'disassembly': 'MOV R13, R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_89(self):
''' Instruction MOV RAX, [RBX] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RBX': 140737488346712L, 'RDI': 7059520L, 'RAX': 140737488350035L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212893L, 'RBP': 0L}, 'memory': {140737488346752: 'x', 140737488346753: '\xec', 140737488346754: '\xff', 140737488346755: '\xff', 140737488346756: '\xff', 140737488346757: '\x7f', 140737488346758: '\x00', 140737488346759: '\x00', 140737488346760: '\xad', 140737488346761: '\xec', 140737488346762: '\xff', 140737488346763: '\xff', 140737488346764: '\xff', 140737488346765: '\x7f', 140737488346766: '\x00', 140737488346767: '\x00', 140737488346768: '\xbe', 140737488346769: '\xec', 140737488346770: '\xff', 140737488346771: '\xff', 140737488346772: '\xff', 140737488346773: '\x7f', 140737488346774: '\x00', 140737488346775: '\x00', 4212893L: 'H', 4212894L: '\x8b', 4212895L: '\x03', 140737488346712: '\xd3', 140737488346713: '\xeb', 140737488346714: '\xff', 140737488346715: '\xff', 140737488346716: '\xff', 140737488346717: '\x7f', 140737488346718: '\x00', 140737488346719: '\x00', 140737488346720: '\xe5', 140737488346721: '\xeb', 140737488346722: '\xff', 140737488346723: '\xff', 140737488346724: '\xff', 140737488346725: '\x7f', 140737488346726: '\x00', 140737488346727: '\x00', 140737488346728: '\xf4', 140737488346729: '\xeb', 140737488346730: '\xff', 140737488346731: '\xff', 140737488346732: '\xff', 140737488346733: '\x7f', 140737488346734: '\x00', 140737488346735: '\x00', 140737488346736: '\x0f', 140737488346737: '\xec', 140737488346738: '\xff', 140737488346739: '\xff', 140737488346740: '\xff', 140737488346741: '\x7f', 140737488346742: '\x00', 140737488346743: '\x00', 140737488346744: 'I', 140737488346745: '\xec', 140737488346746: '\xff', 140737488346747: '\xff', 140737488346748: '\xff', 140737488346749: '\x7f', 140737488346750: '\x00', 140737488346751: '\x00'}}, 'text': 'H\x8b\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350163L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {140737488346752: 'x', 140737488346753: '\xec', 140737488346754: '\xff', 140737488346755: '\xff', 140737488346756: '\xff', 140737488346757: '\x7f', 140737488346758: '\x00', 140737488346759: '\x00', 140737488346760: '\xad', 140737488346761: '\xec', 140737488346762: '\xff', 140737488346763: '\xff', 140737488346764: '\xff', 140737488346765: '\x7f', 140737488346766: '\x00', 140737488346767: '\x00', 140737488346768: '\xbe', 140737488346769: '\xec', 140737488346770: '\xff', 140737488346771: '\xff', 140737488346772: '\xff', 140737488346773: '\x7f', 140737488346774: '\x00', 140737488346775: '\x00', 4212893L: 'H', 4212894L: '\x8b', 4212895L: '\x03', 140737488346712: '\xd3', 140737488346713: '\xeb', 140737488346714: '\xff', 140737488346715: '\xff', 140737488346716: '\xff', 140737488346717: '\x7f', 140737488346718: '\x00', 140737488346719: '\x00', 140737488346720: '\xe5', 140737488346721: '\xeb', 140737488346722: '\xff', 140737488346723: '\xff', 140737488346724: '\xff', 140737488346725: '\x7f', 140737488346726: '\x00', 140737488346727: '\x00', 140737488346728: '\xf4', 140737488346729: '\xeb', 140737488346730: '\xff', 140737488346731: '\xff', 140737488346732: '\xff', 140737488346733: '\x7f', 140737488346734: '\x00', 140737488346735: '\x00', 140737488346736: '\x0f', 140737488346737: '\xec', 140737488346738: '\xff', 140737488346739: '\xff', 140737488346740: '\xff', 140737488346741: '\x7f', 140737488346742: '\x00', 140737488346743: '\x00', 140737488346744: 'I', 140737488346745: '\xec', 140737488346746: '\xff', 140737488346747: '\xff', 140737488346748: '\xff', 140737488346749: '\x7f', 140737488346750: '\x00', 140737488346751: '\x00'}}, 'disassembly': 'MOV RAX, [RBX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_9(self):
''' Instruction MOV R13, [RSP] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320746L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x08', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'text': 'L\x8b,$', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320750L, 'RBP': 4792416L}, 'memory': {140737488345888: '\x08', 140737488345889: '\x00', 140737488345890: '\x00', 140737488345891: '\x00', 140737488345892: '\x00', 140737488345893: '\x00', 140737488345894: '\x00', 140737488345895: '\x00', 140737488345896: '\xc0', 140737488345897: '[', 140737488345898: 'A', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00', 140737488345904: 'p', 140737488345905: '\x06', 140737488345906: '\x00', 140737488345907: '\x00', 140737488345908: '\x00', 140737488345909: '\x00', 140737488345910: '\x00', 140737488345911: '\x00', 140737488345912: '\x03', 140737488345913: 'v', 140737488345914: '\x00', 140737488345915: '\x00', 140737488345916: '\x00', 140737488345917: '\x00', 140737488345918: '\x00', 140737488345919: '\x00', 140737488345920: '\t', 140737488345921: '\x00', 140737488345922: '\x00', 140737488345923: '\x00', 140737488345924: '\x00', 140737488345925: '\x00', 140737488345926: '\x00', 140737488345927: '\x00', 140737488345928: '\xde', 140737488345929: '\xdb', 140737488345930: '\xff', 140737488345931: '\xff', 140737488345932: '\xff', 140737488345933: '\x7f', 140737488345934: '\x00', 140737488345935: '\x00', 140737488345936: '\xc2', 140737488345937: '\x00', 140737488345938: '\x00', 140737488345939: '\x00', 140737488345940: '\x00', 140737488345941: '\x00', 140737488345942: '\x00', 140737488345943: '\x00', 140737488345944: '\xdf', 140737488345945: '\xdb', 140737488345946: '\xff', 140737488345947: '\xff', 140737488345948: '\xff', 140737488345949: '\x7f', 140737488345950: '\x00', 140737488345951: '\x00', 4320746L: 'L', 4320747L: '\x8b', 4320748L: ',', 4320749L: '$'}}, 'disassembly': 'MOV R13, [RSP]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_90(self):
''' Instruction MOV RBX, RDI '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4294967295L, 'RBX': 9L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344184L, 'RDX': 9L, 'RIP': 4397578L, 'RBP': 7049504L}, 'memory': {4397578L: 'H', 4397579L: '\x89', 4397580L: '\xfb'}}, 'text': 'H\x89\xfb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4294967295L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344184L, 'RDX': 9L, 'RIP': 4397581L, 'RBP': 7049504L}, 'memory': {4397578L: 'H', 4397579L: '\x89', 4397580L: '\xfb'}}, 'disassembly': 'MOV RBX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_91(self):
''' Instruction MOV R12, [RSP+0x10] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'R12': 7063824L, 'RAX': 7069696L, 'RSP': 140737488346128L, 'RDX': 7074240L, 'RIP': 4286593L, 'RBP': 80L}, 'memory': {4286593L: 'L', 4286594L: '\x8b', 4286595L: 'd', 4286596L: '$', 4286597L: '\x10', 140737488346144: '@', 140737488346145: '\x00', 140737488346146: '\x00', 140737488346147: '\x00', 140737488346148: '\x00', 140737488346149: '\x00', 140737488346150: '\x00', 140737488346151: '\x00', 140737488346152: 'L', 140737488346153: '\n', 140737488346154: '@', 140737488346155: '\x00', 140737488346156: '\x00', 140737488346157: '\x00', 140737488346158: '\x00', 140737488346159: '\x00', 140737488346160: '\x00', 140737488346161: '\x00', 140737488346162: '\x00', 140737488346163: '\x00', 140737488346164: '\x00', 140737488346165: '\x00', 140737488346166: '\x00', 140737488346167: '\x00', 140737488346168: '\x00', 140737488346169: '\x02', 140737488346170: '@', 140737488346171: '\x00', 140737488346172: '\x00', 140737488346173: '\x00', 140737488346174: '\x00', 140737488346175: '\x00', 140737488346176: '\xc0', 140737488346177: '\x02', 140737488346178: '@', 140737488346179: '\x00', 140737488346180: '\x00', 140737488346181: '\x00', 140737488346182: '\x00', 140737488346183: '\x00', 140737488346184: '\x90', 140737488346185: '\r', 140737488346186: '@', 140737488346187: '\x00', 140737488346188: '\x00', 140737488346189: '\x00', 140737488346190: '\x00', 140737488346191: '\x00', 140737488346192: '\x00', 140737488346193: '\x00', 140737488346194: '\x00', 140737488346195: '\x00', 140737488346196: '\x00', 140737488346197: '\x00', 140737488346198: '\x00', 140737488346199: '\x00', 140737488346200: '\xf0', 140737488346201: '\x0c', 140737488346202: '@', 140737488346203: '\x00', 140737488346204: '\x00', 140737488346205: '\x00', 140737488346206: '\x00', 140737488346207: '\x00'}}, 'text': 'L\x8bd$\x10', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'R12': 64L, 'RAX': 7069696L, 'RSP': 140737488346128L, 'RDX': 7074240L, 'RIP': 4286598L, 'RBP': 80L}, 'memory': {4286593L: 'L', 4286594L: '\x8b', 4286595L: 'd', 4286596L: '$', 4286597L: '\x10', 140737488346144: '@', 140737488346145: '\x00', 140737488346146: '\x00', 140737488346147: '\x00', 140737488346148: '\x00', 140737488346149: '\x00', 140737488346150: '\x00', 140737488346151: '\x00', 140737488346152: 'L', 140737488346153: '\n', 140737488346154: '@', 140737488346155: '\x00', 140737488346156: '\x00', 140737488346157: '\x00', 140737488346158: '\x00', 140737488346159: '\x00', 140737488346160: '\x00', 140737488346161: '\x00', 140737488346162: '\x00', 140737488346163: '\x00', 140737488346164: '\x00', 140737488346165: '\x00', 140737488346166: '\x00', 140737488346167: '\x00', 140737488346168: '\x00', 140737488346169: '\x02', 140737488346170: '@', 140737488346171: '\x00', 140737488346172: '\x00', 140737488346173: '\x00', 140737488346174: '\x00', 140737488346175: '\x00', 140737488346176: '\xc0', 140737488346177: '\x02', 140737488346178: '@', 140737488346179: '\x00', 140737488346180: '\x00', 140737488346181: '\x00', 140737488346182: '\x00', 140737488346183: '\x00', 140737488346184: '\x90', 140737488346185: '\r', 140737488346186: '@', 140737488346187: '\x00', 140737488346188: '\x00', 140737488346189: '\x00', 140737488346190: '\x00', 140737488346191: '\x00', 140737488346192: '\x00', 140737488346193: '\x00', 140737488346194: '\x00', 140737488346195: '\x00', 140737488346196: '\x00', 140737488346197: '\x00', 140737488346198: '\x00', 140737488346199: '\x00', 140737488346200: '\xf0', 140737488346201: '\x0c', 140737488346202: '@', 140737488346203: '\x00', 140737488346204: '\x00', 140737488346205: '\x00', 140737488346206: '\x00', 140737488346207: '\x00'}}, 'disassembly': 'MOV R12, [RSP+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_92(self):
''' Instruction MOV RSI, R15 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 4792824L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320771L, 'RBP': 4792416L}, 'memory': {4320771L: 'L', 4320772L: '\x89', 4320773L: '\xfe'}}, 'text': 'L\x89\xfe', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 4792824L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320774L, 'RBP': 4792416L}, 'memory': {4320771L: 'L', 4320772L: '\x89', 4320773L: '\xfe'}}, 'disassembly': 'MOV RSI, R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_93(self):
''' Instruction MOV R15, R13 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 43L, 'R15': 4792824L, 'RSI': 4792824L, 'RIP': 4320759L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320760L: '\x89', 4320761L: '\xef', 4320759L: 'M'}}, 'text': 'M\x89\xef', 'pos': {'registers': {'RCX': 8L, 'RDX': 134L, 'RBP': 4792416L, 'RDI': 140737488345968L, 'R13': 43L, 'R15': 43L, 'RSI': 4792824L, 'RIP': 4320762L, 'RSP': 140737488345888L, 'RFLAGS': 518L, 'RAX': 4294967295L}, 'memory': {4320760L: '\x89', 4320761L: '\xef', 4320759L: 'M'}}, 'disassembly': 'MOV R15, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_94(self):
''' Instruction MOV R13, [RSP+0x20] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'R13': 7051024L, 'RAX': 79L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199222L, 'RBP': 140737488346224L}, 'memory': {140737488346219: 'i', 140737488346199: '\x00', 140737488346205: '\x00', 140737488346160: '\x07', 140737488346161: '\x00', 140737488346162: '\x00', 140737488346163: '\x00', 140737488346164: '\x00', 140737488346165: '\x00', 140737488346166: '\x00', 4199223L: '\x8b', 4199224L: 'l', 4199225L: '$', 4199226L: ' ', 140737488346171: '\x00', 140737488346172: '\x00', 140737488346173: '\x00', 140737488346174: '\x00', 140737488346175: '\x00', 140737488346176: '\x07', 140737488346177: '\x00', 140737488346178: '\x00', 140737488346179: '\x00', 140737488346180: '\x00', 140737488346181: '\x00', 140737488346182: '\x00', 140737488346183: '\x00', 140737488346184: '\x90', 140737488346185: '\xdd', 140737488346186: '\xff', 140737488346167: '\x00', 140737488346188: '\xff', 140737488346189: '\x7f', 140737488346190: '\x00', 140737488346191: '\x00', 140737488346192: 'h', 140737488346168: 'r', 140737488346194: '\xff', 140737488346195: '\xff', 140737488346196: '\xff', 140737488346197: '\x7f', 140737488346198: '\x00', 140737488346169: '\x05', 140737488346200: '\xf0', 140737488346201: '\x0c', 140737488346202: '@', 140737488346203: '\x00', 140737488346204: '\x04', 140737488346170: '@', 140737488346206: '\x00', 140737488346207: '\x00', 140737488346208: '\x07', 140737488346209: '\x00', 140737488346210: '\x00', 140737488346211: '\x00', 140737488346212: '\x00', 140737488346213: '\x00', 140737488346214: '\x00', 140737488346193: '\xdd', 140737488346216: '\x00', 140737488346217: 'g', 140737488346218: '5', 140737488346215: '\x00', 140737488346220: ':', 140737488346221: 'J', 140737488346222: 's', 140737488346223: '\x89', 140737488346187: '\xff', 4199222L: 'L'}}, 'text': 'L\x8bl$ ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'R13': 7L, 'RAX': 79L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199227L, 'RBP': 140737488346224L}, 'memory': {140737488346169: '\x05', 140737488346160: '\x07', 140737488346161: '\x00', 140737488346162: '\x00', 140737488346163: '\x00', 140737488346164: '\x00', 140737488346165: '\x00', 140737488346166: '\x00', 4199223L: '\x8b', 4199224L: 'l', 4199225L: '$', 4199226L: ' ', 140737488346171: '\x00', 140737488346172: '\x00', 140737488346173: '\x00', 140737488346174: '\x00', 140737488346175: '\x00', 140737488346176: '\x07', 140737488346177: '\x00', 140737488346178: '\x00', 140737488346179: '\x00', 140737488346180: '\x00', 140737488346181: '\x00', 140737488346182: '\x00', 140737488346183: '\x00', 140737488346184: '\x90', 140737488346185: '\xdd', 140737488346186: '\xff', 140737488346167: '\x00', 140737488346188: '\xff', 140737488346189: '\x7f', 140737488346190: '\x00', 140737488346191: '\x00', 140737488346192: 'h', 140737488346168: 'r', 140737488346194: '\xff', 140737488346195: '\xff', 140737488346196: '\xff', 140737488346197: '\x7f', 140737488346198: '\x00', 140737488346199: '\x00', 140737488346200: '\xf0', 140737488346201: '\x0c', 140737488346202: '@', 140737488346203: '\x00', 140737488346204: '\x04', 140737488346205: '\x00', 140737488346206: '\x00', 140737488346207: '\x00', 140737488346208: '\x07', 140737488346209: '\x00', 140737488346210: '\x00', 140737488346211: '\x00', 140737488346212: '\x00', 140737488346213: '\x00', 140737488346214: '\x00', 140737488346215: '\x00', 140737488346216: '\x00', 140737488346217: 'g', 140737488346218: '5', 140737488346219: 'i', 140737488346220: ':', 140737488346221: 'J', 140737488346222: 's', 140737488346223: '\x89', 140737488346187: '\xff', 4199222L: 'L', 140737488346193: '\xdd', 140737488346170: '@'}}, 'disassembly': 'MOV R13, [RSP+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_95(self):
''' Instruction MOV EDX, 0x44 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EDX': 6L, 'RAX': 118L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283898L, 'RBP': 3L}, 'memory': {4283898L: '\xba', 4283899L: 'D', 4283900L: '\x00', 4283901L: '\x00', 4283902L: '\x00'}}, 'text': '\xbaD\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EDX': 68L, 'RAX': 118L, 'RSP': 140737488345968L, 'RDX': 68L, 'RIP': 4283903L, 'RBP': 3L}, 'memory': {4283898L: '\xba', 4283899L: 'D', 4283900L: '\x00', 4283901L: '\x00', 4283902L: '\x00'}}, 'disassembly': 'MOV EDX, 0x44', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_96(self):
''' Instruction MOV RAX, [RIP+0x2afdae] '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 7065872L, 'RIP': 4230059L, 'RBP': 140737488346112L}, 'memory': {7047552: 'x', 7047553: '\xa1', 7047554: 'k', 7047555: '\x00', 7047556: '\x00', 7047557: '\x00', 7047558: '\x00', 7047559: '\x00', 7047560: '\x00', 7047561: '\x00', 7047562: '\x00', 7047563: '\x00', 7047564: '\x00', 7047565: '\x00', 7047566: '\x00', 7047567: '\x00', 7047568: '@', 7047569: 'o', 7047570: 'k', 7047571: '\x00', 7047572: '\x00', 7047573: '\x00', 7047574: '\x00', 7047575: '\x00', 7047576: '\x00', 4230059L: 'H', 4230060L: '\x8b', 4230061L: '\x05', 4230062L: '\xae', 4230063L: '\xfd', 4230064L: '*', 4230065L: '\x00', 7047513: '\xc8', 7047514: 'k', 7047515: '\x00', 7047516: '\x00', 7047517: '\x00', 7047518: '\x00', 7047519: '\x00', 7047520: '\xc0', 7047521: '\x97', 7047522: 'k', 7047523: '\x00', 7047524: '\x00', 7047525: '\x00', 7047526: '\x00', 7047527: '\x00', 7047528: '\x00', 7047529: '\xb8', 7047530: 'k', 7047531: '\x00', 7047532: '\x00', 7047533: '\x00', 7047534: '\x00', 7047535: '\x00', 7047536: '8', 7047537: '\xd0', 7047538: 'k', 7047539: '\x00', 7047540: '\x00', 7047541: '\x00', 7047542: '\x00', 7047543: '\x00', 7047544: '\x10', 7047545: '\x97', 7047546: 'k', 7047547: '\x00', 7047548: '\x00', 7047549: '\x00', 7047550: '\x00', 7047551: '\x00'}}, 'text': 'H\x8b\x05\xae\xfd*\x00', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346032L, 'RDX': 7065872L, 'RIP': 4230066L, 'RBP': 140737488346112L}, 'memory': {7047552: 'x', 7047553: '\xa1', 7047554: 'k', 7047555: '\x00', 7047556: '\x00', 7047557: '\x00', 7047558: '\x00', 7047559: '\x00', 7047560: '\x00', 7047561: '\x00', 7047562: '\x00', 7047563: '\x00', 7047564: '\x00', 7047565: '\x00', 7047566: '\x00', 7047567: '\x00', 7047568: '@', 7047569: 'o', 7047570: 'k', 7047571: '\x00', 7047572: '\x00', 7047573: '\x00', 7047574: '\x00', 7047575: '\x00', 7047576: '\x00', 4230059L: 'H', 4230060L: '\x8b', 4230061L: '\x05', 4230062L: '\xae', 4230063L: '\xfd', 4230064L: '*', 4230065L: '\x00', 7047513: '\xc8', 7047514: 'k', 7047515: '\x00', 7047516: '\x00', 7047517: '\x00', 7047518: '\x00', 7047519: '\x00', 7047520: '\xc0', 7047521: '\x97', 7047522: 'k', 7047523: '\x00', 7047524: '\x00', 7047525: '\x00', 7047526: '\x00', 7047527: '\x00', 7047528: '\x00', 7047529: '\xb8', 7047530: 'k', 7047531: '\x00', 7047532: '\x00', 7047533: '\x00', 7047534: '\x00', 7047535: '\x00', 7047536: '8', 7047537: '\xd0', 7047538: 'k', 7047539: '\x00', 7047540: '\x00', 7047541: '\x00', 7047542: '\x00', 7047543: '\x00', 7047544: '\x10', 7047545: '\x97', 7047546: 'k', 7047547: '\x00', 7047548: '\x00', 7047549: '\x00', 7047550: '\x00', 7047551: '\x00'}}, 'disassembly': 'MOV RAX, [RIP+0x2afdae]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_97(self):
''' Instruction MOV [RDI+0x18], R10 '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035136L, 'R10': 7054432L, 'RDI': 7071792L, 'RAX': 7054432L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245660L, 'RBP': 80L}, 'memory': {7071872: '\x00', 7071873: '\x00', 7071874: '\x00', 7071875: '\x00', 7071876: '\x00', 7071877: '\x00', 7071878: '\x00', 7071879: '\x00', 4245660L: 'L', 4245661L: '\x89', 4245662L: 'W', 4245663L: '\x18', 7071816: '\x00', 7071817: '\x00', 7071818: '\x00', 7071819: '\x00', 7071820: '\x00', 7071821: '\x00', 7071822: '\x00', 7071823: '\x00', 7071824: '\x00', 7071825: '\x00', 7071826: '\x00', 7071827: '\x00', 7071828: '\x00', 7071829: '\x00', 7071830: '\x00', 7071831: '\x00', 7071832: '\x00', 7071833: '\x00', 7071834: '\x00', 7071835: '\x00', 7071836: '\x00', 7071837: '\x00', 7071838: '\x00', 7071839: '\x00', 7071840: '\x00', 7071841: '\x00', 7071842: '\x00', 7071843: '\x00', 7071844: '\x00', 7071845: '\x00', 7071846: '\x00', 7071847: '\x00', 7071848: '\x00', 7071849: '\x00', 7071850: '\x00', 7071851: '\x00', 7071852: '\x00', 7071853: '\x00', 7071854: '\x00', 7071855: '\x00', 7071856: '\x00', 7071857: '\x00', 7071858: '\x00', 7071859: '\x00', 7071860: '\x00', 7071861: '\x00', 7071862: '\x00', 7071863: '\x00', 7071864: '\x00', 7071865: '\x00', 7071866: '\x00', 7071867: '\x00', 7071868: '\x00', 7071869: '\x00', 7071870: '\x00', 7071871: '\x00'}}, 'text': 'L\x89W\x18', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7035136L, 'R10': 7054432L, 'RDI': 7071792L, 'RAX': 7054432L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245664L, 'RBP': 80L}, 'memory': {7071872: '\x00', 7071873: '\x00', 7071874: '\x00', 7071875: '\x00', 7071876: '\x00', 7071877: '\x00', 7071878: '\x00', 7071879: '\x00', 4245660L: 'L', 4245661L: '\x89', 4245662L: 'W', 4245663L: '\x18', 7071816: '`', 7071817: '\xa4', 7071818: 'k', 7071819: '\x00', 7071820: '\x00', 7071821: '\x00', 7071822: '\x00', 7071823: '\x00', 7071824: '\x00', 7071825: '\x00', 7071826: '\x00', 7071827: '\x00', 7071828: '\x00', 7071829: '\x00', 7071830: '\x00', 7071831: '\x00', 7071832: '\x00', 7071833: '\x00', 7071834: '\x00', 7071835: '\x00', 7071836: '\x00', 7071837: '\x00', 7071838: '\x00', 7071839: '\x00', 7071840: '\x00', 7071841: '\x00', 7071842: '\x00', 7071843: '\x00', 7071844: '\x00', 7071845: '\x00', 7071846: '\x00', 7071847: '\x00', 7071848: '\x00', 7071849: '\x00', 7071850: '\x00', 7071851: '\x00', 7071852: '\x00', 7071853: '\x00', 7071854: '\x00', 7071855: '\x00', 7071856: '\x00', 7071857: '\x00', 7071858: '\x00', 7071859: '\x00', 7071860: '\x00', 7071861: '\x00', 7071862: '\x00', 7071863: '\x00', 7071864: '\x00', 7071865: '\x00', 7071866: '\x00', 7071867: '\x00', 7071868: '\x00', 7071869: '\x00', 7071870: '\x00', 7071871: '\x00'}}, 'disassembly': 'MOV [RDI+0x18], R10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_98(self):
''' Instruction MOV [RAX], EDX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'EDX': 0L, 'RAX': 7053688L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4195923L, 'RBP': 0L}, 'memory': {7053696: '\x87', 7053697: "'", 7053698: 'I', 7053699: '\x00', 7053700: '\x00', 7053701: '\x00', 7053702: '\x00', 7053703: '\x00', 7053704: '\xb6', 7053705: "'", 7053706: 'I', 7053707: '\x00', 7053708: '\x00', 7053709: '\x00', 7053710: '\x00', 7053711: '\x00', 7053712: '\x7f', 7053713: '\x03', 7053714: '\x00', 7053715: '\x00', 7053716: '\x08', 7053717: '\x00', 7053718: '\x00', 7053719: '\x00', 7053695: '\x00', 4195923L: '\x89', 7053688: '\x01', 4195924L: '\x10', 7053690: '\x00', 7053691: '\x00', 7053692: '\x00', 7053693: '\x00', 7053694: '\x00', 7053689: '\x00'}}, 'text': '\x89\x10', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'EDX': 0L, 'RAX': 7053688L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4195925L, 'RBP': 0L}, 'memory': {7053696: '\x87', 7053697: "'", 7053698: 'I', 7053699: '\x00', 7053700: '\x00', 7053701: '\x00', 7053702: '\x00', 7053703: '\x00', 7053704: '\xb6', 7053705: "'", 7053706: 'I', 7053707: '\x00', 7053708: '\x00', 7053709: '\x00', 7053710: '\x00', 7053711: '\x00', 7053712: '\x7f', 7053713: '\x03', 7053714: '\x00', 7053715: '\x00', 7053716: '\x08', 7053717: '\x00', 7053718: '\x00', 7053719: '\x00', 7053695: '\x00', 4195923L: '\x89', 7053688: '\x00', 4195924L: '\x10', 7053690: '\x00', 7053691: '\x00', 7053692: '\x00', 7053693: '\x00', 7053694: '\x00', 7053689: '\x00'}}, 'disassembly': 'MOV [RAX], EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMOV_99(self):
''' Instruction MOV [RAX+0x18], RAX '''
test = {'mnemonic': 'MOV', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051464L, 'RSP': 140737488345712L, 'RDX': 144L, 'RIP': 4211151L, 'RBP': 7051232L}, 'memory': {7051520: '\x00', 7051521: '\x00', 7051522: '\x00', 7051523: '\x00', 7051524: '\x00', 7051525: '\x00', 7051526: '\x00', 7051527: '\x00', 7051528: '\x00', 7051529: '\x00', 7051530: '\x00', 7051531: '\x00', 7051532: '\x00', 7051533: '\x00', 7051534: '\x00', 7051535: '\x00', 7051536: '\x00', 7051537: '\x00', 7051538: '\x00', 7051539: '\x00', 7051540: '\x00', 7051541: '\x00', 7051542: '\x00', 7051543: '\x00', 7051544: '\x00', 7051545: '\x00', 7051546: '\x00', 7051547: '\x00', 7051548: '\x00', 7051549: '\x00', 7051550: '\x00', 7051551: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7051488: '\x00', 7051489: '\x00', 7051490: '\x00', 7051491: '\x00', 7051492: '\x00', 7051493: '\x00', 7051494: '\x00', 7051495: '\x00', 7051496: '\x00', 7051497: '\x00', 7051498: '\x00', 7051499: '\x00', 7051500: '\x00', 7051501: '\x00', 7051502: '\x00', 7051503: '\x00', 7051504: '\x00', 7051505: '\x00', 7051506: '\x00', 7051507: '\x00', 7051508: '\x00', 7051509: '\x00', 7051510: '\x00', 7051511: '\x00', 7051512: '\x00', 7051513: '\x00', 7051514: '\x00', 7051515: '\x00', 7051516: '\x00', 7051517: '\x00', 7051518: '\x00', 7051519: '\x00'}}, 'text': 'H\x89@\x18', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051464L, 'RSP': 140737488345712L, 'RDX': 144L, 'RIP': 4211155L, 'RBP': 7051232L}, 'memory': {7051520: '\x00', 7051521: '\x00', 7051522: '\x00', 7051523: '\x00', 7051524: '\x00', 7051525: '\x00', 7051526: '\x00', 7051527: '\x00', 7051528: '\x00', 7051529: '\x00', 7051530: '\x00', 7051531: '\x00', 7051532: '\x00', 7051533: '\x00', 7051534: '\x00', 7051535: '\x00', 7051536: '\x00', 7051537: '\x00', 7051538: '\x00', 7051539: '\x00', 7051540: '\x00', 7051541: '\x00', 7051542: '\x00', 7051543: '\x00', 7051544: '\x00', 7051545: '\x00', 7051546: '\x00', 7051547: '\x00', 7051548: '\x00', 7051549: '\x00', 7051550: '\x00', 7051551: '\x00', 4211151L: 'H', 4211152L: '\x89', 4211153L: '@', 4211154L: '\x18', 7051488: '\xc8', 7051489: '\x98', 7051490: 'k', 7051491: '\x00', 7051492: '\x00', 7051493: '\x00', 7051494: '\x00', 7051495: '\x00', 7051496: '\x00', 7051497: '\x00', 7051498: '\x00', 7051499: '\x00', 7051500: '\x00', 7051501: '\x00', 7051502: '\x00', 7051503: '\x00', 7051504: '\x00', 7051505: '\x00', 7051506: '\x00', 7051507: '\x00', 7051508: '\x00', 7051509: '\x00', 7051510: '\x00', 7051511: '\x00', 7051512: '\x00', 7051513: '\x00', 7051514: '\x00', 7051515: '\x00', 7051516: '\x00', 7051517: '\x00', 7051518: '\x00', 7051519: '\x00'}}, 'disassembly': 'MOV [RAX+0x18], RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_1(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 44L, 'R8': 14757395258967641293L, 'RAX': 44L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2567L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 44L, 'R8': 14757395258967641293L, 'RAX': 3689348814741910332L, 'RSP': 140737488344248L, 'RDX': 35L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_10(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 3L, 'R8': 14757395258967641293L, 'RAX': 3L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 3L, 'R8': 14757395258967641293L, 'RAX': 7378697629483820647L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_2(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 43L, 'R8': 14757395258967641293L, 'RAX': 43L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2567L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 43L, 'R8': 14757395258967641293L, 'RAX': 7378697629483820655L, 'RSP': 140737488344248L, 'RDX': 34L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_3(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_4(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_5(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'R8': 14757395258967641293L, 'RAX': 2L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2695L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'R8': 14757395258967641293L, 'RAX': 11068046444225730970L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_6(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_7(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'R8': 14757395258967641293L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_8(self):
''' Instruction MUL RDX '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 83L, 'RSP': 140737488346080L, 'RDX': 14757395258967641293L, 'RIP': 4520036L, 'RBP': 140737488346112L}, 'memory': {4520036L: 'H', 4520037L: '\xf7', 4520038L: '\xe2'}}, 'text': 'H\xf7\xe2', 'pos': {'registers': {'RFLAGS': 2567L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7378697629483820663L, 'RSP': 140737488346080L, 'RDX': 66L, 'RIP': 4520039L, 'RBP': 140737488346112L}, 'memory': {4520036L: 'H', 4520037L: '\xf7', 4520038L: '\xe2'}}, 'disassembly': 'MUL RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testMUL_9(self):
''' Instruction MUL R8 '''
test = {'mnemonic': 'MUL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 21L, 'R8': 14757395258967641293L, 'RAX': 21L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'text': 'I\xf7\xe0', 'pos': {'registers': {'RFLAGS': 2695L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 21L, 'R8': 14757395258967641293L, 'RAX': 14757395258967641297L, 'RSP': 140737488344248L, 'RDX': 16L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327720L: '\xf7', 4327721L: '\xe0', 4327719L: 'I'}}, 'disassembly': 'MUL R8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x801, test['pos']['registers'][reg_name]&0x801, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testNEG_1(self):
''' Instruction NEG EAX '''
test = {'mnemonic': 'NEG', 'pre': {'registers': {'EAX': 4294967271L, 'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 18446744073709551591L, 'RSP': 140737488343880L, 'RDX': 18446744073709551568L, 'RIP': 4673853L, 'RBP': 18446744073709551568L}, 'memory': {4673853L: '\xf7', 4673854L: '\xd8'}}, 'text': '\xf7\xd8', 'pos': {'registers': {'EAX': 25L, 'RFLAGS': 531L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 25L, 'RSP': 140737488343880L, 'RDX': 18446744073709551568L, 'RIP': 4673855L, 'RBP': 18446744073709551568L}, 'memory': {4673853L: '\xf7', 4673854L: '\xd8'}}, 'disassembly': 'NEG EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testNEG_2(self):
''' Instruction NEG R9 '''
test = {'mnemonic': 'NEG', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074272L, 'RSI': 0L, 'RAX': 7074288L, 'RDI': 7051232L, 'RBP': 140737488346112L, 'RSP': 140737488346080L, 'R9': 80L, 'RIP': 4520106L, 'RDX': 7065472L}, 'memory': {4520106L: 'I', 4520107L: '\xf7', 4520108L: '\xd9'}}, 'text': 'I\xf7\xd9', 'pos': {'registers': {'RFLAGS': 643L, 'RCX': 7074272L, 'RSI': 0L, 'RAX': 7074288L, 'RDI': 7051232L, 'RBP': 140737488346112L, 'RSP': 140737488346080L, 'R9': 18446744073709551536L, 'RIP': 4520109L, 'RDX': 7065472L}, 'memory': {4520106L: 'I', 4520107L: '\xf7', 4520108L: '\xd9'}}, 'disassembly': 'NEG R9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testNEG_3(self):
''' Instruction NEG RAX '''
test = {'mnemonic': 'NEG', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7069759L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 64L, 'RSP': 140737488346160L, 'RDX': 7074240L, 'RIP': 4196959L, 'RBP': 80L}, 'memory': {4196960L: '\xf7', 4196961L: '\xd8', 4196959L: 'H'}}, 'text': 'H\xf7\xd8', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 7069759L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 18446744073709551552L, 'RSP': 140737488346160L, 'RDX': 7074240L, 'RIP': 4196962L, 'RBP': 80L}, 'memory': {4196960L: '\xf7', 4196961L: '\xd8', 4196959L: 'H'}}, 'disassembly': 'NEG RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testNOT_1(self):
''' Instruction NOT RCX '''
test = {'mnemonic': 'NOT', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4095L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223500L, 'RBP': 7051232L}, 'memory': {4223500L: 'H', 4223501L: '\xf7', 4223502L: '\xd1'}}, 'text': 'H\xf7\xd1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709547520L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345824L, 'RDX': 131136L, 'RIP': 4223503L, 'RBP': 7051232L}, 'memory': {4223500L: 'H', 4223501L: '\xf7', 4223502L: '\xd1'}}, 'disassembly': 'NOT RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testNOT_2(self):
''' Instruction NOT R11D '''
test = {'mnemonic': 'NOT', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'R11D': 4294967280L, 'RAX': 4L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285487L, 'RBP': 32768L}, 'memory': {4285488L: '\xf7', 4285489L: '\xd3', 4285487L: 'A'}}, 'text': 'A\xf7\xd3', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'R11D': 15L, 'RAX': 4L, 'RSP': 140737488346144L, 'RDX': 1L, 'RIP': 4285490L, 'RBP': 32768L}, 'memory': {4285488L: '\xf7', 4285489L: '\xd3', 4285487L: 'A'}}, 'disassembly': 'NOT R11D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testNOT_3(self):
''' Instruction NOT RCX '''
test = {'mnemonic': 'NOT', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551610L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4346536L, 'RBP': 140737488345936L}, 'memory': {4346536L: 'H', 4346537L: '\xf7', 4346538L: '\xd1'}}, 'text': 'H\xf7\xd1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737354125325L, 'RDI': 4782910L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4346539L, 'RBP': 140737488345936L}, 'memory': {4346536L: 'H', 4346537L: '\xf7', 4346538L: '\xd1'}}, 'disassembly': 'NOT RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_1(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782997L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4782997L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_10(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782888L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4782888L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_100(self):
''' Instruction OR AH, 0x8 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RDI': 0L, 'AH': 32L, 'RAX': 4222427268L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397740L, 'RBP': 4294967295L}, 'memory': {4397740L: '\x80', 4397741L: '\xcc', 4397742L: '\x08'}}, 'text': '\x80\xcc\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RDI': 0L, 'AH': 40L, 'RAX': 4222429316L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397743L, 'RBP': 4294967295L}, 'memory': {4397740L: '\x80', 4397741L: '\xcc', 4397742L: '\x08'}}, 'disassembly': 'OR AH, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_101(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_11(self):
''' Instruction OR EDX, 0x33 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 275146342400L, 'RSI': 7065696L, 'RDI': 6L, 'EDX': 8L, 'RAX': 4398046511104L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300229L, 'RBP': 1L}, 'memory': {4300229L: '\x83', 4300230L: '\xca', 4300231L: '3'}}, 'text': '\x83\xca3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 275146342400L, 'RSI': 7065696L, 'RDI': 6L, 'EDX': 59L, 'RAX': 4398046511104L, 'RSP': 140737488346168L, 'RDX': 59L, 'RIP': 4300232L, 'RBP': 1L}, 'memory': {4300229L: '\x83', 4300230L: '\xca', 4300231L: '3'}}, 'disassembly': 'OR EDX, 0x33', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_12(self):
''' Instruction OR DWORD [RBX], 0x2 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 140737354125312L, 'RIP': 4203881L, 'RBP': 0L}, 'memory': {4203883L: '\x02', 4203881L: '\x83', 4203882L: '\x0b', 7049504: '\x85', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'text': '\x83\x0b\x02', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 140737354125312L, 'RIP': 4203884L, 'RBP': 0L}, 'memory': {4203883L: '\x02', 4203881L: '\x83', 4203882L: '\x0b', 7049504: '\x87', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'OR DWORD [RBX], 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_13(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_14(self):
''' Instruction OR RAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 137168L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4222909L, 'RBP': 7051232L}, 'memory': {4222912L: '\x01', 4222909L: 'H', 4222910L: '\x83', 4222911L: '\xc8'}}, 'text': 'H\x83\xc8\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 137169L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4222913L, 'RBP': 7051232L}, 'memory': {4222912L: '\x01', 4222909L: 'H', 4222910L: '\x83', 4222911L: '\xc8'}}, 'disassembly': 'OR RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_15(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294963200L, 'RIP': 4248032L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483630L, 'ECX': 0L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 1024L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294963200L, 'RIP': 4248034L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L, 'ECX': 1024L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_16(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_17(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_18(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_19(self):
''' Instruction OR EAX, R8D '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'R8D': 0L, 'RIP': 4336740L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'text': 'D\t\xc0', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'R8D': 0L, 'RIP': 4336743L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'disassembly': 'OR EAX, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_2(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248066L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 1024L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248068L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L, 'ECX': 1024L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_20(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211180L, 'RBP': 7051232L}, 'memory': {4211180L: '\x83', 4211181L: '\xc8', 4211182L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345712L, 'RDX': 2016L, 'RIP': 4211183L, 'RBP': 7051232L}, 'memory': {4211180L: '\x83', 4211181L: '\xc8', 4211182L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_21(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_22(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783022L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4783022L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_23(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248032L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483634L, 'ECX': 57600L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 57634L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248034L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483634L, 'ECX': 57634L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_24(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_25(self):
''' Instruction OR EAX, [RBP-0x5c8] '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336743L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x01', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'text': '\x0b\x858\xfa\xff\xff', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336749L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x01', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'disassembly': 'OR EAX, [RBP-0x5c8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_26(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_27(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_28(self):
''' Instruction OR EAX, [RBP-0x5c8] '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336743L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x03', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'text': '\x0b\x858\xfa\xff\xff', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336749L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x03', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'disassembly': 'OR EAX, [RBP-0x5c8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_29(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_3(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488347312L, 'RSI': 47L, 'ESI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416327L, 'RBP': 140737488347312L}, 'memory': {4416328L: '\xce', 4416329L: '\xff', 4416327L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 140737488347312L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416330L, 'RBP': 140737488347312L}, 'memory': {4416328L: '\xce', 4416329L: '\xff', 4416327L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_30(self):
''' Instruction OR ESI, ECX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'ESI': 2048L, 'RSI': 2048L, 'RIP': 4416410L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L, 'ECX': 0L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'text': '\t\xce', 'pos': {'registers': {'RCX': 0L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'ESI': 2048L, 'RSI': 2048L, 'RIP': 4416412L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347341L, 'ECX': 0L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'disassembly': 'OR ESI, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_31(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783016L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4783016L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_32(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_33(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_34(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_35(self):
''' Instruction OR EAX, R8D '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'R8D': 0L, 'RIP': 4336740L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'text': 'D\t\xc0', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'R8D': 0L, 'RIP': 4336743L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'disassembly': 'OR EAX, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_36(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_37(self):
''' Instruction OR ESI, ECX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 33824L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'ESI': 0L, 'RSI': 0L, 'RIP': 4416410L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L, 'ECX': 33824L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'text': '\t\xce', 'pos': {'registers': {'RCX': 33824L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'ESI': 33824L, 'RSI': 33824L, 'RIP': 4416412L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L, 'ECX': 33824L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'disassembly': 'OR ESI, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_38(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_39(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782903L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4782903L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_4(self):
''' Instruction OR EDI, EAX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 18446744073709551615L, 'RDX': 140737488346512L, 'RBP': 140737488346472L, 'RDI': 831L, 'RSI': 140737488346472L, 'EDI': 831L, 'RIP': 4319826L, 'EAX': 64L, 'RSP': 140737488346200L, 'RFLAGS': 514L, 'RAX': 64L}, 'memory': {4319826L: '\t', 4319827L: '\xc7'}}, 'text': '\t\xc7', 'pos': {'registers': {'RCX': 18446744073709551615L, 'RDX': 140737488346512L, 'RBP': 140737488346472L, 'RDI': 895L, 'RSI': 140737488346472L, 'EDI': 895L, 'RIP': 4319828L, 'EAX': 64L, 'RSP': 140737488346200L, 'RFLAGS': 514L, 'RAX': 64L}, 'memory': {4319826L: '\t', 4319827L: '\xc7'}}, 'disassembly': 'OR EDI, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_40(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_41(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_42(self):
''' Instruction OR RDX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 138785L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222809L, 'RBP': 7051232L}, 'memory': {4222809L: 'H', 4222810L: '\x83', 4222811L: '\xca', 4222812L: '\x01'}}, 'text': 'H\x83\xca\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 138785L, 'RSP': 140737488345824L, 'RDX': 33L, 'RIP': 4222813L, 'RBP': 7051232L}, 'memory': {4222809L: 'H', 4222810L: '\x83', 4222811L: '\xca', 4222812L: '\x01'}}, 'disassembly': 'OR RDX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_43(self):
''' Instruction OR ECX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 1000L, 'ECX': 0L, 'RDI': 140737488347152L, 'RAX': 4297312L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297319L, 'RBP': 0L}, 'memory': {4297320L: '\xc9', 4297321L: '\x01', 4297319L: '\x83'}}, 'text': '\x83\xc9\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 1000L, 'ECX': 1L, 'RDI': 140737488347152L, 'RAX': 4297312L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297322L, 'RBP': 0L}, 'memory': {4297320L: '\xc9', 4297321L: '\x01', 4297319L: '\x83'}}, 'disassembly': 'OR ECX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_44(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_45(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_46(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_47(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_48(self):
''' Instruction OR RCX, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 4782905L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4346527L, 'RBP': 140737488345936L}, 'memory': {4346528L: '\x83', 4346529L: '\xc9', 4346530L: '\xff', 4346527L: 'H'}}, 'text': 'H\x83\xc9\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 140737354125325L, 'RDI': 4782905L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4346531L, 'RBP': 140737488345936L}, 'memory': {4346528L: '\x83', 4346529L: '\xc9', 4346530L: '\xff', 4346527L: 'H'}}, 'disassembly': 'OR RCX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_49(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_5(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_50(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248032L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483619L, 'ECX': 1024L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 1089L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248034L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483619L, 'ECX': 1089L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_51(self):
''' Instruction OR EAX, R8D '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'R8D': 0L, 'RIP': 4336740L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'text': 'D\t\xc0', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967294L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345638L, 'R8D': 0L, 'RIP': 4336743L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'disassembly': 'OR EAX, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_52(self):
''' Instruction OR DWORD [RBX], 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RBX': 7049504L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 7049636L, 'RIP': 4203198L, 'RBP': 7049635L}, 'memory': {4203200L: '\x01', 4203199L: '\x0b', 4203198L: '\x83', 7049504: '\x87', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'text': '\x83\x0b\x01', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 7049636L, 'RIP': 4203201L, 'RBP': 7049635L}, 'memory': {4203200L: '\x01', 4203199L: '\x0b', 4203198L: '\x83', 7049504: '\x87', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'OR DWORD [RBX], 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_53(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_54(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_55(self):
''' Instruction OR EAX, [RBP-0x5c8] '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336743L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'text': '\x0b\x858\xfa\xff\xff', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336749L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'disassembly': 'OR EAX, [RBP-0x5c8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_56(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_57(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248032L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483625L, 'ECX': 1024L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 1089L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248034L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483625L, 'ECX': 1089L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_58(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 254L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248032L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 254L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 4350L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248034L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L, 'ECX': 4350L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_59(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_6(self):
''' Instruction OR EBX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 140737488345859L, 'RDX': 3L, 'RBP': 0L, 'RDI': 1L, 'RSI': 4294967294L, 'RSP': 140737488345728L, 'RIP': 4299480L, 'EDX': 3L, 'EBX': 0L, 'RFLAGS': 514L, 'RAX': 46L}, 'memory': {4299480L: '\t', 4299481L: '\xd3'}}, 'text': '\t\xd3', 'pos': {'registers': {'RCX': 140737488345859L, 'RDX': 3L, 'RBP': 0L, 'RDI': 1L, 'RSI': 4294967294L, 'RSP': 140737488345728L, 'RIP': 4299482L, 'EDX': 3L, 'EBX': 3L, 'RFLAGS': 518L, 'RAX': 46L}, 'memory': {4299480L: '\t', 4299481L: '\xd3'}}, 'disassembly': 'OR EBX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_60(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782899L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4782899L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_61(self):
''' Instruction OR ECX, 0x8 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 0L, 'ECX': 7L, 'RDI': 140737488347200L, 'RAX': 4297216L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297224L, 'RBP': 0L}, 'memory': {4297224L: '\x83', 4297225L: '\xc9', 4297226L: '\x08'}}, 'text': '\x83\xc9\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 15L, 'RSI': 0L, 'ECX': 15L, 'RDI': 140737488347200L, 'RAX': 4297216L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297227L, 'RBP': 0L}, 'memory': {4297224L: '\x83', 4297225L: '\xc9', 4297226L: '\x08'}}, 'disassembly': 'OR ECX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_62(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_63(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 250L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967040L, 'RIP': 4248032L, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 250L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 250L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967040L, 'RIP': 4248034L, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L, 'ECX': 250L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_64(self):
''' Instruction OR EAX, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 25L, 'RFLAGS': 531L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 25L, 'RSP': 140737488343880L, 'RDX': 18446744073709551568L, 'RIP': 4673858L, 'RBP': 18446744073709551568L}, 'memory': {4673858L: '\x83', 4673859L: '\xc8', 4673860L: '\xff'}}, 'text': '\x83\xc8\xff', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4294967295L, 'RSP': 140737488343880L, 'RDX': 18446744073709551568L, 'RIP': 4673861L, 'RBP': 18446744073709551568L}, 'memory': {4673858L: '\x83', 4673859L: '\xc8', 4673860L: '\xff'}}, 'disassembly': 'OR EAX, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_65(self):
''' Instruction OR EBX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 140737488345864L, 'RDX': 5L, 'RBP': 0L, 'RDI': 3L, 'RSI': 4294967293L, 'RSP': 140737488345728L, 'RIP': 4299480L, 'EDX': 5L, 'EBX': 199168L, 'RFLAGS': 518L, 'RAX': 45L}, 'memory': {4299480L: '\t', 4299481L: '\xd3'}}, 'text': '\t\xd3', 'pos': {'registers': {'RCX': 140737488345864L, 'RDX': 5L, 'RBP': 0L, 'RDI': 3L, 'RSI': 4294967293L, 'RSP': 140737488345728L, 'RIP': 4299482L, 'EDX': 5L, 'EBX': 199173L, 'RFLAGS': 518L, 'RAX': 45L}, 'memory': {4299480L: '\t', 4299481L: '\xd3'}}, 'disassembly': 'OR EBX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_66(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_67(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248066L, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 0L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 8L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248068L, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L, 'ECX': 8L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_68(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248032L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483638L, 'ECX': 57600L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 57634L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248034L, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L, 'ECX': 57634L}, 'memory': {4248032L: '\t', 4248033L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_69(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_7(self):
''' Instruction OR EAX, R8D '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'R8D': 0L, 'RIP': 4336740L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'text': 'D\t\xc0', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'R8D': 0L, 'RIP': 4336743L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'disassembly': 'OR EAX, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_70(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_71(self):
''' Instruction OR ESI, ECX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'ESI': 8208L, 'RSI': 8208L, 'RIP': 4416410L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L, 'ECX': 0L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'text': '\t\xce', 'pos': {'registers': {'RCX': 0L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'ESI': 8208L, 'RSI': 8208L, 'RIP': 4416412L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347324L, 'ECX': 0L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'disassembly': 'OR ESI, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_72(self):
''' Instruction OR ESI, ECX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'ESI': 4129L, 'RSI': 4129L, 'RIP': 4416376L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 0L, 'ECX': 0L}, 'memory': {4416376L: '\t', 4416377L: '\xce'}}, 'text': '\t\xce', 'pos': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'ESI': 4129L, 'RSI': 4129L, 'RIP': 4416378L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 0L, 'ECX': 0L}, 'memory': {4416376L: '\t', 4416377L: '\xce'}}, 'disassembly': 'OR ESI, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_73(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_74(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_75(self):
''' Instruction OR EAX, R8D '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 4795649L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'R8D': 0L, 'RIP': 4336740L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'text': 'D\t\xc0', 'pos': {'registers': {'RCX': 4795649L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'R8D': 0L, 'RIP': 4336743L, 'EAX': 0L, 'RSP': 140737488344256L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4336740L: 'D', 4336741L: '\t', 4336742L: '\xc0'}}, 'disassembly': 'OR EAX, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_76(self):
''' Instruction OR EAX, [RBP-0x5c8] '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336743L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'text': '\x0b\x858\xfa\xff\xff', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336749L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'disassembly': 'OR EAX, [RBP-0x5c8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_77(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_78(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_79(self):
''' Instruction OR ESI, ECX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 0L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'ESI': 16L, 'RSI': 16L, 'RIP': 4416410L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L, 'ECX': 0L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'text': '\t\xce', 'pos': {'registers': {'RCX': 0L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'ESI': 16L, 'RSI': 16L, 'RIP': 4416412L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L, 'ECX': 0L}, 'memory': {4416410L: '\t', 4416411L: '\xce'}}, 'disassembly': 'OR ESI, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_8(self):
''' Instruction OR RDX, RCX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 137169L, 'RSP': 140737488345824L, 'RDX': 1617L, 'RIP': 4222917L, 'RBP': 7051232L}, 'memory': {4222917L: 'H', 4222918L: '\t', 4222919L: '\xca'}}, 'text': 'H\t\xca', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 137169L, 'RSP': 140737488345824L, 'RDX': 1617L, 'RIP': 4222920L, 'RBP': 7051232L}, 'memory': {4222917L: 'H', 4222918L: '\t', 4222919L: '\xca'}}, 'disassembly': 'OR RDX, RCX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_80(self):
''' Instruction OR EAX, [RBP-0x5c8] '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336743L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'text': '\x0b\x858\xfa\xff\xff', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336749L, 'RBP': 140737488345936L}, 'memory': {4336747L: '\xff', 140737488344456: '\x00', 140737488344457: '\x00', 140737488344458: '\x00', 140737488344459: '\x00', 140737488344460: '\x00', 140737488344461: '\x00', 140737488344462: '\x00', 140737488344463: '\x00', 140737488344464: '\x00', 140737488344465: '\x00', 140737488344466: '\x00', 140737488344467: '\x00', 140737488344468: '\x00', 140737488344469: '\x00', 140737488344470: '\x00', 140737488344471: '\x00', 140737488344472: '\xff', 140737488344473: '\xff', 140737488344474: '\xff', 140737488344475: '\xff', 140737488344476: '\xff', 140737488344477: '\xff', 140737488344478: '\xff', 140737488344479: '\xff', 140737488344480: '\x00', 140737488344481: '\x00', 140737488344482: '\x00', 140737488344483: '\x00', 140737488344484: '\x00', 140737488344485: '\x00', 140737488344486: '\x00', 140737488344487: '\x00', 4336744L: '\x85', 4336745L: '8', 4336746L: '\xfa', 4336743L: '\x0b', 4336748L: '\xff'}}, 'disassembly': 'OR EAX, [RBP-0x5c8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_81(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_82(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783036L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4783036L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_83(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248066L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L, 'ECX': 1024L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 1089L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248068L, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L, 'ECX': 1089L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_84(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_85(self):
''' Instruction OR ECX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 254L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248066L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 254L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'text': '\t\xd1', 'pos': {'registers': {'RCX': 4350L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248068L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L, 'ECX': 4350L}, 'memory': {4248066L: '\t', 4248067L: '\xd1'}}, 'disassembly': 'OR ECX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_86(self):
''' Instruction OR RAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222805L, 'RBP': 7051232L}, 'memory': {4222808L: '\x01', 4222805L: 'H', 4222806L: '\x83', 4222807L: '\xc8'}}, 'text': 'H\x83\xc8\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 138785L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222809L, 'RBP': 7051232L}, 'memory': {4222808L: '\x01', 4222805L: 'H', 4222806L: '\x83', 4222807L: '\xc8'}}, 'disassembly': 'OR RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_87(self):
''' Instruction OR EAX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 18446744073709551615L, 'RDX': 1L, 'RBP': 8192L, 'RDI': 1L, 'RSI': 140737488343968L, 'RIP': 4661331L, 'EAX': 0L, 'EDX': 1L, 'RSP': 140737488343968L, 'RFLAGS': 582L, 'RAX': 0L}, 'memory': {4661331L: '\t', 4661332L: '\xd0'}}, 'text': '\t\xd0', 'pos': {'registers': {'RCX': 18446744073709551615L, 'RDX': 1L, 'RBP': 8192L, 'RDI': 1L, 'RSI': 140737488343968L, 'RIP': 4661333L, 'EAX': 1L, 'EDX': 1L, 'RSP': 140737488343968L, 'RFLAGS': 514L, 'RAX': 1L}, 'memory': {4661331L: '\t', 4661332L: '\xd0'}}, 'disassembly': 'OR EAX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_88(self):
''' Instruction OR EDX, 0x8 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 7065696L, 'RDI': 6L, 'EDX': 0L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4300166L, 'RBP': 1L}, 'memory': {4300168L: '\x08', 4300166L: '\x83', 4300167L: '\xca'}}, 'text': '\x83\xca\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 7065696L, 'RDI': 6L, 'EDX': 8L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300169L, 'RBP': 1L}, 'memory': {4300168L: '\x08', 4300166L: '\x83', 4300167L: '\xca'}}, 'disassembly': 'OR EDX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_89(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_9(self):
''' Instruction OR ECX, 0x2 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 0L, 'ECX': 1L, 'RDI': 140737488347168L, 'RAX': 4297280L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297287L, 'RBP': 0L}, 'memory': {4297288L: '\xc9', 4297289L: '\x02', 4297287L: '\x83'}}, 'text': '\x83\xc9\x02', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 3L, 'RSI': 0L, 'ECX': 3L, 'RDI': 140737488347168L, 'RAX': 4297280L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297290L, 'RBP': 0L}, 'memory': {4297288L: '\xc9', 4297289L: '\x02', 4297287L: '\x83'}}, 'disassembly': 'OR ECX, 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_90(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_91(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_92(self):
''' Instruction OR EBX, EDX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RCX': 140737488345862L, 'RDX': 10L, 'RBP': 0L, 'RDI': 2L, 'RSI': 4294967294L, 'RSP': 140737488345728L, 'RIP': 4299480L, 'EDX': 10L, 'EBX': 768L, 'RFLAGS': 514L, 'RAX': 46L}, 'memory': {4299480L: '\t', 4299481L: '\xd3'}}, 'text': '\t\xd3', 'pos': {'registers': {'RCX': 140737488345862L, 'RDX': 10L, 'RBP': 0L, 'RDI': 2L, 'RSI': 4294967294L, 'RSP': 140737488345728L, 'RIP': 4299482L, 'EDX': 10L, 'EBX': 778L, 'RFLAGS': 518L, 'RAX': 46L}, 'memory': {4299480L: '\t', 4299481L: '\xd3'}}, 'disassembly': 'OR EBX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_93(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783042L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4783042L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_94(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_95(self):
''' Instruction OR R15, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 138816L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223952L, 'RBP': 7051232L}, 'memory': {4223952L: 'I', 4223953L: '\x83', 4223954L: '\xcf', 4223955L: '\x01'}}, 'text': 'I\x83\xcf\x01', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 138817L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223956L, 'RBP': 7051232L}, 'memory': {4223952L: 'I', 4223953L: '\x83', 4223954L: '\xcf', 4223955L: '\x01'}}, 'disassembly': 'OR R15, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_96(self):
''' Instruction OR ESI, -0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4783048L, 'RSI': 37L, 'ESI': 37L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'text': '\x83\xce\xff', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 4783048L, 'RSI': 4294967295L, 'ESI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247994L, 'RBP': 140737488345936L}, 'memory': {4247992L: '\xce', 4247993L: '\xff', 4247991L: '\x83'}}, 'disassembly': 'OR ESI, -0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_97(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_98(self):
''' Instruction OR EAX, 0x1 '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'text': '\x83\xc8\x01', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {4283339L: '\x83', 4283340L: '\xc8', 4283341L: '\x01'}}, 'disassembly': 'OR EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testOR_99(self):
''' Instruction OR RDX, RBX '''
test = {'mnemonic': 'OR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074240L, 'RSI': 7074272L, 'RBX': 0L, 'RDI': 7213056L, 'RAX': 138785L, 'RSP': 140737488345824L, 'RDX': 33L, 'RIP': 4222813L, 'RBP': 7051232L}, 'memory': {4222813L: 'H', 4222814L: '\t', 4222815L: '\xda'}}, 'text': 'H\t\xda', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074240L, 'RSI': 7074272L, 'RBX': 0L, 'RDI': 7213056L, 'RAX': 138785L, 'RSP': 140737488345824L, 'RDX': 33L, 'RIP': 4222816L, 'RBP': 7051232L}, 'memory': {4222813L: 'H', 4222814L: '\t', 4222815L: '\xda'}}, 'disassembly': 'OR RDX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_1(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4794117: ' ', 4794118: 'f', 4794119: 'a', 4794120: 'i', 4794121: 'l', 4794122: 'e', 4794123: 'd', 4794124: '.', 4794125: '\n', 4794126: '%', 4794127: 'n', 4794128: '\x00', 4794129: '\x00', 4794130: '\x00', 4794131: '\x00', 4794132: '\x00', 4794133: '\x00', 4794134: '\x00', 4794135: '\x00', 4794136: '\x00', 4794137: '\x00', 4794138: '\x00', 4794139: '\x00', 4794140: '\x00', 4794141: '\x00', 4794142: '\x00', 4794143: '\x00', 4794144: 'U', 4794145: 'n', 4794146: 'e', 4794147: 'x', 4794148: 'p', 4794149: 'e', 4794150: 'c', 4794151: 't', 4794152: 'e', 4794153: 'd', 4794154: ' ', 4794155: 'e', 4794156: 'r', 4794157: 'r', 4794158: 'o', 4794159: 'r', 4794160: '.', 4794161: '\n', 4794162: '\x00', 4794163: '\x00', 4794164: '\x8c', 4794165: '{', 4794166: '\xf8', 4794167: '\xff', 4794168: '|', 4794169: '{', 4794170: '\xf8', 4794171: '\xff', 4794172: 'l', 4794173: '{', 4794174: '\xf8', 4794175: '\xff', 4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 280375465082880, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4794117: ' ', 4794118: 'f', 4794119: 'a', 4794120: 'i', 4794121: 'l', 4794122: 'e', 4794123: 'd', 4794124: '.', 4794125: '\n', 4794126: '%', 4794127: 'n', 4794128: '\x00', 4794129: '\x00', 4794130: '\x00', 4794131: '\x00', 4794132: '\x00', 4794133: '\x00', 4794134: '\x00', 4794135: '\x00', 4794136: '\x00', 4794137: '\x00', 4794138: '\x00', 4794139: '\x00', 4794140: '\x00', 4794141: '\x00', 4794142: '\x00', 4794143: '\x00', 4794144: 'U', 4794145: 'n', 4794146: 'e', 4794147: 'x', 4794148: 'p', 4794149: 'e', 4794150: 'c', 4794151: 't', 4794152: 'e', 4794153: 'd', 4794154: ' ', 4794155: 'e', 4794156: 'r', 4794157: 'r', 4794158: 'o', 4794159: 'r', 4794160: '.', 4794161: '\n', 4794162: '\x00', 4794163: '\x00', 4794164: '\x8c', 4794165: '{', 4794166: '\xf8', 4794167: '\xff', 4794168: '|', 4794169: '{', 4794170: '\xf8', 4794171: '\xff', 4794172: 'l', 4794173: '{', 4794174: '\xf8', 4794175: '\xff', 4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_10(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_11(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248050L, 'XMM0': 61743963450839848825131331291115975791L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248054L, 'XMM0': 4278190080, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_12(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_13(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416396L, 'XMM2': 0, 'XMM3': 261712993146723386499317935668814697L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416400L, 'XMM2': 0, 'XMM3': 338953138925461823674472811186503024640L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_14(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_15(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_16(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_17(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416392L, 'XMM0': 154696462191076794052440873859912395888L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416396L, 'XMM0': 1095216660480, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_18(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_19(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 6596154662119929836862747976992L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 280375465148160, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_2(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 101360535869359638812712377514826163237L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 71776119061217535, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_20(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416392L, 'XMM0': 145391946241709797809872351733278401133L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416396L, 'XMM0': 78918677504442992524819169280L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_21(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 7059408L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 7059408L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_22(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248050L, 'XMM0': 101360535869359638812712377514826163237L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248054L, 'XMM0': 71776119061217535, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_23(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4794117: ' ', 4794118: 'f', 4794119: 'a', 4794120: 'i', 4794121: 'l', 4794122: 'e', 4794123: 'd', 4794124: '.', 4794125: '\n', 4794126: '%', 4794127: 'n', 4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 71776119061217280, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4794117: ' ', 4794118: 'f', 4794119: 'a', 4794120: 'i', 4794121: 'l', 4794122: 'e', 4794123: 'd', 4794124: '.', 4794125: '\n', 4794126: '%', 4794127: 'n', 4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_24(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416354L, 'XMM2': 0, 'XMM3': 132098688466593534319927079450625140783L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416354L: 'f', 4416355L: '\x0f', 4416356L: 't', 4416357L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416358L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416354L: 'f', 4416355L: '\x0f', 4416356L: 't', 4416357L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_25(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 5L, 'RDX': 1L, 'RBP': 140737488346472L, 'RDI': 4793989L, 'RSI': 4294967264L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 113401473871765646839159859486903977036L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 5L, 'RDX': 1L, 'RBP': 140737488346472L, 'RDI': 4793989L, 'RSI': 4294967264L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 113401473871765646839159859486903977036L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_26(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_27(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_28(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416396L, 'XMM2': 0, 'XMM3': 161434664049216810285368497307980294507L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416400L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_29(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_3(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 101360535869359638812712377514826163237L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 71776119061217535, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_30(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_31(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_32(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_33(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 5L, 'RDX': 50859318435822L, 'RBP': 140737488346472L, 'RDI': 4793925L, 'RSI': 140737488346472L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86826932514745123378012629685768242252L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 5L, 'RDX': 50859318435822L, 'RBP': 140737488346472L, 'RDI': 4793925L, 'RSI': 140737488346472L, 'RIP': 4239609L, 'XMM0': 18374686479671623680L, 'XMM1': 86826932514745123378012629685768242252L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_34(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_35(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_36(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248054L, 'XMM2': 0, 'XMM3': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248058L, 'XMM2': 0, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_37(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_38(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 94376511227379241736154044347596226881L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 1324035698926381045275276563951124480L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_39(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 6596154662119929836862747976992L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 280375465148160, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_4(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_40(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 61743963450839848825131331291115975791L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_41(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 129103300273056613552361913363439026186L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 20203181441137406086353707335680L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_42(self):
''' Instruction PCMPEQB XMM0, [RAX] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 53L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239633L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4794117: ' ', 4794118: 'f', 4794119: 'a', 4794120: 'i', 4794121: 'l', 4794122: 'e', 4794123: 'd', 4794124: '.', 4794125: '\n', 4794126: '%', 4794127: 'n', 4794128: '\x00', 4239633L: 'f', 4239634L: '\x0f', 4239635L: 't', 4239636L: '\x00', 4794133: '\x00', 4794134: '\x00', 4794135: '\x00', 4794136: '\x00', 4794137: '\x00', 4794138: '\x00', 4794139: '\x00', 4794140: '\x00', 4794141: '\x00', 4794142: '\x00', 4794143: '\x00', 4794144: 'U', 4794145: 'n', 4794146: 'e', 4794147: 'x', 4794148: 'p', 4794149: 'e', 4794150: 'c', 4794151: 't', 4794152: 'e', 4794153: 'd', 4794154: ' ', 4794155: 'e', 4794156: 'r', 4794157: 'r', 4794158: 'o', 4794159: 'r', 4794129: '\x00', 4794130: '\x00', 4794131: '\x00', 4794132: '\x00', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'text': 'f\x0ft\x00', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 1095216660480, 'RCX': 53L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239637L, 'RBP': 140737488346472L}, 'memory': {4794112: ' ', 4794113: '`', 4794114: '%', 4794115: 's', 4794116: "'", 4794117: ' ', 4794118: 'f', 4794119: 'a', 4794120: 'i', 4794121: 'l', 4794122: 'e', 4794123: 'd', 4794124: '.', 4794125: '\n', 4794126: '%', 4794127: 'n', 4794128: '\x00', 4794129: '\x00', 4794130: '\x00', 4794131: '\x00', 4794132: '\x00', 4794133: '\x00', 4794134: '\x00', 4794135: '\x00', 4794136: '\x00', 4794137: '\x00', 4794138: '\x00', 4794139: '\x00', 4794140: '\x00', 4794141: '\x00', 4794142: '\x00', 4794143: '\x00', 4794144: 'U', 4794145: 'n', 4794146: 'e', 4794147: 'x', 4794148: 'p', 4794149: 'e', 4794150: 'c', 4794151: 't', 4794152: 'e', 4794153: 'd', 4794154: ' ', 4794155: 'e', 4794156: 'r', 4794157: 'r', 4794158: 'o', 4794159: 'r', 4239633L: 'f', 4239634L: '\x0f', 4239635L: 't', 4239636L: '\x00', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'disassembly': 'PCMPEQB XMM0, [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_43(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 61743963450839848825131331291115975791L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 4278190080, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_44(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248050L, 'XMM0': 43040918620421324091436533114482288498L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248054L, 'XMM0': 308276084001730439550074880L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_45(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_46(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 140737488346472L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 1095216660480, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 140737488346472L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%', 4794096: 'u', 4794097: ':', 4794098: ' ', 4794099: '%', 4794100: 's', 4794101: '%', 4794102: 's', 4794103: 'A', 4794104: 's', 4794105: 's', 4794106: 'e', 4794107: 'r', 4794108: 't', 4794109: 'i', 4794110: 'o', 4794111: 'n'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_47(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 94376511227379241736154044347596226881L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 0, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_48(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_49(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_5(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_50(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_51(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_52(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 7059408L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 7059408L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_53(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_54(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_55(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 101360535869359638812712377514826163237L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_56(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_57(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_58(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_59(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_6(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_60(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248054L, 'XMM2': 0, 'XMM3': 43040918620421324091436533114482288498L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248058L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_61(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 154763657361063560226840681733874122753L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 0, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_62(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 13L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793933L, 'RSI': 140737488346472L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 375554270925848303279633040492414028L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 13L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793933L, 'RSI': 140737488346472L, 'RIP': 4239609L, 'XMM0': 338953138925153547590470800371487866880L, 'XMM1': 375554270925848303279633040492414028L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_63(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 129103300273056613552361913363439026186L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 20203181441137406086353707335680L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_64(self):
''' Instruction PCMPEQB XMM3, [RAX+0x40] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239719L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'text': 'f\x0ftX@', 'pos': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239724L, 'RBP': 4782912L}, 'memory': {4239719L: 'f', 4239720L: '\x0f', 4239721L: 't', 4239722L: 'X', 4239723L: '@', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00', 4783088: 'F', 4783089: 'A', 4783090: 'T', 4783091: 'A', 4783092: 'L', 4783093: ':', 4783094: ' ', 4783095: 'c', 4783096: 'a', 4783097: 'n', 4783098: 'n', 4783099: 'o', 4783100: 't', 4783101: ' ', 4783102: 'd', 4783103: 'e'}}, 'disassembly': 'PCMPEQB XMM3, [RAX+0x40]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_65(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_66(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_67(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 41L, 'RDX': 1L, 'RBP': 140737488346472L, 'RDI': 4793961L, 'RSI': 1L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 90882157140230411661358273883331839052L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 41L, 'RDX': 1L, 'RBP': 140737488346472L, 'RDI': 4793961L, 'RSI': 1L, 'RIP': 4239609L, 'XMM0': 78918677504442992524819169280L, 'XMM1': 90882157140230411661358273883331839052L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_68(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416392L, 'XMM0': 261712993146723386499317935668814697L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416396L, 'XMM0': 0, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_69(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_7(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 43040918620421324091436533114482288498L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_70(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248050L, 'XMM0': 129103300273056613552361913363439026186L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248054L, 'XMM0': 20203181441137406086353707335680L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_71(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_72(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 29L, 'RDX': 7074288L, 'RBP': 140737488346472L, 'RDI': 4793949L, 'RSI': 1L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 88223701148664206693009503650295268428L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 29L, 'RDX': 7074288L, 'RBP': 140737488346472L, 'RDI': 4793949L, 'RSI': 1L, 'RIP': 4239609L, 'XMM0': 78918677504442992524819169280L, 'XMM1': 88223701148664206693009503650295268428L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_73(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416396L, 'XMM2': 0, 'XMM3': 154696462191076794052440873859912395888L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416400L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_74(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416392L, 'XMM0': 161434664049216810285368497307980294507L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416396L, 'XMM0': 5172014448931175958107644294594560L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416392L: 'f', 4416393L: '\x0f', 4416394L: 't', 4416395L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_75(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416350L, 'XMM0': 132098688466593534319927079450625140783L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416352L: 't', 4416353L: '\xc1', 4416350L: 'f', 4416351L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416354L, 'XMM0': 20203181441137406366729172418815L, 'XMM1': 62718710765820030520700417840365121327L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416352L: 't', 4416353L: '\xc1', 4416350L: 'f', 4416351L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_76(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_77(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248054L, 'XMM2': 0, 'XMM3': 129103300273056613552361913363439026186L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248058L, 'XMM2': 0, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_78(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248050L, 'XMM0': 6596154662119929836862747976992L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248054L, 'XMM0': 280375465148160, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248050L: 'f', 4248051L: '\x0f', 4248052L: 't', 4248053L: '\xc1'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_79(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248054L, 'XMM2': 0, 'XMM3': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248058L, 'XMM2': 0, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_8(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_80(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_81(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416396L, 'XMM2': 0, 'XMM3': 145391946241709797809872351733278401133L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416400L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416396L: 'f', 4416397L: '\x0f', 4416398L: 't', 4416399L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_82(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 154763657361063560226840681733874122753L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 18446744073692839680L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_83(self):
''' Instruction PCMPEQB XMM1, [RAX+0x20] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239693L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'text': 'f\x0ftH ', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239698L, 'RBP': 4782912L}, 'memory': {4239693L: 'f', 4239694L: '\x0f', 4239695L: 't', 4239696L: 'H', 4239697L: ' ', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd'}}, 'disassembly': 'PCMPEQB XMM1, [RAX+0x20]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_84(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_85(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM2': 0, 'XMM3': 6596154662119929836862747976992L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967295L, 'RIP': 4248022L, 'XMM2': 0, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248018L: 'f', 4248019L: '\x0f', 4248020L: 't', 4248021L: '\xda'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_86(self):
''' Instruction PCMPEQB XMM0, [RAX] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239633L, 'RBP': 140737488346472L}, 'memory': {4239633L: 'f', 4239634L: '\x0f', 4239635L: 't', 4239636L: '\x00', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%'}}, 'text': 'f\x0ft\x00', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 1095216660480, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239637L, 'RBP': 140737488346472L}, 'memory': {4239633L: 'f', 4239634L: '\x0f', 4239635L: 't', 4239636L: '\x00', 4793968: '_', 4793969: 'N', 4793970: 'O', 4793971: 'T', 4793972: '\x00', 4793973: 'L', 4793974: 'D', 4793975: '_', 4793976: 'D', 4793977: 'Y', 4793978: 'N', 4793979: 'A', 4793980: 'M', 4793981: 'I', 4793982: 'C', 4793983: '_', 4793984: 'W', 4793985: 'E', 4793986: 'A', 4793987: 'K', 4793988: '\x00', 4793989: 'L', 4793990: 'D', 4793991: '_', 4793992: 'P', 4793993: 'R', 4793994: 'O', 4793995: 'F', 4793996: 'I', 4793997: 'L', 4793998: 'E', 4793999: '_', 4794000: 'O', 4794001: 'U', 4794002: 'T', 4794003: 'P', 4794004: 'U', 4794005: 'T', 4794006: '\x00', 4794007: '/', 4794008: 'e', 4794009: 't', 4794010: 'c', 4794011: '/', 4794012: 's', 4794013: 'u', 4794014: 'i', 4794015: 'd', 4794016: '-', 4794017: 'd', 4794018: 'e', 4794019: 'b', 4794020: 'u', 4794021: 'g', 4794022: '\x00', 4794023: 'M', 4794024: 'A', 4794025: 'L', 4794026: 'L', 4794027: 'O', 4794028: 'C', 4794029: '_', 4794030: 'C', 4794031: 'H', 4794032: 'E', 4794033: 'C', 4794034: 'K', 4794035: '_', 4794036: '\x00', 4794037: 'L', 4794038: 'D', 4794039: '_', 4794040: 'A', 4794041: 'S', 4794042: 'S', 4794043: 'U', 4794044: 'M', 4794045: 'E', 4794046: '_', 4794047: 'K', 4794048: 'E', 4794049: 'R', 4794050: 'N', 4794051: 'E', 4794052: 'L', 4794053: '\x00', 4794054: '/', 4794055: 'p', 4794056: 'r', 4794057: 'o', 4794058: 'c', 4794059: '/', 4794060: 's', 4794061: 'y', 4794062: 's', 4794063: '/', 4794064: 'k', 4794065: 'e', 4794066: 'r', 4794067: 'n', 4794068: 'e', 4794069: 'l', 4794070: '/', 4794071: 'o', 4794072: 's', 4794073: 'r', 4794074: 'e', 4794075: 'l', 4794076: 'e', 4794077: 'a', 4794078: 's', 4794079: 'e', 4794080: '\x00', 4794081: '\x00', 4794082: '\x00', 4794083: '\x00', 4794084: '\x00', 4794085: '\x00', 4794086: '\x00', 4794087: '\x00', 4794088: '%', 4794089: 's', 4794090: '%', 4794091: 's', 4794092: '%', 4794093: 's', 4794094: ':', 4794095: '%'}}, 'disassembly': 'PCMPEQB XMM0, [RAX]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_87(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239605L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'XMM1': 86738642548474510294585684247313465665L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239608L: '\xc1', 4239605L: 'f', 4239606L: '\x0f', 4239607L: 't'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_88(self):
''' Instruction PCMPEQB XMM0, XMM1 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248014L, 'XMM0': 43040918620421324091436533114482288498L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'text': 'f\x0ft\xc1', 'pos': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294967295L, 'RIP': 4248018L, 'XMM0': 308276084001730439550074880L, 'XMM1': 49374304219900875090764158725393818917L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248016L: 't', 4248017L: '\xc1', 4248014L: 'f', 4248015L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM0, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_89(self):
''' Instruction PCMPEQB XMM2, [RAX+0x30] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239706L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'text': 'f\x0ftP0', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239711L, 'RBP': 4782912L}, 'memory': {4239706L: 'f', 4239707L: '\x0f', 4239708L: 't', 4239709L: 'P', 4239710L: '0', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L', 4783056: ':', 4783057: ' ', 4783058: 'k', 4783059: 'e', 4783060: 'r', 4783061: 'n', 4783062: 'e', 4783063: 'l', 4783064: ' ', 4783065: 't', 4783066: 'o', 4783067: 'o', 4783068: ' ', 4783069: 'o', 4783070: 'l', 4783071: 'd', 4783072: '\n', 4783073: '\x00', 4783074: '/', 4783075: 'd', 4783076: 'e', 4783077: 'v', 4783078: '/', 4783079: 'u', 4783080: 'r', 4783081: 'a', 4783082: 'n', 4783083: 'd', 4783084: 'o', 4783085: 'm', 4783086: '\x00', 4783087: '\x00'}}, 'disassembly': 'PCMPEQB XMM2, [RAX+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_9(self):
''' Instruction PCMPEQB XMM3, XMM2 '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248054L, 'XMM2': 0, 'XMM3': 61743963450839848825131331291115975791L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'text': 'f\x0ft\xda', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248058L, 'XMM2': 0, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248056L: 't', 4248057L: '\xda', 4248054L: 'f', 4248055L: '\x0f'}}, 'disassembly': 'PCMPEQB XMM3, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPCMPEQB_90(self):
''' Instruction PCMPEQB XMM0, [RAX+0x10] '''
test = {'mnemonic': 'PCMPEQB', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239680L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'text': 'f\x0ft@\x10', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239685L, 'RBP': 4782912L}, 'memory': {4239680L: 'f', 4239681L: '\x0f', 4239682L: 't', 4239683L: '@', 4239684L: '\x10', 4782928: 'A', 4782929: 'A', 4782930: 'A', 4782931: 'A', 4782932: 'A', 4782933: 'A', 4782934: 'A', 4782935: 'A', 4782936: 'A', 4782937: 'A', 4782938: 'A', 4782939: 'A', 4782940: 'A', 4782941: 'A', 4782942: 'A', 4782943: 'A', 4782944: 'A', 4782945: 'A', 4782946: 'A', 4782947: 'A', 4782948: 'A', 4782949: 'A', 4782950: 'A', 4782951: 'A', 4782952: 'A', 4782953: 'A', 4782954: 'A', 4782955: 'A', 4782956: 'A', 4782957: 'A', 4782958: 'A', 4782959: 'A', 4782960: 'A', 4782961: 'A', 4782962: 'A', 4782963: 'A', 4782964: 'A', 4782965: 'A', 4782966: 'A', 4782967: 'A', 4782968: 'A', 4782969: 'A', 4782970: 'A', 4782971: 'A', 4782972: 'A', 4782973: 'A', 4782974: 'A', 4782975: 'A', 4782976: 'A', 4782977: 'A', 4782978: 'A', 4782979: 'A', 4782980: 'A', 4782981: 'A', 4782982: 'A', 4782983: 'A', 4782984: 'A', 4782985: 'A', 4782986: 'A', 4782987: 'A', 4782988: 'A', 4782989: 'A', 4782990: '\x00', 4782991: 'G', 4782992: 'o', 4782993: 't', 4782994: ' ', 4782995: '%', 4782996: 'd', 4782997: ' ', 4782998: 'a', 4782999: 'r', 4783000: 'g', 4783001: 'u', 4783002: 'm', 4783003: 'e', 4783004: 'n', 4783005: 't', 4783006: 's', 4783007: '.', 4783008: '\n', 4783009: '\x00', 4783010: '\x00', 4783011: '\x00', 4783012: '\x00', 4783013: '\x00', 4783014: '\x00', 4783015: '\x00', 4783016: 'G', 4783017: 'o', 4783018: 't', 4783019: ' ', 4783020: '%', 4783021: 'd', 4783022: ' ', 4783023: 'a', 4783024: 'r', 4783025: 'g', 4783026: 'u', 4783027: 'm', 4783028: 'e', 4783029: 'n', 4783030: 't', 4783031: 's', 4783032: '.', 4783033: ' ', 4783034: '%', 4783035: 'd', 4783036: ' ', 4783037: 'a', 4783038: 'a', 4783039: ' ', 4783040: '%', 4783041: 'd', 4783042: ' ', 4783043: ' ', 4783044: 's', 4783045: ' ', 4783046: '%', 4783047: 'd', 4783048: ' ', 4783049: '\n', 4783050: '\x00', 4783051: 'F', 4783052: 'A', 4783053: 'T', 4783054: 'A', 4783055: 'L'}}, 'disassembly': 'PCMPEQB XMM0, [RAX+0x10]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_1(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_10(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_11(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_12(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248024L, 'XMM0': 20203181441137406086353707335680L, 'EDX': 4294957920L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 8L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248028L, 'XMM0': 20203181441137406086353707335680L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_13(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 13L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793933L, 'RSI': 140737488346472L, 'RIP': 4239609L, 'XMM0': 338953138925153547590470800371487866880L, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 13L, 'RDX': 32768L, 'RBP': 140737488346472L, 'RDI': 4793933L, 'RSI': 140737488346472L, 'RIP': 4239613L, 'XMM0': 338953138925153547590470800371487866880L, 'EDX': 32768L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_14(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248062L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248066L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_15(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_16(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_17(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 79L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_18(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 12L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294963200L, 'RIP': 4248028L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483630L, 'ECX': 12L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294963200L, 'RIP': 4248032L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483630L, 'ECX': 0L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_19(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 13L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416400L, 'XMM0': 78918677504442992524819169280L, 'EDX': 13L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 31L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416404L, 'XMM0': 78918677504442992524819169280L, 'EDX': 2048L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_2(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248024L, 'XMM0': 280375465148160, 'EDX': 9L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483638L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 3L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248028L, 'XMM0': 280375465148160, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483638L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_20(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 8L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248028L, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 8L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 254L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967040L, 'RIP': 4248032L, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 254L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_21(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_22(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967264L, 'RIP': 4248024L, 'XMM0': 4278190080, 'EDX': 4L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483643L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 5L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967264L, 'RIP': 4248028L, 'XMM0': 4278190080, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483643L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_23(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_24(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_25(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 7059408L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 7059408L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_26(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 18446744073704757701L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'RSI': 4294967264L, 'RIP': 4239685L, 'XMM0': 1095216660480, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 582L, 'RAX': 4793968L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 18446744073704757701L, 'RDX': 16L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'RSI': 4294967264L, 'RIP': 4239689L, 'XMM0': 1095216660480, 'EDX': 16L, 'RSP': 140737488346056L, 'RFLAGS': 582L, 'RAX': 4793968L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_27(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248024L, 'XMM0': 280375465148160, 'EDX': 13L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483634L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 7L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248028L, 'XMM0': 280375465148160, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483634L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_28(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 79L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_29(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416404L, 'XMM3': 338953138925461823674472811186503024640L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L, 'ECX': 31L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 33824L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416408L, 'XMM3': 338953138925461823674472811186503024640L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L, 'ECX': 33824L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_3(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248024L, 'XMM0': 71776119061217535, 'EDX': 28L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483619L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 8L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248028L, 'XMM0': 71776119061217535, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483619L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_30(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_31(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 7L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248028L, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483634L, 'ECX': 7L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967168L, 'RIP': 4248032L, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483634L, 'ECX': 57600L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_32(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_33(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 41L, 'RDX': 1L, 'RBP': 140737488346472L, 'RDI': 4793961L, 'RSI': 1L, 'RIP': 4239609L, 'XMM0': 78918677504442992524819169280L, 'EDX': 1L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 41L, 'RDX': 2048L, 'RBP': 140737488346472L, 'RDI': 4793961L, 'RSI': 1L, 'RIP': 4239613L, 'XMM0': 78918677504442992524819169280L, 'EDX': 2048L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_34(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 5L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793989L, 'RSI': 4294967264L, 'RIP': 4239685L, 'XMM0': 71776119061217280, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 514L, 'RAX': 4793984L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 5L, 'RDX': 64L, 'RBP': 140737488346472L, 'RDI': 4793989L, 'RSI': 4294967264L, 'RIP': 4239689L, 'XMM0': 71776119061217280, 'EDX': 64L, 'RSP': 140737488346056L, 'RFLAGS': 514L, 'RAX': 4793984L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_35(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 79L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_36(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416364L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L, 'ECX': 0L}, 'memory': {4416364L: 'f', 4416365L: '\x0f', 4416366L: '\xd7', 4416367L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416368L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L, 'ECX': 0L}, 'memory': {4416364L: 'f', 4416365L: '\x0f', 4416366L: '\xd7', 4416367L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_37(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 14L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294950912L, 'RIP': 4248028L, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483643L, 'ECX': 14L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 254L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294950912L, 'RIP': 4248032L, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483643L, 'ECX': 254L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_38(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_39(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 8L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967040L, 'RIP': 4248028L, 'XMM3': 18446744073692839680L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 8L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 250L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967040L, 'RIP': 4248032L, 'XMM3': 18446744073692839680L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 250L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_4(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 5L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967264L, 'RIP': 4248028L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483643L, 'ECX': 5L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294967264L, 'RIP': 4248032L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_40(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248062L, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248066L, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L, 'ECX': 1024L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_41(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294934528L, 'RIP': 4248024L, 'XMM0': 0, 'EDX': 4294957920L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 15L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294934528L, 'RIP': 4248028L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_42(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 11L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416400L, 'XMM0': 1095216660480, 'EDX': 11L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 31L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416404L, 'XMM0': 1095216660480, 'EDX': 16L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_43(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416404L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L, 'ECX': 31L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 16L, 'RBP': 140737488347312L, 'RDI': 140737488347376L, 'RSI': 2048L, 'RIP': 4416408L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347355L, 'ECX': 0L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_44(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248058L, 'XMM0': 71776119061217535, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294963200L, 'RIP': 4248062L, 'XMM0': 71776119061217535, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483630L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_45(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_46(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416404L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L, 'ECX': 31L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416408L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L, 'ECX': 0L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_47(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 8L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248028L, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483619L, 'ECX': 8L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967040L, 'RIP': 4248032L, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483619L, 'ECX': 1024L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_48(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248024L, 'XMM0': 71776119061217535, 'EDX': 22L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483625L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 2L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248028L, 'XMM0': 71776119061217535, 'EDX': 65L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483625L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_49(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_5(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_50(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 5L, 'RDX': 50859318435822L, 'RBP': 140737488346472L, 'RDI': 4793925L, 'RSI': 140737488346472L, 'RIP': 4239609L, 'XMM0': 18374686479671623680L, 'EDX': 2610683886L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 5L, 'RDX': 128L, 'RBP': 140737488346472L, 'RDI': 4793925L, 'RSI': 140737488346472L, 'RIP': 4239613L, 'XMM0': 18374686479671623680L, 'EDX': 128L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_51(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_52(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248058L, 'XMM0': 308276084001730439550074880L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248062L, 'XMM0': 308276084001730439550074880L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_53(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248058L, 'XMM0': 280375465148160, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248062L, 'XMM0': 280375465148160, 'EDX': 34L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_54(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 79L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_55(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 12L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416400L, 'XMM0': 5172014448931175958107644294594560L, 'EDX': 12L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 31L, 'RDX': 8208L, 'RBP': 140737488347312L, 'RDI': 140737488347344L, 'RSI': 4129L, 'RIP': 4416404L, 'XMM0': 5172014448931175958107644294594560L, 'EDX': 8208L, 'RSP': 140737488346168L, 'RFLAGS': 518L, 'RAX': 140737488347324L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_56(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 18446744073704757637L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'RSI': 4294967264L, 'RIP': 4239685L, 'XMM0': 280375465082880, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 582L, 'RAX': 4794032L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 18446744073704757637L, 'RDX': 32L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'RSI': 4294967264L, 'RIP': 4239689L, 'XMM0': 280375465082880, 'EDX': 32L, 'RSP': 140737488346056L, 'RFLAGS': 582L, 'RAX': 4794032L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_57(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 7059408L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 7059408L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_58(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_59(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 79L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_6(self):
''' Instruction PMOVMSKB EDX, XMM1 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239698L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'text': 'f\x0f\xd7\xd1', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239702L, 'XMM1': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239698L: 'f', 4239699L: '\x0f', 4239700L: '\xd7', 4239701L: '\xd1'}}, 'disassembly': 'PMOVMSKB EDX, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_60(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 18446744073704757701L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'RSI': 4294967264L, 'RIP': 4239647L, 'XMM0': 1095216660480, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4793968L}, 'memory': {4239648L: '\x0f', 4239649L: '\xd7', 4239650L: '\xd0', 4239647L: 'f'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 18446744073704757701L, 'RDX': 16L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'RSI': 4294967264L, 'RIP': 4239651L, 'XMM0': 1095216660480, 'EDX': 16L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4793968L}, 'memory': {4239648L: '\x0f', 4239649L: '\xd7', 4239650L: '\xd0', 4239647L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_61(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294950912L, 'RIP': 4248024L, 'XMM0': 20203181441137406086353707335680L, 'EDX': 4L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483643L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 14L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294950912L, 'RIP': 4248028L, 'XMM0': 20203181441137406086353707335680L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483643L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_62(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 29L, 'RDX': 7074288L, 'RBP': 140737488346472L, 'RDI': 4793949L, 'RSI': 1L, 'RIP': 4239609L, 'XMM0': 78918677504442992524819169280L, 'EDX': 7074288L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 29L, 'RDX': 2048L, 'RBP': 140737488346472L, 'RDI': 4793949L, 'RSI': 1L, 'RIP': 4239613L, 'XMM0': 78918677504442992524819169280L, 'EDX': 2048L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_63(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_64(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 4L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416400L, 'XMM0': 0, 'EDX': 4L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 31L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 16L, 'RIP': 4416404L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416400L: 'f', 4416401L: '\x0f', 4416402L: '\xd7', 4416403L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_65(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 2L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248028L, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483625L, 'ECX': 2L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 1024L, 'RDX': 65L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'RSI': 4294967292L, 'RIP': 4248032L, 'XMM3': 308276084001730439550074880L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483625L, 'ECX': 1024L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_66(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_67(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_68(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_69(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248058L, 'XMM0': 4278190080, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'RSI': 4294934528L, 'RIP': 4248062L, 'XMM0': 4278190080, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_7(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_70(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_71(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125330L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_72(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_73(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248062L, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 254L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248066L, 'XMM3': 18446744073709551360L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 254L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_74(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294963200L, 'RIP': 4248024L, 'XMM0': 308276084001730439550074880L, 'EDX': 17L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483630L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 12L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294963200L, 'RIP': 4248028L, 'XMM0': 308276084001730439550074880L, 'EDX': 1024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483630L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_75(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248062L, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967040L, 'RIP': 4248066L, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 140737488345984L, 'ECX': 57600L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_76(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 79L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 79L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_77(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967040L, 'RIP': 4248024L, 'XMM0': 0, 'EDX': 4294957920L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 8L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'RSI': 4294967040L, 'RIP': 4248028L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248024L: 'f', 4248025L: '\x0f', 4248026L: '\xd7', 4248027L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_78(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_79(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 31L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416404L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L, 'ECX': 31L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 2048L, 'RBP': 140737488347312L, 'RDI': 140737488347360L, 'RSI': 8208L, 'RIP': 4416408L, 'XMM3': 0, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347341L, 'ECX': 0L}, 'memory': {4416404L: 'f', 4416405L: '\x0f', 4416406L: '\xd7', 4416407L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_8(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_80(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 8L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248058L, 'XMM0': 20203181441137406086353707335680L, 'EDX': 8L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 4096L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4294967264L, 'RIP': 4248062L, 'XMM0': 20203181441137406086353707335680L, 'EDX': 4096L, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L}, 'memory': {4248058L: 'f', 4248059L: '\x0f', 4248060L: '\xd7', 4248061L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_81(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_82(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_83(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248062L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 0L, 'RDX': 1024L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4294950912L, 'RIP': 4248066L, 'XMM3': 0, 'RSP': 140737488344248L, 'RFLAGS': 582L, 'RAX': 2147483643L, 'ECX': 0L}, 'memory': {4248064L: '\xd7', 4248065L: '\xcb', 4248062L: 'f', 4248063L: '\x0f'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_84(self):
''' Instruction PMOVMSKB EDX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239724L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'text': 'f\x0f\xd7\xd3', 'pos': {'registers': {'RCX': 0L, 'RDX': 16384L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239728L, 'XMM3': 1324035698926381045275276563951124480L, 'EDX': 16384L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239724L: 'f', 4239725L: '\x0f', 4239726L: '\xd7', 4239727L: '\xd3'}}, 'disassembly': 'PMOVMSKB EDX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_85(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416360L, 'XMM0': 20203181441137406366729172418815L, 'EDX': 4294958480L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416360L: 'f', 4416361L: '\x0f', 4416362L: '\xd7', 4416363L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 4129L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'RSI': 4294967295L, 'RIP': 4416364L, 'XMM0': 20203181441137406366729172418815L, 'EDX': 4129L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416360L: 'f', 4416361L: '\x0f', 4416362L: '\xd7', 4416363L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_86(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239685L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 140737354125695L, 'RIP': 4239689L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 514L, 'RAX': 4782912L}, 'memory': {4239688L: '\xd0', 4239685L: 'f', 4239686L: '\x0f', 4239687L: '\xd7'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_87(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 15L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294934528L, 'RIP': 4248028L, 'XMM3': 1324035698926381045275276563951124480L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 15L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 16384L, 'RDX': 0L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'RSI': 4294934528L, 'RIP': 4248032L, 'XMM3': 1324035698926381045275276563951124480L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L, 'ECX': 16384L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_88(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 5L, 'RDX': 1L, 'RBP': 140737488346472L, 'RDI': 4793989L, 'RSI': 4294967264L, 'RIP': 4239609L, 'XMM0': 0, 'EDX': 1L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 5L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793989L, 'RSI': 4294967264L, 'RIP': 4239613L, 'XMM0': 0, 'EDX': 0L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 0L}, 'memory': {4239609L: 'f', 4239610L: '\x0f', 4239611L: '\xd7', 4239612L: '\xd0'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_89(self):
''' Instruction PMOVMSKB EDX, XMM0 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 18446744073704757637L, 'RDX': 7065280L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'RSI': 4294967264L, 'RIP': 4239647L, 'XMM0': 1095216660480, 'EDX': 7065280L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4794032L}, 'memory': {4239648L: '\x0f', 4239649L: '\xd7', 4239650L: '\xd0', 4239647L: 'f'}}, 'text': 'f\x0f\xd7\xd0', 'pos': {'registers': {'RCX': 18446744073704757637L, 'RDX': 16L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'RSI': 4294967264L, 'RIP': 4239651L, 'XMM0': 1095216660480, 'EDX': 16L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4794032L}, 'memory': {4239648L: '\x0f', 4239649L: '\xd7', 4239650L: '\xd0', 4239647L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_9(self):
''' Instruction PMOVMSKB EDX, XMM2 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239711L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'text': 'f\x0f\xd7\xd2', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4782912L, 'RDI': 4782912L, 'RSI': 4782990L, 'RIP': 4239715L, 'XMM2': 0, 'EDX': 0L, 'RSP': 140737488346120L, 'RFLAGS': 582L, 'RAX': 4782912L}, 'memory': {4239712L: '\x0f', 4239713L: '\xd7', 4239714L: '\xd2', 4239711L: 'f'}}, 'disassembly': 'PMOVMSKB EDX, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPMOVMSKB_90(self):
''' Instruction PMOVMSKB ECX, XMM3 '''
test = {'mnemonic': 'PMOVMSKB', 'pre': {'registers': {'RCX': 3L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248028L, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483638L, 'ECX': 3L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'text': 'f\x0f\xd7\xcb', 'pos': {'registers': {'RCX': 57600L, 'RDX': 34L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'RSI': 4294967288L, 'RIP': 4248032L, 'XMM3': 340282346638528864515623922280452587520L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483638L, 'ECX': 57600L}, 'memory': {4248028L: 'f', 4248029L: '\x0f', 4248030L: '\xd7', 4248031L: '\xcb'}}, 'disassembly': 'PMOVMSKB ECX, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_1(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 7065368L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'RAX': 6L, 'RSP': 140737488346192L, 'RDX': 4L, 'RIP': 4298261L, 'RBP': 140737488346472L}, 'memory': {140737488346198L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x00', 140737488346185L: '\x00', 140737488346186L: '\x00', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 4298262L: '_', 140737488346199L: '\x00', 140737488346200L: '\xdd', 4298261L: 'A'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'RAX': 6L, 'RSP': 140737488346200L, 'RDX': 4L, 'RIP': 4298263L, 'RBP': 140737488346472L}, 'memory': {4298261L: 'A', 4298262L: '_', 140737488346183L: '\x00', 140737488346184L: '\x00', 140737488346185L: '\x00', 140737488346186L: '\x00', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xdd', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_10(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346120L, 'RDX': 64L, 'RIP': 4284650L, 'RBP': 32768L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4284651L: '^', 4284650L: 'A', 140737488346111L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346128L, 'RDX': 64L, 'RIP': 4284652L, 'RBP': 32768L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 4284650L: 'A', 4284651L: '^', 140737488346111L: '\x00'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_100(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R13': 38L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 104L, 'RIP': 4320796L, 'RBP': 9L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320796L: 'A', 4320797L: ']'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R13': 194L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 104L, 'RIP': 4320798L, 'RBP': 9L}, 'memory': {4320796L: 'A', 4320797L: ']', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_101(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R13': 38L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 104L, 'RIP': 4320796L, 'RBP': 3L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320796L: 'A', 4320797L: ']'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 104L, 'RIP': 4320798L, 'RBP': 3L}, 'memory': {4320796L: 'A', 4320797L: ']', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_11(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RBX': 0L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344176L, 'RDX': 0L, 'RIP': 4394907L, 'RBP': 7049504L}, 'memory': {140737488344167L: '\x00', 140737488344168L: ' ', 140737488344169L: '\x91', 140737488344170L: 'k', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '\t', 140737488344177L: '\x00', 140737488344178L: '\x00', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: ']', 4394907L: '['}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RBX': 9L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344184L, 'RDX': 0L, 'RIP': 4394908L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 4394907L: '[', 140737488344167L: '\x00', 140737488344168L: ' ', 140737488344169L: '\x91', 140737488344170L: 'k', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '\t', 140737488344177L: '\x00', 140737488344178L: '\x00', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: ']', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_12(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 104L, 'RIP': 4283978L, 'RBP': 188L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 4283978L: 'A', 4283979L: ']', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R13': 140737488346079L, 'RAX': 0L, 'RSP': 140737488346024L, 'RDX': 104L, 'RIP': 4283980L, 'RBP': 188L}, 'memory': {140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283978L: 'A', 4283979L: ']'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_13(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'R12': 140737488346078L, 'RAX': 32768L, 'RSP': 140737488346008L, 'RDX': 64L, 'RIP': 4283976L, 'RBP': 188L}, 'memory': {140737488346016L: '\xdf', 4283976L: 'A', 4283977L: '\\', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'R12': 140737488346078L, 'RAX': 32768L, 'RSP': 140737488346016L, 'RDX': 64L, 'RIP': 4283978L, 'RBP': 188L}, 'memory': {140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 4283976L: 'A', 4283977L: '\\'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_14(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 7071872L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346096L, 'RDX': 0L, 'RIP': 4205601L, 'RBP': 7054832L}, 'memory': {4205601L: 'A', 4205602L: '_', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346089L: '\x00', 140737488346090L: '\x00', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\xb5'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346104L, 'RDX': 0L, 'RIP': 4205603L, 'RBP': 7054832L}, 'memory': {140737488346112L: '@', 4205601L: 'A', 4205602L: '_', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346089L: '\x00', 140737488346090L: '\x00', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\xb5', 140737488346105L: ',', 140737488346106L: '@', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_15(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7051320L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345776L, 'RDX': 2016L, 'RIP': 4211200L, 'RBP': 7051232L}, 'memory': {4211200L: ']', 140737488345767L: '\x00', 140737488345768L: 'q', 140737488345769L: ':', 140737488345770L: 'J', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '\xe0', 140737488345777L: '\x97', 140737488345778L: 'k', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\x18'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051320L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345784L, 'RDX': 2016L, 'RIP': 4211201L, 'RBP': 7051232L}, 'memory': {4211200L: ']', 140737488345767L: '\x00', 140737488345768L: 'q', 140737488345769L: ':', 140737488345770L: 'J', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '\xe0', 140737488345777L: '\x97', 140737488345778L: 'k', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\x18', 140737488345785L: '\x00', 140737488345786L: '\x00', 140737488345787L: '\x00', 140737488345788L: '\x00', 140737488345789L: '\x00', 140737488345790L: '\x00', 140737488345791L: '\x00', 140737488345792L: '\x07'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_16(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'R13': 7035136L, 'RAX': 7065216L, 'RSP': 140737488346208L, 'RDX': 7065176L, 'RIP': 4197320L, 'RBP': 0L}, 'memory': {140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 4197321L: ']', 4197320L: 'A', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'R13': 0L, 'RAX': 7065216L, 'RSP': 140737488346216L, 'RDX': 7065176L, 'RIP': 4197322L, 'RBP': 0L}, 'memory': {4197320L: 'A', 4197321L: ']', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_17(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 32L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 7065216L, 'RSP': 140737488346216L, 'RDX': 7065176L, 'RIP': 4197322L, 'RBP': 0L}, 'memory': {140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4197323L: '^', 4197322L: 'A', 140737488346207L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 7065216L, 'RSP': 140737488346224L, 'RDX': 7065176L, 'RIP': 4197324L, 'RBP': 0L}, 'memory': {4197322L: 'A', 4197323L: '^', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_18(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'R12': 140737488346512L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4298255L, 'RBP': 140737488346472L}, 'memory': {140737488346176L: '\x07', 140737488346160L: 'h', 140737488346171L: '\xff', 4298255L: 'A', 4298256L: '\\', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346159L: '\x00', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'R12': 140737488346512L, 'RAX': 6L, 'RSP': 140737488346176L, 'RDX': 4L, 'RIP': 4298257L, 'RBP': 140737488346472L}, 'memory': {4298255L: 'A', 4298256L: '\\', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_19(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'R12': 7049504L, 'RAX': 699L, 'RSP': 140737488345912L, 'RDX': 18446744073709551615L, 'RIP': 4393090L, 'RBP': 7049504L}, 'memory': {140737488345920L: '\xbb', 4393090L: 'A', 4393091L: '\\', 140737488345903L: '\x00', 140737488345904L: ' ', 140737488345905L: '\x91', 140737488345906L: 'k', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: '\xd0', 140737488345914L: '\xff', 140737488345915L: '\xf7', 140737488345916L: '\xff', 140737488345917L: '\x7f', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'R12': 140737354125312L, 'RAX': 699L, 'RSP': 140737488345920L, 'RDX': 18446744073709551615L, 'RIP': 4393092L, 'RBP': 7049504L}, 'memory': {4393090L: 'A', 4393091L: '\\', 140737488345903L: '\x00', 140737488345904L: ' ', 140737488345905L: '\x91', 140737488345906L: 'k', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: '\xd0', 140737488345914L: '\xff', 140737488345915L: '\xf7', 140737488345916L: '\xff', 140737488345917L: '\x7f', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_2(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'R13': 140737488346079L, 'RAX': 32768L, 'RSP': 140737488346112L, 'RDX': 64L, 'RIP': 4284648L, 'RBP': 4L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 4284649L: ']', 4284648L: 'A', 140737488346103L: '\x00', 140737488346104L: 'h', 140737488346105L: '\xdd', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'R13': 140737488346512L, 'RAX': 32768L, 'RSP': 140737488346120L, 'RDX': 64L, 'RIP': 4284650L, 'RBP': 4L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4284648L: 'A', 4284649L: ']', 140737488346103L: '\x00', 140737488346104L: 'h', 140737488346105L: '\xdd', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_20(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 6L, 'RIP': 4320800L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345943L: '\x00', 4320801L: '_', 4320800L: 'A', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 6L, 'RIP': 4320802L, 'RBP': 3L}, 'memory': {4320800L: 'A', 4320801L: '_', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_21(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 104L, 'RIP': 4283975L, 'RBP': 9L}, 'memory': {140737488345995L: '\x00', 4283975L: ']', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345991L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 104L, 'RIP': 4283976L, 'RBP': 194L}, 'memory': {140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 4283975L: ']'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_22(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 8L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 6L, 'RIP': 4320794L, 'RBP': 9L}, 'memory': {140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 4320794L: 'A', 4320795L: '\\', 140737488345919L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 6L, 'RIP': 4320796L, 'RBP': 9L}, 'memory': {4320794L: 'A', 4320795L: '\\', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_23(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RBX': 4L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346192L, 'RDX': 140737488346512L, 'RIP': 4299294L, 'RBP': 140737488346472L}, 'memory': {140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346185L: '\r', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x04', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xd8', 4299294L: '['}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RBX': 4L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4299295L, 'RBP': 140737488346472L}, 'memory': {4299294L: '[', 140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346185L: '\r', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x04', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xd8', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_24(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RBX': 140737488345968L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 96L, 'RIP': 4320792L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345912L: 'Z', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 4320792L: '[', 140737488345913L: '\x03', 140737488345914L: 'v', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RBX': 7734106L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 96L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {4320792L: '[', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: 'Z', 140737488345913L: '\x03', 140737488345914L: 'v', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_25(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'R12': 8L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 96L, 'RIP': 4320794L, 'RBP': 3L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 4320794L: 'A', 4320795L: '\\', 140737488345919L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 96L, 'RIP': 4320796L, 'RBP': 3L}, 'memory': {4320794L: 'A', 4320795L: '\\', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_26(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 6L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345913L: 'Z', 140737488345911L: '\x00', 140737488345912L: '\x00', 4320793L: ']', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 6L, 'RIP': 4320794L, 'RBP': 9L}, 'memory': {4320793L: ']', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: 'Z', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_27(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RBX': 7075888L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488345976L, 'RDX': 1617L, 'RIP': 4219557L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 4219557L: '[', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0', 140737488345977L: '\xf1', 140737488345978L: 'k', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RBX': 7074256L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488345984L, 'RDX': 1617L, 'RIP': 4219558L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 4219557L: '[', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0', 140737488345977L: '\xf1', 140737488345978L: 'k', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_28(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 104L, 'RIP': 4283982L, 'RBP': 188L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 4283983L: '_', 4283982L: 'A'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346040L, 'RDX': 104L, 'RIP': 4283984L, 'RBP': 188L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 4283982L: 'A', 4283983L: '_'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_29(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4195592L, 'RBP': 140737488346144L}, 'memory': {140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 4195592L: ']', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: '\x04', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 0L, 'RIP': 4195593L, 'RBP': 4L}, 'memory': {4195592L: ']', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: '\x04', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_3(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RBX': 3L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488345992L, 'RDX': 64L, 'RIP': 4283974L, 'RBP': 9L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 4283974L: '[', 140737488345983L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RBX': 15774463L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346000L, 'RDX': 64L, 'RIP': 4283975L, 'RBP': 9L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 4283974L: '[', 140737488345983L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_30(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4807364L, 'R12': 0L, 'RAX': 7074368L, 'RSP': 140737488346096L, 'RDX': 1L, 'RIP': 4520285L, 'RBP': 140737488346112L}, 'memory': {140737488346087L: '\x00', 140737488346088L: 'q', 140737488346089L: ':', 140737488346090L: 'J', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x90', 140737488346097L: '\xdd', 140737488346098L: '\xff', 140737488346099L: '\xff', 140737488346100L: '\xff', 140737488346101L: '\x7f', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\x07', 4520285L: 'A', 4520286L: '\\'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4807364L, 'R12': 140737488346512L, 'RAX': 7074368L, 'RSP': 140737488346104L, 'RDX': 1L, 'RIP': 4520287L, 'RBP': 140737488346112L}, 'memory': {140737488346112L: 'h', 4520285L: 'A', 4520286L: '\\', 140737488346087L: '\x00', 140737488346088L: 'q', 140737488346089L: ':', 140737488346090L: 'J', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x90', 140737488346097L: '\xdd', 140737488346098L: '\xff', 140737488346099L: '\xff', 140737488346100L: '\xff', 140737488346101L: '\x7f', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\x07', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_31(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RBX': 140737488345968L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 104L, 'RIP': 4320792L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345912L: 'v', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 4320792L: '[', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RBX': 118L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 104L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {4320792L: '[', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: 'v', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_32(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 2176L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 7065216L, 'RSP': 140737488346224L, 'RDX': 7065176L, 'RIP': 4197324L, 'RBP': 0L}, 'memory': {140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 4197325L: '_', 140737488346222L: '\x00', 140737488346221L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda', 140737488346223L: '\x00', 4197324L: 'A'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'RDI': 4098L, 'RAX': 7065216L, 'RSP': 140737488346232L, 'RDX': 7065176L, 'RIP': 4197326L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4197324L: 'A', 4197325L: '_', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_33(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 0L, 'RDI': 6L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4299926L, 'RBP': 1L}, 'memory': {140737488346176L: 'n', 140737488346166L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 4299926L: '[', 140737488346167L: '\x00', 140737488346168L: '\x00', 140737488346169L: '\x02', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4194816L, 'RDI': 6L, 'RAX': 6L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4299927L, 'RBP': 1L}, 'memory': {4299926L: '[', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x00', 140737488346169L: '\x02', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_34(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 39L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 104L, 'RIP': 4320798L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345951L: '\x00', 140737488345950L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 4320798L: 'A', 4320799L: '^'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 104L, 'RIP': 4320800L, 'RBP': 9L}, 'memory': {4320798L: 'A', 4320799L: '^', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_35(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RBX': 140737488346272L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346224L, 'RDX': 18446744072518369280L, 'RIP': 4319972L, 'RBP': 0L}, 'memory': {4319972L: '[', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x90', 140737488346225L: '\r', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 's'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RBX': 4197776L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 18446744072518369280L, 'RIP': 4319973L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4319972L: '[', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x90', 140737488346225L: '\r', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 's', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_36(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'R13': 699L, 'RAX': 699L, 'RSP': 140737488345920L, 'RDX': 18446744073709551615L, 'RIP': 4393092L, 'RBP': 7049504L}, 'memory': {140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa', 140737488345919L: '\x00', 140737488345913L: '\xd0', 140737488345911L: '\x00', 140737488345912L: '\x00', 4393092L: 'A', 140737488345914L: '\xff', 140737488345915L: '\xf7', 140737488345916L: '\xff', 140737488345917L: '\x7f', 140737488345918L: '\x00', 4393093L: ']'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'R13': 699L, 'RAX': 699L, 'RSP': 140737488345928L, 'RDX': 18446744073709551615L, 'RIP': 4393094L, 'RBP': 7049504L}, 'memory': {4393092L: 'A', 4393093L: ']', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: '\xd0', 140737488345914L: '\xff', 140737488345915L: '\xf7', 140737488345916L: '\xff', 140737488345917L: '\x7f', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa', 140737488345929L: '\x04', 140737488345930L: 'C', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_37(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488346008L, 'RDX': 33L, 'RIP': 4219563L, 'RBP': 7051232L}, 'memory': {140737488346016L: '\x00', 4219563L: 'A', 4219564L: '^', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488346016L, 'RDX': 33L, 'RIP': 4219565L, 'RBP': 7051232L}, 'memory': {140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x04', 4219563L: 'A', 4219564L: '^'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_38(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 138817L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488346016L, 'RDX': 33L, 'RIP': 4219565L, 'RBP': 7051232L}, 'memory': {140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x04', 4219565L: 'A', 4219566L: '_', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488346024L, 'RDX': 33L, 'RIP': 4219567L, 'RBP': 7051232L}, 'memory': {4219565L: 'A', 4219566L: '_', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x04', 140737488346025L: '\x8c', 140737488346026L: '@', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_39(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'R13': 7L, 'RAX': 0L, 'RSP': 140737488346048L, 'RDX': 7065872L, 'RIP': 4212949L, 'RBP': 140737488346112L}, 'memory': {140737488346048L: '\x07', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 4212949L: 'A', 4212950L: ']', 140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346041L: '\x00', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'R13': 7L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065872L, 'RIP': 4212951L, 'RBP': 140737488346112L}, 'memory': {140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346041L: '\x00', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x07', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x8e', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: 'q', 4212949L: 'A', 4212950L: ']'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_4(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'R13': 0L, 'RAX': 0L, 'RSP': 140737488346080L, 'RDX': 0L, 'RIP': 4205597L, 'RBP': 7054832L}, 'memory': {140737488346080L: '\x01', 140737488346081L: '\x00', 140737488346082L: '\x00', 140737488346083L: '\x00', 140737488346084L: '\x00', 140737488346085L: '\x00', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\xf8', 140737488346073L: '\xa5', 140737488346074L: 'k', 140737488346075L: '\x00', 140737488346076L: '\x00', 4205597L: 'A', 4205598L: ']', 140737488346079L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'R13': 1L, 'RAX': 0L, 'RSP': 140737488346088L, 'RDX': 0L, 'RIP': 4205599L, 'RBP': 7054832L}, 'memory': {4205597L: 'A', 4205598L: ']', 140737488346071L: '\x00', 140737488346072L: '\xf8', 140737488346073L: '\xa5', 140737488346074L: 'k', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00', 140737488346080L: '\x01', 140737488346081L: '\x00', 140737488346082L: '\x00', 140737488346083L: '\x00', 140737488346084L: '\x00', 140737488346085L: '\x00', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346089L: '\x00', 140737488346090L: '\x00', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_40(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RBX': 0L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345896L, 'RDX': 18446744073709551615L, 'RIP': 4393088L, 'RBP': 140737354125312L}, 'memory': {140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: ' ', 140737488345897L: '\x91', 140737488345898L: 'k', 140737488345899L: '\x00', 140737488345900L: '\x00', 140737488345901L: '\x00', 140737488345902L: '\x00', 140737488345903L: '\x00', 140737488345904L: ' ', 4393088L: '[', 140737488345887L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RBX': 7049504L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345904L, 'RDX': 18446744073709551615L, 'RIP': 4393089L, 'RBP': 140737354125312L}, 'memory': {4393088L: '[', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: ' ', 140737488345897L: '\x91', 140737488345898L: 'k', 140737488345899L: '\x00', 140737488345900L: '\x00', 140737488345901L: '\x00', 140737488345902L: '\x00', 140737488345903L: '\x00', 140737488345904L: ' ', 140737488345905L: '\x91', 140737488345906L: 'k', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_41(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346048L, 'RDX': 140737354125312L, 'RIP': 4394984L, 'RBP': 0L}, 'memory': {140737488346048L: ' ', 140737488346049L: '\x91', 140737488346050L: 'k', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 4394984L: '[', 140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 140737354125312L, 'RIP': 4394985L, 'RBP': 0L}, 'memory': {140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: ' ', 140737488346049L: '\x91', 140737488346050L: 'k', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 4394984L: '['}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_42(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346208L, 'RDX': 5L, 'RIP': 4299528L, 'RBP': 0L}, 'memory': {140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\xf0', 4299528L: ']', 140737488346199L: '\x00', 140737488346200L: '\x90', 140737488346201L: '\r', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 199173L, 'RSP': 140737488346216L, 'RDX': 5L, 'RIP': 4299529L, 'RBP': 0L}, 'memory': {4299528L: ']', 140737488346199L: '\x00', 140737488346200L: '\x90', 140737488346201L: '\r', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\xf0', 140737488346217L: '\x0c', 140737488346218L: '@', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_43(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 8L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 6L, 'RIP': 4320794L, 'RBP': 3L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 4320794L: 'A', 4320795L: '\\', 140737488345919L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 6L, 'RIP': 4320796L, 'RBP': 3L}, 'memory': {4320794L: 'A', 4320795L: '\\', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_44(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 140737488346079L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346024L, 'RDX': 64L, 'RIP': 4283980L, 'RBP': 188L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283980L: 'A', 4283981L: '^', 140737488346015L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346032L, 'RDX': 64L, 'RIP': 4283982L, 'RBP': 188L}, 'memory': {140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: 'r', 4283980L: 'A', 4283981L: '^'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_45(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'R13': 4195080L, 'RAX': 4467264L, 'RSP': 140737488346216L, 'RDX': 0L, 'RIP': 4197597L, 'RBP': 0L}, 'memory': {140737488346208L: '\xf0', 140737488346209L: '\x0c', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4197597L: 'A', 4197598L: ']', 140737488346207L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'R13': 0L, 'RAX': 4467264L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4197599L, 'RBP': 0L}, 'memory': {4197597L: 'A', 4197598L: ']', 140737488346207L: '\x00', 140737488346208L: '\xf0', 140737488346209L: '\x0c', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xd5'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_46(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'R13': 7074256L, 'RAX': 7074256L, 'RSP': 140737488346000L, 'RDX': 33L, 'RIP': 4219561L, 'RBP': 7051232L}, 'memory': {140737488345991L: '\x00', 140737488345992L: '\x18', 4219561L: 'A', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488345993L: '\x00', 140737488346008L: '\x00', 140737488346007L: '\x00', 4219562L: ']'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'R13': 7L, 'RAX': 7074256L, 'RSP': 140737488346008L, 'RDX': 33L, 'RIP': 4219563L, 'RBP': 7051232L}, 'memory': {140737488345991L: '\x00', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\x00', 4219561L: 'A', 4219562L: ']'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_47(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 35L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 96L, 'RIP': 4320798L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345951L: '\x00', 140737488345950L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 4320798L: 'A', 4320799L: '^'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 96L, 'RIP': 4320800L, 'RBP': 9L}, 'memory': {4320798L: 'A', 4320799L: '^', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_48(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 7035168L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4197761L, 'RBP': 0L}, 'memory': {4197761L: 'A', 4197762L: '_', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4197763L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4197761L: 'A', 4197762L: '_', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_49(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'R13': 9L, 'RAX': 9L, 'RSP': 140737488344168L, 'RDX': 32L, 'RIP': 4203626L, 'RBP': 7049504L}, 'memory': {140737488344160L: '\x00', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 140737488344169L: '\x00', 140737488344170L: '\x00', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 4203627L: ']', 4203626L: 'A', 140737488344159L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'R13': 9L, 'RAX': 9L, 'RSP': 140737488344176L, 'RDX': 32L, 'RIP': 4203628L, 'RBP': 7049504L}, 'memory': {140737488344171L: '\x00', 140737488344159L: '\x00', 140737488344160L: '\x00', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 140737488344169L: '\x00', 140737488344170L: '\x00', 4203627L: ']', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 140737488344177L: '\xfb', 140737488344178L: 'H', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: '\xa2', 4203626L: 'A'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_5(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 140737488345968L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 6L, 'RIP': 4320792L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345912L: '\x00', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 4320792L: '[', 140737488345913L: 'Z', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 1979931136L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 6L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {4320792L: '[', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: 'Z', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_50(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 6L, 'RIP': 4320800L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345943L: '\x00', 4320801L: '_', 4320800L: 'A', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 6L, 'RIP': 4320802L, 'RBP': 3L}, 'memory': {4320800L: 'A', 4320801L: '_', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_51(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346128L, 'RDX': 64L, 'RIP': 4284652L, 'RBP': 4L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 4284652L: 'A', 140737488346125L: '\x00', 140737488346124L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346126L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xd1', 4284653L: '_', 140737488346133L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 7035168L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346136L, 'RDX': 64L, 'RIP': 4284654L, 'RBP': 4L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xd1', 140737488346137L: 'a', 140737488346138L: 'A', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x00', 4284652L: 'A', 4284653L: '_'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_52(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 7051320L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345808L, 'RDX': 2016L, 'RIP': 4211207L, 'RBP': 7051232L}, 'memory': {140737488345799L: '\x00', 4211208L: '_', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345800L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\x84', 4211207L: 'A', 140737488345809L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 7051320L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345816L, 'RDX': 2016L, 'RIP': 4211209L, 'RBP': 7051232L}, 'memory': {4211207L: 'A', 4211208L: '_', 140737488345799L: '\x00', 140737488345800L: '\x00', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\x84', 140737488345817L: 'c', 140737488345818L: '@', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00', 140737488345824L: '\x00'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_53(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346096L, 'RDX': 64L, 'RIP': 4284645L, 'RBP': 188L}, 'memory': {4284645L: ']', 140737488346087L: '\x00', 140737488346088L: '`', 140737488346089L: '\xd0', 140737488346090L: 'k', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x04', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346104L, 'RDX': 64L, 'RIP': 4284646L, 'RBP': 4L}, 'memory': {140737488346112L: '\x90', 4284645L: ']', 140737488346087L: '\x00', 140737488346088L: '`', 140737488346089L: '\xd0', 140737488346090L: 'k', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x04', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h', 140737488346105L: '\xdd', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_54(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RBX': 0L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345992L, 'RDX': 104L, 'RIP': 4283974L, 'RBP': 9L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 4283974L: '[', 140737488345983L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RBX': 15774463L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 104L, 'RIP': 4283975L, 'RBP': 9L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 4283974L: '[', 140737488345983L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_55(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 6L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345913L: 'Z', 140737488345911L: '\x00', 140737488345912L: '\x00', 4320793L: ']', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 6L, 'RIP': 4320794L, 'RBP': 3L}, 'memory': {4320793L: ']', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: 'Z', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_56(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346128L, 'RDX': 64L, 'RIP': 4284652L, 'RBP': 32768L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 4284652L: 'A', 140737488346125L: '\x00', 140737488346124L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346126L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 4284653L: '_', 140737488346133L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 7035168L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346136L, 'RDX': 64L, 'RIP': 4284654L, 'RBP': 32768L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: 'a', 140737488346138L: 'A', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x00', 4284652L: 'A', 4284653L: '_'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_57(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346216L, 'RDX': 0L, 'RIP': 4197759L, 'RBP': 0L}, 'memory': {140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4197760L: '^', 140737488346207L: '\x00', 4197759L: 'A'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4197761L, 'RBP': 0L}, 'memory': {4197760L: '^', 140737488346207L: '\x00', 140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 4197759L: 'A'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_58(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 104L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345913L: '\x00', 140737488345911L: '\x00', 140737488345912L: 'v', 4320793L: ']', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 104L, 'RIP': 4320794L, 'RBP': 9L}, 'memory': {4320793L: ']', 140737488345911L: '\x00', 140737488345912L: 'v', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_59(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 96L, 'RIP': 4320800L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345943L: '\x00', 4320801L: '_', 4320800L: 'A', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 96L, 'RIP': 4320802L, 'RBP': 3L}, 'memory': {4320800L: 'A', 4320801L: '_', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_6(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RBX': 4194592L, 'RDI': 0L, 'RAX': 6L, 'RSP': 140737488346152L, 'RDX': 4L, 'RIP': 4298253L, 'RBP': 0L}, 'memory': {140737488346144L: '0', 140737488346145L: '\xe8', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x04', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 4298253L: '[', 140737488346143L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RBX': 4L, 'RDI': 0L, 'RAX': 6L, 'RSP': 140737488346160L, 'RDX': 4L, 'RIP': 4298254L, 'RBP': 0L}, 'memory': {4298253L: '[', 140737488346143L: '\x00', 140737488346144L: '0', 140737488346145L: '\xe8', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x04', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_60(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 104L, 'RIP': 4320800L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345943L: '\x00', 4320801L: '_', 4320800L: 'A', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 104L, 'RIP': 4320802L, 'RBP': 3L}, 'memory': {4320800L: 'A', 4320801L: '_', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_61(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'R13': 140737488346512L, 'RAX': 524288L, 'RSP': 140737488346208L, 'RDX': 0L, 'RIP': 4197757L, 'RBP': 0L}, 'memory': {140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 4197757L: 'A', 4197758L: ']', 140737488346207L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'R13': 7L, 'RAX': 524288L, 'RSP': 140737488346216L, 'RDX': 0L, 'RIP': 4197759L, 'RBP': 0L}, 'memory': {140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4197757L: 'A', 4197758L: ']'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_62(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 6L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345913L: 'v', 140737488345911L: '\x00', 140737488345912L: '\x03', 4320793L: ']', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 6L, 'RIP': 4320794L, 'RBP': 3L}, 'memory': {4320793L: ']', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_63(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 7054976L, 'RSP': 140737488346104L, 'RDX': 0L, 'RIP': 4776995L, 'RBP': 4881624L}, 'memory': {140737488346112L: '@', 4776995L: ']', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: ' ', 140737488346105L: '\xdc', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 7054976L, 'RSP': 140737488346112L, 'RDX': 0L, 'RIP': 4776996L, 'RBP': 140737488346144L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xb1', 4776995L: ']', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: ' ', 140737488346105L: '\xdc', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_64(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RBX': 15774463L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346088L, 'RDX': 64L, 'RIP': 4284644L, 'RBP': 194L}, 'memory': {140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 140737488346084L: '\xff', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '`', 140737488346089L: '\xd0', 140737488346090L: 'k', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 4284644L: '[', 140737488346079L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RBX': 7065696L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346096L, 'RDX': 64L, 'RIP': 4284645L, 'RBP': 194L}, 'memory': {140737488346084L: '\xff', 140737488346079L: '\x00', 140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 4284644L: '[', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '`', 140737488346089L: '\xd0', 140737488346090L: 'k', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x80', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_65(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344152L, 'RDX': 32L, 'RIP': 4203623L, 'RBP': 7049504L}, 'memory': {140737488344160L: '\x00', 4203623L: ']', 140737488344143L: '\x00', 140737488344144L: '\t', 140737488344145L: '\x00', 140737488344146L: '\x00', 140737488344147L: '\x00', 140737488344148L: '\x00', 140737488344149L: '\x00', 140737488344150L: '\x00', 140737488344151L: '\x00', 140737488344152L: ' ', 140737488344153L: '\x91', 140737488344154L: 'k', 140737488344155L: '\x00', 140737488344156L: '\x00', 140737488344157L: '\x00', 140737488344158L: '\x00', 140737488344159L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344160L, 'RDX': 32L, 'RIP': 4203624L, 'RBP': 7049504L}, 'memory': {140737488344143L: '\x00', 140737488344144L: '\t', 140737488344145L: '\x00', 140737488344146L: '\x00', 140737488344147L: '\x00', 140737488344148L: '\x00', 140737488344149L: '\x00', 140737488344150L: '\x00', 140737488344151L: '\x00', 140737488344152L: ' ', 140737488344153L: '\x91', 140737488344154L: 'k', 140737488344155L: '\x00', 140737488344156L: '\x00', 140737488344157L: '\x00', 140737488344158L: '\x00', 140737488344159L: '\x00', 140737488344160L: '\x00', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 4203623L: ']', 140737488344168L: '\t', 140737488344167L: '\x00'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_66(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 96L, 'RIP': 4320800L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345943L: '\x00', 4320801L: '_', 4320800L: 'A', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 96L, 'RIP': 4320802L, 'RBP': 9L}, 'memory': {4320800L: 'A', 4320801L: '_', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_67(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 7049952L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346088L, 'RDX': 0L, 'RIP': 4205599L, 'RBP': 7054832L}, 'memory': {140737488346080L: '\x01', 140737488346081L: '\x00', 140737488346082L: '\x00', 140737488346083L: '\x00', 140737488346084L: '\x00', 140737488346085L: '\x00', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346089L: '\x00', 140737488346090L: '\x00', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346079L: '\x00', 4205600L: '^', 4205599L: 'A'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 0L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346096L, 'RDX': 0L, 'RIP': 4205601L, 'RBP': 7054832L}, 'memory': {4205599L: 'A', 4205600L: '^', 140737488346079L: '\x00', 140737488346080L: '\x01', 140737488346081L: '\x00', 140737488346082L: '\x00', 140737488346083L: '\x00', 140737488346084L: '\x00', 140737488346085L: '\x00', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346089L: '\x00', 140737488346090L: '\x00', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\xb5'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_68(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'R12': 140737488346078L, 'RAX': 4194304L, 'RSP': 140737488346008L, 'RDX': 64L, 'RIP': 4283976L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 4283976L: 'A', 4283977L: '\\', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'R12': 140737488346078L, 'RAX': 4194304L, 'RSP': 140737488346016L, 'RDX': 64L, 'RIP': 4283978L, 'RBP': 194L}, 'memory': {140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 4283976L: 'A', 4283977L: '\\'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_69(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 6L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345913L: 'v', 140737488345911L: '\x00', 140737488345912L: '\x03', 4320793L: ']', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 6L, 'RIP': 4320794L, 'RBP': 9L}, 'memory': {4320793L: ']', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_7(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 104L, 'RIP': 4283975L, 'RBP': 3L}, 'memory': {140737488345995L: '\x00', 4283975L: ']', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345991L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 104L, 'RIP': 4283976L, 'RBP': 188L}, 'memory': {140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 4283975L: ']'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_70(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 104L, 'RIP': 4283976L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 4283976L: 'A', 4283977L: '\\', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 104L, 'RIP': 4283978L, 'RBP': 194L}, 'memory': {140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 4283976L: 'A', 4283977L: '\\'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_71(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 18446744073709551615L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4779604L, 'RBP': 140737488346144L}, 'memory': {140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x1b', 4779604L: ']', 140737488346135L: '\x00', 140737488346136L: '\x90', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 18446744073709551615L, 'RSP': 140737488346152L, 'RDX': 0L, 'RIP': 4779605L, 'RBP': 4L}, 'memory': {140737488346135L: '\x00', 140737488346136L: '\x90', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x1b', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 4779604L: ']'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_72(self):
''' Instruction POP R15 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 104L, 'RIP': 4283982L, 'RBP': 194L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 4283983L: '_', 4283982L: 'A'}}, 'text': 'A_', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346040L, 'RDX': 104L, 'RIP': 4283984L, 'RBP': 194L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 4283982L: 'A', 4283983L: '_'}}, 'disassembly': 'POP R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_73(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'R12': 7074272L, 'RAX': 7074288L, 'RSP': 140737488345992L, 'RDX': 1617L, 'RIP': 4219559L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 140737488345993L: '\x06', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\n', 4219560L: '\\', 4219559L: 'A', 140737488345983L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'R12': 1600L, 'RAX': 7074288L, 'RSP': 140737488346000L, 'RDX': 1617L, 'RIP': 4219561L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 140737488345993L: '\x06', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\n', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 4219559L: 'A', 4219560L: '\\', 140737488345983L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_74(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 7065872L, 'RIP': 4212946L, 'RBP': 0L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x18', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 4212946L: ']'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346040L, 'RDX': 7065872L, 'RIP': 4212947L, 'RBP': 140737488346112L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x18', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346041L: '\x00', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x07', 4212946L: ']'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_75(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346096L, 'RDX': 64L, 'RIP': 4284645L, 'RBP': 194L}, 'memory': {4284645L: ']', 140737488346087L: '\x00', 140737488346088L: '`', 140737488346089L: '\xd0', 140737488346090L: 'k', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x80', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346104L, 'RDX': 64L, 'RIP': 4284646L, 'RBP': 32768L}, 'memory': {140737488346112L: '\x90', 4284645L: ']', 140737488346087L: '\x00', 140737488346088L: '`', 140737488346089L: '\xd0', 140737488346090L: 'k', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x80', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h', 140737488346105L: '\xdd', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_76(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346120L, 'RDX': 64L, 'RIP': 4284650L, 'RBP': 4L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4284651L: '^', 4284650L: 'A', 140737488346111L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346128L, 'RDX': 64L, 'RIP': 4284652L, 'RBP': 4L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xd1', 4284650L: 'A', 4284651L: '^', 140737488346111L: '\x00'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_77(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 0L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 6L, 'RIP': 4320796L, 'RBP': 3L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320796L: 'A', 4320797L: ']'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 6L, 'RIP': 4320798L, 'RBP': 3L}, 'memory': {4320796L: 'A', 4320797L: ']', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_78(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7054976L, 'RBX': 4197776L, 'RDI': 4881624L, 'RAX': 18446744073709551615L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4779603L, 'RBP': 140737488346144L}, 'memory': {140737488346144L: '\x04', 140737488346136L: '\x90', 140737488346127L: '\x00', 140737488346128L: '\x90', 140737488346129L: '\r', 140737488346130L: '@', 4779603L: '[', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346131L: '\x00', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7054976L, 'RBX': 4197776L, 'RDI': 4881624L, 'RAX': 18446744073709551615L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4779604L, 'RBP': 140737488346144L}, 'memory': {140737488346127L: '\x00', 140737488346128L: '\x90', 140737488346129L: '\r', 140737488346130L: '@', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x1b', 4779603L: '['}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_79(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RBX': 0L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345992L, 'RDX': 104L, 'RIP': 4283974L, 'RBP': 3L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 4283974L: '[', 140737488345983L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RBX': 15774463L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 104L, 'RIP': 4283975L, 'RBP': 3L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 4283974L: '[', 140737488345983L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_8(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RBX': 7074272L, 'RDI': 4807364L, 'RAX': 7074368L, 'RSP': 140737488346088L, 'RDX': 1L, 'RIP': 4520284L, 'RBP': 140737488346112L}, 'memory': {140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 140737488346084L: '\xff', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: 'q', 140737488346089L: ':', 140737488346090L: 'J', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x90', 4520284L: '[', 140737488346079L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RBX': 4864625L, 'RDI': 4807364L, 'RAX': 7074368L, 'RSP': 140737488346096L, 'RDX': 1L, 'RIP': 4520285L, 'RBP': 140737488346112L}, 'memory': {4520284L: '[', 140737488346079L: '\x00', 140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 140737488346084L: '\xff', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: 'q', 140737488346089L: ':', 140737488346090L: 'J', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: '\x90', 140737488346097L: '\xdd', 140737488346098L: '\xff', 140737488346099L: '\xff', 140737488346100L: '\xff', 140737488346101L: '\x7f', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\x07'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_80(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RBX': 0L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4205982L, 'RBP': 1L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x00', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\xf0', 4205982L: '[', 140737488346111L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RBX': 0L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7059408L, 'RIP': 4205983L, 'RBP': 1L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x00', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\xf0', 140737488346129L: '\xa5', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xf8', 4205982L: '[', 140737488346111L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_81(self):
''' Instruction POP RSI '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346464L, 'RDX': 0L, 'RIP': 4195301L, 'RBP': 0L}, 'memory': {140737488346464L: '\x04', 140737488346465L: '\x00', 140737488346466L: '\x00', 140737488346467L: '\x00', 140737488346468L: '\x00', 140737488346469L: '\x00', 140737488346470L: '\x00', 140737488346471L: '\x00', 140737488346472L: '\xb0', 140737488346463L: '\x00', 140737488346455L: '\x00', 140737488346456L: '\x00', 140737488346457L: '\x00', 140737488346458L: '\x00', 140737488346459L: '\x00', 140737488346460L: '\x00', 140737488346461L: '\x00', 140737488346462L: '\x00', 4195301L: '^'}}, 'text': '^', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346472L, 'RDX': 0L, 'RIP': 4195302L, 'RBP': 0L}, 'memory': {140737488346463L: '\x00', 140737488346455L: '\x00', 140737488346456L: '\x00', 140737488346457L: '\x00', 140737488346458L: '\x00', 140737488346459L: '\x00', 140737488346460L: '\x00', 140737488346461L: '\x00', 140737488346462L: '\x00', 140737488346469L: '\x00', 140737488346464L: '\x04', 140737488346465L: '\x00', 140737488346466L: '\x00', 140737488346467L: '\x00', 140737488346468L: '\x00', 4195301L: '^', 140737488346470L: '\x00', 140737488346471L: '\x00', 140737488346472L: '\xb0', 140737488346473L: '\xe0', 140737488346474L: '\xff', 140737488346475L: '\xff', 140737488346476L: '\xff', 140737488346477L: '\x7f', 140737488346478L: '\x00', 140737488346479L: '\x00', 140737488346480L: '\xf6'}}, 'disassembly': 'POP RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_82(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 6L, 'RIP': 4320798L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345951L: '\x00', 140737488345950L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 4320798L: 'A', 4320799L: '^'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 6L, 'RIP': 4320800L, 'RBP': 3L}, 'memory': {4320798L: 'A', 4320799L: '^', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_83(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 140737488345968L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 6L, 'RIP': 4320792L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345912L: '\x03', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 4320792L: '[', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 30211L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 6L, 'RIP': 4320793L, 'RBP': 4792416L}, 'memory': {4320792L: '[', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_84(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'R13': 0L, 'RAX': 199173L, 'RSP': 140737488346224L, 'RDX': 5L, 'RIP': 4299531L, 'RBP': 0L}, 'memory': {140737488346219L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\xf0', 140737488346217L: '\x0c', 140737488346218L: '@', 4299531L: 'A', 4299532L: ']', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346220L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3', 140737488346225L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'R13': 0L, 'RAX': 199173L, 'RSP': 140737488346232L, 'RDX': 5L, 'RIP': 4299533L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4299531L: 'A', 4299532L: ']', 140737488346215L: '\x00', 140737488346216L: '\xf0', 140737488346217L: '\x0c', 140737488346218L: '@', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_85(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074256L, 'RSI': 7074272L, 'RBX': 0L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488345976L, 'RDX': 33L, 'RIP': 4219557L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 4219557L: '[', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: 'q', 140737488345977L: ':', 140737488345978L: 'J', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074256L, 'RSI': 7074272L, 'RBX': 4864625L, 'RDI': 7213056L, 'RAX': 7074256L, 'RSP': 140737488345984L, 'RDX': 33L, 'RIP': 4219558L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\x18', 4219557L: '[', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: 'q', 140737488345977L: ':', 140737488345978L: 'J', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_86(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'R12': 4782897L, 'RAX': 9L, 'RSP': 140737488344160L, 'RDX': 32L, 'RIP': 4203624L, 'RBP': 7049504L}, 'memory': {140737488344160L: '\x00', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 4203625L: '\\', 4203624L: 'A', 140737488344151L: '\x00', 140737488344152L: ' ', 140737488344153L: '\x91', 140737488344154L: 'k', 140737488344155L: '\x00', 140737488344156L: '\x00', 140737488344157L: '\x00', 140737488344158L: '\x00', 140737488344159L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'R12': 0L, 'RAX': 9L, 'RSP': 140737488344168L, 'RDX': 32L, 'RIP': 4203626L, 'RBP': 7049504L}, 'memory': {140737488344151L: '\x00', 140737488344152L: ' ', 140737488344153L: '\x91', 140737488344154L: 'k', 140737488344155L: '\x00', 140737488344156L: '\x00', 140737488344157L: '\x00', 140737488344158L: '\x00', 140737488344159L: '\x00', 140737488344160L: '\x00', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 4203625L: '\\', 140737488344170L: '\x00', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 4203624L: 'A', 140737488344169L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_87(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'R12': 140737488346078L, 'RAX': 4194304L, 'RSP': 140737488346104L, 'RDX': 64L, 'RIP': 4284646L, 'RBP': 32768L}, 'memory': {140737488346112L: '\x90', 4284646L: 'A', 4284647L: '\\', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x80', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h', 140737488346105L: '\xdd', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'R12': 140737488346472L, 'RAX': 4194304L, 'RSP': 140737488346112L, 'RDX': 64L, 'RIP': 4284648L, 'RBP': 32768L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 4284646L: 'A', 4284647L: '\\', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x80', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'h', 140737488346105L: '\xdd', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_88(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'R13': 35L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 96L, 'RIP': 4320796L, 'RBP': 3L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320796L: 'A', 4320797L: ']'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 96L, 'RIP': 4320798L, 'RBP': 3L}, 'memory': {4320796L: 'A', 4320797L: ']', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_89(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'RBX': 7049240L, 'RDI': 0L, 'RAX': 7058320L, 'RSP': 140737488346192L, 'RDX': 7058320L, 'RIP': 4198443L, 'RBP': 0L}, 'memory': {140737488346187L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x04', 140737488346185L: '\x00', 140737488346186L: '\x00', 4198443L: '[', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xc4'}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'RBX': 4197776L, 'RDI': 0L, 'RAX': 7058320L, 'RSP': 140737488346200L, 'RDX': 7058320L, 'RIP': 4198444L, 'RBP': 0L}, 'memory': {4198443L: '[', 140737488346183L: '\x00', 140737488346184L: '\x04', 140737488346185L: '\x00', 140737488346186L: '\x00', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xc4', 140737488346201L: '\x10', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_9(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'R12': 140737488345863L, 'RAX': 199173L, 'RSP': 140737488346216L, 'RDX': 5L, 'RIP': 4299529L, 'RBP': 0L}, 'memory': {140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\xf0', 140737488346217L: '\x0c', 140737488346218L: '@', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4299529L: 'A', 4299530L: '\\', 140737488346207L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'R12': 4197616L, 'RAX': 199173L, 'RSP': 140737488346224L, 'RDX': 5L, 'RIP': 4299531L, 'RBP': 0L}, 'memory': {4299529L: 'A', 4299530L: '\\', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\xf0', 140737488346217L: '\x0c', 140737488346218L: '@', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_90(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 140737488346079L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346024L, 'RDX': 64L, 'RIP': 4283980L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283980L: 'A', 4283981L: '^', 140737488346015L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 4096L, 'RSI': 1L, 'RDI': 4L, 'RAX': 4194304L, 'RSP': 140737488346032L, 'RDX': 64L, 'RIP': 4283982L, 'RBP': 194L}, 'memory': {140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: 'r', 4283980L: 'A', 4283981L: '^'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_91(self):
''' Instruction POP RBX '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4195080L, 'RDI': 6L, 'RAX': 4467264L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197593L, 'RBP': 12L}, 'memory': {140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4197593L: '['}}, 'text': '[', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4197776L, 'RDI': 6L, 'RAX': 4467264L, 'RSP': 140737488346200L, 'RDX': 0L, 'RIP': 4197594L, 'RBP': 12L}, 'memory': {140737488346201L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4197593L: '[', 140737488346202L: '\x00', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\xf0'}}, 'disassembly': 'POP RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_92(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'R12': 7051320L, 'RAX': 7074256L, 'RSP': 140737488345992L, 'RDX': 33L, 'RIP': 4219559L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 4219560L: '\\', 4219559L: 'A', 140737488345983L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074256L, 'RSI': 7074272L, 'RDI': 7213056L, 'R12': 24L, 'RAX': 7074256L, 'RSP': 140737488346000L, 'RDX': 33L, 'RIP': 4219561L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 4219559L: 'A', 4219560L: '\\', 140737488345983L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_93(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346008L, 'RDX': 1617L, 'RIP': 4219563L, 'RBP': 7051232L}, 'memory': {140737488346016L: '\x00', 4219563L: 'A', 4219564L: '^', 140737488345999L: '\x00', 140737488346000L: '\n', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346016L, 'RDX': 1617L, 'RIP': 4219565L, 'RBP': 7051232L}, 'memory': {140737488345999L: '\x00', 140737488346000L: '\n', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x04', 4219563L: 'A', 4219564L: '^'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_94(self):
''' Instruction POP R13 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'R13': 7L, 'RAX': 6L, 'RSP': 140737488346176L, 'RDX': 4L, 'RIP': 4298257L, 'RBP': 140737488346472L}, 'memory': {140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x00', 4298257L: 'A', 4298258L: ']', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'A]', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'R13': 7L, 'RAX': 6L, 'RSP': 140737488346184L, 'RDX': 4L, 'RIP': 4298259L, 'RBP': 140737488346472L}, 'memory': {4298257L: 'A', 4298258L: ']', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x00', 140737488346185L: '\x00', 140737488346186L: '\x00', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00'}}, 'disassembly': 'POP R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_95(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'R12': 4788816L, 'RAX': 0L, 'RSP': 140737488346040L, 'RDX': 7065872L, 'RIP': 4212947L, 'RBP': 140737488346112L}, 'memory': {140737488346048L: '\x07', 140737488346045L: '\x00', 140737488346041L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 4212947L: 'A', 4212948L: '\\', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346036L: '\xff', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346035L: '\xff', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'R12': 0L, 'RAX': 0L, 'RSP': 140737488346048L, 'RDX': 7065872L, 'RIP': 4212949L, 'RBP': 140737488346112L}, 'memory': {140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346041L: '\x00', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x07', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 4212947L: 'A', 4212948L: '\\'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_96(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 0L, 'RCX': 7051320L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345800L, 'RDX': 2016L, 'RIP': 4211205L, 'RBP': 7051232L}, 'memory': {140737488345792L: '\x07', 140737488345793L: '\x00', 140737488345794L: '\x00', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\x00', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 4211206L: '^', 140737488345791L: '\x00', 4211205L: 'A'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 0L, 'RCX': 7051320L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 1L, 'RSP': 140737488345808L, 'RDX': 2016L, 'RIP': 4211207L, 'RBP': 7051232L}, 'memory': {4211205L: 'A', 4211206L: '^', 140737488345791L: '\x00', 140737488345792L: '\x07', 140737488345793L: '\x00', 140737488345794L: '\x00', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\x00', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\x84'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_97(self):
''' Instruction POP RBP '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488345984L, 'RDX': 1617L, 'RIP': 4219558L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 4219558L: ']', 140737488345975L: '\x00', 140737488345976L: '\xd0', 140737488345977L: '\xf1', 140737488345978L: 'k', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'text': ']', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488345992L, 'RDX': 1617L, 'RIP': 4219559L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 140737488345993L: '\x06', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\n', 4219558L: ']', 140737488345975L: '\x00', 140737488345976L: '\xd0', 140737488345977L: '\xf1', 140737488345978L: 'k', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'disassembly': 'POP RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_98(self):
''' Instruction POP R14 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 0L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 7059408L, 'RIP': 4205988L, 'RBP': 7054832L}, 'memory': {140737488346144L: '\x01', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 4205988L: 'A', 140737488346143L: '\x00', 4205989L: '^'}}, 'text': 'A^', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 0L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 7059408L, 'RIP': 4205990L, 'RBP': 7054832L}, 'memory': {140737488346143L: '\x00', 140737488346144L: '\x01', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 4205988L: 'A', 4205989L: '^', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'm', 140737488346148L: '\x00', 140737488346149L: '\x00'}}, 'disassembly': 'POP R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPOP_99(self):
''' Instruction POP R12 '''
test = {'mnemonic': 'POP', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'R12': 0L, 'RAX': 0L, 'RSP': 140737488346072L, 'RDX': 0L, 'RIP': 4205595L, 'RBP': 7054832L}, 'memory': {140737488346080L: '\x01', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\xf0', 140737488346065L: '\xa5', 140737488346066L: 'k', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\xf8', 140737488346073L: '\xa5', 140737488346074L: 'k', 4205595L: 'A', 4205596L: '\\', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00'}}, 'text': 'A\\', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'R12': 7054840L, 'RAX': 0L, 'RSP': 140737488346080L, 'RDX': 0L, 'RIP': 4205597L, 'RBP': 7054832L}, 'memory': {4205595L: 'A', 4205596L: '\\', 140737488346063L: '\x00', 140737488346064L: '\xf0', 140737488346065L: '\xa5', 140737488346066L: 'k', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\xf8', 140737488346073L: '\xa5', 140737488346074L: 'k', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00', 140737488346080L: '\x01', 140737488346081L: '\x00', 140737488346082L: '\x00', 140737488346083L: '\x00', 140737488346084L: '\x00', 140737488346085L: '\x00', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: '\x00'}}, 'disassembly': 'POP R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_1(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4783042L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4783042L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_10(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4782997L, 'RSI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4782997L, 'RSI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_11(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4783016L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4783016L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_2(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4782991L, 'RSI': 4294967295L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4782991L, 'RSI': 4294967295L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_3(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 791621423, 'RCX': 140737488347312L, 'RSI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416334L, 'RBP': 140737488347312L}, 'memory': {4416336L: 'p', 4416337L: '\xc9', 4416338L: '\x00', 4416334L: 'f', 4416335L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 62718710765820030520700417840365121327L, 'RCX': 140737488347312L, 'RSI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416339L, 'RBP': 140737488347312L}, 'memory': {4416336L: 'p', 4416337L: '\xc9', 4416338L: '\x00', 4416334L: 'f', 4416335L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_4(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4783036L, 'RSI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4783036L, 'RSI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_5(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4783048L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4783048L, 'RSI': 4294967295L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_6(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4782899L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4782899L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_7(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4783022L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4783022L, 'RSI': 4294967295L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_8(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4782888L, 'RSI': 4294967295L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4782888L, 'RSI': 4294967295L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPSHUFD_9(self):
''' Instruction PSHUFD XMM1, XMM1, 0x0 '''
test = {'mnemonic': 'PSHUFD', 'pre': {'registers': {'RFLAGS': 646L, 'XMM1': 623191333, 'RCX': 4782903L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247998L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'text': 'f\x0fp\xc9\x00', 'pos': {'registers': {'RFLAGS': 646L, 'XMM1': 49374304219900875090764158725393818917L, 'RCX': 4782903L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248000L: 'p', 4248001L: '\xc9', 4248002L: '\x00', 4247998L: 'f', 4247999L: '\x0f'}}, 'disassembly': 'PSHUFD XMM1, XMM1, 0x0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_1(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4782888L, 'RSI': 37L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 623191333, 'RCX': 4782888L, 'RSI': 37L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_10(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 37, 'RCX': 4782888L, 'RSI': 37L, 'RDI': 4782888L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 9509, 'RCX': 4782888L, 'RSI': 37L, 'RDI': 4782888L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_11(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4783048L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4783048L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_12(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 37, 'RCX': 4783036L, 'RSI': 37L, 'RDI': 4783036L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4783036L, 'RSI': 37L, 'RDI': 4783036L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_13(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 12079, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416323L, 'RBP': 140737488347312L}, 'memory': {4416323L: 'f', 4416324L: '\x0f', 4416325L: '`', 4416326L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 791621423, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416327L, 'RBP': 140737488347312L}, 'memory': {4416323L: 'f', 4416324L: '\x0f', 4416325L: '`', 4416326L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_14(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 37, 'RCX': 4783022L, 'RSI': 37L, 'RDI': 4783022L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4783022L, 'RSI': 37L, 'RDI': 4783022L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_15(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_16(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_17(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4782997L, 'RSI': 37L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4782997L, 'RSI': 37L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_18(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 37, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782899L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782899L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_19(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 37, 'RCX': 4782991L, 'RSI': 37L, 'RDI': 4782991L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 9509, 'RCX': 4782991L, 'RSI': 37L, 'RDI': 4782991L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_2(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 37, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782903L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782903L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_20(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 37, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783042L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783042L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_21(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4782991L, 'RSI': 37L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 623191333, 'RCX': 4782991L, 'RSI': 37L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_22(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 37, 'RCX': 4783016L, 'RSI': 37L, 'RDI': 4783016L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 9509, 'RCX': 4783016L, 'RSI': 37L, 'RDI': 4783016L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_3(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4783036L, 'RSI': 37L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 623191333, 'RCX': 4783036L, 'RSI': 37L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_4(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4783016L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4783016L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_5(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_6(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 37, 'RCX': 4783048L, 'RSI': 37L, 'RDI': 4783048L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 9509, 'RCX': 4783048L, 'RSI': 37L, 'RDI': 4783048L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_7(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 37, 'RCX': 4782997L, 'RSI': 37L, 'RDI': 4782997L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247975L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4782997L, 'RSI': 37L, 'RDI': 4782997L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247979L, 'RBP': 140737488345936L}, 'memory': {4247976L: '\x0f', 4247977L: '`', 4247978L: '\xc9', 4247975L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_8(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 47, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416311L, 'RBP': 140737488347312L}, 'memory': {4416312L: '\x0f', 4416313L: '`', 4416314L: '\xc9', 4416311L: 'f'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 12079, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416315L, 'RBP': 140737488347312L}, 'memory': {4416312L: '\x0f', 4416313L: '`', 4416314L: '\xc9', 4416311L: 'f'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUNPCKLBW_9(self):
''' Instruction PUNPCKLBW XMM1, XMM1 '''
test = {'mnemonic': 'PUNPCKLBW', 'pre': {'registers': {'RFLAGS': 518L, 'XMM1': 9509, 'RCX': 4783022L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'text': 'f\x0f`\xc9', 'pos': {'registers': {'RFLAGS': 518L, 'XMM1': 623191333, 'RCX': 4783022L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247991L, 'RBP': 140737488345936L}, 'memory': {4247987L: 'f', 4247988L: '\x0f', 4247989L: '`', 4247990L: '\xc9'}}, 'disassembly': 'PUNPCKLBW XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_1(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RBX': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4205739L, 'RBP': 7054832L}, 'memory': {140737488346123L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xb1', 140737488346121L: '\x04', 140737488346122L: '@', 4205739L: 'S', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\xf0', 140737488346129L: '\xa5', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xf8'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RBX': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4205740L, 'RBP': 7054832L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x00', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\xf0', 140737488346129L: '\xa5', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xf8', 4205739L: 'S', 140737488346111L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_10(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 1L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283765L, 'RBP': 194L}, 'memory': {140737488346038L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 4283766L: 'V', 140737488346039L: '\x00', 140737488346040L: '^', 4283765L: 'A'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 1L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346024L, 'RDX': 140737488346078L, 'RIP': 4283767L, 'RBP': 194L}, 'memory': {140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 4283765L: 'A', 4283766L: 'V'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_100(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051336L, 'RSP': 140737488345816L, 'RDX': 2L, 'RIP': 4210752L, 'RBP': 7051232L}, 'memory': {140737488345824L: '\x00', 4210752L: 'A', 4210753L: 'W', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\x84', 140737488345817L: 'c', 140737488345818L: '@', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 7051336L, 'RSP': 140737488345808L, 'RDX': 2L, 'RIP': 4210754L, 'RBP': 7051232L}, 'memory': {4210752L: 'A', 4210753L: 'W', 140737488345799L: 'o', 140737488345800L: 's', 140737488345801L: 't', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '\x84', 140737488345817L: 'c', 140737488345818L: '@', 140737488345819L: '\x00', 140737488345820L: '\x00', 140737488345821L: '\x00', 140737488345822L: '\x00', 140737488345823L: '\x00', 140737488345824L: '\x00'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_101(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 2567L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346208L, 'RDX': 12297829382473034411L, 'RIP': 4197529L, 'RBP': 0L}, 'memory': {140737488346208L: '\xf0', 140737488346209L: '\x0c', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346201L: '\r', 140737488346199L: '\x00', 140737488346200L: '\x90', 4197529L: 'U', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 2567L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346200L, 'RDX': 12297829382473034411L, 'RIP': 4197530L, 'RBP': 0L}, 'memory': {4197529L: 'U', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 140737488346201L: '\x00', 140737488346202L: '\x00', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\xf0', 140737488346209L: '\x0c', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_11(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'R12': 140737354125312L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 699L, 'RIP': 4392983L, 'RBP': 7049504L}, 'memory': {140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa', 140737488345911L: '\x00', 140737488345912L: '\x07', 4392983L: 'A', 4392984L: 'T', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'R12': 140737354125312L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 699L, 'RIP': 4392985L, 'RBP': 7049504L}, 'memory': {4392983L: 'A', 4392984L: 'T', 140737488345903L: '\x00', 140737488345904L: '\xf0', 140737488345905L: '\x0c', 140737488345906L: '@', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: '\xd0', 140737488345914L: '\xff', 140737488345915L: '\xf7', 140737488345916L: '\xff', 140737488345917L: '\x7f', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_12(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 140737488346078L, 'RIP': 4283775L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346015L: '\x00', 4283776L: 'T', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 4283775L: 'A'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 140737488346078L, 'RIP': 4283777L, 'RBP': 194L}, 'memory': {4283776L: 'T', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 4283775L: 'A'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_13(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 0L, 'RBX': 4197776L, 'RDI': 7049240L, 'RAX': 18446744073709551600L, 'RSP': 140737488346200L, 'RDX': 0L, 'RIP': 4198192L, 'RBP': 0L}, 'memory': {140737488346208L: '\x90', 140737488346192L: 'h', 140737488346191L: '\x00', 4198192L: 'S', 140737488346193L: '\xdd', 140737488346194L: '\xff', 140737488346195L: '\xff', 140737488346196L: '\xff', 140737488346197L: '\x7f', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xc4', 140737488346201L: '\x10', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 0L, 'RBX': 4197776L, 'RDI': 7049240L, 'RAX': 18446744073709551600L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4198193L, 'RBP': 0L}, 'memory': {4198192L: 'S', 140737488346183L: '\x00', 140737488346184L: '\x04', 140737488346185L: '\x00', 140737488346186L: '\x00', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xc4', 140737488346201L: '\x10', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_14(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346160L, 'RDX': 7058304L, 'RIP': 4197777L, 'RBP': 7049240L}, 'memory': {140737488346161L: '\x90', 140737488346151L: '\x00', 140737488346152L: '\xf0', 140737488346153L: '\x0c', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x18', 4197777L: 'S', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346152L, 'RDX': 7058304L, 'RIP': 4197778L, 'RBP': 7049240L}, 'memory': {4197777L: 'S', 140737488346143L: '\x00', 140737488346144L: 'p', 140737488346145L: '\xdc', 140737488346146L: '\xff', 140737488346147L: '\xff', 140737488346148L: '\xff', 140737488346149L: '\x7f', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_15(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346072L, 'RDX': 0L, 'RIP': 4205080L, 'RBP': 7054832L}, 'memory': {140737488346080L: '\x01', 140737488346075L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 4205080L: 'U', 140737488346073L: '\xa5', 140737488346074L: 'k', 140737488346072L: '\xf8', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4205081L, 'RBP': 7054832L}, 'memory': {4205080L: 'U', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\xf0', 140737488346065L: '\xa5', 140737488346066L: 'k', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\xf8', 140737488346073L: '\xa5', 140737488346074L: 'k', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00', 140737488346080L: '\x01'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_16(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'R13': 10L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 2L, 'RIP': 4219316L, 'RBP': 7051232L}, 'memory': {140737488346016L: '\x00', 140737488346015L: '\x00', 140737488346009L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 4219316L: 'A', 4219317L: 'U', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346004L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346005L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'R13': 10L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 2L, 'RIP': 4219318L, 'RBP': 7051232L}, 'memory': {140737488345991L: '\x00', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\n', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\x00', 4219316L: 'A', 4219317L: 'U'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_17(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346224L, 'RDX': 140737488346512L, 'RIP': 4197618L, 'RBP': 0L}, 'memory': {140737488346227L: '\x00', 140737488346226L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 4197618L: 'A', 4197619L: 'V', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346216L, 'RDX': 140737488346512L, 'RIP': 4197620L, 'RBP': 0L}, 'memory': {4197618L: 'A', 4197619L: 'V', 140737488346207L: '\x00', 140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_18(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347264L, 'R13': 0L, 'RAX': 7053688L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4299360L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4299360L: 'A', 4299361L: 'U', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347264L, 'R13': 0L, 'RAX': 7053688L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4299362L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4299360L: 'A', 4299361L: 'U', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_19(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347264L, 'R12': 4197616L, 'RAX': 7053688L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4299362L, 'RBP': 0L}, 'memory': {4299362L: 'A', 4299363L: 'T', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347264L, 'R12': 4197616L, 'RAX': 7053688L, 'RSP': 140737488346216L, 'RDX': 0L, 'RIP': 4299364L, 'RBP': 0L}, 'memory': {4299362L: 'A', 4299363L: 'T', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\xf0', 140737488346217L: '\x0c', 140737488346218L: '@', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xa3'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_2(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 1L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283765L, 'RBP': 188L}, 'memory': {140737488346038L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 4283766L: 'V', 140737488346039L: '\x00', 140737488346040L: 'r', 4283765L: 'A'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 1L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488346024L, 'RDX': 140737488346078L, 'RIP': 4283767L, 'RBP': 188L}, 'memory': {140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: 'r', 4283765L: 'A', 4283766L: 'V'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_20(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 3L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320697L: 'A', 4320698L: 'T'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320699L, 'RBP': 3L}, 'memory': {4320697L: 'A', 4320698L: 'T', 140737488345919L: '\x00', 140737488345920L: '\x00', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_21(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346040L, 'RDX': 140737488346078L, 'RIP': 4283760L, 'RBP': 188L}, 'memory': {140737488346048L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346031L: '\x00', 4283760L: 'A', 4283761L: 'W', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283762L, 'RBP': 188L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x04', 140737488346025L: '\x8c', 140737488346026L: '@', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 4283760L: 'A', 4283761L: 'W'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_22(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346232L, 'RDX': 140737488346512L, 'RIP': 4197616L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346224L: '\xf0', 140737488346225L: '\x0c', 140737488346223L: '\x00', 4197616L: 'A', 4197617L: 'W', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346224L, 'RDX': 140737488346512L, 'RIP': 4197618L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346224L: '\x00', 4197617L: 'W', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 4197616L: 'A', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_23(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346200L, 'RDX': 1L, 'RIP': 4197863L, 'RBP': 0L}, 'memory': {140737488346208L: '\x07', 4197863L: 'U', 140737488346191L: '\x00', 140737488346192L: 'h', 140737488346193L: '\xdd', 140737488346194L: '\xff', 140737488346195L: '\xff', 140737488346196L: '\xff', 140737488346197L: '\x7f', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346192L, 'RDX': 1L, 'RIP': 4197864L, 'RBP': 0L}, 'memory': {140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346185L: '\xdd', 140737488346186L: '\xff', 140737488346187L: '\xff', 140737488346188L: '\xff', 140737488346189L: '\x7f', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x07', 4197863L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_24(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 188L, 'R13': 140737488346079L, 'RAX': 0L, 'RSP': 140737488346024L, 'RDX': 140737488346078L, 'RIP': 4283770L, 'RBP': 188L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283770L: 'A', 4283771L: 'U', 140737488346015L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 188L, 'R13': 140737488346079L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 140737488346078L, 'RIP': 4283772L, 'RBP': 188L}, 'memory': {140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283770L: 'A', 4283771L: 'U'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_25(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 140737488346512L, 'RIP': 4195528L, 'RBP': 4L}, 'memory': {140737488346144L: '0', 140737488346145L: '\xe8', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 4195528L: 'U', 140737488346143L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4195529L, 'RBP': 4L}, 'memory': {140737488346135L: '\x00', 140737488346136L: 'P', 140737488346137L: '\x00', 140737488346138L: '\x00', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 4195528L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_26(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 663L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00', 4320689L: 'W', 4320688L: 'A', 140737488345951L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 663L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 9L}, 'memory': {4320688L: 'A', 4320689L: 'W', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_27(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RBX': 0L, 'RDI': 4195596L, 'RAX': 0L, 'RSP': 140737488346416L, 'RDX': 140737488346472L, 'RIP': 4195867L, 'RBP': 0L}, 'memory': {140737488346407L: '\x00', 140737488346408L: '\x00', 140737488346409L: '\x00', 140737488346410L: '\x00', 140737488346411L: '\x00', 140737488346412L: '\x00', 140737488346413L: '\x00', 140737488346414L: '\x00', 140737488346415L: '\x00', 140737488346416L: '\x00', 140737488346417L: '\x00', 140737488346418L: '\x00', 140737488346419L: '\x00', 140737488346420L: '\x00', 140737488346421L: '\x00', 140737488346422L: '\x00', 140737488346423L: '\x00', 140737488346424L: '\x00', 4195867L: 'S'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RBX': 0L, 'RDI': 4195596L, 'RAX': 0L, 'RSP': 140737488346408L, 'RDX': 140737488346472L, 'RIP': 4195868L, 'RBP': 0L}, 'memory': {4195867L: 'S', 140737488346399L: '\x00', 140737488346400L: '\x00', 140737488346401L: '\x00', 140737488346402L: '\x00', 140737488346403L: '\x00', 140737488346404L: '\x00', 140737488346405L: '\x00', 140737488346406L: '\x00', 140737488346407L: '\x00', 140737488346408L: '\x00', 140737488346409L: '\x00', 140737488346410L: '\x00', 140737488346411L: '\x00', 140737488346412L: '\x00', 140737488346413L: '\x00', 140737488346414L: '\x00', 140737488346415L: '\x00', 140737488346416L: '\x00', 140737488346417L: '\x00', 140737488346418L: '\x00', 140737488346419L: '\x00', 140737488346420L: '\x00', 140737488346421L: '\x00', 140737488346422L: '\x00', 140737488346423L: '\x00', 140737488346424L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_28(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 140737488346078L, 'RIP': 4283777L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 4283777L: 'U', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 140737488346078L, 'RIP': 4283778L, 'RBP': 194L}, 'memory': {4283777L: 'U', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_29(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 7049504L, 'R12': 0L, 'RAX': 0L, 'RSP': 140737488344168L, 'RDX': 9L, 'RIP': 4203452L, 'RBP': 7049504L}, 'memory': {140737488344160L: '\t', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 140737488344169L: '\x00', 140737488344170L: '\x00', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 4203452L: 'A', 4203453L: 'T', 140737488344159L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 7049504L, 'R12': 0L, 'RAX': 0L, 'RSP': 140737488344160L, 'RDX': 9L, 'RIP': 4203454L, 'RBP': 7049504L}, 'memory': {4203452L: 'A', 4203453L: 'T', 140737488344151L: '\x00', 140737488344152L: 'x', 140737488344153L: '\x1b', 140737488344154L: 'C', 140737488344155L: '\x00', 140737488344156L: '\x00', 140737488344157L: '\x00', 140737488344158L: '\x00', 140737488344159L: '\x00', 140737488344160L: '\x00', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 140737488344169L: '\x00', 140737488344170L: '\x00', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '('}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_3(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'R13': 7L, 'RAX': 7059656L, 'RSP': 140737488346216L, 'RDX': 140737488346512L, 'RIP': 4197620L, 'RBP': 0L}, 'memory': {140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4197620L: 'A', 4197621L: 'U', 140737488346207L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'R13': 7L, 'RAX': 7059656L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4197622L, 'RBP': 0L}, 'memory': {140737488346199L: '\x00', 140737488346200L: '\xc4', 140737488346201L: '\x10', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4197620L: 'A', 4197621L: 'U'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_30(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320693L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 4320693L: 'A', 4320694L: 'V', 140737488345943L: '\x00', 140737488345944L: 'e', 140737488345945L: '\x00', 140737488345946L: '\x00', 140737488345947L: '\x00', 140737488345948L: 'I', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 68L, 'RIP': 4320695L, 'RBP': 3L}, 'memory': {4320693L: 'A', 4320694L: 'V', 140737488345935L: '\x00', 140737488345936L: '\x00', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_31(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4467264L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4196770L, 'RBP': 0L}, 'memory': {4196770L: 'A', 4196771L: 'V', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4467264L, 'RSP': 140737488346216L, 'RDX': 0L, 'RIP': 4196772L, 'RBP': 0L}, 'memory': {4196770L: 'A', 4196771L: 'V', 140737488346207L: '\x00', 140737488346208L: '\xf0', 140737488346209L: '\x0c', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_32(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4205732L, 'RBP': 7054832L}, 'memory': {4205732L: 'A', 4205733L: 'V', 140737488346151L: '\x00', 140737488346152L: '\x11', 140737488346153L: '\xfb', 140737488346154L: 'H', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'm'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 0L, 'RIP': 4205734L, 'RBP': 7054832L}, 'memory': {140737488346143L: '\x00', 140737488346144L: '\x18', 140737488346145L: '\x90', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 4205733L: 'V', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'm', 4205732L: 'A', 140737488346149L: '\x00'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_33(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4467264L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4196768L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4196768L: 'A', 4196769L: 'W', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4467264L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4196770L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4196768L: 'A', 4196769L: 'W', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xda', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_34(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RBX': 4864625L, 'RDI': 7051232L, 'RAX': 7051336L, 'RSP': 140737488345776L, 'RDX': 18446744073709551600L, 'RIP': 4210775L, 'RBP': 7051232L}, 'memory': {140737488345767L: '\x00', 140737488345768L: '\x00', 140737488345769L: '\x00', 140737488345770L: '\x00', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '\xe0', 140737488345777L: '\x97', 140737488345778L: 'k', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\x18', 4210775L: 'S'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RBX': 4864625L, 'RDI': 7051232L, 'RAX': 7051336L, 'RSP': 140737488345768L, 'RDX': 18446744073709551600L, 'RIP': 4210776L, 'RBP': 7051232L}, 'memory': {140737488345759L: '\x00', 140737488345760L: '\x00', 140737488345761L: '\x00', 140737488345762L: '\x00', 140737488345763L: '\x00', 140737488345764L: '\x00', 140737488345765L: '\x00', 140737488345766L: '\x00', 140737488345767L: '\x00', 140737488345768L: 'q', 140737488345769L: ':', 140737488345770L: 'J', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '\xe0', 140737488345777L: '\x97', 140737488345778L: 'k', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\x18', 4210775L: 'S'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_35(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 3L, 'RSP': 140737488345944L, 'RDX': 68L, 'RIP': 4320695L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345944L: '\xdf', 140737488345943L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 4320695L: 'A', 4320696L: 'U', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 3L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 3L}, 'memory': {4320695L: 'A', 4320696L: 'U', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_36(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7042728L, 'RSI': 140737488346472L, 'RDI': 0L, 'R13': 7L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7042720L, 'RIP': 4519938L, 'RBP': 140737488346112L}, 'memory': {140737488346112L: 'h', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'z', 4519938L: 'A', 4519939L: 'U', 140737488346103L: '\x00', 140737488346104L: '\x00', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7042728L, 'RSI': 140737488346472L, 'RDI': 0L, 'R13': 7L, 'RAX': 0L, 'RSP': 140737488346104L, 'RDX': 7042720L, 'RIP': 4519940L, 'RBP': 140737488346112L}, 'memory': {140737488346112L: 'h', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'z', 4519938L: 'A', 4519939L: 'U', 140737488346095L: '\x00', 140737488346096L: '\x07', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\x07', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_37(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R12': 24L, 'RAX': 7051336L, 'RSP': 140737488345792L, 'RDX': 18446744073709551600L, 'RIP': 4210772L, 'RBP': 7051232L}, 'memory': {140737488345792L: '\x07', 140737488345793L: '\x00', 140737488345794L: '\x00', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\x00', 4210772L: 'A', 4210773L: 'T', 140737488345783L: '\x00', 140737488345784L: '\x00', 140737488345785L: '\x00', 140737488345786L: '\x00', 140737488345787L: '\x00', 140737488345788L: '\x00', 140737488345789L: '\x00', 140737488345790L: '\x00', 140737488345791L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R12': 24L, 'RAX': 7051336L, 'RSP': 140737488345784L, 'RDX': 18446744073709551600L, 'RIP': 4210774L, 'RBP': 7051232L}, 'memory': {140737488345775L: '\x00', 140737488345776L: '\x00', 140737488345777L: '\x00', 140737488345778L: '\x00', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\x18', 140737488345785L: '\x00', 140737488345786L: '\x00', 140737488345787L: '\x00', 140737488345788L: '\x00', 140737488345789L: '\x00', 140737488345790L: '\x00', 140737488345791L: '\x00', 140737488345792L: '\x07', 140737488345793L: '\x00', 140737488345794L: '\x00', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\x00', 4210772L: 'A', 4210773L: 'T'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_38(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 7734106L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320706L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 4320706L: 'S', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: 'Z', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 7734106L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345912L, 'RDX': 68L, 'RIP': 4320707L, 'RBP': 4792416L}, 'memory': {4320706L: 'S', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: 'Z', 140737488345913L: '\x03', 140737488345914L: 'v', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_39(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 64L, 'RSI': 13L, 'RDI': 194L, 'RAX': 32768L, 'RSP': 140737488346128L, 'RDX': 64L, 'RIP': 4284418L, 'RBP': 32768L}, 'memory': {4284418L: 'A', 4284419L: 'V', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 1L, 'RCX': 64L, 'RSI': 13L, 'RDI': 194L, 'RAX': 32768L, 'RSP': 140737488346120L, 'RDX': 64L, 'RIP': 4284420L, 'RBP': 32768L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 4284418L: 'A', 4284419L: 'V', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346111L: '\x00'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_4(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 663L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 3L}, 'memory': {140737488345952L: '^', 140737488345953L: '\x00', 140737488345954L: '\x00', 140737488345955L: '\x00', 140737488345956L: 'n', 140737488345957L: '\x00', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00', 4320689L: 'W', 4320688L: 'A', 140737488345951L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 663L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 3L}, 'memory': {4320688L: 'A', 4320689L: 'W', 140737488345943L: '\x00', 140737488345944L: 'e', 140737488345945L: '\x00', 140737488345946L: '\x00', 140737488345947L: '\x00', 140737488345948L: 'I', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_40(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'R12': 4197616L, 'RAX': 7059656L, 'RSP': 140737488346208L, 'RDX': 140737488346512L, 'RIP': 4197625L, 'RBP': 0L}, 'memory': {140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346205L: '\x00', 140737488346201L: '\x10', 140737488346199L: '\x00', 140737488346200L: '\xc4', 4197625L: 'A', 4197626L: 'T', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346202L: '@', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'R12': 4197616L, 'RAX': 7059656L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4197627L, 'RBP': 0L}, 'memory': {140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x07', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 4197625L: 'A', 4197626L: 'T'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_41(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'R13': 140737488346079L, 'RAX': 0L, 'RSP': 140737488346024L, 'RDX': 140737488346078L, 'RIP': 4283770L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283770L: 'A', 4283771L: 'U', 140737488346015L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'R13': 140737488346079L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 140737488346078L, 'RIP': 4283772L, 'RBP': 194L}, 'memory': {140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 4283770L: 'A', 4283771L: 'U'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_42(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 659L, 'R15': 0L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4205728L, 'RBP': 7054832L}, 'memory': {140737488346176L: '\x07', 4205728L: 'A', 4205729L: 'W', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'm', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 659L, 'R15': 0L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346160L, 'RDX': 0L, 'RIP': 4205730L, 'RBP': 7054832L}, 'memory': {4205728L: 'A', 4205729L: 'W', 140737488346151L: '\x00', 140737488346152L: '\x11', 140737488346153L: '\xfb', 140737488346154L: 'H', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'm', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_43(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R13': 7L, 'RAX': 7051336L, 'RSP': 140737488345800L, 'RDX': 18446744073709551600L, 'RIP': 4210770L, 'RBP': 7051232L}, 'memory': {140737488345792L: '\x00', 140737488345793L: 'l', 140737488345794L: 'o', 140737488345795L: 'c', 140737488345796L: 'a', 140737488345797L: 'l', 140737488345798L: 'h', 140737488345799L: 'o', 140737488345800L: '\x00', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 4210770L: 'A', 4210771L: 'U', 140737488345791L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'R13': 7L, 'RAX': 7051336L, 'RSP': 140737488345792L, 'RDX': 18446744073709551600L, 'RIP': 4210772L, 'RBP': 7051232L}, 'memory': {140737488345783L: '\x00', 140737488345784L: '\x00', 140737488345785L: '\x00', 140737488345786L: '\x00', 140737488345787L: '\x00', 140737488345788L: '\x00', 140737488345789L: '\x00', 140737488345790L: '\x00', 140737488345791L: '\x00', 140737488345792L: '\x07', 140737488345793L: '\x00', 140737488345794L: '\x00', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\x00', 140737488345801L: '\x00', 140737488345802L: '\x00', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 4210770L: 'A', 4210771L: 'U'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_44(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 43L, 'RSI': 4783016L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488345944L, 'RDX': 140737488345952L, 'RIP': 4329520L, 'RBP': 140737488346224L}, 'memory': {140737488345952L: '\x08', 140737488345936L: 'p', 140737488345935L: '\x00', 4329520L: 'U', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 43L, 'RSI': 4783016L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488345936L, 'RDX': 140737488345952L, 'RIP': 4329521L, 'RBP': 140737488346224L}, 'memory': {4329520L: 'U', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\x08'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_45(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 7049240L, 'RBX': 4197776L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346192L, 'RDX': 1L, 'RIP': 4197867L, 'RBP': 7049240L}, 'memory': {140737488346187L: '\xff', 140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346185L: '\xdd', 140737488346186L: '\xff', 4197867L: 'S', 140737488346188L: '\xff', 140737488346189L: '\x7f', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 7049240L, 'RBX': 4197776L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346184L, 'RDX': 1L, 'RIP': 4197868L, 'RBP': 7049240L}, 'memory': {140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346185L: '\r', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0', 4197867L: 'S'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_46(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4394944L, 'RBP': 0L}, 'memory': {140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 4394944L: 'S', 140737488346047L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346048L, 'RDX': 0L, 'RIP': 4394945L, 'RBP': 0L}, 'memory': {4394944L: 'S', 140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: ' ', 140737488346049L: '\x91', 140737488346050L: 'k', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' '}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_47(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346040L, 'RDX': 140737488346078L, 'RIP': 4283760L, 'RBP': 194L}, 'memory': {140737488346048L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346031L: '\x00', 4283760L: 'A', 4283761L: 'W', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283762L, 'RBP': 194L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '^', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 4283760L: 'A', 4283761L: 'W'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_48(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 1L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346136L, 'RDX': 7058304L, 'RIP': 4704448L, 'RBP': 7035176L}, 'memory': {140737488346144L: 'p', 4704448L: 'S', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xb4', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 1L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4704449L, 'RBP': 7035176L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x01', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xb4', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: 'p', 4704448L: 'S'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_49(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488346040L, 'RDX': 140737488346078L, 'RIP': 4283760L, 'RBP': 194L}, 'memory': {140737488346048L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346031L: '\x00', 4283760L: 'A', 4283761L: 'W', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 0L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RDI': 194L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 140737488346078L, 'RIP': 4283762L, 'RBP': 194L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 140737488346036L: '\x00', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: 'r', 140737488346041L: '`', 140737488346042L: 'A', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x00', 4283760L: 'A', 4283761L: 'W'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_5(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346136L, 'RDX': 7058304L, 'RIP': 4195389L, 'RBP': 140737488346144L}, 'memory': {140737488346144L: '\x18', 140737488346141L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x01', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x80', 140737488346137L: '\xb3', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 4195389L: 'S', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4195390L, 'RBP': 140737488346144L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x00', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x80', 140737488346137L: '\xb3', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x18', 4195389L: 'S'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_50(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RBX': 24L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346032L, 'RDX': 7042720L, 'RIP': 4212693L, 'RBP': 140737488346112L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x00', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 4212693L: 'S'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RBX': 24L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346024L, 'RDX': 7042720L, 'RIP': 4212694L, 'RBP': 140737488346112L}, 'memory': {140737488346015L: '\x00', 140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x18', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 4212693L: 'S'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_51(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 4320689L: 'W', 4320688L: 'A', 140737488345951L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 518L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 9L}, 'memory': {4320688L: 'A', 4320689L: 'W', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_52(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 90L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 3L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320697L: 'A', 4320698L: 'T'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 90L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320699L, 'RBP': 3L}, 'memory': {4320697L: 'A', 4320698L: 'T', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_53(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4205738L, 'RBP': 7054832L}, 'memory': {140737488346144L: '\x01', 4205738L: 'U', 140737488346127L: '\x00', 140737488346128L: '\x00', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xf8', 140737488346137L: '\xa5', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4205739L, 'RBP': 7054832L}, 'memory': {140737488346119L: '\x00', 140737488346120L: '\xb1', 140737488346121L: '\x04', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\xf0', 140737488346129L: '\xa5', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xf8', 140737488346137L: '\xa5', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x01', 4205738L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_54(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 7049504L, 'R13': 9L, 'RAX': 0L, 'RSP': 140737488344176L, 'RDX': 9L, 'RIP': 4203450L, 'RBP': 7049504L}, 'memory': {140737488344167L: '\x00', 140737488344168L: ' ', 140737488344169L: '\x91', 140737488344170L: 'k', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 140737488344177L: '\xfb', 140737488344178L: 'H', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: '\xa2', 4203450L: 'A', 4203451L: 'U'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 7049504L, 'R13': 9L, 'RAX': 0L, 'RSP': 140737488344168L, 'RDX': 9L, 'RIP': 4203452L, 'RBP': 7049504L}, 'memory': {4203450L: 'A', 4203451L: 'U', 140737488344159L: '\x00', 140737488344160L: '\t', 140737488344161L: '\x00', 140737488344162L: '\x00', 140737488344163L: '\x00', 140737488344164L: '\x00', 140737488344165L: '\x00', 140737488344166L: '\x00', 140737488344167L: '\x00', 140737488344168L: '\t', 140737488344169L: '\x00', 140737488344170L: '\x00', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 140737488344177L: '\xfb', 140737488344178L: 'H', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: '\xa2'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_55(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 0L, 'RSP': 140737488345944L, 'RDX': 68L, 'RIP': 4320695L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345944L: '\xdf', 140737488345943L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\x00', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 4320695L: 'A', 4320696L: 'U', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 3L}, 'memory': {4320695L: 'A', 4320696L: 'U', 140737488345927L: '\x00', 140737488345928L: '\x00', 140737488345929L: '\x00', 140737488345930L: '\x00', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_56(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346112L, 'RDX': 7058304L, 'RIP': 4776805L, 'RBP': 140737488346144L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xb1', 140737488346111L: '\x00', 140737488346103L: '\x00', 140737488346104L: '\x00', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 4776805L: 'U'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346104L, 'RDX': 7058304L, 'RIP': 4776806L, 'RBP': 140737488346144L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xb1', 4776805L: 'U', 140737488346095L: '\x00', 140737488346096L: '\x10', 140737488346097L: '\x97', 140737488346098L: 'k', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: ' ', 140737488346105L: '\xdc', 140737488346106L: '\xff', 140737488346107L: '\xff', 140737488346108L: '\xff', 140737488346109L: '\x7f', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_57(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320693L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 4320693L: 'A', 4320694L: 'V', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345944L, 'RDX': 68L, 'RIP': 4320695L, 'RBP': 9L}, 'memory': {4320693L: 'A', 4320694L: 'V', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_58(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4195008L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4241312L, 'RBP': 9L}, 'memory': {140737488346176L: '\x90', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 4241312L: 'S', 140737488346175L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RBX': 4195008L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4241313L, 'RBP': 9L}, 'memory': {4241312L: 'S', 140737488346167L: '\x00', 140737488346168L: '\x00', 140737488346169L: '\x02', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\xc0', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_59(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346104L, 'RDX': 0L, 'RIP': 4394304L, 'RBP': 1L}, 'memory': {140737488346112L: '@', 4394304L: 'S', 140737488346095L: '\x00', 140737488346096L: '\x00', 140737488346097L: '\x00', 140737488346098L: '\x00', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'm', 140737488346105L: '-', 140737488346106L: '@', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RBX': 7049504L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346096L, 'RDX': 0L, 'RIP': 4394305L, 'RBP': 1L}, 'memory': {140737488346112L: '@', 4394304L: 'S', 140737488346087L: '\x00', 140737488346088L: '\x00', 140737488346089L: '\x00', 140737488346090L: '\x00', 140737488346091L: '\x00', 140737488346092L: '\x00', 140737488346093L: '\x00', 140737488346094L: '\x00', 140737488346095L: '\x00', 140737488346096L: ' ', 140737488346097L: '\x91', 140737488346098L: 'k', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'm', 140737488346105L: '-', 140737488346106L: '@', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_6(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 534L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v', 4320689L: 'W', 4320688L: 'A', 140737488345951L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 534L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 3L}, 'memory': {4320688L: 'A', 4320689L: 'W', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_60(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RBX': 9L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344184L, 'RDX': 0L, 'RIP': 4394901L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 140737488344191L: '\x00', 140737488344175L: '\x00', 140737488344176L: '(', 140737488344177L: '\xfb', 140737488344178L: 'H', 140737488344179L: '\x00', 140737488344180L: '\x00', 4394901L: 'S', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: ']', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344181L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RBX': 9L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344176L, 'RDX': 0L, 'RIP': 4394902L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 4394901L: 'S', 140737488344167L: '\x00', 140737488344168L: ' ', 140737488344169L: '\x91', 140737488344170L: 'k', 140737488344171L: '\x00', 140737488344172L: '\x00', 140737488344173L: '\x00', 140737488344174L: '\x00', 140737488344175L: '\x00', 140737488344176L: '\t', 140737488344177L: '\x00', 140737488344178L: '\x00', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: ']', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_61(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346168L, 'RDX': 7058304L, 'RIP': 4197776L, 'RBP': 7049240L}, 'memory': {140737488346176L: '\x07', 140737488346160L: '\x07', 140737488346159L: '\x00', 4197776L: 'U', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346160L, 'RDX': 7058304L, 'RIP': 4197777L, 'RBP': 7049240L}, 'memory': {4197776L: 'U', 140737488346151L: '\x00', 140737488346152L: '\xf0', 140737488346153L: '\x0c', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_62(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346008L, 'RDX': 140737488346078L, 'RIP': 4283777L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 4283777L: 'U', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'RAX': 1979931136L, 'RSP': 140737488346000L, 'RDX': 140737488346078L, 'RIP': 4283778L, 'RBP': 194L}, 'memory': {4283777L: 'U', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xc2', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_63(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 118L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 3L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320697L: 'A', 4320698L: 'T'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 118L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320699L, 'RBP': 3L}, 'memory': {4320697L: 'A', 4320698L: 'T', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_64(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'R12': 140737488346078L, 'RAX': 1979931136L, 'RSP': 140737488346016L, 'RDX': 140737488346078L, 'RIP': 4283775L, 'RBP': 194L}, 'memory': {140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 140737488346015L: '\x00', 4283776L: 'T', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 4283775L: 'A'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 194L, 'R12': 140737488346078L, 'RAX': 1979931136L, 'RSP': 140737488346008L, 'RDX': 140737488346078L, 'RIP': 4283777L, 'RBP': 194L}, 'memory': {4283776L: 'T', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf', 140737488346017L: '\xdb', 140737488346018L: '\xff', 140737488346019L: '\xff', 140737488346020L: '\xff', 140737488346021L: '\x7f', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x01', 4283775L: 'A'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_65(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346232L, 'RDX': 140737488346512L, 'RIP': 4195596L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4195596L: 'U', 140737488346223L: '\x00', 140737488346224L: '\x90', 140737488346225L: '\r', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346224L, 'RDX': 140737488346512L, 'RIP': 4195597L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4195596L: 'U', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_66(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 9L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320697L: 'A', 4320698L: 'T'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320699L, 'RBP': 9L}, 'memory': {4320697L: 'A', 4320698L: 'T', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_67(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346200L, 'RDX': 140737488346512L, 'RIP': 4297472L, 'RBP': 140737488346472L}, 'memory': {140737488346208L: '\x90', 4297472L: 'A', 4297473L: 'W', 140737488346191L: '\x00', 140737488346192L: '\x04', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xdd', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 514L, 'R15': 0L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346192L, 'RDX': 140737488346512L, 'RIP': 4297474L, 'RBP': 140737488346472L}, 'memory': {4297472L: 'A', 4297473L: 'W', 140737488346183L: '\x00', 140737488346184L: '\x90', 140737488346185L: '\r', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xdd', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_68(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 7065696L, 'RBX': 4194816L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346176L, 'RDX': 12297829382473034411L, 'RIP': 4299831L, 'RBP': 1L}, 'memory': {140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346167L: '\x00', 4299831L: 'S', 140737488346168L: '\x00', 140737488346169L: '\x00', 140737488346170L: '\x00', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 7065696L, 'RBX': 4194816L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346168L, 'RDX': 12297829382473034411L, 'RIP': 4299832L, 'RBP': 1L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 4299831L: 'S', 140737488346168L: '\x00', 140737488346169L: '\x02', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346167L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_69(self):
''' Instruction PUSH RAX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346464L, 'RDX': 140737488346472L, 'RIP': 4195309L, 'RBP': 0L}, 'memory': {140737488346464L: '\x04', 140737488346465L: '\x00', 140737488346466L: '\x00', 140737488346467L: '\x00', 140737488346468L: '\x00', 140737488346469L: '\x00', 140737488346470L: '\x00', 140737488346471L: '\x00', 140737488346472L: '\xb0', 4195309L: 'P', 140737488346455L: '\x00', 140737488346456L: '\x00', 140737488346457L: '\x00', 140737488346458L: '\x00', 140737488346459L: '\x00', 140737488346460L: '\x00', 140737488346461L: '\x00', 140737488346462L: '\x00', 140737488346463L: '\x00'}}, 'text': 'P', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346456L, 'RDX': 140737488346472L, 'RIP': 4195310L, 'RBP': 0L}, 'memory': {140737488346447L: '\x00', 140737488346448L: '\x00', 140737488346449L: '\x00', 140737488346450L: '\x00', 140737488346451L: '\x00', 140737488346452L: '\x00', 140737488346453L: '\x00', 140737488346454L: '\x00', 140737488346455L: '\x00', 140737488346456L: '\x00', 140737488346457L: '\x00', 140737488346458L: '\x00', 140737488346459L: '\x00', 140737488346460L: '\x00', 140737488346461L: '\x00', 140737488346462L: '\x00', 140737488346463L: '\x00', 140737488346464L: '\x04', 140737488346465L: '\x00', 140737488346466L: '\x00', 140737488346467L: '\x00', 140737488346468L: '\x00', 140737488346469L: '\x00', 140737488346470L: '\x00', 140737488346471L: '\x00', 140737488346472L: '\xb0', 4195309L: 'P'}}, 'disassembly': 'PUSH RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_7(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345992L, 'RDX': 7065872L, 'RIP': 4219320L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\x00', 140737488345985L: '\x00', 140737488345986L: '\x00', 140737488345987L: '\x00', 140737488345988L: 'x', 140737488345989L: '8', 140737488345990L: '6', 140737488345991L: '_', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 4219320L: 'U', 140737488345983L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345984L, 'RDX': 7065872L, 'RIP': 4219321L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 4219320L: 'U', 140737488345975L: '\x00', 140737488345976L: '\x00', 140737488345977L: '\x00', 140737488345978L: '\x00', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_70(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'R12': 140737488346512L, 'RAX': 1L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4297478L, 'RBP': 140737488346472L}, 'memory': {140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x00', 4297479L: 'T', 4297478L: 'A', 140737488346167L: '\x00', 140737488346168L: '\x00', 140737488346169L: '\xe0', 140737488346170L: 'k', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'R12': 140737488346512L, 'RAX': 1L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4297480L, 'RBP': 140737488346472L}, 'memory': {4297478L: 'A', 4297479L: 'T', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x00'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_71(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4297480L, 'RBP': 140737488346472L}, 'memory': {140737488346176L: '\x07', 4297480L: 'U', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346160L, 'RDX': 140737488346512L, 'RIP': 4297481L, 'RBP': 140737488346472L}, 'memory': {4297480L: 'U', 140737488346151L: '\x00', 140737488346152L: '\x9c', 140737488346153L: '\n', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90', 140737488346169L: '\xdd', 140737488346170L: '\xff', 140737488346171L: '\xff', 140737488346172L: '\xff', 140737488346173L: '\x7f', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_72(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'R12': 7054840L, 'RAX': 0L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4205736L, 'RBP': 7054832L}, 'memory': {140737488346144L: '\x01', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 4205737L: 'T', 4205736L: 'A', 140737488346135L: '\x00', 140737488346136L: '\x80', 140737488346137L: '\xb3', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'R12': 7054840L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4205738L, 'RBP': 7054832L}, 'memory': {140737488346127L: '\x00', 140737488346128L: '\x00', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xf8', 140737488346137L: '\xa5', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x01', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 4205737L: 'T', 4205736L: 'A'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_73(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320693L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 4320693L: 'A', 4320694L: 'V', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 140737488346079L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345944L, 'RDX': 68L, 'RIP': 4320695L, 'RBP': 9L}, 'memory': {4320693L: 'A', 4320694L: 'V', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_74(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'R12': 24L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 7065872L, 'RIP': 4219318L, 'RBP': 7051232L}, 'memory': {140737488346006L: '\x00', 140737488345991L: '_', 140737488345992L: '6', 140737488345993L: '4', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 4219318L: 'A', 140737488346007L: '\x00', 140737488346008L: '\x00', 4219319L: 'T'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'R12': 24L, 'RAX': 0L, 'RSP': 140737488345992L, 'RDX': 7065872L, 'RIP': 4219320L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\x00', 140737488345985L: '\x00', 140737488345986L: '\x00', 140737488345987L: '\x00', 140737488345988L: 'x', 140737488345989L: '8', 140737488345990L: '6', 140737488345991L: '_', 140737488345992L: '\x18', 140737488345993L: '\x00', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x07', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 4219318L: 'A', 4219319L: 'T', 140737488345983L: '\x00'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_75(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 90L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 9L}, 'memory': {140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 4320697L: 'A', 4320698L: 'T'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R12': 140737488346078L, 'RAX': 90L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320699L, 'RBP': 9L}, 'memory': {4320697L: 'A', 4320698L: 'T', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_76(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 30211L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320706L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 4320706L: 'S', 140737488345911L: '\x00', 140737488345912L: 'Z', 140737488345913L: '\x03', 140737488345914L: 'v', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 30211L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345912L, 'RDX': 68L, 'RIP': 4320707L, 'RBP': 4792416L}, 'memory': {4320706L: 'S', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_77(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1600L, 'RBX': 7074256L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345984L, 'RDX': 2L, 'RIP': 4219324L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 140737488345980L: '\x00', 140737488345975L: '\x00', 140737488345976L: 'q', 140737488345977L: ':', 140737488345978L: 'J', 140737488345979L: '\x00', 4219324L: 'S', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 1600L, 'RBX': 7074256L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345976L, 'RDX': 2L, 'RIP': 4219325L, 'RBP': 7051232L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 140737488345986L: 'k', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '@', 4219324L: 'S', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0', 140737488345977L: '\xf1', 140737488345978L: 'k', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_78(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346008L, 'RDX': 140737488346078L, 'RIP': 4283777L, 'RBP': 188L}, 'memory': {140737488346016L: '\xdf', 4283777L: 'U', 140737488345999L: '\x00', 140737488346000L: '\n', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488346000L, 'RDX': 140737488346078L, 'RIP': 4283778L, 'RBP': 188L}, 'memory': {4283777L: 'U', 140737488345991L: '\x00', 140737488345992L: '@', 140737488345993L: '\x06', 140737488345994L: '\x00', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488346009L: '\xdb', 140737488346010L: '\xff', 140737488346011L: '\xff', 140737488346012L: '\xff', 140737488346013L: '\x7f', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\xdf'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_79(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320702L, 'RBP': 3L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 4320702L: 'U', 140737488345919L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320703L, 'RBP': 3L}, 'memory': {140737488345911L: '\x00', 140737488345912L: 'Z', 140737488345913L: '\x03', 140737488345914L: 'v', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 4320702L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_8(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 30211L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320706L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 4320706L: 'S', 140737488345911L: '\x00', 140737488345912L: 'Z', 140737488345913L: '\x03', 140737488345914L: 'v', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 30211L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345912L, 'RDX': 68L, 'RIP': 4320707L, 'RBP': 4792416L}, 'memory': {4320706L: 'S', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_80(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RBX': 15774463L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 140737488346078L, 'RIP': 4283778L, 'RBP': 188L}, 'memory': {4283778L: 'S', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 15774463L, 'RBX': 15774463L, 'RDI': 188L, 'RAX': 0L, 'RSP': 140737488345992L, 'RDX': 140737488346078L, 'RIP': 4283779L, 'RBP': 188L}, 'memory': {140737488345984L: '\xe0', 140737488345985L: '\x97', 4283778L: 'S', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: '\xff', 140737488345993L: '\xb2', 140737488345994L: '\xf0', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\xbc', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\xde', 140737488345986L: 'k', 140737488345983L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_81(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346040L, 'RDX': 7042720L, 'RIP': 4212692L, 'RBP': 140737488346112L}, 'memory': {140737488346048L: '\x07', 140737488346041L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\x00', 140737488346034L: '\x00', 140737488346035L: '\x00', 4212692L: 'U', 140737488346037L: '\x00', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346036L: '\x00', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346032L, 'RDX': 7042720L, 'RIP': 4212693L, 'RBP': 140737488346112L}, 'memory': {140737488346023L: '\x00', 140737488346024L: '\x00', 140737488346025L: '\x00', 140737488346026L: '\x00', 140737488346027L: '\x00', 140737488346028L: '\x00', 140737488346029L: '\x00', 140737488346030L: '\x00', 140737488346031L: '\x00', 140737488346032L: '\x00', 140737488346033L: '\xdc', 140737488346034L: '\xff', 140737488346035L: '\xff', 140737488346036L: '\xff', 140737488346037L: '\x7f', 140737488346038L: '\x00', 140737488346039L: '\x00', 140737488346040L: '\x00', 140737488346041L: '\x00', 140737488346042L: '\x00', 140737488346043L: '\x00', 140737488346044L: '\x00', 140737488346045L: '\x00', 140737488346046L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x07', 4212692L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_82(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 1979931136L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320706L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 4320706L: 'S', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 1979931136L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 68L, 'RIP': 4320707L, 'RBP': 4792416L}, 'memory': {4320706L: 'S', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: 'Z', 140737488345914L: '\x03', 140737488345915L: 'v', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_83(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'R12': 4197616L, 'RAX': 4467264L, 'RSP': 140737488346208L, 'RDX': 0L, 'RIP': 4196774L, 'RBP': 0L}, 'memory': {140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346207L: '\x00', 4196775L: 'T', 140737488346199L: '\x00', 140737488346200L: '\x00', 140737488346201L: '\x00', 140737488346202L: '\x00', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 4196774L: 'A'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'R12': 4197616L, 'RAX': 4467264L, 'RSP': 140737488346200L, 'RDX': 0L, 'RIP': 4196776L, 'RBP': 0L}, 'memory': {4196774L: 'A', 4196775L: 'T', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xf0', 140737488346201L: '\x0c', 140737488346202L: '@', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_84(self):
''' Instruction PUSH R12 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'R12': 7058304L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4195387L, 'RBP': 140737488346144L}, 'memory': {140737488346144L: '\x18', 140737488346145L: '\x90', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x11', 140737488346140L: '\x00', 140737488346139L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xb4', 140737488346137L: '\r', 140737488346138L: '@', 4195387L: 'A', 4195388L: 'T', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': 'AT', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'R12': 7058304L, 'RAX': 4197776L, 'RSP': 140737488346136L, 'RDX': 7058304L, 'RIP': 4195389L, 'RBP': 140737488346144L}, 'memory': {140737488346127L: '\x00', 140737488346128L: '\x01', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x80', 140737488346137L: '\xb3', 140737488346138L: 'k', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x18', 140737488346145L: '\x90', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x11', 4195387L: 'A', 4195388L: 'T'}}, 'disassembly': 'PUSH R12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_85(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R15': 7035168L, 'RCX': 0L, 'RSI': 13L, 'RDI': 188L, 'RAX': 1L, 'RSP': 140737488346136L, 'RDX': 140737488346512L, 'RIP': 4284416L, 'RBP': 4L}, 'memory': {140737488346144L: '\x00', 4284416L: 'A', 4284417L: 'W', 140737488346127L: '\x00', 140737488346128L: '\x90', 140737488346129L: '\r', 140737488346130L: '@', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xd1', 140737488346137L: 'a', 140737488346138L: 'A', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 582L, 'R15': 7035168L, 'RCX': 0L, 'RSI': 13L, 'RDI': 188L, 'RAX': 1L, 'RSP': 140737488346128L, 'RDX': 140737488346512L, 'RIP': 4284418L, 'RBP': 4L}, 'memory': {4284416L: 'A', 4284417L: 'W', 140737488346119L: '\x00', 140737488346120L: '\xad', 140737488346121L: '\x94', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xd1', 140737488346137L: 'a', 140737488346138L: 'A', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x00'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_86(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320702L, 'RBP': 9L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 4320702L: 'U', 140737488345919L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320703L, 'RBP': 9L}, 'memory': {140737488345911L: '\x00', 140737488345912L: 'v', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\t', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xc2', 4320702L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_87(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 534L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v', 4320689L: 'W', 4320688L: 'A', 140737488345951L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 534L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 9L}, 'memory': {4320688L: 'A', 4320689L: 'W', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'v'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_88(self):
''' Instruction PUSH R14 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4219314L, 'RBP': 7051232L}, 'memory': {140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x04', 4219314L: 'A', 4219315L: 'V', 140737488346007L: '\x00', 140737488346008L: 'n', 140737488346009L: 'H', 140737488346010L: '@', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00'}}, 'text': 'AV', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488346008L, 'RDX': 7065872L, 'RIP': 4219316L, 'RBP': 7051232L}, 'memory': {140737488345999L: '\x00', 140737488346000L: '\x00', 140737488346001L: '\x00', 140737488346002L: '\x00', 140737488346003L: '\x00', 140737488346004L: '\x00', 140737488346005L: '\x00', 140737488346006L: '\x00', 140737488346007L: '\x00', 140737488346008L: '\x00', 140737488346009L: '\x00', 140737488346010L: '\x00', 140737488346011L: '\x00', 140737488346012L: '\x00', 140737488346013L: '\x00', 140737488346014L: '\x00', 140737488346015L: '\x00', 140737488346016L: '\x00', 140737488346017L: '\x00', 140737488346018L: '\x00', 140737488346019L: '\x00', 140737488346020L: '\x00', 140737488346021L: '\x00', 140737488346022L: '\x00', 140737488346023L: '\x00', 140737488346024L: '\x04', 4219314L: 'A', 4219315L: 'V'}}, 'disassembly': 'PUSH R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_89(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'RAX': 0L, 'RSP': 140737488346424L, 'RDX': 140737488346472L, 'RIP': 4195863L, 'RBP': 0L}, 'memory': {140737488346432L: '\x00', 140737488346423L: '\x00', 140737488346415L: '\x00', 140737488346416L: '\x00', 140737488346417L: '\x00', 140737488346418L: '\x00', 140737488346419L: '\x00', 140737488346420L: '\x00', 140737488346421L: '\x00', 140737488346422L: '\x00', 4195863L: 'U', 140737488346424L: '\x00', 140737488346425L: '\x00', 140737488346426L: '\x00', 140737488346427L: '\x00', 140737488346428L: '\x00', 140737488346429L: '\x00', 140737488346430L: '\x00', 140737488346431L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 4195596L, 'RAX': 0L, 'RSP': 140737488346416L, 'RDX': 140737488346472L, 'RIP': 4195864L, 'RBP': 0L}, 'memory': {4195863L: 'U', 140737488346407L: '\x00', 140737488346408L: '\x00', 140737488346409L: '\x00', 140737488346410L: '\x00', 140737488346411L: '\x00', 140737488346412L: '\x00', 140737488346413L: '\x00', 140737488346414L: '\x00', 140737488346415L: '\x00', 140737488346416L: '\x00', 140737488346417L: '\x00', 140737488346418L: '\x00', 140737488346419L: '\x00', 140737488346420L: '\x00', 140737488346421L: '\x00', 140737488346422L: '\x00', 140737488346423L: '\x00', 140737488346424L: '\x00', 140737488346425L: '\x00', 140737488346426L: '\x00', 140737488346427L: '\x00', 140737488346428L: '\x00', 140737488346429L: '\x00', 140737488346430L: '\x00', 140737488346431L: '\x00', 140737488346432L: '\x00'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_9(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 118L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320706L, 'RBP': 4792416L}, 'memory': {140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 4320706L: 'S', 140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: 'v', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RBX': 118L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345912L, 'RDX': 68L, 'RIP': 4320707L, 'RBP': 4792416L}, 'memory': {4320706L: 'S', 140737488345903L: '\x00', 140737488345904L: 'p', 140737488345905L: '\x06', 140737488345906L: '\x00', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: 'v', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_90(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345912L, 'RDX': 699L, 'RIP': 4392988L, 'RBP': 7049504L}, 'memory': {140737488345920L: '\xbb', 140737488345916L: '\xff', 140737488345903L: '\x00', 140737488345904L: '\xf0', 140737488345905L: '\x0c', 140737488345906L: '@', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: '\xd0', 140737488345914L: '\xff', 140737488345915L: '\xf7', 4392988L: 'U', 140737488345917L: '\x7f', 140737488345918L: '\x00', 140737488345919L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345904L, 'RDX': 699L, 'RIP': 4392989L, 'RBP': 7049504L}, 'memory': {4392988L: 'U', 140737488345895L: '\x00', 140737488345896L: '\x90', 140737488345897L: '\r', 140737488345898L: '@', 140737488345899L: '\x00', 140737488345900L: '\x00', 140737488345901L: '\x00', 140737488345902L: '\x00', 140737488345903L: '\x00', 140737488345904L: ' ', 140737488345905L: '\x91', 140737488345906L: 'k', 140737488345907L: '\x00', 140737488345908L: '\x00', 140737488345909L: '\x00', 140737488345910L: '\x00', 140737488345911L: '\x00', 140737488345912L: '\x00', 140737488345913L: '\xd0', 140737488345914L: '\xff', 140737488345915L: '\xf7', 140737488345916L: '\xff', 140737488345917L: '\x7f', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\xbb'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_91(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346152L, 'RDX': 0L, 'RIP': 4779552L, 'RBP': 4L}, 'memory': {140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x1b', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 4779552L: 'U', 140737488346143L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4779553L, 'RBP': 4L}, 'memory': {140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: '\x04', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 4779552L: 'U', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x1b', 140737488346153L: '\x03', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346144L: '\x04'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_92(self):
''' Instruction PUSH RBP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345928L, 'RDX': 68L, 'RIP': 4320702L, 'RBP': 3L}, 'memory': {140737488345920L: '\x00', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 4320702L: 'U', 140737488345919L: '\x00'}}, 'text': 'U', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 68L, 'RIP': 4320703L, 'RBP': 3L}, 'memory': {140737488345911L: '\x00', 140737488345912L: '\x03', 140737488345913L: '\x00', 140737488345914L: '\x00', 140737488345915L: '\x00', 140737488345916L: '\x00', 140737488345917L: '\x00', 140737488345918L: '\x00', 140737488345919L: '\x00', 140737488345920L: '\x03', 140737488345921L: '\x00', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 4320702L: 'U'}}, 'disassembly': 'PUSH RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_93(self):
''' Instruction PUSH RSP '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346456L, 'RDX': 140737488346472L, 'RIP': 4195310L, 'RBP': 0L}, 'memory': {140737488346464L: '\x04', 4195310L: 'T', 140737488346447L: '\x00', 140737488346448L: '\x00', 140737488346449L: '\x00', 140737488346450L: '\x00', 140737488346451L: '\x00', 140737488346452L: '\x00', 140737488346453L: '\x00', 140737488346454L: '\x00', 140737488346455L: '\x00', 140737488346456L: '\x00', 140737488346457L: '\x00', 140737488346458L: '\x00', 140737488346459L: '\x00', 140737488346460L: '\x00', 140737488346461L: '\x00', 140737488346462L: '\x00', 140737488346463L: '\x00'}}, 'text': 'T', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346448L, 'RDX': 140737488346472L, 'RIP': 4195311L, 'RBP': 0L}, 'memory': {140737488346439L: '\x00', 140737488346440L: '\x00', 140737488346441L: '\x00', 140737488346442L: '\x00', 140737488346443L: '\x00', 140737488346444L: '\x00', 140737488346445L: '\x00', 140737488346446L: '\x00', 140737488346447L: '\x00', 140737488346448L: 'X', 140737488346449L: '\xdd', 140737488346450L: '\xff', 140737488346451L: '\xff', 140737488346452L: '\xff', 140737488346453L: '\x7f', 140737488346454L: '\x00', 140737488346455L: '\x00', 140737488346456L: '\x00', 140737488346457L: '\x00', 140737488346458L: '\x00', 140737488346459L: '\x00', 140737488346460L: '\x00', 140737488346461L: '\x00', 140737488346462L: '\x00', 140737488346463L: '\x00', 140737488346464L: '\x04', 4195310L: 'T'}}, 'disassembly': 'PUSH RSP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_94(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 13L, 'RDI': 188L, 'R13': 140737488346512L, 'RAX': 1L, 'RSP': 140737488346120L, 'RDX': 140737488346512L, 'RIP': 4284420L, 'RBP': 4L}, 'memory': {140737488346112L: '\x18', 140737488346113L: '\xcf', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4284420L: 'A', 140737488346111L: '\x00', 4284421L: 'U'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 13L, 'RDI': 188L, 'R13': 140737488346512L, 'RAX': 1L, 'RSP': 140737488346112L, 'RDX': 140737488346512L, 'RIP': 4284422L, 'RBP': 4L}, 'memory': {140737488346112L: '\x90', 140737488346113L: '\xdd', 140737488346114L: '\xff', 140737488346115L: '\xff', 140737488346116L: '\xff', 140737488346117L: '\x7f', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x01', 140737488346121L: '\x00', 140737488346122L: '\x00', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4284420L: 'A', 4284421L: 'U', 140737488346103L: '\x00', 140737488346104L: '\x00', 140737488346105L: '\x00', 140737488346106L: '\x00', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_95(self):
''' Instruction PUSH R15 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 659L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345960L, 'RDX': 68L, 'RIP': 4320688L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 4320689L: 'W', 4320688L: 'A', 140737488345951L: '\x00'}}, 'text': 'AW', 'pos': {'registers': {'RFLAGS': 659L, 'R15': 140737488346078L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 9L}, 'memory': {4320688L: 'A', 4320689L: 'W', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03'}}, 'disassembly': 'PUSH R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_96(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RBX': 0L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345992L, 'RDX': 699L, 'RIP': 4394901L, 'RBP': 7049504L}, 'memory': {140737488345984L: '\x00', 140737488345985L: '\x00', 140737488345986L: '\x00', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: 'c', 140737488345993L: '+', 140737488345994L: '@', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x03', 4394901L: 'S', 140737488345983L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RBX': 0L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345984L, 'RDX': 699L, 'RIP': 4394902L, 'RBP': 7049504L}, 'memory': {140737488345984L: '\x00', 140737488345985L: '\x00', 140737488345986L: '\x00', 140737488345987L: '\x00', 140737488345988L: '\x00', 140737488345989L: '\x00', 140737488345990L: '\x00', 140737488345991L: '\x00', 140737488345992L: 'c', 140737488345993L: '+', 140737488345994L: '@', 140737488345995L: '\x00', 140737488345996L: '\x00', 140737488345997L: '\x00', 140737488345998L: '\x00', 140737488345999L: '\x00', 140737488346000L: '\x03', 4394901L: 'S', 140737488345975L: '\x00', 140737488345976L: ' ', 140737488345977L: '\x91', 140737488345978L: 'k', 140737488345979L: '\x00', 140737488345980L: '\x00', 140737488345981L: '\x00', 140737488345982L: '\x00', 140737488345983L: '\x00'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_97(self):
''' Instruction PUSH RBX '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RBX': 4L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346160L, 'RDX': 140737488346512L, 'RIP': 4297481L, 'RBP': 140737488346472L}, 'memory': {140737488346151L: '\x00', 140737488346152L: '\x9c', 4297481L: 'S', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346153L: '\n', 140737488346168L: '\x90', 140737488346167L: '\x00'}}, 'text': 'S', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RBX': 4L, 'RDI': 895L, 'RAX': 1L, 'RSP': 140737488346152L, 'RDX': 140737488346512L, 'RIP': 4297482L, 'RBP': 140737488346472L}, 'memory': {4297481L: 'S', 140737488346143L: '\x00', 140737488346144L: '0', 140737488346145L: '\xe8', 140737488346146L: 'k', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x04', 140737488346153L: '\x00', 140737488346154L: '\x00', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x90'}}, 'disassembly': 'PUSH RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_98(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'R13': 0L, 'RAX': 4467264L, 'RSP': 140737488346216L, 'RDX': 0L, 'RIP': 4196772L, 'RBP': 0L}, 'memory': {140737488346208L: '\xf0', 140737488346209L: '\x0c', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 4196772L: 'A', 140737488346207L: '\x00', 4196773L: 'U'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 2304L, 'R13': 0L, 'RAX': 4467264L, 'RSP': 140737488346208L, 'RDX': 0L, 'RIP': 4196774L, 'RBP': 0L}, 'memory': {4196772L: 'A', 4196773L: 'U', 140737488346199L: '\x00', 140737488346200L: '\x00', 140737488346201L: '\x00', 140737488346202L: '\x00', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x00', 140737488346209L: '\x00', 140737488346210L: '\x00', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00', 140737488346217L: '\x00', 140737488346218L: '\x00', 140737488346219L: '\x00', 140737488346220L: '\x00', 140737488346221L: '\x00', 140737488346222L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPUSH_99(self):
''' Instruction PUSH R13 '''
test = {'mnemonic': 'PUSH', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 118L, 'RSP': 140737488345944L, 'RDX': 68L, 'RIP': 4320695L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345944L: '\xdf', 140737488345943L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 4320695L: 'A', 4320696L: 'U', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': 'AU', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 188L, 'RAX': 118L, 'RSP': 140737488345936L, 'RDX': 68L, 'RIP': 4320697L, 'RBP': 3L}, 'memory': {4320695L: 'A', 4320696L: 'U', 140737488345927L: '\x00', 140737488345928L: '\xde', 140737488345929L: '\xdb', 140737488345930L: '\xff', 140737488345931L: '\xff', 140737488345932L: '\xff', 140737488345933L: '\x7f', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: '\xbc', 140737488345937L: '\x00', 140737488345938L: '\x00', 140737488345939L: '\x00', 140737488345940L: '\x00', 140737488345941L: '\x00', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xdf', 140737488345945L: '\xdb', 140737488345946L: '\xff', 140737488345947L: '\xff', 140737488345948L: '\xff', 140737488345949L: '\x7f', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\xde'}}, 'disassembly': 'PUSH R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_1(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_10(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 518L, 'XMM0': 338953138925153547590470800371487866880L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7074288L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'XMM0': 0, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7074288L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_11(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_12(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_13(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_14(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 518L, 'XMM0': 0, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 50859318435822L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'XMM0': 0, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 50859318435822L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_15(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 140737488346472L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 140737488346472L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_16(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_17(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 308276084001730439550074880L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_18(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 140737488346472L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 140737488346472L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_19(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_2(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 140737488346472L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 140737488346472L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_20(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_21(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 78918677504442992524819169280L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_22(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783016L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783016L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_23(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 113401473871765646839159859486903977036L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 140737488346472L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 140737488346472L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_24(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_25(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 140737488346472L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 140737488346472L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_26(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_27(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783048L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783048L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483619L, 'RSP': 140737488344248L, 'RDX': 28L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_28(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 71776119061217535, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_29(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 4783036L, 'RSI': 37L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 4783036L, 'RSI': 37L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_3(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 518L, 'XMM0': 78918677504442992524819169280L, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'XMM0': 0, 'RCX': 53L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_30(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_31(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_32(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 18374686479671623680L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_33(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 140737488346472L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 140737488346472L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_34(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_35(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_36(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_37(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_38(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_39(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_4(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_40(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_41(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_42(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783022L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783022L, 'RSI': 37L, 'RDI': 4783008L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_43(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 280375465148160, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_44(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_45(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_46(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_47(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_48(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_49(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 340282346638528864515623922280452587520L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_5(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416319L, 'RBP': 140737488347312L}, 'memory': {4416320L: '\x0f', 4416321L: '\xef', 4416322L: '\xd2', 4416319L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 140737488347312L, 'RSI': 47L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416323L, 'RBP': 140737488347312L}, 'memory': {4416320L: '\x0f', 4416321L: '\xef', 4416322L: '\xd2', 4416319L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_50(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM1': 86738642548474510294585684247313465665L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 514L, 'XMM1': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_51(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4782903L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_52(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 4782888L, 'RSI': 37L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 4782888L, 'RSI': 37L, 'RDI': 4782880L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_53(self):
''' Instruction PXOR XMM1, XMM1 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM1': 90882157140230411661358273883331839052L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 140737488346472L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'text': 'f\x0f\xef\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'XMM1': 0, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 140737488346472L}, 'memory': {4239659L: 'f', 4239660L: '\x0f', 4239661L: '\xef', 4239662L: '\xc9'}}, 'disassembly': 'PXOR XMM1, XMM1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_54(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4783042L, 'RSI': 37L, 'RDI': 4783040L, 'RAX': 2147483625L, 'RSP': 140737488344248L, 'RDX': 22L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_55(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_56(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4782997L, 'RSI': 37L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4782997L, 'RSI': 37L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_57(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 140737488346472L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 4793984L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 140737488346472L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_58(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_59(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 518L, 'XMM0': 71776119061217280, 'RCX': 53L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'XMM0': 0, 'RCX': 53L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_6(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 518L, 'XMM0': 1095216660480, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239592L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'XMM0': 0, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239596L, 'RBP': 140737488346472L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_60(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_61(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_62(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239592L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239596L, 'RBP': 4782912L}, 'memory': {4239592L: 'f', 4239593L: '\x0f', 4239594L: '\xef', 4239595L: '\xc0'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_63(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_64(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 140737488346472L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 140737488346472L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_65(self):
''' Instruction PXOR XMM3, XMM3 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM3': 1324035698926381045275276563951124480L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'text': 'f\x0f\xef\xdb', 'pos': {'registers': {'XMM3': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239671L, 'RBP': 4782912L}, 'memory': {4239667L: 'f', 4239668L: '\x0f', 4239669L: '\xef', 4239670L: '\xdb'}}, 'disassembly': 'PXOR XMM3, XMM3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_66(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 4782912L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_67(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_68(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 518L, 'RCX': 4782899L, 'RSI': 37L, 'RDI': 4782896L, 'RAX': 2147483638L, 'RSP': 140737488344248L, 'RDX': 9L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_69(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239663L, 'RBP': 140737488346472L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 582L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239667L, 'RBP': 140737488346472L}, 'memory': {4239664L: '\x0f', 4239665L: '\xef', 4239666L: '\xd2', 4239663L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_7(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 1095216660480, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 140737488346472L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 4793968L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 140737488346472L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_70(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'XMM0': 0, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 4782912L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_8(self):
''' Instruction PXOR XMM2, XMM2 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 4782991L, 'RSI': 37L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247983L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'text': 'f\x0f\xef\xd2', 'pos': {'registers': {'XMM2': 0, 'RFLAGS': 514L, 'RCX': 4782991L, 'RSI': 37L, 'RDI': 4782976L, 'RAX': 140737488345984L, 'RSP': 140737488344248L, 'RDX': 140737488345952L, 'RIP': 4247987L, 'RBP': 140737488345936L}, 'memory': {4247984L: '\x0f', 4247985L: '\xef', 4247986L: '\xd2', 4247983L: 'f'}}, 'disassembly': 'PXOR XMM2, XMM2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testPXOR_9(self):
''' Instruction PXOR XMM0, XMM0 '''
test = {'mnemonic': 'PXOR', 'pre': {'registers': {'RFLAGS': 582L, 'XMM0': 1095216660480, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239655L, 'RBP': 140737488346472L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'text': 'f\x0f\xef\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'XMM0': 0, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239659L, 'RBP': 140737488346472L}, 'memory': {4239656L: '\x0f', 4239657L: '\xef', 4239658L: '\xc0', 4239655L: 'f'}}, 'disassembly': 'PXOR XMM0, XMM0', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_1(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x01', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_10(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: "'", 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_100(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x04', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_101(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 140737354125312L, 'RIP': 4394985L, 'RBP': 0L}, 'memory': {140737488346048L: ' ', 140737488346049L: '\x91', 140737488346050L: 'k', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 4394985L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 140737354125312L, 'RIP': 4203862L, 'RBP': 0L}, 'memory': {140737488346047L: '\x00', 140737488346048L: ' ', 140737488346049L: '\x91', 140737488346050L: 'k', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'V', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 140737488346065L: '\x91', 140737488346066L: 'k', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\x01', 4394985L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_11(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4294934528L, 'RDI': 4783008L, 'RAX': 4782995L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4248078L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 4248078L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xcf', 140737488344249L: '\x10', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4294934528L, 'RDI': 4783008L, 'RAX': 4782995L, 'RSP': 140737488344256L, 'RDX': 3L, 'RIP': 4329679L, 'RBP': 140737488345936L}, 'memory': {4248078L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xcf', 140737488344249L: '\x10', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '8'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_12(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4199231L, 'RBP': 140737488346224L}, 'memory': {140737488346176L: '\x07', 140737488346175L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xe2', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 4199231L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346176L, 'RDX': 79L, 'RIP': 4195810L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xe2', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4199231L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_13(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'RAX': 140737354125487L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4244414L, 'RBP': 7049504L}, 'memory': {140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 4244414L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'RAX': 140737354125487L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392887L, 'RBP': 7049504L}, 'memory': {4244414L: '\xc3', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x07', 140737488346058L: 'C', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: ' '}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_14(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327753L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 4327753L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337479L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xba', 4327753L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_15(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7049636L, 'RIP': 4203215L, 'RBP': 0L}, 'memory': {140737488346048L: '\x00', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x84', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 4203215L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7049636L, 'RIP': 4203908L, 'RBP': 0L}, 'memory': {140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\x84', 140737488346057L: '%', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: ' ', 140737488346065L: '\x91', 140737488346066L: 'k', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '\x01', 4203215L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_16(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 57632L, 'RSI': 4294967288L, 'RDI': 4782912L, 'RAX': 4782901L, 'RSP': 140737488344248L, 'RDX': 5L, 'RIP': 4248078L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 4248078L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 57632L, 'RSI': 4294967288L, 'RDI': 4782912L, 'RAX': 4782901L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4336226L, 'RBP': 140737488345936L}, 'memory': {4248078L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_17(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 11L, 'RSP': 140737488346056L, 'RDX': 11L, 'RIP': 4239746L, 'RBP': 140737488346472L}, 'memory': {140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 4239746L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 11L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322394L, 'RBP': 140737488346472L}, 'memory': {4239746L: '\xc3', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: 'q'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_18(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x11', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_19(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x02', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x02', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_2(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239746L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198960L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_20(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 6L, 'RIP': 4322448L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x06', 140737488346121L: '\x94', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 6L, 'RIP': 4297734L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x06', 140737488346121L: '\x94', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_21(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4241440L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4241416L, 'RBP': 4L}, 'memory': {140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 4241416L: '\xc3', 140737488346175L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4241440L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197584L, 'RBP': 4L}, 'memory': {4241416L: '\xc3', 140737488346175L: '\x00', 140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_22(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4776545L, 'RBP': 140737488346144L}, 'memory': {140737488346144L: '\x04', 4776545L: '\xc3', 140737488346127L: '\x00', 140737488346128L: '\x90', 140737488346129L: '\r', 140737488346130L: '@', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: '\x04', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4195553L, 'RBP': 140737488346144L}, 'memory': {140737488346127L: '\x00', 140737488346128L: '\x90', 140737488346129L: '\r', 140737488346130L: '@', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xe1', 140737488346137L: '\x04', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: '\x04', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x16', 4776545L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_23(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: "'", 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_24(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_25(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345928L, 'RDX': 18446744073709551615L, 'RIP': 4393094L, 'RBP': 7049504L}, 'memory': {140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa', 140737488345929L: '\x04', 140737488345930L: 'C', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 4393094L: '\xc3', 140737488345919L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'RDI': 1L, 'RAX': 699L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392186L, 'RBP': 7049504L}, 'memory': {4393094L: '\xc3', 140737488345919L: '\x00', 140737488345920L: '\xbb', 140737488345921L: '\x02', 140737488345922L: '\x00', 140737488345923L: '\x00', 140737488345924L: '\x00', 140737488345925L: '\x00', 140737488345926L: '\x00', 140737488345927L: '\x00', 140737488345928L: '\xfa', 140737488345929L: '\x04', 140737488345930L: 'C', 140737488345931L: '\x00', 140737488345932L: '\x00', 140737488345933L: '\x00', 140737488345934L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 140737488345943L: '\x00', 140737488345944L: '\xbb'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_26(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294967040L, 'RDI': 4783056L, 'RAX': 4783050L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4248078L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 4248078L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1024L, 'RSI': 4294967040L, 'RDI': 4783056L, 'RAX': 4783050L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4336226L, 'RBP': 140737488345936L}, 'memory': {4248078L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'b', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x02'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_27(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239746L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198960L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_28(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x11', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_29(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4417659L, 'RBP': 5L}, 'memory': {140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 4417659L: '\xc3', 140737488346175L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4426528L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197584L, 'RBP': 5L}, 'memory': {140737488346175L: '\x00', 140737488346176L: 'n', 140737488346177L: '#', 140737488346178L: 'C', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4417659L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_3(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '"', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '"', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_30(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'RAX': 6L, 'RSP': 140737488346200L, 'RDX': 4L, 'RIP': 4298263L, 'RBP': 140737488346472L}, 'memory': {140737488346208L: '\x90', 140737488346199L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 4298263L: '\xc3', 140737488346200L: '\xdd', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1685382481L, 'RSI': 7L, 'RDI': 0L, 'RAX': 6L, 'RSP': 140737488346208L, 'RDX': 4L, 'RIP': 4299741L, 'RBP': 140737488346472L}, 'memory': {4298263L: '\xc3', 140737488346191L: '\x00', 140737488346192L: '\x00', 140737488346193L: '\x00', 140737488346194L: '\x00', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\xdd', 140737488346201L: '\x9b', 140737488346202L: 'A', 140737488346203L: '\x00', 140737488346204L: '\x00', 140737488346205L: '\x00', 140737488346206L: '\x00', 140737488346207L: '\x00', 140737488346208L: '\x90', 140737488346209L: '\r', 140737488346210L: '@', 140737488346211L: '\x00', 140737488346212L: '\x00', 140737488346213L: '\x00', 140737488346214L: '\x00', 140737488346215L: '\x00', 140737488346216L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_31(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239746L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198960L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_32(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_33(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7L, 'RIP': 4322448L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'N', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7L, 'RIP': 4297550L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'N', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_34(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_35(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 5L, 'RIP': 4231472L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344239L: '\x00', 4231472L: '\xf3', 4231473L: '\xc3', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 5L, 'RIP': 4329913L, 'RBP': 140737488345936L}, 'memory': {4231472L: '\xf3', 140737488344241L: '\xff', 140737488344239L: '\x00', 140737488344240L: '\xd0', 4231473L: '\xc3', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xa1'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_36(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x01', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_37(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: "'", 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: "'", 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_38(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4294967295L, 'RSP': 140737488343880L, 'RDX': 18446744073709551568L, 'RIP': 4673861L, 'RBP': 18446744073709551568L}, 'memory': {140737488343872L: '\x00', 140737488343873L: '\x00', 140737488343874L: '\x00', 140737488343875L: '\x00', 140737488343876L: '\x00', 140737488343877L: '\x00', 140737488343878L: '\x00', 140737488343879L: '\x00', 140737488343880L: '\x8c', 140737488343881L: 'P', 140737488343882L: 'G', 140737488343883L: '\x00', 140737488343884L: '\x00', 140737488343885L: '\x00', 140737488343886L: '\x00', 140737488343887L: '\x00', 140737488343888L: '\x00', 140737488343871L: '\x00', 4673861L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'RAX': 4294967295L, 'RSP': 140737488343888L, 'RDX': 18446744073709551568L, 'RIP': 4673676L, 'RBP': 18446744073709551568L}, 'memory': {4673861L: '\xc3', 140737488343871L: '\x00', 140737488343872L: '\x00', 140737488343873L: '\x00', 140737488343874L: '\x00', 140737488343875L: '\x00', 140737488343876L: '\x00', 140737488343877L: '\x00', 140737488343878L: '\x00', 140737488343879L: '\x00', 140737488343880L: '\x8c', 140737488343881L: 'P', 140737488343882L: 'G', 140737488343883L: '\x00', 140737488343884L: '\x00', 140737488343885L: '\x00', 140737488343886L: '\x00', 140737488343887L: '\x00', 140737488343888L: '\x00', 140737488343889L: '\x00', 140737488343890L: '\x00', 140737488343891L: '\x00', 140737488343892L: '\x00', 140737488343893L: '\x00', 140737488343894L: '\x00', 140737488343895L: '\x00', 140737488343896L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_39(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4505474L, 'RBP': 4544L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x9e', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4505474L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 64L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4286622L, 'RBP': 4544L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x9e', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4505474L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_4(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x01', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x01', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_40(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_41(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239746L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198960L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_42(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 7054976L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4782869L, 'RBP': 7049240L}, 'memory': {140737488346176L: '\x07', 140737488346175L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 4782869L: '\xc3', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346165L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 7054976L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4198097L, 'RBP': 7049240L}, 'memory': {4782869L: '\xc3', 140737488346159L: '\x00', 140737488346160L: '\x18', 140737488346161L: '\x90', 140737488346162L: 'k', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd1', 140737488346169L: '\x0e', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_43(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347364L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4416462L, 'RBP': 140737488347312L}, 'memory': {140737488346176L: '\x07', 4416462L: '\xc3', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'K', 140737488346169L: '{', 140737488346170L: 'A', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347364L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4291403L, 'RBP': 140737488347312L}, 'memory': {140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'K', 140737488346169L: '{', 140737488346170L: 'A', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x04', 4416462L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_44(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 11L, 'RIP': 4322448L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xbe', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297662L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xbe', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_45(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 0L, 'RSP': 140737488345768L, 'RDX': 7213056L, 'RIP': 4505474L, 'RBP': 3648L}, 'memory': {140737488345760L: '\x00', 140737488345761L: '\x00', 140737488345762L: '\x00', 140737488345763L: '\x00', 140737488345764L: '\x00', 140737488345765L: '\x00', 140737488345766L: '\x00', 140737488345767L: '\x00', 140737488345768L: 'h', 140737488345769L: 'h', 140737488345770L: 'A', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '\xc0', 4505474L: '\xc3', 140737488345759L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7213056L, 'RAX': 0L, 'RSP': 140737488345776L, 'RDX': 7213056L, 'RIP': 4286568L, 'RBP': 3648L}, 'memory': {4505474L: '\xc3', 140737488345759L: '\x00', 140737488345760L: '\x00', 140737488345761L: '\x00', 140737488345762L: '\x00', 140737488345763L: '\x00', 140737488345764L: '\x00', 140737488345765L: '\x00', 140737488345766L: '\x00', 140737488345767L: '\x00', 140737488345768L: 'h', 140737488345769L: 'h', 140737488345770L: 'A', 140737488345771L: '\x00', 140737488345772L: '\x00', 140737488345773L: '\x00', 140737488345774L: '\x00', 140737488345775L: '\x00', 140737488345776L: '\xc0', 140737488345777L: '\x01', 140737488345778L: 'n', 140737488345779L: '\x00', 140737488345780L: '\x00', 140737488345781L: '\x00', 140737488345782L: '\x00', 140737488345783L: '\x00', 140737488345784L: '\xe0'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_46(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4819040L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 18446744073709551600L, 'RSP': 140737488346232L, 'RDX': 4820576L, 'RIP': 4301014L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346230L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\xf0', 140737488346225L: '\x0c', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 4301014L: '\xc3', 140737488346231L: '\x00', 140737488346232L: ',', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4819040L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 18446744073709551600L, 'RSP': 140737488346240L, 'RDX': 4820576L, 'RIP': 4196140L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4301014L: '\xc3', 140737488346223L: '\x00', 140737488346224L: '\xf0', 140737488346225L: '\x0c', 140737488346226L: '@', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: ',', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_47(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344184L, 'RDX': 32L, 'RIP': 4203630L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 4203630L: '\xc3', 140737488344175L: '\x00', 140737488344176L: '(', 140737488344177L: '\xfb', 140737488344178L: 'H', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: '\xa2', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344192L, 'RDX': 32L, 'RIP': 4392610L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 140737488344193L: '\x00', 140737488344194L: '\x00', 140737488344195L: '\x00', 140737488344196L: '\x00', 140737488344197L: '\x00', 140737488344198L: '\x00', 140737488344199L: '\x00', 140737488344200L: ' ', 4203630L: '\xc3', 140737488344175L: '\x00', 140737488344176L: '(', 140737488344177L: '\xfb', 140737488344178L: 'H', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: '\xa2', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_48(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '"', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '"', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_49(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 6L, 'RIP': 4320802L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 4320802L: '\xc3', 140737488345951L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283914L, 'RBP': 3L}, 'memory': {4320802L: '\xc3', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x03', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_5(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7074240L, 'RIP': 4505474L, 'RBP': 4544L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'h', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4505474L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7074240L, 'RIP': 4286568L, 'RBP': 4544L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: 'h', 140737488346121L: 'h', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4505474L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_50(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 4783020L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344251L: '\x00', 4392783L: '\xc3', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\x87', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344239L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 4783020L, 'RIP': 4329863L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\x87', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x04', 4392783L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_51(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4199231L, 'RBP': 140737488346224L}, 'memory': {140737488346176L: '\x07', 140737488346175L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'Z', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 4199231L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346176L, 'RDX': 79L, 'RIP': 4195674L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'Z', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4199231L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_52(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 6L, 'RIP': 4320802L, 'RBP': 3L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00', 4320802L: '\xc3', 140737488345951L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283914L, 'RBP': 3L}, 'memory': {4320802L: '\xc3', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: '\x00', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_53(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345960L, 'RDX': 96L, 'RIP': 4320802L, 'RBP': 9L}, 'memory': {140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 4320802L: '\xc3', 140737488345951L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283914L, 'RBP': 9L}, 'memory': {4320802L: '\xc3', 140737488345951L: '\x00', 140737488345952L: '\xde', 140737488345953L: '\xdb', 140737488345954L: '\xff', 140737488345955L: '\xff', 140737488345956L: '\xff', 140737488345957L: '\x7f', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '\n', 140737488345961L: '^', 140737488345962L: 'A', 140737488345963L: '\x00', 140737488345964L: '\x00', 140737488345965L: '\x00', 140737488345966L: '\x00', 140737488345967L: '\x00', 140737488345968L: 'Z', 140737488345969L: '\x00', 140737488345970L: '\x00', 140737488345971L: '\x00', 140737488345972L: '\x00', 140737488345973L: '\x00', 140737488345974L: '\x00', 140737488345975L: '\x00', 140737488345976L: '\xd0'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_54(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 2L, 'RSP': 140737488344248L, 'RDX': 4783050L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344251L: '\x00', 4392783L: '\xc3', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344239L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'RAX': 2L, 'RSP': 140737488344256L, 'RDX': 4783050L, 'RIP': 4336291L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca', 4392783L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_55(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4467264L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4197601L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4197601L: '\xc3', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xd5', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4467264L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196053L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 4197601L: '\xc3', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xd5', 140737488346233L: '\x06', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_56(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074272L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346072L, 'RDX': 7051232L, 'RIP': 4230286L, 'RBP': 140737488346112L}, 'memory': {140737488346080L: 'h', 4230286L: '\xc3', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '}', 140737488346073L: '\xf8', 140737488346074L: 'D', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074272L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 7051232L, 'RIP': 4520061L, 'RBP': 140737488346112L}, 'memory': {4230286L: '\xc3', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: '}', 140737488346073L: '\xf8', 140737488346074L: 'D', 140737488346075L: '\x00', 140737488346076L: '\x00', 140737488346077L: '\x00', 140737488346078L: '\x00', 140737488346079L: '\x00', 140737488346080L: 'h', 140737488346081L: '\xdd', 140737488346082L: '\xff', 140737488346083L: '\xff', 140737488346084L: '\xff', 140737488346085L: '\x7f', 140737488346086L: '\x00', 140737488346087L: '\x00', 140737488346088L: 'q'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_57(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 4L, 'RIP': 4322448L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xe2', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 4L, 'RIP': 4297698L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xe2', 140737488346121L: '\x93', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_58(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 30L, 'RIP': 4231472L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344239L: '\x00', 4231472L: '\xf3', 4231473L: '\xc3', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 30L, 'RIP': 4329925L, 'RBP': 140737488345936L}, 'memory': {4231472L: '\xf3', 140737488344241L: '\xff', 140737488344239L: '\x00', 140737488344240L: '\xd0', 4231473L: '\xc3', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xc5', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xca'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_59(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_6(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4284848L, 'RBP': 4L}, 'memory': {140737488346176L: '\x07', 140737488346160L: 'h', 140737488346159L: '\x00', 4284848L: '\xc3', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'l', 140737488346169L: '\r', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197740L, 'RBP': 4L}, 'memory': {4284848L: '\xc3', 140737488346159L: '\x00', 140737488346160L: 'h', 140737488346161L: '\xdd', 140737488346162L: '\xff', 140737488346163L: '\xff', 140737488346164L: '\xff', 140737488346165L: '\x7f', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'l', 140737488346169L: '\r', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_60(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 12L, 'RSP': 140737488344248L, 'RDX': 4783034L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344251L: '\x00', 4392783L: '\xc3', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344239L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 12L, 'RSP': 140737488344256L, 'RDX': 4783034L, 'RIP': 4336291L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xba', 4392783L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_61(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344184L, 'RDX': 0L, 'RIP': 4394908L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 140737488344188L: '\x00', 140737488344175L: '\x00', 140737488344176L: '\t', 140737488344177L: '\x00', 140737488344178L: '\x00', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: ']', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 4394908L: '\xc3', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392541L, 'RBP': 7049504L}, 'memory': {140737488344192L: '\x00', 140737488344193L: '\x00', 140737488344194L: '\x00', 140737488344195L: '\x00', 140737488344196L: '\x00', 140737488344197L: '\x00', 140737488344198L: '\x00', 140737488344199L: '\x00', 140737488344200L: ' ', 4394908L: '\xc3', 140737488344175L: '\x00', 140737488344176L: '\t', 140737488344177L: '\x00', 140737488344178L: '\x00', 140737488344179L: '\x00', 140737488344180L: '\x00', 140737488344181L: '\x00', 140737488344182L: '\x00', 140737488344183L: '\x00', 140737488344184L: ']', 140737488344185L: '\x06', 140737488344186L: 'C', 140737488344187L: '\x00', 140737488344188L: '\x00', 140737488344189L: '\x00', 140737488344190L: '\x00', 140737488344191L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_62(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x08', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x08', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_63(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x11', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_64(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '3', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_65(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x08', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x08', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_66(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '+', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '+', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_67(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 140737354125330L, 'RDI': 140737354125329L, 'RAX': 1L, 'RSP': 140737488344248L, 'RDX': 4782904L, 'RIP': 4392783L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344251L: '\x00', 4392783L: '\xc3', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344239L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 10L, 'RSI': 140737354125330L, 'RDI': 140737354125329L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 4782904L, 'RIP': 4336291L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xa3', 140737488344249L: '*', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '8', 4392783L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_68(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 17L, 'RSP': 140737488345944L, 'RDX': 7059408L, 'RIP': 4330071L, 'RBP': 140737488346224L}, 'memory': {140737488345952L: '\x10', 140737488345943L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 4330071L: '\xc3', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 17L, 'RSP': 140737488345952L, 'RDX': 7059408L, 'RIP': 4198910L, 'RBP': 140737488346224L}, 'memory': {140737488345943L: '\x00', 140737488345935L: '\x00', 140737488345936L: 'p', 140737488345937L: '\xdc', 140737488345938L: '\xff', 140737488345939L: '\xff', 140737488345940L: '\xff', 140737488345941L: '\x7f', 140737488345942L: '\x00', 4330071L: '\xc3', 140737488345944L: '\xfe', 140737488345945L: '\x11', 140737488345946L: '@', 140737488345947L: '\x00', 140737488345948L: '\x00', 140737488345949L: '\x00', 140737488345950L: '\x00', 140737488345951L: '\x00', 140737488345952L: '\x10', 140737488345953L: '\x00', 140737488345954L: '\x00', 140737488345955L: '\x00', 140737488345956L: '0', 140737488345957L: '\x00', 140737488345958L: '\x00', 140737488345959L: '\x00', 140737488345960L: '@'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_69(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4197763L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4197763L: '\xc3', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196201L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 4197763L: '\xc3', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 140737488346248L: '\x00', 140737488346243L: '\x00', 140737488346223L: '\x00', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: 'i', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_7(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '3', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_70(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_71(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '$', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '$', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_72(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4199231L, 'RBP': 140737488346224L}, 'memory': {140737488346176L: '\x07', 140737488346175L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xee', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 4199231L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346176L, 'RDX': 79L, 'RIP': 4195822L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xee', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4199231L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_73(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4199231L, 'RBP': 140737488346224L}, 'memory': {140737488346176L: '\x07', 140737488346175L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd6', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 4199231L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346176L, 'RDX': 79L, 'RIP': 4195798L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\xd6', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4199231L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_74(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 5L, 'RIP': 4322448L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x18', 140737488346113L: '\xcf', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xad', 140737488346121L: '\x94', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 5L, 'RIP': 4297901L, 'RBP': 140737488346472L}, 'memory': {140737488346112L: '\x18', 140737488346113L: '\xcf', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xad', 140737488346121L: '\x94', 140737488346122L: 'A', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: '\x08', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: 'P', 4322448L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_75(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346136L, 'RDX': 7058304L, 'RIP': 4704486L, 'RBP': 7035176L}, 'memory': {140737488346144L: 'p', 4704486L: '\xc3', 140737488346127L: '\x00', 140737488346128L: '\x01', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xb4', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4197812L, 'RBP': 7035176L}, 'memory': {140737488346127L: '\x00', 140737488346128L: '\x01', 140737488346129L: '\x00', 140737488346130L: '\x00', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\xb4', 140737488346137L: '\r', 140737488346138L: '@', 140737488346139L: '\x00', 140737488346140L: '\x00', 140737488346141L: '\x00', 140737488346142L: '\x00', 140737488346143L: '\x00', 140737488346144L: 'p', 140737488346145L: '\xdc', 140737488346146L: '\xff', 140737488346147L: '\xff', 140737488346148L: '\xff', 140737488346149L: '\x7f', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: '\x00', 4704486L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_76(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: 'D', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: 'D', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_77(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4392783L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4392783L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4199109L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4392783L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_78(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x04', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_79(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065872L, 'RIP': 4212951L, 'RBP': 140737488346112L}, 'memory': {140737488346048L: '\x07', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x8e', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: 'q', 4212951L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7065872L, 'RIP': 4230839L, 'RBP': 140737488346112L}, 'memory': {140737488346071L: '\x00', 140737488346047L: '\x00', 140737488346048L: '\x07', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '\x00', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: '\xb7', 140737488346057L: '\x8e', 140737488346058L: '@', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: 'q', 140737488346065L: ':', 140737488346066L: 'J', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 4212951L: '\xc3', 140737488346072L: '8'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_8(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344136L, 'RDX': 140737354129408L, 'RIP': 4661300L, 'RBP': 4294967295L}, 'memory': {140737488344128L: '(', 140737488344129L: '\xfb', 140737488344130L: 'H', 140737488344131L: '\x00', 140737488344132L: '\x00', 140737488344133L: '\x00', 140737488344134L: '\x00', 140737488344135L: '\x00', 140737488344136L: 'L', 140737488344137L: '#', 140737488344138L: '@', 140737488344139L: '\x00', 140737488344140L: '\x00', 140737488344141L: '\x00', 140737488344142L: '\x00', 140737488344143L: '\x00', 140737488344144L: ' ', 4661300L: '\xc3', 140737488344127L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344144L, 'RDX': 140737354129408L, 'RIP': 4203340L, 'RBP': 4294967295L}, 'memory': {4661300L: '\xc3', 140737488344127L: '\x00', 140737488344128L: '(', 140737488344129L: '\xfb', 140737488344130L: 'H', 140737488344131L: '\x00', 140737488344132L: '\x00', 140737488344133L: '\x00', 140737488344134L: '\x00', 140737488344135L: '\x00', 140737488344136L: 'L', 140737488344137L: '#', 140737488344138L: '@', 140737488344139L: '\x00', 140737488344140L: '\x00', 140737488344141L: '\x00', 140737488344142L: '\x00', 140737488344143L: '\x00', 140737488344144L: ' ', 140737488344145L: '\x91', 140737488344146L: 'k', 140737488344147L: '\x00', 140737488344148L: '\x00', 140737488344149L: '\x00', 140737488344150L: '\x00', 140737488344151L: '\x00', 140737488344152L: 'x'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_80(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327753L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 4327753L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 140737488345638L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337479L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\xc0', 4327753L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_81(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343960L, 'RDX': 140737354129408L, 'RIP': 4203233L, 'RBP': 4096L}, 'memory': {140737488343968L: '\x05', 4203233L: '\xc3', 140737488343951L: '\x00', 140737488343952L: '\x00', 140737488343953L: '\x10', 140737488343954L: '\x00', 140737488343955L: '\x00', 140737488343956L: '\x00', 140737488343957L: '\x00', 140737488343958L: '\x00', 140737488343959L: '\x00', 140737488343960L: '\x10', 140737488343961L: ' ', 140737488343962L: 'G', 140737488343963L: '\x00', 140737488343964L: '\x00', 140737488343965L: '\x00', 140737488343966L: '\x00', 140737488343967L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488343968L, 'RDX': 140737354129408L, 'RIP': 4661264L, 'RBP': 4096L}, 'memory': {140737488343951L: '\x00', 140737488343952L: '\x00', 140737488343953L: '\x10', 140737488343954L: '\x00', 140737488343955L: '\x00', 140737488343956L: '\x00', 140737488343957L: '\x00', 140737488343958L: '\x00', 140737488343959L: '\x00', 140737488343960L: '\x10', 140737488343961L: ' ', 140737488343962L: 'G', 140737488343963L: '\x00', 140737488343964L: '\x00', 140737488343965L: '\x00', 140737488343966L: '\x00', 140737488343967L: '\x00', 140737488343968L: '\x05', 140737488343969L: '\x00', 140737488343970L: '\x00', 140737488343971L: '\x00', 140737488343972L: '\x00', 140737488343973L: '\x00', 140737488343974L: '\x00', 140737488343975L: '\x00', 140737488343976L: '\x05', 4203233L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_82(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4195848L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 4195848L: '\xc3', 140737488346223L: '\x89', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196284L, 'RBP': 0L}, 'memory': {140737488346240L: '\x00', 140737488346241L: '\x00', 140737488346242L: '\x00', 140737488346243L: '\x00', 140737488346244L: '\x00', 140737488346245L: '\x00', 140737488346246L: '\x00', 140737488346247L: '\x00', 4195848L: '\xc3', 140737488346248L: '\x00', 140737488346223L: '\x89', 140737488346224L: '\x00', 140737488346225L: '\x00', 140737488346226L: '\x00', 140737488346227L: '\x00', 140737488346228L: '\x00', 140737488346229L: '\x00', 140737488346230L: '\x00', 140737488346231L: '\x00', 140737488346232L: '\xbc', 140737488346233L: '\x07', 140737488346234L: '@', 140737488346235L: '\x00', 140737488346236L: '\x00', 140737488346237L: '\x00', 140737488346238L: '\x00', 140737488346239L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_83(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x04', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x04', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_84(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 15L, 'RSP': 140737488346056L, 'RDX': 4L, 'RIP': 4239772L, 'RBP': 140737488346472L}, 'memory': {140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 4239772L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 15L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322394L, 'RBP': 140737488346472L}, 'memory': {4239772L: '\xc3', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\xdc', 140737488346050L: '\xff', 140737488346051L: '\xff', 140737488346052L: '\xff', 140737488346053L: '\x7f', 140737488346054L: '\x00', 140737488346055L: '\x00', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\n', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: 'q'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_85(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 14L, 'RIP': 4239746L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 14L, 'RIP': 4198960L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '0', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4239746L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_86(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '+', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '+', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_87(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231472L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344239L: '\x00', 4231472L: '\xf3', 4231473L: '\xc3', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 17L, 'RIP': 4329913L, 'RBP': 140737488345936L}, 'memory': {4231472L: '\xf3', 140737488344241L: '\xff', 140737488344239L: '\x00', 140737488344240L: '\xd0', 4231473L: '\xc3', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: '\xb9', 140737488344249L: '\x11', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '8'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_88(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7074240L, 'RSP': 140737488345800L, 'RDX': 7209408L, 'RIP': 4286602L, 'RBP': 7051232L}, 'memory': {140737488345792L: '8', 140737488345793L: '\x98', 140737488345794L: 'k', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\xc9', 140737488345801L: '\xb0', 140737488345802L: '@', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 4286602L: '\xc3', 140737488345791L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 7074240L, 'RSP': 140737488345808L, 'RDX': 7209408L, 'RIP': 4239561L, 'RBP': 7051232L}, 'memory': {4286602L: '\xc3', 140737488345791L: '\x00', 140737488345792L: '8', 140737488345793L: '\x98', 140737488345794L: 'k', 140737488345795L: '\x00', 140737488345796L: '\x00', 140737488345797L: '\x00', 140737488345798L: '\x00', 140737488345799L: '\x00', 140737488345800L: '\xc9', 140737488345801L: '\xb0', 140737488345802L: '@', 140737488345803L: '\x00', 140737488345804L: '\x00', 140737488345805L: '\x00', 140737488345806L: '\x00', 140737488345807L: '\x00', 140737488345808L: '\x00', 140737488345809L: '\x00', 140737488345810L: '\x00', 140737488345811L: '\x00', 140737488345812L: '\x00', 140737488345813L: '\x00', 140737488345814L: '\x00', 140737488345815L: '\x00', 140737488345816L: '('}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_89(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 7L, 'RSP': 140737488346056L, 'RDX': 7L, 'RIP': 4239746L, 'RBP': 140737488346472L}, 'memory': {140737488346048L: '\x00', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '(', 140737488346054L: 'n', 140737488346055L: 'o', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\x00', 4239746L: '\xc3', 140737488346047L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 7L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322394L, 'RBP': 140737488346472L}, 'memory': {4239746L: '\xc3', 140737488346047L: '\x00', 140737488346048L: '\x00', 140737488346049L: '\x00', 140737488346050L: '\x00', 140737488346051L: '\x00', 140737488346052L: '\x00', 140737488346053L: '(', 140737488346054L: 'n', 140737488346055L: 'o', 140737488346056L: 'Z', 140737488346057L: '\xf4', 140737488346058L: 'A', 140737488346059L: '\x00', 140737488346060L: '\x00', 140737488346061L: '\x00', 140737488346062L: '\x00', 140737488346063L: '\x00', 140737488346064L: '\x00', 140737488346065L: '\x00', 140737488346066L: '\x00', 140737488346067L: '\x00', 140737488346068L: '\x00', 140737488346069L: '\x00', 140737488346070L: '\x00', 140737488346071L: '\x00', 140737488346072L: 'q'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_9(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '3', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '3', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_90(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327753L, 'RBP': 140737488345936L}, 'memory': {140737488344256L: '\x00', 4327753L: '\xc3', 140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 140737488345639L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337479L, 'RBP': 140737488345936L}, 'memory': {140737488344239L: '\x00', 140737488344240L: '\xd0', 140737488344241L: '\xff', 140737488344242L: '\xff', 140737488344243L: '\xff', 140737488344244L: '\xff', 140737488344245L: '\xff', 140737488344246L: '\xff', 140737488344247L: '\xff', 140737488344248L: 'G', 140737488344249L: '/', 140737488344250L: 'B', 140737488344251L: '\x00', 140737488344252L: '\x00', 140737488344253L: '\x00', 140737488344254L: '\x00', 140737488344255L: '\x00', 140737488344256L: '\x00', 140737488344257L: '\x00', 140737488344258L: '\x00', 140737488344259L: '\x00', 140737488344260L: '\x00', 140737488344261L: '\x00', 140737488344262L: '\x00', 140737488344263L: '\x00', 140737488344264L: '\x04', 4327753L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_91(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343960L, 'RDX': 140737488343968L, 'RIP': 4285756L, 'RBP': 8192L}, 'memory': {140737488343968L: '\x05', 140737488343965L: '\x00', 140737488343964L: '\x00', 140737488343951L: '\x00', 140737488343952L: '\x00', 140737488343953L: '\x00', 140737488343954L: '\x00', 140737488343955L: '\x00', 140737488343956L: '\x00', 140737488343957L: '\x00', 140737488343958L: '\x00', 140737488343959L: '\x00', 140737488343960L: '\x9b', 140737488343961L: '\x1f', 140737488343962L: 'G', 140737488343963L: '\x00', 4285756L: '\xf3', 4285757L: '\xc3', 140737488343966L: '\x00', 140737488343967L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343968L, 'RDX': 140737488343968L, 'RIP': 4661147L, 'RBP': 8192L}, 'memory': {140737488343951L: '\x00', 140737488343952L: '\x00', 140737488343953L: '\x00', 140737488343954L: '\x00', 140737488343955L: '\x00', 140737488343956L: '\x00', 140737488343957L: '\x00', 140737488343958L: '\x00', 140737488343959L: '\x00', 140737488343960L: '\x9b', 140737488343961L: '\x1f', 140737488343962L: 'G', 140737488343963L: '\x00', 140737488343964L: '\x00', 140737488343965L: '\x00', 140737488343966L: '\x00', 140737488343967L: '\x00', 140737488343968L: '\x05', 140737488343969L: '\x00', 140737488343970L: '\x00', 140737488343971L: '\x00', 140737488343972L: '\x00', 140737488343973L: '\x00', 140737488343974L: '\x00', 140737488343975L: '\x00', 140737488343976L: '\x05', 4285756L: '\xf3', 4285757L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_92(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'RAX': 78L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4392783L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 4392783L: '\xc3', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'RAX': 78L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4199109L, 'RBP': 4782912L}, 'memory': {140737488346112L: '\x00', 140737488346113L: '\x00', 140737488346114L: '\x00', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\xc5', 140737488346121L: '\x12', 140737488346122L: '@', 140737488346123L: '\x00', 140737488346124L: '\x00', 140737488346125L: '\x00', 140737488346126L: '\x00', 140737488346127L: '\x00', 140737488346128L: ' ', 140737488346129L: 'Y', 140737488346130L: 'k', 140737488346131L: '\x00', 140737488346132L: '\x00', 140737488346133L: '\x00', 140737488346134L: '\x00', 140737488346135L: '\x00', 140737488346136L: '\x90', 4392783L: '\xc3', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_93(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4199231L, 'RBP': 140737488346224L}, 'memory': {140737488346176L: '\x07', 140737488346175L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'f', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 4199231L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 79L, 'RSP': 140737488346176L, 'RDX': 79L, 'RIP': 4195686L, 'RBP': 140737488346224L}, 'memory': {140737488346159L: '\x00', 140737488346160L: '\x07', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: 'f', 140737488346169L: '\x05', 140737488346170L: '@', 140737488346171L: '\x00', 140737488346172L: '\x00', 140737488346173L: '\x00', 140737488346174L: '\x00', 140737488346175L: '\x00', 140737488346176L: '\x07', 140737488346177L: '\x00', 140737488346178L: '\x00', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\x90', 4199231L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_94(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '%', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '%', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_95(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 7069696L, 'RSP': 140737488346152L, 'RDX': 7074240L, 'RIP': 4286602L, 'RBP': 80L}, 'memory': {140737488346144L: '@', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: 'L', 140737488346153L: '\n', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 4286602L: '\xc3', 140737488346143L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 64L, 'RDI': 7074240L, 'RAX': 7069696L, 'RSP': 140737488346160L, 'RDX': 7074240L, 'RIP': 4196940L, 'RBP': 80L}, 'memory': {4286602L: '\xc3', 140737488346143L: '\x00', 140737488346144L: '@', 140737488346145L: '\x00', 140737488346146L: '\x00', 140737488346147L: '\x00', 140737488346148L: '\x00', 140737488346149L: '\x00', 140737488346150L: '\x00', 140737488346151L: '\x00', 140737488346152L: 'L', 140737488346153L: '\n', 140737488346154L: '@', 140737488346155L: '\x00', 140737488346156L: '\x00', 140737488346157L: '\x00', 140737488346158L: '\x00', 140737488346159L: '\x00', 140737488346160L: '\x00', 140737488346161L: '\x00', 140737488346162L: '\x00', 140737488346163L: '\x00', 140737488346164L: '\x00', 140737488346165L: '\x00', 140737488346166L: '\x00', 140737488346167L: '\x00', 140737488346168L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_96(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346184L, 'RDX': 0L, 'RIP': 4439397L, 'RBP': 8L}, 'memory': {140737488346176L: '\x90', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346175L: '\x00', 4439397L: '\xc3'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4439408L, 'RSP': 140737488346192L, 'RDX': 0L, 'RIP': 4197584L, 'RBP': 8L}, 'memory': {140737488346175L: '\x00', 140737488346176L: '\x90', 140737488346177L: '\x02', 140737488346178L: '@', 140737488346179L: '\x00', 140737488346180L: '\x00', 140737488346181L: '\x00', 140737488346182L: '\x00', 140737488346183L: '\x00', 140737488346184L: '\xd0', 140737488346185L: '\x0c', 140737488346186L: '@', 140737488346187L: '\x00', 140737488346188L: '\x00', 140737488346189L: '\x00', 140737488346190L: '\x00', 140737488346191L: '\x00', 140737488346192L: '\x90', 140737488346193L: '\r', 140737488346194L: '@', 140737488346195L: '\x00', 140737488346196L: '\x00', 140737488346197L: '\x00', 140737488346198L: '\x00', 140737488346199L: '\x00', 140737488346200L: '\x00', 4439397L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_97(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7049504L, 'RSP': 140737488346104L, 'RDX': 7049636L, 'RIP': 4394350L, 'RBP': 1L}, 'memory': {140737488346112L: '@', 4394350L: '\xc3', 140737488346095L: '\x00', 140737488346096L: ' ', 140737488346097L: '\x91', 140737488346098L: 'k', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'm', 140737488346105L: '-', 140737488346106L: '@', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'text': '\xc3', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 140737354125312L, 'RAX': 7049504L, 'RSP': 140737488346112L, 'RDX': 7049636L, 'RIP': 4205933L, 'RBP': 1L}, 'memory': {140737488346112L: '@', 140737488346113L: 'Y', 140737488346114L: 'k', 140737488346115L: '\x00', 140737488346116L: '\x00', 140737488346117L: '\x00', 140737488346118L: '\x00', 140737488346119L: '\x00', 140737488346120L: '\x00', 4394350L: '\xc3', 140737488346095L: '\x00', 140737488346096L: ' ', 140737488346097L: '\x91', 140737488346098L: 'k', 140737488346099L: '\x00', 140737488346100L: '\x00', 140737488346101L: '\x00', 140737488346102L: '\x00', 140737488346103L: '\x00', 140737488346104L: 'm', 140737488346105L: '-', 140737488346106L: '@', 140737488346107L: '\x00', 140737488346108L: '\x00', 140737488346109L: '\x00', 140737488346110L: '\x00', 140737488346111L: '\x00'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_98(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x02', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x02', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testRET_99(self):
''' Instruction RET '''
test = {'mnemonic': 'RET', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283342L, 'RBP': 4792416L}, 'memory': {140737488345888L: '\x11', 140737488345883L: '\x00', 4283342L: '\xf3', 4283343L: '\xc3', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345871L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00'}}, 'text': '\xf3\xc3', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320778L, 'RBP': 4792416L}, 'memory': {140737488345871L: '\x00', 140737488345872L: '\x00', 140737488345873L: '1', 140737488345874L: '\x00', 140737488345875L: '\x00', 140737488345876L: '\x00', 140737488345877L: '\x00', 140737488345878L: '\x00', 140737488345879L: '\x00', 140737488345880L: '\n', 140737488345881L: '\xee', 140737488345882L: 'A', 140737488345883L: '\x00', 140737488345884L: '\x00', 140737488345885L: '\x00', 140737488345886L: '\x00', 140737488345887L: '\x00', 140737488345888L: '\x11', 140737488345889L: '\x00', 140737488345890L: '\x00', 140737488345891L: '\x00', 140737488345892L: '\x00', 140737488345893L: '\x00', 140737488345894L: '\x00', 140737488345895L: '\x00', 140737488345896L: '\xc0', 4283342L: '\xf3', 4283343L: '\xc3'}}, 'disassembly': 'RET', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testROL_1(self):
''' Instruction ROL RDX, 0x11 '''
test = {'mnemonic': 'ROL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 140737488346240L, 'RIP': 4319893L, 'RBP': 0L}, 'memory': {4319896L: '\x11', 4319893L: 'H', 4319894L: '\xc1', 4319895L: '\xc2'}}, 'text': 'H\xc1\xc2\x11', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 18446744072518369280L, 'RIP': 4319897L, 'RBP': 0L}, 'memory': {4319896L: '\x11', 4319893L: 'H', 4319894L: '\xc1', 4319895L: '\xc2'}}, 'disassembly': 'ROL RDX, 0x11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testROL_2(self):
''' Instruction ROL RBX, 0x11 '''
test = {'mnemonic': 'ROL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 1L, 'RBX': 4197776L, 'RDI': 0L, 'RAX': 7058320L, 'RSP': 140737488346208L, 'RDX': 4294967295L, 'RIP': 4198615L, 'RBP': 0L}, 'memory': {4198616L: '\xc1', 4198617L: '\xc3', 4198618L: '\x11', 4198615L: 'H'}}, 'text': 'H\xc1\xc3\x11', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 1L, 'RBX': 550210895872L, 'RDI': 0L, 'RAX': 7058320L, 'RSP': 140737488346208L, 'RDX': 4294967295L, 'RIP': 4198619L, 'RBP': 0L}, 'memory': {4198616L: '\xc1', 4198617L: '\xc3', 4198618L: '\x11', 4198615L: 'H'}}, 'disassembly': 'ROL RBX, 0x11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testROL_3(self):
''' Instruction ROL RAX, 0x11 '''
test = {'mnemonic': 'ROL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 4196211L, 'RSP': 140737488346232L, 'RDX': 18446744072518369280L, 'RIP': 4319914L, 'RBP': 0L}, 'memory': {4319914L: 'H', 4319915L: '\xc1', 4319916L: '\xc0', 4319917L: '\x11'}}, 'text': 'H\xc1\xc0\x11', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 550005768192L, 'RSP': 140737488346232L, 'RDX': 18446744072518369280L, 'RIP': 4319918L, 'RBP': 0L}, 'memory': {4319914L: 'H', 4319915L: '\xc1', 4319916L: '\xc0', 4319917L: '\x11'}}, 'disassembly': 'ROL RAX, 0x11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testROL_4(self):
''' Instruction ROL RAX, 0x11 '''
test = {'mnemonic': 'ROL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4319855L, 'RBP': 0L}, 'memory': {4319856L: '\xc1', 4319857L: '\xc0', 4319858L: '\x11', 4319855L: 'H'}}, 'text': 'H\xc1\xc0\x11', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4319859L, 'RBP': 0L}, 'memory': {4319856L: '\xc1', 4319857L: '\xc0', 4319858L: '\x11', 4319855L: 'H'}}, 'disassembly': 'ROL RAX, 0x11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testROR_1(self):
''' Instruction ROR RAX, 0x11 '''
test = {'mnemonic': 'ROR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 0L, 'RAX': 550210895872L, 'RSP': 140737488346176L, 'RDX': 7058304L, 'RIP': 4198082L, 'RBP': 7049240L}, 'memory': {4198082L: 'H', 4198083L: '\xc1', 4198084L: '\xc8', 4198085L: '\x11'}}, 'text': 'H\xc1\xc8\x11', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346176L, 'RDX': 7058304L, 'RIP': 4198086L, 'RBP': 7049240L}, 'memory': {4198082L: 'H', 4198083L: '\xc1', 4198084L: '\xc8', 4198085L: '\x11'}}, 'disassembly': 'ROR RAX, 0x11', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_1(self):
''' Instruction SAR RAX, 0x1 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285104L, 'RBP': 32768L}, 'memory': {4285104L: 'H', 4285105L: '\xd1', 4285106L: '\xf8'}}, 'text': 'H\xd1\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285107L, 'RBP': 32768L}, 'memory': {4285104L: 'H', 4285105L: '\xd1', 4285106L: '\xf8'}}, 'disassembly': 'SAR RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_10(self):
''' Instruction SAR RAX, 0x1 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 32768L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285071L, 'RBP': 32768L}, 'memory': {4285072L: '\xd1', 4285073L: '\xf8', 4285071L: 'H'}}, 'text': 'H\xd1\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 16384L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285074L, 'RBP': 32768L}, 'memory': {4285072L: '\xd1', 4285073L: '\xf8', 4285071L: 'H'}}, 'disassembly': 'SAR RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_11(self):
''' Instruction SAR R14, 0x3 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 288L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346208L, 'RDX': 12297829382473034411L, 'RIP': 4197521L, 'RBP': 0L}, 'memory': {4197521L: 'I', 4197522L: '\xc1', 4197523L: '\xfe', 4197524L: '\x03'}}, 'text': 'I\xc1\xfe\x03', 'pos': {'registers': {'RFLAGS': 518L, 'R14': 36L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346208L, 'RDX': 12297829382473034411L, 'RIP': 4197525L, 'RBP': 0L}, 'memory': {4197521L: 'I', 4197522L: '\xc1', 4197523L: '\xfe', 4197524L: '\x03'}}, 'disassembly': 'SAR R14, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_12(self):
''' Instruction SAR ECX, 0x1f '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 9L, 'RSI': 1979931136L, 'ECX': 9L, 'RDI': 194L, 'RAX': 9L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283814L, 'RBP': 194L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'text': '\xc1\xf9\x1f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1979931136L, 'ECX': 0L, 'RDI': 194L, 'RAX': 9L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 194L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'disassembly': 'SAR ECX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_13(self):
''' Instruction SAR RBX, 0x3 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 8L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4197799L, 'RBP': 7035176L}, 'memory': {4197800L: '\xc1', 4197801L: '\xfb', 4197802L: '\x03', 4197799L: 'H'}}, 'text': 'H\xc1\xfb\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 1L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4197803L, 'RBP': 7035176L}, 'memory': {4197800L: '\xc1', 4197801L: '\xfb', 4197802L: '\x03', 4197799L: 'H'}}, 'disassembly': 'SAR RBX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_14(self):
''' Instruction SAR R14, 0x3 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 514L, 'R14': 8L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 18446744073709551615L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197715L, 'RBP': 4L}, 'memory': {4197715L: 'I', 4197716L: '\xc1', 4197717L: '\xfe', 4197718L: '\x03'}}, 'text': 'I\xc1\xfe\x03', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 1L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 18446744073709551615L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197719L, 'RBP': 4L}, 'memory': {4197715L: 'I', 4197716L: '\xc1', 4197717L: '\xfe', 4197718L: '\x03'}}, 'disassembly': 'SAR R14, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_2(self):
''' Instruction SAR RAX, 0x1 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 1048576L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285124L, 'RBP': 32768L}, 'memory': {4285124L: 'H', 4285125L: '\xd1', 4285126L: '\xf8'}}, 'text': 'H\xd1\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 524288L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285127L, 'RBP': 32768L}, 'memory': {4285124L: 'H', 4285125L: '\xd1', 4285126L: '\xf8'}}, 'disassembly': 'SAR RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_3(self):
''' Instruction SAR RBX, 0x3 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 8L, 'RDI': 7064352L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4195438L, 'RBP': 140737488346144L}, 'memory': {4195440L: '\xfb', 4195441L: '\x03', 4195438L: 'H', 4195439L: '\xc1'}}, 'text': 'H\xc1\xfb\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 1L, 'RDI': 7064352L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4195442L, 'RBP': 140737488346144L}, 'memory': {4195440L: '\xfb', 4195441L: '\x03', 4195438L: 'H', 4195439L: '\xc1'}}, 'disassembly': 'SAR RBX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_4(self):
''' Instruction SAR RAX, 0x1 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 32768L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285051L, 'RBP': 32768L}, 'memory': {4285051L: 'H', 4285052L: '\xd1', 4285053L: '\xf8'}}, 'text': 'H\xd1\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 16384L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285054L, 'RBP': 32768L}, 'memory': {4285051L: 'H', 4285052L: '\xd1', 4285053L: '\xf8'}}, 'disassembly': 'SAR RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_5(self):
''' Instruction SAR RDX, 0x3f '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 4194304L, 'RIP': 4285153L, 'RBP': 32768L}, 'memory': {4285153L: 'H', 4285154L: '\xc1', 4285155L: '\xfa', 4285156L: '?'}}, 'text': 'H\xc1\xfa?', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 4194304L, 'RDI': 2L, 'RAX': 4194304L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285157L, 'RBP': 32768L}, 'memory': {4285153L: 'H', 4285154L: '\xc1', 4285155L: '\xfa', 4285156L: '?'}}, 'disassembly': 'SAR RDX, 0x3f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_6(self):
''' Instruction SAR R14, 0x3 '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197655L, 'RBP': 4L}, 'memory': {4197656L: '\xc1', 4197657L: '\xfe', 4197658L: '\x03', 4197655L: 'I'}}, 'text': 'I\xc1\xfe\x03', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197659L, 'RBP': 4L}, 'memory': {4197656L: '\xc1', 4197657L: '\xfe', 4197658L: '\x03', 4197655L: 'I'}}, 'disassembly': 'SAR R14, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_7(self):
''' Instruction SAR ECX, 0x1f '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 3L, 'RSI': 1979931136L, 'ECX': 3L, 'RDI': 188L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283814L, 'RBP': 188L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'text': '\xc1\xf9\x1f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1979931136L, 'ECX': 0L, 'RDI': 188L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 188L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'disassembly': 'SAR ECX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_8(self):
''' Instruction SAR ECX, 0x1f '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 3L, 'RSI': 15774463L, 'ECX': 3L, 'RDI': 188L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283814L, 'RBP': 188L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'text': '\xc1\xf9\x1f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 15774463L, 'ECX': 0L, 'RDI': 188L, 'RAX': 3L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 188L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'disassembly': 'SAR ECX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSAR_9(self):
''' Instruction SAR ECX, 0x1f '''
test = {'mnemonic': 'SAR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 9L, 'RSI': 15774463L, 'ECX': 9L, 'RDI': 194L, 'RAX': 9L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283814L, 'RBP': 194L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'text': '\xc1\xf9\x1f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 15774463L, 'ECX': 0L, 'RDI': 194L, 'RAX': 9L, 'RSP': 140737488345968L, 'RDX': 1431655766L, 'RIP': 4283817L, 'RBP': 194L}, 'memory': {4283816L: '\x1f', 4283814L: '\xc1', 4283815L: '\xf9'}}, 'disassembly': 'SAR ECX, 0x1f', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_1(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_10(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_11(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_12(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_13(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_14(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_15(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_16(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_17(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_18(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_19(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_2(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 530L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_20(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 643L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_21(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_22(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_23(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_24(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_25(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_26(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_27(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_28(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_29(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_3(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_30(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 96L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_31(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_32(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_33(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_34(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_35(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_36(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_37(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_38(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_39(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 2695L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_4(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_40(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_41(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_42(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_43(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_44(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_45(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 9L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_46(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_47(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_48(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 60L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_49(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_5(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 643L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_50(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_51(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_52(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 530L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_53(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_54(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_6(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_7(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 647L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_8(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSBB_9(self):
''' Instruction SBB EAX, EAX '''
test = {'mnemonic': 'SBB', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 659L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283337L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'text': '\x19\xc0', 'pos': {'registers': {'EAX': 4294967295L, 'RFLAGS': 663L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283339L, 'RBP': 4792416L}, 'memory': {4283337L: '\x19', 4283338L: '\xc0'}}, 'disassembly': 'SBB EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSCAS_1(self):
''' Instruction REPNZ SCASB '''
test = {'mnemonic': 'SCAS', 'pre': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551612L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782908L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\xf2\xae', 'pos': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551611L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782909L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'REPNZ SCASB', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x1, test['pos']['registers'][reg_name]&0x1, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name)&1, test['pos']['registers'][reg_name]&1))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSCAS_2(self):
''' Instruction REPNZ SCASB '''
test = {'mnemonic': 'SCAS', 'pre': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551613L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782907L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\xf2\xae', 'pos': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551612L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782908L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'REPNZ SCASB', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSCAS_3(self):
''' Instruction REPNZ SCASB '''
test = {'mnemonic': 'SCAS', 'pre': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551614L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782906L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\xf2\xae', 'pos': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551613L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782907L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'REPNZ SCASB', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x1, test['pos']['registers'][reg_name]&0x1, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSCAS_4(self):
''' Instruction REPNZ SCASB '''
test = {'mnemonic': 'SCAS', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782905L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\xf2\xae', 'pos': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551614L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782906L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782905: 'A', 4782906: 'S', 4782907: 'A', 4782908: 'S', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'REPNZ SCASB', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSCAS_5(self):
''' Instruction REPNZ SCASB '''
test = {'mnemonic': 'SCAS', 'pre': {'registers': {'RFLAGS': 66118L, 'RCX': 18446744073709551611L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782909L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346534L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'text': '\xf2\xae', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551610L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782910L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4346536L, 'RDX': 24L}, 'memory': {4782912: 'A', 4782913: 'A', 4782914: 'A', 4782915: 'A', 4782916: 'A', 4346534L: '\xf2', 4346535L: '\xae', 4782909: '\x00', 4782910: '\x00', 4782911: '\x00'}}, 'disassembly': 'REPNZ SCASB', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_1(self):
''' Instruction SETNZ DL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 0L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297688L, 'RBP': 140737488346472L}, 'memory': {4297688L: '\x0f', 4297689L: '\x95', 4297690L: '\xc2'}}, 'text': '\x0f\x95\xc2', 'pos': {'registers': {'RFLAGS': 582L, 'DL': 0L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297691L, 'RBP': 140737488346472L}, 'memory': {4297688L: '\x0f', 4297689L: '\x95', 4297690L: '\xc2'}}, 'disassembly': 'SETNZ DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_10(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336697L, 'RDX': 4294967295L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336700L, 'RDX': 4294967295L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_11(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336697L, 'RDX': 4294967294L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336700L, 'RDX': 4294967294L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_12(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'CL': 224L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336708L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'CL': 1L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336711L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_13(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336697L, 'RDX': 4294967294L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336700L, 'RDX': 4294967294L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_14(self):
''' Instruction SETNZ DL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 0L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 7065440L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297576L, 'RBP': 140737488346472L}, 'memory': {4297576L: '\x0f', 4297577L: '\x95', 4297578L: '\xc2'}}, 'text': '\x0f\x95\xc2', 'pos': {'registers': {'RFLAGS': 582L, 'DL': 0L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 7065440L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297579L, 'RBP': 140737488346472L}, 'memory': {4297576L: '\x0f', 4297577L: '\x95', 4297578L: '\xc2'}}, 'disassembly': 'SETNZ DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_15(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336697L, 'RDX': 4294967295L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336700L, 'RDX': 4294967295L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_16(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'CL': 0L, 'RDI': 7051232L, 'RAX': 137168L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4222898L, 'RBP': 7051232L}, 'memory': {4222898L: '\x0f', 4222899L: '\x95', 4222900L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'CL': 0L, 'RDI': 7051232L, 'RAX': 137168L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4222901L, 'RBP': 7051232L}, 'memory': {4222898L: '\x0f', 4222899L: '\x95', 4222900L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_17(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'CL': 224L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336708L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'CL': 1L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336711L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_18(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'CL': 224L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336708L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'CL': 1L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4336711L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_2(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336697L, 'RDX': 4294967295L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336700L, 'RDX': 4294967295L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_3(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'CL': 224L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336708L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'CL': 1L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336711L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_4(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'CL': 224L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336708L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'CL': 1L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336711L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_5(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4194304L, 'RAX': 4L, 'RDI': 2L, 'RBP': 32768L, 'RSP': 140737488346144L, 'AL': 4L, 'RIP': 4285497L, 'RDX': 1L}, 'memory': {4285497L: '\x0f', 4285498L: '\x95', 4285499L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 4194304L, 'RAX': 1L, 'RDI': 2L, 'RBP': 32768L, 'RSP': 140737488346144L, 'AL': 1L, 'RIP': 4285500L, 'RDX': 1L}, 'memory': {4285497L: '\x0f', 4285498L: '\x95', 4285499L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_6(self):
''' Instruction SETNZ CL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'CL': 224L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336708L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'text': '\x0f\x95\xc1', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'CL': 1L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4336711L, 'RBP': 140737488345936L}, 'memory': {4336708L: '\x0f', 4336709L: '\x95', 4336710L: '\xc1'}}, 'disassembly': 'SETNZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_7(self):
''' Instruction SETNZ BL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 32L, 'BL': 0L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222794L, 'RBP': 7051232L}, 'memory': {4222794L: '\x0f', 4222795L: '\x95', 4222796L: '\xc3'}}, 'text': '\x0f\x95\xc3', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 32L, 'BL': 0L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222797L, 'RBP': 7051232L}, 'memory': {4222794L: '\x0f', 4222795L: '\x95', 4222796L: '\xc3'}}, 'disassembly': 'SETNZ BL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_8(self):
''' Instruction SETNZ BYTE [RSP+0x30] '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 7051320L, 'RIP': 4222459L, 'RBP': 7051232L}, 'memory': {140737488345872: 'r', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 4222459L: '\x0f', 4222460L: '\x95', 4222461L: 'D', 4222462L: '$', 4222463L: '0'}}, 'text': '\x0f\x95D$0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 7051320L, 'RIP': 4222464L, 'RBP': 7051232L}, 'memory': {140737488345872: '\x00', 140737488345873: '1', 140737488345874: '\x00', 140737488345875: '\x00', 140737488345876: '\x00', 140737488345877: '\x00', 140737488345878: '\x00', 140737488345879: '\x00', 4222459L: '\x0f', 4222460L: '\x95', 4222461L: 'D', 4222462L: '$', 4222463L: '0'}}, 'disassembly': 'SETNZ BYTE [RSP+0x30]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETNZ_9(self):
''' Instruction SETNZ AL '''
test = {'mnemonic': 'SETNZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336697L, 'RDX': 4294967294L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'text': '\x0f\x95\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RAX': 0L, 'RDI': 0L, 'RBP': 140737488345936L, 'RSP': 140737488344256L, 'AL': 0L, 'RIP': 4336700L, 'RDX': 4294967294L}, 'memory': {4336697L: '\x0f', 4336698L: '\x95', 4336699L: '\xc0'}}, 'disassembly': 'SETNZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_1(self):
''' Instruction SETZ CL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 3L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337471L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'text': '\x0f\x94\xc1', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 3L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'disassembly': 'SETZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_10(self):
''' Instruction SETZ AL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RAX': 699L, 'RDI': 0L, 'RBP': 7049504L, 'RSP': 140737488345984L, 'AL': 187L, 'RIP': 4394920L, 'RDX': 18446744073709551615L}, 'memory': {4394920L: '\x0f', 4394921L: '\x94', 4394922L: '\xc0'}}, 'text': '\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RAX': 513L, 'RDI': 0L, 'RBP': 7049504L, 'RSP': 140737488345984L, 'AL': 1L, 'RIP': 4394923L, 'RDX': 18446744073709551615L}, 'memory': {4394920L: '\x0f', 4394921L: '\x94', 4394922L: '\xc0'}}, 'disassembly': 'SETZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_11(self):
''' Instruction SETZ CL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337471L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'text': '\x0f\x94\xc1', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'disassembly': 'SETZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_12(self):
''' Instruction SETZ R8B '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RAX': 1L, 'RDI': 4L, 'R8B': 192L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284095L, 'RBP': 3L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'text': 'A\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RAX': 1L, 'RDI': 4L, 'R8B': 1L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284099L, 'RBP': 3L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'disassembly': 'SETZ R8B', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_13(self):
''' Instruction SETZ R8B '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 511L, 'RSI': 29360191L, 'RAX': 2L, 'RDI': 4L, 'R8B': 1L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284095L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'text': 'A\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 511L, 'RSI': 29360191L, 'RAX': 2L, 'RDI': 4L, 'R8B': 0L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284099L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'disassembly': 'SETZ R8B', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_14(self):
''' Instruction SETZ R8B '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4095L, 'RSI': 62914623L, 'RAX': 3L, 'RDI': 4L, 'R8B': 0L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284095L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'text': 'A\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4095L, 'RSI': 62914623L, 'RAX': 3L, 'RDI': 4L, 'R8B': 0L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284099L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'disassembly': 'SETZ R8B', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_15(self):
''' Instruction SETZ CL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 21L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337471L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'text': '\x0f\x94\xc1', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 21L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'disassembly': 'SETZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_16(self):
''' Instruction SETZ R8B '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RAX': 1L, 'RDI': 4L, 'R8B': 192L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284095L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'text': 'A\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RAX': 1L, 'RDI': 4L, 'R8B': 1L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284099L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'disassembly': 'SETZ R8B', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_2(self):
''' Instruction SETZ CL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337471L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'text': '\x0f\x94\xc1', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'disassembly': 'SETZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_3(self):
''' Instruction SETZ DL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 0L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 7065420L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297724L, 'RBP': 140737488346472L}, 'memory': {4297724L: '\x0f', 4297725L: '\x94', 4297726L: '\xc2'}}, 'text': '\x0f\x94\xc2', 'pos': {'registers': {'RFLAGS': 582L, 'DL': 1L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 7065420L, 'RSP': 140737488346128L, 'RDX': 1L, 'RIP': 4297727L, 'RBP': 140737488346472L}, 'memory': {4297724L: '\x0f', 4297725L: '\x94', 4297726L: '\xc2'}}, 'disassembly': 'SETZ DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_4(self):
''' Instruction SETZ CL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 43L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337471L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'text': '\x0f\x94\xc1', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 43L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'disassembly': 'SETZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_5(self):
''' Instruction SETZ BYTE [RSP+0x48] '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223586L, 'RBP': 7051232L}, 'memory': {4223586L: '\x0f', 4223587L: '\x94', 4223588L: 'D', 4223589L: '$', 4223590L: 'H', 140737488345896: '\x00', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00'}}, 'text': '\x0f\x94D$H', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223591L, 'RBP': 7051232L}, 'memory': {4223586L: '\x0f', 4223587L: '\x94', 4223588L: 'D', 4223589L: '$', 4223590L: 'H', 140737488345896: '\x01', 140737488345897: '\x00', 140737488345898: '\x00', 140737488345899: '\x00', 140737488345900: '\x00', 140737488345901: '\x00', 140737488345902: '\x00', 140737488345903: '\x00'}}, 'disassembly': 'SETZ BYTE [RSP+0x48]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_6(self):
''' Instruction SETZ CL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337471L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'text': '\x0f\x94\xc1', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 140737488345640L, 'CL': 0L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344256L, 'RDX': 10L, 'RIP': 4337474L, 'RBP': 140737488345936L}, 'memory': {4337472L: '\x94', 4337473L: '\xc1', 4337471L: '\x0f'}}, 'disassembly': 'SETZ CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_7(self):
''' Instruction SETZ DL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 0L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 7065376L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297652L, 'RBP': 140737488346472L}, 'memory': {4297652L: '\x0f', 4297653L: '\x94', 4297654L: '\xc2'}}, 'text': '\x0f\x94\xc2', 'pos': {'registers': {'RFLAGS': 582L, 'DL': 1L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 7065376L, 'RSP': 140737488346128L, 'RDX': 1L, 'RIP': 4297655L, 'RBP': 140737488346472L}, 'memory': {4297652L: '\x0f', 4297653L: '\x94', 4297654L: '\xc2'}}, 'disassembly': 'SETZ DL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_8(self):
''' Instruction SETZ AL '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RAX': 4294967295L, 'RDI': 1L, 'RBP': 18446744073709551568L, 'RSP': 140737488343888L, 'AL': 255L, 'RIP': 4673678L, 'RDX': 18446744073709551568L}, 'memory': {4673680L: '\xc0', 4673678L: '\x0f', 4673679L: '\x94'}}, 'text': '\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RAX': 4294967040L, 'RDI': 1L, 'RBP': 18446744073709551568L, 'RSP': 140737488343888L, 'AL': 0L, 'RIP': 4673681L, 'RDX': 18446744073709551568L}, 'memory': {4673680L: '\xc0', 4673678L: '\x0f', 4673679L: '\x94'}}, 'disassembly': 'SETZ AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSETZ_9(self):
''' Instruction SETZ R8B '''
test = {'mnemonic': 'SETZ', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RAX': 1L, 'RDI': 4L, 'R8B': 1L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284095L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'text': 'A\x0f\x94\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RAX': 1L, 'RDI': 4L, 'R8B': 1L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284099L, 'RBP': 9L}, 'memory': {4284096L: '\x0f', 4284097L: '\x94', 4284098L: '\xc0', 4284095L: 'A'}}, 'disassembly': 'SETZ R8B', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x0, test['pos']['registers'][reg_name]&0x0, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_1(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 14L, 'CL': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483643L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 14L, 'CL': 14L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294950912L, 'RSI': 4294950912L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483643L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_10(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 18446744073704757637L, 'CL': 133L, 'RDX': 7065280L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4239645L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4794032L}, 'memory': {4239645L: '\xd3', 4239646L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 18446744073704757637L, 'CL': 133L, 'RDX': 7065280L, 'RBP': 140737488346472L, 'RDI': 4794037L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4239647L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4794032L}, 'memory': {4239645L: '\xd3', 4239646L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_11(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 2L, 'CL': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483625L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 2L, 'CL': 2L, 'RDX': 22L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967292L, 'RSI': 4294967292L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483625L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_12(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 7L, 'CL': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483634L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 7L, 'CL': 7L, 'RDX': 13L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967168L, 'RSI': 4294967168L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483634L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_13(self):
''' Instruction SHL RDX, 0x6 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194368L, 'RSP': 140737488346160L, 'RDX': 7L, 'RIP': 4196815L, 'RBP': 0L}, 'memory': {4196816L: '\xc1', 4196817L: '\xe2', 4196818L: '\x06', 4196815L: 'H'}}, 'text': 'H\xc1\xe2\x06', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 56L, 'RSI': 64L, 'RDI': 2304L, 'RAX': 4194368L, 'RSP': 140737488346160L, 'RDX': 448L, 'RIP': 4196819L, 'RBP': 0L}, 'memory': {4196816L: '\xc1', 4196817L: '\xe2', 4196818L: '\x06', 4196815L: 'H'}}, 'disassembly': 'SHL RDX, 0x6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_14(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 8L, 'CL': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 8L, 'CL': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_15(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 12L, 'CL': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483630L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 12L, 'CL': 12L, 'RDX': 17L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'ESI': 4294963200L, 'RSI': 4294963200L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483630L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_16(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 3L, 'CL': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483638L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 3L, 'CL': 3L, 'RDX': 9L, 'RBP': 140737488345936L, 'RDI': 4782912L, 'ESI': 4294967288L, 'RSI': 4294967288L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483638L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_17(self):
''' Instruction SHL RAX, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 42L, 'RSI': 7065696L, 'CL': 42L, 'RDI': 6L, 'RAX': 1L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300296L, 'RBP': 1L}, 'memory': {4300296L: 'H', 4300297L: '\xd3', 4300298L: '\xe0'}}, 'text': 'H\xd3\xe0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 42L, 'RSI': 7065696L, 'CL': 42L, 'RDI': 6L, 'RAX': 4398046511104L, 'RSP': 140737488346168L, 'RDX': 8L, 'RIP': 4300299L, 'RBP': 1L}, 'memory': {4300296L: 'H', 4300297L: '\xd3', 4300298L: '\xe0'}}, 'disassembly': 'SHL RAX, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_18(self):
''' Instruction SHL RDX, 0x5 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 4L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4198064L, 'RBP': 7049240L}, 'memory': {4198064L: 'H', 4198065L: '\xc1', 4198066L: '\xe2', 4198067L: '\x05'}}, 'text': 'H\xc1\xe2\x05', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 4L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4198068L, 'RBP': 7049240L}, 'memory': {4198064L: 'H', 4198065L: '\xc1', 4198066L: '\xe2', 4198067L: '\x05'}}, 'disassembly': 'SHL RDX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_19(self):
''' Instruction SHL EBX, 0x8 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 0L, 'EBX': 0L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299474L, 'RBP': 0L}, 'memory': {4299474L: '\xc1', 4299475L: '\xe3', 4299476L: '\x08'}}, 'text': '\xc1\xe3\x08', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 140737488345859L, 'RSI': 4294967294L, 'RDI': 0L, 'EBX': 0L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 3L, 'RIP': 4299477L, 'RBP': 0L}, 'memory': {4299474L: '\xc1', 4299475L: '\xe3', 4299476L: '\x08'}}, 'disassembly': 'SHL EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_2(self):
''' Instruction SHL RAX, 0x5 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488346176L, 'RDX': 1L, 'RIP': 4197896L, 'RBP': 7049240L}, 'memory': {4197896L: 'H', 4197897L: '\xc1', 4197898L: '\xe0', 4197899L: '\x05'}}, 'text': 'H\xc1\xe0\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 32L, 'RSP': 140737488346176L, 'RDX': 1L, 'RIP': 4197900L, 'RBP': 7049240L}, 'memory': {4197896L: 'H', 4197897L: '\xc1', 4197898L: '\xe0', 4197899L: '\x05'}}, 'disassembly': 'SHL RAX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_20(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 5L, 'CL': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 2147483643L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 5L, 'CL': 5L, 'RDX': 4L, 'RBP': 140737488345936L, 'RDI': 4783008L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 643L, 'RAX': 2147483643L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_21(self):
''' Instruction SHL R12D, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 10L, 'CL': 10L, 'RDX': 74L, 'RBP': 7051232L, 'RDI': 7051232L, 'RSI': 1600L, 'RIP': 4221016L, 'R12D': 1L, 'RSP': 140737488345824L, 'RFLAGS': 518L, 'RAX': 2L}, 'memory': {4221016L: 'A', 4221017L: '\xd3', 4221018L: '\xe4'}}, 'text': 'A\xd3\xe4', 'pos': {'registers': {'RCX': 10L, 'CL': 10L, 'RDX': 74L, 'RBP': 7051232L, 'RDI': 7051232L, 'RSI': 1600L, 'RIP': 4221019L, 'R12D': 1024L, 'RSP': 140737488345824L, 'RFLAGS': 518L, 'RAX': 2L}, 'memory': {4221016L: 'A', 4221017L: '\xd3', 4221018L: '\xe4'}}, 'disassembly': 'SHL R12D, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_22(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 18446744073704757701L, 'CL': 197L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4239645L, 'RSP': 140737488346056L, 'RFLAGS': 647L, 'RAX': 4793968L}, 'memory': {4239645L: '\xd3', 4239646L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 18446744073704757701L, 'CL': 197L, 'RDX': 0L, 'RBP': 140737488346472L, 'RDI': 4793973L, 'ESI': 4294967264L, 'RSI': 4294967264L, 'RIP': 4239647L, 'RSP': 140737488346056L, 'RFLAGS': 643L, 'RAX': 4793968L}, 'memory': {4239645L: '\xd3', 4239646L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_23(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 0L, 'CL': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4416358L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416358L: '\xd3', 4416359L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 0L, 'CL': 0L, 'RDX': 140737488346512L, 'RBP': 140737488347312L, 'RDI': 140737488347328L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4416360L, 'RSP': 140737488346168L, 'RFLAGS': 582L, 'RAX': 6L}, 'memory': {4416358L: '\xd3', 4416359L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_24(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 15L, 'CL': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 518L, 'RAX': 140737488345984L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 15L, 'CL': 15L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782992L, 'ESI': 4294934528L, 'RSI': 4294934528L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_25(self):
''' Instruction SHL RBX, 0x2 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RBX': 0L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222801L, 'RBP': 7051232L}, 'memory': {4222801L: 'H', 4222802L: '\xc1', 4222803L: '\xe3', 4222804L: '\x02'}}, 'text': 'H\xc1\xe3\x02', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074240L, 'RSI': 7074272L, 'RBX': 0L, 'RDI': 7213056L, 'RAX': 138784L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4222805L, 'RBP': 7051232L}, 'memory': {4222801L: 'H', 4222802L: '\xc1', 4222803L: '\xe3', 4222804L: '\x02'}}, 'disassembly': 'SHL RBX, 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_26(self):
''' Instruction SHL RCX, 0x2 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 137168L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4222905L, 'RBP': 7051232L}, 'memory': {4222905L: 'H', 4222906L: '\xc1', 4222907L: '\xe1', 4222908L: '\x02'}}, 'text': 'H\xc1\xe1\x02', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 137168L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4222909L, 'RBP': 7051232L}, 'memory': {4222905L: 'H', 4222906L: '\xc1', 4222907L: '\xe1', 4222908L: '\x02'}}, 'disassembly': 'SHL RCX, 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_27(self):
''' Instruction SHL RDI, 0x5 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 50L, 'RAX': 7378697629483820663L, 'RSP': 140737488346080L, 'RDX': 2L, 'RIP': 4520052L, 'RBP': 140737488346112L}, 'memory': {4520052L: 'H', 4520053L: '\xc1', 4520054L: '\xe7', 4520055L: '\x05'}}, 'text': 'H\xc1\xe7\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 1600L, 'RAX': 7378697629483820663L, 'RSP': 140737488346080L, 'RDX': 2L, 'RIP': 4520056L, 'RBP': 140737488346112L}, 'memory': {4520052L: 'H', 4520053L: '\xc1', 4520054L: '\xe7', 4520055L: '\x05'}}, 'disassembly': 'SHL RDI, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_28(self):
''' Instruction SHL R12D, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 3L, 'CL': 3L, 'RDX': 3L, 'RBP': 7051232L, 'RDI': 7051232L, 'RSI': 24L, 'RIP': 4221016L, 'R12D': 1L, 'RSP': 140737488345824L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4221016L: 'A', 4221017L: '\xd3', 4221018L: '\xe4'}}, 'text': 'A\xd3\xe4', 'pos': {'registers': {'RCX': 3L, 'CL': 3L, 'RDX': 3L, 'RBP': 7051232L, 'RDI': 7051232L, 'RSI': 24L, 'RIP': 4221019L, 'R12D': 8L, 'RSP': 140737488345824L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4221016L: 'A', 4221017L: '\xd3', 4221018L: '\xe4'}}, 'disassembly': 'SHL R12D, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_29(self):
''' Instruction SHL RDX, 0x20 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 2610683886L, 'RSP': 140737488346128L, 'RDX': 11841L, 'RIP': 4297488L, 'RBP': 140737488346472L}, 'memory': {4297488L: 'H', 4297489L: '\xc1', 4297490L: '\xe2', 4297491L: ' '}}, 'text': 'H\xc1\xe2 ', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737488346472L, 'RDI': 895L, 'RAX': 2610683886L, 'RSP': 140737488346128L, 'RDX': 50856707751936L, 'RIP': 4297492L, 'RBP': 140737488346472L}, 'memory': {4297488L: 'H', 4297489L: '\xc1', 4297490L: '\xe2', 4297491L: ' '}}, 'disassembly': 'SHL RDX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_3(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 8L, 'CL': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 140737488345984L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 8L, 'CL': 8L, 'RDX': 140737488345952L, 'RBP': 140737488345936L, 'RDI': 4782896L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 140737488345984L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_4(self):
''' Instruction SHL RAX, 0x5 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197896L, 'RBP': 7049240L}, 'memory': {4197896L: 'H', 4197897L: '\xc1', 4197898L: '\xe0', 4197899L: '\x05'}}, 'text': 'H\xc1\xe0\x05', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197900L, 'RBP': 7049240L}, 'memory': {4197896L: 'H', 4197897L: '\xc1', 4197898L: '\xe0', 4197899L: '\x05'}}, 'disassembly': 'SHL RAX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_5(self):
''' Instruction SHL R13, 0x3 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074272L, 'RSI': 1600L, 'RDI': 7051232L, 'R13': 10L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 7065472L, 'RIP': 4520080L, 'RBP': 140737488346112L}, 'memory': {4520080L: 'I', 4520081L: '\xc1', 4520082L: '\xe5', 4520083L: '\x03'}}, 'text': 'I\xc1\xe5\x03', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7074272L, 'RSI': 1600L, 'RDI': 7051232L, 'R13': 80L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 7065472L, 'RIP': 4520084L, 'RBP': 140737488346112L}, 'memory': {4520080L: 'I', 4520081L: '\xc1', 4520082L: '\xe5', 4520083L: '\x03'}}, 'disassembly': 'SHL R13, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_6(self):
''' Instruction SHL EBX, 0x8 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 2L, 'EBX': 778L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299474L, 'RBP': 0L}, 'memory': {4299474L: '\xc1', 4299475L: '\xe3', 4299476L: '\x08'}}, 'text': '\xc1\xe3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 2L, 'EBX': 199168L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299477L, 'RBP': 0L}, 'memory': {4299474L: '\xc1', 4299475L: '\xe3', 4299476L: '\x08'}}, 'disassembly': 'SHL EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_7(self):
''' Instruction SHL EBX, 0x8 '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 1L, 'EBX': 3L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 10L, 'RIP': 4299474L, 'RBP': 0L}, 'memory': {4299474L: '\xc1', 4299475L: '\xe3', 4299476L: '\x08'}}, 'text': '\xc1\xe3\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345862L, 'RSI': 4294967294L, 'RDI': 1L, 'EBX': 768L, 'RAX': 46L, 'RSP': 140737488345728L, 'RDX': 10L, 'RIP': 4299477L, 'RBP': 0L}, 'memory': {4299474L: '\xc1', 4299475L: '\xe3', 4299476L: '\x08'}}, 'disassembly': 'SHL EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_8(self):
''' Instruction SHL R11D, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 4L, 'CL': 4L, 'RDX': 1L, 'RBP': 32768L, 'RDI': 2L, 'RSI': 4194304L, 'R11D': 4294967295L, 'RIP': 4285484L, 'RSP': 140737488346144L, 'RFLAGS': 518L, 'RAX': 4L}, 'memory': {4285484L: 'A', 4285485L: '\xd3', 4285486L: '\xe3'}}, 'text': 'A\xd3\xe3', 'pos': {'registers': {'RCX': 4L, 'CL': 4L, 'RDX': 1L, 'RBP': 32768L, 'RDI': 2L, 'RSI': 4194304L, 'R11D': 4294967280L, 'RIP': 4285487L, 'RSP': 140737488346144L, 'RFLAGS': 647L, 'RAX': 4L}, 'memory': {4285484L: 'A', 4285485L: '\xd3', 4285486L: '\xe3'}}, 'disassembly': 'SHL R11D, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHL_9(self):
''' Instruction SHL ESI, CL '''
test = {'mnemonic': 'SHL', 'pre': {'registers': {'RCX': 8L, 'CL': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967295L, 'RSI': 4294967295L, 'RIP': 4248022L, 'RSP': 140737488344248L, 'RFLAGS': 514L, 'RAX': 2147483619L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'text': '\xd3\xe6', 'pos': {'registers': {'RCX': 8L, 'CL': 8L, 'RDX': 28L, 'RBP': 140737488345936L, 'RDI': 4783056L, 'ESI': 4294967040L, 'RSI': 4294967040L, 'RIP': 4248024L, 'RSP': 140737488344248L, 'RFLAGS': 647L, 'RAX': 2147483619L}, 'memory': {4248022L: '\xd3', 4248023L: '\xe6'}}, 'disassembly': 'SHL ESI, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_1(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 74L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 37L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_10(self):
''' Instruction SHR R8D, CL '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RCX': 26L, 'CL': 26L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 33824L, 'R8D': 4294967295L, 'RIP': 4416446L, 'RSP': 140737488346168L, 'RFLAGS': 514L, 'RAX': 140737488347364L}, 'memory': {4416448L: '\xe8', 4416446L: 'A', 4416447L: '\xd3'}}, 'text': 'A\xd3\xe8', 'pos': {'registers': {'RCX': 26L, 'CL': 26L, 'RDX': 0L, 'RBP': 140737488347312L, 'RDI': 140737488347392L, 'RSI': 33824L, 'R8D': 63L, 'RIP': 4416449L, 'RSP': 140737488346168L, 'RFLAGS': 2567L, 'RAX': 140737488347364L}, 'memory': {4416448L: '\xe8', 4416446L: 'A', 4416447L: '\xd3'}}, 'disassembly': 'SHR R8D, CL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_100(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_101(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_11(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'R13': 86L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'R13': 43L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_12(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 77L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 38L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_13(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 74L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 37L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_14(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 1979931136L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283939L, 'RBP': 3L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 7734106L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283942L, 'RBP': 3L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_15(self):
''' Instruction SHR RCX, 0xf '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1616L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219879L, 'RBP': 7051232L}, 'memory': {4219880L: '\xc1', 4219881L: '\xe9', 4219882L: '\x0f', 4219879L: 'H'}}, 'text': 'H\xc1\xe9\x0f', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219883L, 'RBP': 7051232L}, 'memory': {4219880L: '\xc1', 4219881L: '\xe9', 4219882L: '\x0f', 4219879L: 'H'}}, 'disassembly': 'SHR RCX, 0xf', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_16(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 74L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 37L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_17(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 103L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 51L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_18(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_19(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_2(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125932L, 'RAX': 3476L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_20(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_21(self):
''' Instruction SHR ESI, 0xc '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 62914623L, 'ESI': 62914623L, 'RDI': 4L, 'RAX': 15L, 'RSP': 140737488345968L, 'RDX': 63L, 'RIP': 4284253L, 'RBP': 9L}, 'memory': {4284253L: '\xc1', 4284254L: '\xee', 4284255L: '\x0c'}}, 'text': '\xc1\xee\x0c', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 15360L, 'ESI': 15360L, 'RDI': 4L, 'RAX': 15L, 'RSP': 140737488345968L, 'RDX': 63L, 'RIP': 4284256L, 'RBP': 9L}, 'memory': {4284253L: '\xc1', 4284254L: '\xee', 4284255L: '\x0c'}}, 'disassembly': 'SHR ESI, 0xc', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_22(self):
''' Instruction SHR EAX, 0x16 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'EAX': 62914623L, 'RFLAGS': 534L, 'RCX': 4096L, 'RSI': 62914623L, 'RDI': 4L, 'RAX': 62914623L, 'RSP': 140737488345968L, 'RDX': 62914623L, 'RIP': 4284244L, 'RBP': 9L}, 'memory': {4284244L: '\xc1', 4284245L: '\xe8', 4284246L: '\x16'}}, 'text': '\xc1\xe8\x16', 'pos': {'registers': {'EAX': 15L, 'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 62914623L, 'RDI': 4L, 'RAX': 15L, 'RSP': 140737488345968L, 'RDX': 62914623L, 'RIP': 4284247L, 'RBP': 9L}, 'memory': {4284244L: '\xc1', 4284245L: '\xe8', 4284246L: '\x16'}}, 'disassembly': 'SHR EAX, 0x16', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_23(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'R13': 78L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'R13': 39L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_24(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125853L, 'RAX': 3555L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_25(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'R13': 78L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'R13': 39L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 124L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_26(self):
''' Instruction SHR RDX, 0xc '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1616L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 94L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219843L, 'RBP': 7051232L}, 'memory': {4219843L: 'H', 4219844L: '\xc1', 4219845L: '\xea', 4219846L: '\x0c'}}, 'text': 'H\xc1\xea\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1616L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 94L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4219847L, 'RBP': 7051232L}, 'memory': {4219843L: 'H', 4219844L: '\xc1', 4219845L: '\xea', 4219846L: '\x0c'}}, 'disassembly': 'SHR RDX, 0xc', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_27(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_28(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2695L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'RAX': 11068046444225730970L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'RAX': 11068046444225730970L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_29(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_3(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EBX': 7734106L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283939L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EBX': 30211L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283942L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_30(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_31(self):
''' Instruction SHR EDX, 0x4 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 24L, 'RDI': 7051232L, 'EDX': 32L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219798L, 'RBP': 7051232L}, 'memory': {4219800L: '\x04', 4219798L: '\xc1', 4219799L: '\xea'}}, 'text': '\xc1\xea\x04', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 24L, 'RDI': 7051232L, 'EDX': 2L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219801L, 'RBP': 7051232L}, 'memory': {4219800L: '\x04', 4219798L: '\xc1', 4219799L: '\xea'}}, 'disassembly': 'SHR EDX, 0x4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_32(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_33(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_34(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125774L, 'RAX': 3634L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_35(self):
''' Instruction SHR RAX, 0x12 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219883L, 'RBP': 7051232L}, 'memory': {4219883L: 'H', 4219884L: '\xc1', 4219885L: '\xe8', 4219886L: '\x12'}}, 'text': 'H\xc1\xe8\x12', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219887L, 'RBP': 7051232L}, 'memory': {4219883L: 'H', 4219884L: '\xc1', 4219885L: '\xe8', 4219886L: '\x12'}}, 'disassembly': 'SHR RAX, 0x12', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_36(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_37(self):
''' Instruction SHR RAX, 0x6 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219717L, 'RBP': 7051232L}, 'memory': {4219720L: '\x06', 4219717L: 'H', 4219718L: '\xc1', 4219719L: '\xe8'}}, 'text': 'H\xc1\xe8\x06', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 25L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219721L, 'RBP': 7051232L}, 'memory': {4219720L: '\x06', 4219717L: 'H', 4219718L: '\xc1', 4219719L: '\xe8'}}, 'disassembly': 'SHR RAX, 0x6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_38(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_39(self):
''' Instruction SHR EDI, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 532341759L, 'RSI': 7065696L, 'RAX': 132775L, 'RDI': 132775L, 'EDI': 132775L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300127L, 'RBP': 1L}, 'memory': {4300128L: '\xef', 4300129L: '\x08', 4300127L: '\xc1'}}, 'text': '\xc1\xef\x08', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 532341759L, 'RSI': 7065696L, 'RAX': 132775L, 'RDI': 518L, 'EDI': 518L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300130L, 'RBP': 1L}, 'memory': {4300128L: '\xef', 4300129L: '\x08', 4300127L: '\xc1'}}, 'disassembly': 'SHR EDI, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_4(self):
''' Instruction SHR EDX, 0x4 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1616L, 'RSI': 1600L, 'RDI': 7051232L, 'EDX': 1616L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219798L, 'RBP': 7051232L}, 'memory': {4219800L: '\x04', 4219798L: '\xc1', 4219799L: '\xea'}}, 'text': '\xc1\xea\x04', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 1616L, 'RSI': 1600L, 'RDI': 7051232L, 'EDX': 101L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 101L, 'RIP': 4219801L, 'RBP': 7051232L}, 'memory': {4219800L: '\x04', 4219798L: '\xc1', 4219799L: '\xea'}}, 'disassembly': 'SHR EDX, 0x4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_40(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_41(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_42(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'R13': 71L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'R13': 35L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_43(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125409L, 'RAX': 3999L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_44(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_45(self):
''' Instruction SHR RDX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2567L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7378697629483820663L, 'RSP': 140737488346080L, 'RDX': 66L, 'RIP': 4520039L, 'RBP': 140737488346112L}, 'memory': {4520040L: '\xc1', 4520041L: '\xea', 4520042L: '\x05', 4520039L: 'H'}}, 'text': 'H\xc1\xea\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 7213056L, 'RAX': 7378697629483820663L, 'RSP': 140737488346080L, 'RDX': 2L, 'RIP': 4520043L, 'RBP': 140737488346112L}, 'memory': {4520040L: '\xc1', 4520041L: '\xea', 4520042L: '\x05', 4520039L: 'H'}}, 'disassembly': 'SHR RDX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_46(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_47(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'R13': 71L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'R13': 35L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 102L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_48(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'R13': 86L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'R13': 43L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_49(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 77L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 38L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_5(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 30211L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283939L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 118L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283942L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_50(self):
''' Instruction SHR RDX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 259L, 'RSP': 140737488343968L, 'RDX': 259L, 'RIP': 4661312L, 'RBP': 8192L}, 'memory': {4661312L: 'H', 4661313L: '\xc1', 4661314L: '\xea', 4661315L: '\x08'}}, 'text': 'H\xc1\xea\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 259L, 'RSP': 140737488343968L, 'RDX': 1L, 'RIP': 4661316L, 'RBP': 8192L}, 'memory': {4661312L: 'H', 4661313L: '\xc1', 4661314L: '\xea', 4661315L: '\x08'}}, 'disassembly': 'SHR RDX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_51(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2695L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 21L, 'RAX': 14757395258967641297L, 'RSP': 140737488344248L, 'RDX': 16L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 21L, 'RAX': 14757395258967641297L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_52(self):
''' Instruction SHR R8D, 0x4 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'R8D': 132775L, 'RFLAGS': 519L, 'RCX': 132775L, 'RSI': 7065696L, 'RDI': 518L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300144L, 'RBP': 1L}, 'memory': {4300144L: 'A', 4300145L: '\xc1', 4300146L: '\xe8', 4300147L: '\x04'}}, 'text': 'A\xc1\xe8\x04', 'pos': {'registers': {'R8D': 8298L, 'RFLAGS': 518L, 'RCX': 132775L, 'RSI': 7065696L, 'RDI': 518L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300148L, 'RBP': 1L}, 'memory': {4300144L: 'A', 4300145L: '\xc1', 4300146L: '\xe8', 4300147L: '\x04'}}, 'disassembly': 'SHR R8D, 0x4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_53(self):
''' Instruction SHR RCX, 0x6 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219801L, 'RBP': 7051232L}, 'memory': {4219801L: 'H', 4219802L: '\xc1', 4219803L: '\xe9', 4219804L: '\x06'}}, 'text': 'H\xc1\xe9\x06', 'pos': {'registers': {'RFLAGS': 583L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219805L, 'RBP': 7051232L}, 'memory': {4219801L: 'H', 4219802L: '\xc1', 4219803L: '\xe9', 4219804L: '\x06'}}, 'disassembly': 'SHR RCX, 0x6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_54(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_55(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_56(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2567L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 44L, 'RAX': 3689348814741910332L, 'RSP': 140737488344248L, 'RDX': 35L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 44L, 'RAX': 3689348814741910332L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_57(self):
''' Instruction SHR EAX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'EAX': 469778721L, 'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284086L, 'RBP': 3L}, 'memory': {4284088L: '\x05', 4284086L: '\xc1', 4284087L: '\xe8'}}, 'text': '\xc1\xe8\x05', 'pos': {'registers': {'EAX': 14680585L, 'RFLAGS': 518L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 14680585L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284089L, 'RBP': 3L}, 'memory': {4284088L: '\x05', 4284086L: '\xc1', 4284087L: '\xe8'}}, 'disassembly': 'SHR EAX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_58(self):
''' Instruction SHR EDX, 0x4 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'EDX': 32L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219596L, 'RBP': 7051232L}, 'memory': {4219596L: '\xc1', 4219597L: '\xea', 4219598L: '\x04'}}, 'text': '\xc1\xea\x04', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'EDX': 2L, 'RAX': 47L, 'RSP': 140737488345824L, 'RDX': 2L, 'RIP': 4219599L, 'RBP': 7051232L}, 'memory': {4219596L: '\xc1', 4219597L: '\xea', 4219598L: '\x04'}}, 'disassembly': 'SHR EDX, 0x4', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_59(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EBX': 7734106L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283939L, 'RBP': 3L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'EBX': 30211L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283942L, 'RBP': 3L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_6(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'EBX': 118L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 104L, 'RIP': 4283939L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'EBX': 0L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 104L, 'RIP': 4283942L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_60(self):
''' Instruction SHR EAX, 0x16 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'EAX': 29360191L, 'RFLAGS': 530L, 'RCX': 64L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 29360191L, 'RSP': 140737488345968L, 'RDX': 29360191L, 'RIP': 4284244L, 'RBP': 3L}, 'memory': {4284244L: '\xc1', 4284245L: '\xe8', 4284246L: '\x16'}}, 'text': '\xc1\xe8\x16', 'pos': {'registers': {'EAX': 7L, 'RFLAGS': 514L, 'RCX': 64L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 7L, 'RSP': 140737488345968L, 'RDX': 29360191L, 'RIP': 4284247L, 'RBP': 3L}, 'memory': {4284244L: '\xc1', 4284245L: '\xe8', 4284246L: '\x16'}}, 'disassembly': 'SHR EAX, 0x16', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_61(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 583L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'R13': 0L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_62(self):
''' Instruction SHR R15D, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'R15D': 74L, 'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 146L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4220984L, 'RBP': 7051232L}, 'memory': {4220984L: 'A', 4220985L: '\xc1', 4220986L: '\xef', 4220987L: '\x05'}}, 'text': 'A\xc1\xef\x05', 'pos': {'registers': {'R15D': 2L, 'RFLAGS': 514L, 'RCX': 7051336L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 146L, 'RSP': 140737488345824L, 'RDX': 74L, 'RIP': 4220988L, 'RBP': 7051232L}, 'memory': {4220984L: 'A', 4220985L: '\xc1', 4220986L: '\xef', 4220987L: '\x05'}}, 'disassembly': 'SHR R15D, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_63(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_64(self):
''' Instruction SHR RDX, 0xc '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 91L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219843L, 'RBP': 7051232L}, 'memory': {4219843L: 'H', 4219844L: '\xc1', 4219845L: '\xea', 4219846L: '\x0c'}}, 'text': 'H\xc1\xea\x0c', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 91L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4219847L, 'RBP': 7051232L}, 'memory': {4219843L: 'H', 4219844L: '\xc1', 4219845L: '\xea', 4219846L: '\x0c'}}, 'disassembly': 'SHR RDX, 0xc', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_65(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 515L, 'RCX': 8L, 'RSI': 4792552L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 60L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_66(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 583L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'R13': 0L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_67(self):
''' Instruction SHR ECX, 0xc '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 132775L, 'RSI': 7065696L, 'ECX': 132775L, 'RDI': 518L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300148L, 'RBP': 1L}, 'memory': {4300148L: '\xc1', 4300149L: '\xe9', 4300150L: '\x0c'}}, 'text': '\xc1\xe9\x0c', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 7065696L, 'ECX': 32L, 'RDI': 518L, 'RAX': 132775L, 'RSP': 140737488346168L, 'RDX': 3219913727L, 'RIP': 4300151L, 'RBP': 1L}, 'memory': {4300148L: '\xc1', 4300149L: '\xe9', 4300150L: '\x0c'}}, 'disassembly': 'SHR ECX, 0xc', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_68(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 103L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 51L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_69(self):
''' Instruction SHR EAX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'EAX': 469778755L, 'RFLAGS': 518L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778755L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284086L, 'RBP': 9L}, 'memory': {4284088L: '\x05', 4284086L: '\xc1', 4284087L: '\xe8'}}, 'text': '\xc1\xe8\x05', 'pos': {'registers': {'EAX': 14680586L, 'RFLAGS': 518L, 'RCX': 511L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 14680586L, 'RSP': 140737488345968L, 'RDX': 3L, 'RIP': 4284089L, 'RBP': 9L}, 'memory': {4284088L: '\x05', 4284086L: '\xc1', 4284087L: '\xe8'}}, 'disassembly': 'SHR EAX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_7(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 74L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'R13': 37L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 120L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_70(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 103L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 519L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 51L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_71(self):
''' Instruction SHR RAX, 0x9 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 583L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 32L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219814L, 'RBP': 7051232L}, 'memory': {4219816L: '\xe8', 4219817L: '\t', 4219814L: 'H', 4219815L: '\xc1'}}, 'text': 'H\xc1\xe8\t', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 32L, 'RIP': 4219818L, 'RBP': 7051232L}, 'memory': {4219816L: '\xe8', 4219817L: '\t', 4219814L: 'H', 4219815L: '\xc1'}}, 'disassembly': 'SHR RAX, 0x9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_72(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 583L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'R13': 0L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 8L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_73(self):
''' Instruction SHR RAX, 0x9 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 25L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219814L, 'RBP': 7051232L}, 'memory': {4219816L: '\xe8', 4219817L: '\t', 4219814L: 'H', 4219815L: '\xc1'}}, 'text': 'H\xc1\xe8\t', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 25L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 3L, 'RSP': 140737488345824L, 'RDX': 1616L, 'RIP': 4219818L, 'RBP': 7051232L}, 'memory': {4219816L: '\xe8', 4219817L: '\t', 4219814L: 'H', 4219815L: '\xc1'}}, 'disassembly': 'SHR RAX, 0x9', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_74(self):
''' Instruction SHR EAX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'EAX': 469778722L, 'RFLAGS': 514L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 469778722L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284086L, 'RBP': 9L}, 'memory': {4284088L: '\x05', 4284086L: '\xc1', 4284087L: '\xe8'}}, 'text': '\xc1\xe8\x05', 'pos': {'registers': {'EAX': 14680585L, 'RFLAGS': 518L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'RAX': 14680585L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284089L, 'RBP': 9L}, 'memory': {4284088L: '\x05', 4284086L: '\xc1', 4284087L: '\xe8'}}, 'disassembly': 'SHR EAX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_75(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 72L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 36L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_76(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792432L, 'RDI': 140737488345968L, 'R13': 1L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 9L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_77(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125330L, 'RAX': 4078L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_78(self):
''' Instruction SHR EDX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 63L, 'RSI': 4194304L, 'RDI': 1L, 'EDX': 469778721L, 'RAX': 469778721L, 'RSP': 140737488346144L, 'RDX': 469778721L, 'RIP': 4284964L, 'RBP': 32768L}, 'memory': {4284964L: '\xc1', 4284965L: '\xea', 4284966L: '\x05'}}, 'text': '\xc1\xea\x05', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 63L, 'RSI': 4194304L, 'RDI': 1L, 'EDX': 14680585L, 'RAX': 469778721L, 'RSP': 140737488346144L, 'RDX': 14680585L, 'RIP': 4284967L, 'RBP': 32768L}, 'memory': {4284964L: '\xc1', 4284965L: '\xea', 4284966L: '\x05'}}, 'disassembly': 'SHR EDX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_79(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 72L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'R13': 36L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 103L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_8(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2567L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 43L, 'RAX': 7378697629483820655L, 'RSP': 140737488344248L, 'RDX': 34L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 43L, 'RAX': 7378697629483820655L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_80(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'R13': 2L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 12L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_81(self):
''' Instruction SHR ESI, 0xc '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 29360191L, 'ESI': 29360191L, 'RDI': 4L, 'RAX': 7L, 'RSP': 140737488345968L, 'RDX': 63L, 'RIP': 4284253L, 'RBP': 3L}, 'memory': {4284253L: '\xc1', 4284254L: '\xee', 4284255L: '\x0c'}}, 'text': '\xc1\xee\x0c', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 7168L, 'ESI': 7168L, 'RDI': 4L, 'RAX': 7L, 'RSP': 140737488345968L, 'RDX': 63L, 'RIP': 4284256L, 'RBP': 3L}, 'memory': {4284253L: '\xc1', 4284254L: '\xee', 4284255L: '\x0c'}}, 'disassembly': 'SHR ESI, 0xc', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_82(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 8L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'R13': 4L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 34L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_83(self):
''' Instruction SHR EAX, 0xe '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'EAX': 470008163L, 'RFLAGS': 582L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 4L, 'RAX': 470008163L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4284975L, 'RBP': 32768L}, 'memory': {4284976L: '\xe8', 4284977L: '\x0e', 4284975L: '\xc1'}}, 'text': '\xc1\xe8\x0e', 'pos': {'registers': {'EAX': 28687L, 'RFLAGS': 518L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 4L, 'RAX': 28687L, 'RSP': 140737488346144L, 'RDX': 3L, 'RIP': 4284978L, 'RBP': 32768L}, 'memory': {4284976L: '\xe8', 4284977L: '\x0e', 4284975L: '\xc1'}}, 'disassembly': 'SHR EAX, 0xe', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_84(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 30211L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283939L, 'RBP': 3L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 118L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283942L, 'RBP': 3L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_85(self):
''' Instruction SHR R15D, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'R15D': 3L, 'RFLAGS': 518L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 4L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4220984L, 'RBP': 7051232L}, 'memory': {4220984L: 'A', 4220985L: '\xc1', 4220986L: '\xef', 4220987L: '\x05'}}, 'text': 'A\xc1\xef\x05', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 7051336L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 4L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4220988L, 'RBP': 7051232L}, 'memory': {4220984L: 'A', 4220985L: '\xc1', 4220986L: '\xef', 4220987L: '\x05'}}, 'disassembly': 'SHR R15D, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_86(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_87(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_88(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 3L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 3689348814741910324L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_89(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_9(self):
''' Instruction SHR RCX, 0x6 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1616L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 101L, 'RIP': 4219801L, 'RBP': 7051232L}, 'memory': {4219801L: 'H', 4219802L: '\xc1', 4219803L: '\xe9', 4219804L: '\x06'}}, 'text': 'H\xc1\xe9\x06', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 25L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 1616L, 'RSP': 140737488345824L, 'RDX': 101L, 'RIP': 4219805L, 'RBP': 7051232L}, 'memory': {4219801L: 'H', 4219802L: '\xc1', 4219803L: '\xe9', 4219804L: '\x06'}}, 'disassembly': 'SHR RCX, 0x6', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_90(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'R13': 86L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'R13': 43L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 134L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_91(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 78L, 'RSI': 4782912L, 'ECX': 78L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244475L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 4782912L, 'ECX': 2L, 'RDI': 140737354125567L, 'RAX': 3841L, 'RSP': 140737488346056L, 'RDX': 78L, 'RIP': 4244478L, 'RBP': 7049504L}, 'memory': {4244475L: '\xc1', 4244476L: '\xe9', 4244477L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_92(self):
''' Instruction SHR EDX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 4L, 'EDX': 470008163L, 'RAX': 470008163L, 'RSP': 140737488346144L, 'RDX': 470008163L, 'RIP': 4284964L, 'RBP': 32768L}, 'memory': {4284964L: '\xc1', 4284965L: '\xea', 4284966L: '\x05'}}, 'text': '\xc1\xea\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4095L, 'RSI': 4194304L, 'RDI': 4L, 'EDX': 14687755L, 'RAX': 470008163L, 'RSP': 140737488346144L, 'RDX': 14687755L, 'RIP': 4284967L, 'RBP': 32768L}, 'memory': {4284964L: '\xc1', 4284965L: '\xea', 4284966L: '\x05'}}, 'disassembly': 'SHR EDX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_93(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_94(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 68L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_95(self):
''' Instruction SHR RAX, 0x20 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 259L, 'RSP': 140737488343968L, 'RDX': 1L, 'RIP': 4661316L, 'RBP': 8192L}, 'memory': {4661316L: 'H', 4661317L: '\xc1', 4661318L: '\xe8', 4661319L: ' '}}, 'text': 'H\xc1\xe8 ', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488343968L, 'RDI': 1L, 'RAX': 0L, 'RSP': 140737488343968L, 'RDX': 1L, 'RIP': 4661320L, 'RBP': 8192L}, 'memory': {4661316L: 'H', 4661317L: '\xc1', 4661318L: '\xe8', 4661319L: ' '}}, 'disassembly': 'SHR RAX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_96(self):
''' Instruction SHR ECX, 0x5 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 643L, 'RCX': 32L, 'RSI': 7035136L, 'ECX': 32L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245627L, 'RBP': 80L}, 'memory': {4245627L: '\xc1', 4245628L: '\xe9', 4245629L: '\x05'}}, 'text': '\xc1\xe9\x05', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 7035136L, 'ECX': 1L, 'RDI': 7071792L, 'RAX': 7071792L, 'RSP': 140737488346152L, 'RDX': 32L, 'RIP': 4245630L, 'RBP': 80L}, 'memory': {4245627L: '\xc1', 4245628L: '\xe9', 4245629L: '\x05'}}, 'disassembly': 'SHR ECX, 0x5', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_97(self):
''' Instruction SHR EBX, 0x8 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 1979931136L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283939L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'text': '\xc1\xeb\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'EBX': 7734106L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 6L, 'RIP': 4283942L, 'RBP': 9L}, 'memory': {4283939L: '\xc1', 4283940L: '\xeb', 4283941L: '\x08'}}, 'disassembly': 'SHR EBX, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_98(self):
''' Instruction SHR R13, 0x1 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 34L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320756L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'text': 'I\xd1\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'R13': 17L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 78L, 'RIP': 4320759L, 'RBP': 4792416L}, 'memory': {4320756L: 'I', 4320757L: '\xd1', 4320758L: '\xed'}}, 'disassembly': 'SHR R13, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSHR_99(self):
''' Instruction SHR RDX, 0x3 '''
test = {'mnemonic': 'SHR', 'pre': {'registers': {'RFLAGS': 2563L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 3L, 'RAX': 7378697629483820647L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327722L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'text': 'H\xc1\xea\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 3L, 'RAX': 7378697629483820647L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327726L, 'RBP': 140737488345936L}, 'memory': {4327722L: 'H', 4327723L: '\xc1', 4327724L: '\xea', 4327725L: '\x03'}}, 'disassembly': 'SHR RDX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_1(self):
''' Instruction SUB RDI, RAX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 21L, 'RAX': 20L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327733L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'text': 'H)\xc7', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 1L, 'RAX': 20L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327736L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'disassembly': 'SUB RDI, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_10(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R13': 2L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R13': 2L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_100(self):
''' Instruction SUB RCX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4782903L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248003L: 'H', 4248004L: ')', 4248005L: '\xf9'}}, 'text': 'H)\xf9', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 4294967295L, 'RDI': 4782896L, 'RAX': 2147483634L, 'RSP': 140737488344248L, 'RDX': 13L, 'RIP': 4248006L, 'RBP': 140737488345936L}, 'memory': {4248003L: 'H', 4248004L: ')', 4248005L: '\xf9'}}, 'disassembly': 'SUB RCX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_101(self):
''' Instruction SUB R15, RBX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 0L, 'RBX': 7074240L, 'RDX': 0L, 'RBP': 7051232L, 'RDI': 7213056L, 'R15': 7213056L, 'RSI': 24L, 'RIP': 4223949L, 'RSP': 140737488345824L, 'RFLAGS': 518L, 'RAX': 0L}, 'memory': {4223949L: 'I', 4223950L: ')', 4223951L: '\xdf'}}, 'text': 'I)\xdf', 'pos': {'registers': {'RCX': 0L, 'RBX': 7074240L, 'RDX': 0L, 'RBP': 7051232L, 'RDI': 7213056L, 'R15': 138816L, 'RSI': 24L, 'RIP': 4223952L, 'RSP': 140737488345824L, 'RFLAGS': 514L, 'RAX': 0L}, 'memory': {4223949L: 'I', 4223950L: ')', 4223951L: '\xdf'}}, 'disassembly': 'SUB R15, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_11(self):
''' Instruction SUB EAX, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488345984L, 'RDX': 18446744073709551615L, 'RIP': 4394926L, 'RBP': 7049504L}, 'memory': {4394928L: '\x01', 4394926L: '\x83', 4394927L: '\xe8'}}, 'text': '\x83\xe8\x01', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488345984L, 'RDX': 18446744073709551615L, 'RIP': 4394929L, 'RBP': 7049504L}, 'memory': {4394928L: '\x01', 4394926L: '\x83', 4394927L: '\xe8'}}, 'disassembly': 'SUB EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_12(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 4794032L, 'RSP': 140737488346056L, 'RDX': 32L, 'RIP': 4239760L, 'RBP': 140737488346472L}, 'memory': {4239760L: 'H', 4239761L: ')', 4239762L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 18446744073709551611L, 'RSP': 140737488346056L, 'RDX': 32L, 'RIP': 4239763L, 'RBP': 140737488346472L}, 'memory': {4239760L: 'H', 4239761L: ')', 4239762L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_13(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_14(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'R13': 4L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4783020L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125667L, 'RDI': 140737354125663L, 'R13': 4L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4783020L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_15(self):
''' Instruction SUB R13D, EBP '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 4095L, 'RDX': 3L, 'RBP': 9L, 'RDI': 4L, 'RSI': 62914623L, 'RIP': 4284142L, 'R13D': 9L, 'EBP': 9L, 'RSP': 140737488345968L, 'RFLAGS': 534L, 'RAX': 3L}, 'memory': {4284144L: '\xed', 4284142L: 'A', 4284143L: ')'}}, 'text': 'A)\xed', 'pos': {'registers': {'RCX': 4095L, 'RDX': 3L, 'RBP': 9L, 'RDI': 4L, 'RSI': 62914623L, 'RIP': 4284145L, 'R13D': 0L, 'EBP': 9L, 'RSP': 140737488345968L, 'RFLAGS': 582L, 'RAX': 3L}, 'memory': {4284144L: '\xed', 4284142L: 'A', 4284143L: ')'}}, 'disassembly': 'SUB R13D, EBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_16(self):
''' Instruction SUB RSP, 0x8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345896L, 'RDX': 699L, 'RIP': 4392993L, 'RBP': 140737354125312L}, 'memory': {4392993L: 'H', 4392994L: '\x83', 4392995L: '\xec', 4392996L: '\x08'}}, 'text': 'H\x83\xec\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 699L, 'RIP': 4392997L, 'RBP': 140737354125312L}, 'memory': {4392993L: 'H', 4392994L: '\x83', 4392995L: '\xec', 4392996L: '\x08'}}, 'disassembly': 'SUB RSP, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_17(self):
''' Instruction SUB RCX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 140737488347312L, 'RSI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416339L, 'RBP': 140737488347312L}, 'memory': {4416339L: 'H', 4416340L: ')', 4416341L: '\xf9'}}, 'text': 'H)\xf9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4294967295L, 'RDI': 140737488347312L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4416342L, 'RBP': 140737488347312L}, 'memory': {4416339L: 'H', 4416340L: ')', 4416341L: '\xf9'}}, 'disassembly': 'SUB RCX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_18(self):
''' Instruction SUB RAX, RDX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737354125693L, 'RDI': 140737354125691L, 'RAX': 2147483647L, 'RSP': 140737488344256L, 'RDX': 28L, 'RIP': 4337019L, 'RBP': 140737488345936L}, 'memory': {4337019L: 'H', 4337020L: ')', 4337021L: '\xd0'}}, 'text': 'H)\xd0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737354125693L, 'RDI': 140737354125691L, 'RAX': 2147483619L, 'RSP': 140737488344256L, 'RDX': 28L, 'RIP': 4337022L, 'RBP': 140737488345936L}, 'memory': {4337019L: 'H', 4337020L: ')', 4337021L: '\xd0'}}, 'disassembly': 'SUB RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_19(self):
''' Instruction SUB EDX, 0x30 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 659L, 'RCX': 140737488345861L, 'RSI': 4294967294L, 'RDI': 1L, 'EDX': 49L, 'RAX': 48L, 'RSP': 140737488345728L, 'RDX': 49L, 'RIP': 4299429L, 'RBP': 0L}, 'memory': {4299429L: '\x83', 4299430L: '\xea', 4299431L: '0'}}, 'text': '\x83\xea0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345861L, 'RSI': 4294967294L, 'RDI': 1L, 'EDX': 1L, 'RAX': 48L, 'RSP': 140737488345728L, 'RDX': 1L, 'RIP': 4299432L, 'RBP': 0L}, 'memory': {4299429L: '\x83', 4299430L: '\xea', 4299431L: '0'}}, 'disassembly': 'SUB EDX, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_2(self):
''' Instruction SUB EAX, 0x20 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 100L, 'RFLAGS': 659L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 100L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330547L, 'RBP': 140737488345936L}, 'memory': {4330547L: '\x83', 4330548L: '\xe8', 4330549L: ' '}}, 'text': '\x83\xe8 ', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330547L: '\x83', 4330548L: '\xe8', 4330549L: ' '}}, 'disassembly': 'SUB EAX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_20(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'R13': 0L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4783040L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'R13': 0L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4783040L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_21(self):
''' Instruction SUB EDX, 0x30 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 140737488345864L, 'RSI': 4294967294L, 'RDI': 2L, 'EDX': 53L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 53L, 'RIP': 4299429L, 'RBP': 0L}, 'memory': {4299429L: '\x83', 4299430L: '\xea', 4299431L: '0'}}, 'text': '\x83\xea0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345864L, 'RSI': 4294967294L, 'RDI': 2L, 'EDX': 5L, 'RAX': 45L, 'RSP': 140737488345728L, 'RDX': 5L, 'RIP': 4299432L, 'RBP': 0L}, 'memory': {4299429L: '\x83', 4299430L: '\xea', 4299431L: '0'}}, 'disassembly': 'SUB EDX, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_22(self):
''' Instruction SUB RSP, 0x30 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346224L, 'RDX': 140737488346512L, 'RIP': 4195600L, 'RBP': 140737488346224L}, 'memory': {4195600L: 'H', 4195601L: '\x83', 4195602L: '\xec', 4195603L: '0'}}, 'text': 'H\x83\xec0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4195604L, 'RBP': 140737488346224L}, 'memory': {4195600L: 'H', 4195601L: '\x83', 4195602L: '\xec', 4195603L: '0'}}, 'disassembly': 'SUB RSP, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_23(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_24(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 4782976L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239736L, 'RBP': 4782912L}, 'memory': {4239736L: 'H', 4239737L: ')', 4239738L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 64L, 'RSP': 140737488346120L, 'RDX': 16384L, 'RIP': 4239739L, 'RBP': 4782912L}, 'memory': {4239736L: 'H', 4239737L: ')', 4239738L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_25(self):
''' Instruction SUB RSI, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345640L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327715L, 'RBP': 140737488345936L}, 'memory': {4327715L: 'H', 4327716L: '\x83', 4327717L: '\xee', 4327718L: '\x01'}}, 'text': 'H\x83\xee\x01', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 44L, 'RAX': 44L, 'RSP': 140737488344248L, 'RDX': 10L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327715L: 'H', 4327716L: '\x83', 4327717L: '\xee', 4327718L: '\x01'}}, 'disassembly': 'SUB RSI, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_26(self):
''' Instruction SUB R14, R15 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4L, 'RDI': 4881624L, 'R14': 7035176L, 'R15': 7035168L, 'RSI': 7054976L, 'RIP': 4197712L, 'RSP': 140737488346176L, 'RFLAGS': 514L, 'RAX': 18446744073709551615L}, 'memory': {4197712L: 'M', 4197713L: ')', 4197714L: '\xfe'}}, 'text': 'M)\xfe', 'pos': {'registers': {'RCX': 0L, 'RDX': 0L, 'RBP': 4L, 'RDI': 4881624L, 'R14': 8L, 'R15': 7035168L, 'RSI': 7054976L, 'RIP': 4197715L, 'RSP': 140737488346176L, 'RFLAGS': 514L, 'RAX': 18446744073709551615L}, 'memory': {4197712L: 'M', 4197713L: ')', 4197714L: '\xfe'}}, 'disassembly': 'SUB R14, R15', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_27(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4392467L, 'RBP': 7049504L}, 'memory': {4392467L: 'H', 4392468L: '\x83', 4392469L: '\xec', 4392470L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392471L, 'RBP': 7049504L}, 'memory': {4392467L: 'H', 4392468L: '\x83', 4392469L: '\xec', 4392470L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_28(self):
''' Instruction SUB RDX, [RBP-0x560] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4336566L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xbb', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 4336566L: 'H', 4336567L: '+', 4336568L: '\x95', 4336569L: '\xa0', 4336570L: '\xfa', 4336571L: '\xff', 4336572L: '\xff', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 140737488344563: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 140737488344569: '\x00', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'text': 'H+\x95\xa0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336573L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xbb', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 4336566L: 'H', 4336567L: '+', 4336568L: '\x95', 4336569L: '\xa0', 4336570L: '\xfa', 4336571L: '\xff', 4336572L: '\xff', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 140737488344563: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 140737488344569: '\x00', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'disassembly': 'SUB RDX, [RBP-0x560]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_29(self):
''' Instruction SUB RDX, [RBP-0x538] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 140737488345638L, 'RIP': 4336631L, 'RBP': 140737488345936L}, 'memory': {140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '1', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 4336631L: 'H', 4336632L: '+', 4336633L: '\x95', 4336634L: '\xc8', 4336635L: '\xfa', 4336636L: '\xff', 4336637L: '\xff'}}, 'text': 'H+\x95\xc8\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 18446744073709551614L, 'RIP': 4336638L, 'RBP': 140737488345936L}, 'memory': {140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '1', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 4336631L: 'H', 4336632L: '+', 4336633L: '\x95', 4336634L: '\xc8', 4336635L: '\xfa', 4336636L: '\xff', 4336637L: '\xff'}}, 'disassembly': 'SUB RDX, [RBP-0x538]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_3(self):
''' Instruction SUB RSP, 0xa8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 9L, 'RSI': 4294967295L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344136L, 'RDX': 9L, 'RIP': 4661106L, 'RBP': 4294967295L}, 'memory': {4661106L: 'H', 4661107L: '\x81', 4661108L: '\xec', 4661109L: '\xa8', 4661110L: '\x00', 4661111L: '\x00', 4661112L: '\x00'}}, 'text': 'H\x81\xec\xa8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 9L, 'RSI': 4294967295L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488343968L, 'RDX': 9L, 'RIP': 4661113L, 'RBP': 4294967295L}, 'memory': {4661106L: 'H', 4661107L: '\x81', 4661108L: '\xec', 4661109L: '\xa8', 4661110L: '\x00', 4661111L: '\x00', 4661112L: '\x00'}}, 'disassembly': 'SUB RSP, 0xa8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_30(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'R13': 0L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'R13': 0L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_31(self):
''' Instruction SUB RSP, 0x8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 0L, 'RIP': 4198160L, 'RBP': 0L}, 'memory': {4198160L: 'H', 4198161L: '\x83', 4198162L: '\xec', 4198163L: '\x08'}}, 'text': 'H\x83\xec\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346224L, 'RDX': 0L, 'RIP': 4198164L, 'RBP': 0L}, 'memory': {4198160L: 'H', 4198161L: '\x83', 4198162L: '\xec', 4198163L: '\x08'}}, 'disassembly': 'SUB RSP, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_32(self):
''' Instruction SUB R13, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'R13': 140737354129408L, 'RAX': 0L, 'RSP': 140737488344144L, 'RDX': 9L, 'RIP': 4203485L, 'RBP': 7049504L}, 'memory': {4203485L: 'I', 4203486L: ')', 4203487L: '\xfd'}}, 'text': 'I)\xfd', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 4782888L, 'RDI': 140737354125312L, 'R13': 4096L, 'RAX': 0L, 'RSP': 140737488344144L, 'RDX': 9L, 'RIP': 4203488L, 'RBP': 7049504L}, 'memory': {4203485L: 'I', 4203486L: ')', 4203487L: '\xfd'}}, 'disassembly': 'SUB R13, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_33(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'R13': 78L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354126010L, 'R13': 78L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_34(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'R13': 4L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4782995L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125650L, 'RDI': 140737354125646L, 'R13': 4L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 4782995L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_35(self):
''' Instruction SUB RSP, 0x18 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345912L, 'RDX': 68L, 'RIP': 4320710L, 'RBP': 4792416L}, 'memory': {4320712L: '\xec', 4320713L: '\x18', 4320710L: 'H', 4320711L: '\x83'}}, 'text': 'H\x83\xec\x18', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320714L, 'RBP': 4792416L}, 'memory': {4320712L: '\xec', 4320713L: '\x18', 4320710L: 'H', 4320711L: '\x83'}}, 'disassembly': 'SUB RSP, 0x18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_36(self):
''' Instruction SUB R14, RAX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 530L, 'R14': 4195080L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346216L, 'RDX': 12297829382473034411L, 'RIP': 4197516L, 'RBP': 0L}, 'memory': {4197516L: 'I', 4197517L: ')', 4197518L: '\xc6'}}, 'text': 'I)\xc6', 'pos': {'registers': {'RFLAGS': 514L, 'R14': 288L, 'RCX': 140737488345864L, 'RSI': 4294967293L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346216L, 'RDX': 12297829382473034411L, 'RIP': 4197519L, 'RBP': 0L}, 'memory': {4197516L: 'I', 4197517L: ')', 4197518L: '\xc6'}}, 'disassembly': 'SUB R14, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_37(self):
''' Instruction SUB EAX, 0x20 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 115L, 'RFLAGS': 663L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 115L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330547L, 'RBP': 140737488345936L}, 'memory': {4330547L: '\x83', 4330548L: '\xe8', 4330549L: ' '}}, 'text': '\x83\xe8 ', 'pos': {'registers': {'EAX': 83L, 'RFLAGS': 518L, 'RCX': 115L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'RAX': 83L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330547L: '\x83', 4330548L: '\xe8', 4330549L: ' '}}, 'disassembly': 'SUB EAX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_38(self):
''' Instruction SUB EAX, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329942L, 'RBP': 140737488345936L}, 'memory': {4329944L: '\x01', 4329942L: '\x83', 4329943L: '\xe8'}}, 'text': '\x83\xe8\x01', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329945L, 'RBP': 140737488345936L}, 'memory': {4329944L: '\x01', 4329942L: '\x83', 4329943L: '\xe8'}}, 'disassembly': 'SUB EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_39(self):
''' Instruction SUB RCX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4782997L, 'RSI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248003L: 'H', 4248004L: ')', 4248005L: '\xf9'}}, 'text': 'H)\xf9', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967295L, 'RDI': 4782992L, 'RAX': 2147483643L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4248006L, 'RBP': 140737488345936L}, 'memory': {4248003L: 'H', 4248004L: ')', 4248005L: '\xf9'}}, 'disassembly': 'SUB RCX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_4(self):
''' Instruction SUB RSP, 0x8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346152L, 'RDX': 7058304L, 'RIP': 4197778L, 'RBP': 7049240L}, 'memory': {4197778L: 'H', 4197779L: '\x83', 4197780L: '\xec', 4197781L: '\x08'}}, 'text': 'H\x83\xec\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4197782L, 'RBP': 7049240L}, 'memory': {4197778L: 'H', 4197779L: '\x83', 4197780L: '\xec', 4197781L: '\x08'}}, 'disassembly': 'SUB RSP, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_40(self):
''' Instruction SUB RSP, 0xd8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4L, 'RDI': 4782991L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 4L, 'RIP': 4198752L, 'RBP': 140737488346224L}, 'memory': {4198752L: 'H', 4198753L: '\x81', 4198754L: '\xec', 4198755L: '\xd8', 4198756L: '\x00', 4198757L: '\x00', 4198758L: '\x00'}}, 'text': 'H\x81\xec\xd8\x00\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4L, 'RDI': 4782991L, 'RAX': 0L, 'RSP': 140737488345952L, 'RDX': 4L, 'RIP': 4198759L, 'RBP': 140737488346224L}, 'memory': {4198752L: 'H', 4198753L: '\x81', 4198754L: '\xec', 4198755L: '\xd8', 4198756L: '\x00', 4198757L: '\x00', 4198758L: '\x00'}}, 'disassembly': 'SUB RSP, 0xd8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_41(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'R13': 0L, 'RAX': 12L, 'RSP': 140737488344192L, 'RDX': 4783034L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 32L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'R13': 0L, 'RAX': 12L, 'RSP': 140737488344192L, 'RDX': 4783034L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_42(self):
''' Instruction SUB RSP, 0x28 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7049636L, 'RIP': 4203165L, 'RBP': 0L}, 'memory': {4203168L: '(', 4203165L: 'H', 4203166L: '\x83', 4203167L: '\xec'}}, 'text': 'H\x83\xec(', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 7049635L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346016L, 'RDX': 7049636L, 'RIP': 4203169L, 'RBP': 0L}, 'memory': {4203168L: '(', 4203165L: 'H', 4203166L: '\x83', 4203167L: '\xec'}}, 'disassembly': 'SUB RSP, 0x28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_43(self):
''' Instruction SUB RDX, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 32L, 'RSP': 140737488346176L, 'RDX': 1L, 'RIP': 4197910L, 'RBP': 7049240L}, 'memory': {4197912L: '\xea', 4197913L: '\x01', 4197910L: 'H', 4197911L: '\x83'}}, 'text': 'H\x83\xea\x01', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 7049240L, 'RDI': 0L, 'RAX': 32L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197914L, 'RBP': 7049240L}, 'memory': {4197912L: '\xea', 4197913L: '\x01', 4197910L: 'H', 4197911L: '\x83'}}, 'disassembly': 'SUB RDX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_44(self):
''' Instruction SUB RSP, 0x8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346168L, 'RDX': 140737488346512L, 'RIP': 4195080L, 'RBP': 4L}, 'memory': {4195080L: 'H', 4195081L: '\x83', 4195082L: '\xec', 4195083L: '\x08'}}, 'text': 'H\x83\xec\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346160L, 'RDX': 140737488346512L, 'RIP': 4195084L, 'RBP': 4L}, 'memory': {4195080L: 'H', 4195081L: '\x83', 4195082L: '\xec', 4195083L: '\x08'}}, 'disassembly': 'SUB RSP, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_45(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4205084L, 'RBP': 7054832L}, 'memory': {4205084L: 'H', 4205085L: '\x83', 4205086L: '\xec', 4205087L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205088L, 'RBP': 7054832L}, 'memory': {4205084L: 'H', 4205085L: '\x83', 4205086L: '\xec', 4205087L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_46(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 4782901L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125325L, 'RDI': 140737354125323L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 4782901L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_47(self):
''' Instruction SUB RAX, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 4096L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4222359L, 'RBP': 7051232L}, 'memory': {4222360L: '\x83', 4222361L: '\xe8', 4222362L: '\x01', 4222359L: 'H'}}, 'text': 'H\x83\xe8\x01', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 7053544L, 'RSI': 24L, 'RDI': 7051232L, 'RAX': 4095L, 'RSP': 140737488345824L, 'RDX': 3L, 'RIP': 4222363L, 'RBP': 7051232L}, 'memory': {4222360L: '\x83', 4222361L: '\xe8', 4222362L: '\x01', 4222359L: 'H'}}, 'disassembly': 'SUB RAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_48(self):
''' Instruction SUB RSI, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 2L, 'RAX': 2L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327715L, 'RBP': 140737488345936L}, 'memory': {4327715L: 'H', 4327716L: '\x83', 4327717L: '\xee', 4327718L: '\x01'}}, 'text': 'H\x83\xee\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'RAX': 2L, 'RSP': 140737488344248L, 'RDX': 2L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327715L: 'H', 4327716L: '\x83', 4327717L: '\xee', 4327718L: '\x01'}}, 'disassembly': 'SUB RSI, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_49(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'R13': 0L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'R13': 0L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_5(self):
''' Instruction SUB EDX, EAX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 4795872L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'RIP': 4336688L, 'EAX': 0L, 'EDX': 4294967295L, 'RSP': 140737488344256L, 'RFLAGS': 646L, 'RAX': 0L}, 'memory': {4336688L: ')', 4336689L: '\xc2'}}, 'text': ')\xc2', 'pos': {'registers': {'RCX': 4795872L, 'RDX': 4294967295L, 'RBP': 140737488345936L, 'RDI': 0L, 'RSI': 140737488345639L, 'RIP': 4336690L, 'EAX': 0L, 'EDX': 4294967295L, 'RSP': 140737488344256L, 'RFLAGS': 646L, 'RAX': 0L}, 'memory': {4336688L: ')', 4336689L: '\xc2'}}, 'disassembly': 'SUB EDX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_50(self):
''' Instruction SUB RSP, 0x28 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 1600L, 'RAX': 7378697629483820663L, 'RSP': 140737488346072L, 'RDX': 2L, 'RIP': 4230055L, 'RBP': 140737488346112L}, 'memory': {4230056L: '\x83', 4230057L: '\xec', 4230058L: '(', 4230055L: 'H'}}, 'text': 'H\x83\xec(', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7074240L, 'RSI': 7074272L, 'RDI': 1600L, 'RAX': 7378697629483820663L, 'RSP': 140737488346032L, 'RDX': 2L, 'RIP': 4230059L, 'RBP': 140737488346112L}, 'memory': {4230056L: '\x83', 4230057L: '\xec', 4230058L: '(', 4230055L: 'H'}}, 'disassembly': 'SUB RSP, 0x28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_51(self):
''' Instruction SUB RDI, RAX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327733L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'text': 'H)\xc7', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327736L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'disassembly': 'SUB RDI, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_52(self):
''' Instruction SUB RSP, 0x28 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346168L, 'RDX': 79L, 'RIP': 4198951L, 'RBP': 4782912L}, 'memory': {4198952L: '\x83', 4198953L: '\xec', 4198954L: '(', 4198951L: 'H'}}, 'text': 'H\x83\xec(', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4198955L, 'RBP': 4782912L}, 'memory': {4198952L: '\x83', 4198953L: '\xec', 4198954L: '(', 4198951L: 'H'}}, 'disassembly': 'SUB RSP, 0x28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_53(self):
''' Instruction SUB RSI, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327715L, 'RBP': 140737488345936L}, 'memory': {4327715L: 'H', 4327716L: '\x83', 4327717L: '\xee', 4327718L: '\x01'}}, 'text': 'H\x83\xee\x01', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 4L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327719L, 'RBP': 140737488345936L}, 'memory': {4327715L: 'H', 4327716L: '\x83', 4327717L: '\xee', 4327718L: '\x01'}}, 'disassembly': 'SUB RSI, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_54(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392467L, 'RBP': 7049504L}, 'memory': {4392467L: 'H', 4392468L: '\x83', 4392469L: '\xec', 4392470L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392471L, 'RBP': 7049504L}, 'memory': {4392467L: 'H', 4392468L: '\x83', 4392469L: '\xec', 4392470L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_55(self):
''' Instruction SUB RAX, 0x3 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347040L, 'RAX': 3L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'text': 'H\x83\xe8\x03', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347040L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'disassembly': 'SUB RAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_56(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'R13': 78L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125773L, 'R13': 78L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_57(self):
''' Instruction SUB RAX, 0x3 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347088L, 'RAX': 7L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'text': 'H\x83\xe8\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347088L, 'RAX': 4L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'disassembly': 'SUB RAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_58(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125408L, 'R13': 78L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125408L, 'R13': 78L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_59(self):
''' Instruction SUB RCX, [RBP-0x560] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345640L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336910L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xad', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344563: '\xff', 4336910L: 'H', 140737488344569: '\x00', 4336911L: '+', 4336912L: '\x8d', 4336913L: '\xa0', 4336914L: '\xfa', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 4336915L: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 4336916L: '\xff', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'text': 'H+\x8d\xa0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336917L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xad', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344563: '\xff', 4336910L: 'H', 140737488344569: '\x00', 4336911L: '+', 4336912L: '\x8d', 4336913L: '\xa0', 4336914L: '\xfa', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 4336915L: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 4336916L: '\xff', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'disassembly': 'SUB RCX, [RBP-0x560]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_6(self):
''' Instruction SUB RAX, RDX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 1L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 2147483647L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4337019L, 'RBP': 140737488345936L}, 'memory': {4337019L: 'H', 4337020L: ')', 4337021L: '\xd0'}}, 'text': 'H)\xd0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'RAX': 2147483643L, 'RSP': 140737488344256L, 'RDX': 4L, 'RIP': 4337022L, 'RBP': 140737488345936L}, 'memory': {4337019L: 'H', 4337020L: ')', 4337021L: '\xd0'}}, 'disassembly': 'SUB RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_60(self):
''' Instruction SUB EAX, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 1L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199145L, 'RBP': 4782912L}, 'memory': {4199145L: '\x83', 4199146L: '\xe8', 4199147L: '\x01'}}, 'text': '\x83\xe8\x01', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199148L, 'RBP': 4782912L}, 'memory': {4199145L: '\x83', 4199146L: '\xe8', 4199147L: '\x01'}}, 'disassembly': 'SUB EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_61(self):
''' Instruction SUB RBX, RBP '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 7035184L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4197796L, 'RBP': 7035176L}, 'memory': {4197796L: 'H', 4197797L: ')', 4197798L: '\xeb'}}, 'text': 'H)\xeb', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 7058320L, 'RSI': 0L, 'RBX': 8L, 'RDI': 0L, 'RAX': 4197776L, 'RSP': 140737488346144L, 'RDX': 7058304L, 'RIP': 4197799L, 'RBP': 7035176L}, 'memory': {4197796L: 'H', 4197797L: ')', 4197798L: '\xeb'}}, 'disassembly': 'SUB RBX, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_62(self):
''' Instruction SUB RCX, [RBP-0x560] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 140737488345640L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336910L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xc1', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344563: '\xff', 4336910L: 'H', 140737488344569: '\x00', 4336911L: '+', 4336912L: '\x8d', 4336913L: '\xa0', 4336914L: '\xfa', 140737488344560: '&', 140737488344561: '\xda', 140737488344562: '\xff', 4336915L: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 4336916L: '\xff', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'text': 'H+\x8d\xa0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336917L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xc1', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344563: '\xff', 4336910L: 'H', 140737488344569: '\x00', 4336911L: '+', 4336912L: '\x8d', 4336913L: '\xa0', 4336914L: '\xfa', 140737488344560: '&', 140737488344561: '\xda', 140737488344562: '\xff', 4336915L: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 4336916L: '\xff', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'disassembly': 'SUB RCX, [RBP-0x560]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_63(self):
''' Instruction SUB EAX, 0x20 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 100L, 'RFLAGS': 659L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 100L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330547L, 'RBP': 140737488345936L}, 'memory': {4330547L: '\x83', 4330548L: '\xe8', 4330549L: ' '}}, 'text': '\x83\xe8 ', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330550L, 'RBP': 140737488345936L}, 'memory': {4330547L: '\x83', 4330548L: '\xe8', 4330549L: ' '}}, 'disassembly': 'SUB EAX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_64(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 52L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'R13': 1L, 'RAX': 1L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 52L, 'RSI': 140737354125651L, 'RDI': 140737354125650L, 'R13': 1L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_65(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_66(self):
''' Instruction SUB RSP, 0x30 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346128L, 'RDX': 7058304L, 'RIP': 4704452L, 'RBP': 7035176L}, 'memory': {4704452L: 'H', 4704453L: '\x83', 4704454L: '\xec', 4704455L: '0'}}, 'text': 'H\x83\xec0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 7064352L, 'RAX': 4197776L, 'RSP': 140737488346080L, 'RDX': 7058304L, 'RIP': 4704456L, 'RBP': 7035176L}, 'memory': {4704452L: 'H', 4704453L: '\x83', 4704454L: '\xec', 4704455L: '0'}}, 'disassembly': 'SUB RSP, 0x30', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_67(self):
''' Instruction SUB R8, R10 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 4350L, 'R8': 4783009L, 'RDX': 1L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4782997L, 'R10': 4782997L, 'RIP': 4336258L, 'RSP': 140737488344256L, 'RFLAGS': 518L, 'RAX': 7041664L}, 'memory': {4336258L: 'M', 4336259L: ')', 4336260L: '\xd0'}}, 'text': 'M)\xd0', 'pos': {'registers': {'RCX': 4350L, 'R8': 12L, 'RDX': 1L, 'RBP': 140737488345936L, 'RDI': 4783024L, 'RSI': 4782997L, 'R10': 4782997L, 'RIP': 4336261L, 'RSP': 140737488344256L, 'RFLAGS': 534L, 'RAX': 7041664L}, 'memory': {4336258L: 'M', 4336259L: ')', 4336260L: '\xd0'}}, 'disassembly': 'SUB R8, R10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_68(self):
''' Instruction SUB RSP, 0x8 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4779557L, 'RBP': 140737488346144L}, 'memory': {4779560L: '\x08', 4779557L: 'H', 4779558L: '\x83', 4779559L: '\xec'}}, 'text': 'H\x83\xec\x08', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4779561L, 'RBP': 140737488346144L}, 'memory': {4779560L: '\x08', 4779557L: 'H', 4779558L: '\x83', 4779559L: '\xec'}}, 'disassembly': 'SUB RSP, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_69(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7065432L, 'RSP': 140737488346120L, 'RDX': 7074288L, 'RIP': 4322385L, 'RBP': 140737488346472L}, 'memory': {4322385L: 'H', 4322386L: '\x83', 4322387L: '\xec', 4322388L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7065432L, 'RSP': 140737488346064L, 'RDX': 7074288L, 'RIP': 4322389L, 'RBP': 140737488346472L}, 'memory': {4322385L: 'H', 4322386L: '\x83', 4322387L: '\xec', 4322388L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_7(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125931L, 'R13': 78L, 'RAX': 78L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392725L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125931L, 'R13': 78L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392728L, 'RBP': 7049504L}, 'memory': {4392725L: 'L', 4392726L: ')', 4392727L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_70(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 140737354129408L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_71(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392467L, 'RBP': 7049504L}, 'memory': {4392467L: 'H', 4392468L: '\x83', 4392469L: '\xec', 4392470L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392471L, 'RBP': 7049504L}, 'memory': {4392467L: 'H', 4392468L: '\x83', 4392469L: '\xec', 4392470L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_72(self):
''' Instruction SUB R8, R10 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 1024L, 'R8': 4783034L, 'RDX': 10L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4783022L, 'R10': 4783022L, 'RIP': 4336258L, 'RSP': 140737488344256L, 'RFLAGS': 518L, 'RAX': 7041664L}, 'memory': {4336258L: 'M', 4336259L: ')', 4336260L: '\xd0'}}, 'text': 'M)\xd0', 'pos': {'registers': {'RCX': 1024L, 'R8': 12L, 'RDX': 10L, 'RBP': 140737488345936L, 'RDI': 4783040L, 'RSI': 4783022L, 'R10': 4783022L, 'RIP': 4336261L, 'RSP': 140737488344256L, 'RFLAGS': 534L, 'RAX': 7041664L}, 'memory': {4336258L: 'M', 4336259L: ')', 4336260L: '\xd0'}}, 'disassembly': 'SUB R8, R10', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_73(self):
''' Instruction SUB RSP, 0x18 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346088L, 'RDX': 0L, 'RIP': 4203842L, 'RBP': 1L}, 'memory': {4203842L: 'H', 4203843L: '\x83', 4203844L: '\xec', 4203845L: '\x18'}}, 'text': 'H\x83\xec\x18', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4203846L, 'RBP': 1L}, 'memory': {4203842L: 'H', 4203843L: '\x83', 4203844L: '\xec', 4203845L: '\x18'}}, 'disassembly': 'SUB RSP, 0x18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_74(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_75(self):
''' Instruction SUB RAX, 0x3 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347232L, 'RAX': 1L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'text': 'H\x83\xe8\x03', 'pos': {'registers': {'RFLAGS': 659L, 'RCX': 4294967295L, 'RSI': 0L, 'RDI': 140737488347232L, 'RAX': 18446744073709551614L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'disassembly': 'SUB RAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_76(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'R13': 0L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 32L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'R13': 0L, 'RAX': 4L, 'RSP': 140737488344192L, 'RDX': 4783046L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_77(self):
''' Instruction SUB RAX, RBX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782897L, 'RSI': 4782888L, 'RBX': 0L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344144L, 'RDX': 32L, 'RIP': 4203619L, 'RBP': 7049504L}, 'memory': {4203619L: 'H', 4203620L: ')', 4203621L: '\xd8'}}, 'text': 'H)\xd8', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4782897L, 'RSI': 4782888L, 'RBX': 0L, 'RDI': 140737354125321L, 'RAX': 9L, 'RSP': 140737488344144L, 'RDX': 32L, 'RIP': 4203622L, 'RBP': 7049504L}, 'memory': {4203619L: 'H', 4203620L: ')', 4203621L: '\xd8'}}, 'disassembly': 'SUB RAX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_78(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4322385L, 'RBP': 140737488346472L}, 'memory': {4322385L: 'H', 4322386L: '\x83', 4322387L: '\xec', 4322388L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4322389L, 'RBP': 140737488346472L}, 'memory': {4322385L: 'H', 4322386L: '\x83', 4322387L: '\xec', 4322388L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_79(self):
''' Instruction SUB RDX, [RBP-0x560] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4336566L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\x94', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\x93', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 4336566L: 'H', 4336567L: '+', 4336568L: '\x95', 4336569L: '\xa0', 4336570L: '\xfa', 4336571L: '\xff', 4336572L: '\xff', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 140737488344563: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 140737488344569: '\x00', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'text': 'H+\x95\xa0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 1L, 'RIP': 4336573L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\x94', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\x93', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 4336566L: 'H', 4336567L: '+', 4336568L: '\x95', 4336569L: '\xa0', 4336570L: '\xfa', 4336571L: '\xff', 4336572L: '\xff', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 140737488344563: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 140737488344569: '\x00', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'disassembly': 'SUB RDX, [RBP-0x560]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_8(self):
''' Instruction SUB R13D, EBP '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RCX': 63L, 'RDX': 1L, 'RBP': 3L, 'RDI': 4L, 'RSI': 29360191L, 'RIP': 4284142L, 'R13D': 3L, 'EBP': 3L, 'RSP': 140737488345968L, 'RFLAGS': 518L, 'RAX': 1L}, 'memory': {4284144L: '\xed', 4284142L: 'A', 4284143L: ')'}}, 'text': 'A)\xed', 'pos': {'registers': {'RCX': 63L, 'RDX': 1L, 'RBP': 3L, 'RDI': 4L, 'RSI': 29360191L, 'RIP': 4284145L, 'R13D': 0L, 'EBP': 3L, 'RSP': 140737488345968L, 'RFLAGS': 582L, 'RAX': 1L}, 'memory': {4284144L: '\xed', 4284142L: 'A', 4284143L: ')'}}, 'disassembly': 'SUB R13D, EBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_80(self):
''' Instruction SUB RAX, 0x3 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'text': 'H\x83\xe8\x03', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 11L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'disassembly': 'SUB RAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_81(self):
''' Instruction SUB RAX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125650L, 'RAX': 140737354129408L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392624L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'text': 'H)\xf8', 'pos': {'registers': {'RFLAGS': 530L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125650L, 'RAX': 3758L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392624L: 'H', 4392625L: ')', 4392626L: '\xf8'}}, 'disassembly': 'SUB RAX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_82(self):
''' Instruction SUB RDI, RAX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 44L, 'RAX': 40L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327733L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'text': 'H)\xc7', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 4L, 'RAX': 40L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4327736L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'disassembly': 'SUB RDI, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_83(self):
''' Instruction SUB RCX, [RBP-0x560] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737488345640L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336910L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xbb', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344563: '\xff', 4336910L: 'H', 140737488344569: '\x00', 4336911L: '+', 4336912L: '\x8d', 4336913L: '\xa0', 4336914L: '\xfa', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 4336915L: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 4336916L: '\xff', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'text': 'H+\x8d\xa0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336917L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xbb', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344563: '\xff', 4336910L: 'H', 140737488344569: '\x00', 4336911L: '+', 4336912L: '\x8d', 4336913L: '\xa0', 4336914L: '\xfa', 140737488344560: "'", 140737488344561: '\xda', 140737488344562: '\xff', 4336915L: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 4336916L: '\xff', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'disassembly': 'SUB RCX, [RBP-0x560]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_84(self):
''' Instruction SUB EAX, 0x20 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 100L, 'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 100L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330350L, 'RBP': 140737488345936L}, 'memory': {4330352L: ' ', 4330350L: '\x83', 4330351L: '\xe8'}}, 'text': '\x83\xe8 ', 'pos': {'registers': {'EAX': 68L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 68L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4330353L, 'RBP': 140737488345936L}, 'memory': {4330352L: ' ', 4330350L: '\x83', 4330351L: '\xe8'}}, 'disassembly': 'SUB EAX, 0x20', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_85(self):
''' Instruction SUB RAX, RDX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2147483647L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4337019L, 'RBP': 140737488345936L}, 'memory': {4337019L: 'H', 4337020L: ')', 4337021L: '\xd0'}}, 'text': 'H)\xd0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 2L, 'RSI': 140737354125323L, 'RDI': 140737354125321L, 'RAX': 2147483638L, 'RSP': 140737488344256L, 'RDX': 9L, 'RIP': 4337022L, 'RBP': 140737488345936L}, 'memory': {4337019L: 'H', 4337020L: ')', 4337021L: '\xd0'}}, 'disassembly': 'SUB RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_86(self):
''' Instruction SUB RSP, 0x38 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7065280L, 'RIP': 4322385L, 'RBP': 140737488346472L}, 'memory': {4322385L: 'H', 4322386L: '\x83', 4322387L: '\xec', 4322388L: '8'}}, 'text': 'H\x83\xec8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7065280L, 'RIP': 4322389L, 'RBP': 140737488346472L}, 'memory': {4322385L: 'H', 4322386L: '\x83', 4322387L: '\xec', 4322388L: '8'}}, 'disassembly': 'SUB RSP, 0x38', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_87(self):
''' Instruction SUB RDI, RAX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327733L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'text': 'H)\xc7', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 2L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327736L, 'RBP': 140737488345936L}, 'memory': {4327733L: 'H', 4327734L: ')', 4327735L: '\xc7'}}, 'disassembly': 'SUB RDI, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_88(self):
''' Instruction SUB RDX, [RBP-0x538] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 140737488345639L, 'RIP': 4336631L, 'RBP': 140737488345936L}, 'memory': {140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 4336631L: 'H', 4336632L: '+', 4336633L: '\x95', 4336634L: '\xc8', 4336635L: '\xfa', 4336636L: '\xff', 4336637L: '\xff'}}, 'text': 'H+\x95\xc8\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 663L, 'RCX': 4795872L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 18446744073709551615L, 'RIP': 4336638L, 'RBP': 140737488345936L}, 'memory': {140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 140737488344624: '\x00', 140737488344625: '\x00', 140737488344626: '\x00', 140737488344627: '\x00', 140737488344628: '\x00', 140737488344629: '\x00', 140737488344630: '\x00', 140737488344631: '\x00', 140737488344632: '\x00', 140737488344633: '\x00', 140737488344634: '\x00', 140737488344635: '\x00', 140737488344636: '\x00', 140737488344637: '\x00', 140737488344638: '\x00', 140737488344639: '\x00', 140737488344640: '\x00', 140737488344641: '\x00', 140737488344642: '\x00', 140737488344643: '\x00', 140737488344644: '\x00', 140737488344645: '\x00', 140737488344646: '\x00', 140737488344647: '\x00', 140737488344648: '\x00', 140737488344649: '\x00', 140737488344650: '\x00', 140737488344651: '\x00', 140737488344652: '\x00', 140737488344653: '\x00', 140737488344654: '\x00', 140737488344655: '\x00', 140737488344656: '\x00', 140737488344657: '\x00', 140737488344658: '\x00', 140737488344659: '\x00', 140737488344660: '\x00', 140737488344661: '\x00', 140737488344662: '\x00', 140737488344663: '\x00', 4336631L: 'H', 4336632L: '+', 4336633L: '\x95', 4336634L: '\xc8', 4336635L: '\xfa', 4336636L: '\xff', 4336637L: '\xff'}}, 'disassembly': 'SUB RDX, [RBP-0x538]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_89(self):
''' Instruction SUB RAX, RDX '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4783046L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 2147483647L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338839L, 'RBP': 140737488345936L}, 'memory': {4338840L: ')', 4338841L: '\xd0', 4338839L: 'H'}}, 'text': 'H)\xd0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4783046L, 'RSI': 140737354125691L, 'RDI': 140737354125687L, 'RAX': 2147483623L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338842L, 'RBP': 140737488345936L}, 'memory': {4338840L: ')', 4338841L: '\xd0', 4338839L: 'H'}}, 'disassembly': 'SUB RAX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_9(self):
''' Instruction SUB RSP, 0x690 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488345936L, 'RDX': 140737488345952L, 'RIP': 4329550L, 'RBP': 140737488345936L}, 'memory': {4329550L: 'H', 4329551L: '\x81', 4329552L: '\xec', 4329553L: '\x90', 4329554L: '\x06', 4329555L: '\x00', 4329556L: '\x00'}}, 'text': 'H\x81\xec\x90\x06\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 7059408L, 'RSI': 4782991L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329557L, 'RBP': 140737488345936L}, 'memory': {4329550L: 'H', 4329551L: '\x81', 4329552L: '\xec', 4329553L: '\x90', 4329554L: '\x06', 4329555L: '\x00', 4329556L: '\x00'}}, 'disassembly': 'SUB RSP, 0x690', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_90(self):
''' Instruction SUB RAX, 0x3 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 13L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'text': 'H\x83\xe8\x03', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 10L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'disassembly': 'SUB RAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_91(self):
''' Instruction SUB RSP, 0x18 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488345992L, 'RDX': 140737488346078L, 'RIP': 4283781L, 'RBP': 188L}, 'memory': {4283784L: '\x18', 4283781L: 'H', 4283782L: '\x83', 4283783L: '\xec'}}, 'text': 'H\x83\xec\x18', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 140737488346079L, 'RSI': 1979931136L, 'RDI': 188L, 'RAX': 1979931136L, 'RSP': 140737488345968L, 'RDX': 140737488346078L, 'RIP': 4283785L, 'RBP': 188L}, 'memory': {4283784L: '\x18', 4283781L: 'H', 4283782L: '\x83', 4283783L: '\xec'}}, 'disassembly': 'SUB RSP, 0x18', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_92(self):
''' Instruction SUB RDX, [RBP-0x560] '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 140737488345640L, 'RIP': 4336566L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xc1', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 4336566L: 'H', 4336567L: '+', 4336568L: '\x95', 4336569L: '\xa0', 4336570L: '\xfa', 4336571L: '\xff', 4336572L: '\xff', 140737488344560: '&', 140737488344561: '\xda', 140737488344562: '\xff', 140737488344563: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 140737488344569: '\x00', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'text': 'H+\x95\xa0\xfa\xff\xff', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 2L, 'RIP': 4336573L, 'RBP': 140737488345936L}, 'memory': {140737488344576: '\xc1', 140737488344577: '\xfb', 140737488344578: 'H', 140737488344579: '\x00', 140737488344580: '\x00', 140737488344581: '\x00', 140737488344582: '\x00', 140737488344583: '\x00', 140737488344584: 'd', 140737488344585: '\x00', 140737488344586: '\x00', 140737488344587: '\x00', 140737488344588: '\x00', 140737488344589: '\x00', 140737488344590: '\x00', 140737488344591: '\x00', 140737488344592: '\x00', 140737488344593: '\x00', 140737488344594: '\x00', 140737488344595: '\x00', 140737488344596: '\x00', 140737488344597: '\x00', 140737488344598: '\x00', 140737488344599: '\x00', 140737488344600: '(', 140737488344601: '\xda', 140737488344602: '\xff', 140737488344603: '\xff', 140737488344604: '\xff', 140737488344605: '\x7f', 140737488344606: '\x00', 140737488344607: '\x00', 140737488344608: '\xac', 140737488344609: '\xfb', 140737488344610: 'H', 140737488344611: '\x00', 140737488344612: '\x00', 140737488344613: '\x00', 140737488344614: '\x00', 140737488344615: '\x00', 140737488344616: '\x00', 140737488344617: '\x00', 140737488344618: '\x00', 140737488344619: '\x00', 140737488344620: '\x00', 140737488344621: '\x00', 140737488344622: '\x00', 140737488344623: '\x00', 4336566L: 'H', 4336567L: '+', 4336568L: '\x95', 4336569L: '\xa0', 4336570L: '\xfa', 4336571L: '\xff', 4336572L: '\xff', 140737488344560: '&', 140737488344561: '\xda', 140737488344562: '\xff', 140737488344563: '\xff', 140737488344564: '\xff', 140737488344565: '\x7f', 140737488344566: '\x00', 140737488344567: '\x00', 140737488344568: '\x00', 140737488344569: '\x00', 140737488344570: '\x00', 140737488344571: '\x00', 140737488344572: '\x00', 140737488344573: '\x00', 140737488344574: '\x00', 140737488344575: '\x00'}}, 'disassembly': 'SUB RDX, [RBP-0x560]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_93(self):
''' Instruction SUB RSP, 0x28 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 531L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 140737354125312L, 'RSP': 140737488343960L, 'RDX': 140737354129408L, 'RIP': 4203165L, 'RBP': 4096L}, 'memory': {4203168L: '(', 4203165L: 'H', 4203166L: '\x83', 4203167L: '\xec'}}, 'text': 'H\x83\xec(', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 140737354125312L, 'RSP': 140737488343920L, 'RDX': 140737354129408L, 'RIP': 4203169L, 'RBP': 4096L}, 'memory': {4203168L: '(', 4203165L: 'H', 4203166L: '\x83', 4203167L: '\xec'}}, 'disassembly': 'SUB RSP, 0x28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_94(self):
''' Instruction SUB RAX, R13 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 10L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 4783050L, 'RIP': 4392746L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'text': 'L)\xe8', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 10L, 'RSI': 140737354125695L, 'RDI': 140737354125693L, 'R13': 0L, 'RAX': 2L, 'RSP': 140737488344192L, 'RDX': 4783050L, 'RIP': 4392749L, 'RBP': 7049504L}, 'memory': {4392746L: 'L', 4392747L: ')', 4392748L: '\xe8'}}, 'disassembly': 'SUB RAX, R13', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_95(self):
''' Instruction SUB RAX, 0x3 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 33L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296944L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'text': 'H\x83\xe8\x03', 'pos': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488346976L, 'RAX': 30L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296948L, 'RBP': 0L}, 'memory': {4296944L: 'H', 4296945L: '\x83', 4296946L: '\xe8', 4296947L: '\x03'}}, 'disassembly': 'SUB RAX, 0x3', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_96(self):
''' Instruction SUB EAX, 0x1 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 1L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329942L, 'RBP': 140737488345936L}, 'memory': {4329944L: '\x01', 4329942L: '\x83', 4329943L: '\xe8'}}, 'text': '\x83\xe8\x01', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329945L, 'RBP': 140737488345936L}, 'memory': {4329944L: '\x01', 4329942L: '\x83', 4329943L: '\xe8'}}, 'disassembly': 'SUB EAX, 0x1', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_97(self):
''' Instruction SUB RSP, 0x690 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488345936L, 'RDX': 140737488345952L, 'RIP': 4329550L, 'RBP': 140737488345936L}, 'memory': {4329550L: 'H', 4329551L: '\x81', 4329552L: '\xec', 4329553L: '\x90', 4329554L: '\x06', 4329555L: '\x00', 4329556L: '\x00'}}, 'text': 'H\x81\xec\x90\x06\x00\x00', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 4782888L, 'RDI': 7049504L, 'RAX': 7051024L, 'RSP': 140737488344256L, 'RDX': 140737488345952L, 'RIP': 4329557L, 'RBP': 140737488345936L}, 'memory': {4329550L: 'H', 4329551L: '\x81', 4329552L: '\xec', 4329553L: '\x90', 4329554L: '\x06', 4329555L: '\x00', 4329556L: '\x00'}}, 'disassembly': 'SUB RSP, 0x690', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_98(self):
''' Instruction SUB RCX, RDI '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4783036L, 'RSI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4248003L, 'RBP': 140737488345936L}, 'memory': {4248003L: 'H', 4248004L: ')', 4248005L: '\xf9'}}, 'text': 'H)\xf9', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 12L, 'RSI': 4294967295L, 'RDI': 4783024L, 'RAX': 2147483630L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4248006L, 'RBP': 140737488345936L}, 'memory': {4248003L: 'H', 4248004L: ')', 4248005L: '\xf9'}}, 'disassembly': 'SUB RCX, RDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testSUB_99(self):
''' Instruction SUB RSP, 0x28 '''
test = {'mnemonic': 'SUB', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 0L, 'RSP': 140737488346072L, 'RDX': 7065872L, 'RIP': 4230055L, 'RBP': 140737488346112L}, 'memory': {4230056L: '\x83', 4230057L: '\xec', 4230058L: '(', 4230055L: 'H'}}, 'text': 'H\x83\xec(', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 0L, 'RSP': 140737488346032L, 'RDX': 7065872L, 'RIP': 4230059L, 'RBP': 140737488346112L}, 'memory': {4230056L: '\x83', 4230057L: '\xec', 4230058L: '(', 4230055L: 'H'}}, 'disassembly': 'SUB RSP, 0x28', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8d5, test['pos']['registers'][reg_name]&0x8d5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_1(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350653L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350653L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_10(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488350606L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488350606L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_100(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488347766L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488347766L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_101(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322537L, 'RBP': 140737488350163L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488350163L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_11(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488349535L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488349535L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_12(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346385L, 'RDI': 7L, 'RAX': 9904341620251518720L, 'RSP': 140737488346240L, 'RDX': 7L, 'RIP': 4196099L, 'RBP': 0L}, 'memory': {4196099L: 'H', 4196100L: '\x85', 4196101L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737488346385L, 'RDI': 7L, 'RAX': 9904341620251518720L, 'RSP': 140737488346240L, 'RDX': 7L, 'RIP': 4196102L, 'RBP': 0L}, 'memory': {4196099L: 'H', 4196100L: '\x85', 4196101L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_13(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231354L, 'RBP': 140737488345936L}, 'memory': {4231354L: 'H', 4231355L: '\x85', 4231356L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231357L, 'RBP': 140737488345936L}, 'memory': {4231354L: 'H', 4231355L: '\x85', 4231356L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_14(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488350976L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488350976L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_15(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488349988L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488349988L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_16(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488347948L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488347948L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_17(self):
''' Instruction TEST EAX, EAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4284812L, 'RBP': 4L}, 'memory': {4284812L: '\x85', 4284813L: '\xc0'}}, 'text': '\x85\xc0', 'pos': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 0L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 1L, 'RSP': 140737488346144L, 'RDX': 140737488346512L, 'RIP': 4284814L, 'RBP': 4L}, 'memory': {4284812L: '\x85', 4284813L: '\xc0'}}, 'disassembly': 'TEST EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_18(self):
''' Instruction TEST BYTE [RIP+0x2b24d6], 0x2 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223751L, 'RBP': 7051232L}, 'memory': {4223751L: '\xf6', 4223752L: '\x05', 4223753L: '\xd6', 4223754L: '$', 4223755L: '+', 4223756L: '\x00', 4223757L: '\x02', 7051229: '\x00', 7051230: '\x00', 7051231: '\x00', 7051232: '\x01', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01'}}, 'text': '\xf6\x05\xd6$+\x00\x02', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223758L, 'RBP': 7051232L}, 'memory': {4223751L: '\xf6', 4223752L: '\x05', 4223753L: '\xd6', 4223754L: '$', 4223755L: '+', 4223756L: '\x00', 4223757L: '\x02', 7051229: '\x00', 7051230: '\x00', 7051231: '\x00', 7051232: '\x01', 7051233: '\x00', 7051234: '\x00', 7051235: '\x00', 7051236: '\x01'}}, 'disassembly': 'TEST BYTE [RIP+0x2b24d6], 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_19(self):
''' Instruction TEST RDX, RDX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197900L, 'RBP': 7049240L}, 'memory': {4197900L: 'H', 4197901L: '\x85', 4197902L: '\xd2'}}, 'text': 'H\x85\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058320L, 'RSI': 0L, 'RDI': 4881624L, 'RAX': 0L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4197903L, 'RBP': 7049240L}, 'memory': {4197900L: 'H', 4197901L: '\x85', 4197902L: '\xd2'}}, 'disassembly': 'TEST RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_2(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231354L, 'RBP': 140737488345936L}, 'memory': {4231354L: 'H', 4231355L: '\x85', 4231356L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 17L, 'RIP': 4231357L, 'RBP': 140737488345936L}, 'memory': {4231354L: 'H', 4231355L: '\x85', 4231356L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_20(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488350606L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350606L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_21(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488348069L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488348069L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_22(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488348069L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488348069L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_23(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488350562L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350562L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_24(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346608L, 'RAX': 140737488347948L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346608L, 'RAX': 140737488347948L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_25(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346048L, 'RDX': 64L, 'RIP': 4284530L, 'RBP': 188L}, 'memory': {4284530L: 'H', 4284531L: '\x85', 4284532L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 64L, 'RSI': 1L, 'RDI': 4L, 'RAX': 32768L, 'RSP': 140737488346048L, 'RDX': 64L, 'RIP': 4284533L, 'RBP': 188L}, 'memory': {4284530L: 'H', 4284531L: '\x85', 4284532L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_26(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350223L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350223L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_27(self):
''' Instruction TEST R8D, R8D '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336768L, 'RBP': 140737488345936L}, 'memory': {4336768L: 'E', 4336769L: '\x85', 4336770L: '\xc0'}}, 'text': 'E\x85\xc0', 'pos': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336771L, 'RBP': 140737488345936L}, 'memory': {4336768L: 'E', 4336769L: '\x85', 4336770L: '\xc0'}}, 'disassembly': 'TEST R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_28(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350989L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350989L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_29(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346816L, 'RAX': 140737488350473L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346816L, 'RAX': 140737488350473L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_3(self):
''' Instruction TEST DI, DI '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'DI': 0L, 'RDI': 0L, 'RAX': 699L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392352L, 'RBP': 699L}, 'memory': {4392352L: 'f', 4392353L: '\x85', 4392354L: '\xff'}}, 'text': 'f\x85\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 140737354125312L, 'DI': 0L, 'RDI': 0L, 'RAX': 699L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392355L, 'RBP': 699L}, 'memory': {4392352L: 'f', 4392353L: '\x85', 4392354L: '\xff'}}, 'disassembly': 'TEST DI, DI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_30(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488347960L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488347960L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_31(self):
''' Instruction TEST EAX, EAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199148L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'text': '\x85\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199150L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'disassembly': 'TEST EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_32(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350429L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350429L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_33(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297262L, 'RBP': 0L}, 'memory': {4297264L: '\xc0', 4297262L: 'H', 4297263L: '\x85'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 7L, 'RSI': 0L, 'RDI': 140737488347184L, 'RAX': 14L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297265L, 'RBP': 0L}, 'memory': {4297264L: '\xc0', 4297262L: 'H', 4297263L: '\x85'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_34(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4336422L, 'RBP': 140737488345936L}, 'memory': {4336424L: '\xc0', 4336422L: 'H', 4336423L: '\x85'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4336425L, 'RBP': 140737488345936L}, 'memory': {4336424L: '\xc0', 4336422L: 'H', 4336423L: '\x85'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_35(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488350830L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488350830L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_36(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488350381L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350381L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_37(self):
''' Instruction TEST EAX, EAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199148L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'text': '\x85\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199150L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'disassembly': 'TEST EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_38(self):
''' Instruction TEST EDI, EDI '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 0L, 'RAX': 0L, 'RDI': 0L, 'EDI': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205088L, 'RBP': 7054832L}, 'memory': {4205088L: '\x85', 4205089L: '\xff'}}, 'text': '\x85\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RAX': 0L, 'RDI': 0L, 'EDI': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205090L, 'RBP': 7054832L}, 'memory': {4205088L: '\x85', 4205089L: '\xff'}}, 'disassembly': 'TEST EDI, EDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_39(self):
''' Instruction TEST R12D, R12D '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'R12D': 17L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336894L, 'RBP': 140737488345936L}, 'memory': {4336896L: '\xe4', 4336894L: 'E', 4336895L: '\x85'}}, 'text': 'E\x85\xe4', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RAX': 0L, 'RDI': 0L, 'R12D': 17L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4336897L, 'RBP': 140737488345936L}, 'memory': {4336896L: '\xe4', 4336894L: 'E', 4336895L: '\x85'}}, 'disassembly': 'TEST R12D, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_4(self):
''' Instruction TEST R14, R14 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392734L, 'RBP': 7049504L}, 'memory': {4392736L: '\xf6', 4392734L: 'M', 4392735L: '\x85'}}, 'text': 'M\x85\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 51L, 'RSI': 140737354125687L, 'RDI': 140737354125685L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 140737488345640L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392736L: '\xf6', 4392734L: 'M', 4392735L: '\x85'}}, 'disassembly': 'TEST R14, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_40(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322537L, 'RBP': 140737488347777L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488347777L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_41(self):
''' Instruction TEST EBX, EBX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'EBX': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205271L, 'RBP': 7049728L}, 'memory': {4205272L: '\xdb', 4205271L: '\x85'}}, 'text': '\x85\xdb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 0L, 'RDI': 0L, 'EBX': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205273L, 'RBP': 7049728L}, 'memory': {4205272L: '\xdb', 4205271L: '\x85'}}, 'disassembly': 'TEST EBX, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_42(self):
''' Instruction TEST RBX, RBX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 13L, 'RSI': 140737488346472L, 'RBX': 140737488346512L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322409L, 'RBP': 140737488346472L}, 'memory': {4322409L: 'H', 4322410L: '\x85', 4322411L: '\xdb'}}, 'text': 'H\x85\xdb', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RBX': 140737488346512L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322412L, 'RBP': 140737488346472L}, 'memory': {4322409L: 'H', 4322410L: '\x85', 4322411L: '\xdb'}}, 'disassembly': 'TEST RBX, RBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_43(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488350621L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350621L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_44(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488349535L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488349535L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_45(self):
''' Instruction TEST R12D, R12D '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 663L, 'RCX': 4294967292L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782910L, 'R12D': 13L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339875L, 'RBP': 140737488345936L}, 'memory': {4339875L: 'E', 4339876L: '\x85', 4339877L: '\xe4'}}, 'text': 'E\x85\xe4', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4294967292L, 'RSI': 140737354125325L, 'RAX': 0L, 'RDI': 4782910L, 'R12D': 13L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4339878L, 'RBP': 140737488345936L}, 'memory': {4339875L: 'E', 4339876L: '\x85', 4339877L: '\xe4'}}, 'disassembly': 'TEST R12D, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_46(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322537L, 'RBP': 140737488347858L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488347858L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_47(self):
''' Instruction TEST DL, 0x8 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'DL': 14L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354125400L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244346L, 'RBP': 7049504L}, 'memory': {4244346L: '\xf6', 4244347L: '\xc2', 4244348L: '\x08'}}, 'text': '\xf6\xc2\x08', 'pos': {'registers': {'RFLAGS': 514L, 'DL': 14L, 'RCX': 1094795585L, 'RSI': 4782982L, 'RDI': 140737354125400L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244349L, 'RBP': 7049504L}, 'memory': {4244346L: '\xf6', 4244347L: '\xc2', 4244348L: '\x08'}}, 'disassembly': 'TEST DL, 0x8', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_48(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346832L, 'RAX': 140737488350498L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346832L, 'RAX': 140737488350498L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_49(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488351047L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488351047L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_5(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322485L, 'RBP': 140737488347397L}, 'memory': {4322485L: 'H', 4322486L: '\x85', 4322487L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322488L, 'RBP': 140737488347397L}, 'memory': {4322485L: 'H', 4322486L: '\x85', 4322487L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_50(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488350498L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488350498L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_51(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488347630L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488347630L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_52(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322537L, 'RBP': 140737488351013L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488351013L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_53(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488350281L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488350281L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_54(self):
''' Instruction TEST RDX, RDX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392471L, 'RBP': 7049504L}, 'memory': {4392472L: '\x85', 4392473L: '\xd2', 4392471L: 'H'}}, 'text': 'H\x85\xd2', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392474L, 'RBP': 7049504L}, 'memory': {4392472L: '\x85', 4392473L: '\xd2', 4392471L: 'H'}}, 'disassembly': 'TEST RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_55(self):
''' Instruction TEST R14, R14 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197659L, 'RBP': 4L}, 'memory': {4197659L: 'M', 4197660L: '\x85', 4197661L: '\xf6'}}, 'text': 'M\x85\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 7049240L, 'RSI': 140737488346472L, 'RDI': 4L, 'RAX': 7059656L, 'RSP': 140737488346176L, 'RDX': 140737488346512L, 'RIP': 4197662L, 'RBP': 4L}, 'memory': {4197659L: 'M', 4197660L: '\x85', 4197661L: '\xf6'}}, 'disassembly': 'TEST R14, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_56(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488347727L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488347727L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_57(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392632L: 'H', 4392633L: '\x85', 4392634L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125488L, 'RAX': 3920L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392635L, 'RBP': 7049504L}, 'memory': {4392632L: 'H', 4392633L: '\x85', 4392634L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_58(self):
''' Instruction TEST RSI, RSI '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 16384L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285081L, 'RBP': 32768L}, 'memory': {4285081L: 'H', 4285082L: '\x85', 4285083L: '\xf6'}}, 'text': 'H\x85\xf6', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 4L, 'RSI': 1048576L, 'RDI': 2L, 'RAX': 16384L, 'RSP': 140737488346144L, 'RDX': 0L, 'RIP': 4285084L, 'RBP': 32768L}, 'memory': {4285081L: 'H', 4285082L: '\x85', 4285083L: '\xf6'}}, 'disassembly': 'TEST RSI, RSI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_59(self):
''' Instruction TEST RDX, RDX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327736L, 'RBP': 140737488345936L}, 'memory': {4327736L: 'H', 4327737L: '\x85', 4327738L: '\xd2'}}, 'text': 'H\x85\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795872L, 'RSI': 140737488345638L, 'RDI': 4L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 0L, 'RIP': 4327739L, 'RBP': 140737488345936L}, 'memory': {4327736L: 'H', 4327737L: '\x85', 4327738L: '\xd2'}}, 'disassembly': 'TEST RDX, RDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_6(self):
''' Instruction TEST EAX, EAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199148L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'text': '\x85\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199150L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'disassembly': 'TEST EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_60(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322537L, 'RBP': 140737488351129L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488351129L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_61(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322537L, 'RBP': 140737488350013L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488350013L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_62(self):
''' Instruction TEST R14, R14 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392734L, 'RBP': 7049504L}, 'memory': {4392736L: '\xf6', 4392734L: 'M', 4392735L: '\x85'}}, 'text': 'M\x85\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125487L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392736L: '\xf6', 4392734L: 'M', 4392735L: '\x85'}}, 'disassembly': 'TEST R14, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_63(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283914L, 'RBP': 3L}, 'memory': {4283914L: 'H', 4283915L: '\x85', 4283916L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345968L, 'RDX': 96L, 'RIP': 4283917L, 'RBP': 3L}, 'memory': {4283914L: 'H', 4283915L: '\x85', 4283916L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_64(self):
''' Instruction TEST DL, 0x2 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'DL': 14L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125473L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244310L, 'RBP': 7049504L}, 'memory': {4244312L: '\x02', 4244310L: '\xf6', 4244311L: '\xc2'}}, 'text': '\xf6\xc2\x02', 'pos': {'registers': {'RFLAGS': 514L, 'DL': 14L, 'RCX': 0L, 'RSI': 4782976L, 'RDI': 140737354125473L, 'RAX': 4702111234474983745L, 'RSP': 140737488346056L, 'RDX': 14L, 'RIP': 4244313L, 'RBP': 7049504L}, 'memory': {4244312L: '\x02', 4244310L: '\xf6', 4244311L: '\xc2'}}, 'disassembly': 'TEST DL, 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_65(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347364L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4291403L, 'RBP': 140737488347312L}, 'memory': {4291403L: 'H', 4291404L: '\x85', 4291405L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 26L, 'RSI': 33824L, 'RDI': 140737488347392L, 'RAX': 140737488347364L, 'RSP': 140737488346176L, 'RDX': 0L, 'RIP': 4291406L, 'RBP': 140737488347312L}, 'memory': {4291403L: 'H', 4291404L: '\x85', 4291405L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_66(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488350642L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350642L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_67(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488349709L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488349709L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_68(self):
''' Instruction TEST EAX, EAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330008L, 'RBP': 140737488345936L}, 'memory': {4330008L: '\x85', 4330009L: '\xc0'}}, 'text': '\x85\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4783009L, 'RSI': 140737354125663L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4330010L, 'RBP': 140737488345936L}, 'memory': {4330008L: '\x85', 4330009L: '\xc0'}}, 'disassembly': 'TEST EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_69(self):
''' Instruction TEST EBP, EBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'EBP': 9L, 'RAX': 1L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284121L, 'RBP': 9L}, 'memory': {4284121L: '\x85', 4284122L: '\xed'}}, 'text': '\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 4L, 'EBP': 9L, 'RAX': 1L, 'RSP': 140737488345968L, 'RDX': 2L, 'RIP': 4284123L, 'RBP': 9L}, 'memory': {4284121L: '\x85', 4284122L: '\xed'}}, 'disassembly': 'TEST EBP, EBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_7(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346768L, 'RAX': 140737488350381L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195975L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346768L, 'RAX': 140737488350381L, 'RSP': 140737488346240L, 'RDX': 140737488346456L, 'RIP': 4195978L, 'RBP': 0L}, 'memory': {4195976L: '\x85', 4195977L: '\xc0', 4195975L: 'H'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_70(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322537L, 'RBP': 140737488347664L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322540L, 'RBP': 140737488347664L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_71(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347056L, 'RAX': 4L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297405L, 'RBP': 0L}, 'memory': {4297405L: 'H', 4297406L: '\x85', 4297407L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 0L, 'RDI': 140737488347056L, 'RAX': 4L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297408L, 'RBP': 0L}, 'memory': {4297405L: 'H', 4297406L: '\x85', 4297407L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_72(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322537L, 'RBP': 140737488349720L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488349720L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_73(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488349565L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488349565L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_74(self):
''' Instruction TEST EAX, EAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199148L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'text': '\x85\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199150L, 'RBP': 4782912L}, 'memory': {4199148L: '\x85', 4199149L: '\xc0'}}, 'disassembly': 'TEST EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_75(self):
''' Instruction TEST DWORD [RBX], 0x202 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RBX': 7049504L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392400L, 'RBP': 699L}, 'memory': {4392400L: '\xf7', 4392401L: '\x03', 4392402L: '\x02', 4392403L: '\x02', 4392404L: '\x00', 4392405L: '\x00', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'text': '\xf7\x03\x02\x02\x00\x00', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4294967295L, 'RDI': 0L, 'RAX': 140737354125312L, 'RSP': 140737488345936L, 'RDX': 18446744073709551615L, 'RIP': 4392406L, 'RBP': 699L}, 'memory': {4392400L: '\xf7', 4392401L: '\x03', 4392402L: '\x02', 4392403L: '\x02', 4392404L: '\x00', 4392405L: '\x00', 7049504: '\x84', 7049505: '(', 7049506: '\xad', 7049507: '\xfb', 7049508: '\x00', 7049509: '\x00', 7049510: '\x00', 7049511: '\x00', 7049512: '\x00', 7049513: '\xd0', 7049514: '\xff', 7049515: '\xf7', 7049516: '\xff', 7049517: '\x7f', 7049518: '\x00', 7049519: '\x00', 7049520: '\x00', 7049521: '\xd0', 7049522: '\xff', 7049523: '\xf7', 7049524: '\xff', 7049525: '\x7f', 7049526: '\x00', 7049527: '\x00', 7049528: '\x00', 7049529: '\xd0', 7049530: '\xff', 7049531: '\xf7', 7049532: '\xff', 7049533: '\x7f', 7049534: '\x00', 7049535: '\x00'}}, 'disassembly': 'TEST DWORD [RBX], 0x202', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_76(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488350653L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488350653L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_77(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322537L, 'RBP': 140737488349535L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488349535L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_78(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350751L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488350751L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_79(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322537L, 'RBP': 140737488349968L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488349968L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_8(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488347948L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488347948L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_80(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488347888L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212896L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'RAX': 140737488347888L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212899L, 'RBP': 0L}, 'memory': {4212896L: 'H', 4212897L: '\x85', 4212898L: '\xc0'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_81(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488351013L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488351013L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_82(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322537L, 'RBP': 140737488347906L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322540L, 'RBP': 140737488347906L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_83(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322537L, 'RBP': 140737488347888L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073704757637L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 5L, 'RIP': 4322540L, 'RBP': 140737488347888L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_84(self):
''' Instruction TEST RAX, RAX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297662L, 'RBP': 140737488346472L}, 'memory': {4297664L: '\xc0', 4297662L: 'H', 4297663L: '\x85'}}, 'text': 'H\x85\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297665L, 'RBP': 140737488346472L}, 'memory': {4297664L: '\xc0', 4297662L: 'H', 4297663L: '\x85'}}, 'disassembly': 'TEST RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_85(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322537L, 'RBP': 140737488350843L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488350843L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_86(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488351032L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488351032L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_87(self):
''' Instruction TEST AH, 0x80 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 647L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'AH': 40L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199130L, 'RBP': 4782912L}, 'memory': {4199130L: '\xf6', 4199131L: '\xc4', 4199132L: '\x80'}}, 'text': '\xf6\xc4\x80', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 7049504L, 'AH': 40L, 'RAX': 4222429316L, 'RSP': 140737488346128L, 'RDX': 79L, 'RIP': 4199133L, 'RBP': 4782912L}, 'memory': {4199130L: '\xf6', 4199131L: '\xc4', 4199132L: '\x80'}}, 'disassembly': 'TEST AH, 0x80', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_88(self):
''' Instruction TEST AL, 0x2 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 7049635L, 'RAX': 4222427272L, 'RDI': 140737354125312L, 'RBP': 1L, 'RSP': 140737488346112L, 'AL': 136L, 'RIP': 4205794L, 'RDX': 7059408L}, 'memory': {4205794L: '\xa8', 4205795L: '\x02'}}, 'text': '\xa8\x02', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7049635L, 'RAX': 4222427272L, 'RDI': 140737354125312L, 'RBP': 1L, 'RSP': 140737488346112L, 'AL': 136L, 'RIP': 4205796L, 'RDX': 7059408L}, 'memory': {4205794L: '\xa8', 4205795L: '\x02'}}, 'disassembly': 'TEST AL, 0x2', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_89(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322537L, 'RBP': 140737488351093L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322540L, 'RBP': 140737488351093L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_9(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322537L, 'RBP': 140737488350429L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 4294967264L, 'RDI': 4793989L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 6L, 'RIP': 4322540L, 'RBP': 140737488350429L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_90(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322537L, 'RBP': 140737488347888L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322540L, 'RBP': 140737488347888L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_91(self):
''' Instruction TEST EDX, EDX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'EDX': 0L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239689L, 'RBP': 4782912L}, 'memory': {4239689L: '\x85', 4239690L: '\xd2'}}, 'text': '\x85\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782990L, 'RDI': 4782912L, 'EDX': 0L, 'RAX': 4782912L, 'RSP': 140737488346120L, 'RDX': 0L, 'RIP': 4239691L, 'RBP': 4782912L}, 'memory': {4239689L: '\x85', 4239690L: '\xd2'}}, 'disassembly': 'TEST EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_92(self):
''' Instruction TEST R12D, R12D '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RAX': 4222429316L, 'RDI': 0L, 'R12D': 4294967295L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397763L, 'RBP': 4294967295L}, 'memory': {4397763L: 'E', 4397764L: '\x85', 4397765L: '\xe4'}}, 'text': 'E\x85\xe4', 'pos': {'registers': {'RFLAGS': 646L, 'RCX': 140737354129408L, 'RSI': 140737354125312L, 'RAX': 4222429316L, 'RDI': 0L, 'R12D': 4294967295L, 'RSP': 140737488344160L, 'RDX': 140737354125312L, 'RIP': 4397766L, 'RBP': 4294967295L}, 'memory': {4397763L: 'E', 4397764L: '\x85', 4397765L: '\xe4'}}, 'disassembly': 'TEST R12D, R12D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_93(self):
''' Instruction TEST R14, R14 '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125931L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392734L, 'RBP': 7049504L}, 'memory': {4392736L: '\xf6', 4392734L: 'M', 4392735L: '\x85'}}, 'text': 'M\x85\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14': 0L, 'RCX': 4702111234474983745L, 'RSI': 4782990L, 'RDI': 140737354125931L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392737L, 'RBP': 7049504L}, 'memory': {4392736L: '\xf6', 4392734L: 'M', 4392735L: '\x85'}}, 'disassembly': 'TEST R14, R14', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_94(self):
''' Instruction TEST R8D, R8D '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'R8D': 4294967295L, 'RFLAGS': 518L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346016L, 'RDX': 7042720L, 'RIP': 4212705L, 'RBP': 140737488346112L}, 'memory': {4212705L: 'E', 4212706L: '\x85', 4212707L: '\xc0'}}, 'text': 'E\x85\xc0', 'pos': {'registers': {'R8D': 4294967295L, 'RFLAGS': 646L, 'RCX': 7042728L, 'RSI': 4519992L, 'RDI': 24L, 'RAX': 7051200L, 'RSP': 140737488346016L, 'RDX': 7042720L, 'RIP': 4212708L, 'RBP': 140737488346112L}, 'memory': {4212705L: 'E', 4212706L: '\x85', 4212707L: '\xc0'}}, 'disassembly': 'TEST R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_95(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205534L, 'RBP': 0L}, 'memory': {4205536L: '\xed', 4205534L: 'H', 4205535L: '\x85'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205537L, 'RBP': 0L}, 'memory': {4205536L: '\xed', 4205534L: 'H', 4205535L: '\x85'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_96(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 530L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322537L, 'RBP': 140737488349619L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 18446744073704757701L, 'RSI': 4294967264L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 4L, 'RIP': 4322540L, 'RBP': 140737488349619L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_97(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488350181L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488350181L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_98(self):
''' Instruction TEST EBX, EBX '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'EBX': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205418L, 'RBP': 7049280L}, 'memory': {4205418L: '\x85', 4205419L: '\xdb'}}, 'text': '\x85\xdb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'EBX': 0L, 'RAX': 0L, 'RSP': 140737488346000L, 'RDX': 0L, 'RIP': 4205420L, 'RBP': 7049280L}, 'memory': {4205418L: '\x85', 4205419L: '\xdb'}}, 'disassembly': 'TEST EBX, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testTEST_99(self):
''' Instruction TEST RBP, RBP '''
test = {'mnemonic': 'TEST', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322537L, 'RBP': 140737488347750L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'text': 'H\x85\xed', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322540L, 'RBP': 140737488347750L}, 'memory': {4322537L: 'H', 4322538L: '\x85', 4322539L: '\xed'}}, 'disassembly': 'TEST RBP, RBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_1(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 63L, 'RDX': 0L, 'RBP': 9L, 'RDI': 194L, 'ESI': 15774463L, 'RSI': 15774463L, 'RSP': 140737488345968L, 'RIP': 4284024L, 'EBX': 29360191L, 'RFLAGS': 582L, 'RAX': 469778721L}, 'memory': {4284024L: '\x87', 4284025L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 63L, 'RDX': 0L, 'RBP': 9L, 'RDI': 194L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284026L, 'EBX': 15774463L, 'RFLAGS': 582L, 'RAX': 469778721L}, 'memory': {4284024L: '\x87', 4284025L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_10(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 2L, 'RDX': 2L, 'RBP': 9L, 'RDI': 4L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284073L, 'EBX': 2L, 'RFLAGS': 514L, 'RAX': 4L}, 'memory': {4284073L: '\x87', 4284074L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 2L, 'RDX': 2L, 'RBP': 9L, 'RDI': 4L, 'ESI': 2L, 'RSI': 2L, 'RSP': 140737488345968L, 'RIP': 4284075L, 'EBX': 29360191L, 'RFLAGS': 514L, 'RAX': 4L}, 'memory': {4284073L: '\x87', 4284074L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_2(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 4095L, 'RDX': 6L, 'RBP': 9L, 'RDI': 4L, 'ESI': 3L, 'RSI': 3L, 'RSP': 140737488345968L, 'RIP': 4284077L, 'EBX': 62914623L, 'RFLAGS': 518L, 'RAX': 470008163L}, 'memory': {4284077L: '\x87', 4284078L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 4095L, 'RDX': 6L, 'RBP': 9L, 'RDI': 4L, 'ESI': 62914623L, 'RSI': 62914623L, 'RSP': 140737488345968L, 'RIP': 4284079L, 'EBX': 3L, 'RFLAGS': 518L, 'RAX': 470008163L}, 'memory': {4284077L: '\x87', 4284078L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_3(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 63L, 'RDX': 0L, 'RBP': 9L, 'RDI': 4L, 'ESI': 1L, 'RSI': 1L, 'RSP': 140737488345968L, 'RIP': 4284077L, 'EBX': 29360191L, 'RFLAGS': 514L, 'RAX': 469778722L}, 'memory': {4284077L: '\x87', 4284078L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 63L, 'RDX': 0L, 'RBP': 9L, 'RDI': 4L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284079L, 'EBX': 1L, 'RFLAGS': 514L, 'RAX': 469778722L}, 'memory': {4284077L: '\x87', 4284078L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_4(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 0L, 'RDX': 3L, 'RBP': 9L, 'RDI': 194L, 'ESI': 15774463L, 'RSI': 15774463L, 'RSP': 140737488345968L, 'RIP': 4284020L, 'EBX': 15774463L, 'RFLAGS': 582L, 'RAX': 4L}, 'memory': {4284020L: '\x87', 4284021L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 0L, 'RDX': 3L, 'RBP': 9L, 'RDI': 194L, 'ESI': 15774463L, 'RSI': 15774463L, 'RSP': 140737488345968L, 'RIP': 4284022L, 'EBX': 15774463L, 'RFLAGS': 582L, 'RAX': 4L}, 'memory': {4284020L: '\x87', 4284021L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_5(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 1L, 'RDX': 1L, 'RBP': 9L, 'RDI': 4L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284073L, 'EBX': 1L, 'RFLAGS': 514L, 'RAX': 4L}, 'memory': {4284073L: '\x87', 4284074L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 1L, 'RDX': 1L, 'RBP': 9L, 'RDI': 4L, 'ESI': 1L, 'RSI': 1L, 'RSP': 140737488345968L, 'RIP': 4284075L, 'EBX': 29360191L, 'RFLAGS': 514L, 'RAX': 4L}, 'memory': {4284073L: '\x87', 4284074L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_6(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 0L, 'RDX': 1L, 'RBP': 3L, 'RDI': 188L, 'ESI': 15774463L, 'RSI': 15774463L, 'RSP': 140737488345968L, 'RIP': 4284020L, 'EBX': 15774463L, 'RFLAGS': 582L, 'RAX': 4L}, 'memory': {4284020L: '\x87', 4284021L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 0L, 'RDX': 1L, 'RBP': 3L, 'RDI': 188L, 'ESI': 15774463L, 'RSI': 15774463L, 'RSP': 140737488345968L, 'RIP': 4284022L, 'EBX': 15774463L, 'RFLAGS': 582L, 'RAX': 4L}, 'memory': {4284020L: '\x87', 4284021L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_7(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 511L, 'RDX': 0L, 'RBP': 9L, 'RDI': 4L, 'ESI': 2L, 'RSI': 2L, 'RSP': 140737488345968L, 'RIP': 4284077L, 'EBX': 29360191L, 'RFLAGS': 514L, 'RAX': 469778755L}, 'memory': {4284077L: '\x87', 4284078L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 511L, 'RDX': 0L, 'RBP': 9L, 'RDI': 4L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284079L, 'EBX': 2L, 'RFLAGS': 514L, 'RAX': 469778755L}, 'memory': {4284077L: '\x87', 4284078L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_8(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 63L, 'RDX': 0L, 'RBP': 3L, 'RDI': 188L, 'ESI': 15774463L, 'RSI': 15774463L, 'RSP': 140737488345968L, 'RIP': 4284024L, 'EBX': 29360191L, 'RFLAGS': 582L, 'RAX': 469778721L}, 'memory': {4284024L: '\x87', 4284025L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 63L, 'RDX': 0L, 'RBP': 3L, 'RDI': 188L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284026L, 'EBX': 15774463L, 'RFLAGS': 582L, 'RAX': 469778721L}, 'memory': {4284024L: '\x87', 4284025L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXCHG_9(self):
''' Instruction XCHG ESI, EBX '''
test = {'mnemonic': 'XCHG', 'pre': {'registers': {'RCX': 3L, 'RDX': 3L, 'RBP': 9L, 'RDI': 4L, 'ESI': 29360191L, 'RSI': 29360191L, 'RSP': 140737488345968L, 'RIP': 4284073L, 'EBX': 3L, 'RFLAGS': 518L, 'RAX': 4L}, 'memory': {4284073L: '\x87', 4284074L: '\xde'}}, 'text': '\x87\xde', 'pos': {'registers': {'RCX': 3L, 'RDX': 3L, 'RBP': 9L, 'RDI': 4L, 'ESI': 3L, 'RSI': 3L, 'RSP': 140737488345968L, 'RIP': 4284075L, 'EBX': 29360191L, 'RFLAGS': 518L, 'RAX': 4L}, 'memory': {4284073L: '\x87', 4284074L: '\xde'}}, 'disassembly': 'XCHG ESI, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXGETBV_1(self):
''' Instruction XGETBV '''
test = {'mnemonic': 'XGETBV', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 4398046511104L, 'RSP': 140737488346168L, 'RDX': 59L, 'RIP': 4299901L, 'RBP': 1L}, 'memory': {4299901L: '\x0f', 4299902L: '\x01', 4299903L: '\xd0'}}, 'text': '\x0f\x01\xd0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7065696L, 'RDI': 6L, 'RAX': 7L, 'RSP': 140737488346168L, 'RDX': 0L, 'RIP': 4299904L, 'RBP': 1L}, 'memory': {4299901L: '\x0f', 4299902L: '\x01', 4299903L: '\xd0'}}, 'disassembly': 'XGETBV', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x10cd5, test['pos']['registers'][reg_name]&0x10cd5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_1(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 6L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_10(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'EDX': 2L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 57632L, 'RSI': 4782899L, 'RDI': 140737354125323L, 'EDX': 0L, 'RAX': 4085L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_100(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_101(self):
''' Instruction XOR ECX, ECX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 100L, 'RSI': 4782888L, 'ECX': 100L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4337435L, 'RBP': 140737488345936L}, 'memory': {4337435L: '1', 4337436L: '\xc9'}}, 'text': '1\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782888L, 'ECX': 0L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4337437L, 'RBP': 140737488345936L}, 'memory': {4337435L: '1', 4337436L: '\xc9'}}, 'disassembly': 'XOR ECX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_11(self):
''' Instruction XOR ESI, ESI '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4819040L, 'RSI': 33824L, 'ESI': 33824L, 'RDI': 140737488347392L, 'RAX': 18446744073709551600L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196147L, 'RBP': 0L}, 'memory': {4196147L: '1', 4196148L: '\xf6'}}, 'text': '1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4819040L, 'RSI': 0L, 'ESI': 0L, 'RDI': 140737488347392L, 'RAX': 18446744073709551600L, 'RSP': 140737488346240L, 'RDX': 0L, 'RIP': 4196149L, 'RBP': 0L}, 'memory': {4196147L: '1', 4196148L: '\xf6'}}, 'disassembly': 'XOR ESI, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_12(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7041664L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392442L, 'RBP': 4782912L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392444L, 'RBP': 4782912L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_13(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_14(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 118L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792688L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 78L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_15(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 6L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4294967295L, 'RDI': 140737488347328L, 'RAX': 6L, 'RSP': 140737488346168L, 'RDX': 4129L, 'RIP': 4416372L, 'RBP': 140737488347312L}, 'memory': {4416372L: '1', 4416373L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4294967295L, 'RDI': 140737488347328L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 4129L, 'RIP': 4416374L, 'RBP': 140737488347312L}, 'memory': {4416372L: '1', 4416373L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_16(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'EDX': 2L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'EDX': 0L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_17(self):
''' Instruction XOR ESI, ESI '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 7071872L, 'ESI': 7071872L, 'RDI': 4783074L, 'RAX': 0L, 'RSP': 140737488346240L, 'RDX': 7065176L, 'RIP': 4196357L, 'RBP': 0L}, 'memory': {4196357L: '1', 4196358L: '\xf6'}}, 'text': '1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'ESI': 0L, 'RDI': 4783074L, 'RAX': 0L, 'RSP': 140737488346240L, 'RDX': 7065176L, 'RIP': 4196359L, 'RBP': 0L}, 'memory': {4196357L: '1', 4196358L: '\xf6'}}, 'disassembly': 'XOR ESI, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_18(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'R14D': 4294958047L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320728L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_19(self):
''' Instruction XOR AL, AL '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 13L, 'RAX': 1979931137L, 'RDI': 188L, 'RBP': 188L, 'RSP': 140737488346048L, 'AL': 1L, 'RIP': 4284595L, 'RDX': 1L}, 'memory': {4284595L: '0', 4284596L: '\xc0'}}, 'text': '0\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 13L, 'RAX': 1979931136L, 'RDI': 188L, 'RBP': 188L, 'RSP': 140737488346048L, 'AL': 0L, 'RIP': 4284597L, 'RDX': 1L}, 'memory': {4284595L: '0', 4284596L: '\xc0'}}, 'disassembly': 'XOR AL, AL', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_2(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'EDX': 1L, 'RAX': 3728L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125680L, 'EDX': 0L, 'RAX': 3728L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_20(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 530L, 'R14D': 4782888L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125321L, 'RAX': 4087L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_21(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 249954304L, 'RFLAGS': 514L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 550005768192L, 'RSP': 140737488346232L, 'RDX': 18446744072518369280L, 'RIP': 4319936L, 'RBP': 0L}, 'memory': {4319936L: '1', 4319937L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346232L, 'RDX': 18446744072518369280L, 'RIP': 4319938L, 'RBP': 0L}, 'memory': {4319936L: '1', 4319937L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_22(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_23(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 7065360L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239584L, 'RBP': 140737488346472L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793973L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 0L, 'RIP': 4239587L, 'RBP': 140737488346472L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_24(self):
''' Instruction XOR ESI, ESI '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7074272L, 'RSI': 1600L, 'ESI': 1600L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 7065472L, 'RIP': 4520104L, 'RBP': 140737488346112L}, 'memory': {4520104L: '1', 4520105L: '\xf6'}}, 'text': '1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7074272L, 'RSI': 0L, 'ESI': 0L, 'RDI': 7051232L, 'RAX': 7074288L, 'RSP': 140737488346080L, 'RDX': 7065472L, 'RIP': 4520106L, 'RBP': 140737488346112L}, 'memory': {4520104L: '1', 4520105L: '\xf6'}}, 'disassembly': 'XOR ESI, ESI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_25(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7059656L, 'RFLAGS': 514L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 7059656L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322407L, 'RBP': 140737488346472L}, 'memory': {4322408L: '\xc0', 4322407L: '1'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793925L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 7L, 'RIP': 4322409L, 'RBP': 140737488346472L}, 'memory': {4322408L: '\xc0', 4322407L: '1'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_26(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 104L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_27(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 7065376L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239584L, 'RBP': 140737488346472L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 1L, 'RIP': 4239587L, 'RBP': 140737488346472L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_28(self):
''' Instruction XOR R8D, R8D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R8D': 4197776L, 'RFLAGS': 518L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346976L, 'RAX': 33L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296927L, 'RBP': 0L}, 'memory': {4296928L: '1', 4296929L: '\xc0', 4296927L: 'E'}}, 'text': 'E1\xc0', 'pos': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 4197616L, 'RSI': 4L, 'RDI': 140737488346976L, 'RAX': 33L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4296930L, 'RBP': 0L}, 'memory': {4296928L: '1', 4296929L: '\xc0', 4296927L: 'E'}}, 'disassembly': 'XOR R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_29(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337357L: '1', 4337358L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337359L, 'RBP': 140737488345936L}, 'memory': {4337357L: '1', 4337358L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_3(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4194792L, 'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 7065696L, 'RDI': 3L, 'RAX': 4194792L, 'RSP': 140737488346168L, 'RDX': 12297829382473034411L, 'RIP': 4299832L, 'RBP': 1L}, 'memory': {4299832L: '1', 4299833L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 140737488345864L, 'RSI': 7065696L, 'RDI': 3L, 'RAX': 0L, 'RSP': 140737488346168L, 'RDX': 12297829382473034411L, 'RIP': 4299834L, 'RBP': 1L}, 'memory': {4299832L: '1', 4299833L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_30(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4371072L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 1L, 'RDI': 4783008L, 'RAX': 4371072L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329767L, 'RBP': 140737488345936L}, 'memory': {4329768L: '\xc0', 4329767L: '1'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 1L, 'RDI': 4783008L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329769L, 'RBP': 140737488345936L}, 'memory': {4329768L: '\xc0', 4329767L: '1'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_31(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7041664L, 'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488345920L, 'RDX': 699L, 'RIP': 4392978L, 'RBP': 7049504L}, 'memory': {4392978L: '1', 4392979L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 7058288L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488345920L, 'RDX': 699L, 'RIP': 4392980L, 'RBP': 7049504L}, 'memory': {4392978L: '1', 4392979L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_32(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 32L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239584L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4783050L, 'RSI': 140737354125695L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239587L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_33(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 4792696L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_34(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 0L, 'RFLAGS': 514L, 'RCX': 119L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 1648L, 'RIP': 4219926L, 'RBP': 7051232L}, 'memory': {4219928L: '\xff', 4219926L: 'E', 4219927L: '1'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 119L, 'RSI': 1600L, 'RDI': 7051232L, 'RAX': 124L, 'RSP': 140737488345824L, 'RDX': 1648L, 'RIP': 4219929L, 'RBP': 7051232L}, 'memory': {4219928L: '\xff', 4219926L: 'E', 4219927L: '1'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_35(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239584L, 'RBP': 140737488346472L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4793628L, 'RSI': 4294967264L, 'RDI': 4794037L, 'RAX': 0L, 'RSP': 140737488346056L, 'RDX': 7065280L, 'RIP': 4239587L, 'RBP': 140737488346472L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_36(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_37(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_38(self):
''' Instruction XOR R8D, R8D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R8D': 4160737618L, 'RFLAGS': 514L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338614L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'text': 'E1\xc0', 'pos': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125650L, 'RDI': 7065768L, 'RAX': 4L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'disassembly': 'XOR R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_39(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'EDX': 78L, 'RAX': 3841L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125567L, 'EDX': 0L, 'RAX': 3841L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_4(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'EDX': 4294958480L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 140737488346512L, 'RIP': 4776562L, 'RBP': 140737488346144L}, 'memory': {4776562L: '1', 4776563L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 7054976L, 'RDI': 4881624L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488346136L, 'RDX': 0L, 'RIP': 4776564L, 'RBP': 140737488346144L}, 'memory': {4776562L: '1', 4776563L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_40(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 4294958046L, 'RFLAGS': 534L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320690L, 'RBP': 3L}, 'memory': {4320690L: 'E', 4320691L: '1', 4320692L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345952L, 'RDX': 68L, 'RIP': 4320693L, 'RBP': 3L}, 'memory': {4320690L: 'E', 4320691L: '1', 4320692L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_41(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'EDX': 7L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 7L, 'RIP': 4297564L, 'RBP': 140737488346472L}, 'memory': {4297564L: '1', 4297565L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 5L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'EDX': 0L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297566L, 'RBP': 140737488346472L}, 'memory': {4297564L: '1', 4297565L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_42(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'R14D': 4294958047L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320728L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 90L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_43(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 4792696L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792696L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 96L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_44(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 530L, 'R14D': 4782888L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'RAX': 4079L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 57600L, 'RSI': 4782903L, 'RDI': 140737354125329L, 'RAX': 4079L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_45(self):
''' Instruction XOR EBP, EBP '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'EBP': 4294958080L, 'RAX': 7059656L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212861L, 'RBP': 140737488346112L}, 'memory': {4212861L: '1', 4212862L: '\xed'}}, 'text': '1\xed', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4519992L, 'RDI': 7059520L, 'EBP': 0L, 'RAX': 7059656L, 'RSP': 140737488346016L, 'RDX': 7065872L, 'RIP': 4212863L, 'RBP': 0L}, 'memory': {4212861L: '1', 4212862L: '\xed'}}, 'disassembly': 'XOR EBP, EBP', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_46(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792448L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 12L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_47(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'EDX': 2L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125691L, 'EDX': 0L, 'RAX': 3717L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_48(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 534L, 'R14D': 4783016L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 140737354125668L, 'RAX': 3740L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 1024L, 'RSI': 4783022L, 'RDI': 140737354125668L, 'RAX': 3740L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_49(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 530L, 'R14D': 4783016L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 4L, 'RSI': 4783016L, 'RDI': 140737354125663L, 'RAX': 3745L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_5(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 135168L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 135168L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4224089L, 'RBP': 7051232L}, 'memory': {4224089L: '1', 4224090L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4224091L, 'RBP': 7051232L}, 'memory': {4224089L: '1', 4224090L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_50(self):
''' Instruction XOR R8D, R8D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R8D': 12L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338614L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'text': 'E1\xc0', 'pos': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125680L, 'RDI': 140737354125668L, 'RAX': 3L, 'RSP': 140737488344256L, 'RDX': 24L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'disassembly': 'XOR R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_51(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 135168L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223553L, 'RBP': 7051232L}, 'memory': {4223553L: 'E', 4223554L: '1', 4223555L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'RDI': 7209408L, 'RAX': 0L, 'RSP': 140737488345824L, 'RDX': 0L, 'RIP': 4223556L, 'RBP': 7051232L}, 'memory': {4223553L: 'E', 4223554L: '1', 4223555L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_52(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 4792416L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_53(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'R14D': 4294958047L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320728L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 3L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_54(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322542L, 'RBP': 0L}, 'memory': {4322542L: '1', 4322543L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 13L, 'RSI': 140737488346472L, 'RDI': 4793933L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 15L, 'RIP': 4322544L, 'RBP': 0L}, 'memory': {4322542L: '1', 4322543L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_55(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792760L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 124L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_56(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793961L, 'EDX': 11L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 11L, 'RIP': 4297640L, 'RBP': 140737488346472L}, 'memory': {4297640L: '1', 4297641L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793961L, 'EDX': 0L, 'RAX': 4864625L, 'RSP': 140737488346128L, 'RDX': 0L, 'RIP': 4297642L, 'RBP': 140737488346472L}, 'memory': {4297640L: '1', 4297641L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_57(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7041664L, 'RFLAGS': 530L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4392442L, 'RBP': 140737488345936L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 4L, 'RIP': 4392444L, 'RBP': 140737488345936L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_58(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392558L, 'RBP': 7049504L}, 'memory': {4392558L: '1', 4392559L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392560L, 'RBP': 7049504L}, 'memory': {4392558L: '1', 4392559L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_59(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'R14D': 4294958047L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320728L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 118L, 'RSP': 140737488345888L, 'RDX': 68L, 'RIP': 4320731L, 'RBP': 4792416L}, 'memory': {4320728L: 'E', 4320729L: '1', 4320730L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_6(self):
''' Instruction XOR ESI, [RDI+0x8] '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 0L, 'RSI': 0L, 'ESI': 0L, 'RDI': 140737488347136L, 'RAX': 4297312L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297312L, 'RBP': 0L}, 'memory': {4297312L: '3', 4297313L: 'w', 140737488347144: '\xe8', 140737488347145: '\x03', 140737488347146: '\x00', 140737488347147: '\x00', 140737488347148: '\x00', 140737488347149: '\x00', 140737488347150: '\x00', 140737488347151: '\x00', 140737488347152: '\x0c', 140737488347153: '\x00', 140737488347154: '\x00', 140737488347155: '\x00', 140737488347156: '\x00', 140737488347157: '\x00', 140737488347158: '\x00', 140737488347159: '\x00', 140737488347160: '\xe8', 140737488347161: '\x03', 140737488347162: '\x00', 140737488347163: '\x00', 140737488347164: '\x00', 140737488347165: '\x00', 140737488347166: '\x00', 140737488347167: '\x00', 140737488347168: '\r', 140737488347169: '\x00', 140737488347170: '\x00', 140737488347171: '\x00', 140737488347172: '\x00', 140737488347173: '\x00', 140737488347174: '\x00', 140737488347175: '\x00', 4297314L: '\x08'}}, 'text': '3w\x08', 'pos': {'registers': {'RFLAGS': 518L, 'RCX': 0L, 'RSI': 1000L, 'ESI': 1000L, 'RDI': 140737488347136L, 'RAX': 4297312L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297315L, 'RBP': 0L}, 'memory': {4297312L: '3', 4297313L: 'w', 140737488347144: '\xe8', 140737488347145: '\x03', 140737488347146: '\x00', 140737488347147: '\x00', 140737488347148: '\x00', 140737488347149: '\x00', 140737488347150: '\x00', 140737488347151: '\x00', 140737488347152: '\x0c', 140737488347153: '\x00', 140737488347154: '\x00', 140737488347155: '\x00', 140737488347156: '\x00', 140737488347157: '\x00', 140737488347158: '\x00', 140737488347159: '\x00', 140737488347160: '\xe8', 140737488347161: '\x03', 140737488347162: '\x00', 140737488347163: '\x00', 140737488347164: '\x00', 140737488347165: '\x00', 140737488347166: '\x00', 140737488347167: '\x00', 140737488347168: '\r', 140737488347169: '\x00', 140737488347170: '\x00', 140737488347171: '\x00', 140737488347172: '\x00', 140737488347173: '\x00', 140737488347174: '\x00', 140737488347175: '\x00', 4297314L: '\x08'}}, 'disassembly': 'XOR ESI, [RDI+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_60(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'EDX': 78L, 'RAX': 3555L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125853L, 'EDX': 0L, 'RAX': 3555L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_61(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7041664L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392442L, 'RBP': 4782912L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392444L, 'RBP': 4782912L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_62(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346224L, 'RDX': 18446744072518369280L, 'RIP': 4319970L, 'RBP': 0L}, 'memory': {4319970L: '1', 4319971L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 4L, 'RSI': 0L, 'RDI': 140737488346272L, 'RAX': 0L, 'RSP': 140737488346224L, 'RDX': 18446744072518369280L, 'RIP': 4319972L, 'RBP': 0L}, 'memory': {4319970L: '1', 4319971L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_63(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792480L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 34L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_64(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7041664L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392442L, 'RBP': 4782912L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 78L, 'RIP': 4392444L, 'RBP': 4782912L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_65(self):
''' Instruction XOR R13D, R13D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'R13D': 1L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 7049952L, 'RSP': 140737488346112L, 'RDX': 0L, 'RIP': 4205771L, 'RBP': 7054832L}, 'memory': {4205771L: 'E', 4205772L: '1', 4205773L: '\xed'}}, 'text': 'E1\xed', 'pos': {'registers': {'RFLAGS': 582L, 'R13D': 0L, 'RCX': 0L, 'RSI': 0L, 'RDI': 0L, 'RAX': 7049952L, 'RSP': 140737488346112L, 'RDX': 0L, 'RIP': 4205774L, 'RBP': 7054832L}, 'memory': {4205771L: 'E', 4205772L: '1', 4205773L: '\xed'}}, 'disassembly': 'XOR R13D, R13D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_66(self):
''' Instruction XOR EBX, EBX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'EBX': 4197776L, 'RAX': 0L, 'RSP': 140737488345728L, 'RDX': 0L, 'RIP': 4299401L, 'RBP': 0L}, 'memory': {4299401L: '1', 4299402L: '\xdb'}}, 'text': '1\xdb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 0L, 'RDI': 0L, 'EBX': 0L, 'RAX': 0L, 'RSP': 140737488345728L, 'RDX': 0L, 'RIP': 4299403L, 'RBP': 0L}, 'memory': {4299401L: '1', 4299402L: '\xdb'}}, 'disassembly': 'XOR EBX, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_67(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 530L, 'R14D': 4782991L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 4350L, 'RSI': 4782997L, 'RDI': 140737354125651L, 'RAX': 3757L, 'RSP': 140737488344192L, 'RDX': 12L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_68(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239584L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239587L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_69(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 79L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239584L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7059408L, 'RSI': 4782990L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 79L, 'RIP': 4239587L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_7(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7041664L, 'RFLAGS': 514L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 7041664L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4392442L, 'RBP': 140737488345936L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 7049504L, 'RAX': 0L, 'RSP': 140737488344248L, 'RDX': 1L, 'RIP': 4392444L, 'RBP': 140737488345936L}, 'memory': {4392442L: '1', 4392443L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_70(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 4792720L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792720L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345888L, 'RDX': 104L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_71(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 7049240L, 'RSI': 1L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 7058320L, 'RSP': 140737488346208L, 'RDX': 4294967295L, 'RIP': 4198631L, 'RBP': 0L}, 'memory': {4198632L: '\xd2', 4198631L: '1'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 7049240L, 'RSI': 1L, 'RDI': 0L, 'EDX': 0L, 'RAX': 7058320L, 'RSP': 140737488346208L, 'RDX': 0L, 'RIP': 4198633L, 'RBP': 0L}, 'memory': {4198632L: '\xd2', 4198631L: '1'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_72(self):
''' Instruction XOR EDI, EDI '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4096L, 'RAX': 4096L, 'RDI': 1L, 'EDI': 1L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661215L, 'RBP': 4096L}, 'memory': {4661216L: '\xff', 4661215L: '1'}}, 'text': '1\xff', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 4096L, 'RAX': 4096L, 'RDI': 0L, 'EDI': 0L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661217L, 'RBP': 4096L}, 'memory': {4661216L: '\xff', 4661215L: '1'}}, 'disassembly': 'XOR EDI, EDI', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_73(self):
''' Instruction XOR ECX, ECX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 519L, 'RCX': 18446744073709551615L, 'RSI': 24L, 'ECX': 4294967295L, 'RDI': 7209408L, 'RAX': 7209408L, 'RSP': 140737488345768L, 'RDX': 7209408L, 'RIP': 4505458L, 'RBP': 135168L}, 'memory': {4505458L: '1', 4505459L: '\xc9'}}, 'text': '1\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 24L, 'ECX': 0L, 'RDI': 7209408L, 'RAX': 7209408L, 'RSP': 140737488345768L, 'RDX': 7209408L, 'RIP': 4505460L, 'RBP': 135168L}, 'memory': {4505458L: '1', 4505459L: '\xc9'}}, 'disassembly': 'XOR ECX, ECX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_74(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 646L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 4294967295L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967295L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337357L: '1', 4337358L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345639L, 'RDI': 0L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337359L, 'RBP': 140737488345936L}, 'memory': {4337357L: '1', 4337358L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_75(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 642L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 4294967294L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 4294967294L, 'RIP': 4337357L, 'RBP': 140737488345936L}, 'memory': {4337357L: '1', 4337358L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4795649L, 'RSI': 140737488345638L, 'RDI': 0L, 'EDX': 0L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 0L, 'RIP': 4337359L, 'RBP': 140737488345936L}, 'memory': {4337357L: '1', 4337358L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_76(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 530L, 'R14D': 4783016L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 1088L, 'RSI': 4783042L, 'RDI': 140737354125687L, 'RAX': 3721L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_77(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 534L, 'R14D': 4783016L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125685L, 'RAX': 3723L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 2L, 'RSI': 140737488345638L, 'RDI': 140737354125685L, 'RAX': 3723L, 'RSP': 140737488344192L, 'RDX': 2L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_78(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792728L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 120L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_79(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_8(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 530L, 'R14D': 4783016L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'RAX': 3727L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 1089L, 'RSI': 4783036L, 'RDI': 140737354125681L, 'RAX': 3727L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_80(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 7059656L, 'RFLAGS': 514L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 7059656L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322407L, 'RBP': 140737488346472L}, 'memory': {4322408L: '\xc0', 4322407L: '1'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 29L, 'RSI': 1L, 'RDI': 4793949L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322409L, 'RBP': 140737488346472L}, 'memory': {4322408L: '\xc0', 4322407L: '1'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_81(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4371072L, 'RFLAGS': 514L, 'RCX': 57634L, 'RSI': 1L, 'RDI': 4782912L, 'RAX': 4371072L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329767L, 'RBP': 140737488345936L}, 'memory': {4329768L: '\xc0', 4329767L: '1'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 57634L, 'RSI': 1L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488344256L, 'RDX': 7059408L, 'RIP': 4329769L, 'RBP': 140737488345936L}, 'memory': {4329768L: '\xc0', 4329767L: '1'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_82(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'EDX': 78L, 'RAX': 4078L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125330L, 'EDX': 0L, 'RAX': 4078L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_83(self):
''' Instruction XOR R8D, [RDI+0x8] '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R8D': 0L, 'RFLAGS': 515L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 4297248L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297248L, 'RBP': 0L}, 'memory': {140737488347200: '\x17', 140737488347201: '\x00', 140737488347202: '\x00', 140737488347203: '\x00', 140737488347204: '\x00', 140737488347205: '\x00', 140737488347206: '\x00', 140737488347207: '\x00', 4297248L: 'D', 4297249L: '3', 4297250L: 'G', 4297251L: '\x08', 140737488347176: '\xe8', 140737488347177: '\x03', 140737488347178: '\x00', 140737488347179: '\x00', 140737488347180: '\x00', 140737488347181: '\x00', 140737488347182: '\x00', 140737488347183: '\x00', 140737488347184: '\x0e', 140737488347185: '\x00', 140737488347186: '\x00', 140737488347187: '\x00', 140737488347188: '\x00', 140737488347189: '\x00', 140737488347190: '\x00', 140737488347191: '\x00', 140737488347192: '\xe8', 140737488347193: '\x03', 140737488347194: '\x00', 140737488347195: '\x00', 140737488347196: '\x00', 140737488347197: '\x00', 140737488347198: '\x00', 140737488347199: '\x00'}}, 'text': 'D3G\x08', 'pos': {'registers': {'R8D': 1000L, 'RFLAGS': 518L, 'RCX': 3L, 'RSI': 0L, 'RDI': 140737488347168L, 'RAX': 4297248L, 'RSP': 140737488346232L, 'RDX': 4793504L, 'RIP': 4297252L, 'RBP': 0L}, 'memory': {140737488347200: '\x17', 140737488347201: '\x00', 140737488347202: '\x00', 140737488347203: '\x00', 140737488347204: '\x00', 140737488347205: '\x00', 140737488347206: '\x00', 140737488347207: '\x00', 4297248L: 'D', 4297249L: '3', 4297250L: 'G', 4297251L: '\x08', 140737488347176: '\xe8', 140737488347177: '\x03', 140737488347178: '\x00', 140737488347179: '\x00', 140737488347180: '\x00', 140737488347181: '\x00', 140737488347182: '\x00', 140737488347183: '\x00', 140737488347184: '\x0e', 140737488347185: '\x00', 140737488347186: '\x00', 140737488347187: '\x00', 140737488347188: '\x00', 140737488347189: '\x00', 140737488347190: '\x00', 140737488347191: '\x00', 140737488347192: '\xe8', 140737488347193: '\x03', 140737488347194: '\x00', 140737488347195: '\x00', 140737488347196: '\x00', 140737488347197: '\x00', 140737488347198: '\x00', 140737488347199: '\x00'}}, 'disassembly': 'XOR R8D, [RDI+0x8]', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_84(self):
''' Instruction XOR R9D, R9D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 518L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'R9D': 15L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661209L, 'RBP': 4096L}, 'memory': {4661209L: 'E', 4661210L: '1', 4661211L: '\xc9'}}, 'text': 'E1\xc9', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 18446744073709551615L, 'RSI': 21505L, 'RDI': 1L, 'R9D': 0L, 'RAX': 4096L, 'RSP': 140737488343968L, 'RDX': 18446744073709551568L, 'RIP': 4661212L, 'RBP': 4096L}, 'memory': {4661209L: 'E', 4661210L: '1', 4661211L: '\xc9'}}, 'disassembly': 'XOR R9D, R9D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_85(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 518L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792712L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 103L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_86(self):
''' Instruction XOR R14D, R14D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 534L, 'R14D': 4782888L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 4083L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392627L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'text': 'E1\xf6', 'pos': {'registers': {'RFLAGS': 582L, 'R14D': 0L, 'RCX': 4294967292L, 'RSI': 4782905L, 'RDI': 140737354125325L, 'RAX': 4083L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392627L: 'E', 4392628L: '1', 4392629L: '\xf6'}}, 'disassembly': 'XOR R14D, R14D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_87(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322542L, 'RBP': 0L}, 'memory': {4322542L: '1', 4322543L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 41L, 'RSI': 1L, 'RDI': 4793961L, 'RAX': 0L, 'RSP': 140737488346064L, 'RDX': 11L, 'RIP': 4322544L, 'RBP': 0L}, 'memory': {4322542L: '1', 4322543L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_88(self):
''' Instruction XOR R8D, R8D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R8D': 4294967295L, 'RFLAGS': 514L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338614L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'text': 'E1\xc0', 'pos': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 100L, 'RSI': 4782888L, 'RDI': 7065768L, 'RAX': 21L, 'RSP': 140737488344256L, 'RDX': 16L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'disassembly': 'XOR R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_89(self):
''' Instruction XOR EBX, EBX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 194L, 'EBX': 15774463L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284033L, 'RBP': 9L}, 'memory': {4284033L: '1', 4284034L: '\xdb'}}, 'text': '1\xdb', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 63L, 'RSI': 29360191L, 'RDI': 194L, 'EBX': 0L, 'RAX': 469778721L, 'RSP': 140737488345968L, 'RDX': 1L, 'RIP': 4284035L, 'RBP': 9L}, 'memory': {4284033L: '1', 4284034L: '\xdb'}}, 'disassembly': 'XOR EBX, EBX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_9(self):
''' Instruction XOR R15D, R15D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R15D': 4792416L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320808L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'text': 'E1\xff', 'pos': {'registers': {'R15D': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792416L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345888L, 'RDX': 6L, 'RIP': 4320811L, 'RBP': 4792416L}, 'memory': {4320808L: 'E', 4320809L: '1', 4320810L: '\xff'}}, 'disassembly': 'XOR R15D, R15D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_90(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 534L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'EDX': 0L, 'RAX': 9L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392569L, 'RBP': 7049504L}, 'memory': {4392569L: '1', 4392570L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4096L, 'RSI': 140737354125312L, 'RDI': 7049504L, 'EDX': 0L, 'RAX': 9L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392571L, 'RBP': 7049504L}, 'memory': {4392569L: '1', 4392570L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_91(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 1L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 1L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792824L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 134L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_92(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_93(self):
''' Instruction XOR RAX, RAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 514L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 18L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239584L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'text': 'H1\xc0', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4782904L, 'RSI': 140737354125330L, 'RDI': 4782912L, 'RAX': 0L, 'RSP': 140737488346120L, 'RDX': 7059408L, 'RIP': 4239587L, 'RBP': 4782912L}, 'memory': {4239584L: 'H', 4239585L: '1', 4239586L: '\xc0'}}, 'disassembly': 'XOR RAX, RAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_94(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'EDX': 1L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 1L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 1L, 'RSI': 140737488345639L, 'RDI': 140737354125667L, 'EDX': 0L, 'RAX': 3741L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_95(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 140737354125646L, 'EDX': 4L, 'RAX': 3762L, 'RSP': 140737488344192L, 'RDX': 4L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 4L, 'RSI': 4782991L, 'RDI': 140737354125646L, 'EDX': 0L, 'RAX': 3762L, 'RSP': 140737488344192L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_96(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792704L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 102L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_97(self):
''' Instruction XOR R8D, R8D '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'R8D': 4L, 'RFLAGS': 518L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338614L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'text': 'E1\xc0', 'pos': {'registers': {'R8D': 0L, 'RFLAGS': 582L, 'RCX': 100L, 'RSI': 140737354125685L, 'RDI': 140737354125681L, 'RAX': 43L, 'RSP': 140737488344256L, 'RDX': 32L, 'RIP': 4338617L, 'RBP': 140737488345936L}, 'memory': {4338616L: '\xc0', 4338614L: 'E', 4338615L: '1'}}, 'disassembly': 'XOR R8D, R8D', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_98(self):
''' Instruction XOR EDX, EDX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'EDX': 78L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 78L, 'RIP': 4392630L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'text': '1\xd2', 'pos': {'registers': {'RFLAGS': 582L, 'RCX': 0L, 'RSI': 4782912L, 'RDI': 140737354125774L, 'EDX': 0L, 'RAX': 3634L, 'RSP': 140737488346064L, 'RDX': 0L, 'RIP': 4392632L, 'RBP': 7049504L}, 'memory': {4392630L: '1', 4392631L: '\xd2'}}, 'disassembly': 'XOR EDX, EDX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
def testXOR_99(self):
''' Instruction XOR EAX, EAX '''
test = {'mnemonic': 'XOR', 'pre': {'registers': {'EAX': 4294967295L, 'RFLAGS': 514L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 4294967295L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283331L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'text': '1\xc0', 'pos': {'registers': {'EAX': 0L, 'RFLAGS': 582L, 'RCX': 8L, 'RSI': 4792424L, 'RDI': 140737488345968L, 'RAX': 0L, 'RSP': 140737488345880L, 'RDX': 8L, 'RIP': 4283333L, 'RBP': 4792416L}, 'memory': {4283331L: '1', 4283332L: '\xc0'}}, 'disassembly': 'XOR EAX, EAX', 'arch': 'amd64'}
mem = CPUTest.Mem(test['pre']['memory'])
cpu = Cpu(mem, test['arch'])
for reg_name in test['pre']['registers']:
cpu.setRegister(reg_name, test['pre']['registers'][reg_name])
cpu.execute()
for addr in mem.mem:
self.assertEqual(mem.getchar(addr), test['pos']['memory'][addr], "Memory at address %016x doesn't match %s vs %s"%(addr, repr(mem.getchar(addr)), repr(test['pos']['memory'][addr])))
for reg_name in test['pos']['registers']:
if 'FLAG' in reg_name:
self.assertEqual(cpu.getRegister(reg_name)&0x8c5, test['pos']['registers'][reg_name]&0x8c5, "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
else:
self.assertEqual(cpu.getRegister(reg_name), test['pos']['registers'][reg_name], "%s doesn't match %x vs %x"%(reg_name,cpu.getRegister(reg_name), test['pos']['registers'][reg_name]))
if __name__ == '__main__':
unittest.main()
|
2f57bb11bff21959fc6f3134cf70e2cc791d4b99
|
eb9f655206c43c12b497c667ba56a0d358b6bc3a
|
/python/helpers/generator3/util_methods.py
|
5afbbccbee1d4ffdd54e5632885510e6689a120f
|
[
"Apache-2.0"
] |
permissive
|
JetBrains/intellij-community
|
2ed226e200ecc17c037dcddd4a006de56cd43941
|
05dbd4575d01a213f3f4d69aa4968473f2536142
|
refs/heads/master
| 2023-09-03T17:06:37.560889
| 2023-09-03T11:51:00
| 2023-09-03T12:12:27
| 2,489,216
| 16,288
| 6,635
|
Apache-2.0
| 2023-09-12T07:41:58
| 2011-09-30T13:33:05
| null |
UTF-8
|
Python
| false
| false
| 28,171
|
py
|
util_methods.py
|
import ast
import collections
import errno
import functools
import hashlib
import json
import keyword
import logging
import multiprocessing
import shutil
from contextlib import contextmanager
from generator3.constants import *
try:
import inspect
except ImportError:
inspect = None
BIN_READ_BLOCK = 64 * 1024
def create_named_tuple(): #TODO: user-skeleton
return """
class __namedtuple(tuple):
'''A mock base class for named tuples.'''
__slots__ = ()
_fields = ()
def __new__(cls, *args, **kwargs):
'Create a new instance of the named tuple.'
return tuple.__new__(cls, *args)
@classmethod
def _make(cls, iterable, new=tuple.__new__, len=len):
'Make a new named tuple object from a sequence or iterable.'
return new(cls, iterable)
def __repr__(self):
return ''
def _asdict(self):
'Return a new dict which maps field types to their values.'
return {}
def _replace(self, **kwargs):
'Return a new named tuple object replacing specified fields with new values.'
return self
def __getnewargs__(self):
return tuple(self)
"""
def create_generator():
# Fake <type 'generator'>
if version[0] < 3:
next_name = "next"
else:
next_name = "__next__"
txt = """
class __generator(object):
'''A mock class representing the generator function type.'''
def __init__(self):
self.gi_code = None
self.gi_frame = None
self.gi_running = 0
def __iter__(self):
'''Defined to support iteration over container.'''
pass
def %s(self):
'''Return the next item from the container.'''
pass
""" % (next_name,)
if version[0] >= 3 or (version[0] == 2 and version[1] >= 5):
txt += """
def close(self):
'''Raises new GeneratorExit exception inside the generator to terminate the iteration.'''
pass
def send(self, value):
'''Resumes the generator and "sends" a value that becomes the result of the current yield-expression.'''
pass
def throw(self, type, value=None, traceback=None):
'''Used to raise an exception inside the generator.'''
pass
"""
return txt
def create_async_generator():
# Fake <type 'asyncgenerator'>
txt = """
class __asyncgenerator(object):
'''A mock class representing the async generator function type.'''
def __init__(self):
'''Create an async generator object.'''
self.__name__ = ''
self.__qualname__ = ''
self.ag_await = None
self.ag_frame = None
self.ag_running = False
self.ag_code = None
def __aiter__(self):
'''Defined to support iteration over container.'''
pass
def __anext__(self):
'''Returns an awaitable, that performs one asynchronous generator iteration when awaited.'''
pass
def aclose(self):
'''Returns an awaitable, that throws a GeneratorExit exception into generator.'''
pass
def asend(self, value):
'''Returns an awaitable, that pushes the value object in generator.'''
pass
def athrow(self, type, value=None, traceback=None):
'''Returns an awaitable, that throws an exception into generator.'''
pass
"""
return txt
def create_function():
txt = """
class __function(object):
'''A mock class representing function type.'''
def __init__(self):
self.__name__ = ''
self.__doc__ = ''
self.__dict__ = ''
self.__module__ = ''
"""
if version[0] == 2:
txt += """
self.func_defaults = {}
self.func_globals = {}
self.func_closure = None
self.func_code = None
self.func_name = ''
self.func_doc = ''
self.func_dict = ''
"""
if version[0] >= 3 or (version[0] == 2 and version[1] >= 6):
txt += """
self.__defaults__ = {}
self.__globals__ = {}
self.__closure__ = None
self.__code__ = None
self.__name__ = ''
"""
if version[0] >= 3:
txt += """
self.__annotations__ = {}
self.__kwdefaults__ = {}
"""
if version[0] >= 3 and version[1] >= 3:
txt += """
self.__qualname__ = ''
"""
return txt
def create_method():
txt = """
class __method(object):
'''A mock class representing method type.'''
def __init__(self):
"""
if version[0] == 2:
txt += """
self.im_class = None
self.im_self = None
self.im_func = None
"""
if version[0] >= 3 or (version[0] == 2 and version[1] >= 6):
txt += """
self.__func__ = None
self.__self__ = None
"""
return txt
def create_coroutine():
if version[0] == 3 and version[1] >= 5:
return """
class __coroutine(object):
'''A mock class representing coroutine type.'''
def __init__(self):
self.__name__ = ''
self.__qualname__ = ''
self.cr_await = None
self.cr_frame = None
self.cr_running = False
self.cr_code = None
def __await__(self):
return []
def close(self):
pass
def send(self, value):
pass
def throw(self, type, value=None, traceback=None):
pass
"""
return ""
def _searchbases(cls, accum):
# logic copied from inspect.py
if cls not in accum:
accum.append(cls)
for x in cls.__bases__:
_searchbases(x, accum)
def get_mro(a_class):
# logic copied from inspect.py
"""Returns a tuple of MRO classes."""
if hasattr(a_class, "__mro__"):
return a_class.__mro__
elif hasattr(a_class, "__bases__"):
bases = []
_searchbases(a_class, bases)
return tuple(bases)
else:
return tuple()
def get_bases(a_class): # TODO: test for classes that don't fit this scheme
"""Returns a sequence of class's bases."""
if hasattr(a_class, "__bases__"):
return a_class.__bases__
else:
return ()
def is_callable(x):
return hasattr(x, '__call__')
def sorted_no_case(p_array):
"""Sort an array case insensitively, returns a sorted copy"""
p_array = list(p_array)
p_array = sorted(p_array, key=lambda x: x.upper())
return p_array
def cleanup(value):
result = []
prev = i = 0
length = len(value)
last_ascii = chr(127)
while i < length:
char = value[i]
replacement = None
if char == '\n':
replacement = '\\n'
elif char == '\r':
replacement = '\\r'
elif char < ' ' or char > last_ascii:
replacement = '?' # NOTE: such chars are rare; long swaths could be precessed differently
if replacement:
result.append(value[prev:i])
result.append(replacement)
prev = i + 1
i += 1
result.append(value[prev:])
return "".join(result)
def is_valid_expr(s):
try:
compile(s, '<unknown>', 'eval', ast.PyCF_ONLY_AST)
except SyntaxError:
return False
return True
_prop_types = [type(property())]
#noinspection PyBroadException
try:
_prop_types.append(types.GetSetDescriptorType)
except:
pass
#noinspection PyBroadException
try:
_prop_types.append(types.MemberDescriptorType)
except:
pass
_prop_types = tuple(_prop_types)
def is_property(x):
return isinstance(x, _prop_types)
def reliable_repr(value):
# some subclasses of built-in types (see PyGtk) may provide invalid __repr__ implementations,
# so we need to sanitize the output
if type(bool) == type and isinstance(value, bool):
return repr(bool(value))
for num_type in NUM_TYPES:
if isinstance(value, num_type):
return repr(num_type(value))
return repr(value)
def sanitize_value(p_value):
"""Returns p_value or its part if it represents a sane simple value, else returns 'None'"""
if isinstance(p_value, STR_TYPES):
match = SIMPLE_VALUE_RE.match(p_value)
if match:
return match.groups()[match.lastindex - 1]
else:
return 'None'
elif isinstance(p_value, NUM_TYPES):
return reliable_repr(p_value)
elif p_value is None:
return 'None'
else:
if hasattr(p_value, "__name__") and hasattr(p_value, "__module__") and p_value.__module__ == BUILTIN_MOD_NAME:
return p_value.__name__ # float -> "float"
else:
return repr(repr(p_value)) # function -> "<function ...>", etc
def report(msg, *data):
"""Say something at error level (stderr)"""
sys.stderr.write(msg % data)
sys.stderr.write("\n")
def say(msg, *data):
"""Say something at info level (stdout)"""
sys.stdout.write(msg % data)
sys.stdout.write("\n")
sys.stdout.flush()
def flatten(seq):
"""Transforms tree lists like ['a', ['b', 'c'], 'd'] to strings like '(a, (b, c), d)', enclosing each tree level in parens."""
ret = []
for one in seq:
if type(one) is list:
ret.append(flatten(one))
else:
ret.append(one)
return "(" + ", ".join(ret) + ")"
def make_names_unique(seq, name_map=None):
"""
Returns a copy of tree list seq where all clashing names are modified by numeric suffixes:
['a', 'b', 'a', 'b'] becomes ['a', 'b', 'a_1', 'b_1'].
Each repeating name has its own counter in the name_map.
"""
ret = []
if not name_map:
name_map = {}
for one in seq:
if type(one) is list:
ret.append(make_names_unique(one, name_map))
else:
if keyword.iskeyword(one):
one += "_"
one_key = lstrip(one, "*") # starred parameters are unique sans stars
if one_key in name_map:
old_one = one_key
one = one + "_" + str(name_map[old_one])
name_map[old_one] += 1
else:
name_map[one_key] = 1
ret.append(one)
return ret
def out_docstring(out_func, docstring, indent):
if not isinstance(docstring, str): return
lines = docstring.strip().split("\n")
if lines:
if len(lines) == 1:
out_func(indent, '""" ' + lines[0] + ' """')
else:
out_func(indent, '"""')
for line in lines:
try:
out_func(indent, line)
except UnicodeEncodeError:
continue
out_func(indent, '"""')
def out_doc_attr(out_func, p_object, indent, p_class=None):
the_doc = getattr(p_object, "__doc__", None)
if the_doc:
if p_class and the_doc == object.__init__.__doc__ and p_object is not object.__init__ and p_class.__doc__:
the_doc = str(p_class.__doc__) # replace stock init's doc with class's; make it a certain string.
the_doc += "\n# (copied from class doc)"
out_docstring(out_func, the_doc, indent)
else:
out_func(indent, "# no doc")
def is_skipped_in_module(p_module, p_value):
"""
Returns True if p_value's value must be skipped for module p_module.
"""
skip_list = SKIP_VALUE_IN_MODULE.get(p_module, [])
if p_value in skip_list:
return True
skip_list = SKIP_VALUE_IN_MODULE.get("*", [])
if p_value in skip_list:
return True
return False
def restore_predefined_builtin(class_name, func_name):
spec = func_name + PREDEFINED_BUILTIN_SIGS[(class_name, func_name)]
note = "known special case of " + (class_name and class_name + "." or "") + func_name
return (spec, note)
def restore_by_inspect(p_func):
"""
Returns paramlist restored by inspect.
"""
args, varg, kwarg, defaults, kwonlyargs, kwonlydefaults, _ = getfullargspec(p_func)
spec = []
if defaults:
dcnt = len(defaults) - 1
else:
dcnt = -1
args = args or []
args.reverse() # backwards, for easier defaults handling
for arg in args:
if dcnt >= 0:
arg += "=" + sanitize_value(defaults[dcnt])
dcnt -= 1
spec.insert(0, arg)
if varg:
spec.append("*" + varg)
elif kwonlyargs:
spec.append("*")
kwonlydefaults = kwonlydefaults or {}
for arg in kwonlyargs:
if arg in kwonlydefaults:
spec.append(arg + '=' + sanitize_value(kwonlydefaults[arg]))
else:
spec.append(arg)
if kwarg:
spec.append("**" + kwarg)
return flatten(spec)
def restore_parameters_for_overloads(parameter_lists):
param_index = 0
star_args = False
optional = False
params = []
while True:
parameter_lists_copy = [pl for pl in parameter_lists]
for pl in parameter_lists_copy:
if param_index >= len(pl):
parameter_lists.remove(pl)
optional = True
if not parameter_lists:
break
name = parameter_lists[0][param_index]
for pl in parameter_lists[1:]:
if pl[param_index] != name:
star_args = True
break
if star_args: break
if optional and not '=' in name:
params.append(name + '=None')
else:
params.append(name)
param_index += 1
if star_args:
params.append("*__args")
return params
def build_signature(p_name, params):
return p_name + '(' + ', '.join(params) + ')'
def propose_first_param(deco):
"""@return: name of missing first paramater, considering a decorator"""
if deco is None:
return "self"
if deco == "classmethod":
return "cls"
# if deco == "staticmethod":
return None
def qualifier_of(cls, qualifiers_to_skip):
m = getattr(cls, "__module__", None)
if m in qualifiers_to_skip:
return ""
return m
def handle_error_func(item_name, out):
exctype, value = sys.exc_info()[:2]
msg = "Error generating skeleton for function %s: %s"
args = item_name, value
report(msg, *args)
out(0, "# " + msg % args)
out(0, "")
def format_accessors(accessor_line, getter, setter, deleter):
"""Nicely format accessors, like 'getter, fdel=deleter'"""
ret = []
consecutive = True
for key, arg, par in (('r', 'fget', getter), ('w', 'fset', setter), ('d', 'fdel', deleter)):
if key in accessor_line:
if consecutive:
ret.append(par)
else:
ret.append(arg + "=" + par)
else:
consecutive = False
return ", ".join(ret)
def has_regular_python_ext(file_name):
"""Does name end with .py?"""
return file_name.endswith(".py")
# Note that the standard library on MacOS X 10.6 is shipped only as .pyc files, so we need to
# have them processed by the generator in order to have any code insight for the standard library.
def detect_constructor(p_class):
# try to inspect the thing
constr = getattr(p_class, "__init__")
if constr and inspect and inspect.isfunction(constr):
args, _, _, _, kwonlyargs, _, _ = getfullargspec(constr)
return ", ".join(args + [a + '=' + a for a in kwonlyargs])
else:
return None
############## notes, actions #################################################################
_is_verbose = False # controlled by -v
CURRENT_ACTION = "nothing yet"
def action(msg, *data):
global CURRENT_ACTION
CURRENT_ACTION = msg % data
note(msg, *data)
def set_verbose(verbose):
global _is_verbose
_is_verbose = verbose
def note(msg, *data):
"""Say something at debug info level (stderr)"""
if _is_verbose:
sys.stderr.write(msg % data)
sys.stderr.write("\n")
############## plaform-specific methods #######################################################
import sys
if sys.platform == 'cli':
#noinspection PyUnresolvedReferences
import clr
# http://blogs.msdn.com/curth/archive/2009/03/29/an-ironpython-profiler.aspx
def print_profile():
data = []
data.extend(clr.GetProfilerData())
data.sort(lambda x, y: -cmp(x.ExclusiveTime, y.ExclusiveTime))
for pd in data:
say('%s\t%d\t%d\t%d', pd.Name, pd.InclusiveTime, pd.ExclusiveTime, pd.Calls)
def is_clr_type(clr_type):
if not clr_type: return False
try:
clr.GetClrType(clr_type)
return True
except TypeError:
return False
def restore_clr(p_name, p_class):
"""
Restore the function signature by the CLR type signature
:return (is_static, spec, sig_note)
"""
clr_type = clr.GetClrType(p_class)
if p_name == '__new__':
methods = [c for c in clr_type.GetConstructors()]
if not methods:
return False, p_name + '(self, *args)', 'cannot find CLR constructor' # "self" is always first argument of any non-static method
else:
methods = [m for m in clr_type.GetMethods() if m.Name == p_name]
if not methods:
bases = p_class.__bases__
if len(bases) == 1 and p_name in dir(bases[0]):
# skip inherited methods
return False, None, None
return False, p_name + '(self, *args)', 'cannot find CLR method'
# "self" is always first argument of any non-static method
parameter_lists = []
for m in methods:
parameter_lists.append([p.Name for p in m.GetParameters()])
params = restore_parameters_for_overloads(parameter_lists)
is_static = False
if not methods[0].IsStatic:
params = ['self'] + params
else:
is_static = True
return is_static, build_signature(p_name, params), None
def build_pkg_structure(base_dir, qname):
if not qname:
return base_dir
subdirname = base_dir
for part in qname.split("."):
subdirname = os.path.join(subdirname, part)
if not os.path.isdir(subdirname):
action("creating subdir %r", subdirname)
os.makedirs(subdirname)
init_py = os.path.join(subdirname, "__init__.py")
if os.path.isfile(subdirname + ".py"):
os.rename(subdirname + ".py", init_py)
elif not os.path.isfile(init_py):
fopen(init_py, "w").close()
return subdirname
def is_valid_implicit_namespace_package_name(s):
"""
Checks whether provided string could represent implicit namespace package name.
:param s: string to check
:return: True if provided string could represent implicit namespace package name and False otherwise
"""
return isidentifier(s) and not keyword.iskeyword(s)
def isidentifier(s):
"""
Checks whether provided string complies Python identifier syntax requirements.
:param s: string to check
:return: True if provided string comply Python identifier syntax requirements and False otherwise
"""
if version[0] >= 3:
return s.isidentifier()
else:
# quick test on provided string to comply major Python identifier syntax requirements
return (s and
not s[:1].isdigit() and
"-" not in s and
" " not in s)
@contextmanager
def ignored_os_errors(*errno):
try:
yield
# Since Python 3.3 IOError and OSError were merged into OSError
except EnvironmentError as e:
if e.errno not in errno:
raise
def mkdir(path):
try:
os.makedirs(path)
except EnvironmentError as e:
if e.errno != errno.EEXIST or not os.path.isdir(path):
raise
def copy(src, dst, merge=False, pre_copy_hook=None, conflict_handler=None, post_copy_hook=None):
if pre_copy_hook is None:
def pre_copy_hook(p1, p2):
return True
if conflict_handler is None:
def conflict_handler(p1, p2):
return False
if post_copy_hook is None:
def post_copy_hook(p1, p2):
pass
if not pre_copy_hook(src, dst):
return
# Note about shutil.copy vs shutil.copy2.
# There is an open CPython bug which breaks copy2 on NFS when it tries to copy the xattr.
# https://bugs.python.org/issue24564
# https://youtrack.jetbrains.com/issue/PY-37523
# However, in all our use cases, we do not care about the xattr,
# so just always use shutil.copy to avoid this problem.
if os.path.isdir(src):
if not merge:
if version[0] >= 3:
shutil.copytree(src, dst, copy_function=shutil.copy)
else:
shutil.copytree(src, dst)
else:
mkdir(dst)
for child in os.listdir(src):
child_src = os.path.join(src, child)
child_dst = os.path.join(dst, child)
try:
copy(child_src, child_dst, merge=merge,
pre_copy_hook=pre_copy_hook,
conflict_handler=conflict_handler,
post_copy_hook=post_copy_hook)
except OSError as e:
if e.errno == errno.EEXIST and not (os.path.isdir(child_src) and os.path.isdir(child_dst)):
if conflict_handler(child_src, child_dst):
continue
raise
else:
mkdir(os.path.dirname(dst))
shutil.copy(src, dst)
post_copy_hook(src, dst)
def copy_skeletons(src_dir, dst_dir, new_origin=None):
def overwrite(src, dst):
delete(dst)
copy(src, dst)
return True
# Remove packages/modules with the same import name
def mod_pkg_cleanup(src, dst):
dst_dir = os.path.dirname(dst)
name, ext = os.path.splitext(os.path.basename(src))
if ext == '.py':
delete(os.path.join(dst_dir, name))
elif not ext:
delete(dst + '.py')
def override_origin_stamp(src, dst):
_, ext = os.path.splitext(dst)
if ext == '.py' and new_origin:
with fopen(dst, 'r') as f:
lines = f.readlines()
for i, line in enumerate(lines):
if not line.startswith('#'):
return
m = SKELETON_HEADER_ORIGIN_LINE.match(line)
if m:
break
else:
return
with fopen(dst, 'w') as f:
lines[i] = '# from ' + new_origin + '\n'
f.writelines(lines)
def post_copy_hook(src, dst):
override_origin_stamp(src, dst)
mod_pkg_cleanup(src, dst)
def ignore_failed_version_stamps(src, dst):
return not os.path.basename(src).startswith(FAILED_VERSION_STAMP_PREFIX)
copy(src_dir, dst_dir, merge=True,
pre_copy_hook=ignore_failed_version_stamps,
conflict_handler=overwrite,
post_copy_hook=post_copy_hook)
def delete(path, content=False):
with ignored_os_errors(errno.ENOENT):
if os.path.isdir(path):
if not content:
shutil.rmtree(path)
else:
for child in os.listdir(path):
delete(child)
else:
os.remove(path)
def cached(func):
func._results = {}
unknown = object()
# noinspection PyProtectedMember
@functools.wraps(func)
def wrapper(*args):
result = func._results.get(args, unknown)
if result is unknown:
result = func._results[args] = func(*args)
return result
return wrapper
def sha256_digest(binary_or_file):
# "bytes" type is available in Python 2.7
if isinstance(binary_or_file, bytes):
return hashlib.sha256(binary_or_file).hexdigest()
else:
acc = hashlib.sha256()
while True:
block = binary_or_file.read(BIN_READ_BLOCK)
if not block:
break
acc.update(block)
return acc.hexdigest()
def get_portable_test_module_path(abs_path, qname):
abs_path_components = os.path.normpath(abs_path).split(os.path.sep)
qname_components_count = len(qname.split('.'))
if os.path.splitext(abs_path_components[-1])[0] == '__init__':
rel_path_components_count = qname_components_count + 1
else:
rel_path_components_count = qname_components_count
return '/'.join(abs_path_components[-rel_path_components_count:])
def is_text_file(path):
"""
Verify that some path is a text file (not a binary file).
Ideally there should be usage of libmagic but it can be not
installed on a target machine.
Actually this algorithm is inspired by function `file_encoding`
from libmagic.
"""
try:
with open(path, 'rb') as candidate_stream:
# Buffer size like in libmagic
buffer = candidate_stream.read(256 * 1024)
except EnvironmentError:
return False
# Verify that it looks like ASCII, UTF-8 or UTF-16.
for encoding in 'utf-8', 'utf-16', 'utf-16-be', 'utf-16-le':
try:
buffer.decode(encoding)
except UnicodeDecodeError as err:
if err.args[0].endswith(('truncated data', 'unexpected end of data')):
return True
else:
return True
# Verify that it looks like ISO-8859 or non-ISO extended ASCII.
return all(c not in _bytes_that_never_appears_in_text for c in buffer)
_bytes_that_never_appears_in_text = set(range(7)) | {11} | set(range(14, 27)) | set(range(28, 32)) | {127}
# This wrapper is intentionally made top-level: local functions can't be pickled.
def _multiprocessing_wrapper(data, func, *args, **kwargs):
configure_logging(data.root_logger_level)
data.result_conn.send(func(*args, **kwargs))
_MainProcessData = collections.namedtuple('_MainProcessData', ['result_conn', 'root_logger_level'])
def execute_in_subprocess_synchronously(name, func, args, kwargs, failure_result=None):
import multiprocessing as mp
extra_process_kwargs = {}
if sys.version_info[0] >= 3:
extra_process_kwargs['daemon'] = True
# There is no need to use a full-blown queue for single producer/single consumer scenario.
# Also, Pipes don't suffer from issues such as https://bugs.python.org/issue35797.
# TODO experiment with a shared queue maintained by multiprocessing.Manager
# (it will require an additional service process)
recv_conn, send_conn = mp.Pipe(duplex=False)
data = _MainProcessData(result_conn=send_conn,
root_logger_level=logging.getLogger().level)
p = mp.Process(name=name,
target=_multiprocessing_wrapper,
args=(data, func) + args,
kwargs=kwargs,
**extra_process_kwargs)
p.start()
# This is actually against the multiprocessing guidelines
# https://docs.python.org/3/library/multiprocessing.html#programming-guidelines
# but allows us to fail-fast if the child process terminated abnormally with a segfault
# (otherwise we would have to wait by timeout on acquiring the result) and should work
# fine for small result values such as generation status.
p.join()
if recv_conn.poll():
return recv_conn.recv()
else:
return failure_result
def configure_logging(root_level):
logging.addLevelName(logging.DEBUG - 1, 'TRACE')
root = logging.getLogger()
root.setLevel(root_level)
# In environments where fork is implemented entire logging configuration is already inherited by child processes.
# Configuring it twice will lead to duplicated records.
# Reset logger similarly to how it's done in logging.config
for h in root.handlers[:]:
root.removeHandler(h)
for f in root.filters[:]:
root.removeFilter(f)
class JsonFormatter(logging.Formatter):
def format(self, record):
s = super(JsonFormatter, self).format(record)
return json.dumps({
'type': 'log',
'level': record.levelname.lower(),
'message': s
})
handler = logging.StreamHandler(sys.stdout)
handler.setFormatter(JsonFormatter())
root.addHandler(handler)
|
7dfa22c501f4ce123a6d400c763de2d1b29fbad8
|
8e342677ebe58bfb6c7360b555044acc6964f333
|
/src/einsteinpy/hypersurface/schwarzschildembedding.py
|
a2264112ff475dc046df3cf428fd2dfc85e8d754
|
[
"LicenseRef-scancode-proprietary-license",
"MIT"
] |
permissive
|
einsteinpy/einsteinpy
|
5d48142cab52f7c629d78b47088d804ff3eafae9
|
1bd1b27e142b0a0ec2e26bf2611468dbf50d9cf8
|
refs/heads/main
| 2023-08-17T19:17:34.239265
| 2023-01-31T20:43:54
| 2023-01-31T20:43:54
| 168,302,584
| 594
| 292
|
MIT
| 2023-08-12T07:30:41
| 2019-01-30T07:56:15
|
Python
|
UTF-8
|
Python
| false
| false
| 4,910
|
py
|
schwarzschildembedding.py
|
import warnings
import numpy as np
from astropy import units as u
from matplotlib import pyplot as plt
class SchwarzschildEmbedding:
"""
Class for Utility functions for Schwarzschild Embedding surface to
implement gravitational lensing
Attributes
----------
input_units : list
list of input units of M
units_list : list
customized units to handle values of M and render plots
within grid range
r_init : ~astropy.units.m
"""
def __init__(self, M):
"""
Constructor
Initialize mass and embedding initial radial coordinate in appropiate units
in order to render the plots of the surface in finite grid. The initial r
is taken to be just greater than schwarzschild radius but it is important
to note that the embedding breaks at r < 9m/4.
Parameters
----------
M : ~astropy.units.kg
Mass of the body
"""
self.input_units = [M.unit]
self.units_list = [u.kg * 10e22, u.m / M.to(u.kg * 10e22).value]
M = M.to(self.units_list[0])
self.M = M
self.r_init = (((3 * self.M.value + 0.0001) / self.M.value) * u.m).to(
self.units_list[1]
)
def gradient(self, r):
"""
Calculate gradient of Z coordinate w.r.t r to update the value of r and
thereby get value of spherical radial coordinate R.
Parameters
----------
r : float
schwarzschild coordinate at which gradient is supposed to be obtained
Returns
-------
float
gradient of Z w.r.t r at the point r (passed as argument)
"""
R = r / np.sqrt(1 - (2 * self.M.value / r))
num_one = 1 - (3 * self.M.value / r)
num_two = np.sqrt(
((4 * self.M.value * r - 9 * self.M.value * self.M.value) * R)
/ (r - 3 * self.M.value) ** 2
)
deno = np.sqrt(1 - (2 * self.M.value / r)) ** 3
return num_one * num_two / deno
def radial_coord(self, r):
"""
Returns spherical radial coordinate (of the embedding) from given schwarzschild
coordinate.
Parameters
----------
r : float
Returns
-------
float
spherical radial coordinate of the 3d embedding
"""
return r / np.sqrt(1 - (2 * self.M.value / r))
def get_values(self, alpha):
"""
Obtain the Z coordinate values and corrosponding R values for range of
r as 9m/4 < r < 9m.
Parameters
----------
alpha : float
scaling factor to obtain the step size for incrementing r
Returns
-------
tuple
(list, list) : values of R (x_axis) and Z (y_axis)
"""
x_axis = []
y_axis = []
r_initial = self.r_init.value
r_step = self.M.value / alpha
z = 0
r = r_initial
while r < 9 * self.M.value:
x_axis.append(self.radial_coord(r))
y_axis.append(z)
z = z + self.gradient(r) * r_step
r = r + r_step
z = 0
r = r_initial
while r > (9 * self.M.value / 4):
x_axis.append(self.radial_coord(r))
y_axis.append(z)
z = z + self.gradient(r) * r_step
r = r - r_step
return x_axis, y_axis
def get_values_surface(self, alpha):
"""
Obtain the same values as of the get_values function but reshapes them to obtain
values for all points on the solid of revolution about Z axis (as the
embedding is symmetric in angular coordinates).
Parameters
----------
alpha : float
scaling factor to obtain the step size for incrementing r
Returns
-------
tuple
(~numpy.array of X, ~numpy.array of Y, ~numpy.array of Z) values in cartesian coordinates
obtained after applying solid of revolution
"""
r_initial = self.r_init.value
r_step = self.M.value / alpha
phi_values = np.linspace(0, 2 * np.pi, 60)
R_values = []
z_values = []
z = 0
r = r_initial
while r < 20 * self.M.value:
R_values.append(self.radial_coord(r))
z_values.append(z)
z = z + self.gradient(r) * r_step
r = r + r_step
R_values = np.array(R_values)
R_values, phi_values = np.meshgrid(R_values, phi_values)
X = R_values * np.cos(phi_values)
Y = R_values * np.sin(phi_values)
x_len = X.shape[0]
Z = np.array(z_values)
z_values = np.array(z_values)
for i in range(0, x_len - 1):
Z = np.concatenate((Z, z_values), axis=0)
Z.reshape((X.shape[0], X.shape[1]))
return X, Y, Z
|
9bc62ed910a5d2f3b977e59d84ff8fe6f65dbd40
|
aa2ae30a88361b4b80ffa28c4d8a54600bbee542
|
/Chapter12/tmp/00_pong_pg.py
|
565e86e5df717a6904a52ed4b3252c8507cf23d1
|
[
"MIT"
] |
permissive
|
PacktPublishing/Deep-Reinforcement-Learning-Hands-On-Second-Edition
|
6728fadb38076f6243da3d98b1cf18faf6b287af
|
d5a421d63c6d3ebbdfa54537fa5ce485bc2b9220
|
refs/heads/master
| 2023-07-05T23:08:32.621622
| 2022-01-17T12:18:54
| 2022-01-17T12:18:54
| 195,020,985
| 963
| 491
|
MIT
| 2023-03-25T01:00:07
| 2019-07-03T09:21:47
|
Jupyter Notebook
|
UTF-8
|
Python
| false
| false
| 5,430
|
py
|
00_pong_pg.py
|
#!/usr/bin/env python3
import gym
import ptan
import numpy as np
import argparse
import collections
from tensorboardX import SummaryWriter
import torch
import torch.nn.functional as F
import torch.nn.utils as nn_utils
import torch.optim as optim
from torch.autograd import Variable
from lib import common
GAMMA = 0.99
LEARNING_RATE = 0.0001
ENTROPY_BETA = 0.02
BATCH_SIZE = 32
REWARD_STEPS = 10
BASELINE_STEPS = 1000000
GRAD_L2_CLIP = 0.1
ENV_COUNT = 50
USE_MEAN_BASELINE = True
def make_env():
return ptan.common.wrappers.wrap_dqn(gym.make("PongNoFrameskip-v4"))
class MeanBuffer:
def __init__(self, capacity):
self.capacity = capacity
self.deque = collections.deque(maxlen=capacity)
self.sum = 0.0
def add(self, val):
if len(self.deque) == self.capacity:
self.sum -= self.deque[0]
self.deque.append(val)
self.sum += val
def mean(self):
if not self.deque:
return 0.0
return self.sum / len(self.deque)
if __name__ == "__main__":
parser = argparse.ArgumentParser()
parser.add_argument("--cuda", default=False, action="store_true", help="Enable cuda")
parser.add_argument("-n", '--name', required=True, help="Name of the run")
args = parser.parse_args()
envs = [make_env() for _ in range(ENV_COUNT)]
writer = SummaryWriter(comment="-pong-pg-" + args.name)
net = common.AtariPGN(envs[0].observation_space.shape, envs[0].action_space.n)
if args.cuda:
net.cuda()
print(net)
agent = ptan.agent.PolicyAgent(net, apply_softmax=True, cuda=args.cuda)
exp_source = ptan.experience.ExperienceSourceFirstLast(envs, agent, gamma=GAMMA, steps_count=REWARD_STEPS)
optimizer = optim.Adam(net.parameters(), lr=LEARNING_RATE, eps=1e-3)
total_rewards = []
step_idx = 0
done_episodes = 0
train_step_idx = 0
baseline_buf = MeanBuffer(BASELINE_STEPS)
batch_states, batch_actions, batch_scales = [], [], []
m_baseline, m_batch_scales, m_loss_entropy, m_loss_policy, m_loss_total = [], [], [], [], []
sum_reward = 0.0
with common.RewardTracker(writer, stop_reward=18) as tracker:
for step_idx, exp in enumerate(exp_source):
baseline_buf.add(exp.reward)
baseline = baseline_buf.mean()
batch_states.append(np.array(exp.state, copy=False))
batch_actions.append(int(exp.action))
if USE_MEAN_BASELINE:
batch_scales.append(exp.reward - baseline)
else:
batch_scales.append(exp.reward)
# handle new rewards
new_rewards = exp_source.pop_total_rewards()
if new_rewards:
if tracker.reward(new_rewards[0], step_idx):
break
if len(batch_states) < BATCH_SIZE:
continue
train_step_idx += 1
states_v = Variable(torch.from_numpy(np.array(batch_states, copy=False)))
batch_actions_t = torch.LongTensor(batch_actions)
scale_std = np.std(batch_scales)
batch_scale_v = Variable(torch.FloatTensor(batch_scales))
if args.cuda:
states_v = states_v.cuda()
batch_actions_t = batch_actions_t.cuda()
batch_scale_v = batch_scale_v.cuda()
optimizer.zero_grad()
logits_v = net(states_v)
log_prob_v = F.log_softmax(logits_v)
log_prob_actions_v = batch_scale_v * log_prob_v[range(BATCH_SIZE), batch_actions_t]
loss_policy_v = -log_prob_actions_v.mean()
loss_policy_v.backward(retain_graph=True)
grads = np.concatenate([p.grad.data.cpu().numpy().flatten()
for p in net.parameters()
if p.grad is not None])
prob_v = F.softmax(logits_v)
entropy_v = -(prob_v * log_prob_v).sum(dim=1).mean()
entropy_loss_v = -ENTROPY_BETA * entropy_v
loss_v = loss_policy_v + entropy_loss_v
loss_v.backward()
nn_utils.clip_grad_norm(net.parameters(), GRAD_L2_CLIP)
optimizer.step()
loss_v += loss_policy_v
# calc KL-div
new_logits_v = net(states_v)
new_prob_v = F.softmax(new_logits_v)
kl_div_v = -((new_prob_v / prob_v).log() * prob_v).sum(dim=1).mean()
writer.add_scalar("kl", kl_div_v.data.cpu().numpy()[0], step_idx)
writer.add_scalar("baseline", baseline, step_idx)
writer.add_scalar("entropy", entropy_v.data.cpu().numpy()[0], step_idx)
writer.add_scalar("batch_scales", np.mean(batch_scales), step_idx)
writer.add_scalar("batch_scales_std", scale_std, step_idx)
writer.add_scalar("loss_entropy", entropy_loss_v.data.cpu().numpy()[0], step_idx)
writer.add_scalar("loss_policy", loss_policy_v.data.cpu().numpy()[0], step_idx)
writer.add_scalar("loss_total", loss_v.data.cpu().numpy()[0], step_idx)
writer.add_scalar("grad_l2", np.sqrt(np.mean(np.square(grads))), step_idx)
writer.add_scalar("grad_max", np.max(np.abs(grads)), step_idx)
writer.add_scalar("grad_var", np.var(grads), step_idx)
batch_states.clear()
batch_actions.clear()
batch_scales.clear()
writer.close()
|
0c34df4af29e128cb5133b4112267783f7e9e08f
|
9472c7d1608e318e46214f231773fbb3f33de0f1
|
/kats/metrics/metadata.py
|
653372398279ba9d4e3a081fb35bb8ad0a4d0b6b
|
[
"MIT"
] |
permissive
|
facebookresearch/Kats
|
16eee984bc1c482bd709cb5d62c226d4ad85f216
|
00ab9a3db27218b4817eae2e05dc602e437f634f
|
refs/heads/main
| 2023-08-30T23:33:12.654847
| 2023-08-25T16:02:04
| 2023-08-25T16:02:04
| 342,388,745
| 4,514
| 517
|
MIT
| 2023-09-14T15:28:43
| 2021-02-25T21:51:06
|
Python
|
UTF-8
|
Python
| false
| false
| 5,302
|
py
|
metadata.py
|
# Copyright (c) Meta Platforms, Inc. and affiliates.
#
# This source code is licensed under the MIT license found in the
# LICENSE file in the root directory of this source tree.
from dataclasses import dataclass
from enum import Enum, IntEnum
from functools import lru_cache
from typing import Dict
import numpy as np
class MetricType(Enum):
"""Metrics can be scores, errors, or neither."""
NONE = 0
"""Neither score nor error"""
SCORE = 1
"""Larger is better (1 is better than 0)"""
ERROR = 2
"""Closer to zero is better (0 is better than 1 or -1)"""
class Directionality(IntEnum):
"""Metrics can improve in a direction (up or down) or lack clear direction.
Non-negative error metrics are negative and vice-versa because lower values
are also closer to zero. However, metrics that can result in negative values
cannot be simultaneously NEGATIVE and ERROR.
"""
NONE = 0
"""Neither positive nor negative."""
POSITIVE = 1
"""Larger is better (1 is better than 0)"""
NEGATIVE = -1
"""Smaller is better (-1 better than 0 better than 1)"""
@dataclass
class MetricMetadata:
"""Metadata about a metric method."""
type: MetricType
"""The type of metric (score, error, neither)."""
direction: Directionality
"""The directionality of a metric (positive, negative, or neither is better)."""
lower_bound: float
"""All values returned by this metric are at least the lower bound."""
upper_bound: float
"""All values returned by this metric are at most the upper bound."""
_NONNEGATIVE_ERROR_METRIC = MetricMetadata(
MetricType.ERROR, Directionality.NEGATIVE, 0.0, np.inf
)
_ERROR_RATE_METRIC = MetricMetadata(MetricType.ERROR, Directionality.NEGATIVE, 0.0, 1.0)
_UNBOUNDED_ERROR_METRIC = MetricMetadata(
MetricType.ERROR, Directionality.NONE, np.NINF, np.inf
)
_UNBOUNDED_METRIC = MetricMetadata(
MetricType.NONE, Directionality.NONE, np.NINF, np.inf
)
_SCORE_MAX_1 = MetricMetadata(MetricType.SCORE, Directionality.POSITIVE, np.NINF, 1.0)
_SCORE_MIN_0 = MetricMetadata(MetricType.SCORE, Directionality.POSITIVE, 0.0, np.inf)
# These metadata values apply only when unweighted. When unconstrained weights
# are used, most metrics become unbounded.
@lru_cache(None)
def _metadata() -> Dict[str, MetricMetadata]:
metadata = {
"continuous_rank_probability_score": _ERROR_RATE_METRIC,
"cross_entropy": _NONNEGATIVE_ERROR_METRIC,
"frequency_exceed_relative_threshold": _ERROR_RATE_METRIC,
"linear_error_in_probability_space": _ERROR_RATE_METRIC,
"max_error": _UNBOUNDED_ERROR_METRIC,
"mean_absolute_error": _NONNEGATIVE_ERROR_METRIC,
"mean_absolute_percentage_error": _NONNEGATIVE_ERROR_METRIC,
"mean_absolute_scaled_error": _NONNEGATIVE_ERROR_METRIC,
"mean_error": _UNBOUNDED_ERROR_METRIC,
"mean_interval_score": _SCORE_MIN_0,
"mean_percentage_error": _UNBOUNDED_ERROR_METRIC,
"mean_squared_error": _NONNEGATIVE_ERROR_METRIC,
"mean_squared_log_error": _NONNEGATIVE_ERROR_METRIC,
"median_absolute_error": _UNBOUNDED_ERROR_METRIC,
"median_absolute_percentage_error": _NONNEGATIVE_ERROR_METRIC,
"r2_score": _SCORE_MAX_1,
"root_mean_squared_error": _NONNEGATIVE_ERROR_METRIC,
"root_mean_squared_log_error": _NONNEGATIVE_ERROR_METRIC,
"root_mean_squared_percentage_error": _NONNEGATIVE_ERROR_METRIC,
"symmetric_bias": _UNBOUNDED_METRIC,
"symmetric_mean_absolute_percentage_error": _ERROR_RATE_METRIC,
"tracking_signal": _UNBOUNDED_ERROR_METRIC,
}
# aliases
metadata["bias"] = metadata["mean_error"]
metadata["crps"] = metadata["continuous_rank_probability_score"]
metadata["leps"] = metadata["linear_error_in_probability_space"]
metadata["mae"] = metadata["mean_absolute_error"]
metadata["mape"] = metadata["mean_absolute_percentage_error"]
metadata["mase"] = metadata["mean_absolute_scaled_error"]
metadata["mdae"] = metadata["median_absolute_error"]
metadata["mdape"] = metadata["median_absolute_percentage_error"]
metadata["me"] = metadata["mean_error"]
metadata["median_absolute_deviation"] = metadata["median_absolute_error"]
metadata["mean_absolute_deviation"] = metadata["mean_absolute_error"]
metadata["mis"] = metadata["mean_interval_score"]
metadata["mpe"] = metadata["mean_percentage_error"]
metadata["mse"] = metadata["mean_squared_error"]
metadata["r2"] = metadata["r2_score"]
metadata["rmse"] = metadata["root_mean_squared_error"]
metadata["rmsle"] = metadata["root_mean_squared_log_error"]
metadata["rmspe"] = metadata["root_mean_squared_percentage_error"]
metadata["sbias"] = metadata["symmetric_bias"]
metadata["smape"] = metadata["symmetric_mean_absolute_percentage_error"]
return metadata
def inspect(name: str) -> MetricMetadata:
"""Get metadata about a metric, by name.
Args:
name: the metric name
Returns:
Metadata about that metric.
Raises:
ValueError if the metric name is not a Kats metric.
"""
metadata = _metadata()
try:
return metadata[name]
except KeyError:
raise ValueError(f"Unknown metric {name}")
|
b198f8ae4ad590d183a6b3e51afb0cc0363ab597
|
5095200e9ca55cd3a37af34ed44448c02e2a1bb5
|
/modules/image/text_recognition/ch_pp-ocrv3/test.py
|
07a0049170521049e4e72e7d5b25290a4834f66b
|
[
"Apache-2.0"
] |
permissive
|
PaddlePaddle/PaddleHub
|
8712603ef486c45e83eb0bc5725b0b3ed3ddbbde
|
b402610a6f0b382a978e82473b541ea1fc6cf09a
|
refs/heads/develop
| 2023-07-24T06:03:13.172978
| 2023-03-28T11:49:55
| 2023-03-28T11:49:55
| 162,672,577
| 12,914
| 2,239
|
Apache-2.0
| 2023-07-06T21:38:19
| 2018-12-21T06:00:48
|
Python
|
UTF-8
|
Python
| false
| false
| 3,954
|
py
|
test.py
|
import os
import shutil
import unittest
import cv2
import requests
import paddlehub as hub
os.environ['CUDA_VISIBLE_DEVICES'] = '0'
class TestHubModule(unittest.TestCase):
@classmethod
def setUpClass(cls) -> None:
img_url = 'https://unsplash.com/photos/KTzZVDjUsXw/download?ixid=MnwxMjA3fDB8MXxzZWFyY2h8MzM3fHx0ZXh0fGVufDB8fHx8MTY2MzUxMTExMQ&force=true&w=640'
if not os.path.exists('tests'):
os.makedirs('tests')
response = requests.get(img_url)
assert response.status_code == 200, 'Network Error.'
with open('tests/test.jpg', 'wb') as f:
f.write(response.content)
cls.module = hub.Module(name="ch_pp-ocrv3")
@classmethod
def tearDownClass(cls) -> None:
shutil.rmtree('tests')
shutil.rmtree('inference')
shutil.rmtree('ocr_result')
def test_recognize_text1(self):
results = self.module.recognize_text(
paths=['tests/test.jpg'],
use_gpu=False,
visualization=False,
)
self.assertEqual(results[0]['data'], [{
'text': 'GIVE.',
'confidence': 0.9509768486022949,
'text_box_position': [[283, 162], [352, 162], [352, 202], [283, 202]]
}, {
'text': 'THANKS',
'confidence': 0.9943074584007263,
'text_box_position': [[261, 202], [376, 202], [376, 239], [261, 239]]
}])
def test_recognize_text2(self):
results = self.module.recognize_text(
images=[cv2.imread('tests/test.jpg')],
use_gpu=False,
visualization=False,
)
self.assertEqual(results[0]['data'], [{
'text': 'GIVE.',
'confidence': 0.9509768486022949,
'text_box_position': [[283, 162], [352, 162], [352, 202], [283, 202]]
}, {
'text': 'THANKS',
'confidence': 0.9943074584007263,
'text_box_position': [[261, 202], [376, 202], [376, 239], [261, 239]]
}])
def test_recognize_text3(self):
results = self.module.recognize_text(
images=[cv2.imread('tests/test.jpg')],
use_gpu=True,
visualization=False,
)
self.assertEqual(results[0]['data'], [{
'text': 'GIVE.',
'confidence': 0.9509768486022949,
'text_box_position': [[283, 162], [352, 162], [352, 202], [283, 202]]
}, {
'text': 'THANKS',
'confidence': 0.9943074584007263,
'text_box_position': [[261, 202], [376, 202], [376, 239], [261, 239]]
}])
def test_recognize_text4(self):
results = self.module.recognize_text(
images=[cv2.imread('tests/test.jpg')],
use_gpu=False,
visualization=True,
)
self.assertEqual(results[0]['data'], [{
'text': 'GIVE.',
'confidence': 0.9509768486022949,
'text_box_position': [[283, 162], [352, 162], [352, 202], [283, 202]]
}, {
'text': 'THANKS',
'confidence': 0.9943074584007263,
'text_box_position': [[261, 202], [376, 202], [376, 239], [261, 239]]
}])
def test_recognize_text5(self):
self.assertRaises(AttributeError, self.module.recognize_text, images=['tests/test.jpg'])
def test_recognize_text6(self):
self.assertRaises(AssertionError, self.module.recognize_text, paths=['no.jpg'])
def test_save_inference_model(self):
self.module.save_inference_model('./inference/model')
self.assertTrue(os.path.exists('./inference/model/model.pdmodel'))
self.assertTrue(os.path.exists('./inference/model/model.pdiparams'))
self.assertTrue(os.path.exists('./inference/model/_text_detector_module.pdmodel'))
self.assertTrue(os.path.exists('./inference/model/_text_detector_module.pdiparams'))
if __name__ == "__main__":
unittest.main()
|
39d16c042b2a02062a4eb37185e3223927a7b84a
|
d110546d747d7e3865ce5742d5fca09f404623c0
|
/tests/integration/modules/test_mac_sysctl.py
|
6d7b1c945d6cc5099522dcaaa323e098e30046dd
|
[
"Apache-2.0",
"MIT",
"BSD-2-Clause"
] |
permissive
|
saltstack/salt
|
354fc86a7be1f69514b3dd3b2edb9e6f66844c1d
|
1ef90cbdc7203f97775edb7666db86a41eb9fc15
|
refs/heads/master
| 2023-07-19T20:56:20.210556
| 2023-06-29T23:12:28
| 2023-07-19T11:47:47
| 1,390,248
| 11,026
| 6,296
|
Apache-2.0
| 2023-09-14T20:45:37
| 2011-02-20T20:16:56
|
Python
|
UTF-8
|
Python
| false
| false
| 5,782
|
py
|
test_mac_sysctl.py
|
"""
:codeauthor: Nicole Thomas <nicole@saltstack.com>
"""
import os
import random
import pytest
import salt.utils.files
from salt.exceptions import CommandExecutionError
from tests.support.case import ModuleCase
# Module Variables
ASSIGN_CMD = "net.inet.icmp.icmplim"
CONFIG = "/etc/sysctl.conf"
@pytest.mark.destructive_test
@pytest.mark.skip_if_not_root
@pytest.mark.skip_unless_on_darwin
class DarwinSysctlModuleTest(ModuleCase):
"""
Integration tests for the darwin_sysctl module
"""
def setUp(self):
"""
Sets up the test requirements
"""
super().setUp()
# Data needed for cleanup
self.has_conf = False
self.val = self.run_function("sysctl.get", [ASSIGN_CMD])
# If sysctl file is present, make a copy
# Remove original file so we can replace it with test files
if os.path.isfile(CONFIG):
self.has_conf = True
try:
self.conf = self.__copy_sysctl()
except CommandExecutionError:
msg = "Could not copy file: {0}"
raise CommandExecutionError(msg.format(CONFIG))
os.remove(CONFIG)
@pytest.mark.slow_test
def test_assign(self):
"""
Tests assigning a single sysctl parameter
"""
try:
rand = random.randint(0, 500)
while rand == self.val:
rand = random.randint(0, 500)
self.run_function("sysctl.assign", [ASSIGN_CMD, rand])
info = int(self.run_function("sysctl.get", [ASSIGN_CMD]))
try:
self.assertEqual(rand, info)
except AssertionError:
self.run_function("sysctl.assign", [ASSIGN_CMD, self.val])
raise
except CommandExecutionError:
self.run_function("sysctl.assign", [ASSIGN_CMD, self.val])
raise
@pytest.mark.slow_test
def test_persist_new_file(self):
"""
Tests assigning a sysctl value to a system without a sysctl.conf file
"""
# Always start with a clean/known sysctl.conf state
if os.path.isfile(CONFIG):
os.remove(CONFIG)
try:
self.run_function("sysctl.persist", [ASSIGN_CMD, 10])
line = "{}={}".format(ASSIGN_CMD, 10)
found = self.__check_string(CONFIG, line)
self.assertTrue(found)
except CommandExecutionError:
os.remove(CONFIG)
raise
@pytest.mark.slow_test
def test_persist_already_set(self):
"""
Tests assigning a sysctl value that is already set in sysctl.conf file
"""
# Always start with a clean/known sysctl.conf state
if os.path.isfile(CONFIG):
os.remove(CONFIG)
try:
self.run_function("sysctl.persist", [ASSIGN_CMD, 50])
ret = self.run_function("sysctl.persist", [ASSIGN_CMD, 50])
self.assertEqual(ret, "Already set")
except CommandExecutionError:
os.remove(CONFIG)
raise
@pytest.mark.slow_test
def test_persist_apply_change(self):
"""
Tests assigning a sysctl value and applying the change to system
"""
# Always start with a clean/known sysctl.conf state
if os.path.isfile(CONFIG):
os.remove(CONFIG)
try:
rand = random.randint(0, 500)
while rand == self.val:
rand = random.randint(0, 500)
self.run_function("sysctl.persist", [ASSIGN_CMD, rand], apply_change=True)
info = int(self.run_function("sysctl.get", [ASSIGN_CMD]))
self.assertEqual(info, rand)
except CommandExecutionError:
os.remove(CONFIG)
raise
def __copy_sysctl(self):
"""
Copies an existing sysconf file and returns temp file path. Copied
file will be restored in tearDown
"""
# Create new temporary file path and open needed files
temp_path = salt.utils.files.mkstemp()
with salt.utils.files.fopen(CONFIG, "r") as org_conf:
with salt.utils.files.fopen(temp_path, "w") as temp_sysconf:
# write sysctl lines to temp file
for line in org_conf:
temp_sysconf.write(line)
return temp_path
def __restore_sysctl(self):
"""
Restores the original sysctl.conf file from temporary copy
"""
# If sysctl testing file exists, delete it
if os.path.isfile(CONFIG):
os.remove(CONFIG)
# write temp lines to sysctl file to restore
with salt.utils.files.fopen(self.conf, "r") as temp_sysctl:
with salt.utils.files.fopen(CONFIG, "w") as sysctl:
for line in temp_sysctl:
sysctl.write(line)
# delete temporary file
os.remove(self.conf)
def __check_string(self, conf_file, to_find):
"""
Returns True if given line is present in file
"""
with salt.utils.files.fopen(conf_file, "r") as f_in:
for line in f_in:
if to_find in salt.utils.stringutils.to_unicode(line):
return True
return False
def tearDown(self):
"""
Clean up after tests
"""
ret = self.run_function("sysctl.get", [ASSIGN_CMD])
if ret != self.val:
self.run_function("sysctl.assign", [ASSIGN_CMD, self.val])
if self.has_conf is True:
# restore original sysctl file
self.__restore_sysctl()
if self.has_conf is False and os.path.isfile(CONFIG):
# remove sysctl.conf created by tests
os.remove(CONFIG)
|
274be29382d19816c5eeac076640a0e5f40af3a6
|
06955f6c7f2a0ce54413fcb9ed10453298e36dcf
|
/fsspec/implementations/tests/test_common.py
|
f09f13ce048fd05a0e3f4a7bc199087706e2fb71
|
[
"BSD-3-Clause"
] |
permissive
|
fsspec/filesystem_spec
|
aba07f52331dc380370af326ea79a0f2061816c0
|
212c26f34ada124e3d6ff9b2b520fdadc4903094
|
refs/heads/master
| 2023-09-01T00:02:37.323404
| 2023-08-31T19:14:12
| 2023-08-31T19:14:12
| 130,727,736
| 308
| 135
|
BSD-3-Clause
| 2023-09-14T20:25:47
| 2018-04-23T16:45:08
|
Python
|
UTF-8
|
Python
| false
| false
| 1,070
|
py
|
test_common.py
|
import datetime
import time
import pytest
from fsspec import AbstractFileSystem
from fsspec.implementations.tests.conftest import READ_ONLY_FILESYSTEMS
@pytest.mark.parametrize("fs", ["local"], indirect=["fs"])
def test_created(fs: AbstractFileSystem, temp_file):
try:
fs.touch(temp_file)
created = fs.created(path=temp_file)
assert isinstance(created, datetime.datetime)
finally:
if not isinstance(fs, tuple(READ_ONLY_FILESYSTEMS)):
fs.rm(temp_file)
@pytest.mark.parametrize("fs", ["local", "memory", "arrow"], indirect=["fs"])
def test_modified(fs: AbstractFileSystem, temp_file):
try:
fs.touch(temp_file)
# created = fs.created(path=temp_file)
created = datetime.datetime.now(
tz=datetime.timezone.utc
) # pyarrow only have modified
time.sleep(0.05)
fs.touch(temp_file)
modified = fs.modified(path=temp_file)
assert isinstance(modified, datetime.datetime)
assert modified > created
finally:
fs.rm(temp_file)
|
e44d67da56eef75d39fd49935fc23b795b819374
|
3d063af394b4b55ea49ded7915d0793602015859
|
/python/media/photo.py
|
180b9bf1bf4c230ad10e33866a892f457e2ea777
|
[
"Apache-2.0"
] |
permissive
|
ringgaard/sling
|
00edad71195bfe71aa11e2e8dda97109c047e6e5
|
a612c5823954552ba422b441a7c7d57c1a5b4fcb
|
refs/heads/master
| 2023-08-07T15:24:10.569228
| 2023-08-02T12:25:44
| 2023-08-02T12:25:44
| 106,742,468
| 141
| 10
|
Apache-2.0
| 2020-08-03T13:25:36
| 2017-10-12T20:34:28
|
C++
|
UTF-8
|
Python
| false
| false
| 27,415
|
py
|
photo.py
|
# Copyright 2021 Ringgaard Research ApS
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http:#www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""Photo profile library."""
import hashlib
import json
import os
import io
import re
import requests
import ssl
import time
import urllib.parse
import urllib3
from PIL import Image
import sling
import sling.flags as flags
flags.define("--photodb",
help="database for photo profiles",
default="vault/photo",
metavar="DB")
flags.define("--mediadb",
help="database for images",
default="vault/media",
metavar="DB")
flags.define("--fpdb",
help="database for photo fingerprints",
default="vault/fingerprint",
metavar="DB")
flags.define("--check",
help="check that photo exists before adding",
default=False,
action="store_true")
flags.define("--fixedcaption",
default=None,
help="override photo caption")
flags.define("--captions",
help="add caption to photos",
default=False,
action="store_true")
flags.define("--perimagecaption",
help="use individual captions for images in albums",
default=False,
action="store_true")
flags.define("--preservecaptioned",
help="do not remove captioned duplicates",
default=False,
action="store_true")
flags.define("--numbering",
help="photo numbering for albums",
default=False,
action="store_true")
flags.define("--source",
default=None,
help="photo source")
flags.define("--video",
help="allow video clips",
default=False,
action="store_true")
flags.define("--albums",
help="add albums from posting",
default=False,
action="store_true")
flags.define("--hash",
help="image hash method",
default="average")
# Photo database.
db = None
# Media database.
mediadb = None
# Photo fingerprint database.
fpdb = None
# Session for fetching image data. Disable SSL checking.
class TLSAdapter(requests.adapters.HTTPAdapter):
def init_poolmanager(self, *args, **kwargs):
ctx = ssl.create_default_context()
ctx.check_hostname = False
ctx.verify_mode = ssl.CERT_NONE
ctx.set_ciphers('DEFAULT@SECLEVEL=1')
kwargs['ssl_context'] = ctx
return super(TLSAdapter, self).init_poolmanager(*args, **kwargs)
session = requests.Session()
session.verify = False
session.mount('https://', TLSAdapter())
urllib3.disable_warnings()
pool = urllib3.PoolManager(cert_reqs=ssl.CERT_NONE)
# Global store.
store = sling.Store()
n_media = store["media"]
n_is = store["is"]
n_legend = store["P2096"]
n_stated_in = store["P248"]
n_has_quality = store["P1552"]
n_nsfw = store["Q2716583"]
# Get API keys for Imgur and ImgChest.
imgurkeys = None
if os.path.exists("local/keys/imgur.json"):
with open("local/keys/imgur.json", "r") as f:
imgurkeys = json.load(f)
imgchestkeys = None
if os.path.exists("local/keys/imgchest.json"):
with open("local/keys/imgchest.json", "r") as f:
imgchestkeys = json.load(f)
# Tri-state override.
def tri(value, override):
if override is None:
return value
else:
return override
def photodb():
global db
if db is None: db = sling.Database(flags.arg.photodb)
return db
# Video detection.
video_suffixes = [
".gif",
".gifv",
".mp4",
".webm",
]
video_prefixes = [
"https://gfycat.com/",
"https://redgifs.com/",
"https://v.redd.it/"
]
album_patterns = [
re.compile(r"\[(.+)\]\((https?:\/\/imgur.com\/a\/\w+)\)"),
re.compile(r"\[(.+)\]\((https?:\/\/(?:www\.)?imgchest\.com\/p\/\w+)\)"),
re.compile(r"(https?:\/\/imgur\.com\/a\/\w+)"),
re.compile(r"(https?:\/\/(?:www\.)?imgchest\.com\/p\/\w+)"),
]
commons_base_url = "https://upload.wikimedia.org/wikipedia/commons"
def is_video(url):
for suffix in video_suffixes:
if url.endswith(suffix): return True
for prefix in video_prefixes:
if url.startswith(prefix): return True
return False
def commons_media(fn):
if fn is None: return None
fn = fn.replace(' ', '_')
md5 = hashlib.md5(fn.encode("utf8")).hexdigest()
fn = fn.replace("?", "%3F")
fn = fn.replace("+", "%2B")
fn = fn.replace("&", "%26")
return "%s/%s/%s/%s" % (commons_base_url, md5[0], md5[0:2], fn)
# Image hashing.
Image.MAX_IMAGE_PIXELS = None
# MD5 hash computation.
def md5_hasher(image):
return hashlib.md5(image).hexdigest(), 1, len(image)
# Average hash computation.
# See:
# https://www.hackerfactor.com/blog/index.php?/archives/432-Looks-Like-It.html
def average_hasher(image):
try:
# Read image.
img = Image.open(io.BytesIO(image))
# Simplify image by reducing its size and colors.
pixels = img.convert("L").resize((8, 8), Image.ANTIALIAS).getdata()
# Get the average pixel value.
sum = 0.0
for p in pixels: sum += p
mean = sum / 64
# Generate the hash by comparing each pixel's value to the average.
bits = 0
for p in pixels:
bits <<= 1
if p > mean: bits |= 1
return "%016x" % bits, img.width, img.height
except Exception:
# Fall back to MD hashing if fingerprint cannot be computed.
return md5_hasher(image)
image_hashers = {
"md5": md5_hasher,
"average": average_hasher,
}
class Photo:
def __init__(self, item, url):
self.item = item
self.url = url
self.fingerprint = None
self.width = None
self.height = None
def size(self):
return self.width * self.height
photo_cache = {}
def fetch_image(url):
# Try to get image from media database.
global mediadb
if mediadb is None and flags.arg.mediadb:
mediadb = sling.Database(flags.arg.mediadb)
if mediadb:
image = mediadb[url]
if image: return image
# Fetch image from source if it is not in the media database.
try:
print("fetch", url)
r = pool.request("GET", url, timeout=60)
for h in r.retries.history:
if h.redirect_location.endswith("/removed.png"): return None
if h.redirect_location.endswith("/no_image.jpg"): return None
if r.status != 200: return None
return r.data
except Exception as e:
print("fail", e, url)
return None
def get_photo(item, url):
# Check if photo is cached.
photo = photo_cache.get(url)
if photo is not None: return photo
# Get image.
image = fetch_image(url)
if image is None: return None
# Get photo fingerprint.
photo = Photo(item, url)
hasher = image_hashers[flags.arg.hash]
photo.fingerprint, photo.width, photo.height = hasher(image)
# Add photo to cache.
photo_cache[url] = photo
return photo
def load_fingerprints(urls):
missing = []
for url in urls:
if url not in photo_cache: missing.append(url)
if len(missing) == 0: return
# Fetch fingerprints from database.
if len(flags.arg.fpdb) == 0: return
global fpdb
if fpdb is None: fpdb = sling.Database(flags.arg.fpdb)
for url, data in fpdb[missing].items():
if data is None: continue
fp = json.loads(data)
if flags.arg.hash not in fp: continue
photo = Photo(fp.get("item"), url)
photo.fingerprint = fp[flags.arg.hash]
photo.width = fp["width"]
photo.height = fp["height"]
photo_cache[url] = photo
class Profile:
def __init__(self, itemid, data=None):
self.itemid = itemid
self.excluded = None
self.isnew = False
self.captions = flags.arg.captions
if data is None and itemid is not None:
data, _ = photodb().get(itemid)
if data is None:
self.frame = store.frame({})
self.isnew = True
else:
self.frame = store.parse(data)
# Write photo profile to database.
def write(self):
if self.itemid is None or self.itemid == "": raise Error("empty id")
data = self.frame.data(binary=True)
result = photodb().put(self.itemid, data)
if result == sling.DBUNCHANGED: print(self.itemid, "unchanged")
# Clear all photos.
def clear(self):
del self.frame[n_media]
# Return number of photos in profile.
def count(self):
return self.frame.count(n_media)
# Return iterator over all photos.
def media(self):
return self.frame(n_media)
# Return url for media.
def url(self, media):
if type(media) is sling.Frame: media = media[n_is]
if media.startswith('!'): media = media[1:]
return media
# Return nsfw status for media.
def isnsfw(self, media):
if type(media) is sling.Frame:
if media[n_is].startswith('!'): return True
if media[n_has_quality] == n_nsfw: return True
return False
else:
return media.startswith('!')
# Return caption for photo.
def caption(self, media):
if type(media) is sling.Frame and n_legend in media:
return str(media[n_legend])
else:
return None
# Check if media has caption.
def captioned(self, media):
if type(media) is sling.Frame:
return n_legend in media
else:
return False
# Preload photo fingerprints.
def preload_fingerprints(self):
urls = []
for media in self.media():
url = self.url(media)
if is_video(url): continue
urls.append(url)
load_fingerprints(urls)
# Import all photos from another profile.
def copy(self, other):
num_added = 0
for media in other.media():
url = self.url(media)
nsfw = self.isnsfw(media)
caption = self.caption(media)
num_added += self.add_photo(url, caption, None, nsfw)
return num_added
# Replace photos in profile:
def replace(self, photos):
slots = []
for photo in photos: slots.append((n_media, photo))
del self.frame[n_media]
self.frame.extend(slots)
# Return all media urls.
def urls(self):
urls = []
for media in self.media():
urls.append(self.url(media))
return urls
# Check if photo already in profile.
def has(self, url, alturl=None):
for media in self.media():
u = self.url(media)
if u == url or u == alturl: return True
return False
# Add photo to profile.
def add_photo(self, url, caption=None, source=None, nsfw=None):
# Check if photo should be excluded.
if self.excluded and url in self.excluded:
print("Skip excluded photo:", url)
return 0
# Check if photo exists.
if flags.arg.check:
r = session.head(url)
if r.status_code // 100 == 3:
redirect = r.headers['Location']
if redirect.endswith("/removed.png"):
print("Skip removed photo:", url, r.status_code)
return 0
# Check if redirect exists.
r = session.head(redirect)
if r.status_code != 200:
print("Skip missing redirect:", url, r.status_code)
return 0
# Use redirected url.
url = redirect
elif r.status_code != 200:
print("Skip missing photo:", url, r.status_code)
return 0
# Check content length.
if url.startswith("https://i.reddituploads.com/"):
length = r.headers.get("Content-Length")
if length == 0:
print("Skip empty photo:", url)
return 0
# Check content type.
ct = r.headers.get("Content-Type")
if ct != None and not ct.startswith("image/"):
print("Skip non-image content:", url, ct)
return 0
# Check if photo is already in the profile.
alturl = None
if url.startswith("https://imgur.com/"):
alturl = "https://i.imgur.com/" + url[18:]
elif url.startswith("https://i.imgur.com/"):
alturl = "https://imgur.com/" + url[20:]
if self.has(url, alturl):
print("Skip existing photo", url)
return 0
# Add media to profile.
if nsfw: url = "!" + url
slots = [(n_is, url)]
if flags.arg.fixedcaption: caption = flags.arg.fixedcaption
if caption and self.captions: slots.append((n_legend, caption))
if source: slots.append((n_stated_in, store[source]))
if len(slots) == 1:
self.frame.append(n_media, url)
else:
self.frame.append(n_media, store.frame(slots))
return 1
# Add Imgur album.
def add_imgur_album(self, albumid, caption, nsfw_override=None):
print("Imgur album", albumid)
auth = {'Authorization': "Client-ID " + imgurkeys["clientid"]}
r = session.get("https://api.imgur.com/3/album/" + albumid, headers=auth)
if r.status_code == 404:
print("Skipping missing album", albumid)
return 0
if r.status_code == 403:
print("Skipping unaccessible album", albumid)
return 0
r.raise_for_status()
reply = r.json()["data"]
#print(json.dumps(reply, indent=2))
serial = 1
total = len(reply["images"])
album_title = reply["title"]
if album_title is None:
album_title = caption
elif caption is not None and caption.startswith(album_title):
album_title = caption
count = 0
for image in reply["images"]:
link = image["link"]
# Remove query parameters.
qs = link.find("?")
if qs != -1: link = link[:qs]
# Skip anmated GIFs.
if (not flags.arg.video and image["animated"]):
print("Skipping animated image", link);
continue
# Image caption.
if flags.arg.perimagecaption:
title = image["title"]
if title is None:
title = image["description"]
else:
title = None
if title is None and album_title != None:
if flags.arg.numbering:
title = album_title + " (%d/%d)" % (serial, total)
else:
title = album_title
if title != None:
title = title.replace("\n", " ").strip()
# NSFW flag.
nsfw = tri(reply["nsfw"] or image["nsfw"], nsfw_override)
# Add media frame to profile.
if self.add_photo(link, title, None, nsfw): count += 1
serial += 1
return count
# Add Imgur image.
def add_imgur_image(self, imageid, caption=None, nsfw_override=None):
print("Imgur image", imageid)
auth = {'Authorization': "Client-ID " + imgurkeys["clientid"]}
r = session.get("https://api.imgur.com/3/image/" + imageid, headers=auth)
if r.status_code == 404:
print("Skipping missing image", imageid)
return 0
r.raise_for_status()
reply = r.json()["data"]
#print(json.dumps(reply, indent=2))
# Photo URL.
link = reply["link"]
qs = link.find("?")
if qs != -1: link = link[:qs]
# Skip anmated GIFs.
if (not flags.arg.video and reply["animated"]):
print("Skipping animated image", link);
return 0
# Image caption.
if caption is None:
caption = reply["title"]
if caption is None:
caption = reply["description"]
if caption is not None:
caption = caption.replace("\n", " ").strip()
# NSFW flag.
nsfw = tri(reply["nsfw"] or reply["nsfw"], nsfw_override)
# Add media to profile frame.
return self.add_photo(link, caption, None, nsfw)
# Add Reddit gallery.
def add_reddit_gallery(self, galleryid, caption, nsfw_override=None):
print("Redit posting", galleryid)
while True:
r = requests.get("https://api.reddit.com/api/info/?id=t3_" + galleryid,
headers = {"User-agent": "SLING Bot 1.0"})
if r.status_code != 429: break
reset = int(r.headers.get("x-ratelimit-reset", 60))
print("gallery rate limit", reset, "secs")
time.sleep(reset)
r.raise_for_status()
children = r.json()["data"]["children"]
if len(children) == 0:
print("Skipping empty post", galleryid);
return 0
reply = children[0]["data"]
#print(json.dumps(reply, indent=2))
if not flags.arg.albums and reply["is_self"]:
print("Skipping self post", galleryid);
return 0
if reply["removed_by_category"] != None:
print("Skipping deleted post", galleryid);
return 0
if reply["is_video"]:
print("Skipping video", galleryid);
return 0
mediadata = reply.get("media_metadata")
if mediadata is None:
url = reply.get("url")
if url is None:
print("Skipping empty gallery", galleryid);
return 0
title = reply["title"]
if title is None: title = caption
if not self.captions: title = None
nsfw = tri(reply["over_18"], nsfw_override)
count = 0
if flags.arg.albums:
# Fetch albums from text.
selftext = reply["selftext"]
for m in re.finditer("\[(.+)\]\((https?://imgur.com/a/\w+)\)", selftext):
print("Album", m[2], m[1])
count += self.add_media(m[2], m[1], nsfw)
else:
# Add media to profile frame.
count = self.add_media(url, title, nsfw)
return count
# Get gallery items.
gallery = reply.get("gallery_data")
if gallery is None:
print("Skipping missing gallery data in", galleryid);
return 0
items = gallery.get("items")
if items is None:
print("Skipping missing gallery items in", galleryid);
return 0
count = 0
serial = 1
for item in items:
mediaid = item["media_id"]
media = mediadata[mediaid].get("s")
if media is None:
print("Skipping missing media in gallery", mediaid);
continue
link = media.get("u")
if link is None:
print("Skipping missing image in gallery", mediaid);
continue
m = re.match("https://preview.redd.it/(\w+\.\w+)\?", link)
if m != None: link = "https://i.redd.it/" + m.group(1)
# Image caption.
title = reply["title"]
if title is None:
title = caption
elif caption is not None and caption.startswith(title):
title = caption
if not self.captions: title = None
if title != None and flags.arg.numbering:
title = "%s (%d/%d)" % (title, serial, len(items))
# NSFW flag.
nsfw = tri(reply["over_18"], nsfw_override)
# Add media to profile frame.
if self.add_photo(link, title, None, nsfw): count += 1
serial += 1
return count
# Add imgchest album.
def add_imgchest_album(self, albumid, caption, nsfw_override=None):
print("Image chest album", albumid)
auth = {"Authorization": "Bearer " + imgchestkeys["token"]}
r = session.get("https://api.imgchest.com/v1/post/" + albumid, headers=auth)
if r.status_code == 404:
print("Skipping missing album", albumid)
return 0
if r.status_code == 403:
print("Skipping unaccessible album", albumid)
return 0
r.raise_for_status()
reply = r.json()["data"]
#print(json.dumps(reply, indent=2))
total = len(reply["images"])
album_title = reply.get("title")
if album_title is None:
album_title = caption
elif caption is not None and caption.startswith(album_title):
album_title = caption
count = 0
serial = 1
for image in reply["images"]:
link = image["link"]
# Remove query parameters.
qs = link.find("?")
if qs != -1: link = link[:qs]
# Skip anmated GIFs.
if (not flags.arg.video and image.get("animated", False)):
print("Skipping animated image", link);
continue
# Image caption.
if flags.arg.perimagecaption:
title = image.get("title")
if title is None:
title = image.get("description")
else:
title = None
if title is None and album_title != None:
if flags.arg.numbering:
title = album_title + " (%d/%d)" % (serial, total)
else:
title = album_title
if title != None:
title = title.replace("\n", " ").strip()
# NSFW flag.
nsfw = tri(reply["nsfw"], nsfw_override)
# Add media frame to profile.
if self.add_photo(link, title, None, nsfw): count += 1
serial += 1
return count
# Add media.
def add_media(self, url, caption=None, nsfw=None):
# NSFW urls.
if url.startswith("!"):
nsfw = True
url = url[1:]
# Trim url.
url = url.replace("/i.imgur.com/", "/imgur.com/")
url = url.replace("/www.imgur.com/", "/imgur.com/")
url = url.replace("/m.imgur.com/", "/imgur.com/")
m = re.match("(https://imgur\.com/.+)\.jpeg", url)
if m != None: url = m.group(1) + ".jpg"
url = url.replace("/www.reddit.com/", "/reddit.com/")
url = url.replace("/old.reddit.com/", "/reddit.com/")
if url.startswith("http://reddit.com"): url = "https" + url[4:]
if url.startswith("http://imgur.com"): url = "https" + url[4:]
m = re.match("(https://imgur\.com/.+)[\?#].*", url)
if m == None: m = re.match("(https?://reddit\.com/.+)[\?#].*", url)
if m == None: m = re.match("(https?://i\.redd\.it/.+)[\?#].*", url)
if m == None: m = re.match("(https?://i\.redditmedia\.com/.+)[\?#].*", url)
if m != None:
url = m.group(1)
if url.endswith("/new"): url = url[:-4]
m = re.match("https://preview.redd.it/(\w+.png)\?.+", url)
if m != None: url = "https://i.redd.it/" + m.group(1)
m = re.match("(https://imgur\.com/.+\.jpe?g)-\w+", url)
if m != None: url = m.group(1)
# Discard videos.
if not flags.arg.video and is_video(url):
print("Skipping video", url)
return 0
# Discard subreddits.
m = re.match("^https?://reddit\.com/r/\w+/?$", url)
if m != None: return 0;
# Discard empty urls.
if len(url) == 0: return 0
# Imgur album.
m = re.match("https://imgur\.com/a/(\w+)", url)
if m != None:
albumid = m.group(1)
return self.add_imgur_album(albumid, caption, nsfw)
# Imgur gallery.
m = re.match("https://imgur\.com/gallery/(\w+)", url)
if m != None:
galleryid = m.group(1)
return self.add_imgur_album(galleryid, caption, nsfw)
m = re.match("https?://imgur\.com/\w/\w+/(\w+)", url)
if m != None:
galleryid = m.group(1)
return self.add_imgur_album(galleryid, caption, nsfw)
# Single-image imgur.
m = re.match("https://imgur\.com/(\w+)$", url)
if m != None:
imageid = m.group(1)
return self.add_imgur_image(imageid, caption, nsfw)
# Reddit gallery.
m = re.match("https://reddit\.com/gallery/(\w+)", url)
if m != None:
galleryid = m.group(1)
return self.add_reddit_gallery(galleryid, caption, nsfw)
# Reddit posting.
m = re.match("https://(www\.)?reddit\.com/\w+/.+/comments/(\w+)/", url)
if m != None:
galleryid = m.group(2)
return self.add_reddit_gallery(galleryid, caption, nsfw)
# Reddit preview.
m = re.match("https://preview.redd.it/(\w+.png)\?", url)
if m != None:
imagename = m.group(1)
url = "https://i.redd.it/" + imagename
m = re.match("https://preview.redd.it/(\w+.jpg)\?", url)
if m != None:
imagename = m.group(1)
url = "https://i.redd.it/" + imagename
# DR image scaler.
m = re.match("https://asset.dr.dk/[Ii]mage[Ss]caler/\?(.+)", url)
if m != None:
q = urllib.parse.parse_qs(m.group(1))
url = "https://%s/%s" % (q["server"][0], q["file"][0])
# Image chest album.
m = re.match("https://(?:www\.)?imgchest.com/p/(\w+)", url)
if m != None:
albumid = m.group(1)
return self.add_imgchest_album(albumid, caption, nsfw)
# Listal thumb.
m = re.match("(https://lthumb.lisimg.com/[0-9\/].jpg)\?.+", url)
if m != None: url = m.group(1)
# Add media to profile.
return self.add_photo(url, caption, flags.arg.source, nsfw)
# Add albums in comments.
def add_albums_in_comments(self, url, nsfw=None):
print("Redit albums in commens", url)
while True:
r = requests.get(url + ".json",
headers = {"User-agent": "SLING Bot 1.0"})
if r.status_code != 429: break
reset = int(r.headers.get("x-ratelimit-reset", 60))
print("album rate limit", reset, "secs")
time.sleep(reset)
r.raise_for_status()
comments = r.json()[1]["data"]["children"]
count = 0
for comment in comments:
comment = comment["data"]
body = comment["body"]
for pat in album_patterns:
for m in pat.finditer(body):
if len(m.groups()) == 2:
print("Album link", m[1], m[2])
count += self.add_media(m[2], m[1], nsfw)
else:
print("Album link", m[1])
count += self.add_media(m[1], None, nsfw)
if count > 0: break
return count
# Remove duplicate photos.
def dedup(self):
# Add photo fingerprints to cache.
self.preload_fingerprints()
# Compute image hash for each photo to detect duplicates.
photos = {}
pixels = {}
captions = {}
duplicates = set()
missing = set()
naughty = set()
num_photos = 0
for media in self.media():
url = self.url(media)
if is_video(url): continue
nsfw = self.isnsfw(media)
captioned = self.captioned(media)
if captioned: captions[url] = self.caption(media)
# Get photo information.
photo = get_photo(self.itemid, url)
if photo is None:
missing.add(url)
continue
# Check for duplicate.
dup = photos.get(photo.fingerprint)
if dup != None:
if flags.arg.preservecaptioned and captioned:
print(self.itemid, url, " preserve captioned duplicate of", dup.url)
else:
# Keep biggest captioned photo.
caption = captions.get(url)
dupcaption = captions.get(dup.url)
bigger = photo.size() * 0.8 > dup.size()
if bigger or (caption is not None and dupcaption is None):
# Remove previous duplicate.
duplicates.add(dup.url)
msg = "replacement for"
else:
# Remove this duplicate.
duplicates.add(photo.url)
msg = "duplicate of"
if nsfw:
if dup not in naughty: msg = "nsfw " + msg
else:
if dup in naughty: msg = "sfw " + msg
if caption is not None: msg = "captioned " + msg
if dupcaption is not None: msg = msg + " captioned"
if photo.size() < dup.size():
msg = "smaller " + msg
elif photo.size() > dup.size():
msg = "bigger " + msg
print(self.itemid, url, msg, dup.url)
# Add photo fingerprint for new or bigger photos.
if dup is None or dup.size() < photo.size():
photos[photo.fingerprint] = photo
if nsfw: naughty.add(photo)
num_photos += 1
# Remove duplicates.
if len(duplicates) > 0 or len(missing) > 0:
# Find photos to keep.
keep = []
for media in self.media():
url = self.url(media)
if url not in duplicates and url not in missing: keep.append(media)
self.replace(keep)
print(self.itemid,
num_photos, "photos,",
len(duplicates), "duplicates",
len(missing), "missing")
return len(duplicates) + len(missing)
|
8e4f069f623f7b69d493d01842749ebf4236338d
|
6960dfbe2e3373968c82ea70e77b68460dcb4ad7
|
/examples/demo_simple.py
|
cbd02efb54dd6d81f3a977d8fafa59c9a00c7c45
|
[
"MIT"
] |
permissive
|
lebrice/SimpleParsing
|
a19423a0814f5c8a6a9d1542c1200785f53a4b78
|
77e4ff514787d6a6eff13a735766e088e22e664e
|
refs/heads/master
| 2023-08-16T13:55:36.456203
| 2023-08-10T13:45:49
| 2023-08-10T13:45:49
| 213,200,949
| 304
| 35
|
MIT
| 2023-08-14T20:36:44
| 2019-10-06T16:15:54
|
Python
|
UTF-8
|
Python
| false
| false
| 360
|
py
|
demo_simple.py
|
# examples/demo_simple.py
from dataclasses import dataclass
import simple_parsing
@dataclass
class Options:
"""Help string for this group of command-line arguments"""
log_dir: str # Help string for a required str argument
learning_rate: float = 1e-4 # Help string for a float argument
options = simple_parsing.parse(Options)
print(options)
|
c5131db1881877448f21fb423d9a3e261b3059d0
|
4d45ac082322ec48ad2654ea3b48e5f34e6307e9
|
/business_rules/operators.py
|
d43e5b1fa667aa4b25578d7e07b54a4cb20984dc
|
[
"MIT"
] |
permissive
|
venmo/business-rules
|
13adda5d2a44721ef976107a8a6d797ef312ffa6
|
b5c1a3cee725ae5cebcd64c19b6165dd2cb4e59e
|
refs/heads/master
| 2023-07-05T01:04:05.040596
| 2022-03-18T16:35:43
| 2022-03-18T16:35:43
| 18,422,074
| 856
| 255
|
MIT
| 2023-06-25T13:40:46
| 2014-04-03T23:58:50
|
Python
|
UTF-8
|
Python
| false
| false
| 7,627
|
py
|
operators.py
|
import inspect
import re
from functools import wraps
from six import string_types, integer_types
from .fields import (FIELD_TEXT, FIELD_NUMERIC, FIELD_NO_INPUT,
FIELD_SELECT, FIELD_SELECT_MULTIPLE)
from .utils import fn_name_to_pretty_label, float_to_decimal
from decimal import Decimal, Inexact, Context
class BaseType(object):
def __init__(self, value):
self.value = self._assert_valid_value_and_cast(value)
def _assert_valid_value_and_cast(self, value):
raise NotImplemented()
@classmethod
def get_all_operators(cls):
methods = inspect.getmembers(cls)
return [{'name': m[0],
'label': m[1].label,
'input_type': m[1].input_type}
for m in methods if getattr(m[1], 'is_operator', False)]
def export_type(cls):
""" Decorator to expose the given class to business_rules.export_rule_data. """
cls.export_in_rule_data = True
return cls
def type_operator(input_type, label=None,
assert_type_for_arguments=True):
""" Decorator to make a function into a type operator.
- assert_type_for_arguments - if True this patches the operator function
so that arguments passed to it will have _assert_valid_value_and_cast
called on them to make type errors explicit.
"""
def wrapper(func):
func.is_operator = True
func.label = label \
or fn_name_to_pretty_label(func.__name__)
func.input_type = input_type
@wraps(func)
def inner(self, *args, **kwargs):
if assert_type_for_arguments:
args = [self._assert_valid_value_and_cast(arg) for arg in args]
kwargs = dict((k, self._assert_valid_value_and_cast(v))
for k, v in kwargs.items())
return func(self, *args, **kwargs)
return inner
return wrapper
@export_type
class StringType(BaseType):
name = "string"
def _assert_valid_value_and_cast(self, value):
value = value or ""
if not isinstance(value, string_types):
raise AssertionError("{0} is not a valid string type.".
format(value))
return value
@type_operator(FIELD_TEXT)
def equal_to(self, other_string):
return self.value == other_string
@type_operator(FIELD_TEXT, label="Equal To (case insensitive)")
def equal_to_case_insensitive(self, other_string):
return self.value.lower() == other_string.lower()
@type_operator(FIELD_TEXT)
def starts_with(self, other_string):
return self.value.startswith(other_string)
@type_operator(FIELD_TEXT)
def ends_with(self, other_string):
return self.value.endswith(other_string)
@type_operator(FIELD_TEXT)
def contains(self, other_string):
return other_string in self.value
@type_operator(FIELD_TEXT)
def matches_regex(self, regex):
return re.search(regex, self.value)
@type_operator(FIELD_NO_INPUT)
def non_empty(self):
return bool(self.value)
@export_type
class NumericType(BaseType):
EPSILON = Decimal('0.000001')
name = "numeric"
@staticmethod
def _assert_valid_value_and_cast(value):
if isinstance(value, float):
# In python 2.6, casting float to Decimal doesn't work
return float_to_decimal(value)
if isinstance(value, integer_types):
return Decimal(value)
if isinstance(value, Decimal):
return value
else:
raise AssertionError("{0} is not a valid numeric type.".
format(value))
@type_operator(FIELD_NUMERIC)
def equal_to(self, other_numeric):
return abs(self.value - other_numeric) <= self.EPSILON
@type_operator(FIELD_NUMERIC)
def greater_than(self, other_numeric):
return (self.value - other_numeric) > self.EPSILON
@type_operator(FIELD_NUMERIC)
def greater_than_or_equal_to(self, other_numeric):
return self.greater_than(other_numeric) or self.equal_to(other_numeric)
@type_operator(FIELD_NUMERIC)
def less_than(self, other_numeric):
return (other_numeric - self.value) > self.EPSILON
@type_operator(FIELD_NUMERIC)
def less_than_or_equal_to(self, other_numeric):
return self.less_than(other_numeric) or self.equal_to(other_numeric)
@export_type
class BooleanType(BaseType):
name = "boolean"
def _assert_valid_value_and_cast(self, value):
if type(value) != bool:
raise AssertionError("{0} is not a valid boolean type".
format(value))
return value
@type_operator(FIELD_NO_INPUT)
def is_true(self):
return self.value
@type_operator(FIELD_NO_INPUT)
def is_false(self):
return not self.value
@export_type
class SelectType(BaseType):
name = "select"
def _assert_valid_value_and_cast(self, value):
if not hasattr(value, '__iter__'):
raise AssertionError("{0} is not a valid select type".
format(value))
return value
@staticmethod
def _case_insensitive_equal_to(value_from_list, other_value):
if isinstance(value_from_list, string_types) and \
isinstance(other_value, string_types):
return value_from_list.lower() == other_value.lower()
else:
return value_from_list == other_value
@type_operator(FIELD_SELECT, assert_type_for_arguments=False)
def contains(self, other_value):
for val in self.value:
if self._case_insensitive_equal_to(val, other_value):
return True
return False
@type_operator(FIELD_SELECT, assert_type_for_arguments=False)
def does_not_contain(self, other_value):
for val in self.value:
if self._case_insensitive_equal_to(val, other_value):
return False
return True
@export_type
class SelectMultipleType(BaseType):
name = "select_multiple"
def _assert_valid_value_and_cast(self, value):
if not hasattr(value, '__iter__'):
raise AssertionError("{0} is not a valid select multiple type".
format(value))
return value
@type_operator(FIELD_SELECT_MULTIPLE)
def contains_all(self, other_value):
select = SelectType(self.value)
for other_val in other_value:
if not select.contains(other_val):
return False
return True
@type_operator(FIELD_SELECT_MULTIPLE)
def is_contained_by(self, other_value):
other_select_multiple = SelectMultipleType(other_value)
return other_select_multiple.contains_all(self.value)
@type_operator(FIELD_SELECT_MULTIPLE)
def shares_at_least_one_element_with(self, other_value):
select = SelectType(self.value)
for other_val in other_value:
if select.contains(other_val):
return True
return False
@type_operator(FIELD_SELECT_MULTIPLE)
def shares_exactly_one_element_with(self, other_value):
found_one = False
select = SelectType(self.value)
for other_val in other_value:
if select.contains(other_val):
if found_one:
return False
found_one = True
return found_one
@type_operator(FIELD_SELECT_MULTIPLE)
def shares_no_elements_with(self, other_value):
return not self.shares_at_least_one_element_with(other_value)
|
7b6663013ddbce912f04f2ac58a8eb01644f1ba6
|
7378aaee27ef676db95dce7702c48f8643c63313
|
/grow/testing/google_service.py
|
666d26d9fe3ce2aa018c92d6f500a6f1e2f3b359
|
[
"MIT"
] |
permissive
|
grow/grow
|
323fa25c7690643bf170cc4558fffdfbd406ac76
|
17471c436621ebfd978b51225fa4de05367a53e1
|
refs/heads/main
| 2023-06-15T09:51:08.288251
| 2022-07-21T16:19:33
| 2022-07-21T16:19:33
| 12,899,663
| 352
| 56
|
MIT
| 2023-02-08T02:35:36
| 2013-09-17T15:51:40
|
Python
|
UTF-8
|
Python
| false
| false
| 2,752
|
py
|
google_service.py
|
"""Testing utility for working with google service APIs."""
import mock
class GoogleServiceMock:
"""Utility for creating mocks for Google APIs."""
@classmethod
def get_batch_requests(cls, mocked):
"""Return all batch requests from the mocked object."""
requests = []
for _, kwargs in mocked.call_args_list:
requests += kwargs['body']['requests']
return requests
@classmethod
def mock_drive_service(cls, create=None):
"""Create mock for a google drive service."""
mock_service = mock.Mock()
mock_permissions = mock.Mock()
mock_service.permissions.return_value = mock_permissions
mock_permissions_create = mock.Mock()
mock_permissions.create.return_value = mock_permissions_create
mock_permissions_create.execute.return_value = create
return {
'service': mock_service,
'permissions': mock_permissions,
'permissions.create': mock_permissions_create,
}
@classmethod
def mock_sheets_service(cls, create=None, get=None, values=None, batch_values=None, files=None):
"""Create mock for a google sheets service."""
mock_files = mock.Mock()
mock_files_get = mock.Mock()
mock_files_get.execute.return_value = files
mock_files.get.return_value = mock_files_get
mock_spreadsheets = mock.Mock()
mock_batch_update = mock.Mock()
mock_spreadsheets.batchUpdate = mock_batch_update
mock_create = mock.Mock()
mock_create.execute.return_value = create
mock_spreadsheets.create.return_value = mock_create
mock_get = mock.Mock()
mock_get.execute.return_value = get
mock_spreadsheets.get.return_value = mock_get
mock_values_get = mock.Mock()
mock_values_get.execute.return_value = values
mock_values_batch_get = mock.Mock()
mock_values_batch_get.execute.return_value = batch_values
mock_values = mock.Mock()
mock_values.get.return_value = mock_values_get
mock_values.batchGet.return_value = mock_values_batch_get
mock_spreadsheets.values.return_value = mock_values
mock_service = mock.Mock()
mock_service.files.return_value = mock_files
mock_service.spreadsheets.return_value = mock_spreadsheets
return {
'service': mock_service,
'spreadsheets': mock_spreadsheets,
'spreadsheets.batchUpdate': mock_batch_update,
'spreadsheets.create': mock_create,
'spreadsheets.get': mock_get,
'spreadsheets.values.batchGet': mock_values_batch_get,
'spreadsheets.values.get': mock_values_get,
}
|
6507bfe7cc000f8bb84351aa94f5f057f7e53f05
|
5b6ba0f288b1e2ac236af846a9bf546a63228476
|
/simtbx/nanoBragg/tst_nanoBragg_multipanel.py
|
95a2bb36e89510a63d9a1e3fb208cf458c9cbdc3
|
[
"BSD-3-Clause-LBNL"
] |
permissive
|
cctbx/cctbx_project
|
5b547b416cadbdf95cca21dace9f54272a08d98a
|
7f4dfb6c873fd560920f697cbfd8a5ff6eed82fa
|
refs/heads/master
| 2023-08-17T17:44:05.077010
| 2023-08-16T22:40:22
| 2023-08-16T22:40:22
| 39,508,026
| 206
| 131
|
NOASSERTION
| 2023-09-14T17:12:55
| 2015-07-22T13:36:27
|
Python
|
UTF-8
|
Python
| false
| false
| 4,016
|
py
|
tst_nanoBragg_multipanel.py
|
"""
Simple test of multi-panel
detector simulation
"""
from __future__ import absolute_import, division, print_function
import numpy as np
import copy
import simtbx.nanoBragg
from scitbx.matrix import sqr
from dxtbx.model.beam import BeamFactory
from dxtbx.model.crystal import CrystalFactory
from dxtbx.model.detector import DetectorFactory, Detector, Panel
from six.moves import range
# dxtbx beam model description
beam_descr = {'direction': (0.0, 0.0, 1.0),
'divergence': 0.0,
'flux': 1e12,
'polarization_fraction': 1.,
'polarization_normal': (0.0, 1.0, 0.0),
'sigma_divergence': 0.0,
'transmission': 1.0,
'wavelength': 1.4}
# dxtbx crystal description
cryst_descr = {'__id__': 'crystal',
'real_space_a': (79, 0, 0),
'real_space_b': (0, 79, 0),
'real_space_c': (0, 0, 38),
'space_group_hall_symbol': '-P 4 2'}
# monolithic camera description
det_descr = {'panels':
[{'fast_axis': (-1.0, 0.0, 0.0),
'gain': 1.0,
'identifier': '',
'image_size': (512, 256),
'mask': [],
'material': '',
'mu': 0.0,
'name': 'Panel',
'origin': (25.6, -12.8, -100),
'pedestal': 0.0,
'pixel_size': (0.1, 0.1),
'px_mm_strategy': {'type': 'SimplePxMmStrategy'},
'raw_image_offset': (0, 0),
'slow_axis': (0.0, 1.0, 0.0),
'thickness': 0.0,
'trusted_range': (0.0, 65536.0),
'type': ''}]}
beam = BeamFactory.from_dict(beam_descr)
whole_det = DetectorFactory.from_dict(det_descr)
cryst = CrystalFactory.from_dict(cryst_descr)
def main():
# ---------
SIM = simtbx.nanoBragg.nanoBragg( whole_det, beam)
SIM.Amatrix = sqr(cryst.get_A()).transpose().elems
SIM.default_F = 1
SIM.F000 = 10
SIM.oversample=2
SIM.Ncells_abc = (5,5,5)
SIM.show_params()
SIM.add_nanoBragg_spots()
SIM.raw_pixels *= 2000
wholepix = SIM.raw_pixels.as_numpy_array()
# ---------
# now make 2 smaller detectors
# that equal the whole detector above
# then append them as a dials multi panel
origin0 = (25.6, -12.8, -100)
origin1 = (25.6, 0, -100)
panel_size =(512, 128)
pan0 = {'fast_axis': (-1.0, 0.0, 0.0),
'gain': 1.0,
'identifier': '',
'image_size': (512, 128),
'mask': [],
'material': '',
'mu': 0.0,
'name': 'panel1',
'origin': origin0,
'pedestal': 0.0,
'pixel_size': (0.1, 0.1),
'px_mm_strategy': {'type': 'SimplePxMmStrategy'},
'raw_image_offset': (0, 0),
'slow_axis': (0.0, 1.0, 0.0),
'thickness': 0.0,
'trusted_range': (0.0, 65536.0),
'type': ''}
pan1 = copy.deepcopy(pan0)
pan1["origin"] = origin1
# combine the panels into a multi-panel detector
parts_det = Detector()
parts_det.add_panel( Panel.from_dict(pan0))
parts_det.add_panel( Panel.from_dict(pan1))
SIMs = {}
for i_pan in range(2):
SIM = simtbx.nanoBragg.nanoBragg( parts_det, beam, panel_id=i_pan)
SIM.Amatrix = sqr(cryst.get_A()).transpose().elems
SIM.default_F = 1
SIM.F000 = 10
SIM.oversample=2
SIM.Ncells_abc = (5,5,5)
SIM.add_nanoBragg_spots()
SIM.raw_pixels *= 2000
SIMs[i_pan] = SIM
# check comparison with whole camera
# ----------------------------------
# combine the two panels:
pix0 = SIMs[0].raw_pixels.as_numpy_array()
pix1 = SIMs[1].raw_pixels.as_numpy_array()
# FIXME: not sure why but in this case the first pixel in memory is off by 0.05
# but the others are all close..
pix1[0,0] = wholepix[128,0] # pix1[0,0] = 1.217 and pix[128,0] = 1.264
pix01 = np.vstack((pix0,pix1))
assert( np.allclose(wholepix, pix01))
if __name__=="__main__":
main()
print("OK")
|
2b09fd73c0052b302d451a225614a53ab7519c30
|
472c0ba1911619f8e2e1a68b4f956fad05be4e94
|
/src/matlab2cpp/rules/_reserved.py
|
75a0236eba0b581a7fc43582f94fdd693c51a167
|
[
"BSD-3-Clause"
] |
permissive
|
jonathf/matlab2cpp
|
f8b9541cf79507ec764b04b8211e73c47a20c131
|
b6e2cbaedb36c909952911adfe44fe26252a36a1
|
refs/heads/master
| 2022-08-08T21:28:23.028072
| 2022-07-15T19:58:01
| 2022-07-15T19:58:01
| 31,599,354
| 197
| 68
|
BSD-3-Clause
| 2022-07-15T19:58:02
| 2015-03-03T13:20:32
|
Python
|
UTF-8
|
Python
| false
| false
| 38,389
|
py
|
_reserved.py
|
"""
Reserved translation rules
See :py:attr:`rules.reserved <matlab2cpp.rules.reserved>` for a collection of
set of the various reserved words implemented into matlab2cpp.
"""
import matlab2cpp
# List of function names that should be handled by reserved.py:
reserved = {
"and", "or", "not", "all", "any", "isequal",
"false", "true", "pi", "inf", "Inf", "nan", "NaN",
"eps", "exp", "log", "log2", "log10", "power", "floor", "ceil", "fix",
"cos", "acos", "cosh", "acosh",
"sin", "asin", "sinh", "asinh", "mod",
"eye", "fliplr", "flipud", "length", "max", "min", "size", "chol",
"trace", "transpose", "ctranspose",
"abs", "sqrt", "nextpow2", "fft", "ifft", "fft2", "ifft2", "hankel",
"zeros", "ones", "round", "return", "rand",
"qr",
"clear", "close", "clc", "clf", "more", "format",
"_conv_to", "_reshape", "reshape",
"interp1", "linspace", "varargin",
"sum", "cumsum", "conj", "real", "imag",
"tic", "toc", "diag", "tril", "triu",
"disp", "fprintf", "error", "convmtx", "conv2",
"figure", "clf", "cla", "show", "xlabel", "ylabel", "hold", "load",
"title", "plot", "imshow", "imagesc", "wigb", "colorbar",
"xlim", "ylim", "caxis", "axis", "grid", "subplot", "colormap",
"_splot", "logspace", "find", "unique", "intersect", "isempty", "sortrows",
}
# Common attribute
from .assign import Assign
#Assign = "%(0)s = %(1)s ;"
def Var(node):
return "%(name)s"
Var_pi = "datum::pi"
Var_true = "1"
Var_false = "0"
Var_inf = "datum::inf"
Var_Inf = "datum::inf"
Var_nan = "datum::nan"
Var_NaN = "datum::nan"
Var_eps = "datum::eps"
def Get_NaN(node):
return "arma::zeros(", ", ", ") * datum::nan"
def conv_to(str, type):
return "arma::conv_to<" + type + ">::from(" + str + ")"
def Assign_elemwise_(node):
if node[0].type != node[1].type:
if node[0].dim == 0 and node[1].dim == 0:
return "%(0)s = " + node[0].type + "(%(1)s) ;"
if node[0].dim == 0 and node[1].dim > 0:
if node[0].mem != node[1].mem:
return "%(0)s = " + node[0].type + "(arma::as_scalar(%(1)s)) ;"
return "%(0)s = arma::as_scalar(%(1)s) ;"
if node[0].mem != node[1].mem:
return "%(0)s = arma::conv_to<" + node[0].type + ">::from(%(1)s) ;"
return "%(0)s = %(1)s ;"
def Get_exp(node):
node.type = node[0].type
# scalar done through std
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::exp(", ", ", ")"
return "arma::exp(", ", ", ")"
def Get_log(node):
node.type = node[0].type
# scalar done through std
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::log(", ", ", ")"
return "arma::log(", ", ", ")"
def Get_log2(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::log(%(0)s)/std::log(2)"
#seems like it is a C++11 feature
#return "std::log2(", ", ", ")"
return "arma::log2(", ", ", ")"
def Get_log10(node) :
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::log10(", ", ", ")"
return "arma::log10(", ", ", ")"
def Get_power(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::pow(", ", ", ")"
return "arma::pow(", ", ", ")"
def Get_floor(node):
# unknown input
#if node[0].type == "TYPE":
# return "floor(", ", ", ")"
node.type = node[0].type
# scalar done through std
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::floor(", ", ", ")"
return "arma::floor(", ", ", ")"
def Get_ceil(node):
node.type = node[0].type
# scalar done through std
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::ceil(%(0)s)"
return "arma::ceil(%(0)s)"
def Get_round(node):
node.type = node[0].type
assert len(node)<3
# number of decimals to retain
if len(node) == 2:
decimals = str(node[1])
else:
decimals = "0"
# int and uword do not have decimals
if node[0].mem < 2:
return "%(0)s"
# hack to cut-off for scalars
if node[0].dim == 0:
node.include("cmath")
if decimals == "0":
return "std::round(%(0)s)"
return "std::round(%(0)s*std::pow(10, %(1)s))*std::pow(10, -%(1)s)"
# hack for cut-off for array-type
if decimals == "0":
return "arma::round(%(0)s)"
return "arma::round(%(0)s*std::pow(10, %(1)s))*std::pow(10, -%(1)s)"
def Get_fix(node):
node.type = node[0].type
if node[0].mem < 2:
return "%(0)s"
if node[0].dim == 0 and node[0].mem != 4:
node.include("mconvert")
return "m2cpp::fix(%(0)s)"
return "arma::trunc(%(0)s)"
def Assign_fix(node):
return Assign_elemwise_(node)
def Get_cos(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::cos(", ", ", ")"
return "arma::cos(", ", ", ")"
def Get_acos(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::acos(", ", ", ")"
return "arma::acos(", ", ", ")"
def Get_cosh(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::cosh(", ", ", ")"
return "arma::cosh(", ", ", ")"
def Get_acosh(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
#is a C++11 feature
return "std::acosh(", ", ", ")"
return "arma::acosh(", ", ", ")"
def Get_sin(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::sin(", ", ", ")"
return "arma::sin(", ", ", ")"
def Get_asin(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::asin", ", ", ")"
return "arma::asin(", ", ", ")"
def Get_sinh(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::sinh", ", ", ")"
return "arma::sinh(", ", ", ")"
def Get_asinh(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
node.include("cmath")
return "std::asinh", ", ", ")"
return "arma::asinh(", ", ", ")"
# Special handle of 'i'-variable
""" removed from reserved: "i",
def Var_i(node):
return "cx_double(0, 1)"
"""
def Get_mod(node):
node.type = node[0].type
if node[0].dim == 0 and node[0].mem != 4:
return "", " __percent__ ", ""
return "mod(", ", ", ")"
def Get_abs(node):
node.type = node[0].type
if len(node) and node[0].dim == 0:
if node[0].mem == 4: #cx_double
node.include("m2cpp")
return "abs(m2cpp::smat(%(0)s))"
node.include("cmath")
return "std::abs(", ", ", ")"
return "abs(", ", ", ")"
def Get_sqrt(node):
node.type = node[0].type
#if len(node) > 0 ...
if len(node) and node[0].cls == "Neg" and len(node[0]) == 1:
return "cx_double(0, " + node[0][0].str + ")"
return "sqrt(", ", ", ")"
def Get_and(node):
return "(", "*", ")"
def Get_or(node):
return "("+"+".join(["%(" + i +")s*%(" + i + ")s" \
for i in range(len(node))])+")"
def Get_not(node):
assert len(node) == 1
if not node[0].num:
return "not(%(0)s)"
return "(%(0)s == 0)"
def Get_any(node):
if not node[0].num:
return "any(", ", ", ")"
# unknown datatype
if node[0].dim == 0:
return "%(0)s"
return "any(", ", ", ")"
def Get_all(node):
# unkonwn datatype
if not node[0].num:
return "all(", ", ", ")"
# scalar value
if node[0].dim == 0:
return "%(0)s"
return "all(", ", ", ")"
def Get_isequal(node):
return "%(0)s == %(1)s"
def Var_return(node):
# multi-return does not return a value
if node.func.backend == "func_returns":
return "return"
return "return " + str(node.func[0])
def Get_size(node):
# unknown input
if node[0].type == "TYPE" or node.parent.cls == "Assigns":
return "size(", ", ", ")"
var = str(node[0])
# multiple args
if len(node) > 1:
# determine ax from second arg
arg2 = node[1].value
if arg2 == "1":
return var+".n_rows"
if arg2 == "2":
return var+".n_cols"
if arg2 == "3":
return var+".n_slices"
# colvec or rowvec
elif node[0].dim in (1,2):
#if node.parent.backend == "reserved" and\
# node.parent.name in ("min", "max"):
# return var+".n_elem"
#if node[0].dim == 1:
# return "%(0)s.n_elem, 1"
#elif node[0].dim == 2:
# return "1, %(0)s.n_elem"
#return var+".n_elem"
if node.parent.cls == "Get":
if node.parent.backend in ("reserved", "func_return",
"func_returns", "func_lambda", "unknown"):
return "%(0)s.n_rows, %(0)s.n_cols"
# inline calls moved to own line
if node.parent.cls not in ("Statement", "Assign"):
return str(node.auxiliary())
return "{%(0)s.n_rows, %(0)s.n_cols}"
# matrix (returns two values)
elif node[0].dim == 3:
if node.parent.cls == "Get":
if node.parent.backend in ("reserved", "func_return",
"func_returns", "func_lambda", "unknown"):
return "%(0)s.n_rows, %(0)s.n_cols"
return "%(0)s.n_rows-1, %(0)s.n_cols"
# inline calls moved to own line
if node.parent.cls not in ("Statement", "Assign"):
return str(node.auxiliary())
return "{%(0)s.n_rows, %(0)s.n_cols}"
# cube (return three values)
elif node[0].dim == 4:
if node.parent.cls == "Get":
if node.parent.backend in ("reserved", "func_return",
"func_returns", "func_lambda", "unknown"):
return "%(0)s.n_rows, %(0)s.n_cols, %(0)s.n_slices"
return "%(0)s.n_rows-1, %(0)s.n_cols-1, %(0)s.n_slices"
# inline calls moved to own line
if node.parent.cls not in ("Statement", "Assign"):
return str(node.auxiliary())
return "{%(0)s.n_rows, %(0)s.n_cols, %(0)s.n_slices}"
return "size(", ", ", ")"
def Assign_size(node):
num = node[-1][0].dim == 3 and "2" or "2"
if len(node[-1]) == 2 and (node[-1][1].str == "1" or node[-1][1].str == "2"):
return "%(0)s = %(1)s ;"
else:
return "uword _%(0)s [] = %(1)s ;\n"+\
"%(0)s = urowvec(_%(0)s, " + num + ", false) ;"
def Assigns_size(node):
val = node[-1][0]
# multi-assigned size to own line
if val.cls != "Var":
val = val.auxiliary()
val = str(val)
# suggest some types for matrix
out = ""
if node[0].str != '~':
out += "%(0)s = " + val + ".n_rows;\n"
if node[1].str != '~':
out += "%(1)s = " + val + ".n_cols;\n"
if len(node) == 4 and node[2] != '~':
out += "%(2)s = " + val + ".n_slices;\n"
#if len(node)==3:
# return
# return "%(0)s = " +val+ ".n_rows ;\n%(1)s = " +val+ ".n_cols ;"
if not (len(node) == 3 or len(node) == 4):
raise NotImplementedError
return out
# suggest some types for cube
#if len(node)==4:
# return "%(0)s = "+val+".n_rows ;\n"+\
# "%(1)s = "+val+".n_cols ;\n"+\
# "%(2)s = "+val+".n_slices ;"
def Get_chol(node):
return "", ", ", ""
def Assign_chol(node):
lhs, rhs = node
my_list = []
for n in rhs:
my_list.append(n.str)
my_string = ", ".join(my_list)
return "%(0)s = chol(" + my_string + ") ;"
def Assigns_chol(node):
lhs = node[:-1]
rhs = node[-1]
if len(lhs) == 2:
rhs_string = lhs[0].str + ", " + rhs.str
# flip p bool value, to get same value as matlab
ret_bool = lhs[1].str + " = !" + lhs[1].str + " ;"
return lhs[1].str + " = chol(" + rhs_string + ") ;\n" + ret_bool
# Default out. If more lhs values, then write new if statement
lhs_list = [n.str for n in lhs]
rhs_list = [n.str for n in rhs]
lhs_string = ", ".join(lhs_list)
rhs_string = ", ".join(rhs_list)
return "[" + lhs_string + "]" + " = chol(" + rhs_string + ") ;"
def Get_unique(node):
node.include("m2cpp")
return "", ", ", ""
def Assign_unique(node):
node.include("m2cpp")
args = ", ".join([n.str for n in node])
return "m2cpp::unique(" + args + ");"
def Assigns_unique(node):
node.include("m2cpp")
args = ", ".join([n.str for n in node])
return "m2cpp::unique(" + args + ");"
def Get_sortrows(node):
node.include("m2cpp")
args = ", ".join([n.str for n in node])
return "m2cpp::sortrows(" + args + ");"
def Get_intersect(node):
node.include("m2cpp")
return "", ", ", ""
def Assign_intersect(node):
node.include("m2cpp")
lhs, rhs = node
my_list = []
for n in rhs:
my_list.append(n.str)
my_string = ", ".join(my_list)
return "%(0)s = m2cpp::intersect(" + my_string + ") ;"
def Assigns_intersect(node):
node.include("m2cpp")
rhs = ", ".join([n.str for n in node])
return "m2cpp::intersect(" + rhs + ");"
def Get_length(node):
# array-type uses n_elem
if node.cls == "Var":
return "%(0)s.n_elem"
node.include("m2cpp")
return "m2cpp::length(%(0)s)"
def Get_isempty(node):
node.include("m2cpp")
return "m2cpp::isempty(%(0)s)"
def Get_min(node):
# non.numerical input
if not all([n.num for n in node]):
return "min(", ", ", ")"
# everything scalar
if all([(n.dim < 1) for n in node]):
if any([n.mem == 4 for n in node]):
node.include("m2cpp")
nodes = map(str, node)
nodes = ["m2cpp::smat<cx_double>(" + name + ")" for name in nodes]
arg = ", ".join(nodes)
return "arma::min(" + arg + ")"
node.include("algorithm")
return "std::min(", ", ", ")"
# single arg
if len(node) == 1:
return "arma::min(%(0)s)"
# two args
if len(node) == 2:
if node[0].dim and node[1].dim:
return "arma::min(%(0)s, %(1)s)"
if node[0].dim==0:
return "arma::clamp(%(1)s, %(1)s.min(), %(0)s)"
if node[1].dim==0:
return "arma::clamp(%(0)s, %(0)s.min(), %(1)s)"
# three args
if len(node) == 3:
if node[2].dim == 0:
# assues third arg is int and sets axis
val = node[2].value
if val == "1":
return "arma::min(%(0)s, 1)"
elif val == "2":
return "arma::min(%(0)s, 0)"
return "arma::min(%(0)s, %(2)s-1)"
assert False
def Assigns_min(node):
assert len(node) == 3
var = node[2][0]
# non-numerical assignment
if not var.num:
return "[", ", ", "] = min(", ") ;"
# multi-assignmens on own line
if var.cls != "Var":
var = var.auxiliary()
var = str(var)
if node[0].str != '~':
return "%(0)s = " + var + ".min(%(1)s) ;"
else:
return var + ".min(%(1)s);"
def Get_max(node):
# non.numerical input
if not all([n.num for n in node]):
return "max(", ", ", ")"
# everything scalar
if all([(n.dim<1) for n in node]):
if any([n.mem == 4 for n in node]):
node.include("m2cpp")
nodes = map(str, node)
nodes = ["m2cpp::smat<cx_double>(" + name + ")" for name in nodes]
arg = ", ".join(nodes)
return "arma::max(" + arg + ")"
# single element, uword (returned from size(a))
#if len(node) == 1 and node[0].dim == 0:
# return "%(0)s"
node.include("algorithm")
return "std::max(", ", ", ")"
# number of args is ...
if len(node) == 1:
return "arma::max(%(0)s)"
if len(node) == 2:
if node[0].dim and node[1].dim:
return "arma::max(%(0)s, %(1)s)"
if node[0].dim==0:
return "arma::clamp(%(1)s, %(0)s, %(1)s.max())"
if node[1].dim==0:
return "arma::clamp(%(0)s, %(1)s, %(0)s.max())"
if len(node) == 3:
if node[2].dim == 0:
# thrid argument sets axis to take max over
val = node[2]["value"]
if val == "1":
return "arma::max(%(0)s, 1)"
elif val == "2":
return "arma::max(%(0)s, 0)"
return "arma::max(%(0)s, %(2)s-1)"
assert False
def Assigns_max(node):
assert len(node) == 3
# right hand side of assignment
var = node[-1]
# non-numerical input
if not var.num:
return "[", ", ", "] = max(", ") ;"
# multi-assign max on own line
if var.cls != "Var":
var = var.auxiliary()
var = str(var)
if node[0].str != '~':
return "%(0)s = " + var + ".max(%(1)s);"
else:
var + ".max(%(1)s);"
Var_eye = "1"
def Get_eye(node):
# not numerical input
if not node[0].num:
return "eye(", ", ", ")"
# single argument constructor
if len(node) == 1:
if node[0].dim == 0:
return "arma::eye<%(type)s>(%(0)s, %(0)s)"
return "arma::eye<%(type)s>(%(0)s(0), %(0)s(1))"
# double arguments
if len(node) == 2:
return "arma::eye<%(type)s>(%(0)s, %(1)s)"
raise NotImplementedError
def Get_trace(node):
return "arma::trace(", ", ", ")"
def Get_transpose(node):
"""Simple transpose
"""
return "arma::strans(%(0)s)"
def Get_ctranspose(node):
"""Complex transpose
"""
return "arma::trans(%(0)s)"
def Get_fliplr(node):
return "arma::fliplr(%(0)s)"
def Get_flipud(node):
return "arma::flipud(%(0)s)"
def Get_ones(node):
# one argument
if len(node) == 1:
#size as argument: zeros(size(A))
if node[0].backend == "reserved" and node[0].name == "size":
#Take the type of the LHS, normally it is the other way around
if node.parent.cls == "Assign" and node.parent[0] != node:
out = "arma::ones<" + node.parent[0].type + ">("
return out, ", ", ")"
#return "arma::ones<%(type)s>(", ", ", ")"
#arg input is a scalar
if node[0].num and node[0].dim == 0:
#dim is matrix
if node.dim == 3:
return "arma::ones<%(type)s>(%(0)s, %(0)s)"
# arg input is vector
if node[0].num and node[0].dim in (1,2):
# non-trivial variables moved out to own line
if node[0].cls != "Var":
node[0].auxiliary()
# indexing arg as input
if node.dim in (1,2):
return "arma::ones<%(type)s>(%(0)s(0))"
if node.dim == 3:
return "arma::ones<%(type)s>(%(0)s(0), %(0)s(1))"
if node.dim == 4:
return "arma::ones<%(type)s>(%(0)s(0), %(0)s(1), %(0)s(2))"
# two args where one vector and other "1" handled specially
elif len(node) == 2:
if node.dim == 3:
return "arma::ones<%(type)s>(%(0)s, %(1)s)"
if node.dim in (1,2):
if node[0].cls == "Int" and node[0].value == "1":
return "arma::ones<%(type)s>(%(1)s)"
if node[1].cls == "Int" and node[1].value == "1":
return "arma::ones<%(type)s>(%(0)s)"
return "arma::ones<%(type)s>(", ", ", ")"
def Get_zeros(node):
# one argument
if len(node) == 1:
#size as argument: zeros(size(A))
if node[0].backend == "reserved" and node[0].name == "size":
#Take the type of the LHS, normally it is the other way around
if node.parent.cls == "Assign" and node.parent[0] != node:
out = "arma::zeros<" + node.parent[0].type + ">("
return out, ", ", ")"
#return "arma::zeros<%(type)s>(", ", ", ")"
#arg input is a scalar
if node[0].num and node[0].dim == 0:
#dim is matrix
if node.dim == 3:
return "arma::zeros<%(type)s>(%(0)s, %(0)s)"
# arg input is vector
if node[0].num and node[0].dim in (1,2):
# non-trivial variables moved out to own line
if node[0].cls != "Var":
node[0].auxiliary()
# indexing arg as input if vector
if node.dim in (1,2):
return "arma::zeros<%(type)s>(%(0)s(0))"
if node.dim == 3:
return "arma::zeros<%(type)s>(%(0)s(0), %(0)s(1))"
if node.dim == 4:
return "arma::zeros<%(type)s>(%(0)s(0), %(0)s(1), %(0)s(2))"
# double argument creates colvec/rowvec/matrix depending on context
elif len(node) == 2:
if node.dim == 3:
return "arma::zeros<%(type)s>(%(0)s, %(1)s)"
if node.dim in (1,2):
# use colvec if first index is '1'
if node[0].cls == "Int" and node[0].value == "1":
return "arma::zeros<%(type)s>(%(1)s)"
# use rowvec if second index is '1'
elif node[1].cls == "Int" and node[1].value == "1":
return "arma::zeros<%(type)s>(%(0)s)"
return "arma::zeros<%(type)s>(", ", ", ")"
def Get_qr(node):
return "", ", ", ""
def Assign_qr(node):
return "arma::qr(", ", ", ")"
def Assigns_qr(node):
return "arma::qr(", ", ", ")"
def Var_rand(node):
return "arma::randu<" + node.type + ">(1)"
def Get_rand(node):
return "arma::randu<" + node.type + ">(", ", ", ")"
def Var_clear(node):
#index = node.parent.children.index(node)
#print(node.parent.parent.names)
#del node.parent.parent.children[0]
#print(node.parent.summary())
#return ""
return "// clear"
def Get_clear(node):
return "// clear(", ", ", ")"
def Var_close(node):
return "// close"
def Get_close(node):
return "// close(", ", ", ")"
def Var_clc(node):
return "// clc"
def Get_clc(node):
return "// clc"
def Var_clf(node):
return "// clf"
def Get_clf(node):
return "// clf"
def Var_more(node):
return "// more"
def Get_more(node):
return "// more"
def Var_format(node):
return "// format"
def Get_format(node):
return "// format"
def Get__conv_to(node):
return "conv_to<%(type)s>::from(%(0)s)"
def Get__reshape(node):
return "%(value)s(", ", ", ")"
def Get_reshape(node):
return "reshape(", ", ", ")"
def Get_nextpow2(node):
node.include("m2cpp")
return "m2cpp::nextpow2(", ", ", ")"
def Assign_fft(node):
if node[0].mem == 3:
return "%(0)s = arma::conv_to<" + node[0].type + ">::from(%(1)s) ;"
return "%(0)s = %(1)s ;"
def Assign_ifft(node):
return Assign_fft(node)
def Get_fft(node):
if node[0].mem != None:
node.type = node[0].type
# arma & matlab fft same for n_args in (1,2)
if len(node) in (1, 2):
return "arma::fft(", ", ", ")"
elif len(node) == 3:
if node[0].dim in (1,2):
return "arma::fft(%(0)s, %(1)s)"
if node[1].cls == "Matrix":
node.include("m2cpp")
return "m2cpp::fft<" + node[0].type + ">(%(0)s, %(2)s)"
else:
node.include("m2cpp")
return "m2cpp::fft<" + node[0].type + ">(", ", ", ")"
else:
node.error("Number of args in 'fft' should be between 1 and 3")
return "arma::fft(", ", ", ")"
def Get_ifft(node):
if node[0].mem != None:
node.type = node[0].type
# unknown input
if not node.num:
return "arma::ifft(", ", ", ")"
if len(node) == 1:
return "arma::ifft<%(type)s>(%(0)s)"
elif len(node) == 2:
return "arma::ifft<%(type)s>(%(0)s, %(1)s)"
elif len(node) == 3:
if node[0].dim in (1, 2):
return "arma::ifft<%(type)s>(%(0)s, %(1)s)"
if node[1].cls == "Matrix":
node.include("m2cpp")
return "m2cpp::ifft<%(type)s>(%(0)s, %(2)s)"
else:
node.include("m2cpp")
return "m2cpp::ifft<%(type)s>(", ", ", ")"
else:
node.error("Number of args in 'ifft' should be between 1 and 3")
if node[0].mem != 4:
node.warning("Argument datatype of 'ifft' should be complex")
return "arma::ifft(", ", ", ")"
def Get_fft2(node):
if node[0].mem != None:
node.type = node[0].type
return "arma::fft2(", ", ", ")"
def Get_ifft2(node):
if node[0].mem != None:
node.type = node[0].type
return "arma::ifft2(", ", ", ")"
def Assign_fft2(node):
return Assign_fft(node)
def Assign_ifft2(node):
return Assign_fft(node)
def Get_hankel(node):
node.include("m2cpp")
return "m2cpp::hankel(", ", ", ")"
def Get_interp1(node):
if node.parent.cls == "Assign":
out = "arma::interp1(%(0)s, %(1)s, %(2)s, " + node.parent[0].str
if node[-1].type == "string":
out = out + ", %(3)s)"
else:
out = out + ")"
else:
out = "arma::interp1(", ", ", ")"
return out
def Assign_interp1(node):
return "%(1)s ;"
def Get_linspace(node):
return "arma::linspace<%(type)s>(", ", ", ")"
def Get_sum(node):
"""
Summation function.
Examples:
>>> print(matlab2cpp.qscript("a=[1,2]; b = sum(a)", suggest=True))
sword _a [] = {1, 2} ;
a = irowvec(_a, 2, false) ;
b = int(arma::as_scalar(arma::sum(a))) ;
>>> print(matlab2cpp.qscript("a=[1.5;2]; b = sum(a)", suggest=True))
double _a [] = {1.5, 2} ;
a = vec(_a, 2, false) ;
b = double(arma::as_scalar(arma::sum(a))) ;
>>> print(matlab2cpp.qscript("a=[-1,2;3,4]; b = sum(a, 1)", suggest=True))
sword _a [] = {-1, 2, 3, 4} ;
a = arma::strans(imat(_a, 2, 2, false)) ;
b = arma::sum(arma:vectorize(a), 0) ;
>>> print(matlab2cpp.qscript("a=[1., 2.; 3., 4.]; b = sum(a(:))", suggest=True))
double _a [] = {1., 2., 3., 4.} ;
a = arma::strans(mat(_a, 2, 2, false)) ;
b = double(arma::as_scalar(arma::sum(arma:vectorize(a(span(0, a.n_rows-1)))))) ;
>>> print(matlab2cpp.qscript("a=rand(9, 9, 9); b = sum(a(:))", suggest=True))
a = arma::randu<cube>(9, 9, 9) ;
b = double(arma::as_scalar(arma::sum(arma:vectorize(a(span(0, a.n_rows-1)))))) ;
"""
arg = node[0]
# unknown input
if not arg.num or arg.dim == 0:
node.error("sum over non-array")
return "arma::sum(", ", ", ")"
if arg.dim > 2:
arg = "arma:vectorize(%(0)s)"
else:
arg = "%(0)s"
# second argument should be dim, matlab uses dim 1/2, and armadillo 0/1
if len(node) == 1:
node.dim = 0
out = "%(type)s(arma::as_scalar(arma::sum(" + arg + ")))"
elif len(node) == 2:
out = "arma::sum(" + arg + ", %(1)s-1)"
else:
out = "arma::sum(", ", ", ")"
return out
def Get_cumsum(node):
if len(node) < 2:
return "cumsum(", ", ", ")"
elif len(node) == 2:
return "cumsum(%(0)s, %(1)s-1)"
else:
return "cumsum(", ", ", ")"
def Get_conj(node):
if node.dim == 0:
if node.mem == 4:
node.include("complex")
return "std::conj(", ", ", ")"
else:
return "%(0)s"
return "arma::conj(", ", ", ")"
def Get_imag(node):
return "arma::imag(", ", ", ")"
def Get_real(node):
# output always real
return "arma::real(", ", ", ")"
def Var_tic(node):
return Get_tic(node)
def Get_tic(node):
node.wall_clock()
node.type = 'double'
return "m2cpp::tic()"
def Assign_tic(node):
node.wall_clock()
node[0].type = 'double'
return "%(0)s = m2cpp::tic();"
def Var_toc(node):
return Get_toc(node)
def Get_toc(node):
node.wall_clock()
arg = ", ".join([n.str for n in node])
if node.parent.cls != "Statement":
return "m2cpp::toc(" + arg + ")"
node.include("iostream")
return 'std::cout << "Elapsed time = " << m2cpp::toc(' + arg + ') << std::endl'
def Get_diag(node):
if node.dim == 3:
return "diagmat(", ", ", ")"
return "diagvec(", ", ", ")"
def Get_tril(node):
return "trimatl(", ", ", ")"
def Get_triu(node):
return "trimatu(", ", ", ")"
def Var_disp(node):
return "// disp"
def Get_disp(node):
node.include("iostream")
if len(node) == 1:
arg = node[0]
if not arg.num or arg.dim == 0:
return "std::cout << %(0)s << std::endl"
else:
return "%(0)s.print()"
else:
node.error("disp should take one argument")
return "std::cout << ", "<< ", " << std::endl"
def Get_fprintf(node):
""" Matlab's fprintf can write to file and screen... this is translated to printf (so only printing to screen)
will give error if trying to write to file.
"""
node.include("cstdio")
return "std::printf(", ", ", ")"
def Get_error(node):
node.include("iostream")
return "std::cerr << ", "<< ", " << std::endl"
def Get_convmtx(node):
node.include("m2cpp")
return "m2cpp::convmtx(", ", ", ")"
def Get_conv2(node):
node.include("m2cpp")
return "m2cpp::conv2<%(type)s>(", ", ", ")"
#return "m2cpp::conv2<" + node[0].type + "," + node[1].type + ">(", ", ", ")"
#SPlot reserved words
def Get_figure(node):
node.plotting()
return "_plot.figure(", ", ", ")"
def Var_hold(node):
return Get_hold(node)
def Get_hold(node):
node.plotting()
if node and node[0].cls == "String":
if node[0].value == "on":
return "_plot.hold(1)"
if node[0].value == "off":
return "_plot.hold(0)"
node.error('argument must either be "on" or "off"')
return "_plot.hold(", ", ", ")"
node.error("hold toggle not supported")
return "_plot.hold(", ", ", ")"
def Var_load(node):
return Get_load(node)
def Get_load(node):
out = "load " + node.code
if len(node) == 1:
if node[0].cls == "String":
name = str(node[0].value).split(".")[0]
out = name + ".load(%(0)s)"
else:
out = "%(0)s.load(\"" + node.value + "\")"
return out
def Var_clf(node):
return Get_clf(node)
def Get_clf(node):
node.plotting()
return "_plot.clf(", ", ", ")"
def Var_cla(node):
return Get_cla(node)
def Get_cla(node):
node.plotting()
return "_plot.cla(", ", ", ")"
def Get_show(node):
node.plotting()
return "_plot.show(", ", ", ")"
def Get_xlabel(node):
node.plotting()
return "_plot.xlabel(", ", ", ")"
def Get_ylabel(node):
node.plotting()
return "_plot.ylabel(", ", ", ")"
def Get_title(node):
node.plotting()
return "_plot.title(", ", ", ")"
def Get_plot(node):
node.plotting()
if len(node) > 2:
state = True
num_children = len(node)
cur_child = 0
out = ""
while state:
#if cur_child > 0 and cur_child < num_children:
# out += "\n"
#elif cur_child >= num_children:
# break
out += "_plot.plot("
#add next two childen
if (cur_child+2) <= num_children:
out += "%(" + str(cur_child) + ")s, "
cur_child += 1
out += "%(" + str(cur_child) + ")s"
cur_child += 1
#test if linespec
if cur_child < num_children and node[cur_child].type == "string":
out += ", %(" + str(cur_child) + ")s"
cur_child += 1
elif cur_child < num_children and node[cur_child].type != "string":
out += ""
elif cur_child >= num_children:
out += ""
#add next two children
if (cur_child+2) <= num_children:
out += ", %(" + str(cur_child) + ")s, "
cur_child += 1
out += "%(" + str(cur_child) + ")s"
cur_child += 1
#test if linespec
if cur_child < num_children and node[cur_child].type == "string":
out += ", %(" + str(cur_child) + ")s"
cur_child += 1
elif cur_child < num_children and node[cur_child].type != "string":
out += ""
elif cur_child >= num_children:
out += ""
if (cur_child+1) <= num_children:
out += ") ;\n"
else:
out += ")"
state = False
return out
return "_plot.plot(", ", ", ")"
def Get_imshow(node):
node.plotting()
return "_plot.imshow(", ", ", ")"
def Get_imagesc(node):
node.plotting()
return "_plot.imagesc(", ", ", ")"
def Get_wigb(node):
node.plotting()
return "_plot.wigb(", ", ", ")"
def Var_colorbar(node):
return Get_colorbar(node)
def Get_colorbar(node):
node.plotting()
return "_plot.colorbar(", ", ", ")"
def Get_xlim(node):
"""
Examples:
>>> print(matlab2cpp.qscript("xlim(0.0, 3.14)"))
_plot.xlim(0.0, 3.14) ;
_plot.show() ;
>>> print(matlab2cpp.qscript("xlim([0.0, 3.14])"))
_plot.xlim(0.0, 3.14) ;
_plot.show() ;
"""
node.plotting()
if len(node) == 1:
arg = node[0]
if arg.cls == "Matrix" and len(arg[0]) == 2:
a,b = arg[0]
return "_plot.xlim(" + str(a) + ", " + str(b) + ")"
elif arg.cls != "Matrix" and arg.num and arg.dim>0:
name1 = arg.name + "(0)"
name2 = arg.name + "(1)"
if arg.mem not in (2,3):
name1 = "static_cast<double>(" + name1 + ")"
name2 = "static_cast<double>(" + name2 + ")"
return "_plot.xlim(" + name1 + ", " + name2 + ")"
node.error("argument array type")
return "_plot.xlim(", ", ", ")"
def Get_ylim(node):
"""
Examples:
>>> print(matlab2cpp.qscript("ylim(0.5,.7)"))
_plot.ylim(0.5, 0.7) ;
_plot.show() ;
>>> print(matlab2cpp.qscript("ylim([0.5,.7])"))
_plot.ylim(0.5, 0.7) ;
_plot.show() ;
"""
node.plotting()
if len(node) == 1:
arg = node[0]
if arg.cls == "Matrix" and len(arg[0]) == 2:
a,b = arg[0]
return "_plot.ylim(" + str(a) + ", " + str(b) + ")"
elif arg.cls != "Matrix" and arg.num and arg.dim>0:
name1 = arg.name + "(0)"
name2 = arg.name + "(1)"
if arg.mem not in (2,3):
name1 = "static_cast<double>(" + name1 + ")"
name2 = "static_cast<double>(" + name2 + ")"
return "_plot.ylim(" + name1 + ", " + name2 + ")"
node.error("argument array type")
return "_plot.ylim(", ", ", ")"
def Get_caxis(node):
"""
>>> print(matlab2cpp.qscript("caxis(0, 3)"))
_plot.caxis(0, 3) ;
_plot.show() ;
>>> print(matlab2cpp.qscript("caxis([0, 3])"))
_plot.caxis(0, 3) ;
_plot.show() ;
"""
node.plotting()
if len(node) == 1:
arg = node[0]
if arg.cls == "Matrix" and len(arg[0]) == 2:
a,b = arg[0]
return "_plot.caxis(" + str(a) + ", " + str(b) + ")"
elif arg.cls != "Matrix" and arg.num and arg.dim>0:
name1 = arg.name + "(0)"
name2 = arg.name + "(1)"
if arg.mem not in (2,3):
name1 = "static_cast<double>(" + name1 + ")"
name2 = "static_cast<double>(" + name2 + ")"
return "_plot.caxis(" + name1 + ", " + name2 + ")"
node.error("argument array type")
return "_plot.caxis(", ", ", ")"
def Get_axis(node):
"""
>>> print(matlab2cpp.qscript("axis(0, 3, -2, 4)"))
_plot.axis(0, 3, -2, 4) ;
_plot.show() ;
>>> print(matlab2cpp.qscript("axis([0, 3, -2, 4])"))
_plot.axis(0, 3, -2, 4) ;
_plot.show() ;
"""
node.plotting()
if len(node) == 1:
arg = node[0]
if arg.cls == "Matrix" and len(arg[0]) == 4:
a,b,c,d = arg[0]
return "_plot.axis(" + str(a) + ", " + str(b) + ", " + str(c) + ", " + str(d) + ")"
elif arg.cls != "Matrix" and arg.num and arg.dim>0:
name1 = arg.name + "(0)";
name2 = arg.name + "(1)"
name3 = arg.name + "(2)";
name4 = arg.name + "(3)"
if arg.mem not in (2,3):
name1 = "static_cast<double>(" + name1 + ")"
name2 = "static_cast<double>(" + name2 + ")"
name3 = "static_cast<double>(" + name3 + ")"
name4 = "static_cast<double>(" + name4 + ")"
return "_plot.axis(" + name1 + ", " + name2 + ", " + name3 + ", " + name4 + ")"
node.error("argument array type")
return "_plot.axis(", ", ", ")"
def Var_grid(node):
return Get_grid(node)
def Get_grid(node):
node.plotting()
if node and node[0].cls == "String":
if node[0].value == "on":
return "_plot.grid({{\"b\", \"on\"}})"
if node[0].value == "off":
return "_plot.grid({{\"b\", \"off\"}})"
node.error('argument must either be "on" or "off"')
return "_plot.grid(", ", ", ")"
return "_plot.grid(", ", ", ")"
def Get_subplot(node):
node.plotting()
return "_plot.subplot(", ", ", ")"
def Get_colormap(node):
node.plotting()
if len(node) == 1:
arg = node[0]
if len(arg) == 0:
name = str(arg)[:-2] + "(1)"
return "_plot.colormap(" + name + ")"
return "_plot.colormap(", ", ", ")"
def Get__splot(node):
return "_plot.show()"
def Get_logspace(node):
if len(node) == 2:
return "logspace<%(type)s>(%(0)s, %(1)s, 50)"
if len(node) == 3:
return "logspace<%(type)s>(%(0)s, %(1)s, %(2)s)"
return "logspace<%(type)s>(", ", ", ")"
def Get_find(node):
return "find(", ", ", ") + 1"
if __name__ == "__main__":
import doctest
doctest.testmod()
|
3cd22d5a0cd5b62145f345dba87b591187a8f201
|
acf7457d3a799cb9bff12686d2d616688bcd4b5b
|
/packages/python/chart-studio/chart_studio/tests/test_plot_ly/test_plotly/test_credentials.py
|
6659dbab6ff54eebea03ddd89a458802afcd15fd
|
[
"MIT"
] |
permissive
|
plotly/plotly.py
|
f4f61639f08160f16195efc95b5901dc5a937346
|
975a704074f01c078e0fdfa32bdf17130bf89e69
|
refs/heads/master
| 2023-09-06T06:15:08.340035
| 2023-08-24T12:28:14
| 2023-08-24T12:28:14
| 14,579,099
| 14,751
| 2,989
|
MIT
| 2023-09-08T19:55:32
| 2013-11-21T05:53:08
|
Python
|
UTF-8
|
Python
| false
| false
| 3,126
|
py
|
test_credentials.py
|
from __future__ import absolute_import
import _plotly_utils.exceptions
from chart_studio import plotly as py, exceptions
import chart_studio.session as session
import chart_studio.tools as tls
from chart_studio.tests.utils import PlotlyTestCase
import sys
# import from mock
if sys.version_info >= (3, 3):
from unittest.mock import patch
else:
from mock import patch
class TestSignIn(PlotlyTestCase):
def setUp(self):
super(TestSignIn, self).setUp()
patcher = patch("chart_studio.api.v2.users.current")
self.users_current_mock = patcher.start()
self.addCleanup(patcher.stop)
def test_get_credentials(self):
session_credentials = session.get_session_credentials()
if "username" in session_credentials:
del session._session["credentials"]["username"]
if "api_key" in session_credentials:
del session._session["credentials"]["api_key"]
creds = py.get_credentials()
file_creds = tls.get_credentials_file()
self.assertEqual(creds, file_creds)
def test_sign_in(self):
un = "anyone"
ak = "something"
# TODO, add this!
# si = ['this', 'and-this']
py.sign_in(un, ak)
creds = py.get_credentials()
self.assertEqual(creds["username"], un)
self.assertEqual(creds["api_key"], ak)
# TODO, and check it!
# assert creds['stream_ids'] == si
def test_get_config(self):
plotly_domain = "test domain"
plotly_streaming_domain = "test streaming domain"
config1 = py.get_config()
session._session["config"]["plotly_domain"] = plotly_domain
config2 = py.get_config()
session._session["config"]["plotly_streaming_domain"] = plotly_streaming_domain
config3 = py.get_config()
self.assertEqual(config2["plotly_domain"], plotly_domain)
self.assertNotEqual(config2["plotly_streaming_domain"], plotly_streaming_domain)
self.assertEqual(config3["plotly_streaming_domain"], plotly_streaming_domain)
def test_sign_in_with_config(self):
username = "place holder"
api_key = "place holder"
plotly_domain = "test domain"
plotly_streaming_domain = "test streaming domain"
plotly_ssl_verification = False
py.sign_in(
username,
api_key,
plotly_domain=plotly_domain,
plotly_streaming_domain=plotly_streaming_domain,
plotly_ssl_verification=plotly_ssl_verification,
)
config = py.get_config()
self.assertEqual(config["plotly_domain"], plotly_domain)
self.assertEqual(config["plotly_streaming_domain"], plotly_streaming_domain)
self.assertEqual(config["plotly_ssl_verification"], plotly_ssl_verification)
def test_sign_in_cannot_validate(self):
self.users_current_mock.side_effect = exceptions.PlotlyRequestError(
"msg", 400, "foobar"
)
with self.assertRaisesRegex(
_plotly_utils.exceptions.PlotlyError, "Sign in failed"
):
py.sign_in("foo", "bar")
|
a0afa87483c56f62a4b698f6587e98328f658625
|
a1cb622d58db6941f72c75920a4791cdae5c9984
|
/WDL/runtime/download.py
|
26bcf28cc54bfa5f6677cd5e8de68eb1cc7c519c
|
[
"MIT"
] |
permissive
|
chanzuckerberg/miniwdl
|
b9a5a6fee43bd65b6c2ed168c87cb3b2697ac948
|
6052fa836ea0cd91c7a07a6a2766b6cf44c0afe0
|
refs/heads/main
| 2023-08-24T03:38:39.712491
| 2023-08-13T03:03:49
| 2023-08-13T03:03:49
| 144,358,960
| 155
| 45
|
MIT
| 2023-08-12T20:20:40
| 2018-08-11T05:43:50
|
Python
|
UTF-8
|
Python
| false
| false
| 15,237
|
py
|
download.py
|
"""
Downloading input files from URIs, with plugin modules for different URI schemes
Download URI plugins are installed & registered using the setuptools entry point group
"miniwdl.plugin.file_download", with name equal to the URI scheme (e.g. "gs" or "s3").
The plugin entry point should be a context manager, which the runtime keeps open for the duration of
the download operation. Given the desired URI, it should quickly yield a tuple with:
1. source code of a WDL 1.0 task to perform the download
2. dict of Cromwell-style JSON inputs to give to the task
miniwdl then executes this specified operation, expecting it to produce an output "File file" with
the downloaded file. By doing the heavy lifting in a WDL task, the operation gets to inherit all
the functionality of miniwdl's task runtime, e.g. pulling docker image with binary dependencies,
resource scheduling & isolation, logging, error/signal handling, retry, etc.
The Python context manager itself might be used to obtain and manage the lifetime of any needed
security credentials.
"""
import os
import logging
import traceback
import tempfile
import hashlib
import shlex
from contextlib import ExitStack
from typing import Optional, Generator, Dict, Any, Tuple, Callable
from . import config
from .cache import CallCache
from .._util import compose_coroutines
from .._util import StructuredLogMessage as _
def _load(cfg: config.Loader):
if getattr(cfg, "_downloaders", None):
return
# default public URI downloaders
file_downloaders = {
"https": aria2c_downloader,
"http": aria2c_downloader,
"ftp": aria2c_downloader,
}
directory_downloaders = {}
# plugins
for plugin_name, plugin_fn in config.load_plugins(cfg, "file_download"):
file_downloaders[plugin_name] = plugin_fn
for plugin_name, plugin_fn in config.load_plugins(cfg, "directory_download"):
directory_downloaders[plugin_name] = plugin_fn
setattr(cfg, "_downloaders", (file_downloaders, directory_downloaders))
def _downloader(
cfg: config.Loader, uri: str, directory: bool = False
) -> Optional[Callable[..., Generator[Dict[str, Any], Dict[str, Any], None]]]:
_load(cfg)
colon = uri.find(":")
if colon <= 0:
return None
scheme = uri[:colon]
return getattr(cfg, "_downloaders")[1 if directory else 0].get(scheme, None)
def able(cfg: config.Loader, uri: Optional[str], directory: bool = False) -> bool:
"""
Returns True if uri appears to be a URI we know how to download
"""
return bool(uri and _downloader(cfg, uri, directory=directory) is not None)
def run(
cfg: config.Loader, logger: logging.Logger, uri: str, directory: bool = False, **kwargs
) -> str:
"""
Download the URI and return the local filename.
kwargs are passed through to ``run_local_task``, so ``run_dir`` and ``logger_prefix`` may be
useful in particular.
"""
from .error import RunFailed, DownloadFailed, Terminated, error_json
from .task import run_local_task
from .. import parse_document, values_from_json, values_to_json, Walker
gen = _downloader(cfg, uri, directory=directory)
assert gen
try:
logger.info(_(f"start {'directory ' if directory else ''}download", uri=uri))
with compose_coroutines([lambda kwargs: gen(cfg, logger, **kwargs)], {"uri": uri}) as cor:
recv = next(cor)
if "task_wdl" in recv:
task_wdl, inputs = (recv[k] for k in ["task_wdl", "inputs"])
doc = parse_document(task_wdl, version="development") # pyre-ignore
assert len(doc.tasks) == 1 and not doc.workflow
doc.typecheck()
Walker.SetParents()(doc)
task = doc.tasks[0]
inputs = values_from_json(inputs, task.available_inputs) # pyre-ignore
subdir, outputs_env = run_local_task(
cfg, task, inputs, run_id=("download-" + task.name), **kwargs
)
recv = cor.send(
{"outputs": values_to_json(outputs_env), "dir": subdir} # pyre-ignore
)
ans = recv["outputs"]["directory" if directory else "file"]
assert isinstance(ans, str) and os.path.exists(ans)
logger.info(_(f"downloaded{' directory' if directory else ' file'}", uri=uri, file=ans))
return ans
except RunFailed as exn:
if isinstance(exn.__cause__, Terminated):
raise exn.__cause__ from None
raise DownloadFailed(uri) from exn.__cause__
except Exception as exn:
logger.debug(traceback.format_exc())
logger.error(_("downloader error", uri=uri, **error_json(exn)))
raise DownloadFailed(uri) from exn
def run_cached(
cfg,
logger: logging.Logger,
cache: CallCache,
uri: str,
run_dir: str,
directory: bool = False,
**kwargs,
) -> Tuple[bool, str]:
"""
Cached download logic: returns the file from the cache if available; otherwise, runs the
download and puts it into the cache before returning
"""
cached = cache.get_download(uri, directory=directory, logger=logger)
if cached:
return True, cached
cache_path = cache.download_cacheable(uri, directory=directory)
cache_path_preexists = cache_path and os.path.exists(cache_path)
if cache_path and not cache_path_preexists:
# run the download in a holding area under the cache directory, so that it can later be
# moved atomically into its final cache location
run_dir = os.path.join(cfg["download_cache"]["dir"], "ops")
filename = run(cfg, logger, uri, directory=directory, run_dir=run_dir, **kwargs)
if cache_path_preexists:
# a cache entry had already existed, but we didn't use it (--no-cache).
# FIXME: it'd be better to replace the old copy...but what if another workflow is using it?
logger.warning(
_(
"ignored a previously-cached download, which remains in the cache",
uri=uri,
downloaded=filename,
cache_path=cache_path,
)
)
# use the newly downloaded copy in the current run directory
cache.memo_download(uri, filename, directory=directory)
return False, filename
return False, cache.put_download(
uri, os.path.realpath(filename), directory=directory, logger=logger
)
# WDL tasks for downloading a file based on its URI scheme
def aria2c_downloader(
cfg: config.Loader, logger: logging.Logger, uri: str, **kwargs
) -> Generator[Dict[str, Any], Dict[str, Any], None]:
wdl = r"""
task aria2c {
input {
String uri
String docker
Int connections = 10
}
command <<<
set -euxo pipefail
mkdir __out
cd __out
aria2c -x ~{connections} -s ~{connections} \
--file-allocation=none --retry-wait=2 --stderr=true --enable-color=false \
"~{uri}"
>>>
output {
File file = glob("__out/*")[0]
}
runtime {
docker: docker
}
}
"""
recv = yield {
"task_wdl": wdl,
"inputs": {"uri": uri, "docker": cfg["download_aria2c"]["docker"]},
}
yield recv # pyre-ignore
def awscli_downloader(
cfg: config.Loader, logger: logging.Logger, uri: str, **kwargs
) -> Generator[Dict[str, Any], Dict[str, Any], None]:
inputs: Dict[str, Any] = {"uri": uri, "docker": cfg["download_awscli"]["docker"]}
with ExitStack() as cleanup:
inputs["aws_credentials"] = prepare_aws_credentials(cfg, logger, cleanup)
wdl = r"""
task aws_s3_cp {
input {
String uri
String docker
File? aws_credentials
}
command <<<
set -euo pipefail
if [ -n "~{aws_credentials}" ]; then
source "~{aws_credentials}"
fi
export AWS_RETRY_MODE=standard
export AWS_MAX_ATTEMPTS=5
set -x
mkdir __out
if ! aws s3 cp "~{uri}" __out/ ; then
# Retry with --no-sign-request in case the object is public. Without this flag,
# the previous invocation could have failed either because (i) no AWS
# credentials are available or (ii) the IAM policy restricts accessible S3
# buckets regardless of whether the desired object is public.
rm -f __out/*
>&2 echo 'Retrying with --no-sign-request in case the object is public.' \
' If the overall operation fails, the real error may precede this message.'
aws s3 cp --no-sign-request "~{uri}" __out/
fi
>>>
output {
File file = glob("__out/*")[0]
}
runtime {
docker: docker
}
}
"""
recv = yield {"task_wdl": wdl, "inputs": inputs}
yield recv # pyre-ignore
def awscli_directory_downloader(
cfg: config.Loader, logger: logging.Logger, uri: str, **kwargs
) -> Generator[Dict[str, Any], Dict[str, Any], None]:
inputs: Dict[str, Any] = {"uri": uri, "docker": cfg["download_awscli"]["docker"]}
with ExitStack() as cleanup:
inputs["aws_credentials"] = prepare_aws_credentials(cfg, logger, cleanup)
wdl = r"""
task aws_s3_cp_directory {
input {
String uri
String docker
File? aws_credentials
}
String dnm = basename(uri, "/")
command <<<
set -euo pipefail
if [ -n "~{aws_credentials}" ]; then
source "~{aws_credentials}"
fi
export AWS_RETRY_MODE=standard
export AWS_MAX_ATTEMPTS=5
set -x
mkdir -p "__out/~{dnm}/"
if ! aws s3 cp --recursive "~{uri}" "__out/~{dnm}/" ; then
# Retry with --no-sign-request in case the object is public. Without this flag,
# the previous invocation could have failed either because (i) no AWS
# credentials are available or (ii) the IAM policy restricts accessible S3
# buckets regardless of whether the desired object is public.
rm -f "__out/~{dnm}/*"
>&2 echo 'Retrying with --no-sign-request in case the folder is public.' \
' If the overall operation fails, the real error may precede this message.'
aws s3 cp --recursive --no-sign-request "~{uri}" "__out/~{dnm}/"
fi
>>>
output {
Directory directory = "__out/" + dnm
}
runtime {
docker: docker
}
}
"""
recv = yield {"task_wdl": wdl, "inputs": inputs}
yield recv # pyre-ignore
def prepare_aws_credentials(
cfg: config.Loader, logger: logging.Logger, cleanup: ExitStack
) -> Optional[str]:
host_aws_credentials = {}
if "AWS_EC2_METADATA_DISABLED" in os.environ:
# https://github.com/aws/aws-cli/issues/5623
host_aws_credentials["AWS_EC2_METADATA_DISABLED"] = os.environ["AWS_EC2_METADATA_DISABLED"]
# get AWS credentials from boto3 (unless prevented by configuration)
if cfg["download_awscli"].get_bool("host_credentials"):
import boto3 # pyre-fixme
try:
b3creds = boto3.session.Session().get_credentials()
host_aws_credentials["AWS_ACCESS_KEY_ID"] = b3creds.access_key
host_aws_credentials["AWS_SECRET_ACCESS_KEY"] = b3creds.secret_key
host_aws_credentials["AWS_SESSION_TOKEN"] = b3creds.token
except Exception:
pass
if host_aws_credentials:
# write credentials to temp file that'll self-destruct afterwards
host_aws_credentials = (
"\n".join(f"export {k}={shlex.quote(v)}" for (k, v) in host_aws_credentials.items())
+ "\n"
)
aws_credentials_file = cleanup.enter_context(
tempfile.NamedTemporaryFile(
prefix=hashlib.sha256(host_aws_credentials.encode()).hexdigest(),
delete=True,
mode="w",
)
)
print(host_aws_credentials, file=aws_credentials_file, flush=True)
# make file group-readable to ensure it'll be usable if the docker image runs as non-root
os.chmod(aws_credentials_file.name, os.stat(aws_credentials_file.name).st_mode | 0o40)
logger.getChild("awscli_downloader").info("loaded host AWS credentials")
return aws_credentials_file.name
else:
logger.getChild("awscli_downloader").info(
"no AWS credentials available via host awscli/boto3; if needed, "
"configure them and set [download_awscli] host_credentials=true. "
"(On EC2: awscli might still assume role from instance metadata "
"service.)"
)
return None
def gsutil_downloader(
cfg: config.Loader, logger: logging.Logger, uri: str, **kwargs
) -> Generator[Dict[str, Any], Dict[str, Any], None]:
"""
Built-in downloader plugin for public gs:// URIs; registered by setup.cfg entry_points section
TODO: adopt security credentials from runtime environment
"""
if uri == "gs://8675309":
# hook for test coverage of exception handler
raise RuntimeError("don't change your number")
wdl = r"""
task gsutil_cp {
input {
String uri
String docker
}
command <<<
set -euxo pipefail
mkdir __out/
gsutil -q cp "~{uri}" __out/
>>>
output {
File file = glob("__out/*")[0]
}
runtime {
docker: docker
}
}
"""
yield ( # pyre-ignore
yield {"task_wdl": wdl, "inputs": {"uri": uri, "docker": cfg["download_gsutil"]["docker"]}}
)
def gsutil_directory_downloader(
cfg: config.Loader, logger: logging.Logger, uri: str, **kwargs
) -> Generator[Dict[str, Any], Dict[str, Any], None]:
"""
Built-in downloader plugin for public gs:// URIs; registered by setup.cfg entry_points section
TODO: adopt security credentials from runtime environment
"""
wdl = r"""
task gsutil_cp {
input {
String uri
String docker
}
String dnm = basename(uri, "/")
command <<<
set -euxo pipefail
mkdir __out/
gsutil -q -m cp -r "~{uri}" __out/
>>>
output {
Directory directory = "__out/" + dnm
}
runtime {
docker: docker
}
}
"""
yield ( # pyre-ignore
yield {"task_wdl": wdl, "inputs": {"uri": uri, "docker": cfg["download_gsutil"]["docker"]}}
)
|
faca115cfe714ab8f12ec6d3a3a8654543375319
|
972424c9c4e7415f248aa2730d0cb2b8d8de50d2
|
/pytket/pytket/utils/symbolic.py
|
c24a0dd50d264448533499c7b8e29b75502fb24b
|
[
"Apache-2.0"
] |
permissive
|
CQCL/tket
|
845e118b8215edcb48d018436be2ec84828b63b0
|
d3b783cb33a4a4a743924433cfb854c5dad12a2c
|
refs/heads/develop
| 2023-08-30T04:34:48.654880
| 2023-08-29T13:04:12
| 2023-08-29T13:04:12
| 405,970,114
| 189
| 27
|
Apache-2.0
| 2023-09-14T16:05:50
| 2021-09-13T12:46:23
|
C++
|
UTF-8
|
Python
| false
| false
| 14,460
|
py
|
symbolic.py
|
# Copyright 2019-2023 Cambridge Quantum Computing
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""Collection of methods to calculate symbolic statevectors and unitaries,
for symbolic circuits. This uses the sympy.physics.quantum module and produces
sympy objects. The implementations are slow and scale poorly, so this is
only suitable for very small (up to 5 qubit) circuits."""
from typing import Callable, Dict, List, Optional, Type, Union, cast
import numpy as np
import sympy # type: ignore
from sympy import ( # type: ignore
BlockDiagMatrix,
BlockMatrix,
Expr,
Identity,
ImmutableMatrix,
Matrix,
Mul,
I,
diag,
eye,
zeros,
)
from sympy.physics.quantum import gate as symgate # type: ignore
from sympy.physics.quantum import represent # type: ignore
from sympy.physics.quantum.tensorproduct import matrix_tensor_product # type: ignore
from sympy.physics.quantum.qapply import qapply # type: ignore
from sympy.physics.quantum.qubit import Qubit, matrix_to_qubit # type: ignore
from pytket.circuit import Circuit, Op, OpType # type: ignore
# gates that have an existing definition in sympy
_FIXED_GATE_MAP: Dict[OpType, Type[symgate.Gate]] = {
OpType.H: symgate.HadamardGate,
OpType.S: symgate.PhaseGate,
OpType.CX: symgate.CNotGate,
OpType.SWAP: symgate.SwapGate,
OpType.T: symgate.TGate,
OpType.X: symgate.XGate,
OpType.Y: symgate.YGate,
OpType.Z: symgate.ZGate,
}
ParamsType = List[Union[Expr, float]]
# Make sure the return matrix is Immutable https://github.com/sympy/sympy/issues/18733
SymGateFunc = Callable[[ParamsType], ImmutableMatrix]
SymGateMap = Dict[OpType, SymGateFunc]
# Begin matrix definitions for symbolic OpTypes
# matches internal TKET definitions
# see OpType documentation
def symb_controlled(target: SymGateFunc) -> SymGateFunc:
return lambda x: ImmutableMatrix(BlockDiagMatrix(Identity(2), target(x))) # type: ignore
def symb_rz(params: ParamsType) -> ImmutableMatrix:
return ImmutableMatrix( # type: ignore
[
[sympy.exp(-I * (sympy.pi / 2) * params[0]), 0],
[0, sympy.exp(I * (sympy.pi / 2) * params[0])],
]
)
def symb_rx(params: ParamsType) -> ImmutableMatrix:
costerm = sympy.cos((sympy.pi / 2) * params[0])
sinterm = -I * sympy.sin((sympy.pi / 2) * params[0])
return ImmutableMatrix( # type: ignore
[
[costerm, sinterm],
[sinterm, costerm],
]
)
def symb_ry(params: ParamsType) -> ImmutableMatrix:
costerm = sympy.cos((sympy.pi / 2) * params[0])
sinterm = sympy.sin((sympy.pi / 2) * params[0])
return ImmutableMatrix( # type: ignore
[
[costerm, -sinterm],
[sinterm, costerm],
]
)
def symb_u3(params: ParamsType) -> ImmutableMatrix:
theta, phi, lam = params
costerm = sympy.cos((sympy.pi / 2) * theta)
sinterm = sympy.sin((sympy.pi / 2) * theta)
return ImmutableMatrix( # type: ignore
[
[costerm, -sinterm * sympy.exp(I * sympy.pi * lam)],
[
sinterm * sympy.exp(I * sympy.pi * phi),
costerm * sympy.exp(I * sympy.pi * (phi + lam)),
],
]
)
def symb_u2(params: ParamsType) -> ImmutableMatrix:
return symb_u3([0.5] + params) # type: ignore
def symb_u1(params: ParamsType) -> ImmutableMatrix:
return symb_u3([0.0, 0.0] + params) # type: ignore
def symb_tk1(params: ParamsType) -> ImmutableMatrix:
return symb_rz([params[0]]) * symb_rx([params[1]]) * symb_rz([params[2]]) # type: ignore
def symb_tk2(params: ParamsType) -> ImmutableMatrix:
return ( # type: ignore
symb_xxphase([params[0]])
* symb_yyphase([params[1]])
* symb_zzphase([params[2]])
)
def symb_iswap(params: ParamsType) -> ImmutableMatrix:
alpha = params[0]
costerm = sympy.cos((sympy.pi / 2) * alpha)
sinterm = sympy.sin((sympy.pi / 2) * alpha)
return ImmutableMatrix( # type: ignore
[
[1, 0, 0, 0],
[0, costerm, I * sinterm, 0],
[0, I * sinterm, costerm, 0],
[0, 0, 0, 1],
]
)
def symb_phasediswap(params: ParamsType) -> ImmutableMatrix:
p, alpha = params
costerm = sympy.cos((sympy.pi / 2) * alpha)
sinterm = I * sympy.sin((sympy.pi / 2) * alpha)
phase = sympy.exp(2 * I * sympy.pi * p)
return ImmutableMatrix( # type: ignore
[
[1, 0, 0, 0],
[0, costerm, sinterm * phase, 0],
[0, sinterm / phase, costerm, 0],
[0, 0, 0, 1],
]
)
def symb_xxphase(params: ParamsType) -> ImmutableMatrix:
alpha = params[0]
c = sympy.cos((sympy.pi / 2) * alpha)
s = -I * sympy.sin((sympy.pi / 2) * alpha)
return ImmutableMatrix( # type: ignore
[
[c, 0, 0, s],
[0, c, s, 0],
[0, s, c, 0],
[s, 0, 0, c],
]
)
def symb_yyphase(params: ParamsType) -> ImmutableMatrix:
alpha = params[0]
c = sympy.cos((sympy.pi / 2) * alpha)
s = I * sympy.sin((sympy.pi / 2) * alpha)
return ImmutableMatrix( # type: ignore
[
[c, 0, 0, s],
[0, c, -s, 0],
[0, -s, c, 0],
[s, 0, 0, c],
]
)
def symb_zzphase(params: ParamsType) -> ImmutableMatrix:
alpha = params[0]
t = sympy.exp(I * (sympy.pi / 2) * alpha)
return ImmutableMatrix(diag(1 / t, t, t, 1 / t)) # type: ignore
def symb_xxphase3(params: ParamsType) -> ImmutableMatrix:
xxphase2 = symb_xxphase(params)
res1 = matrix_tensor_product(xxphase2, eye(2)) # type: ignore
res2 = Matrix(
BlockMatrix( # type: ignore
[
[xxphase2[:2, :2], zeros(2), xxphase2[:2, 2:], zeros(2)], # type: ignore
[zeros(2), xxphase2[:2, :2], zeros(2), xxphase2[:2, 2:]], # type: ignore
[xxphase2[2:, :2], zeros(2), xxphase2[2:, 2:], zeros(2)], # type: ignore
[zeros(2), xxphase2[2:, :2], zeros(2), xxphase2[2:, 2:]], # type: ignore
]
)
)
res3 = matrix_tensor_product(eye(2), xxphase2) # type: ignore
res = ImmutableMatrix(res1 * res2 * res3) # type: ignore
return res
def symb_phasedx(params: ParamsType) -> ImmutableMatrix:
alpha, beta = params
return symb_rz([beta]) * symb_rx([alpha]) * symb_rz([-beta]) # type: ignore
def symb_eswap(params: ParamsType) -> ImmutableMatrix:
alpha = params[0]
c = sympy.cos((sympy.pi / 2) * alpha)
s = -I * sympy.sin((sympy.pi / 2) * alpha)
t = sympy.exp(-I * (sympy.pi / 2) * alpha)
return ImmutableMatrix( # type: ignore
[
[t, 0, 0, 0],
[0, c, s, 0],
[0, s, c, 0],
[0, 0, 0, t],
]
)
def symb_fsim(params: ParamsType) -> ImmutableMatrix:
alpha, beta = params
c = sympy.cos(sympy.pi * alpha)
s = -I * sympy.sin(sympy.pi * alpha)
t = sympy.exp(-I * sympy.pi * beta)
return ImmutableMatrix( # type: ignore
[
[1, 0, 0, 0],
[0, c, s, 0],
[0, s, c, 0],
[0, 0, 0, t],
]
)
# end symbolic matrix definitions
class SymGateRegister:
"""Static class holding mapping from OpType to callable generating symbolic matrix.
Allows users to add their own definitions, or override existing definitions."""
_g_map: SymGateMap = {
OpType.Rx: symb_rx,
OpType.Ry: symb_ry,
OpType.Rz: symb_rz,
OpType.TK1: symb_tk1,
OpType.TK2: symb_tk2,
OpType.U1: symb_u1,
OpType.U2: symb_u2,
OpType.U3: symb_u3,
OpType.CRx: symb_controlled(symb_rx),
OpType.CRy: symb_controlled(symb_ry),
OpType.CRz: symb_controlled(symb_rz),
OpType.CU1: symb_controlled(symb_u1),
OpType.CU3: symb_controlled(symb_u3),
OpType.ISWAP: symb_iswap,
OpType.PhasedISWAP: symb_phasediswap,
OpType.XXPhase: symb_xxphase,
OpType.YYPhase: symb_yyphase,
OpType.ZZPhase: symb_zzphase,
OpType.XXPhase3: symb_xxphase3,
OpType.PhasedX: symb_phasedx,
OpType.ESWAP: symb_eswap,
OpType.FSim: symb_fsim,
}
@classmethod
def register_func(cls, typ: OpType, f: SymGateFunc, replace: bool = False) -> None:
"""Register a callable for an optype.
:param typ: OpType to register
:type typ: OpType
:param f: Callable for generating symbolic matrix.
:type f: SymGateFunc
:param replace: Whether to replace existing entry, defaults to False
:type replace: bool, optional
"""
if typ not in cls._g_map or replace:
cls._g_map[typ] = f
@classmethod
def get_func(cls, typ: OpType) -> SymGateFunc:
"""Get registered callable."""
return cls._g_map[typ]
@classmethod
def is_registered(cls, typ: OpType) -> bool:
"""Check if type has a callable registered."""
return typ in cls._g_map
def _op_to_sympy_gate(op: Op, targets: List[int]) -> symgate.Gate:
# convert Op to sympy gate
if op.type in _FIXED_GATE_MAP:
return _FIXED_GATE_MAP[op.type](*targets)
if op.is_gate():
# check if symbolic definition is needed
float_params = all(isinstance(p, float) for p in op.params)
else:
raise ValueError(
f"Circuit can only contain unitary gates, operation {op} not valid."
)
# pytket matrix basis indexing is in opposite order to sympy
targets = targets[::-1]
if (not float_params) and SymGateRegister.is_registered(op.type):
u_mat = SymGateRegister.get_func(op.type)(op.params)
else:
try:
# use internal tket unitary definition
u_mat = ImmutableMatrix(op.get_unitary()) # type: ignore
except RuntimeError as e:
# to catch tket failure to get Op unitary
# most likely due to symbolic parameters.
raise ValueError(
f"{op.type} is not supported for symbolic conversion."
" Try registering your own symbolic matrix representation"
" with SymGateRegister.func."
) from e
gate = symgate.UGate(targets, u_mat) # type: ignore
return gate
def circuit_to_symbolic_gates(circ: Circuit) -> Mul:
"""Generate a multiplication expression of sympy gates from Circuit
:param circ: Input circuit
:type circ: Circuit
:raises ValueError: If circ does not match a unitary operation.
:return: Symbolic gate multiplication expression.
:rtype: Mul
"""
outmat = symgate.IdentityGate(0) # type: ignore
nqb = circ.n_qubits
qubit_map = {qb: nqb - 1 - i for i, qb in enumerate(circ.qubits)}
for com in circ:
op = com.op
if op.type == OpType.Barrier:
continue
args = com.args
try:
targs = [qubit_map[q] for q in args]
except KeyError as e:
raise ValueError(
f"Gates can only act on qubits. Operation {com} not valid."
) from e
gate = _op_to_sympy_gate(op, targs)
outmat = gate * outmat
for i in range(len(qubit_map)):
outmat = symgate.IdentityGate(i) * outmat # type: ignore
return outmat * sympy.exp((circ.phase * sympy.pi * I)) # type: ignore
def circuit_to_symbolic_unitary(circ: Circuit) -> ImmutableMatrix:
"""Generate a symbolic unitary from Circuit.
Unitary matches pytket default ILO BasisOrder.
:param circ: Input circuit
:type circ: Circuit
:return: Symbolic unitary.
:rtype: ImmutableMatrix
"""
gates = circuit_to_symbolic_gates(circ)
nqb = circ.n_qubits
try:
return cast(ImmutableMatrix, represent(gates, nqubits=circ.n_qubits)) # type: ignore
except NotImplementedError:
# sympy can't represent n>1 qubit unitaries very well
# so if it fails we will just calculate columns using the statevectors
# for all possible input basis states
matrix_dim = 1 << nqb
input_states = (Qubit(f"{i:0{nqb}b}") for i in range(matrix_dim)) # type: ignore
outmat = Matrix([]) # type: ignore
for col, input_state in enumerate(input_states):
outmat = outmat.col_insert(col, represent(qapply(gates * input_state))) # type: ignore
return ImmutableMatrix(outmat) # type: ignore
def circuit_apply_symbolic_qubit(circ: Circuit, input_qb: Expr) -> Qubit:
"""Apply circuit to an input state to calculate output symbolic state.
:param circ: Input Circuit.
:type circ: Circuit
:param input_qb: Sympy Qubit expression corresponding to a state.
:type input_qb: Expr
:return: Output state after circuit acts on input_qb.
:rtype: Qubit
"""
gates = circuit_to_symbolic_gates(circ)
return cast(Qubit, qapply(gates * input_qb)) # type: ignore
def circuit_apply_symbolic_statevector(
circ: Circuit, input_state: Optional[Union[np.ndarray, ImmutableMatrix]] = None
) -> ImmutableMatrix:
"""Apply circuit to an optional input statevector
to calculate output symbolic statevector.
If no input statevector given, the all zero state is assumed.
Statevector follows pytket default ILO BasisOrder.
:param circ: Input Circuit.
:type circ: Circuit
:param input_state: Input statevector as a column vector, defaults to None.
:type input_state: Optional[Union[np.ndarray, ImmutableMatrix]], optional
:return: Symbolic state after circ acts on input_state.
:rtype: ImmutableMatrix
"""
if input_state:
input_qb = matrix_to_qubit(input_state) # type: ignore
else:
input_qb = Qubit("0" * circ.n_qubits) # type: ignore
return cast(
ImmutableMatrix,
represent(circuit_apply_symbolic_qubit(circ, cast(Qubit, input_qb))), # type: ignore
)
|
40b0098a1a6e8209329a3671e600a7012df12581
|
a5a99f646e371b45974a6fb6ccc06b0a674818f2
|
/RecoVertex/BeamSpotProducer/python/BeamSpotFakeConditionsNominalCollision_cff.py
|
b3ed57bc3c70914739d6e076dbb9ad3463e854ed
|
[
"Apache-2.0"
] |
permissive
|
cms-sw/cmssw
|
4ecd2c1105d59c66d385551230542c6615b9ab58
|
19c178740257eb48367778593da55dcad08b7a4f
|
refs/heads/master
| 2023-08-23T21:57:42.491143
| 2023-08-22T20:22:40
| 2023-08-22T20:22:40
| 10,969,551
| 1,006
| 3,696
|
Apache-2.0
| 2023-09-14T19:14:28
| 2013-06-26T14:09:07
|
C++
|
UTF-8
|
Python
| false
| false
| 128
|
py
|
BeamSpotFakeConditionsNominalCollision_cff.py
|
import FWCore.ParameterSet.Config as cms
from RecoVertex.BeamSpotProducer.BeamSpotFakeConditionsNominalCollision_cfi import *
|
7b4155c512b38bc55f927f4fdca0e1bd7e0c3bc0
|
a8ca3225e24c8b093056ce6baa1db6ba3aea8f97
|
/tests/em/em1d/test_EM1D_FD_fwd.py
|
f7c79ebaa5e2c752a846205ffdd7eb643d760831
|
[
"MIT"
] |
permissive
|
simpeg/simpeg
|
3e8779392d7b26fe576a7a665205068989d8f4d8
|
ebde5856c318f7b4deb92d755b4fefe19012c48e
|
refs/heads/main
| 2023-09-03T18:49:03.545965
| 2023-08-27T15:45:50
| 2023-08-27T15:45:50
| 14,727,320
| 437
| 268
|
MIT
| 2023-09-10T18:16:22
| 2013-11-26T19:46:36
|
Python
|
UTF-8
|
Python
| false
| false
| 18,789
|
py
|
test_EM1D_FD_fwd.py
|
import unittest
import SimPEG.electromagnetics.frequency_domain as fdem
from SimPEG import maps
import numpy as np
from scipy.constants import mu_0
from geoana.em.fdem import (
MagneticDipoleHalfSpace,
omega,
vertical_magnetic_field_horizontal_loop as mag_field,
)
import empymod
class EM1D_FD_test_failures(unittest.TestCase):
def setUp(self):
nearthick = np.logspace(-1, 1, 5)
deepthick = np.logspace(1, 2, 10)
thicknesses = np.r_[nearthick, deepthick]
topo = np.r_[0.0, 0.0, 100.0]
self.topo = topo
self.thicknesses = thicknesses
self.nlayers = len(thicknesses) + 1
def test_height_failures(self):
frequencies = np.logspace(-1, 5, 6)
x_offset = 10.0
z_tx = [-10.0, 1.0, 1.0]
z_rx = [1.0, -10.0, -10.0]
use_source_receiver_offset = [False, False, True]
error_type = [ValueError, ValueError, ValueError]
test_type_string = [
"NO SOURCE BELOW SURFACE",
"NO RX BELOW SURFACE (STANDARD)",
"NO RX BELOW SURFACE (OFFSET)",
]
for ii in range(0, len(error_type)):
if use_source_receiver_offset[ii]:
rx_location = np.array([[x_offset, 0.0, z_rx[ii]]])
else:
rx_location = np.array([[x_offset, 0.0, z_rx[ii] + self.topo[2]]])
receiver_list = [
fdem.receivers.PointMagneticFieldSecondary(
rx_location,
orientation="z",
component="both",
use_source_receiver_offset=use_source_receiver_offset[ii],
)
]
src_location = np.array([[0.0, 0.0, z_tx[ii] + self.topo[2]]])
source_list = [
fdem.sources.MagDipole(receiver_list, f, src_location, orientation="z")
for f in frequencies
]
survey = fdem.Survey(source_list)
self.assertRaises(
error_type[ii],
fdem.Simulation1DLayered,
survey=survey,
thicknesses=self.thicknesses,
topo=self.topo,
)
print(test_type_string[ii] + " TEST PASSED")
def test_loop_orientation_failures(self):
src_location = np.array([0.0, 0.0, 1e-5])
frequencies = np.logspace(-1, 5, 6)
sigma_map = maps.ExpMap(nP=self.nlayers)
m_1D = np.log(np.ones(self.nlayers) * 0.01)
offsets = [10.0, 0.0]
rx_orientation = ["z", "z"]
src_orientation = ["z", "x"]
test_type_string = ["NO TX-RX OFFSET", "ONLY HORIZONTAL LOOP"]
error_type = [ValueError, ValueError]
for ii in range(0, len(offsets)):
rx_location = np.array([[offsets[ii], 0.0, 1e-5]])
receiver_list = [
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation=rx_orientation[ii], component="both"
)
]
source_list = [
fdem.sources.CircularLoop(
receiver_list,
f,
src_location,
radius=5.0,
orientation=src_orientation[ii],
)
for f in frequencies
]
survey = fdem.Survey(source_list)
sim = fdem.Simulation1DLayered(
survey=survey, thicknesses=self.thicknesses, sigmaMap=sigma_map
)
self.assertRaises(error_type[ii], sim.dpred, m_1D)
print(test_type_string[ii] + " TEST PASSED")
class EM1D_FD_FwdProblemTests(unittest.TestCase):
def setUp(self):
nearthick = np.logspace(-1, 1, 5)
deepthick = np.logspace(1, 2, 10)
thicknesses = np.r_[nearthick, deepthick]
topo = np.r_[0.0, 0.0, 100.0]
offset = 10.0
src_location = np.array([[0.0, 0.0, 100.0 + 1e-5]])
rx_location = np.array([[offset, 0.0, 0.0]])
frequencies = np.logspace(-1, 5, 61)
# Receiver list
receiver_list = []
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location,
orientation="z",
component="real",
use_source_receiver_offset=True,
)
)
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location,
orientation="z",
component="imag",
use_source_receiver_offset=True,
)
)
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location,
orientation="x",
component="real",
use_source_receiver_offset=True,
)
)
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location,
orientation="x",
component="imag",
use_source_receiver_offset=True,
)
)
source_list = []
for frequency in frequencies:
src = fdem.sources.MagDipole(
receiver_list, frequency, src_location, orientation="z"
)
source_list.append(src)
# Survey
# survey = em1d.survey.EM1DSurveyFD(source_list)
survey = fdem.Survey(source_list)
sigma = 1.0
chi = 0.0
tau = 1e-3
eta = 2e-1
c = 1.0
self.topo = topo
self.survey = survey
self.sigma = sigma
self.tau = tau
self.eta = eta
self.c = c
self.chi = chi
self.offset = offset
self.frequencies = frequencies
self.thicknesses = thicknesses
self.nlayers = len(thicknesses) + 1
def test_basic_properties(self):
sim = fdem.Simulation1DLayered(
survey=self.survey, thicknesses=self.thicknesses, topo=self.topo
)
# Number of filters
self.assertEqual(sim.n_filter, sim._fhtfilt.base.size)
# Layer depths
depths = np.r_[0.0, -np.cumsum(self.thicknesses)]
self.assertTrue(np.all(depths == sim.depth))
def test_EM1DFDfwd_VMD_Halfspace(self):
sigma_map = maps.ExpMap(nP=1)
sim = fdem.Simulation1DLayered(
survey=self.survey, sigmaMap=sigma_map, topo=self.topo
)
m_1D = np.array([np.log(self.sigma)])
H = sim.dpred(m_1D)
dip = MagneticDipoleHalfSpace(
location=np.r_[0.0, 0.0, 0.0],
orientation="z",
frequency=self.frequencies,
sigma=np.asarray(self.sigma),
quasistatic=True,
)
H_analytic = np.squeeze(dip.magnetic_field(np.array([[self.offset, 0.0]])))
Hx = H_analytic[:, 0]
Hz = H_analytic[:, 2]
H_analytic = np.c_[Hz.real, Hz.imag, Hx.real, Hx.imag].reshape(-1)
err = np.linalg.norm(H - H_analytic) / np.linalg.norm(H_analytic)
self.assertLess(err, 1e-5)
def test_EM1DFDfwd_VMD_RealCond(self):
sigma_map = maps.ExpMap(nP=self.nlayers)
sim = fdem.Simulation1DLayered(
survey=self.survey,
thicknesses=self.thicknesses,
sigmaMap=sigma_map,
topo=self.topo,
)
m_1D = np.log(np.ones(self.nlayers) * self.sigma)
H = sim.dpred(m_1D)
dip = MagneticDipoleHalfSpace(
location=np.r_[0.0, 0.0, 0.0],
orientation="z",
frequency=self.frequencies,
sigma=np.asarray(self.sigma),
quasistatic=True,
)
H_analytic = np.squeeze(dip.magnetic_field(np.array([[self.offset, 0.0]])))
Hx = H_analytic[:, 0]
Hz = H_analytic[:, 2]
H_analytic = np.c_[Hz.real, Hz.imag, Hx.real, Hx.imag].reshape(-1)
err = np.linalg.norm(H - H_analytic) / np.linalg.norm(H_analytic)
self.assertLess(err, 1e-5)
def test_EM1DFDfwd_VMD_ComplexCond(self):
sigma_map = maps.IdentityMap(nP=self.nlayers)
mu = mu_0 * np.ones(self.nlayers)
tau = self.tau * np.ones(self.nlayers)
c = self.c * np.ones(self.nlayers)
eta = self.eta * np.ones(self.nlayers)
sim = fdem.Simulation1DLayered(
survey=self.survey,
thicknesses=self.thicknesses,
topo=self.topo,
sigmaMap=sigma_map,
eta=eta,
tau=tau,
c=c,
mu=mu,
)
m_1D = self.sigma * np.ones(self.nlayers)
H = sim.dpred(m_1D)
sigmas = sim.compute_complex_sigma(self.frequencies)[0, :]
H_analytic = []
for sigma, frequency in zip(sigmas, self.frequencies):
sig = np.real(sigma)
eps = np.imag(sigma) / omega(frequency)
dip = MagneticDipoleHalfSpace(
location=np.r_[0.0, 0.0, 0.0],
orientation="z",
frequency=[frequency],
sigma=sig,
epsilon=eps,
quasistatic=False,
)
hv = np.squeeze(dip.magnetic_field(np.array([[self.offset, 0.0]])))
hx = hv[0]
hz = hv[2]
H_analytic.append([hz.real, hz.imag, hx.real, hx.imag])
H_analytic = np.hstack(H_analytic)
err = np.linalg.norm(H - H_analytic) / np.linalg.norm(H_analytic)
self.assertTrue(err < 1e-2)
def test_EM1DFDfwd_HMD_RealCond(self):
src_location = np.array([0.0, 0.0, 100.0 + 1e-5])
rx_location = np.array([self.offset, 0.0, 100.0 + 1e-5])
frequencies = np.logspace(-1, 5, 61)
# Receiver list
receiver_list = []
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation="z", component="real"
)
)
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation="z", component="imag"
)
)
source_list = []
for frequency in frequencies:
src = fdem.sources.MagDipole(
receiver_list, frequency, src_location, orientation="x"
)
source_list.append(src)
survey = fdem.Survey(source_list)
sigma_map = maps.ExpMap(nP=self.nlayers)
sim = fdem.Simulation1DLayered(
survey=survey,
thicknesses=self.thicknesses,
sigmaMap=sigma_map,
topo=self.topo,
)
m_1D = np.log(np.ones(self.nlayers) * self.sigma)
Hz = sim.dpred(m_1D)
dip = MagneticDipoleHalfSpace(
location=np.r_[0.0, 0.0, 0.0],
orientation="x",
frequency=self.frequencies,
sigma=np.asarray(self.sigma),
quasistatic=True,
)
H_analytic = np.squeeze(dip.magnetic_field(np.array([[self.offset, 0.0]])))[
:, 2
]
H_analytic = np.c_[H_analytic.real, H_analytic.imag].reshape(-1)
err = np.linalg.norm(Hz - H_analytic) / np.linalg.norm(H_analytic)
self.assertLess(err, 1e-5)
def test_EM1DFDfwd_CircularLoop_RealCond(self):
src_location = np.array([0.0, 0.0, 100.0 + 1e-5])
rx_location = np.array([0.0, 0.0, 100.0 + 1e-5])
frequencies = np.logspace(-1, 5, 61)
# Receiver list
receiver_list = []
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation="z", component="real"
)
)
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation="z", component="imag"
)
)
source_list = []
for frequency in frequencies:
src = fdem.sources.CircularLoop(
receiver_list, frequency, src_location, radius=5.0
)
source_list.append(src)
survey = fdem.Survey(source_list)
sigma_map = maps.ExpMap(nP=self.nlayers)
sim = fdem.Simulation1DLayered(
survey=survey,
thicknesses=self.thicknesses,
sigmaMap=sigma_map,
topo=self.topo,
)
m_1D = np.log(np.ones(self.nlayers) * self.sigma)
Hz = sim.dpred(m_1D)
hz = mag_field(self.frequencies, sigma=self.sigma, radius=5.0)
H_analytic = np.c_[hz.real, hz.imag].reshape(-1)
err = np.linalg.norm(Hz - H_analytic) / np.linalg.norm(H_analytic)
self.assertLess(err, 1e-5)
def test_EM1DFDfwd_CircularLoop_ComplexCond(self):
src_location = np.array([0.0, 0.0, 100.0 + 1e-5])
rx_location = np.array([0.0, 0.0, 100.0 + 1e-5])
frequencies = np.logspace(-1, 5, 61)
# Receiver list
receiver_list = []
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation="z", component="real"
)
)
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
rx_location, orientation="z", component="imag"
)
)
source_list = []
for frequency in frequencies:
src = fdem.sources.CircularLoop(
receiver_list, frequency, src_location, radius=5.0
)
source_list.append(src)
survey = fdem.Survey(source_list)
sigma_map = maps.IdentityMap(nP=self.nlayers)
mu = mu_0 * np.ones(self.nlayers)
tau = self.tau * np.ones(self.nlayers)
c = self.c * np.ones(self.nlayers)
eta = self.eta * np.ones(self.nlayers)
sim = fdem.Simulation1DLayered(
survey=survey,
thicknesses=self.thicknesses,
topo=self.topo,
sigmaMap=sigma_map,
eta=eta,
tau=tau,
c=c,
mu=mu,
)
m_1D = self.sigma * np.ones(self.nlayers)
Hz = sim.dpred(m_1D)
sigma_colecole = sim.compute_complex_sigma(self.frequencies)[0, :]
hz = mag_field(self.frequencies, sigma=sigma_colecole, radius=5.0)
H_analytic = np.c_[hz.real, hz.imag].reshape(-1)
err = np.linalg.norm(Hz - H_analytic) / np.linalg.norm(H_analytic)
self.assertLess(err, 1e-5)
class EM1D_FD_LineCurrentTest(unittest.TestCase):
def setUp(self):
x_path = np.array([-2, -2, 2, 2, -2])
y_path = np.array([-1, 1, 1, -1, -1])
frequencies = np.logspace(0, 4)
wire_paths = np.c_[x_path, y_path, np.ones(5) * 0.5]
source_list = []
receiver_list = []
receiver_location = np.array([9.28, 0.0, 0.45])
receiver_orientation = "z"
receiver_list.append(
fdem.receivers.PointMagneticFieldSecondary(
receiver_location,
orientation=receiver_orientation,
data_type="field",
component="both",
)
)
for freq in frequencies:
source = fdem.sources.LineCurrent(receiver_list, freq, wire_paths)
source_list.append(source)
# Survey
survey = fdem.Survey(source_list)
background_conductivity = 1e-1
layer_conductivity = 1e0
sigma = np.ones(3) * background_conductivity
sigma[1] = layer_conductivity
thicknesses = np.array([20.0, 40.0])
self.frequencies = frequencies
self.survey = survey
self.sigma = sigma
self.thicknesses = thicknesses
def test_with_empymod(self):
sim = fdem.Simulation1DLayered(
survey=self.survey,
sigmaMap=maps.IdentityMap(nP=3),
thicknesses=self.thicknesses,
)
H = sim.dpred(self.sigma)
def solution(res):
EM_left = empymod.model.bipole(
src=[-2, -2, -1, 1, -0.5, -0.5], # El. bipole source; half of one side.
rec=[9.28, 0, -0.45, 0, 90], # Receiver at the origin, vertical.
depth=np.r_[
0, np.cumsum(sim.thicknesses)
], # Depth-model, adding air-interface.
res=res, # Provided resistivity model, adding air.
freqtime=self.frequencies, # Required frequencies.
mrec=True, # It is an el. source, but a magn. rec.
strength=1, # To account for 1 side of square loop.
srcpts=3, # Approx. the finite dip. with 3 points.
htarg={"dlf": "key_101_2009"}, # Short filter, so fast.
verb=0,
)
EM_right = empymod.model.bipole(
src=[2, 2, 1, -1, -0.5, -0.5], # El. bipole source; half of one side.
rec=[9.28, 0, -0.45, 0, 90], # Receiver at the origin, vertical.
depth=np.r_[
0, np.cumsum(sim.thicknesses)
], # Depth-model, adding air-interface.
res=res, # Provided resistivity model, adding air.
freqtime=self.frequencies, # Required frequencies.
mrec=True, # It is an el. source, but a magn. rec.
strength=1, # To account for 1 side of square loop.
srcpts=3, # Approx. the finite dip. with 3 points.
htarg={"dlf": "key_101_2009"}, # Short filter, so fast.
verb=0,
)
EM_top = empymod.model.bipole(
src=[-2, 2, 1, 1, -0.5, -0.5], # El. bipole source; half of one side.
rec=[9.28, 0, -0.45, 0, 90], # Receiver at the origin, vertical.
depth=np.r_[
0, np.cumsum(sim.thicknesses)
], # Depth-model, adding air-interface.
res=res, # Provided resistivity model, adding air.
freqtime=self.frequencies, # Required frequencies.
mrec=True, # It is an el. source, but a magn. rec.
strength=2, # To account for 2 sides of square loop.
srcpts=3, # Approx. the finite dip. with 3 points.
htarg={"dlf": "key_101_2009"}, # Short filter, so fast.
verb=0,
)
EM = EM_left + EM_right + EM_top
return EM
res = np.r_[2e14, 1.0 / sim.sigma]
resBG = np.ones(4) * 2e14
EM = solution(res) - solution(resBG)
H_analytic = np.c_[EM.real, EM.imag].reshape(-1)
err = np.linalg.norm(H - H_analytic) / np.linalg.norm(H_analytic)
self.assertLess(err, 1e-4)
if __name__ == "__main__":
unittest.main()
|
2517fd8d1e7444f9cdcc7e9b287da2215112e58e
|
aeef2494b283012ed619870c4275e7d015f4017a
|
/sdk/python/pulumi_gcp/cloudidentity/get_groups.py
|
a5c75e8338c166749bb5201610c92a607ab95585
|
[
"MPL-2.0",
"BSD-3-Clause",
"Apache-2.0"
] |
permissive
|
pulumi/pulumi-gcp
|
d4fd3f80c3df5290edaf33eb5eafe34e6699d0ff
|
7deea0a50a4ee5ab7bd722a83eca01707e298f85
|
refs/heads/master
| 2023-08-31T07:12:45.921522
| 2023-08-31T06:16:27
| 2023-08-31T06:16:27
| 97,485,806
| 160
| 63
|
Apache-2.0
| 2023-09-14T19:49:36
| 2017-07-17T14:28:37
|
Java
|
UTF-8
|
Python
| false
| false
| 3,889
|
py
|
get_groups.py
|
# coding=utf-8
# *** WARNING: this file was generated by the Pulumi Terraform Bridge (tfgen) Tool. ***
# *** Do not edit by hand unless you're certain you know what you are doing! ***
import copy
import warnings
import pulumi
import pulumi.runtime
from typing import Any, Mapping, Optional, Sequence, Union, overload
from .. import _utilities
from . import outputs
__all__ = [
'GetGroupsResult',
'AwaitableGetGroupsResult',
'get_groups',
'get_groups_output',
]
@pulumi.output_type
class GetGroupsResult:
"""
A collection of values returned by getGroups.
"""
def __init__(__self__, groups=None, id=None, parent=None):
if groups and not isinstance(groups, list):
raise TypeError("Expected argument 'groups' to be a list")
pulumi.set(__self__, "groups", groups)
if id and not isinstance(id, str):
raise TypeError("Expected argument 'id' to be a str")
pulumi.set(__self__, "id", id)
if parent and not isinstance(parent, str):
raise TypeError("Expected argument 'parent' to be a str")
pulumi.set(__self__, "parent", parent)
@property
@pulumi.getter
def groups(self) -> Sequence['outputs.GetGroupsGroupResult']:
"""
The list of groups under the provided customer or namespace. Structure is documented below.
"""
return pulumi.get(self, "groups")
@property
@pulumi.getter
def id(self) -> str:
"""
The provider-assigned unique ID for this managed resource.
"""
return pulumi.get(self, "id")
@property
@pulumi.getter
def parent(self) -> str:
return pulumi.get(self, "parent")
class AwaitableGetGroupsResult(GetGroupsResult):
# pylint: disable=using-constant-test
def __await__(self):
if False:
yield self
return GetGroupsResult(
groups=self.groups,
id=self.id,
parent=self.parent)
def get_groups(parent: Optional[str] = None,
opts: Optional[pulumi.InvokeOptions] = None) -> AwaitableGetGroupsResult:
"""
Use this data source to get list of the Cloud Identity Groups under a customer or namespace.
https://cloud.google.com/identity/docs/concepts/overview#groups
## Example Usage
```python
import pulumi
import pulumi_gcp as gcp
groups = gcp.cloudidentity.get_groups(parent="customers/A01b123xz")
```
:param str parent: The parent resource under which to list all Groups. Must be of the form identitysources/{identity_source_id} for external- identity-mapped groups or customers/{customer_id} for Google Groups.
"""
__args__ = dict()
__args__['parent'] = parent
opts = pulumi.InvokeOptions.merge(_utilities.get_invoke_opts_defaults(), opts)
__ret__ = pulumi.runtime.invoke('gcp:cloudidentity/getGroups:getGroups', __args__, opts=opts, typ=GetGroupsResult).value
return AwaitableGetGroupsResult(
groups=pulumi.get(__ret__, 'groups'),
id=pulumi.get(__ret__, 'id'),
parent=pulumi.get(__ret__, 'parent'))
@_utilities.lift_output_func(get_groups)
def get_groups_output(parent: Optional[pulumi.Input[str]] = None,
opts: Optional[pulumi.InvokeOptions] = None) -> pulumi.Output[GetGroupsResult]:
"""
Use this data source to get list of the Cloud Identity Groups under a customer or namespace.
https://cloud.google.com/identity/docs/concepts/overview#groups
## Example Usage
```python
import pulumi
import pulumi_gcp as gcp
groups = gcp.cloudidentity.get_groups(parent="customers/A01b123xz")
```
:param str parent: The parent resource under which to list all Groups. Must be of the form identitysources/{identity_source_id} for external- identity-mapped groups or customers/{customer_id} for Google Groups.
"""
...
|
6a2e51658082f5eb9fe1890ad982e70c68ee87d1
|
0869d7edac80e8aebe951682a2cc311a083eade3
|
/Python/tdw/FBOutput/ObiSolverData.py
|
7ca95f832b5988657c8760460c89c03c3c36c54e
|
[
"BSD-2-Clause"
] |
permissive
|
threedworld-mit/tdw
|
7d5b4453832647733ff91ad7a7ce7ec2320454c1
|
9df96fba455b327bb360d8dd5886d8754046c690
|
refs/heads/master
| 2023-09-01T11:45:28.132298
| 2023-08-31T16:13:30
| 2023-08-31T16:13:30
| 245,492,977
| 427
| 75
|
BSD-2-Clause
| 2023-09-14T17:36:12
| 2020-03-06T18:42:09
|
Python
|
UTF-8
|
Python
| false
| false
| 3,115
|
py
|
ObiSolverData.py
|
# automatically generated by the FlatBuffers compiler, do not modify
# namespace: FBOutput
import tdw.flatbuffers
class ObiSolverData(object):
__slots__ = ['_tab']
@classmethod
def GetRootAsObiSolverData(cls, buf, offset):
n = tdw.flatbuffers.encode.Get(tdw.flatbuffers.packer.uoffset, buf, offset)
x = ObiSolverData()
x.Init(buf, n + offset)
return x
# ObiSolverData
def Init(self, buf, pos):
self._tab = tdw.flatbuffers.table.Table(buf, pos)
# ObiSolverData
def Id(self):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(4))
if o != 0:
return self._tab.Get(tdw.flatbuffers.number_types.Int32Flags, o + self._tab.Pos)
return 0
# ObiSolverData
def Positions(self, j):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(6))
if o != 0:
a = self._tab.Vector(o)
return self._tab.Get(tdw.flatbuffers.number_types.Float32Flags, a + tdw.flatbuffers.number_types.UOffsetTFlags.py_type(j * 4))
return 0
# ObiSolverData
def PositionsAsNumpy(self):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(6))
if o != 0:
return self._tab.GetVectorAsNumpy(tdw.flatbuffers.number_types.Float32Flags, o)
return 0
# ObiSolverData
def PositionsLength(self):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(6))
if o != 0:
return self._tab.VectorLen(o)
return 0
# ObiSolverData
def Velocities(self, j):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(8))
if o != 0:
a = self._tab.Vector(o)
return self._tab.Get(tdw.flatbuffers.number_types.Float32Flags, a + tdw.flatbuffers.number_types.UOffsetTFlags.py_type(j * 4))
return 0
# ObiSolverData
def VelocitiesAsNumpy(self):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(8))
if o != 0:
return self._tab.GetVectorAsNumpy(tdw.flatbuffers.number_types.Float32Flags, o)
return 0
# ObiSolverData
def VelocitiesLength(self):
o = tdw.flatbuffers.number_types.UOffsetTFlags.py_type(self._tab.Offset(8))
if o != 0:
return self._tab.VectorLen(o)
return 0
def ObiSolverDataStart(builder): builder.StartObject(3)
def ObiSolverDataAddId(builder, id): builder.PrependInt32Slot(0, id, 0)
def ObiSolverDataAddPositions(builder, positions): builder.PrependUOffsetTRelativeSlot(1, tdw.flatbuffers.number_types.UOffsetTFlags.py_type(positions), 0)
def ObiSolverDataStartPositionsVector(builder, numElems): return builder.StartVector(4, numElems, 4)
def ObiSolverDataAddVelocities(builder, velocities): builder.PrependUOffsetTRelativeSlot(2, tdw.flatbuffers.number_types.UOffsetTFlags.py_type(velocities), 0)
def ObiSolverDataStartVelocitiesVector(builder, numElems): return builder.StartVector(4, numElems, 4)
def ObiSolverDataEnd(builder): return builder.EndObject()
|
c8118117bff6cd1517240557b329b71d4c253dd4
|
e07191ad899201010690588ba84536e431f55f9c
|
/astroturf/app.py
|
33190e3ba58387e0a2c681e0da8c11f1dd181d8d
|
[
"MIT"
] |
permissive
|
frandallfarmer/neohabitat
|
c15a202020d7947d302148b37d50e2995c3f3342
|
eb610c5b9cf69bedc868a533e7f1dccb9b57cfef
|
refs/heads/master
| 2023-08-17T05:13:55.622138
| 2023-08-11T21:03:52
| 2023-08-11T21:03:52
| 78,450,437
| 226
| 101
|
MIT
| 2023-08-23T17:31:07
| 2017-01-09T17:08:14
|
Java
|
UTF-8
|
Python
| false
| false
| 1,325
|
py
|
app.py
|
from __future__ import print_function
import argparse
import os
import sys
from glob import glob
from astroturf import Astroturf
ARG_PARSER = argparse.ArgumentParser(
description='Renders templated regions based upon Griddle input files',
)
ARG_PARSER.add_argument(
'--input_dir',
dest='input_dir',
default='.',
help='where the base Griddle and JSON template region files can be found',
)
ARG_PARSER.add_argument(
'--output_dir',
dest='output_dir',
default='astroturf',
help='where to output Neohabitat JSON region files',
)
def convert_files_in_dir(input_dir, output_dir):
griddle_base_files = glob(os.path.join(input_dir, '*.i'))
if not griddle_base_files:
print(' ! No .i file found in input dir, bailing...')
sys.exit(-1)
griddle_base_file = griddle_base_files[0]
region_proto_files = glob(os.path.join(input_dir, '*.json'))
if not region_proto_files:
print(' ! No .json files found in input dir, bailing...')
sys.exit(-2)
astroturf = Astroturf(input_dir, output_dir, griddle_base_file, region_proto_files)
success = astroturf.write_output_files()
if not success:
print(' ! Failed to convert all regions.')
sys.exit(-3)
if __name__ in '__main__':
args = ARG_PARSER.parse_args()
convert_files_in_dir(args.input_dir, args.output_dir)
|
ba84f5895ba3a755d9adb6fed8885b0f7e817ecf
|
fa1ad2e2ac7e376fc7cb3b3a6e1bb88eed3e80be
|
/dts/airbyte/airbyte-integrations/connectors/source-tiktok-marketing/source_tiktok_marketing/spec.py
|
f703069d50f3a57b27b3bf764f37bd978ddafaff
|
[
"Apache-2.0",
"BSD-3-Clause",
"MIT",
"Elastic-2.0"
] |
permissive
|
alldatacenter/alldata
|
7bc7713c9f1d56ad6b8e59ea03206d1073b7e047
|
8d5f9a2d49ab8f9e85ccf058cb02c2fda287afc6
|
refs/heads/master
| 2023-08-05T07:32:25.442740
| 2023-08-03T13:17:24
| 2023-08-03T13:17:24
| 213,321,771
| 774
| 250
|
Apache-2.0
| 2023-09-06T17:35:32
| 2019-10-07T07:36:18
| null |
UTF-8
|
Python
| false
| false
| 4,469
|
py
|
spec.py
|
#
# Copyright (c) 2023 Airbyte, Inc., all rights reserved.
#
import json
import re
from typing import Union
from jsonschema import RefResolver
from pydantic import BaseModel, Field
from .streams import DEFAULT_START_DATE, ReportGranularity
class OauthCredSpec(BaseModel):
class Config:
title = "OAuth2.0"
auth_type: str = Field(default="oauth2.0", const=True, order=0)
app_id: str = Field(title="App ID", description="The Developer Application App ID.", airbyte_secret=True)
secret: str = Field(title="Secret", description="The Developer Application Secret.", airbyte_secret=True)
access_token: str = Field(title="Access Token", description="Long-term Authorized Access Token.", airbyte_secret=True)
class SandboxEnvSpec(BaseModel):
class Config:
title = "Sandbox Access Token"
auth_type: str = Field(default="sandbox_access_token", const=True, order=0)
# it is string because UI has the bug https://github.com/airbytehq/airbyte/issues/6875
advertiser_id: str = Field(
title="Advertiser ID", description="The Advertiser ID which generated for the developer's Sandbox application."
)
access_token: str = Field(title="Access Token", description="The long-term authorized access token.", airbyte_secret=True)
class SourceTiktokMarketingSpec(BaseModel):
class Config:
title = "TikTok Marketing Source Spec"
credentials: Union[OauthCredSpec, SandboxEnvSpec] = Field(
title="Authentication Method", description="Authentication method", order=0, default={}, type="object"
)
start_date: str = Field(
title="Replication Start Date",
default=DEFAULT_START_DATE,
pattern="^[0-9]{4}-[0-9]{2}-[0-9]{2}$",
description="The Start Date in format: YYYY-MM-DD. Any data before this date will not be replicated. "
"If this parameter is not set, all data will be replicated.",
order=1,
)
end_date: str = Field(
None,
title="End Date",
pattern="^[0-9]{4}-[0-9]{2}-[0-9]{2}$",
description=(
"The date until which you'd like to replicate data for all incremental streams, in the format YYYY-MM-DD. "
"All data generated between start_date and this date will be replicated. "
"Not setting this option will result in always syncing the data till the current date."
),
order=2,
)
report_granularity: str = Field(
None,
title="Report Aggregation Granularity",
description="The granularity used for aggregating performance data in reports. See <a "
'href="https://docs.airbyte.com/integrations/sources/tiktok-marketing/#report-aggregation">the docs</a>.',
enum=[g.value for g in ReportGranularity],
order=3,
airbyte_hidden=True,
)
@classmethod
def change_format_to_oneOf(cls, schema: dict) -> dict:
new_schema = {}
for key, value in schema.items():
if isinstance(value, dict):
value = cls.change_format_to_oneOf(value)
if key == "anyOf":
new_schema["oneOf"] = value
else:
new_schema[key] = value
return new_schema
@staticmethod
def resolve_refs(schema: dict) -> dict:
json_schema_ref_resolver = RefResolver.from_schema(schema)
str_schema = json.dumps(schema)
for ref_block in re.findall(r'{"\$ref": "#\/definitions\/.+?(?="})"}', str_schema):
ref = json.loads(ref_block)["$ref"]
str_schema = str_schema.replace(ref_block, json.dumps(json_schema_ref_resolver.resolve(ref)[1]))
pyschema = json.loads(str_schema)
del pyschema["definitions"]
return pyschema
@classmethod
def schema(cls) -> dict:
"""we're overriding the schema classmethod to enable some post-processing"""
schema = super().schema()
schema = cls.change_format_to_oneOf(schema)
return cls.resolve_refs(schema)
class CompleteOauthOutputSpecification(BaseModel):
access_token: str = Field(path_in_connector_config=["credentials", "access_token"])
class CompleteOauthServerInputSpecification(BaseModel):
app_id: str = Field()
secret: str = Field()
class CompleteOauthServerOutputSpecification(BaseModel):
app_id: str = Field(path_in_connector_config=["credentials", "app_id"])
secret: str = Field(path_in_connector_config=["credentials", "secret"])
|
cb42f40ff5a570411b36c214576cc16073bc3c2f
|
786f9ae62cb62d2b8f193350d8beb695c47d2e98
|
/tests/support/test_cache.py
|
8287c32b5a93b9472f535acd2611898eab3aea1d
|
[
"MIT"
] |
permissive
|
postlund/pyatv
|
a4213957d4d9b557c16310450bfd444cc715e17c
|
05ca46d2a8bbc8e725ad63794d14b2d1fb9913fa
|
refs/heads/master
| 2023-09-01T20:11:48.374857
| 2023-08-29T04:23:22
| 2023-08-29T11:13:17
| 80,614,028
| 749
| 120
|
MIT
| 2023-09-14T04:54:01
| 2017-02-01T11:30:30
|
Python
|
UTF-8
|
Python
| false
| false
| 1,711
|
py
|
test_cache.py
|
"""Unit tests for cache."""
import pytest
from pyatv.support.cache import Cache
ID1 = "id1"
ID2 = "id2"
ID3 = "id3"
DATA1 = 123
DATA2 = 456
DATA3 = 789
@pytest.fixture
def cache():
yield Cache(limit=2)
def test_cache_is_empty(cache):
assert cache.empty()
def test_put_get_item(cache):
cache.put(ID1, DATA1)
assert cache.get(ID1) == DATA1
def test_put_get_multiple(cache):
cache.put(ID1, DATA1)
cache.put(ID2, DATA2)
assert cache.get(ID1) == DATA1
assert cache.get(ID2) == DATA2
def test_cache_not_empty(cache):
cache.put(ID1, DATA1)
assert not cache.empty()
def test_cache_has_item(cache):
cache.put(ID1, DATA1)
assert ID1 in cache
assert ID2 not in cache
def test_cache_size(cache):
assert len(cache) == 0
cache.put(ID1, DATA1)
assert len(cache) == 1
def test_put_same_identifier_replaces_data(cache):
cache.put(ID1, DATA1)
cache.put(ID1, DATA2)
assert cache.get(ID1) == DATA2
assert len(cache) == 1
def test_put_removes_oldest(cache):
cache.put(ID1, DATA1)
cache.put(ID2, DATA2)
cache.put(ID3, DATA3)
assert len(cache) == 2
assert ID1 not in cache
assert ID2 in cache
assert ID3 in cache
def test_get_makes_data_newer(cache):
cache.put(ID1, DATA1)
cache.put(ID2, DATA2)
cache.get(ID1)
cache.put(ID3, DATA3)
assert len(cache) == 2
assert ID1 in cache
assert ID2 not in cache
assert ID3 in cache
def test_get_latest_identifier(cache):
assert cache.latest() is None
cache.put(ID1, DATA1)
assert cache.latest() == ID1
cache.put(ID2, DATA2)
assert cache.latest() == ID2
cache.get(ID1)
assert cache.latest() == ID1
|
582e6b15a01e82d6a8e32b1c722e815c978f0677
|
27e7e43b104fcb4ba7ede5c2cbe28059717e3cef
|
/snowfakery/tools/mkdocs.py
|
fd7edea28b6f4f6d6e397f445d1c61d8679417b8
|
[] |
permissive
|
SFDO-Tooling/Snowfakery
|
328365863a22637c02788f2fe1e019498c0394b1
|
ef72d8a9c3bd4f0ce841d4e9a8a9009d14f69dba
|
refs/heads/main
| 2023-08-19T03:08:23.765099
| 2023-06-09T10:19:13
| 2023-06-09T10:19:13
| 247,177,199
| 122
| 28
|
BSD-3-Clause
| 2023-08-03T16:33:32
| 2020-03-13T23:15:12
|
Python
|
UTF-8
|
Python
| false
| false
| 1,103
|
py
|
mkdocs.py
|
import sys
from pathlib import Path
from importlib import import_module
from unittest.mock import patch
from mkdocs.plugins import BasePlugin
import mkdocs
class Plugin(BasePlugin):
config_scheme = (
("build_locales", mkdocs.config.config_options.Type(bool, default=False)),
)
def on_config(self, config):
"""Look for and load main_mkdocs_plugin in tools/faker_docs_utils/mkdocs_plugins.py
This bootstrap plugin is needed because that other one is never "installed"
It is just present in the repo. So it can't have an official entry point
in setup.py.
"""
docs_dir = config["docs_dir"]
plugins_dir = Path(docs_dir).parent / "tools/faker_docs_utils/mkdocs_plugins"
new_sys_path = [*sys.path, str(plugins_dir)]
with patch.object(sys, "path", new_sys_path):
module = import_module("main_mkdocs_plugin")
main_plugin = module.Plugin()
config["plugins"]["main_mkdocs_plugin"] = main_plugin
main_plugin.config = self.config
main_plugin.on_config(config)
|
8d942dd98ee385ce09cb54be7e0c2ada59ef6537
|
568fa58296378fa129ab3349adf010daa44ed45b
|
/tests/common/test_run/ascend/kldiv_loss_run.py
|
c375907ca0f5f373eac652689bc0c99c5e0099a6
|
[
"Apache-2.0",
"BSD-3-Clause",
"NCSA",
"X11-distribute-modifications-variant",
"Zlib",
"MIT",
"LicenseRef-scancode-unknown-license-reference",
"Unlicense",
"LLVM-exception",
"BSD-2-Clause"
] |
permissive
|
mindspore-ai/akg
|
37f471badc66de6a831f1f45ad84344f34d23ef2
|
99f33858d6972741748cbfc9ab0bf9600428fef7
|
refs/heads/master
| 2023-07-25T23:03:17.672665
| 2023-07-11T07:33:57
| 2023-07-11T07:33:57
| 274,077,856
| 319
| 36
|
Apache-2.0
| 2021-12-30T13:43:08
| 2020-06-22T08:09:05
|
Python
|
UTF-8
|
Python
| false
| false
| 3,503
|
py
|
kldiv_loss_run.py
|
# Copyright 2019-2021 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
from akg.utils import kernel_exec as utils
from akg.utils.kernel_exec import product_is_mini
from tests.common.tensorio import compare_tensor
import numpy as np
from tests.common.test_op.ascend import kldiv_loss
from tests.common.gen_random import random_gaussian
from akg.utils.dsl_create import get_reduce_out_shape
def kldiv_loss_run(shape, dtype, reduction='none', kernel_name="kldiv_loss", attrs=None):
input_shape = [shape, shape]
input_dtype = [dtype, dtype]
op_attrs = [reduction]
if not product_is_mini():
attrs['enable_multicore'] = True
if 'tuning' in attrs.keys():
t = attrs.get("tuning", False)
kernel_name = attrs.get("kernel_name", False)
mod = utils.op_build_test(kldiv_loss.kldiv_loss, input_shape, input_dtype, op_attrs, kernel_name=kernel_name, attrs=attrs, tuning=t)
if t:
expect, output, prediction, target = gen_data(dtype, reduction, shape)
return mod, expect, (prediction, target, output)
else:
return mod
else:
mod = utils.op_build_test(kldiv_loss.kldiv_loss, input_shape, input_dtype, op_attrs, kernel_name=kernel_name, attrs=attrs)
expect, output, prediction, target = gen_data(dtype, reduction, shape)
output = utils.mod_launch(mod, (prediction, target, output), expect=expect)
return (prediction, target), output, expect, compare_tensor(output, expect, rtol=0.005, atol=0.005)
def gen_data(dtype, reduction, shape):
# support_list = {"float16": np.float16, "float32": np.float32}
target = random_gaussian(shape, miu=0, sigma=1).astype(dtype)
target = np.abs(target)
prediction = random_gaussian(shape, miu=0, sigma=1).astype(dtype)
prediction = np.abs(prediction)
# off_set = np.full(prediction.shape, 0.05, dtype)
off_set = np.full(prediction.shape, 2, dtype)
prediction = np.add(prediction, off_set)
target = np.add(target, off_set)
pre_log = np.log(prediction).astype(dtype)
tar_log = np.log(target).astype(dtype)
sub_log = np.subtract(tar_log, pre_log)
expect = np.multiply(target, sub_log).astype(dtype)
if reduction == 'sum':
expect = np.sum(expect)
if reduction == 'mean':
expect = np.mean(expect)
if reduction == 'batchmean':
reduce_axis = tuple(np.arange(1, len(shape)))
expect = np.mean(expect, axis=reduce_axis, keepdims=False)
if reduction == 'sum' or reduction == 'mean':
out_shape = []
out_shape.append(1)
output = np.full(out_shape, 0, dtype)
if reduction == 'batchmean':
reduce_axis = tuple(np.arange(1, len(shape)))
out_shape = get_reduce_out_shape(shape, axis=reduce_axis, keepdims=False)
output = np.full(expect.shape, np.nan, dtype)
if reduction == 'none':
output = np.full(expect.shape, np.nan, dtype)
return expect, output, prediction, target
|
18270681cf7b927a12b8a6174603e50cd57b1046
|
c530897cb72b6943c7226b25824444cad5f3503b
|
/usaspending_api/etl/tests/integration/test_spark_app.py
|
47dedd1f3d8c1a54fd4472db92937624e6a29ec7
|
[
"CC0-1.0"
] |
permissive
|
fedspendingtransparency/usaspending-api
|
fc63a22d32ea0207b7273d3e1ef26ba9dbabc42a
|
38f920438697930ae3ac57bbcaae9034877d8fb7
|
refs/heads/master
| 2023-09-01T22:00:36.633612
| 2023-08-29T18:39:18
| 2023-08-29T18:39:18
| 65,394,827
| 276
| 118
|
CC0-1.0
| 2023-09-14T20:33:15
| 2016-08-10T15:39:45
|
Python
|
UTF-8
|
Python
| false
| false
| 12,930
|
py
|
test_spark_app.py
|
"""Module to verify that spark-based integration tests can run in our CI environment, with all required
spark components (docker-compose container services) are up and running and integratable.
NOTE: Uses Pytest Fixtures from immediate parent conftest.py: usaspending_api/etl/tests/conftest.py
"""
import logging
import random
import sys
import uuid
from datetime import date
from unittest.mock import MagicMock, call
import boto3
from model_bakery import baker
from pyspark.sql import SparkSession, Row
from pytest import fixture, mark
from usaspending_api.awards.models import TransactionFABS, TransactionFPDS
from usaspending_api.common.helpers.spark_helpers import (
get_jvm_logger,
get_jdbc_url_from_pg_uri,
get_jdbc_connection_properties,
get_broker_jdbc_url,
)
from usaspending_api.common.etl.spark import _USAS_RDS_REF_TABLES, _BROKER_REF_TABLES, create_ref_temp_views
from usaspending_api.common.helpers.sql_helpers import get_database_dsn_string
from usaspending_api.config import CONFIG
def test_hive_metastore_db(spark: SparkSession, s3_unittest_data_bucket, hive_unittest_metastore_db):
"""Ensure that schemas and tables created are tracked in the hive metastore_db"""
test_schema = "my_delta_test_schema"
test_table = "my_delta_test_table"
spark.sql(f"create schema if not exists {test_schema}")
spark.sql(
f"""
create table if not exists {test_schema}.{test_table}(id INT, name STRING, age INT)
using delta
location 's3a://{s3_unittest_data_bucket}/{CONFIG.DELTA_LAKE_S3_PATH}/{test_table}'
"""
)
schemas_in_metastore = [s[0] for s in spark.sql("SHOW SCHEMAS").collect()]
assert len(schemas_in_metastore) == 2
assert "default" in schemas_in_metastore
assert test_schema in schemas_in_metastore
spark.sql(f"USE {test_schema}")
tables_in_test_schema = [t for t in spark.sql("SHOW TABLES").collect()]
assert len(tables_in_test_schema) == 1
assert tables_in_test_schema[0]["namespace"] == test_schema
assert tables_in_test_schema[0]["tableName"] == test_table
def test_tmp_hive_metastore_db_empty_on_test_start(spark: SparkSession, hive_unittest_metastore_db):
"""Test that when using the spark test fixture, the metastore_db is configured to live in a tmp directory,
so that schemas and tables created while under-test only live or are known for the duration of a SINGLE test,
not a test SESSION. And test that the metastore used for unit tests is empty on each test run (except for the
empty "default" database"""
# Ensure only the default schema exists
schemas_in_metastore = [s[0] for s in spark.sql("SHOW SCHEMAS").collect()]
assert len(schemas_in_metastore) == 1
assert schemas_in_metastore[0] == "default"
# Ensure the default schema has no tables
spark.sql("USE DEFAULT")
tables_in_default_schema = [t for t in spark.sql("SHOW TABLES").collect()]
assert len(tables_in_default_schema) == 0
def test_spark_app_run_local_master(spark: SparkSession):
"""Execute a simple spark app and verify it logged expected output.
Effectively if it runs without failing, it worked.
NOTE: This will probably work regardless of whether any separately running (dockerized) spark infrastructure is
present in the CI integration test env, because it will leverage the pyspark PyPI dependent package that is
discovered in the PYTHONPATH, and treat the client machine as the spark driver.
And furthermore, the default config for spark.master property if not set is local[*]
"""
logger = get_jvm_logger(spark)
versions = f"""
@ Python Version: {sys.version}
@ Spark Version: {spark.version}
@ Hadoop Version: {spark.sparkContext._gateway.jvm.org.apache.hadoop.util.VersionInfo.getVersion()}
"""
logger.info(versions)
def test_spark_write_csv_app_run(spark: SparkSession, s3_unittest_data_bucket):
"""More involved integration test that requires MinIO to be up as an s3 alternative."""
data = [
{"first_col": "row 1", "id": str(uuid.uuid4()), "color": "blue", "numeric_val": random.randint(-100, 100)},
{"first_col": "row 2", "id": str(uuid.uuid4()), "color": "green", "numeric_val": random.randint(-100, 100)},
{"first_col": "row 3", "id": str(uuid.uuid4()), "color": "pink", "numeric_val": random.randint(-100, 100)},
{"first_col": "row 4", "id": str(uuid.uuid4()), "color": "yellow", "numeric_val": random.randint(-100, 100)},
{"first_col": "row 5", "id": str(uuid.uuid4()), "color": "red", "numeric_val": random.randint(-100, 100)},
{"first_col": "row 6", "id": str(uuid.uuid4()), "color": "orange", "numeric_val": random.randint(-100, 100)},
{"first_col": "row 7", "id": str(uuid.uuid4()), "color": "magenta", "numeric_val": random.randint(-100, 100)},
]
df = spark.createDataFrame([Row(**data_row) for data_row in data])
# NOTE! NOTE! NOTE! MinIO locally does not support a TRAILING SLASH after object (folder) name
df.write.option("header", True).csv(f"s3a://{s3_unittest_data_bucket}" f"/{CONFIG.DELTA_LAKE_S3_PATH}/write_to_s3")
# Verify there are *.csv part files in the chosen bucket
s3_client = boto3.client(
"s3",
endpoint_url=f"http://{CONFIG.AWS_S3_ENDPOINT}",
aws_access_key_id=CONFIG.AWS_ACCESS_KEY.get_secret_value(),
aws_secret_access_key=CONFIG.AWS_SECRET_KEY.get_secret_value(),
)
response = s3_client.list_objects_v2(Bucket=s3_unittest_data_bucket)
assert "Contents" in response # the Bucket has contents
bucket_objects = [c["Key"] for c in response["Contents"]]
assert any([obj.endswith(".csv") for obj in bucket_objects])
@fixture()
def _transaction_and_award_test_data(db):
agency1 = baker.make("references.Agency")
awd1 = baker.make("search.AwardSearch", award_id=1, awarding_agency_id=agency1.id)
baker.make(
"search.TransactionSearch",
transaction_id=1,
award=awd1,
modification_number="1",
awarding_agency_id=agency1.id,
last_modified_date=date(2012, 3, 1),
business_funds_indicator="a",
record_type=1,
total_funding_amount=1000.00,
is_fpds=False,
)
assert TransactionFABS.objects.all().count() == 1
awd2 = baker.make("search.AwardSearch", award_id=1, awarding_agency_id=agency1.id)
baker.make(
"search.TransactionSearch",
transaction_id=2,
award=awd2,
modification_number="1",
awarding_agency_id=agency1.id,
last_modified_date=date(2012, 4, 1),
is_fpds=True,
piid="abc",
base_and_all_options_value=1000,
)
assert TransactionFPDS.objects.all().count() == 1
@mark.django_db(transaction=True) # must commit Django data for Spark to be able to read it
def test_spark_write_to_s3_delta_from_db(
_transaction_and_award_test_data,
spark: SparkSession,
delta_lake_unittest_schema,
s3_unittest_data_bucket,
request,
):
"""Test that we can read from Postgres DB and write to new delta tables,
and the tables are created and data gets there"""
pg_uri = get_database_dsn_string()
jdbc_url = get_jdbc_url_from_pg_uri(pg_uri)
if not jdbc_url.startswith("jdbc:postgresql://"):
raise ValueError("JDBC URL given is not in postgres JDBC URL format (e.g. jdbc:postgresql://...")
schema_name = delta_lake_unittest_schema
# ==== transaction_normalized ====
table_name = "vw_transaction_normalized"
logging.info(f"Reading db records for {table_name} from connection: {jdbc_url}")
df = spark.read.jdbc(url=jdbc_url, table=table_name, properties=get_jdbc_connection_properties())
# NOTE! NOTE! NOTE! MinIO locally does not support a TRAILING SLASH after object (folder) name
path = f"s3a://{s3_unittest_data_bucket}/{CONFIG.DELTA_LAKE_S3_PATH}/{table_name}"
log = get_jvm_logger(spark, request.node.name)
log.info(f"Loading {df.count()} rows from DB to Delta table named {schema_name}.{table_name} at path {path}")
# Create table in the metastore using DataFrame's schema and write data to the table
df.write.saveAsTable(
format="delta",
name=f"{table_name}",
mode="overwrite",
path=path,
)
# ==== transaction_fabs ====
table_name = "vw_transaction_fabs"
logging.info(f"Reading db records for {table_name} from connection: {jdbc_url}")
df = spark.read.jdbc(url=jdbc_url, table=table_name, properties=get_jdbc_connection_properties())
# NOTE! NOTE! NOTE! MinIO locally does not support a TRAILING SLASH after object (folder) name
path = f"s3a://{s3_unittest_data_bucket}/{CONFIG.DELTA_LAKE_S3_PATH}/{table_name}"
log = get_jvm_logger(spark, request.node.name)
log.info(f"Loading {df.count()} rows from DB to Delta table named {schema_name}.{table_name} at path {path}")
# Create table in the metastore using DataFrame's schema and write data to the table
df.write.saveAsTable(
format="delta",
name=f"{table_name}",
mode="overwrite",
path=path,
)
# ==== transaction_fpds ====
table_name = "vw_transaction_fpds"
logging.info(f"Reading db records for {table_name} from connection: {jdbc_url}")
df = spark.read.jdbc(url=jdbc_url, table=table_name, properties=get_jdbc_connection_properties())
# NOTE! NOTE! NOTE! MinIO locally does not support a TRAILING SLASH after object (folder) name
path = f"s3a://{s3_unittest_data_bucket}/{CONFIG.DELTA_LAKE_S3_PATH}/{table_name}"
log = get_jvm_logger(spark, request.node.name)
log.info(f"Loading {df.count()} rows from DB to Delta table named {schema_name}.{table_name} at path {path}")
# Create table in the metastore using DataFrame's schema and write data to the table
df.write.saveAsTable(
format="delta",
name=f"{table_name}",
mode="overwrite",
path=path,
)
schema_tables = spark.sql(f"show tables in {schema_name}").collect()
assert len(schema_tables) == 3
schema_table_names = [t.tableName for t in schema_tables]
assert "vw_transaction_normalized" in schema_table_names
assert "vw_transaction_fabs" in schema_table_names
assert "vw_transaction_fpds" in schema_table_names
# Now assert that we're still by-default using the unittest schema, by way of using that pytest fixture.
# i.e. don't tell it what schema to look at
tables = spark.sql(f"show tables").collect()
assert len(tables) == 3
table_names = [t.tableName for t in tables]
assert "vw_transaction_normalized" in table_names
assert "vw_transaction_fabs" in table_names
assert "vw_transaction_fpds" in table_names
# Assert rows are present
assert spark.sql("select count(*) from vw_transaction_normalized").collect()[0][0] == 2
assert spark.sql("select count(*) from vw_transaction_fabs").collect()[0][0] == 1
assert spark.sql("select count(*) from vw_transaction_fpds").collect()[0][0] == 1
@mark.django_db(transaction=True)
def test_create_ref_temp_views(spark: SparkSession):
# Add dummy data to each test views
for rds_ref_table in _USAS_RDS_REF_TABLES:
baker.make(rds_ref_table)
baker.make(rds_ref_table)
baker.make(rds_ref_table)
# make the temp views
create_ref_temp_views(spark)
# verify the data in the temp view matches the dummy data
for rds_ref_table in _USAS_RDS_REF_TABLES:
spark_count = spark.sql(f"select count(*) from global_temp.{rds_ref_table._meta.db_table}").collect()[0][0]
assert rds_ref_table.objects.count() == spark_count
# Setup for testing the Broker table(s)
mock_spark_session = MagicMock(autospec=SparkSession)
mock_broker_sql_strings = []
jdbc_conn_props = get_jdbc_connection_properties()
for broker_table in _BROKER_REF_TABLES:
mock_broker_sql_strings.append(
call(
f"""
CREATE OR REPLACE GLOBAL TEMPORARY VIEW {broker_table}
USING JDBC
OPTIONS (
driver '{jdbc_conn_props["driver"]}',
fetchsize '{jdbc_conn_props["fetchsize"]}',
url '{get_broker_jdbc_url()}',
dbtable '{broker_table}'
)
"""
)
)
# Test that the Broker's SQL is being run when create_broker_views=True
create_ref_temp_views(mock_spark_session, create_broker_views=True)
mock_spark_session.sql.assert_called()
mock_spark_session.sql.assert_has_calls(mock_broker_sql_strings, any_order=True)
# Test that the Broker's SQL is NOT being called when create_broker_views=False
mock_spark_session.sql.reset_mock()
create_ref_temp_views(mock_spark_session)
for broker_mock_call in mock_broker_sql_strings:
assert broker_mock_call not in mock_spark_session.sql.mock_calls
|
b4c2f1195ac9c6babd01ac35feece3d5eaf772bc
|
3daa53a2190f365ee2e2acae39ca4e84919f2f50
|
/test/unit/common/middleware/s3api/test_etree.py
|
63cb5c7ffc1fdee770055b6ec835814ddc72d347
|
[
"Apache-2.0"
] |
permissive
|
openstack/swift
|
4c8e4a14c1c6f7efb049f983ede28e89bd2e9140
|
f06e5369579599648cc78e4b556887bc6d978c2b
|
refs/heads/master
| 2023-08-28T15:04:33.200849
| 2023-08-24T20:35:07
| 2023-08-24T21:05:48
| 790,019
| 2,370
| 957
|
Apache-2.0
| 2023-06-22T02:45:53
| 2010-07-22T01:50:07
|
Python
|
UTF-8
|
Python
| false
| false
| 2,775
|
py
|
test_etree.py
|
# Copyright (c) 2014 OpenStack Foundation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import unittest
import six
from swift.common.middleware.s3api import etree
class TestS3ApiEtree(unittest.TestCase):
def test_xml_namespace(self):
def test_xml(ns, prefix):
return '<A %(ns)s><%(prefix)sB>C</%(prefix)sB></A>' % \
({'ns': ns, 'prefix': prefix})
# No namespace is same as having the S3 namespace.
xml = test_xml('', '')
elem = etree.fromstring(xml)
self.assertEqual(elem.find('./B').text, 'C')
# The S3 namespace is handled as no namespace.
xml = test_xml('xmlns="%s"' % etree.XMLNS_S3, '')
elem = etree.fromstring(xml)
self.assertEqual(elem.find('./B').text, 'C')
xml = test_xml('xmlns:s3="%s"' % etree.XMLNS_S3, 's3:')
elem = etree.fromstring(xml)
self.assertEqual(elem.find('./B').text, 'C')
# Any namespaces without a prefix work as no namespace.
xml = test_xml('xmlns="http://example.com/"', '')
elem = etree.fromstring(xml)
self.assertEqual(elem.find('./B').text, 'C')
xml = test_xml('xmlns:s3="http://example.com/"', 's3:')
elem = etree.fromstring(xml)
self.assertIsNone(elem.find('./B'))
def test_xml_with_comments(self):
xml = '<A><!-- comment --><B>C</B></A>'
elem = etree.fromstring(xml)
self.assertEqual(elem.find('./B').text, 'C')
def test_tostring_with_nonascii_text(self):
elem = etree.Element('Test')
sub = etree.SubElement(elem, 'FOO')
sub.text = '\xef\xbc\xa1'
self.assertTrue(isinstance(sub.text, str))
xml_string = etree.tostring(elem)
self.assertIsInstance(xml_string, bytes)
def test_fromstring_with_nonascii_text(self):
input_str = b'<?xml version="1.0" encoding="UTF-8"?>\n' \
b'<Test><FOO>\xef\xbc\xa1</FOO></Test>'
elem = etree.fromstring(input_str)
text = elem.find('FOO').text
if six.PY2:
self.assertEqual(text, b'\xef\xbc\xa1')
else:
self.assertEqual(text, b'\xef\xbc\xa1'.decode('utf8'))
self.assertIsInstance(text, str)
if __name__ == '__main__':
unittest.main()
|
fce037fe82d29a8dc3371f951534ea2d71587953
|
3225f903ab65e9e242f250a02b3b74fc7e34b098
|
/gateware/opsis_i2c.py
|
6376c73bf3e63cf22c463ab4694663620f1ae247
|
[
"MIT",
"BSD-2-Clause"
] |
permissive
|
timvideos/litex-buildenv
|
6f7657a0d2836f66bbc8ad29f89f1f975eda7832
|
fafb0f1c645a0d36ff4947686b4d2d8e3433f686
|
refs/heads/master
| 2022-06-04T18:02:22.567089
| 2022-05-21T15:21:25
| 2022-05-21T15:21:25
| 115,785,208
| 217
| 88
|
BSD-2-Clause
| 2022-05-21T15:21:26
| 2017-12-30T08:50:22
|
Python
|
UTF-8
|
Python
| false
| false
| 7,764
|
py
|
opsis_i2c.py
|
"""Modules for I2C bus on the Opsis.
FIXME: Refactor this properly...
"""
from migen.fhdl import *
from migen.fhdl.specials import TSTriple
from migen.genlib.cdc import MultiReg
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser
from migen.genlib.misc import split, displacer, chooser
from litex.soc.cores.gpio import GPIOIn, GPIOOut
from litex.soc.interconnect.csr import *
from gateware import i2c
class I2CShiftReg(Module, AutoCSR):
def __init__(self, pads):
STATUS_FULL = 1
STATUS_EMPTY = 2
self.shift_reg = shift_reg = CSRStorage(8, write_from_dev=True)
self.status = status = CSRStorage(2, reset=STATUS_EMPTY, write_from_dev=True)
self.slave_addr = slave_addr = CSRStorage(7)
###
scl_raw = Signal()
sda_i = Signal()
sda_raw = Signal()
sda_drv = Signal()
scl_drv = Signal()
_sda_drv_reg = Signal()
self._sda_i_async = _sda_i_async = Signal()
self._scl_i_async = _scl_i_async = Signal()
_scl_drv_reg = Signal()
self.sync += _sda_drv_reg.eq(sda_drv)
self.sync += _scl_drv_reg.eq(scl_drv)
self.comb += [
pads.scl.w.eq(0),
pads.scl.oe.eq(_scl_drv_reg),
_scl_i_async.eq(pads.scl.r),
pads.sda.w.eq(0),
pads.sda.oe.eq(_sda_drv_reg),
_sda_i_async.eq(pads.sda.r),
]
self.specials += [
MultiReg(_scl_i_async, scl_raw),
MultiReg(_sda_i_async, sda_raw),
]
# for debug
self.scl = scl_raw
self.sda_i = sda_i
self.sda_o = Signal()
self.comb += self.sda_o.eq(~_sda_drv_reg)
self.sda_oe = _sda_drv_reg
shift_reg_full = Signal()
shift_reg_empty = Signal()
scl_i = Signal()
samp_count = Signal(3)
samp_carry = Signal()
self.sync += [
Cat(samp_count, samp_carry).eq(samp_count + 1),
If(samp_carry,
scl_i.eq(scl_raw),
sda_i.eq(sda_raw)
)
]
scl_r = Signal()
sda_r = Signal()
scl_rising = Signal()
scl_falling = Signal()
sda_rising = Signal()
sda_falling = Signal()
self.sync += [
scl_r.eq(scl_i),
sda_r.eq(sda_i)
]
self.comb += [
shift_reg_full.eq(status.storage[0]),
shift_reg_empty.eq(status.storage[1]),
scl_rising.eq(scl_i & ~scl_r),
scl_falling.eq(~scl_i & scl_r),
sda_rising.eq(sda_i & ~sda_r),
sda_falling.eq(~sda_i & sda_r)
]
start = Signal()
self.comb += start.eq(scl_i & sda_falling)
din = Signal(8)
counter = Signal(max=9)
counter_reset = Signal()
self.sync += [
If(start | counter_reset, counter.eq(0)),
If(scl_rising,
If(counter == 8,
counter.eq(0)
).Else(
counter.eq(counter + 1),
din.eq(Cat(sda_i, din[:7]))
)
)
]
self.din = din
self.counter = counter
is_read = Signal()
update_is_read = Signal()
self.sync += If(update_is_read, is_read.eq(din[0]))
data_bit = Signal()
zero_drv = Signal()
data_drv = Signal()
pause_drv = Signal()
self.comb += scl_drv.eq(pause_drv)
self.comb += If(zero_drv, sda_drv.eq(1)).Elif(data_drv,
sda_drv.eq(~data_bit))
data_drv_en = Signal()
data_drv_stop = Signal()
self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop,
data_drv.eq(0))
self.sync += If(data_drv_en, chooser(shift_reg.storage,
counter, data_bit, 8,
reverse=True))
self.submodules.fsm = fsm = FSM()
fsm.act("WAIT_START",
data_drv_stop.eq(1),
)
fsm.act("RCV_ADDRESS",
data_drv_stop.eq(1),
If(counter == 8,
If(din[1:] == slave_addr.storage,
update_is_read.eq(1),
NextState("ACK_ADDRESS0"),
).Else(
NextState("WAIT_START"),
)
)
)
fsm.act("ACK_ADDRESS0",
counter_reset.eq(1),
If(~scl_i, NextState("ACK_ADDRESS1")),
)
fsm.act("ACK_ADDRESS1",
counter_reset.eq(1),
zero_drv.eq(1),
If(scl_i, NextState("ACK_ADDRESS2")),
)
fsm.act("ACK_ADDRESS2",
counter_reset.eq(1),
zero_drv.eq(1),
If(~scl_i,
NextState("PAUSE")
)
)
fsm.act("PAUSE",
counter_reset.eq(1),
pause_drv.eq(1),
If(~shift_reg_empty & is_read,
counter_reset.eq(1),
NextState("DO_READ"),
).Elif(~shift_reg_full & ~is_read,
NextState("DO_WRITE"),
)
)
fsm.act("DO_READ",
If(~scl_i,
If(counter == 8,
data_drv_stop.eq(1),
status.we.eq(1),
status.dat_w.eq(STATUS_EMPTY),
NextState("ACK_READ0"),
).Else(
data_drv_en.eq(1),
)
)
)
fsm.act("ACK_READ0",
counter_reset.eq(1),
If(scl_rising,
If(sda_i,
NextState("WAIT_START"),
).Else(
NextState("ACK_READ1"),
)
)
)
fsm.act("ACK_READ1",
counter_reset.eq(1),
If(scl_falling,
NextState("PAUSE"),
)
)
fsm.act("DO_WRITE",
If(counter == 8,
shift_reg.dat_w.eq(din),
shift_reg.we.eq(1),
NextState("ACK_WRITE0"),
)
)
fsm.act("ACK_WRITE0",
counter_reset.eq(1),
If(~scl_i, NextState("ACK_WRITE1")),
)
fsm.act("ACK_WRITE1",
counter_reset.eq(1),
zero_drv.eq(1),
If(scl_i, NextState("ACK_WRITE2")),
)
fsm.act("ACK_WRITE2",
counter_reset.eq(1),
zero_drv.eq(1),
If(~scl_i,
NextState("PAUSE"),
status.we.eq(1),
status.dat_w.eq(STATUS_FULL),
)
)
for state in fsm.actions.keys():
fsm.act(state, If(start, NextState("RCV_ADDRESS")))
for state in fsm.actions.keys():
fsm.act(state, If(self.slave_addr.re, NextState("WAIT_START")))
class OpsisI2C(Module, AutoCSR):
"""I2C bus on the Opsis.
Used for;
* Small EEPROM which contains FX2 firmware + MAC address.
* Loading firmware onto the FX2.
"""
def __init__(self, platform):
self.submodules.mux = i2c.I2CMux(platform.request("opsis_i2c"))
self.submodules.master = i2c.I2C(self.mux.get_i2c_pads())
# Use a proper Tristate for the FX2 reset so the "pull up" works.
fx2_reset = TSTriple(1)
self.comb += [
fx2_reset.o.eq(0),
]
self.specials += [
fx2_reset.get_tristate(platform.request("fx2_reset")),
]
self.submodules.fx2_reset = GPIOOut(fx2_reset.oe)
self.submodules.fx2_hack = I2CShiftReg(self.mux.get_i2c_pads())
|
1cb4ab1cdc699f617c2b828be3aa694025091e42
|
fa1ad2e2ac7e376fc7cb3b3a6e1bb88eed3e80be
|
/dts/seatunnel/tools/update_modules_check/update_modules_check.py
|
324a961bc7e2de25dc60fa1777d5766fb75487dc
|
[
"Apache-2.0",
"BSD-3-Clause",
"MIT"
] |
permissive
|
alldatacenter/alldata
|
7bc7713c9f1d56ad6b8e59ea03206d1073b7e047
|
8d5f9a2d49ab8f9e85ccf058cb02c2fda287afc6
|
refs/heads/master
| 2023-08-05T07:32:25.442740
| 2023-08-03T13:17:24
| 2023-08-03T13:17:24
| 213,321,771
| 774
| 250
|
Apache-2.0
| 2023-09-06T17:35:32
| 2019-10-07T07:36:18
| null |
UTF-8
|
Python
| false
| false
| 6,797
|
py
|
update_modules_check.py
|
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership.
# The ASF licenses this file to You under the Apache License, Version 2.0
# (the "License"); you may not use this file except in compliance with
# the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# !/usr/bin/python
import json
import sys
def get_cv2_modules(files):
get_modules(files, 1, "connector-", "seatunnel-connectors-v2")
def get_cv2_e2e_modules(files):
get_modules(files, 2, "connector-", "seatunnel-connector-v2-e2e")
def get_engine_modules(files):
# We don't run all connector e2e when engine module update
print(",connector-seatunnel-e2e-base,connector-console-seatunnel-e2e")
def get_engine_e2e_modules(files):
get_modules(files, 2, "connector-", "seatunnel-engine-e2e")
def get_modules(files, index, start_pre, root_module):
update_files = json.loads(files)
modules_name_set = set([])
for file in update_files:
names = file.split('/')
module_name = names[index]
if module_name.startswith(start_pre):
modules_name_set.add(module_name)
if len(names) > index + 1 and names[index + 1].startswith(start_pre):
modules_name_set.add(names[index + 1])
output_module = ""
if len(modules_name_set) > 0:
for module in modules_name_set:
output_module = output_module + "," + module
else:
output_module = output_module + "," + root_module
print(output_module)
def replace_comma_to_commacolon(modules_str):
modules_str = modules_str.replace(",", ",:")
modules_str = ":" + modules_str
print(modules_str)
def get_sub_modules(file):
output = ""
with open(file, 'r', encoding='utf-8') as f:
for line in f.readlines():
line = line.replace(" ", "")
if line.startswith("<string>"):
line = line.replace(" ", "").replace("<string>", "").replace("</string>", "").replace("\n", "")
output = output + "," + line
print(output)
def get_dependency_tree_includes(modules_str):
modules = modules_str.split(',')
output = ""
for module in modules:
output = ",org.apache.seatunnel:" + module + output
output = output[1:len(output)]
output = "-Dincludes=" + output
print(output)
def get_final_it_modules(file):
output = ""
with open(file, 'r', encoding='utf-8') as f:
for line in f.readlines():
if line.startswith("org.apache.seatunnel"):
con = line.split(":")
# find all e2e modules
if con[2] == "jar" and "-e2e" in con[1] and "transform" not in con[1]:
output = output + "," + ":" + con[1]
output = output[1:len(output)]
print(output)
def get_final_ut_modules(file):
output = ""
with open(file, 'r', encoding='utf-8') as f:
for line in f.readlines():
if line.startswith("org.apache.seatunnel"):
con = line.split(":")
# find all e2e modules
if con[2] == "jar":
output = output + "," + ":" + con[1]
output = output[1:len(output)]
print(output)
def remove_deleted_modules(pl_modules, deleted_modules):
pl_modules_arr = pl_modules.replace(":", "").split(",")
deleted_modules_arr = deleted_modules.split(",")
output = ""
for module in pl_modules_arr:
if deleted_modules_arr.count(module) == 0:
output = output + ",:" + module
output = output[1:len(output)]
print(output)
def get_deleted_modules(files):
update_files = json.loads(files)
modules_name_set = set([])
for file in update_files:
names = file.split('/')
module_name = names[len(names) - 2]
modules_name_set.add(module_name)
output_module = ""
if len(modules_name_set) > 0:
for module in modules_name_set:
output_module = output_module + "," + module
output_module = output_module[1:len(output_module)]
print(output_module)
def get_sub_it_modules(modules, total_num, current_num):
modules_arr = modules.split(",")
modules_arr.remove("connector-jdbc-e2e")
modules_arr.remove("connector-kafka-e2e")
modules_arr.remove("connector-rocketmq-e2e")
output = ""
for i, module in enumerate(modules_arr):
if len(module) > 0 and i % int(total_num) == int(current_num):
output = output + ",:" + module
output = output[1:len(output)]
print(output)
def get_sub_update_it_modules(modules, total_num, current_num):
final_modules = list()
# :connector-jdbc-e2e-common,:connector-jdbc-e2e-part-1 --> connector-jdbc-e2e-common,:connector-jdbc-e2e-part-1
modules = modules[1:]
# connector-jdbc-e2e-common,:connector-jdbc-e2e-part-1 --> [connector-jdbc-e2e-common, connector-jdbc-e2e-part-1]
module_list = modules.split(",:")
for i, module in enumerate(module_list):
if len(module) > 0 and i % int(total_num) == int(current_num):
final_modules.append(":" + module)
print(",".join(final_modules))
def main(argv):
if argv[1] == "cv2":
get_cv2_modules(argv[2])
elif argv[1] == "cv2-e2e":
get_cv2_e2e_modules(argv[2])
elif argv[1] == "cv2-flink-e2e":
get_cv2_flink_e2e_modules(argv[2])
elif argv[1] == "cv2-spark-e2e":
get_cv2_spark_e2e_modules(argv[2])
elif argv[1] == "engine":
get_engine_modules(argv[2])
elif argv[1] == "engine-e2e":
get_engine_e2e_modules(argv[2])
elif argv[1] == "tree":
get_dependency_tree_includes(argv[2])
elif argv[1] == "final_it":
get_final_it_modules(argv[2])
elif argv[1] == "final_ut":
get_final_ut_modules(argv[2])
elif argv[1] == "replace":
replace_comma_to_commacolon(argv[2])
elif argv[1] == "sub":
get_sub_modules(argv[2])
elif argv[1] == "delete":
get_deleted_modules(argv[2])
elif argv[1] == "rm":
remove_deleted_modules(argv[2], argv[3])
elif argv[1] == "sub_it_module":
get_sub_it_modules(argv[2], argv[3], argv[4])
elif argv[1] == "sub_update_it_module":
get_sub_update_it_modules(argv[2], argv[3], argv[4])
if __name__ == "__main__":
main(sys.argv)
|
4a72263745b43da48558d8f27a8181b9db7cd05a
|
4c9997c8bcc8bbdea0bb8a043fdb7644bd99b02c
|
/src/ReIDdatasets.py
|
26be169806e04a8079aba9efd67bb80bd59afb9f
|
[] |
no_license
|
KovenYu/MAR
|
22cb1224da2378f3f89565431ac38f4888e9256a
|
860031695e4e1b623b48a7a1228a3cf8051d8dcf
|
refs/heads/master
| 2021-12-31T08:13:47.459636
| 2021-12-22T01:27:45
| 2021-12-22T01:27:45
| 175,545,909
| 341
| 93
| null | null | null | null |
UTF-8
|
Python
| false
| false
| 4,514
|
py
|
ReIDdatasets.py
|
import h5py
import numpy as np
import torch.utils.data as data
from PIL import Image
class Market(data.Dataset):
def __init__(self, root, state='train', transform=None, require_views=True):
super(Market, self).__init__()
self.root = root
self.state = state
self.transform = transform
self.require_views = require_views
if self.transform is not None:
self.on_transform = True
else:
self.on_transform = False
f = h5py.File(self.root, 'r')
variables = list(f.items())
# [0]: gallery_data
# [1]: gallery_labels
# [2]: gallery_views
# [3]: probe_data
# [4]: probe_labels
# [5]: probe_views
# [6]: train_data
# [7]: train_labels
# [8]: train_views
if self.state == 'train':
_, temp = variables[6]
self.data = np.transpose(temp.value, (0, 3, 2, 1))
_, temp = variables[7]
self.labels = np.squeeze(temp.value)
_, temp = variables[8]
self.views = np.squeeze(temp.value)
elif self.state == 'gallery':
_, temp = variables[0]
self.data = np.transpose(temp.value, (0, 3, 2, 1))
_, temp = variables[1]
self.labels = np.squeeze(temp.value)
_, temp = variables[2]
self.views = np.squeeze(temp.value)
elif self.state == 'probe':
_, temp = variables[3]
self.data = np.transpose(temp.value, (0, 3, 2, 1))
_, temp = variables[4]
self.labels = np.squeeze(temp.value)
_, temp = variables[5]
self.views = np.squeeze(temp.value)
else:
assert False, 'Unknown state: {}\n'.format(self.state)
def return_mean(self, axis=(0, 1, 2)):
return np.mean(self.data, axis)
def return_std(self, axis=(0, 1, 2)):
return np.std(self.data, axis)
def return_num_class(self):
return np.size(np.unique(self.labels))
def turn_on_transform(self, transform=None):
self.on_transform = True
if transform is not None:
self.transform = transform
assert self.transform is not None, 'Transform not specified.'
def turn_off_transform(self):
self.on_transform = False
def __len__(self):
return self.labels.shape[0]
def __getitem__(self, index):
img, label, view = self.data[index], self.labels[index], self.views[index]
img = Image.fromarray(img)
if self.on_transform:
img = self.transform(img)
if self.require_views:
return img, label, view, index
else:
return img, label
class FullTraining(data.Dataset):
def __init__(self, root, transform=None, require_views=False):
super(FullTraining, self).__init__()
self.root = root
self.transform = transform
self.require_views = require_views
if self.transform is not None:
self.on_transform = True
else:
self.on_transform = False
f = h5py.File(self.root, 'r')
variables = list(f.items())
# [0]: data
# [1]: labels
_, temp = variables[0]
self.data = np.transpose(temp.value, (0, 3, 2, 1))
_, temp = variables[1]
self.labels = np.squeeze(temp.value)
def return_mean(self, axis=(0, 1, 2)):
if 'MSMT17' in self.root:
return np.array([79.2386, 73.9793, 77.2493])
else:
return np.std(self.data, axis)
def return_std(self, axis=(0, 1, 2)):
if 'MSMT17' in self.root:
return np.array([67.2012, 63.9191, 61.8367])
else:
return np.std(self.data, axis)
def return_num_class(self):
return np.size(np.unique(self.labels))
def turn_on_transform(self, transform=None):
self.on_transform = True
if transform is not None:
self.transform = transform
assert self.transform is not None, 'Transform not specified.'
def turn_off_transform(self):
self.on_transform = False
def __len__(self):
return self.labels.shape[0]
def __getitem__(self, index):
img, label = self.data[index], self.labels[index]
img = Image.fromarray(img)
if self.on_transform:
img = self.transform(img)
return img, label
def main():
pass
if __name__ == '__main__':
main()
|
1c520d17006ab70c0e5282071c84fc444c5aa56b
|
5c508c0cd2e637f06caa674282dd9eeff7bd63ae
|
/app_common/models/res_users.py
|
1c18b7ad2f8a02b30a11c4d5c671ee9b3b462615
|
[] |
no_license
|
guohuadeng/app-odoo
|
606afda698003aa0f9633903435085404659a1a8
|
2e06dfc88071f8f229863aa7edc7ce3bfcdc21f0
|
refs/heads/13.0
| 2023-08-30T21:01:11.040302
| 2023-08-28T08:17:34
| 2023-08-28T08:17:34
| 98,264,816
| 308
| 347
| null | 2023-02-13T15:52:00
| 2017-07-25T04:39:16
|
HTML
|
UTF-8
|
Python
| false
| false
| 244
|
py
|
res_users.py
|
# -*- coding: utf-8 -*-
# Part of Odoo. See LICENSE file for full copyright and licensing details.
from odoo import api, fields, models, tools, _
class ResUsers(models.Model):
_inherit = 'res.users'
login = fields.Char(index=True)
|
56a9bb44b78556f0b3796439ca7c4bfdfaa64fbf
|
d78675577db0716204b19302f930ebd64216b74f
|
/testapps/on_device_unit_tests/test_app/widgets.py
|
eab93405ae2f6d975af25ba7695965a521dcc79a
|
[
"MIT",
"Python-2.0"
] |
permissive
|
kivy/python-for-android
|
1c676f6899d6b469bfb3f833996adb5475f7d3c1
|
4d50d7d883bb6313f37c22402ecfaefa689bbbed
|
refs/heads/develop
| 2023-09-03T19:22:51.596101
| 2023-09-03T07:56:15
| 2023-09-03T07:56:15
| 2,866,041
| 7,512
| 1,840
|
MIT
| 2023-09-03T09:59:02
| 2011-11-28T09:02:36
|
Python
|
UTF-8
|
Python
| false
| false
| 657
|
py
|
widgets.py
|
# -*- coding: utf-8 -*-
from kivy.properties import StringProperty
from kivy.uix.boxlayout import BoxLayout
from kivy.uix.popup import Popup
from kivy.uix.behaviors.button import ButtonBehavior
from kivy.uix.widget import Widget
from kivy.vector import Vector
from tools import load_kv_from
load_kv_from('widgets.kv')
class Spacer20(Widget):
pass
class TestImage(BoxLayout):
text = StringProperty()
source = StringProperty()
class CircularButton(ButtonBehavior, Widget):
def collide_point(self, x, y):
return Vector(x, y).distance(self.center) <= self.width / 2
class ErrorPopup(Popup):
error_text = StringProperty('')
|
29aec44aaeaee17f3f112af8faf28cadc6094e70
|
3eb3c4046b17e265930aaf89fa93f41896f243cb
|
/spynnaker/pyNN/models/abstract_pynn_model.py
|
fbbb7f070a3bbad622b3c44d30a151ad56af2479
|
[
"Apache-2.0"
] |
permissive
|
SpiNNakerManchester/sPyNNaker
|
b177613a114cfc7e7687ec36c1f72a2f07f66977
|
891cfb3046f66185fd8df52d270380fa94c32eab
|
refs/heads/master
| 2023-09-01T11:28:21.252266
| 2023-08-17T08:07:43
| 2023-08-17T08:07:43
| 20,801,613
| 101
| 53
|
Apache-2.0
| 2023-09-14T18:39:29
| 2014-06-13T11:07:19
|
Python
|
UTF-8
|
Python
| false
| false
| 6,512
|
py
|
abstract_pynn_model.py
|
# Copyright (c) 2017 The University of Manchester
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
from collections import defaultdict
import sys
import numpy
from pyNN import descriptions
from spinn_utilities.classproperty import classproperty
from spinn_utilities.abstract_base import (
AbstractBase, abstractmethod, abstractproperty)
from spynnaker.pyNN.models.defaults import get_dict_from_init
from spynnaker.pyNN.exceptions import SpynnakerException
class AbstractPyNNModel(object, metaclass=AbstractBase):
"""
A Model that can be passed in to a Population object in PyNN.
"""
__slots__ = []
_max_atoms_per_core = defaultdict(lambda: None)
@classmethod
def set_model_max_atoms_per_dimension_per_core(cls, n_atoms=None):
"""
Set the default maximum number of atoms per dimension per core for
this model. This can be overridden by the individual Population.
The new value can be `None`, meaning that the maximum is the same as
the number of atoms, an int, meaning all Populations of this model
must have one dimension, or a tuple of *n* integers, meaning all
Populations of this model must have *n* dimensions.
If not all Populations of this model have the same number of
dimensions, it is recommended to set this to `None` here and then
set the maximum on each Population.
:param n_atoms: The new maximum, or `None` for the largest possible
:type n_atoms: int or tuple or None
"""
abs_max = cls.absolute_max_atoms_per_core
if n_atoms is not None and numpy.prod(n_atoms) > abs_max:
raise SpynnakerException(
"The absolute maximum neurons per core for this model is"
f" {abs_max}")
AbstractPyNNModel._max_atoms_per_core[cls] = n_atoms
@classmethod
def get_model_max_atoms_per_dimension_per_core(cls):
"""
Get the maximum number of atoms per dimension per core for this model.
:rtype: int or tuple or None
"""
# If there is a stored value, use it
max_stored = AbstractPyNNModel._max_atoms_per_core.get(cls)
if max_stored is not None:
return max_stored
# Otherwise return the absolute maximum
return cls.absolute_max_atoms_per_core
@classproperty
def absolute_max_atoms_per_core(cls): # pylint: disable=no-self-argument
"""
The absolute maximum number of atoms per core.
This is an integer regardless of the number of dimensions
in any vertex.
:rtype: int
"""
return sys.maxsize
@staticmethod
def __get_init_params_and_svars(the_cls):
init = getattr(the_cls, "__init__")
while hasattr(init, "_method"):
init = getattr(init, "_method")
params = None
if hasattr(init, "_parameters"):
params = getattr(init, "_parameters")
svars = None
if hasattr(init, "_state_variables"):
svars = getattr(init, "_state_variables")
return init, params, svars
@classproperty
def default_parameters(cls): # pylint: disable=no-self-argument
"""
Get the default values for the parameters of the model.
:rtype: dict(str, Any)
"""
init, params, svars = cls.__get_init_params_and_svars(cls)
return get_dict_from_init(init, skip=svars, include=params)
@classproperty
def default_initial_values(cls): # pylint: disable=no-self-argument
"""
Get the default initial values for the state variables of the model.
:rtype: dict(str, Any)
"""
init, params, svars = cls.__get_init_params_and_svars(cls)
if params is None and svars is None:
return {}
return get_dict_from_init(init, skip=params, include=svars)
@classmethod
def get_parameter_names(cls):
"""
Get the names of the parameters of the model.
:rtype: list(str)
"""
return cls.default_parameters.keys() # pylint: disable=no-member
@classmethod
def has_parameter(cls, name):
"""
Determine if the model has a parameter with the given name.
:param str name: The name of the parameter to check for
:rtype: bool
"""
return name in cls.default_parameters
@abstractproperty
def default_population_parameters(self):
"""
The default values for the parameters at the population level.
These are parameters that can be passed in to the Population
constructor in addition to the standard PyNN options.
:rtype: dict(str, Any)
"""
@abstractmethod
def create_vertex(self, n_neurons, label):
"""
Create a vertex for a population of the model.
:param int n_neurons: The number of neurons in the population
:param str label: The label to give to the vertex
:return: An application vertex for the population
:rtype: PopulationApplicationVertex
"""
@property
def name(self):
"""
The name of this model.
:rtype: str
"""
return self.__class__.__name__
def describe(self, template='modeltype_default.txt', engine='default'):
"""
Returns a human-readable description of the population.
The output may be customized by specifying a different template
together with an associated template engine (see
:mod:`pyNN.descriptions`).
If ``template`` is ``None``, then a dictionary containing the template
context will be returned.
:param str template: Template filename
:param engine: Template substitution engine
:type engine: str or ~pyNN.descriptions.TemplateEngine or None
:rtype: str or dict
"""
context = {
"name": self.name
}
return descriptions.render(engine, template, context)
|
0c168b101f77a363498b0a3e7c9402742f0f649e
|
f305f84ea6f721c2391300f0a60e21d2ce14f2a5
|
/7_graph/带权图最短路和最小生成树/同余最短路/tempCodeRunnerFile.py
|
b311621f12501197b4b976ed42b98efbe440b5c3
|
[] |
no_license
|
981377660LMT/algorithm-study
|
f2ada3e6959338ae1bc21934a84f7314a8ecff82
|
7e79e26bb8f641868561b186e34c1127ed63c9e0
|
refs/heads/master
| 2023-09-01T18:26:16.525579
| 2023-09-01T12:21:58
| 2023-09-01T12:21:58
| 385,861,235
| 225
| 24
| null | null | null | null |
UTF-8
|
Python
| false
| false
| 59
|
py
|
tempCodeRunnerFile.py
|
# if curDist > dist[cur]:
# continue
|
0ae3ba36f9916b7219f2a9b2a030dec12012b5e9
|
9cc6f9d9eed9aceb5efa56e3b2f364900df11051
|
/improver/wxcode/modal_code.py
|
92ebe9de283d3c31bf8f049bd41ca3d32bfc690d
|
[
"BSD-3-Clause",
"LicenseRef-scancode-proprietary-license"
] |
permissive
|
metoppv/improver
|
8553a4f8b93c88291bde0db8f5dfd7b577c04b92
|
cd2c9019944345df1e703bf8f625db537ad9f559
|
refs/heads/master
| 2023-08-30T19:01:04.946698
| 2023-08-25T13:57:20
| 2023-08-25T13:57:20
| 85,334,761
| 101
| 88
|
BSD-3-Clause
| 2023-09-14T19:07:45
| 2017-03-17T16:51:29
|
Python
|
UTF-8
|
Python
| false
| false
| 11,693
|
py
|
modal_code.py
|
# -*- coding: utf-8 -*-
# -----------------------------------------------------------------------------
# (C) British Crown copyright. The Met Office.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
#
# * Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# * Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
"""Module containing a plugin to calculate the modal weather code in a period."""
from typing import Optional
import iris
import numpy as np
from iris.analysis import Aggregator
from iris.cube import Cube, CubeList
from numpy import ndarray
from scipy import stats
from improver import BasePlugin
from improver.blending import RECORD_COORD
from improver.blending.utilities import (
record_run_coord_to_attr,
store_record_run_as_coord,
)
from improver.utilities.cube_manipulation import MergeCubes
from ..metadata.forecast_times import forecast_period_coord
from .utilities import DAYNIGHT_CODES, GROUPED_CODES
CODE_MAX = 100
UNSET_CODE_INDICATOR = -99
class ModalWeatherCode(BasePlugin):
"""Plugin that returns the modal code over the period spanned by the
input data. In cases of a tie in the mode values, scipy returns the smaller
value. The opposite is desirable in this case as the significance /
importance of the weather codes generally increases with the value. To
achieve this the codes are subtracted from an arbitrarily larger
number prior to calculating the mode, and this operation reversed in the
final output.
If there are many different codes for a single point over the time
spanned by the input cubes it may be that the returned mode is not robust.
Given the preference to return more significant codes explained above,
a 12 hour period with 12 different codes, one of which is thunder, will
return a thunder code to describe the whole period. This is likely not a
good representation. In these cases grouping is used to try and select
a suitable weather code (e.g. a rain shower if the codes include a mix of
rain showers and dynamic rain) by providing a more robust mode. The lowest
number (least significant) member of the group is returned as the code.
Use of the least significant member reflects the lower certainty in the
forecasts.
Where there are different weather codes available for night and day, the
modal code returned is always a day code, regardless of the times
covered by the input files.
"""
def __init__(
self, model_id_attr: Optional[str] = None, record_run_attr: Optional[str] = None
):
"""
Set up plugin and create an aggregator instance for reuse
Args:
model_id_attr:
Name of attribute recording source models that should be
inherited by the output cube. The source models are expected as
a space-separated string.
record_run_attr:
Name of attribute used to record models and cycles used in
constructing the weather symbols.
"""
self.aggregator_instance = Aggregator("mode", self.mode_aggregator)
self.model_id_attr = model_id_attr
self.record_run_attr = record_run_attr
@staticmethod
def _unify_day_and_night(cube: Cube):
"""Remove distinction between day and night codes so they can each
contribute when calculating the modal code. The cube of weather
codes is modified in place with all night codes made into their
daytime equivalents.
Args:
A cube of weather codes.
"""
night_codes = np.array(DAYNIGHT_CODES) - 1
for code in night_codes:
cube.data[cube.data == code] += 1
@staticmethod
def _group_codes(modal: Cube, cube: Cube):
"""In instances where the mode returned is not significant, i.e. the
weather code chosen occurs infrequently in the period, the codes can be
grouped to yield a more definitive period code. Given the uncertainty,
the least significant weather type (lowest number in a group that is
found in the data) is used to replace the other data values that belong
to that group prior to recalculating the modal code.
The modal cube is modified in place.
Args:
modal:
The modal weather code cube which contains UNSET_CODE_INDICATOR
values that need to be replaced with a more definitive period
code.
cube:
The original input data. Data relating to unset points will be
grouped and the mode recalculated."""
undecided_points = np.argwhere(modal.data == UNSET_CODE_INDICATOR)
for point in undecided_points:
data = cube.data[(..., *point)].copy()
for _, codes in GROUPED_CODES.items():
default_code = sorted([code for code in data if code in codes])
if default_code:
data[np.isin(data, codes)] = default_code[0]
mode_result, counts = stats.mode(CODE_MAX - data)
modal.data[tuple(point)] = CODE_MAX - mode_result
@staticmethod
def mode_aggregator(data: ndarray, axis: int) -> ndarray:
"""An aggregator for use with iris to calculate the mode along the
specified axis. If the modal value selected comprises less than 30%
of data along the dimension being collapsed, the value is set to the
UNSET_CODE_INDICATOR to indicate that the uncertainty was too high to
return a mode.
Args:
data:
The data for which a mode is to be calculated.
axis:
The axis / dimension over which to calculate the mode.
Returns:
The data array collapsed over axis, containing the calculated modes.
"""
# Iris aggregators support indexing from the end of the array.
if axis < 0:
axis += data.ndim
# Aggregation coordinate is moved to the -1 position in initialisation;
# move this back to the leading coordinate
data = np.moveaxis(data, [axis], [0])
minimum_significant_count = 0.3 * data.shape[0]
mode_result, counts = stats.mode(CODE_MAX - data, axis=0)
mode_result[counts < minimum_significant_count] = (
CODE_MAX - UNSET_CODE_INDICATOR
)
return CODE_MAX - np.squeeze(mode_result)
@staticmethod
def _set_blended_times(cube: Cube) -> None:
"""Updates time coordinates so that time point is at the end of the time bounds,
blend_time and forecast_reference_time (if present) are set to the end of the
bound period and bounds are removed, and forecast_period is updated to match."""
cube.coord("time").points = cube.coord("time").bounds[0][-1]
for coord_name in ["blend_time", "forecast_reference_time"]:
if coord_name in [c.name() for c in cube.coords()]:
coord = cube.coord(coord_name)
if coord.has_bounds():
coord = coord.copy(coord.bounds[0][-1])
cube.replace_coord(coord)
if "forecast_period" in [c.name() for c in cube.coords()]:
calculated_coord = forecast_period_coord(
cube, force_lead_time_calculation=True
)
new_coord = cube.coord("forecast_period").copy(
points=calculated_coord.points, bounds=calculated_coord.bounds
)
cube.replace_coord(new_coord)
def process(self, cubes: CubeList) -> Cube:
"""Calculate the modal weather code, with handling for edge cases.
Args:
cubes:
A list of weather code cubes at different times. A modal
code will be calculated over the time coordinate to return
the most comon code, which is taken to be the best
representation of the whole period.
Returns:
A single weather code cube with time bounds that span those of
the input weather code cubes.
"""
# Store the information for the record_run attribute on the cubes.
if self.record_run_attr and self.model_id_attr:
store_record_run_as_coord(cubes, self.record_run_attr, self.model_id_attr)
cube = MergeCubes()(cubes)
# Create the expected cell method. The aggregator adds a cell method
# but cannot include an interval, so we create it here manually,
# ensuring to preserve any existing cell methods.
cell_methods = list(cube.cell_methods)
try:
(input_data_period,) = np.unique(np.diff(cube.coord("time").bounds)) / 3600
except ValueError as err:
raise ValueError(
"Input diagnostics do not have consistent periods."
) from err
cell_methods.append(
iris.coords.CellMethod(
"mode", coords="time", intervals=f"{int(input_data_period)} hour"
)
)
self._unify_day_and_night(cube)
# Handle case in which a single time is provided.
if len(cube.coord("time").points) == 1:
result = cube
else:
result = cube.collapsed("time", self.aggregator_instance)
self._set_blended_times(result)
result.cell_methods = None
for cell_method in cell_methods:
result.add_cell_method(cell_method)
if self.model_id_attr:
# Update contributing models
contributing_models = set()
for source_cube in cubes:
for model in source_cube.attributes[self.model_id_attr].split(" "):
contributing_models.update([model])
result.attributes[self.model_id_attr] = " ".join(
sorted(list(contributing_models))
)
if self.record_run_attr and self.model_id_attr:
record_run_coord_to_attr(
result, cube, self.record_run_attr, discard_weights=True
)
result.remove_coord(RECORD_COORD)
# Handle any unset points where it was hard to determine a suitable mode
if (result.data == UNSET_CODE_INDICATOR).any():
self._group_codes(result, cube)
return result
|
56bbe5376b21cbdc9845507e981830b73772bafd
|
5f49680d6c50d554ca25b37798bc3113f637a68c
|
/Dreamer/utils.py
|
3b7c125a5fa2c8af1309a5add5f6e7eb96bcdc1c
|
[
"MIT"
] |
permissive
|
masa-su/pixyzoo
|
ad9bd4b28dc80f26d5582129f37d4c34a9ee9312
|
1fa0d9ded00c4e10e35ed1bf99892f81e5a5e3d2
|
refs/heads/master
| 2023-01-19T06:31:40.566390
| 2023-01-10T07:18:44
| 2023-01-10T07:18:44
| 156,181,088
| 107
| 23
| null | 2023-01-10T07:18:45
| 2018-11-05T08:02:08
|
Jupyter Notebook
|
UTF-8
|
Python
| false
| false
| 7,454
|
py
|
utils.py
|
from models import ActorModel, TransitionModel
import os
import cv2
import numpy as np
import plotly
from plotly.graph_objs import Scatter
from plotly.graph_objs.scatter import Line
import torch
from torch.nn import functional as F
from typing import Iterable
from torch.nn import Module
# Plots min, max and mean + standard deviation bars of a population over time
def lineplot(xs, ys_population, title, path='', xaxis='episode'):
max_colour, mean_colour, std_colour, transparent = 'rgb(0, 132, 180)', 'rgb(0, 172, 237)', 'rgba(29, 202, 255, 0.2)', 'rgba(0, 0, 0, 0)'
if isinstance(ys_population[0], list) or isinstance(ys_population[0], tuple):
ys = np.asarray(ys_population, dtype=np.float32)
ys_min, ys_max, ys_mean, ys_std, ys_median = ys.min(1), ys.max(1), ys.mean(1), ys.std(1), np.median(ys, 1)
ys_upper, ys_lower = ys_mean + ys_std, ys_mean - ys_std
trace_max = Scatter(x=xs, y=ys_max, line=Line(color=max_colour, dash='dash'), name='Max')
trace_upper = Scatter(x=xs, y=ys_upper, line=Line(color=transparent), name='+1 Std. Dev.', showlegend=False)
trace_mean = Scatter(x=xs, y=ys_mean, fill='tonexty', fillcolor=std_colour, line=Line(color=mean_colour), name='Mean')
trace_lower = Scatter(x=xs, y=ys_lower, fill='tonexty', fillcolor=std_colour, line=Line(color=transparent), name='-1 Std. Dev.', showlegend=False)
trace_min = Scatter(x=xs, y=ys_min, line=Line(color=max_colour, dash='dash'), name='Min')
trace_median = Scatter(x=xs, y=ys_median, line=Line(color=max_colour), name='Median')
data = [trace_upper, trace_mean, trace_lower, trace_min, trace_max, trace_median]
else:
data = [Scatter(x=xs, y=ys_population, line=Line(color=mean_colour))]
plotly.offline.plot({
'data': data,
'layout': dict(title=title, xaxis={'title': xaxis}, yaxis={'title': title})
}, filename=os.path.join(path, title + '.html'), auto_open=False)
def write_video(frames, title, path=''):
frames = np.multiply(np.stack(frames, axis=0).transpose(0, 2, 3, 1), 255).clip(0, 255).astype(np.uint8)[:, :, :, ::-1] # VideoWrite expects H x W x C in BGR
_, H, W, _ = frames.shape
writer = cv2.VideoWriter(os.path.join(path, '%s.mp4' % title), cv2.VideoWriter_fourcc(*'mp4v'), 30., (W, H), True)
for frame in frames:
writer.write(frame)
writer.release()
def imagine_ahead(prev_state, prev_belief, policy: ActorModel, transition_model: TransitionModel, planning_horizon=12):
'''
imagine_ahead is the function to draw the imaginary tracjectory using the dynamics model, actor, critic.
Input: current state (posterior), current belief (hidden), policy, transition_model # torch.Size([50, 30]) torch.Size([50, 200])
Output: generated trajectory of features includes beliefs, prior_states, prior_means, prior_std_devs
torch.Size([49, 50, 200]) torch.Size([49, 50, 30]) torch.Size([49, 50, 30]) torch.Size([49, 50, 30])
'''
flatten = lambda x: x.view([-1]+list(x.size()[2:]))
prev_belief = flatten(prev_belief)
prev_state = flatten(prev_state)
# Create lists for hidden states (cannot use single tensor as buffer because autograd won't work with inplace writes)
T = planning_horizon
beliefs, prior_states, prior_means, prior_std_devs = [torch.empty(0)] * T, [torch.empty(0)] * T, [torch.empty(0)] * T, [torch.empty(0)] * T
beliefs[0], prior_states[0] = prev_belief, prev_state
# Loop over time sequence
for t in range(T - 1):
_state = prior_states[t]
actions = policy.get_action(beliefs[t].detach(), _state.detach())
# Compute belief (deterministic hidden state)
hidden = transition_model.act_fn(transition_model.fc_embed_state_action(torch.cat([_state, actions], dim=1)))
beliefs[t + 1] = transition_model.rnn(hidden, beliefs[t])
# Compute state prior by applying transition dynamics
"""
hidden = transition_model.act_fn(transition_model.fc_embed_belief_prior(beliefs[t + 1]))
prior_means[t + 1], _prior_std_dev = torch.chunk(transition_model.fc_state_prior(hidden), 2, dim=1)
"""
prior_states[t + 1] = transition_model.stochastic_state_model.sample(
{'h_t': beliefs[t + 1]}, reparam=True)['s_t']
loc_and_scale = transition_model.stochastic_state_model(h_t=beliefs[t + 1])
prior_std_devs[t + 1] = loc_and_scale['scale']
prior_means[t + 1] = loc_and_scale['loc']
# Return new hidden states
# imagined_traj = [beliefs, prior_states, prior_means, prior_std_devs]
imagined_traj = [torch.stack(beliefs[1:], dim=0), torch.stack(prior_states[1:], dim=0), torch.stack(prior_means[1:], dim=0), torch.stack(prior_std_devs[1:], dim=0)]
return imagined_traj
def lambda_return(imged_reward, value_pred, bootstrap, discount=0.99, lambda_=0.95):
# Setting lambda=1 gives a discounted Monte Carlo return.
# Setting lambda=0 gives a fixed 1-step return.
next_values = torch.cat([value_pred[1:], bootstrap[None]], 0)
discount_tensor = discount * torch.ones_like(imged_reward) #pcont
inputs = imged_reward + discount_tensor * next_values * (1 - lambda_)
last = bootstrap
indices = reversed(range(len(inputs)))
outputs = []
for index in indices:
inp, disc = inputs[index], discount_tensor[index]
last = inp + disc*lambda_*last
outputs.append(last)
outputs = list(reversed(outputs))
outputs = torch.stack(outputs, 0)
returns = outputs
return returns
class ActivateParameters:
def __init__(self, modules: Iterable[Module]):
"""
Context manager to locally Activate the gradients.
example:
```
with ActivateParameters([module]):
output_tensor = module(input_tensor)
```
:param modules: iterable of modules. used to call .parameters() to freeze gradients.
"""
self.modules = modules
self.param_states = [p.requires_grad for p in get_parameters(self.modules)]
def __enter__(self):
for param in get_parameters(self.modules):
# print(param.requires_grad)
param.requires_grad = True
def __exit__(self, exc_type, exc_val, exc_tb):
for i, param in enumerate(get_parameters(self.modules)):
param.requires_grad = self.param_states[i]
# "get_parameters" and "FreezeParameters" are from the following repo
# https://github.com/juliusfrost/dreamer-pytorch
def get_parameters(modules: Iterable[Module]):
"""
Given a list of torch modules, returns a list of their parameters.
:param modules: iterable of modules
:returns: a list of parameters
"""
model_parameters = []
for module in modules:
model_parameters += list(module.parameters())
return model_parameters
class FreezeParameters:
def __init__(self, modules: Iterable[Module]):
"""
Context manager to locally freeze gradients.
In some cases with can speed up computation because gradients aren't calculated for these listed modules.
example:
```
with FreezeParameters([module]):
output_tensor = module(input_tensor)
```
:param modules: iterable of modules. used to call .parameters() to freeze gradients.
"""
self.modules = modules
self.param_states = [p.requires_grad for p in get_parameters(self.modules)]
def __enter__(self):
for param in get_parameters(self.modules):
param.requires_grad = False
def __exit__(self, exc_type, exc_val, exc_tb):
for i, param in enumerate(get_parameters(self.modules)):
param.requires_grad = self.param_states[i]
|
5adfc9ecc4f7f38226799d5fbb687057baaa3683
|
d88458a65a173999df390117005fa813735e5fe2
|
/docs/make_doctests.py
|
779ca24d3e26c07ff96734d65df90252b97b0c03
|
[
"BSD-3-Clause"
] |
permissive
|
astropy/astroquery
|
9a2793826229ba4b41ec3607ca77832036a534e9
|
51316d7417d7daf01a8b29d1df99037b9227c2bc
|
refs/heads/main
| 2023-09-01T20:52:41.625935
| 2023-08-29T23:22:40
| 2023-08-29T23:22:40
| 4,787,269
| 636
| 365
|
BSD-3-Clause
| 2023-09-14T21:56:33
| 2012-06-25T20:52:07
|
Python
|
UTF-8
|
Python
| false
| false
| 1,222
|
py
|
make_doctests.py
|
"""
A hacktackular (tm) script for extracting runnable code from the docs and
writing them to 'doctests.py'. This was easier than figuring out how to
manipulate the doctest system to do the same thing, but it is an unsustainable
model. As such, this file should be deleted once we have functioning doctests.
"""
import os
import re
leftarrows = re.compile(r"^ *>>> ")
leftdots = re.compile(r"^ *\.\.\. ")
docskip = re.compile(r'doctest: \+SKIP')
def test_line(line):
if docskip.search(line):
return False
elif leftarrows.search(line):
return True
elif leftdots.search(line):
if line.count('...') == 1:
return True
def strip_line(line):
return leftdots.sub("", leftarrows.sub("", line))
with open('doctests.py', 'w') as doctests:
for root, dirs, files in os.walk('.'):
for fn in files:
if os.path.splitext(fn)[1] == '.rst':
with open(os.path.join(root, fn), 'r') as f:
lines = f.read().splitlines()
pylines = [strip_line(L)
for L in lines if test_line(L)]
doctests.write("# {fn}\n".format(fn=fn))
doctests.writelines(pylines)
|
8721d89aa9d533df12e6799370c742e827ad4f50
|
d95f049c5ae622790367085957d9d13a0aa85351
|
/preview_generator/preview/builder/video__ffmpeg.py
|
94d0c451b3a0789a3e37a61f3003eb02f8040f34
|
[
"MIT",
"LicenseRef-scancode-unknown-license-reference"
] |
permissive
|
algoo/preview-generator
|
42b11937723d78104b2232558bdc2e979fb4de93
|
9948f6555d827602024f98478dad8057e65aeae6
|
refs/heads/develop
| 2023-09-01T16:19:45.302197
| 2023-02-17T15:06:30
| 2023-02-17T15:06:30
| 90,982,830
| 214
| 60
|
MIT
| 2023-08-28T22:38:14
| 2017-05-11T13:33:20
|
Python
|
UTF-8
|
Python
| false
| false
| 7,058
|
py
|
video__ffmpeg.py
|
# -*- coding: utf-8 -*-
import json
from shutil import which
from subprocess import check_output
import typing
from preview_generator import utils
from preview_generator.exception import BuilderDependencyNotFound
from preview_generator.exception import PreviewGeneratorException
from preview_generator.preview.generic_preview import PreviewBuilder
ffmpeg_installed = True
try:
import ffmpeg
except ImportError:
ffmpeg_installed = False
class NoVideoStream(PreviewGeneratorException):
pass
class VideoPreviewBuilderFFMPEG(PreviewBuilder):
page_nb = 10
weight = 80
@classmethod
def get_label(cls) -> str:
return "Video files - based on ffmpeg"
@classmethod
def check_dependencies(cls) -> None:
if not ffmpeg_installed:
raise BuilderDependencyNotFound("this builder requires ffmpeg to be available")
@classmethod
def dependencies_versions(cls) -> typing.Optional[str]:
return "{} from {}".format(
check_output(["ffmpeg", "-version"], universal_newlines=True).strip().split("\n")[0],
which("ffmpeg"),
)
@classmethod
def get_supported_mimetypes(cls) -> typing.List[str]:
return [
"application/x-videolan",
"video/3gpp",
"video/annodex",
"video/dl",
"video/dv",
"video/fli",
"video/gl",
"video/mpeg",
"video/mp2t",
"video/mp4",
"video/quicktime",
"video/mp4v-es",
"video/ogg",
"video/parityfec",
"video/pointer",
"video/webm",
"video/vnd.fvt",
"video/vnd.motorola.video",
"video/vnd.motorola.videop",
"video/vnd.mpegurl",
"video/vnd.mts",
"video/vnd.nokia.interleaved-multimedia",
"video/vnd.vivo",
"video/x-flv",
"video/x-la-asf",
"video/x-mng",
"video/x-ms-asf",
"video/x-ms-wm",
"video/x-ms-wmv",
"video/x-ms-wmx",
"video/x-ms-wvx",
"video/x-msvideo",
"video/x-sgi-movie",
"video/x-matroska",
"video/x-theora+ogg",
"video/x-m4v",
]
def get_dims_from_ffmpeg_probe(
self, probe_result: typing.Dict[str, typing.Any]
) -> utils.ImgDims:
"""
Extract the width and height of the video stream from probe dict and return it
"""
video_stream_data = {} # type:typing.Dict[str,typing.Any]
for stream_data in probe_result["streams"]:
if stream_data["codec_type"] == "video":
video_stream_data = stream_data
if not video_stream_data:
raise NoVideoStream
return utils.ImgDims(width=video_stream_data["width"], height=video_stream_data["height"])
def _get_frame_time(self, page_id: int, page_nb: int, video_duration: float) -> float:
"""
Compute time of frame #page_id
The algorithm is:
- first frame is at 2%
- last frame is at 98%
- time is plitted between 2% and 98% according to the number of requested frames
- if 1 frame only, then return 2%
:param page_id: id of the page, value must be between 0 and page_nb-1. If -1, return the first frame
:param page_nb: total number of frames
:param video_duration: duration of the full video (float)
:return: the time of the requested frame
"""
if page_nb > 1:
# 100 - 4 is:
# - we take first frame at 2% of full duration
# - we take last frame at 2% of end of movie
# - we split the 96% remaining for all frames
delta_between_two_frames_in_percent = (100 - 4) / (page_nb - 1)
else:
delta_between_two_frames_in_percent = 0
return video_duration * (2 + delta_between_two_frames_in_percent * page_id) / 100
def _get_extraction_size(
self, video_dims: utils.ImgDims, preview_dims: utils.ImgDims
) -> utils.ImgDims:
"""
Compute extraction dimensions.
The extract size in order to directly get the right height or width according
to what is expected for preview
:param video_dims: ImgDims object representing width and height of the video stream
:param preview_dims: ImgDims object representing width and height of the preview to generate
:return: ImgDims to use for ffmpeg video frame extraction
"""
extract_size = utils.ImgDims(-1, -1)
if video_dims.ratio() > preview_dims.ratio():
extract_size.width = preview_dims.width
else:
extract_size.height = preview_dims.height
return extract_size
def build_jpeg_preview(
self,
file_path: str,
preview_name: str,
cache_path: str,
page_id: int,
extension: str = ".jpg",
size: utils.ImgDims = None,
mimetype: str = "",
) -> None:
"""
generate the jpeg preview
"""
if not size:
size = self.default_size
preview_path = "{path}{file_name}{extension}".format(
file_name=preview_name, path=cache_path, extension=extension
)
video_probe_data = ffmpeg.probe(file_path)
video_size = self.get_dims_from_ffmpeg_probe(video_probe_data)
extraction_size = self._get_extraction_size(video_size, size)
video_duration = float(video_probe_data["format"]["duration"])
page_nb = self.get_page_number(file_path, preview_name, cache_path)
frame_time = self._get_frame_time(page_id, page_nb, video_duration)
(
ffmpeg.input(file_path, ss=frame_time)
.filter("scale", extraction_size.width, extraction_size.height)
.output(preview_path, vframes=1)
# INFO - G.M - 2020-07-03 we do allow overwrite to allow forcing the refresh of
# the preview.
.overwrite_output()
.run()
)
def build_json_preview(
self,
file_path: str,
preview_name: str,
cache_path: str,
page_id: int = 0,
extension: str = ".json",
) -> None:
"""
generate the json preview. Default implementation is based on ExifTool
"""
metadata = ffmpeg.probe(file_path)
with open(cache_path + preview_name + extension, "w") as jsonfile:
json.dump(metadata, jsonfile)
def set_page_nb(self, page_nb: int) -> int:
"""
Allow to override default page_nb (10 by default)
"""
self.page_nb = page_nb
return self.page_nb
def get_page_number(
self,
file_path: str,
preview_name: str,
cache_path: str,
mimetype: typing.Optional[str] = None,
) -> int:
return self.page_nb
def has_jpeg_preview(self) -> bool:
return True
|
d5c65bfa440d64619925c7ff73546bfbff143c9b
|
2f7dc0184e5b4c0c15973b498c589de2d049e277
|
/pre_commit_hooks/check_executables_have_shebangs.py
|
d8e4f4901d02160e4d3af5e6a55d99932b3debc5
|
[
"MIT"
] |
permissive
|
pre-commit/pre-commit-hooks
|
178ab044f0b18893d69521f13fc6cf9a29a13a09
|
3a569ca95749f562ff8b742e3568a077caeb5eb7
|
refs/heads/main
| 2023-08-18T02:31:00.550553
| 2023-08-15T14:18:50
| 2023-08-15T14:18:50
| 17,714,713
| 4,311
| 831
|
MIT
| 2023-09-14T20:13:15
| 2014-03-13T15:21:46
|
Python
|
UTF-8
|
Python
| false
| false
| 2,427
|
py
|
check_executables_have_shebangs.py
|
"""Check that executable text files have a shebang."""
from __future__ import annotations
import argparse
import shlex
import sys
from typing import Generator
from typing import NamedTuple
from typing import Sequence
from pre_commit_hooks.util import cmd_output
from pre_commit_hooks.util import zsplit
EXECUTABLE_VALUES = frozenset(('1', '3', '5', '7'))
def check_executables(paths: list[str]) -> int:
fs_tracks_executable_bit = cmd_output(
'git', 'config', 'core.fileMode', retcode=None,
).strip()
if fs_tracks_executable_bit == 'false': # pragma: win32 cover
return _check_git_filemode(paths)
else: # pragma: win32 no cover
retv = 0
for path in paths:
if not has_shebang(path):
_message(path)
retv = 1
return retv
class GitLsFile(NamedTuple):
mode: str
filename: str
def git_ls_files(paths: Sequence[str]) -> Generator[GitLsFile, None, None]:
outs = cmd_output('git', 'ls-files', '-z', '--stage', '--', *paths)
for out in zsplit(outs):
metadata, filename = out.split('\t')
mode, _, _ = metadata.split()
yield GitLsFile(mode, filename)
def _check_git_filemode(paths: Sequence[str]) -> int:
seen: set[str] = set()
for ls_file in git_ls_files(paths):
is_executable = any(b in EXECUTABLE_VALUES for b in ls_file.mode[-3:])
if is_executable and not has_shebang(ls_file.filename):
_message(ls_file.filename)
seen.add(ls_file.filename)
return int(bool(seen))
def has_shebang(path: str) -> int:
with open(path, 'rb') as f:
first_bytes = f.read(2)
return first_bytes == b'#!'
def _message(path: str) -> None:
print(
f'{path}: marked executable but has no (or invalid) shebang!\n'
f" If it isn't supposed to be executable, try: "
f'`chmod -x {shlex.quote(path)}`\n'
f' If on Windows, you may also need to: '
f'`git add --chmod=-x {shlex.quote(path)}`\n'
f' If it is supposed to be executable, double-check its shebang.',
file=sys.stderr,
)
def main(argv: Sequence[str] | None = None) -> int:
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('filenames', nargs='*')
args = parser.parse_args(argv)
return check_executables(args.filenames)
if __name__ == '__main__':
raise SystemExit(main())
|
245e31d27a05038a0e440c0a1455a095f36e6fd7
|
c5a73b830c9441dae8d0d7e8e785bc99845061a4
|
/test/functional/__init__.py
|
249dafe09de8ea79cbb85c47e61dc337ee97c256
|
[
"Apache-2.0"
] |
permissive
|
openstack/python-swiftclient
|
9eb54c71c2ceada7347e204ec2f922884fc07f7c
|
54fbfa8bc9c10feb48fbce843d6ba6fcf6533ece
|
refs/heads/master
| 2023-08-28T15:04:16.508266
| 2023-08-25T15:56:21
| 2023-08-25T16:43:43
| 4,393,696
| 230
| 163
|
Apache-2.0
| 2021-04-30T06:12:15
| 2012-05-21T13:13:40
|
Python
|
UTF-8
|
Python
| false
| false
| 3,821
|
py
|
__init__.py
|
# Copyright (c) 2014 Christian Schwede <christian.schwede@enovance.com>
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import configparser
import os
TEST_CONFIG = None
def _load_config(force_reload=False):
global TEST_CONFIG
if not force_reload and TEST_CONFIG is not None:
return TEST_CONFIG
config_file = os.environ.get('SWIFT_TEST_CONFIG_FILE',
'/etc/swift/test.conf')
parser = configparser.ConfigParser({'auth_version': '1'})
parser.read(config_file)
conf = {}
if parser.has_section('func_test'):
if parser.has_option('func_test', 'auth_uri'):
conf['auth_url'] = parser.get('func_test', 'auth_uri')
try:
conf['auth_version'] = parser.get('func_test', 'auth_version')
except configparser.NoOptionError:
last_piece = conf['auth_url'].rstrip('/').rsplit('/', 1)[1]
if last_piece.endswith('.0'):
last_piece = last_piece[:-2]
if last_piece in ('1', '2', '3'):
conf['auth_version'] = last_piece
else:
raise
else:
auth_host = parser.get('func_test', 'auth_host')
auth_port = parser.getint('func_test', 'auth_port')
auth_ssl = parser.getboolean('func_test', 'auth_ssl')
auth_prefix = parser.get('func_test', 'auth_prefix')
conf['auth_version'] = parser.get('func_test', 'auth_version')
if auth_ssl:
auth_url = "https://"
else:
auth_url = "http://"
auth_url += "%s:%s%s" % (auth_host, auth_port, auth_prefix)
if conf['auth_version'] == "1":
auth_url += 'v1.0'
conf['auth_url'] = auth_url
try:
conf['cacert'] = parser.get('func_test', 'cacert')
except configparser.NoOptionError:
conf['cacert'] = None
try:
conf['account_username'] = parser.get('func_test',
'account_username')
except configparser.NoOptionError:
conf['account'] = parser.get('func_test', 'account')
conf['username'] = parser.get('func_test', 'username')
conf['account_username'] = "%s:%s" % (conf['account'],
conf['username'])
else:
# Still try to get separate account/usernames for keystone tests
try:
conf['account'] = parser.get('func_test', 'account')
conf['username'] = parser.get('func_test', 'username')
except configparser.NoOptionError:
pass
conf['password'] = parser.get('func_test', 'password')
# For keystone v3
try:
conf['account4'] = parser.get('func_test', 'account4')
conf['username4'] = parser.get('func_test', 'username4')
conf['domain4'] = parser.get('func_test', 'domain4')
conf['password4'] = parser.get('func_test', 'password4')
except configparser.NoOptionError:
pass
TEST_CONFIG = conf
try:
_load_config()
except configparser.NoOptionError:
TEST_CONFIG = None # sentinel used in test setup
|
393e6347fe123fcb4d1d3cf4485ccc5dc0a031ef
|
a9fdace9236af6c73133fd8dddb80843697efc7d
|
/tests/catalyst/metrics/functional/test_mrr.py
|
b0ffc18e6218f9b146dd0d53f877d2bc7fa1d878
|
[
"Apache-2.0"
] |
permissive
|
catalyst-team/catalyst
|
026c38f26dad471cd77347adbc13423b156a5d8b
|
e99f90655d0efcf22559a46e928f0f98c9807ebf
|
refs/heads/master
| 2023-08-26T23:12:49.277005
| 2022-04-29T04:19:24
| 2022-04-29T04:19:24
| 145,385,156
| 3,038
| 487
|
Apache-2.0
| 2023-08-12T03:40:14
| 2018-08-20T07:56:13
|
Python
|
UTF-8
|
Python
| false
| false
| 2,332
|
py
|
test_mrr.py
|
# flake8: noqa
import torch
from catalyst.metrics.functional._mrr import mrr, reciprocal_rank
def test_reciprocal_rank():
"""
Tests for catalyst.metrics.mrr metric.
"""
# # check 0 simple case
y_pred = [0.5, 0.2]
y_true = [1.0, 0.0]
k = 2
value = reciprocal_rank(torch.Tensor([y_pred]), torch.Tensor([y_true]), k)
assert value[0][0] == 1
# check 1 simple case
y_pred = [0.5, 0.2]
y_true = [0.0, 1.0]
k = 2
value = reciprocal_rank(torch.Tensor([y_pred]), torch.Tensor([y_true]), k)
assert value[0][0] == 0.5
# check 2 simple case
y_pred = [0.2, 0.5]
y_true = [0.0, 1.0]
k = 2
value = reciprocal_rank(torch.Tensor([y_pred]), torch.Tensor([y_true]), k)
assert value[0][0] == 1.0
# check 3 test multiple users
y_pred1 = [0.2, 0.5]
y_pred05 = [0.5, 0.2]
y_true = [0.0, 1.0]
k = 2
value = reciprocal_rank(
torch.Tensor([y_pred1, y_pred05]), torch.Tensor([y_true, y_true]), k
)
assert value[0][0] == 1.0
assert value[1][0] == 0.5
# check 4 test with k
y_pred1 = [4.0, 2.0, 3.0, 1.0]
y_pred2 = [1.0, 2.0, 3.0, 4.0]
y_true1 = [0, 0, 1.0, 1.0]
y_true2 = [0, 0, 1.0, 1.0]
k = 3
y_pred_torch = torch.Tensor([y_pred1, y_pred2])
y_true_torch = torch.Tensor([y_true1, y_true2])
value = reciprocal_rank(y_pred_torch, y_true_torch, k=k)
assert value[0][0] == 0.5
assert value[1][0] == 1.0
# check 5 test with k
y_pred1 = [4.0, 2.0, 3.0, 1.0]
y_pred2 = [1.0, 2.0, 3.0, 4.0]
y_true1 = [0, 0, 1.0, 1.0]
y_true2 = [0, 0, 1.0, 1.0]
k = 1
y_pred_torch = torch.Tensor([y_pred1, y_pred2])
y_true_torch = torch.Tensor([y_true1, y_true2])
value = reciprocal_rank(y_pred_torch, y_true_torch, k=k)
assert value[0][0] == 0.0
assert value[1][0] == 1.0
def test_mrr():
"""
Test mrr
"""
y_pred1 = [4.0, 2.0, 3.0, 1.0]
y_pred2 = [1.0, 2.0, 3.0, 4.0]
y_true1 = [0, 0, 1.0, 1.0]
y_true2 = [0, 0, 1.0, 1.0]
k_list = [1, 3]
y_pred_torch = torch.Tensor([y_pred1, y_pred2])
y_true_torch = torch.Tensor([y_true1, y_true2])
mrr_results = mrr(y_pred_torch, y_true_torch, k_list)
mrr_at1 = mrr_results[0]
mrr_at3 = mrr_results[1]
assert mrr_at1 == 0.5
assert mrr_at3 == 0.75
|
b629cd864a6a4a09c662e80aa6d339cbdb6d5e2b
|
e04a5b20f946c5033f24d4dd8acda395a98747c5
|
/clear-intermediate-datasets/python-runnables/clear_int_datasets/runnable.py
|
48d6415601683def31fa5c1ebe0d27252ce23bd8
|
[
"LicenseRef-scancode-free-unknown",
"Apache-2.0",
"BSD-2-Clause",
"MIT",
"BSD-3-Clause",
"LicenseRef-scancode-unknown-license-reference",
"LicenseRef-scancode-other-permissive"
] |
permissive
|
dataiku/dataiku-contrib
|
2a2f2fb420d7f2ab49b82d80659cc6f6ec1d8f61
|
9a9f189e8a544a81c205d8a8b3779d4517b88653
|
refs/heads/master
| 2023-09-04T03:33:58.625093
| 2023-04-26T08:17:34
| 2023-04-26T08:17:34
| 45,074,604
| 103
| 94
|
Apache-2.0
| 2023-06-08T21:29:07
| 2015-10-27T22:41:00
|
Python
|
UTF-8
|
Python
| false
| false
| 7,593
|
py
|
runnable.py
|
import dataiku
import logging
import pandas as pd
from dataiku.runnables import Runnable, ResultTable
from utils import populate_result_table_with_list, append_datasets_to_list
logging.basicConfig(format="%(asctime)s [%(levelname)s] %(message)s", level=logging.INFO)
logging.getLogger().setLevel(logging.INFO)
class MyRunnable(Runnable):
"""The base interface for a Python runnable."""
def __init__(self, project_key, config, plugin_config):
"""
:param project_key: the project in which the runnable executes
:param config: the dict of the configuration of the object
:param plugin_config: contains the plugin settings
"""
self.project_key = project_key
self.config = config
self.plugin_config = plugin_config
def get_progress_target(self):
"""
If the runnable will return some progress info, have this function return a tuple of
(target, unit) where unit is one of: SIZE, FILES, RECORDS, NONE
"""
return None
def run(self, progress_callback):
# Retrieve macro parameters:
is_dry_run = self.config.get("is_dry_run")
keep_partitioned = self.config.get("keep_partitioned")
keep_shared = self.config.get("keep_shared")
logging.info("DRY RUN is set to {}".format(str(is_dry_run)))
logging.info("KEEP PARTITIONED is set to {}".format(str(keep_partitioned)))
logging.info("KEEP SHARED is set to {}".format(str(keep_shared)))
# Initialize macro result table:
result_table = ResultTable()
result_table.add_column("dataset", "Dataset", "STRING")
result_table.add_column("type", "Type", "STRING")
result_table.add_column("action", "Action", "STRING")
result_table.add_column("action_status", "Action Status", "STRING")
action_status = "Not done (Dry run)" if is_dry_run else "Done"
client = dataiku.api_client()
if self.config.get("project_key", None):
project = client.get_project(self.config.get("project_key"))
else:
project = client.get_project(self.project_key)
manually_selected_datasets = self.config.get("datasets_to_exclude")
all_datasets = project.list_datasets()
all_recipes = project.list_recipes()
# Build deduplicated lists of input/output datasets:
input_datasets = []
output_datasets = []
for recipe in all_recipes:
recipe_inputs_dict = recipe["inputs"]
recipe_outputs_dict = recipe["outputs"]
# CASE: no input dataset
if recipe_inputs_dict:
append_datasets_to_list(recipe_inputs_dict, input_datasets)
append_datasets_to_list(recipe_outputs_dict, output_datasets)
# Identify Flow input/outputs:
flow_inputs = [dataset for dataset in input_datasets if dataset not in output_datasets]
flow_outputs = [dataset for dataset in output_datasets if dataset not in input_datasets]
logging.info("Found {} FLOW INPUT datasets: {}".format(str(len(flow_inputs)),
str(flow_inputs)))
logging.info("Found {} FLOW OUTPUT datasets: {}".format(str(len(flow_outputs)),
str(flow_outputs)))
# Identify standalone, intermediate, and partitioned datasets
excluded_datasets = []
standalone_datasets = []
intermediate_datasets = []
partitioned_datasets = []
for dataset in all_datasets:
if dataset["name"] in manually_selected_datasets:
excluded_datasets.append(dataset["name"])
if dataset["name"] not in input_datasets + output_datasets:
standalone_datasets.append(dataset["name"])
if dataset["name"] not in flow_inputs + flow_outputs + standalone_datasets:
intermediate_datasets.append(dataset["name"])
is_partitioned = lambda dataset: len(dataset["partitioning"]["dimensions"]) > 0
if is_partitioned(dataset):
partitioned_datasets.append(dataset["name"])
logging.info("Found {} EXCLUDED datasets: {}".format(str(len(excluded_datasets)),
str(excluded_datasets)))
logging.info("Found {} STANDALONE datasets: {}".format(str(len(standalone_datasets)),
str(standalone_datasets)))
logging.info("Found {} INTERMEDIATE datasets: {}".format(str(len(intermediate_datasets)),
str(intermediate_datasets)))
logging.info("Found {} PARTITIONED datasets: {}".format(str(len(partitioned_datasets)),
str(partitioned_datasets)))
# Identify shared datasets:
shared_objects = project.get_settings().settings["exposedObjects"]["objects"]
shared_datasets = [object["localName"] for object in shared_objects if object["type"]=="DATASET"]
logging.info("Found {} SHARED datasets: {}".format(str(len(shared_datasets)),
str(shared_datasets)))
# Add dataset types to results list
results = []
datasets = {
"EXCLUDED":excluded_datasets,
"STANDALONE":standalone_datasets,
"INPUT":flow_inputs,
"OUTPUT":flow_outputs,
"INTERMEDIATE": intermediate_datasets,
"SHARED": shared_datasets,
"PARTITIONED": partitioned_datasets
}
for dataset_type, dataset_type_list in datasets.items():
for dataset in dataset_type_list:
results.append([dataset, dataset_type])
# Identify which datasets should be kept
to_keep = excluded_datasets + standalone_datasets + flow_inputs + flow_outputs
if keep_partitioned:
to_keep += partitioned_datasets
if keep_shared:
to_keep += shared_datasets
logging.info("Total of {} datasets to KEEP: {}".format(str(len(to_keep)),
str(to_keep)))
# Create df with all results
results_df = pd.DataFrame(results, columns=["Dataset", "Type"])
results_grouped = results_df.groupby(["Dataset"])['Type'].apply(lambda x: ', '.join(x)).reset_index()
results_grouped["Action"] = results_grouped["Dataset"].apply(lambda x: "KEEP" if x in to_keep else "CLEAR")
results_grouped["Status"] = action_status
results_grouped = results_grouped.sort_values(by=['Action', 'Type'])
# Perform cleanup
to_clear = list(results_grouped["Dataset"][results_grouped['Action']=="CLEAR"])
logging.info("Total of {} datasets to CLEAR: {}".format(str(len(to_clear)),
str(to_clear)))
if not is_dry_run:
for ds in to_clear:
dataset = project.get_dataset(ds)
logging.info("Clearing {}...".format(ds))
dataset.clear()
logging.info("Clearing {} datasets: done.".format(str(len(to_clear))))
# Pass results to result table
for index, row in results_grouped.iterrows():
result_table.add_record(list(row))
return result_table
|
7ba43d2ef78079a19ebadf5491bf7171837091dc
|
a5a99f646e371b45974a6fb6ccc06b0a674818f2
|
/DQM/CSCMonitorModule/python/test/csc_hlt_dqm_sourceclient-file_cfg.py
|
308dbf23c98f7bb07749407e9e4568e20690d532
|
[
"Apache-2.0"
] |
permissive
|
cms-sw/cmssw
|
4ecd2c1105d59c66d385551230542c6615b9ab58
|
19c178740257eb48367778593da55dcad08b7a4f
|
refs/heads/master
| 2023-08-23T21:57:42.491143
| 2023-08-22T20:22:40
| 2023-08-22T20:22:40
| 10,969,551
| 1,006
| 3,696
|
Apache-2.0
| 2023-09-14T19:14:28
| 2013-06-26T14:09:07
|
C++
|
UTF-8
|
Python
| false
| false
| 3,225
|
py
|
csc_hlt_dqm_sourceclient-file_cfg.py
|
import FWCore.ParameterSet.Config as cms
process = cms.Process("CSC HLT DQM")
#-------------------------------------------------
# DQM Module Configuration
#-------------------------------------------------
process.load("DQM.CSCMonitorModule.csc_hlt_dqm_sourceclient_cfi")
#----------------------------
# Event Source
#-----------------------------
process.maxEvents = cms.untracked.PSet(input = cms.untracked.int32(-1))
process.source = cms.Source("PoolSource",
fileNames = cms.untracked.vstring(
'/store/data/Commissioning09/Cosmics/RAW/v1/000/079/035/422F78CA-7019-DE11-A599-001617E30CD4.root',
'/store/data/Commissioning09/Cosmics/RAW/v1/000/079/035/764D08CA-7019-DE11-813F-001617C3B69C.root',
'/store/data/Commissioning09/Cosmics/RAW/v1/000/079/035/963C5DCA-7019-DE11-9ABF-001617DBD316.root',
'/store/data/Commissioning09/Cosmics/RAW/v1/000/079/035/C882B9D5-7219-DE11-8B69-000423D6BA18.root'
#'/store/data/Commissioning08/Cosmics/RAW/v1/000/066/910/8CA64FCF-259F-DD11-B86D-000423D99BF2.root'
#'/store/data/Commissioning08/Cosmics/RAW/v1/000/066/910/8CA64FCF-259F-DD11-B86D-000423D99BF2.root'
),
#skipEvents = cms.untracked.uint32(25900)
)
#-------------------------------------------------
# Global Tag
#-------------------------------------------------
process.load("Configuration.StandardSequences.FrontierConditions_GlobalTag_cff")
#process.GlobalTag.connect = "sqlite_file:/nfshome0/malgeri/public/globtag/CRZT210_V1H.db"
#process.GlobalTag.connect = "frontier://FrontierDev/CMS_COND_CSC"
process.GlobalTag.globaltag = "CRAFT_30X::All"
process.es_prefer_GlobalTag = cms.ESPrefer('PoolDBESSource','GlobalTag')
#----------------------------
# DQM Environment
#-----------------------------
process.load("DQMServices.Core.DQM_cfg")
process.load("DQMServices.Components.DQMEnvironment_cfi")
#----------------------------
# DQM Playback Environment
#-----------------------------
process.load("DQM.Integration.test.environment_playback_cfi")
process.dqmEnv.subSystemFolder = "CSC"
process.DQM.collectorHost = 'pccmsdqm02.cern.ch'
#process.DQM.collectorHost = 'localhost'
process.dqmSaver.dirName = '.'
#--------------------------
# Message Logger
#--------------------------
MessageLogger = cms.Service("MessageLogger",
suppressInfo = cms.untracked.vstring('source'),
suppressDebug = cms.untracked.vstring('source'),
suppressWarning = cms.untracked.vstring('source'),
cout = cms.untracked.PSet(
threshold = cms.untracked.string('INFO'),
WARNING = cms.untracked.PSet(
limit = cms.untracked.int32(0)
),
noLineBreaks = cms.untracked.bool(False)
),
detailedInfo = cms.untracked.PSet(
threshold = cms.untracked.string('INFO')
),
critical = cms.untracked.PSet(
threshold = cms.untracked.string('ERROR')
),
debug = cms.untracked.PSet(
threshold = cms.untracked.string('DEBUG')
),
debugModules = cms.untracked.vstring('CSCHLTMonitormodule'),
destinations = cms.untracked.vstring(
# 'debug',
# 'detailedInfo',
# 'critical',
# 'cout'
)
)
#--------------------------
# Sequences
#--------------------------
process.p = cms.Path(process.cscDQMEvF+process.dqmEnv+process.dqmSaver)
|
60681f8e3351bb2a6dd937085b6b4f0892c2047f
|
a5a99f646e371b45974a6fb6ccc06b0a674818f2
|
/DQM/TrigXMonitorClient/python/L1TScalersClient_cfi.py
|
6a978a4adfe979f4f8c4c82db999d233ee976702
|
[
"Apache-2.0"
] |
permissive
|
cms-sw/cmssw
|
4ecd2c1105d59c66d385551230542c6615b9ab58
|
19c178740257eb48367778593da55dcad08b7a4f
|
refs/heads/master
| 2023-08-23T21:57:42.491143
| 2023-08-22T20:22:40
| 2023-08-22T20:22:40
| 10,969,551
| 1,006
| 3,696
|
Apache-2.0
| 2023-09-14T19:14:28
| 2013-06-26T14:09:07
|
C++
|
UTF-8
|
Python
| false
| false
| 249
|
py
|
L1TScalersClient_cfi.py
|
import FWCore.ParameterSet.Config as cms
l1tsClient = cms.EDAnalyzer("L1ScalersClient",
algoMonitorBits = cms.untracked.vint32(54,55,56),
techMonitorBits = cms.untracked.vint32(1,2,9),
dqmFolder = cms.untracked.string("L1T/L1Scalers_EvF")
)
|
6cbd5bcd11f53c6f1887b04b1ec043d676c82777
|
32b01231af56c01a0ed057222ede46490b1488ce
|
/amplify/agent/objects/nginx/binary.py
|
c21d48a5c9622935e4842f542a60c0ef8093873b
|
[
"BSD-2-Clause"
] |
permissive
|
nginxinc/nginx-amplify-agent
|
118478cf17ff3788e5c3d807c0f9a97a584afa65
|
f6be8cf8f8bcc61c549a821bf2aba41b2d843f18
|
refs/heads/master
| 2023-08-24T18:55:44.088497
| 2022-10-25T09:54:50
| 2022-10-25T09:54:50
| 46,153,777
| 312
| 80
|
BSD-2-Clause
| 2022-06-07T16:34:53
| 2015-11-14T00:07:42
|
Python
|
UTF-8
|
Python
| false
| false
| 5,489
|
py
|
binary.py
|
# -*- coding: utf-8 -*-
import re
from amplify.agent.common.util import subp
from amplify.agent.common.context import context
__author__ = "Mike Belov"
__copyright__ = "Copyright (C) Nginx, Inc. All rights reserved."
__license__ = ""
__maintainer__ = "Mike Belov"
__email__ = "dedm@nginx.com"
DEFAULT_PREFIX = '/usr/local/nginx'
DEFAULT_CONFPATH = 'conf/nginx.conf'
_SSL_LIB_CAPTURE_GROUPS = r'(\S+) +(\S+)(?: +(\d{1,2} +\w{3,} +\d{4}))?'
BUILT_WITH_RE = re.compile('^built with ' + _SSL_LIB_CAPTURE_GROUPS)
RUNNING_WITH_RE = re.compile('\(running with ' + _SSL_LIB_CAPTURE_GROUPS + '\)$')
RUN_WITH_RE = re.compile('^run with ' + _SSL_LIB_CAPTURE_GROUPS)
def nginx_v(bin_path):
"""
call -V and parse results
:param bin_path str - path to binary
:return {} - see result
"""
result = {
'version': None,
'plus': {'enabled': False, 'release': None},
'ssl': {'built': None, 'run': None},
'configure': {}
}
_, nginx_v_err = subp.call("%s -V" % bin_path)
for line in nginx_v_err:
# SSL stuff
try:
if line.lower().startswith('built with') and 'ssl' in line.lower():
match = BUILT_WITH_RE.search(line)
result['ssl']['built'] = list(match.groups())
# example: "built with OpenSSL 1.0.2g-fips 1 Mar 2016 (running with OpenSSL 1.0.2g 1 Mar 2016)"
match = RUNNING_WITH_RE.search(line) or match
result['ssl']['run'] = list(match.groups())
elif line.lower().startswith('run with') and 'ssl' in line.lower():
match = RUN_WITH_RE.search(line)
result['ssl']['run'] = list(match.groups())
except:
context.log.error('Failed to determine ssl library from "%s"' % line, exc_info=True)
parts = line.split(':', 1)
if len(parts) < 2:
continue
# parse version
key, value = parts
if key == 'nginx version':
# parse major version
major_parsed = re.match('.*/([\d\w\.]+)', value)
result['version'] = major_parsed.group(1) if major_parsed else value.lstrip()
# parse plus version
if 'plus' in value:
plus_parsed = re.match('.*\(([\w\-]+)\).*', value)
if plus_parsed:
result['plus']['enabled'] = True
result['plus']['release'] = plus_parsed.group(1)
# parse configure
elif key == 'configure arguments':
arguments = _parse_arguments(value)
result['configure'] = arguments
return result
def get_prefix_and_conf_path(cmd, configure=None):
"""
Finds prefix and path to config based on running cmd and optional configure args
:param running_binary_cmd: full cmd from ps
:param configure: parsed configure args from nginx -V
:return: prefix, conf_path
"""
cmd = cmd.replace('nginx: master process ', '')
params = iter(cmd.split())
# find bin path
bin_path = next(params)
prefix = None
conf_path = None
# try to find config and prefix
for param in params:
if param == '-c':
conf_path = next(params, None)
elif param == '-p':
prefix = next(params, None)
# parse nginx -V
parsed_v = nginx_v(bin_path)
if configure is None:
configure = parsed_v['configure']
# if prefix was not found in cmd - try to read it from configure args
# if there is no key "prefix" in args, then use default
if not prefix:
prefix = configure.get('prefix', DEFAULT_PREFIX)
if not conf_path:
# if there is a conf_path get it from the config file
if context.app_config.get('nginx', {}).get('configfile'):
conf_path = context.app_config['nginx']['configfile']
if not conf_path.startswith('/'):
conf_path = '/' + conf_path
# else get it from the parsed information/DEFAULT
else:
conf_path = configure.get('conf-path', DEFAULT_CONFPATH)
# remove trailing slashes from prefix
prefix = prefix.rstrip('/')
# start processing conf_path
# if it has not an absolutely path, then we should add prefix to it
if not conf_path.startswith('/'):
conf_path = '%s/%s' % (prefix, conf_path)
return bin_path, prefix, conf_path, parsed_v['version']
def _parse_arguments(argstring):
"""
Parses argstring from nginx -V
:param argstring: configure string
:return: {} of parsed string
"""
if argstring.startswith('configure arguments:'):
__, argstring = argstring.split(':', 1)
arg_parts = iter(filter(len, argstring.split(' --')))
arguments = {}
for part in arg_parts:
# if the argument is a simple switch, add it and move on
if '=' not in part:
arguments[part] = True
continue
key, value = part.split('=', 1)
# this fixes quoted argument values that broke from the ' --' split
if value.startswith("'"):
while not value.endswith("'"):
value += ' --' + next(arg_parts)
# if a key is set multiple times, values are stored as a list
if key not in arguments:
arguments[key] = value
elif not isinstance(arguments[key], list):
arguments[key] = [arguments[key], value]
else:
arguments[key].append(value)
return arguments
|
057e4498369fd941799bf4ee6cba026eea0c3cf4
|
7a6aca7d300c0752f2a73730b743a1a7361e941b
|
/tensorflow_graphics/rendering/tests/splat_with_opengl_test.py
|
45c7ec8ae4dc827fbf3ff9c5bf1b2b58bcf28ba3
|
[
"Apache-2.0"
] |
permissive
|
tensorflow/graphics
|
ef0abe102398a58eb7c41b709393df3d0b0a2811
|
1b0203eb538f2b6a1013ec7736d0d548416f059a
|
refs/heads/master
| 2023-09-03T20:41:25.992578
| 2023-08-08T21:16:36
| 2023-08-08T21:17:31
| 164,626,274
| 2,920
| 413
|
Apache-2.0
| 2023-08-27T14:26:47
| 2019-01-08T10:39:44
|
Python
|
UTF-8
|
Python
| false
| false
| 1,452
|
py
|
splat_with_opengl_test.py
|
# Copyright 2020 The TensorFlow Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""Tests for rasterize than splat functionality with opengl rasterization."""
from tensorflow_graphics.rendering import rasterization_backend
from tensorflow_graphics.rendering.tests import splat_test
from tensorflow_graphics.util import test_case
class SplatWithOpenGLTest(splat_test.SplatTest):
def setUp(self):
super().setUp()
# This pattern was chosen instead of a parametrized test to faclitate
# running the test cases in pure CPU mode on machines that do not have a
# GPU. In this case the opengl rasterizer cannot be added as dependency to
# the binary as CPU only machines do not have the required libEGL.so
# available. This pattern provides a separate build target for the opengl
# rasterizer version.
self._backend = rasterization_backend.RasterizationBackends.OPENGL
if __name__ == '__main__':
test_case.main()
|
ede4858d7711b75644a9e7487960314ae71b7464
|
2c1dc7049d820d2b75811a6c0479bd34eb84ad87
|
/test/integration/broken/test_escalation_listTemplateDomainAdmin.py
|
2148a607357f6456dfa45f3f768f9bbb6e407a9b
|
[
"Apache-2.0",
"GPL-2.0-only",
"BSD-3-Clause",
"MIT",
"GPL-1.0-or-later",
"LicenseRef-scancode-public-domain",
"BSD-2-Clause",
"LicenseRef-scancode-unknown"
] |
permissive
|
apache/cloudstack
|
3775c9171022dfaf91d655bd166149e36f4caa41
|
819dd7b75c1b61ae444c45476f5834dbfb9094d0
|
refs/heads/main
| 2023-08-30T15:05:36.976909
| 2023-08-30T09:29:16
| 2023-08-30T09:29:16
| 9,759,448
| 1,468
| 1,232
|
Apache-2.0
| 2023-09-14T16:57:46
| 2013-04-29T22:27:12
|
Java
|
UTF-8
|
Python
| false
| false
| 5,982
|
py
|
test_escalation_listTemplateDomainAdmin.py
|
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# regarding copyright ownership. The ASF licenses this file
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
from marvin.cloudstackTestCase import cloudstackTestCase
from marvin.lib.base import (Account,
Domain, Template
)
from marvin.lib.utils import (cleanup_resources, validateList)
from marvin.lib.common import (get_zone, get_builtin_template_info)
from nose.plugins.attrib import attr
from marvin.codes import PASS
import time
class TestlistTemplatesDomainAdmin(cloudstackTestCase):
@classmethod
def setUpClass(cls):
testClient = super(
TestlistTemplatesDomainAdmin, cls).getClsTestClient()
cls.apiclient = testClient.getApiClient()
cls.testdata = testClient.getParsedTestDataConfig()
cls.zone = get_zone(cls.apiclient, cls.testClient.getZoneForTests())
cls.hypervisor = cls.testClient.getHypervisorInfo()
builtin_info = get_builtin_template_info(cls.apiclient, cls.zone.id)
cls.testdata["privatetemplate"]["url"] = builtin_info[0]
cls.testdata["privatetemplate"]["hypervisor"] = builtin_info[1]
cls.testdata["privatetemplate"]["format"] = builtin_info[2]
cls.cleanup = []
# Create 2 domain admin accounts
cls.domain1 = Domain.create(
cls.apiclient,
cls.testdata["domain"])
cls.domain2 = Domain.create(
cls.apiclient,
cls.testdata["domain"])
cls.account1 = Account.create(
cls.apiclient,
cls.testdata["account"],
admin=True,
domainid=cls.domain1.id)
cls.account2 = Account.create(
cls.apiclient,
cls.testdata["account2"],
admin=True,
domainid=cls.domain2.id)
cls.debug("Created account %s in domain %s" %
(cls.account1.name, cls.domain1.id))
cls.debug("Created account %s in domain %s" %
(cls.account2.name, cls.domain2.id))
cls.cleanup.append(cls.account1)
cls.cleanup.append(cls.account2)
cls.cleanup.append(cls.domain1)
cls.cleanup.append(cls.domain2)
@classmethod
def tearDownClass(cls):
try:
# Cleanup resources used
cleanup_resources(cls.apiclient, cls.cleanup)
except Exception as e:
raise Exception("Warning: Exception during cleanup : %s" % e)
return
# test that the template register under root/domain1->account1 is not
# listed under root/domain2->account2
@attr(tags=["advanced", "basic"], required_hardware="true")
def test_listtemplate(self):
# Register template under one domain admin(root/domain1->account 1)
template_register = Template.register(
self.apiclient,
self.testdata["privatetemplate"],
zoneid=self.zone.id,
hypervisor=self.hypervisor,
account=self.account1.name,
domainid=self.domain1.id)
template_register.download(self.apiclient)
self.download(self.apiclient, template_register.id)
listtemplate = Template.list(
self.apiclient,
zoneid=self.zone.id,
hypervisor=self.hypervisor,
account=self.account2.name,
domainid=self.account2.domainid,
templatefilter="executable")
self.assertEqual(
listtemplate,
None,
"Check templates are not listed - CLOUDSTACK-10149"
)
return
def download(self, apiclient, template_id, retries=12, interval=5):
"""Check if template download will finish in 1 minute"""
while retries > -1:
time.sleep(interval)
template_response = Template.list(
apiclient,
id=template_id,
zoneid=self.zone.id,
templatefilter='self'
)
if isinstance(template_response, list):
template = template_response[0]
if not hasattr(template, 'status') or not template or not template.status:
retries = retries - 1
continue
# If template is ready,
# template.status = Download Complete
# Downloading - x% Downloaded
# if Failed
# Error - Any other string
if 'Failed' in template.status:
raise Exception(
"Failed to download template: status - %s" %
template.status)
elif template.status == 'Download Complete' and template.isready:
return
elif 'Downloaded' in template.status:
retries = retries - 1
continue
elif 'Installing' not in template.status:
if retries >= 0:
retries = retries - 1
continue
raise Exception(
"Error in downloading template: status - %s" %
template.status)
else:
retries = retries - 1
raise Exception("Template download failed exception.")
|
171c4d6dd29e8d1e6f64244cf889d13dbf2d0ca0
|
5a52ccea88f90dd4f1acc2819997fce0dd5ffb7d
|
/alipay/aop/api/response/AlipayInsSceneInsassetprodPetprofileDeleteResponse.py
|
ebbf651d408e47d03c1f546079f746b627dc962f
|
[
"Apache-2.0"
] |
permissive
|
alipay/alipay-sdk-python-all
|
8bd20882852ffeb70a6e929038bf88ff1d1eff1c
|
1fad300587c9e7e099747305ba9077d4cd7afde9
|
refs/heads/master
| 2023-08-27T21:35:01.778771
| 2023-08-23T07:12:26
| 2023-08-23T07:12:26
| 133,338,689
| 247
| 70
|
Apache-2.0
| 2023-04-25T04:54:02
| 2018-05-14T09:40:54
|
Python
|
UTF-8
|
Python
| false
| false
| 784
|
py
|
AlipayInsSceneInsassetprodPetprofileDeleteResponse.py
|
#!/usr/bin/env python
# -*- coding: utf-8 -*-
import json
from alipay.aop.api.response.AlipayResponse import AlipayResponse
class AlipayInsSceneInsassetprodPetprofileDeleteResponse(AlipayResponse):
def __init__(self):
super(AlipayInsSceneInsassetprodPetprofileDeleteResponse, self).__init__()
self._delete_flag = None
@property
def delete_flag(self):
return self._delete_flag
@delete_flag.setter
def delete_flag(self, value):
self._delete_flag = value
def parse_response_content(self, response_content):
response = super(AlipayInsSceneInsassetprodPetprofileDeleteResponse, self).parse_response_content(response_content)
if 'delete_flag' in response:
self.delete_flag = response['delete_flag']
|
1c61b5c771cdd0ec481cbab5ec423602a6e51100
|
5a52ccea88f90dd4f1acc2819997fce0dd5ffb7d
|
/alipay/aop/api/response/ZhimaCreditPeZmgoSettleApplyResponse.py
|
bd041a0c4dd7150eaff838498d9a1e3031806a78
|
[
"Apache-2.0"
] |
permissive
|
alipay/alipay-sdk-python-all
|
8bd20882852ffeb70a6e929038bf88ff1d1eff1c
|
1fad300587c9e7e099747305ba9077d4cd7afde9
|
refs/heads/master
| 2023-08-27T21:35:01.778771
| 2023-08-23T07:12:26
| 2023-08-23T07:12:26
| 133,338,689
| 247
| 70
|
Apache-2.0
| 2023-04-25T04:54:02
| 2018-05-14T09:40:54
|
Python
|
UTF-8
|
Python
| false
| false
| 2,013
|
py
|
ZhimaCreditPeZmgoSettleApplyResponse.py
|
#!/usr/bin/env python
# -*- coding: utf-8 -*-
import json
from alipay.aop.api.response.AlipayResponse import AlipayResponse
class ZhimaCreditPeZmgoSettleApplyResponse(AlipayResponse):
def __init__(self):
super(ZhimaCreditPeZmgoSettleApplyResponse, self).__init__()
self._agreement_id = None
self._fail_reason = None
self._out_request_no = None
self._settle_status = None
self._withhold_plan_no = None
@property
def agreement_id(self):
return self._agreement_id
@agreement_id.setter
def agreement_id(self, value):
self._agreement_id = value
@property
def fail_reason(self):
return self._fail_reason
@fail_reason.setter
def fail_reason(self, value):
self._fail_reason = value
@property
def out_request_no(self):
return self._out_request_no
@out_request_no.setter
def out_request_no(self, value):
self._out_request_no = value
@property
def settle_status(self):
return self._settle_status
@settle_status.setter
def settle_status(self, value):
self._settle_status = value
@property
def withhold_plan_no(self):
return self._withhold_plan_no
@withhold_plan_no.setter
def withhold_plan_no(self, value):
self._withhold_plan_no = value
def parse_response_content(self, response_content):
response = super(ZhimaCreditPeZmgoSettleApplyResponse, self).parse_response_content(response_content)
if 'agreement_id' in response:
self.agreement_id = response['agreement_id']
if 'fail_reason' in response:
self.fail_reason = response['fail_reason']
if 'out_request_no' in response:
self.out_request_no = response['out_request_no']
if 'settle_status' in response:
self.settle_status = response['settle_status']
if 'withhold_plan_no' in response:
self.withhold_plan_no = response['withhold_plan_no']
|
ad5dfe268b3c8e5d4e32df93a871d5bc62ce1c03
|
3e1f6dfde5c940f7acde208d098e56a54550945f
|
/dash_docs/reusable_components/Header.py
|
678515bb64fcee0100771b41f1991ff726b4f360
|
[
"MIT"
] |
permissive
|
plotly/dash-docs
|
a4d1b9e450aa19e811f8ae043fd56de330cce63a
|
f494e987701be1085ba9fb7b29bd875ee2146d5b
|
refs/heads/master
| 2023-08-03T02:18:16.257115
| 2021-12-14T18:51:52
| 2021-12-14T18:51:52
| 84,095,619
| 396
| 210
|
MIT
| 2023-01-18T20:29:56
| 2017-03-06T16:30:08
|
Python
|
UTF-8
|
Python
| false
| false
| 218
|
py
|
Header.py
|
import dash_html_components as html
def Header(title):
return html.Div(
style={'borderBottom': 'thin lightgrey solid', 'marginRight': 20},
children=[html.Div(title, style={'fontSize': 30})]
)
|
6af72643a1ead9b8573f7853483b831e4b61ce44
|
27b86f422246a78704e0e84983b2630533a47db6
|
/tests/test_04_dxf_high_level_structs/test_421_new_drawings.py
|
064ba62799ced0f92c0aab5e734a3df8c0b2b6de
|
[
"MIT"
] |
permissive
|
mozman/ezdxf
|
7512decd600896960660f0f580cab815bf0d7a51
|
ba6ab0264dcb6833173042a37b1b5ae878d75113
|
refs/heads/master
| 2023-09-01T11:55:13.462105
| 2023-08-15T11:50:05
| 2023-08-15T12:00:04
| 79,697,117
| 750
| 194
|
MIT
| 2023-09-14T09:40:41
| 2017-01-22T05:55:55
|
Python
|
UTF-8
|
Python
| false
| false
| 1,184
|
py
|
test_421_new_drawings.py
|
# Copyright (C) 2011-2019, Manfred Moitzi
# License: MIT License
import pytest
import ezdxf
new = ezdxf.new
def test_new_AC1009():
doc = new("R12")
assert "AC1009" == doc.dxfversion
def test_new_AC1015():
doc = new("R2000")
assert "AC1015" == doc.dxfversion
def test_new_AC1018():
doc = new("R2004")
assert "AC1018" == doc.dxfversion
def test_new_AC1021():
doc = new("R2007")
assert "AC1021" == doc.dxfversion
def test_new_AC1024():
doc = new("R2010")
assert "AC1024" == doc.dxfversion
def test_new_AC1027():
doc = new("R2013")
assert "AC1027" == doc.dxfversion
def test_new_AC1032():
doc = new("R2018")
assert "AC1032" == doc.dxfversion
def test_invalid_dxf_version():
with pytest.raises(ezdxf.const.DXFVersionError):
new("R13")
with pytest.raises(ezdxf.const.DXFVersionError):
new("R14")
with pytest.raises(ezdxf.const.DXFVersionError):
new("XYZ")
with pytest.raises(ezdxf.const.DXFVersionError):
new("AC1012")
with pytest.raises(ezdxf.const.DXFVersionError):
new("AC1013")
with pytest.raises(ezdxf.const.DXFVersionError):
new("AC1014")
|
feddb23b126242cdd230010b4a2e59d431c72962
|
eb9f655206c43c12b497c667ba56a0d358b6bc3a
|
/python/testData/refactoring/introduceVariable/multiReference.after.py
|
62256df64cd642d7b4f3a784272a640456ac972f
|
[
"Apache-2.0"
] |
permissive
|
JetBrains/intellij-community
|
2ed226e200ecc17c037dcddd4a006de56cd43941
|
05dbd4575d01a213f3f4d69aa4968473f2536142
|
refs/heads/master
| 2023-09-03T17:06:37.560889
| 2023-09-03T11:51:00
| 2023-09-03T12:12:27
| 2,489,216
| 16,288
| 6,635
|
Apache-2.0
| 2023-09-12T07:41:58
| 2011-09-30T13:33:05
| null |
UTF-8
|
Python
| false
| false
| 45
|
py
|
multiReference.after.py
|
P = {'a': 0}
M = [42]
a_ = P['a']
M[a_] += 1
|
b61da3f2ba2411cfdf5895cac0fb7e958dbc73df
|
851c22930898a3050e0881b9e9b9705d1e22849e
|
/pyrseas/dbobject/function.py
|
2356261e5b13434b18df15d4eb2a13fd0604317c
|
[
"BSD-3-Clause"
] |
permissive
|
perseas/Pyrseas
|
d54d71c3aafe70f65e38d9c568cfcd3ee9346b0b
|
ec682513d5256e383647f38f7fba29530cfb9fbe
|
refs/heads/master
| 2023-07-06T01:51:37.469775
| 2023-07-05T15:38:22
| 2023-07-05T15:43:08
| 1,546,410
| 323
| 61
|
BSD-3-Clause
| 2023-04-27T18:58:06
| 2011-03-30T14:23:28
|
Python
|
UTF-8
|
Python
| false
| false
| 29,562
|
py
|
function.py
|
# -*- coding: utf-8 -*-
"""
pyrseas.dbobject.function
~~~~~~~~~~~~~~~~~~~~~~~~~
This module defines four classes: Proc derived from
DbSchemaObject, Function and Aggregate derived from Proc, and
FunctionDict derived from DbObjectDict.
"""
from pyrseas.yamlutil import MultiLineStr
from . import DbObjectDict, DbSchemaObject
from . import commentable, ownable, grantable, split_schema_obj
VOLATILITY_TYPES = {'i': 'immutable', 's': 'stable', 'v': 'volatile'}
PARALLEL_SAFETY = {'r': 'restricted', 's': 'safe', 'u': 'unsafe'}
def split_schema_func(schema, func):
"""Split a function related to an object from its schema
:param schema: schema to which the main object belongs
:param func: possibly qualified function name
:returns: a schema, function tuple, or just the unqualified function name
"""
(sch, fnc) = split_schema_obj(func, schema)
if sch != schema:
return (sch, fnc)
else:
return fnc
def join_schema_func(func):
"""Join the schema and function, if needed, to form a qualified name
:param func: a schema, function tuple, or just an unqualified function name
:returns: a possibly-qualified schema.function string
"""
if isinstance(func, tuple):
return "%s.%s" % func
else:
return func
class Proc(DbSchemaObject):
"""A procedure such as a FUNCTION or an AGGREGATE"""
keylist = ['schema', 'name', 'arguments']
catalog = 'pg_proc'
@property
def allprivs(self):
return 'X'
def __init__(self, name, schema, description, owner, privileges,
arguments):
"""Initialize the procedure
:param name: function name (from proname)
:param schema: schema name (from pronamespace)
:param description: comment text (from obj_description())
:param owner: owner name (from rolname via proowner)
:param privileges: access privileges (from proacl)
:param arguments: argument list (without default values, from
pg_function_identity_arguments)
"""
super(Proc, self).__init__(name, schema, description)
self._init_own_privs(owner, privileges)
self.arguments = arguments
def extern_key(self):
"""Return the key to be used in external maps for this function
:return: string
"""
return '%s %s(%s)' % (self.objtype.lower(), self.name, self.arguments)
def identifier(self):
"""Return a full identifier for a function object
:return: string
"""
return "%s(%s)" % (self.qualname(), self.arguments)
def get_implied_deps(self, db):
# List the previous dependencies
deps = super(Proc, self).get_implied_deps(db)
# Add back the language
if isinstance(self, Function) and getattr(self, 'language', None):
lang = db.languages.get(self.language)
if lang:
deps.add(lang)
# Add back the types
if self.arguments:
for arg in self.arguments.split(', '):
arg = db.find_type(arg.split()[-1])
if arg is not None:
deps.add(arg)
return deps
class Function(Proc):
"""A procedural language function"""
def __init__(self, name, schema, description, owner, privileges,
arguments, language, returns, source, obj_file=None,
configuration=None, volatility=None, leakproof=False,
strict=False, security_definer=False, cost=0, rows=0,
allargs=None, oid=None):
"""Initialize the function
:param name-arguments: see Proc.__init__ params
:param language: implementation language (from prolang)
:param returns: return type (from pg_get_function_result/prorettype)
:param source: source code, link symbol, etc. (from prosrc)
:param obj_file: language-specific info (from probin)
:param configuration: configuration variables (from proconfig)
:param volatility: volatility type (from provolatile)
:param leakproof: has side effects (from proleakproof)
:param strict: null handling (from proisstrict)
:param security_definer: security definer (from prosecdef)
:param cost: execution cost estimate (from procost)
:param rows: result row estimate (from prorows)
:param allargs: argument list with defaults (from
pg_get_function_arguments)
"""
super(Function, self).__init__(
name, schema, description, owner, privileges, arguments)
self.language = language
self.returns = returns
if source and '\n' in source:
newsrc = []
for line in source.split('\n'):
if line and line[-1] in (' ', '\t'):
line = line.rstrip()
newsrc.append(line)
source = '\n'.join(newsrc)
self.source = MultiLineStr(source)
self.obj_file = obj_file
self.configuration = configuration
self.allargs = allargs
if volatility is not None:
self.volatility = volatility[:1].lower()
else:
self.volatility = 'v'
assert self.volatility in VOLATILITY_TYPES.keys()
self.leakproof = leakproof
self.strict = strict
self.security_definer = security_definer
self.cost = cost
self.rows = rows
self.oid = oid
@staticmethod
def query(dbversion=None):
query = """
SELECT nspname AS schema, proname AS name,
pg_get_function_identity_arguments(p.oid) AS arguments,
pg_get_function_arguments(p.oid) AS allargs,
pg_get_function_result(p.oid) AS returns, rolname AS owner,
array_to_string(proacl, ',') AS privileges,
l.lanname AS language, provolatile AS volatility,
proisstrict AS strict, prosrc AS source,
probin::text AS obj_file, proconfig AS configuration,
prosecdef AS security_definer, procost AS cost,
proleakproof AS leakproof, prorows::integer AS rows,
obj_description(p.oid, 'pg_proc') AS description, p.oid
FROM pg_proc p JOIN pg_roles r ON (r.oid = proowner)
JOIN pg_namespace n ON (pronamespace = n.oid)
JOIN pg_language l ON (prolang = l.oid)
WHERE (nspname != 'pg_catalog' AND nspname != 'information_schema')
AND %s
AND p.oid NOT IN (
SELECT objid FROM pg_depend WHERE deptype = 'e'
AND classid = 'pg_proc'::regclass)
ORDER BY nspname, proname"""
if dbversion < 110000:
query = query % "NOT proisagg"
else:
query = query % "prokind = 'f'"
return query
@staticmethod
def from_map(name, schema, arguments, inobj):
"""Initialize a function instance from a YAML map
:param name: function name
:param name: schema name
:param arguments: arguments
:param inobj: YAML map of the function
:return: function instance
"""
src = inobj.get('source', None)
objfile = inobj.get('obj_file', None)
if (src and objfile) or not (src or objfile):
raise ValueError("Function '%s': either source or obj_file must "
"be specified" % name)
obj = Function(
name, schema.name, inobj.pop('description', None),
inobj.pop('owner', None), inobj.pop('privileges', []),
arguments, inobj.pop('language', None),
inobj.pop('returns', None), inobj.pop('source', None),
inobj.pop('obj_file', None),
inobj.pop('configuration', None),
inobj.pop('volatility', None),
inobj.pop('leakproof', False), inobj.pop('strict', False),
inobj.pop('security_definer', False),
inobj.pop('cost', 0), inobj.pop('rows', 0),
inobj.pop('allargs', None))
obj.fix_privileges()
return obj
def to_map(self, db, no_owner, no_privs):
"""Convert a function to a YAML-suitable format
:param no_owner: exclude function owner information
:param no_privs: exclude privilege information
:return: dictionary
"""
dct = super(Function, self).to_map(db, no_owner, no_privs)
for attr in ('leakproof', 'strict', 'security_definer'):
if dct[attr] is False:
dct.pop(attr)
if self.allargs is None or len(self.allargs) == 0 or \
self.allargs == self.arguments:
dct.pop('allargs')
if self.configuration is None:
dct.pop('configuration')
if self.volatility == 'v':
dct.pop('volatility')
else:
dct['volatility'] = VOLATILITY_TYPES[self.volatility]
if self.obj_file is not None:
dct['link_symbol'] = self.source
del dct['source']
else:
del dct['obj_file']
if self.cost != 0:
if self.language in ['c', 'internal']:
if self.cost == 1:
del dct['cost']
else:
if self.cost == 100:
del dct['cost']
else:
del dct['cost']
if self.rows != 0:
if self.rows == 1000:
del dct['rows']
else:
del dct['rows']
return dct
@commentable
@grantable
@ownable
def create(self, dbversion=None, newsrc=None, basetype=False, returns=None):
"""Return SQL statements to CREATE or REPLACE the function
:param newsrc: new source for a changed function
:return: SQL statements
"""
stmts = []
if self.obj_file is not None:
src = "'%s', '%s'" % (self.obj_file,
hasattr(self, 'link_symbol') and
self.link_symbol or self.name)
elif self.language == 'internal':
src = "$$%s$$" % (newsrc or self.source)
else:
src = "$_$%s$_$" % (newsrc or self.source)
volat = leakproof = strict = secdef = cost = rows = config = ''
if self.volatility != 'v':
volat = ' ' + VOLATILITY_TYPES[self.volatility].upper()
if self.leakproof is True:
leakproof = ' LEAKPROOF'
if self.strict:
strict = ' STRICT'
if self.security_definer:
secdef = ' SECURITY DEFINER'
if self.configuration is not None:
config = ' SET %s' % self.configuration[0]
if self.cost != 0:
if self.language in ['c', 'internal']:
if self.cost != 1:
cost = " COST %s" % self.cost
else:
if self.cost != 100:
cost = " COST %s" % self.cost
if self.rows != 0:
if self.rows != 1000:
rows = " ROWS %s" % self.rows
# We may have to create a shell type if we are its input or output
# functions
t = getattr(self, '_defining', None)
if t is not None:
if not hasattr(t, '_shell_created'):
t._shell_created = True
stmts.append("CREATE TYPE %s" % t.qualname())
if self.allargs is not None:
args = self.allargs
elif self.arguments is not None:
args = self.arguments
else:
args = ''
stmts.append("CREATE%s FUNCTION %s(%s) RETURNS %s\n LANGUAGE %s"
"%s%s%s%s%s%s%s\n AS %s" % (
newsrc and " OR REPLACE" or '', self.qualname(),
args, returns or self.returns, self.language, volat, leakproof,
strict, secdef, cost, rows, config, src))
return stmts
def alter(self, infunction, dbversion=None, no_owner=False):
"""Generate SQL to transform an existing function
:param infunction: a YAML map defining the new function
:return: list of SQL statements
Compares the function to an input function and generates SQL
statements to transform it into the one represented by the
input.
"""
stmts = []
if self.source != infunction.source and infunction.source is not None:
stmts.append(self.create(
dbversion=dbversion,
returns=infunction.returns,
newsrc=infunction.source,
))
if self.leakproof is True:
if infunction.leakproof is True:
stmts.append("ALTER FUNCTION %s LEAKPROOF" % self.identifier())
else:
stmts.append("ALTER FUNCTION %s NOT LEAKPROOF"
% self.identifier())
elif infunction.leakproof is True:
stmts.append("ALTER FUNCTION %s LEAKPROOF" % self.qualname())
stmts.append(super(Function, self).alter(infunction,
no_owner=no_owner))
return stmts
def get_implied_deps(self, db):
# List the previous dependencies
deps = super(Function, self).get_implied_deps(db)
# Add back the return type
rettype = self.returns
if rettype.upper().startswith("SETOF "):
rettype = rettype.split(None, 1)[-1]
rettype = db.find_type(rettype)
if rettype is not None:
deps.add(rettype)
return deps
def get_deps(self, db):
deps = super(Function, self).get_deps(db)
# avoid circular import dependencies
from .dbtype import DbType
# drop the dependency on the type if this function is an in/out
# because there is a loop here.
for dep in list(deps):
if isinstance(dep, DbType):
for attr in ('input', 'output', 'send', 'receive'):
fname = getattr(dep, attr, None)
if isinstance(fname, tuple):
fname = "%s.%s" % fname
else:
fname = "%s.%s" % (self.schema, fname)
if fname and fname == self.qualname():
deps.remove(dep)
self._defining = dep # we may need a shell for this
break
return deps
def drop(self):
"""Generate SQL to drop the current function
:return: list of SQL statements
"""
# If the function defines a type it will be dropped by the CASCADE
# on the type.
if getattr(self, '_defining', None):
return []
else:
return super(Function, self).drop()
AGGREGATE_KINDS = {'n': 'normal', 'o': 'ordered', 'h': 'hypothetical'}
class Aggregate(Proc):
"""An aggregate function"""
def __init__(self, name, schema, description, owner, privileges,
arguments, sfunc, stype, sspace=0, finalfunc=None,
finalfunc_extra=False, initcond=None, sortop=None,
msfunc=None, minvfunc=None, mstype=None, msspace=0,
mfinalfunc=None, mfinalfunc_extra=False, minitcond=None,
kind='normal', combinefunc=None, serialfunc=None,
deserialfunc=None, parallel='unsafe',
oid=None):
"""Initialize the aggregate
:param name-arguments: see Proc.__init__ params
:param sfunc: state transition function (from aggtransfn)
:param stype: state datatype (from aggtranstype)
:param sspace: transition state data size (from aggtransspace)
:param finalfunc: final function (from aggfinalfn)
:param finalfunc_extra: extra args? (from aggfinalextra)
:param initcond: initial value (from agginitval)
:param sortop: sort operator (from aggsortop)
:param msfunc: state transition function (from aggmtransfn)
:param minvfunc: inverse transition function (from aggminvtransfn)
:param mstype: state datatype (from aggmtranstype)
:param msspace: transition state data size (from aggmtransspace)
:param mfinalfunc: final function (from aggfinalfn)
:param mfinalfunc_extra: extra args? (from aggmfinalextra)
:param minitcond: initial value (from aggminitval)
:param kind: aggregate kind (from aggkind)
:param combinefunc: combine function (from aggcombinefn)
:param serialfunc: serialization function (from aggserialfn)
:param deserialfunc: deserialization function (from aggdeserialfn)
:param parallel: parallel safety indicator (from proparallel)
"""
super(Aggregate, self).__init__(
name, schema, description, owner, privileges, arguments)
self.sfunc = split_schema_obj(sfunc, self.schema)
self.stype = self.unqualify(stype)
self.sspace = sspace
if finalfunc is not None and finalfunc != '-':
self.finalfunc = split_schema_obj(finalfunc, self.schema)
else:
self.finalfunc = None
self.finalfunc_extra = finalfunc_extra
self.initcond = initcond
self.sortop = sortop if sortop != '0' else None
if msfunc is not None and msfunc != '-':
self.msfunc = split_schema_obj(msfunc, self.schema)
else:
self.msfunc = None
if minvfunc is not None and minvfunc != '-':
self.minvfunc = split_schema_obj(minvfunc, self.schema)
else:
self.minvfunc = None
if mstype is not None and mstype != '-':
self.mstype = self.unqualify(mstype)
else:
self.mstype = None
self.msspace = msspace
if mfinalfunc is not None and mfinalfunc != '-':
self.mfinalfunc = split_schema_obj(mfinalfunc, self.schema)
else:
self.mfinalfunc = None
self.mfinalfunc_extra = mfinalfunc_extra
self.minitcond = minitcond
if kind is None:
self.kind = 'normal'
elif len(kind) == 1:
self.kind = AGGREGATE_KINDS[kind]
else:
self.kind = kind
assert self.kind in AGGREGATE_KINDS.values()
self.combinefunc = combinefunc if combinefunc != '-' else None
self.serialfunc = serialfunc if serialfunc != '-' else None
self.deserialfunc = deserialfunc if deserialfunc != '-' else None
if parallel is None:
self.parallel = 'unsafe'
elif len(parallel) == 1:
self.parallel = PARALLEL_SAFETY[parallel]
else:
self.parallel = parallel
assert self.parallel in PARALLEL_SAFETY.values()
self.oid = oid
@staticmethod
def query(dbversion):
query = """
SELECT nspname AS schema, proname AS name,
pg_get_function_identity_arguments(p.oid) AS arguments,
rolname AS owner,
array_to_string(proacl, ',') AS privileges,
aggtransfn::regproc AS sfunc,
aggtranstype::regtype AS stype, aggtransspace AS sspace,
aggfinalfn::regproc AS finalfunc,
aggfinalextra AS finalfunc_extra,
agginitval AS initcond, aggsortop::regoper AS sortop,
aggmtransfn::regproc AS msfunc,
aggminvtransfn::regproc AS minvfunc,
aggmtranstype::regtype AS mstype,
aggmtransspace AS msspace,
aggmfinalfn::regproc AS mfinalfunc,
aggmfinalextra AS mfinalfunc_extra,
aggminitval AS minitcond, aggkind AS kind,
aggcombinefn AS combinefunc,
aggserialfn AS serialfunc, aggdeserialfn AS deserialfunc,
proparallel AS parallel,%s
obj_description(p.oid, 'pg_proc') AS description, p.oid
FROM pg_proc p JOIN pg_roles r ON (r.oid = proowner)
JOIN pg_namespace n ON (pronamespace = n.oid)
LEFT JOIN pg_aggregate a ON (p.oid = aggfnoid)
WHERE (nspname != 'pg_catalog' AND nspname != 'information_schema')
%s
AND p.oid NOT IN (
SELECT objid FROM pg_depend WHERE deptype = 'e'
AND classid = 'pg_proc'::regclass)
ORDER BY nspname, proname"""
extra = ("", "")
if dbversion < 110000:
extra = (" proisagg,", "")
else:
extra = ("", "AND prokind = 'a'")
return query % extra
@staticmethod
def from_map(name, schema, arguments, inobj):
"""Initialize an aggregate instance from a YAML map
:param name: aggregate name
:param name: schema name
:param arguments: arguments
:param inobj: YAML map of the aggregate
:return: aggregate instance
"""
obj = Aggregate(
name, schema.name, inobj.pop('description', None),
inobj.pop('owner', None), inobj.pop('privileges', []),
arguments, inobj.get('sfunc'), inobj.get('stype'),
inobj.pop('sspace', 0), inobj.pop('finalfunc', None),
inobj.pop('finalfunc_extra', False), inobj.pop('initcond', None),
inobj.pop('sortop', None), inobj.pop('msfunc', None),
inobj.pop('minvfunc', None), inobj.pop('mstype', None),
inobj.pop('msspace', 0), inobj.pop('mfinalfunc', None),
inobj.pop('mfinalfunc_extra', False),
inobj.pop('minitcond', None), inobj.pop('kind', 'normal'),
inobj.pop('combinefunc', None), inobj.pop('serialfunc', None),
inobj.pop('deseriafunc', None), inobj.pop('parallel', 'unsafe'))
obj.fix_privileges()
return obj
def to_map(self, db, no_owner, no_privs):
"""Convert an aggregate to a YAML-suitable format
:param no_owner: exclude aggregate owner information
:param no_privs: exclude privilege information
:return: dictionary
"""
dct = super(Aggregate, self).to_map(db, no_owner, no_privs)
dct['sfunc'] = self.unqualify(join_schema_func(self.sfunc))
for attr in ('finalfunc', 'msfunc', 'minvfunc', 'mfinalfunc'):
if getattr(self, attr) is None:
dct.pop(attr)
else:
dct[attr] = self.unqualify(
join_schema_func(getattr(self, attr)))
for attr in ('initcond', 'sortop', 'minitcond', 'mstype',
'combinefunc', 'serialfunc', 'deserialfunc'):
if getattr(self, attr) is None:
dct.pop(attr)
for attr in ('sspace', 'msspace'):
if getattr(self, attr) == 0:
dct.pop(attr)
for attr in ('finalfunc_extra', 'mfinalfunc_extra'):
if getattr(self, attr) is False:
dct.pop(attr)
if self.kind == 'normal':
dct.pop('kind')
if self.parallel == 'unsafe':
dct.pop('parallel')
return dct
@commentable
@grantable
@ownable
def create(self, dbversion=None):
"""Return SQL statements to CREATE the aggregate
:param dbversion: Posgres version
:return: SQL statements
"""
opt_clauses = []
if self.finalfunc is not None:
opt_clauses.append("FINALFUNC = %s" %
join_schema_func(self.finalfunc))
if self.initcond is not None:
opt_clauses.append("INITCOND = '%s'" % self.initcond)
if self.combinefunc is not None:
opt_clauses.append("COMBINEFUNC = %s" % self.combinefunc)
if self.serialfunc is not None:
opt_clauses.append("SERIALFUNC = %s" % self.serialfunc)
if self.deserialfunc is not None:
opt_clauses.append("DESERIALFUNC = %s" % self.deserialfunc)
if self.sspace > 0:
opt_clauses.append("SSPACE = %d" % self.sspace)
if self.finalfunc_extra:
opt_clauses.append("FINALFUNC_EXTRA")
if self.msfunc is not None:
opt_clauses.append("MSFUNC = %s" % join_schema_func(self.msfunc))
if self.minvfunc is not None:
opt_clauses.append("MINVFUNC = %s" % join_schema_func(self.minvfunc))
if self.mstype is not None:
opt_clauses.append("MSTYPE = %s" % self.mstype)
if self.msspace > 0:
opt_clauses.append("MSSPACE = %d" % self.msspace)
if self.mfinalfunc is not None:
opt_clauses.append("MFINALFUNC = %s" %
join_schema_func(self.mfinalfunc))
if self.mfinalfunc_extra:
opt_clauses.append("MFINALFUNC_EXTRA")
if self.minitcond is not None:
opt_clauses.append("MINITCOND = '%s'" % self.minitcond)
if self.kind == 'hypothetical':
opt_clauses.append("HYPOTHETICAL")
if self.sortop is not None:
clause = self.sortop
if not clause.startswith('OPERATOR'):
clause = "OPERATOR(%s)" % clause
opt_clauses.append("SORTOP = %s" % clause)
if self.parallel != 'unsafe':
opt_clauses.append("PARALLEL = %s" % self.parallel.upper())
return ["CREATE AGGREGATE %s(%s) (\n SFUNC = %s,"
"\n STYPE = %s%s%s)" % (
self.qualname(), self.arguments,
join_schema_func(self.sfunc), self.stype,
opt_clauses and ',\n ' or '',
',\n '.join(opt_clauses))]
def get_implied_deps(self, db):
# List the previous dependencies
deps = super(Aggregate, self).get_implied_deps(db)
if isinstance(self.sfunc, tuple):
sch, fnc = self.sfunc
else:
sch, fnc = self.schema, self.sfunc
if 'ORDER BY' in self.arguments:
args = self.arguments.replace(' ORDER BY', ',')
else:
args = self.stype + ', ' + self.arguments
deps.add(db.functions[sch, fnc, args])
for fn in ('finalfunc', 'mfinalfunc'):
if getattr(self, fn) is not None:
func = getattr(self, fn)
if isinstance(func, tuple):
sch, fnc = func
else:
sch, fnc = self.schema, func
deps.add(db.functions[sch, fnc, self.mstype
if fn[0] == 'm' else self.stype])
for fn in ('msfunc', 'minvfunc'):
if getattr(self, fn) is not None:
func = getattr(self, fn)
if isinstance(func, tuple):
sch, fnc = func
else:
sch, fnc = self.schema, func
args = self.mstype + ", " + self.arguments
deps.add(db.functions[sch, fnc, args])
return deps
class ProcDict(DbObjectDict):
"The collection of regular and aggregate functions in a database"
cls = Proc
def _from_catalog(self):
"""Initialize the dictionary of procedures by querying the catalogs"""
for cls in (Function, Aggregate):
self.cls = cls
for obj in self.fetch():
self[obj.key()] = obj
self.by_oid[obj.oid] = obj
def from_map(self, schema, infuncs):
"""Initialize the dictionary of functions by converting the input map
:param schema: schema owning the functions
:param infuncs: YAML map defining the functions
"""
for key in infuncs:
(objtype, spc, fnc) = key.partition(' ')
if spc != ' ' or objtype not in ['function', 'aggregate']:
raise KeyError("Unrecognized object type: %s" % key)
paren = fnc.find('(')
if paren == -1 or fnc[-1:] != ')':
raise KeyError("Invalid function signature: %s" % fnc)
arguments = fnc[paren + 1:-1]
inobj = infuncs[key]
fnc = fnc[:paren]
if objtype == 'function':
func = Function.from_map(fnc, schema, arguments, inobj)
else:
func = Aggregate.from_map(fnc, schema, arguments, inobj)
self[(schema.name, fnc, arguments)] = func
def find(self, func, args):
"""Return a function given its name and arguments
:param func: name of the function, eventually with schema
:param args: list of type names
Return the function found, else None.
"""
schema, name = split_schema_obj(func)
args = ', '.join(args)
return self.get((schema, name, args))
def link_refs(self, dbtypes):
"""Connect the functions to other objects
- Connect defining functions to the type they define
:param dbtypes: dictionary of types
"""
# TODO: this link is needed from map, not from sql.
# is this a pattern? I was assuming link_refs would have disappeared
# but I'm actually still maintaining them. Verify if they are always
# only used for from_map, not for from_catalog
for key in dbtypes:
t = dbtypes[key]
for f in t.find_defining_funcs(self):
f._defining = t
|
23c796c4a7150b5705c3af205c5f88e7cff38b4e
|
5a52ccea88f90dd4f1acc2819997fce0dd5ffb7d
|
/alipay/aop/api/domain/TransportAuthStatusData.py
|
eb8b9c8f748599e589881ab74a9dcef8321fc653
|
[
"Apache-2.0"
] |
permissive
|
alipay/alipay-sdk-python-all
|
8bd20882852ffeb70a6e929038bf88ff1d1eff1c
|
1fad300587c9e7e099747305ba9077d4cd7afde9
|
refs/heads/master
| 2023-08-27T21:35:01.778771
| 2023-08-23T07:12:26
| 2023-08-23T07:12:26
| 133,338,689
| 247
| 70
|
Apache-2.0
| 2023-04-25T04:54:02
| 2018-05-14T09:40:54
|
Python
|
UTF-8
|
Python
| false
| false
| 2,310
|
py
|
TransportAuthStatusData.py
|
#!/usr/bin/env python
# -*- coding: utf-8 -*-
import json
from alipay.aop.api.constant.ParamConstants import *
class TransportAuthStatusData(object):
def __init__(self):
self._auth_status = None
self._auth_time = None
self._open_id = None
self._user_id = None
@property
def auth_status(self):
return self._auth_status
@auth_status.setter
def auth_status(self, value):
self._auth_status = value
@property
def auth_time(self):
return self._auth_time
@auth_time.setter
def auth_time(self, value):
self._auth_time = value
@property
def open_id(self):
return self._open_id
@open_id.setter
def open_id(self, value):
self._open_id = value
@property
def user_id(self):
return self._user_id
@user_id.setter
def user_id(self, value):
self._user_id = value
def to_alipay_dict(self):
params = dict()
if self.auth_status:
if hasattr(self.auth_status, 'to_alipay_dict'):
params['auth_status'] = self.auth_status.to_alipay_dict()
else:
params['auth_status'] = self.auth_status
if self.auth_time:
if hasattr(self.auth_time, 'to_alipay_dict'):
params['auth_time'] = self.auth_time.to_alipay_dict()
else:
params['auth_time'] = self.auth_time
if self.open_id:
if hasattr(self.open_id, 'to_alipay_dict'):
params['open_id'] = self.open_id.to_alipay_dict()
else:
params['open_id'] = self.open_id
if self.user_id:
if hasattr(self.user_id, 'to_alipay_dict'):
params['user_id'] = self.user_id.to_alipay_dict()
else:
params['user_id'] = self.user_id
return params
@staticmethod
def from_alipay_dict(d):
if not d:
return None
o = TransportAuthStatusData()
if 'auth_status' in d:
o.auth_status = d['auth_status']
if 'auth_time' in d:
o.auth_time = d['auth_time']
if 'open_id' in d:
o.open_id = d['open_id']
if 'user_id' in d:
o.user_id = d['user_id']
return o
|
f764e743c42f98ec3e6dfbad0e4775081c9d7663
|
11cd362cdd78c2fc48042ed203614b201ac94aa6
|
/apps/oozie/src/oozie/migrations/0001_initial.py
|
8a0bca70dea204ebda8d5ed1899bdb4dfa55731f
|
[
"CC-BY-3.0",
"LicenseRef-scancode-other-copyleft",
"LicenseRef-scancode-unknown-license-reference",
"ZPL-2.0",
"Unlicense",
"LGPL-3.0-only",
"CC0-1.0",
"LicenseRef-scancode-other-permissive",
"CNRI-Python",
"LicenseRef-scancode-warranty-disclaimer",
"GPL-2.0-or-later",
"Python-2.0",
"GPL-3.0-only",
"CC-BY-4.0",
"LicenseRef-scancode-jpython-1.1",
"AFL-2.1",
"JSON",
"WTFPL",
"MIT",
"LicenseRef-scancode-generic-exception",
"LicenseRef-scancode-jython",
"GPL-3.0-or-later",
"LicenseRef-scancode-python-cwi",
"BSD-3-Clause",
"LGPL-3.0-or-later",
"Zlib",
"LicenseRef-scancode-free-unknown",
"Classpath-exception-2.0",
"LicenseRef-scancode-proprietary-license",
"GPL-1.0-or-later",
"LGPL-2.0-or-later",
"MPL-2.0",
"ISC",
"GPL-2.0-only",
"ZPL-2.1",
"BSL-1.0",
"Apache-2.0",
"LGPL-2.0-only",
"LicenseRef-scancode-public-domain",
"Xnet",
"BSD-2-Clause"
] |
permissive
|
cloudera/hue
|
b42343d0e03d2936b5a9a32f8ddb3e9c5c80c908
|
dccb9467675c67b9c3399fc76c5de6d31bfb8255
|
refs/heads/master
| 2023-08-31T06:49:25.724501
| 2023-08-28T20:45:00
| 2023-08-28T20:45:00
| 732,593
| 5,655
| 2,244
|
Apache-2.0
| 2023-09-14T03:05:41
| 2010-06-21T19:46:51
|
JavaScript
|
UTF-8
|
Python
| false
| false
| 85,308
|
py
|
0001_initial.py
|
# -*- coding: utf-8 -*-
# Generated by Django 1.11 on 2018-06-06 18:55
from __future__ import unicode_literals
from django.conf import settings
import django.core.validators
from django.db import migrations, models
import django.db.models.deletion
class Migration(migrations.Migration):
initial = True
dependencies = [
migrations.swappable_dependency(settings.AUTH_USER_MODEL),
]
operations = [
migrations.CreateModel(
name='BundledCoordinator',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('parameters', models.TextField(default='[{"name":"oozie.use.system.libpath","value":"true"}]', help_text='Constants used at the submission time (e.g. market=US, oozie.use.system.libpath=true).', verbose_name='Parameters')),
],
),
migrations.CreateModel(
name='DataInput',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('name', models.CharField(help_text='The name of the variable of the workflow to automatically fill up.', max_length=40, validators=[django.core.validators.RegexValidator(message='Enter a valid value: combination of 2 - 40 letters and digits starting by a letter', regex='^[a-zA-Z_][\\-_a-zA-Z0-9]{1,39}$')], verbose_name='Name of an input variable in the workflow.')),
],
),
migrations.CreateModel(
name='DataOutput',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('name', models.CharField(help_text='The name of the variable of the workflow to automatically filled up.', max_length=40, validators=[django.core.validators.RegexValidator(message='Enter a valid value: combination of 2 - 40 letters and digits starting by a letter', regex='^[a-zA-Z_][\\-_a-zA-Z0-9]{1,39}$')], verbose_name='Name of an output variable in the workflow')),
],
),
migrations.CreateModel(
name='Dataset',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('name', models.CharField(help_text='The name of the dataset.', max_length=40, validators=[django.core.validators.RegexValidator(message='Enter a valid value: combination of 2 - 40 letters and digits starting by a letter', regex='^[a-zA-Z_][\\-_a-zA-Z0-9]{1,39}$')], verbose_name='Name')),
('description', models.CharField(blank=True, default='', help_text='A description of the dataset.', max_length=1024, verbose_name='Description')),
('start', models.DateTimeField(auto_now=True, help_text=' The UTC datetime of the initial instance of the dataset. The initial instance also provides the baseline datetime to compute instances of the dataset using multiples of the frequency.', verbose_name='Start')),
('frequency_number', models.SmallIntegerField(choices=[(1, 1), (2, 2), (3, 3), (4, 4), (5, 5), (6, 6), (7, 7), (8, 8), (9, 9), (10, 10), (11, 11), (12, 12), (13, 13), (14, 14), (15, 15), (16, 16), (17, 17), (18, 18), (19, 19), (20, 20), (21, 21), (22, 22), (23, 23), (24, 24), (25, 25), (26, 26), (27, 27), (28, 28), (29, 29), (30, 30), (31, 31), (32, 32), (33, 33), (34, 34), (35, 35), (36, 36), (37, 37), (38, 38), (39, 39), (40, 40), (41, 41), (42, 42), (43, 43), (44, 44), (45, 45), (46, 46), (47, 47), (48, 48), (49, 49), (50, 50), (51, 51), (52, 52), (53, 53), (54, 54), (55, 55), (56, 56), (57, 57), (58, 58), (59, 59), (60, 60)], default=1, help_text='The number of units of the rate at which data is periodically created.', verbose_name='Frequency number')),
('frequency_unit', models.CharField(choices=[('minutes', 'Minutes'), ('hours', 'Hours'), ('days', 'Days'), ('months', 'Months')], default='days', help_text='The unit of the rate at which data is periodically created.', max_length=20, verbose_name='Frequency unit')),
('uri', models.CharField(default='/data/${YEAR}${MONTH}${DAY}', help_text='The URI template that identifies the dataset and can be resolved into concrete URIs to identify a particular dataset instance. The URI consist of constants (e.g. ${YEAR}/${MONTH}) and configuration properties (e.g. /home/${USER}/projects/${PROJECT})', max_length=1024, verbose_name='URI')),
('timezone', models.CharField(choices=[('Africa/Abidjan', 'Africa/Abidjan'), ('Africa/Accra', 'Africa/Accra'), ('Africa/Addis_Ababa', 'Africa/Addis_Ababa'), ('Africa/Algiers', 'Africa/Algiers'), ('Africa/Asmara', 'Africa/Asmara'), ('Africa/Asmera', 'Africa/Asmera'), ('Africa/Bamako', 'Africa/Bamako'), ('Africa/Bangui', 'Africa/Bangui'), ('Africa/Banjul', 'Africa/Banjul'), ('Africa/Bissau', 'Africa/Bissau'), ('Africa/Blantyre', 'Africa/Blantyre'), ('Africa/Brazzaville', 'Africa/Brazzaville'), ('Africa/Bujumbura', 'Africa/Bujumbura'), ('Africa/Cairo', 'Africa/Cairo'), ('Africa/Casablanca', 'Africa/Casablanca'), ('Africa/Ceuta', 'Africa/Ceuta'), ('Africa/Conakry', 'Africa/Conakry'), ('Africa/Dakar', 'Africa/Dakar'), ('Africa/Dar_es_Salaam', 'Africa/Dar_es_Salaam'), ('Africa/Djibouti', 'Africa/Djibouti'), ('Africa/Douala', 'Africa/Douala'), ('Africa/El_Aaiun', 'Africa/El_Aaiun'), ('Africa/Freetown', 'Africa/Freetown'), ('Africa/Gaborone', 'Africa/Gaborone'), ('Africa/Harare', 'Africa/Harare'), ('Africa/Johannesburg', 'Africa/Johannesburg'), ('Africa/Juba', 'Africa/Juba'), ('Africa/Kampala', 'Africa/Kampala'), ('Africa/Khartoum', 'Africa/Khartoum'), ('Africa/Kigali', 'Africa/Kigali'), ('Africa/Kinshasa', 'Africa/Kinshasa'), ('Africa/Lagos', 'Africa/Lagos'), ('Africa/Libreville', 'Africa/Libreville'), ('Africa/Lome', 'Africa/Lome'), ('Africa/Luanda', 'Africa/Luanda'), ('Africa/Lubumbashi', 'Africa/Lubumbashi'), ('Africa/Lusaka', 'Africa/Lusaka'), ('Africa/Malabo', 'Africa/Malabo'), ('Africa/Maputo', 'Africa/Maputo'), ('Africa/Maseru', 'Africa/Maseru'), ('Africa/Mbabane', 'Africa/Mbabane'), ('Africa/Mogadishu', 'Africa/Mogadishu'), ('Africa/Monrovia', 'Africa/Monrovia'), ('Africa/Nairobi', 'Africa/Nairobi'), ('Africa/Ndjamena', 'Africa/Ndjamena'), ('Africa/Niamey', 'Africa/Niamey'), ('Africa/Nouakchott', 'Africa/Nouakchott'), ('Africa/Ouagadougou', 'Africa/Ouagadougou'), ('Africa/Porto-Novo', 'Africa/Porto-Novo'), ('Africa/Sao_Tome', 'Africa/Sao_Tome'), ('Africa/Timbuktu', 'Africa/Timbuktu'), ('Africa/Tripoli', 'Africa/Tripoli'), ('Africa/Tunis', 'Africa/Tunis'), ('Africa/Windhoek', 'Africa/Windhoek'), ('America/Adak', 'America/Adak'), ('America/Anchorage', 'America/Anchorage'), ('America/Anguilla', 'America/Anguilla'), ('America/Antigua', 'America/Antigua'), ('America/Araguaina', 'America/Araguaina'), ('America/Argentina/Buenos_Aires', 'America/Argentina/Buenos_Aires'), ('America/Argentina/Catamarca', 'America/Argentina/Catamarca'), ('America/Argentina/ComodRivadavia', 'America/Argentina/ComodRivadavia'), ('America/Argentina/Cordoba', 'America/Argentina/Cordoba'), ('America/Argentina/Jujuy', 'America/Argentina/Jujuy'), ('America/Argentina/La_Rioja', 'America/Argentina/La_Rioja'), ('America/Argentina/Mendoza', 'America/Argentina/Mendoza'), ('America/Argentina/Rio_Gallegos', 'America/Argentina/Rio_Gallegos'), ('America/Argentina/Salta', 'America/Argentina/Salta'), ('America/Argentina/San_Juan', 'America/Argentina/San_Juan'), ('America/Argentina/San_Luis', 'America/Argentina/San_Luis'), ('America/Argentina/Tucuman', 'America/Argentina/Tucuman'), ('America/Argentina/Ushuaia', 'America/Argentina/Ushuaia'), ('America/Aruba', 'America/Aruba'), ('America/Asuncion', 'America/Asuncion'), ('America/Atikokan', 'America/Atikokan'), ('America/Atka', 'America/Atka'), ('America/Bahia', 'America/Bahia'), ('America/Bahia_Banderas', 'America/Bahia_Banderas'), ('America/Barbados', 'America/Barbados'), ('America/Belem', 'America/Belem'), ('America/Belize', 'America/Belize'), ('America/Blanc-Sablon', 'America/Blanc-Sablon'), ('America/Boa_Vista', 'America/Boa_Vista'), ('America/Bogota', 'America/Bogota'), ('America/Boise', 'America/Boise'), ('America/Buenos_Aires', 'America/Buenos_Aires'), ('America/Cambridge_Bay', 'America/Cambridge_Bay'), ('America/Campo_Grande', 'America/Campo_Grande'), ('America/Cancun', 'America/Cancun'), ('America/Caracas', 'America/Caracas'), ('America/Catamarca', 'America/Catamarca'), ('America/Cayenne', 'America/Cayenne'), ('America/Cayman', 'America/Cayman'), ('America/Chicago', 'America/Chicago'), ('America/Chihuahua', 'America/Chihuahua'), ('America/Coral_Harbour', 'America/Coral_Harbour'), ('America/Cordoba', 'America/Cordoba'), ('America/Costa_Rica', 'America/Costa_Rica'), ('America/Creston', 'America/Creston'), ('America/Cuiaba', 'America/Cuiaba'), ('America/Curacao', 'America/Curacao'), ('America/Danmarkshavn', 'America/Danmarkshavn'), ('America/Dawson', 'America/Dawson'), ('America/Dawson_Creek', 'America/Dawson_Creek'), ('America/Denver', 'America/Denver'), ('America/Detroit', 'America/Detroit'), ('America/Dominica', 'America/Dominica'), ('America/Edmonton', 'America/Edmonton'), ('America/Eirunepe', 'America/Eirunepe'), ('America/El_Salvador', 'America/El_Salvador'), ('America/Ensenada', 'America/Ensenada'), ('America/Fort_Wayne', 'America/Fort_Wayne'), ('America/Fortaleza', 'America/Fortaleza'), ('America/Glace_Bay', 'America/Glace_Bay'), ('America/Godtha', 'America/Godtha'), ('America/Goose_Bay', 'America/Goose_Bay'), ('America/Grand_Turk', 'America/Grand_Turk'), ('America/Grenada', 'America/Grenada'), ('America/Guadeloupe', 'America/Guadeloupe'), ('America/Guatemala', 'America/Guatemala'), ('America/Guayaquil', 'America/Guayaquil'), ('America/Guyana', 'America/Guyana'), ('America/Halifax', 'America/Halifax'), ('America/Havana', 'America/Havana'), ('America/Hermosillo', 'America/Hermosillo'), ('America/Indiana/Indianapolis', 'America/Indiana/Indianapolis'), ('America/Indiana/Knox', 'America/Indiana/Knox'), ('America/Indiana/Marengo', 'America/Indiana/Marengo'), ('America/Indiana/Petersburg', 'America/Indiana/Petersburg'), ('America/Indiana/Tell_City', 'America/Indiana/Tell_City'), ('America/Indiana/Vevay', 'America/Indiana/Vevay'), ('America/Indiana/Vincennes', 'America/Indiana/Vincennes'), ('America/Indiana/Winamac', 'America/Indiana/Winamac'), ('America/Indianapolis', 'America/Indianapolis'), ('America/Inuvik', 'America/Inuvik'), ('America/Iqaluit', 'America/Iqaluit'), ('America/Jamaica', 'America/Jamaica'), ('America/Jujuy', 'America/Jujuy'), ('America/Juneau', 'America/Juneau'), ('America/Kentucky/Louisville', 'America/Kentucky/Louisville'), ('America/Kentucky/Monticello', 'America/Kentucky/Monticello'), ('America/Knox_IN', 'America/Knox_IN'), ('America/Kralendijk', 'America/Kralendijk'), ('America/La_Paz', 'America/La_Paz'), ('America/Lima', 'America/Lima'), ('America/Los_Angeles', 'America/Los_Angeles'), ('America/Louisville', 'America/Louisville'), ('America/Lower_Princes', 'America/Lower_Princes'), ('America/Maceio', 'America/Maceio'), ('America/Managua', 'America/Managua'), ('America/Manaus', 'America/Manaus'), ('America/Marigot', 'America/Marigot'), ('America/Martinique', 'America/Martinique'), ('America/Matamoros', 'America/Matamoros'), ('America/Mazatlan', 'America/Mazatlan'), ('America/Mendoza', 'America/Mendoza'), ('America/Menominee', 'America/Menominee'), ('America/Merida', 'America/Merida'), ('America/Metlakatla', 'America/Metlakatla'), ('America/Mexico_City', 'America/Mexico_City'), ('America/Miquelon', 'America/Miquelon'), ('America/Moncton', 'America/Moncton'), ('America/Monterrey', 'America/Monterrey'), ('America/Montevideo', 'America/Montevideo'), ('America/Montreal', 'America/Montreal'), ('America/Montserrat', 'America/Montserrat'), ('America/Nassau', 'America/Nassau'), ('America/New_York', 'America/New_York'), ('America/Nipigon', 'America/Nipigon'), ('America/Nome', 'America/Nome'), ('America/Noronha', 'America/Noronha'), ('America/North_Dakota/Beulah', 'America/North_Dakota/Beulah'), ('America/North_Dakota/Center', 'America/North_Dakota/Center'), ('America/North_Dakota/New_Salem', 'America/North_Dakota/New_Salem'), ('America/Ojinaga', 'America/Ojinaga'), ('America/Panama', 'America/Panama'), ('America/Pangnirtung', 'America/Pangnirtung'), ('America/Paramaribo', 'America/Paramaribo'), ('America/Phoenix', 'America/Phoenix'), ('America/Port-au-Prince', 'America/Port-au-Prince'), ('America/Port_of_Spain', 'America/Port_of_Spain'), ('America/Porto_Acre', 'America/Porto_Acre'), ('America/Porto_Velho', 'America/Porto_Velho'), ('America/Puerto_Rico', 'America/Puerto_Rico'), ('America/Rainy_River', 'America/Rainy_River'), ('America/Rankin_Inlet', 'America/Rankin_Inlet'), ('America/Recife', 'America/Recife'), ('America/Regina', 'America/Regina'), ('America/Resolute', 'America/Resolute'), ('America/Rio_Branco', 'America/Rio_Branco'), ('America/Rosario', 'America/Rosario'), ('America/Santa_Isabel', 'America/Santa_Isabel'), ('America/Santarem', 'America/Santarem'), ('America/Santiago', 'America/Santiago'), ('America/Santo_Domingo', 'America/Santo_Domingo'), ('America/Sao_Paulo', 'America/Sao_Paulo'), ('America/Scoresbysund', 'America/Scoresbysund'), ('America/Shiprock', 'America/Shiprock'), ('America/Sitka', 'America/Sitka'), ('America/St_Barthelemy', 'America/St_Barthelemy'), ('America/St_Johns', 'America/St_Johns'), ('America/St_Kitts', 'America/St_Kitts'), ('America/St_Lucia', 'America/St_Lucia'), ('America/St_Thomas', 'America/St_Thomas'), ('America/St_Vincent', 'America/St_Vincent'), ('America/Swift_Current', 'America/Swift_Current'), ('America/Tegucigalpa', 'America/Tegucigalpa'), ('America/Thule', 'America/Thule'), ('America/Thunder_Bay', 'America/Thunder_Bay'), ('America/Tijuana', 'America/Tijuana'), ('America/Toronto', 'America/Toronto'), ('America/Tortola', 'America/Tortola'), ('America/Vancouver', 'America/Vancouver'), ('America/Virgin', 'America/Virgin'), ('America/Whitehorse', 'America/Whitehorse'), ('America/Winnipeg', 'America/Winnipeg'), ('America/Yakutat', 'America/Yakutat'), ('America/Yellowknife', 'America/Yellowknife'), ('Antarctica/Casey', 'Antarctica/Casey'), ('Antarctica/Davis', 'Antarctica/Davis'), ('Antarctica/DumontDUrville', 'Antarctica/DumontDUrville'), ('Antarctica/Macquarie', 'Antarctica/Macquarie'), ('Antarctica/Mawson', 'Antarctica/Mawson'), ('Antarctica/McMurdo', 'Antarctica/McMurdo'), ('Antarctica/Palmer', 'Antarctica/Palmer'), ('Antarctica/Rothera', 'Antarctica/Rothera'), ('Antarctica/South_Pole', 'Antarctica/South_Pole'), ('Antarctica/Syowa', 'Antarctica/Syowa'), ('Antarctica/Vostok', 'Antarctica/Vostok'), ('Arctic/Longyearbyen', 'Arctic/Longyearbyen'), ('Asia/Aden', 'Asia/Aden'), ('Asia/Almaty', 'Asia/Almaty'), ('Asia/Amman', 'Asia/Amman'), ('Asia/Anadyr', 'Asia/Anadyr'), ('Asia/Aqtau', 'Asia/Aqtau'), ('Asia/Aqtobe', 'Asia/Aqtobe'), ('Asia/Ashgabat', 'Asia/Ashgabat'), ('Asia/Ashkhabad', 'Asia/Ashkhabad'), ('Asia/Baghdad', 'Asia/Baghdad'), ('Asia/Bahrain', 'Asia/Bahrain'), ('Asia/Baku', 'Asia/Baku'), ('Asia/Bangkok', 'Asia/Bangkok'), ('Asia/Beijing', 'Asia/Beijing'), ('Asia/Beirut', 'Asia/Beirut'), ('Asia/Bishkek', 'Asia/Bishkek'), ('Asia/Brunei', 'Asia/Brunei'), ('Asia/Calcutta', 'Asia/Calcutta'), ('Asia/Choibalsan', 'Asia/Choibalsan'), ('Asia/Chongqing', 'Asia/Chongqing'), ('Asia/Chungking', 'Asia/Chungking'), ('Asia/Colombo', 'Asia/Colombo'), ('Asia/Dacca', 'Asia/Dacca'), ('Asia/Damascus', 'Asia/Damascus'), ('Asia/Dhaka', 'Asia/Dhaka'), ('Asia/Dili', 'Asia/Dili'), ('Asia/Dubai', 'Asia/Dubai'), ('Asia/Dushanbe', 'Asia/Dushanbe'), ('Asia/Gaza', 'Asia/Gaza'), ('Asia/Harbin', 'Asia/Harbin'), ('Asia/Hebron', 'Asia/Hebron'), ('Asia/Ho_Chi_Minh', 'Asia/Ho_Chi_Minh'), ('Asia/Hong_Kong', 'Asia/Hong_Kong'), ('Asia/Hovd', 'Asia/Hovd'), ('Asia/Irkutsk', 'Asia/Irkutsk'), ('Asia/Istanbul', 'Asia/Istanbul'), ('Asia/Jakarta', 'Asia/Jakarta'), ('Asia/Jayapura', 'Asia/Jayapura'), ('Asia/Jerusalem', 'Asia/Jerusalem'), ('Asia/Kabul', 'Asia/Kabul'), ('Asia/Kamchatka', 'Asia/Kamchatka'), ('Asia/Karachi', 'Asia/Karachi'), ('Asia/Kashgar', 'Asia/Kashgar'), ('Asia/Kathmandu', 'Asia/Kathmandu'), ('Asia/Katmandu', 'Asia/Katmandu'), ('Asia/Kolkata', 'Asia/Kolkata'), ('Asia/Krasnoyarsk', 'Asia/Krasnoyarsk'), ('Asia/Kuala_Lumpur', 'Asia/Kuala_Lumpur'), ('Asia/Kuching', 'Asia/Kuching'), ('Asia/Kuwait', 'Asia/Kuwait'), ('Asia/Macao', 'Asia/Macao'), ('Asia/Macau', 'Asia/Macau'), ('Asia/Magadan', 'Asia/Magadan'), ('Asia/Makassar', 'Asia/Makassar'), ('Asia/Manila', 'Asia/Manila'), ('Asia/Muscat', 'Asia/Muscat'), ('Asia/Nicosia', 'Asia/Nicosia'), ('Asia/Novokuznetsk', 'Asia/Novokuznetsk'), ('Asia/Novosibirsk', 'Asia/Novosibirsk'), ('Asia/Omsk', 'Asia/Omsk'), ('Asia/Oral', 'Asia/Oral'), ('Asia/Phnom_Penh', 'Asia/Phnom_Penh'), ('Asia/Pontianak', 'Asia/Pontianak'), ('Asia/Pyongyang', 'Asia/Pyongyang'), ('Asia/Qatar', 'Asia/Qatar'), ('Asia/Qyzylorda', 'Asia/Qyzylorda'), ('Asia/Rangoon', 'Asia/Rangoon'), ('Asia/Riyadh', 'Asia/Riyadh'), ('Asia/Riyadh87', 'Asia/Riyadh87'), ('Asia/Riyadh88', 'Asia/Riyadh88'), ('Asia/Riyadh89', 'Asia/Riyadh89'), ('Asia/Saigon', 'Asia/Saigon'), ('Asia/Sakhalin', 'Asia/Sakhalin'), ('Asia/Samarkand', 'Asia/Samarkand'), ('Asia/Seoul', 'Asia/Seoul'), ('Asia/Shanghai', 'Asia/Shanghai'), ('Asia/Singapore', 'Asia/Singapore'), ('Asia/Taipei', 'Asia/Taipei'), ('Asia/Tashkent', 'Asia/Tashkent'), ('Asia/Tbilisi', 'Asia/Tbilisi'), ('Asia/Tehran', 'Asia/Tehran'), ('Asia/Tel_Aviv', 'Asia/Tel_Aviv'), ('Asia/Thimbu', 'Asia/Thimbu'), ('Asia/Thimphu', 'Asia/Thimphu'), ('Asia/Tokyo', 'Asia/Tokyo'), ('Asia/Ujung_Pandang', 'Asia/Ujung_Pandang'), ('Asia/Ulaanbaatar', 'Asia/Ulaanbaatar'), ('Asia/Ulan_Bator', 'Asia/Ulan_Bator'), ('Asia/Urumqi', 'Asia/Urumqi'), ('Asia/Vientiane', 'Asia/Vientiane'), ('Asia/Vladivostok', 'Asia/Vladivostok'), ('Asia/Yakutsk', 'Asia/Yakutsk'), ('Asia/Yekaterinburg', 'Asia/Yekaterinburg'), ('Asia/Yerevan', 'Asia/Yerevan'), ('Atlantic/Azores', 'Atlantic/Azores'), ('Atlantic/Bermuda', 'Atlantic/Bermuda'), ('Atlantic/Canary', 'Atlantic/Canary'), ('Atlantic/Cape_Verde', 'Atlantic/Cape_Verde'), ('Atlantic/Faeroe', 'Atlantic/Faeroe'), ('Atlantic/Faroe', 'Atlantic/Faroe'), ('Atlantic/Jan_Mayen', 'Atlantic/Jan_Mayen'), ('Atlantic/Madeira', 'Atlantic/Madeira'), ('Atlantic/Reykjavik', 'Atlantic/Reykjavik'), ('Atlantic/South_Georgia', 'Atlantic/South_Georgia'), ('Atlantic/St_Helena', 'Atlantic/St_Helena'), ('Atlantic/Stanley', 'Atlantic/Stanley'), ('Australia/ACT', 'Australia/ACT'), ('Australia/Adelaide', 'Australia/Adelaide'), ('Australia/Brisbane', 'Australia/Brisbane'), ('Australia/Broken_Hill', 'Australia/Broken_Hill'), ('Australia/Canberra', 'Australia/Canberra'), ('Australia/Currie', 'Australia/Currie'), ('Australia/Darwin', 'Australia/Darwin'), ('Australia/Eucla', 'Australia/Eucla'), ('Australia/Hobart', 'Australia/Hobart'), ('Australia/LHI', 'Australia/LHI'), ('Australia/Lindeman', 'Australia/Lindeman'), ('Australia/Lord_Howe', 'Australia/Lord_Howe'), ('Australia/Melbourne', 'Australia/Melbourne'), ('Australia/NSW', 'Australia/NSW'), ('Australia/North', 'Australia/North'), ('Australia/Perth', 'Australia/Perth'), ('Australia/Queensland', 'Australia/Queensland'), ('Australia/South', 'Australia/South'), ('Australia/Sydney', 'Australia/Sydney'), ('Australia/Tasmania', 'Australia/Tasmania'), ('Australia/Victoria', 'Australia/Victoria'), ('Australia/West', 'Australia/West'), ('Australia/Yancowinna', 'Australia/Yancowinna'), ('Brazil/Acre', 'Brazil/Acre'), ('Brazil/DeNoronha', 'Brazil/DeNoronha'), ('Brazil/East', 'Brazil/East'), ('Brazil/West', 'Brazil/West'), ('CET', 'CET'), ('CST6CDT', 'CST6CDT'), ('Canada/Atlantic', 'Canada/Atlantic'), ('Canada/Central', 'Canada/Central'), ('Canada/East-Saskatchewan', 'Canada/East-Saskatchewan'), ('Canada/Eastern', 'Canada/Eastern'), ('Canada/Mountain', 'Canada/Mountain'), ('Canada/Newfoundland', 'Canada/Newfoundland'), ('Canada/Pacific', 'Canada/Pacific'), ('Canada/Saskatchewan', 'Canada/Saskatchewan'), ('Canada/Yukon', 'Canada/Yukon'), ('Chile/Continental', 'Chile/Continental'), ('Chile/EasterIsland', 'Chile/EasterIsland'), ('Cuba', 'Cuba'), ('EET', 'EET'), ('EST', 'EST'), ('EST5EDT', 'EST5EDT'), ('Egypt', 'Egypt'), ('Eire', 'Eire'), ('Etc/GMT', 'Etc/GMT'), ('Etc/GMT+0', 'Etc/GMT+0'), ('Etc/GMT+1', 'Etc/GMT+1'), ('Etc/GMT+10', 'Etc/GMT+10'), ('Etc/GMT+11', 'Etc/GMT+11'), ('Etc/GMT+12', 'Etc/GMT+12'), ('Etc/GMT+2', 'Etc/GMT+2'), ('Etc/GMT+3', 'Etc/GMT+3'), ('Etc/GMT+4', 'Etc/GMT+4'), ('Etc/GMT+5', 'Etc/GMT+5'), ('Etc/GMT+6', 'Etc/GMT+6'), ('Etc/GMT+7', 'Etc/GMT+7'), ('Etc/GMT+8', 'Etc/GMT+8'), ('Etc/GMT+9', 'Etc/GMT+9'), ('Etc/GMT-0', 'Etc/GMT-0'), ('Etc/GMT-1', 'Etc/GMT-1'), ('Etc/GMT-10', 'Etc/GMT-10'), ('Etc/GMT-11', 'Etc/GMT-11'), ('Etc/GMT-12', 'Etc/GMT-12'), ('Etc/GMT-13', 'Etc/GMT-13'), ('Etc/GMT-14', 'Etc/GMT-14'), ('Etc/GMT-2', 'Etc/GMT-2'), ('Etc/GMT-3', 'Etc/GMT-3'), ('Etc/GMT-4', 'Etc/GMT-4'), ('Etc/GMT-5', 'Etc/GMT-5'), ('Etc/GMT-6', 'Etc/GMT-6'), ('Etc/GMT-7', 'Etc/GMT-7'), ('Etc/GMT-8', 'Etc/GMT-8'), ('Etc/GMT-9', 'Etc/GMT-9'), ('Etc/GMT0', 'Etc/GMT0'), ('Etc/Greenwich', 'Etc/Greenwich'), ('Etc/UCT', 'Etc/UCT'), ('Etc/UTC', 'Etc/UTC'), ('Etc/Universal', 'Etc/Universal'), ('Etc/Zulu', 'Etc/Zulu'), ('Europe/Amsterdam', 'Europe/Amsterdam'), ('Europe/Andorra', 'Europe/Andorra'), ('Europe/Athens', 'Europe/Athens'), ('Europe/Belfast', 'Europe/Belfast'), ('Europe/Belgrade', 'Europe/Belgrade'), ('Europe/Berlin', 'Europe/Berlin'), ('Europe/Bratislava', 'Europe/Bratislava'), ('Europe/Brussels', 'Europe/Brussels'), ('Europe/Bucharest', 'Europe/Bucharest'), ('Europe/Budapest', 'Europe/Budapest'), ('Europe/Chisinau', 'Europe/Chisinau'), ('Europe/Copenhagen', 'Europe/Copenhagen'), ('Europe/Dublin', 'Europe/Dublin'), ('Europe/Gibraltar', 'Europe/Gibraltar'), ('Europe/Guernsey', 'Europe/Guernsey'), ('Europe/Helsinki', 'Europe/Helsinki'), ('Europe/Isle_of_Man', 'Europe/Isle_of_Man'), ('Europe/Istanbul', 'Europe/Istanbul'), ('Europe/Jersey', 'Europe/Jersey'), ('Europe/Kaliningrad', 'Europe/Kaliningrad'), ('Europe/Kiev', 'Europe/Kiev'), ('Europe/Lisbon', 'Europe/Lisbon'), ('Europe/Ljubljana', 'Europe/Ljubljana'), ('Europe/London', 'Europe/London'), ('Europe/Luxembourg', 'Europe/Luxembourg'), ('Europe/Madrid', 'Europe/Madrid'), ('Europe/Malta', 'Europe/Malta'), ('Europe/Mariehamn', 'Europe/Mariehamn'), ('Europe/Minsk', 'Europe/Minsk'), ('Europe/Monaco', 'Europe/Monaco'), ('Europe/Moscow', 'Europe/Moscow'), ('Europe/Nicosia', 'Europe/Nicosia'), ('Europe/Oslo', 'Europe/Oslo'), ('Europe/Paris', 'Europe/Paris'), ('Europe/Podgorica', 'Europe/Podgorica'), ('Europe/Prague', 'Europe/Prague'), ('Europe/Riga', 'Europe/Riga'), ('Europe/Rome', 'Europe/Rome'), ('Europe/Samara', 'Europe/Samara'), ('Europe/San_Marino', 'Europe/San_Marino'), ('Europe/Sarajevo', 'Europe/Sarajevo'), ('Europe/Simferopol', 'Europe/Simferopol'), ('Europe/Skopje', 'Europe/Skopje'), ('Europe/Sofia', 'Europe/Sofia'), ('Europe/Stockholm', 'Europe/Stockholm'), ('Europe/Tallinn', 'Europe/Tallinn'), ('Europe/Tirane', 'Europe/Tirane'), ('Europe/Tiraspol', 'Europe/Tiraspol'), ('Europe/Uzhgorod', 'Europe/Uzhgorod'), ('Europe/Vaduz', 'Europe/Vaduz'), ('Europe/Vatican', 'Europe/Vatican'), ('Europe/Vienna', 'Europe/Vienna'), ('Europe/Vilnius', 'Europe/Vilnius'), ('Europe/Volgograd', 'Europe/Volgograd'), ('Europe/Warsaw', 'Europe/Warsaw'), ('Europe/Zagre', 'Europe/Zagre'), ('Europe/Zaporozhye', 'Europe/Zaporozhye'), ('Europe/Zurich', 'Europe/Zurich'), ('Factory', 'Factory'), ('G', 'G'), ('GB-Eire', 'GB-Eire'), ('GMT', 'GMT'), ('GMT+0', 'GMT+0'), ('GMT+1', 'GMT+1'), ('GMT+10', 'GMT+10'), ('GMT+11', 'GMT+11'), ('GMT+12', 'GMT+12'), ('GMT+13', 'GMT+13'), ('GMT+14', 'GMT+14'), ('GMT+2', 'GMT+2'), ('GMT+3', 'GMT+3'), ('GMT+4', 'GMT+4'), ('GMT+5', 'GMT+5'), ('GMT+6', 'GMT+6'), ('GMT+7', 'GMT+7'), ('GMT+8', 'GMT+8'), ('GMT+9', 'GMT+9'), ('GMT-0', 'GMT-0'), ('GMT-1', 'GMT-1'), ('GMT-10', 'GMT-10'), ('GMT-11', 'GMT-11'), ('GMT-12', 'GMT-12'), ('GMT-2', 'GMT-2'), ('GMT-3', 'GMT-3'), ('GMT-4', 'GMT-4'), ('GMT-5', 'GMT-5'), ('GMT-6', 'GMT-6'), ('GMT-7', 'GMT-7'), ('GMT-8', 'GMT-8'), ('GMT-9', 'GMT-9'), ('GMT0', 'GMT0'), ('Greenwich', 'Greenwich'), ('HST', 'HST'), ('Hongkong', 'Hongkong'), ('Iceland', 'Iceland'), ('Indian/Antananarivo', 'Indian/Antananarivo'), ('Indian/Chagos', 'Indian/Chagos'), ('Indian/Christmas', 'Indian/Christmas'), ('Indian/Cocos', 'Indian/Cocos'), ('Indian/Comoro', 'Indian/Comoro'), ('Indian/Kerguelen', 'Indian/Kerguelen'), ('Indian/Mahe', 'Indian/Mahe'), ('Indian/Maldives', 'Indian/Maldives'), ('Indian/Mauritius', 'Indian/Mauritius'), ('Indian/Mayotte', 'Indian/Mayotte'), ('Indian/Reunion', 'Indian/Reunion'), ('Iran', 'Iran'), ('Israel', 'Israel'), ('Jamaica', 'Jamaica'), ('Japan', 'Japan'), ('Kwajalein', 'Kwajalein'), ('Libya', 'Libya'), ('MET', 'MET'), ('MST', 'MST'), ('MST7MDT', 'MST7MDT'), ('Mexico/BajaNorte', 'Mexico/BajaNorte'), ('Mexico/BajaSur', 'Mexico/BajaSur'), ('Mexico/General', 'Mexico/General'), ('Mideast/Riyadh87', 'Mideast/Riyadh87'), ('Mideast/Riyadh88', 'Mideast/Riyadh88'), ('Mideast/Riyadh89', 'Mideast/Riyadh89'), ('NZ', 'NZ'), ('NZ-CHAT', 'NZ-CHAT'), ('Navajo', 'Navajo'), ('PRC', 'PRC'), ('PST8PDT', 'PST8PDT'), ('Pacific/Apia', 'Pacific/Apia'), ('Pacific/Auckland', 'Pacific/Auckland'), ('Pacific/Chatham', 'Pacific/Chatham'), ('Pacific/Chuuk', 'Pacific/Chuuk'), ('Pacific/Easter', 'Pacific/Easter'), ('Pacific/Efate', 'Pacific/Efate'), ('Pacific/Enderbury', 'Pacific/Enderbury'), ('Pacific/Fakaofo', 'Pacific/Fakaofo'), ('Pacific/Fiji', 'Pacific/Fiji'), ('Pacific/Funafuti', 'Pacific/Funafuti'), ('Pacific/Galapagos', 'Pacific/Galapagos'), ('Pacific/Gambier', 'Pacific/Gambier'), ('Pacific/Guadalcanal', 'Pacific/Guadalcanal'), ('Pacific/Guam', 'Pacific/Guam'), ('Pacific/Honolulu', 'Pacific/Honolulu'), ('Pacific/Johnston', 'Pacific/Johnston'), ('Pacific/Kiritimati', 'Pacific/Kiritimati'), ('Pacific/Kosrae', 'Pacific/Kosrae'), ('Pacific/Kwajalein', 'Pacific/Kwajalein'), ('Pacific/Majuro', 'Pacific/Majuro'), ('Pacific/Marquesas', 'Pacific/Marquesas'), ('Pacific/Midway', 'Pacific/Midway'), ('Pacific/Nauru', 'Pacific/Nauru'), ('Pacific/Niue', 'Pacific/Niue'), ('Pacific/Norfolk', 'Pacific/Norfolk'), ('Pacific/Noumea', 'Pacific/Noumea'), ('Pacific/Pago_Pago', 'Pacific/Pago_Pago'), ('Pacific/Palau', 'Pacific/Palau'), ('Pacific/Pitcairn', 'Pacific/Pitcairn'), ('Pacific/Pohnpei', 'Pacific/Pohnpei'), ('Pacific/Ponape', 'Pacific/Ponape'), ('Pacific/Port_Moresby', 'Pacific/Port_Moresby'), ('Pacific/Rarotonga', 'Pacific/Rarotonga'), ('Pacific/Saipan', 'Pacific/Saipan'), ('Pacific/Samoa', 'Pacific/Samoa'), ('Pacific/Tahiti', 'Pacific/Tahiti'), ('Pacific/Tarawa', 'Pacific/Tarawa'), ('Pacific/Tongatapu', 'Pacific/Tongatapu'), ('Pacific/Truk', 'Pacific/Truk'), ('Pacific/Wake', 'Pacific/Wake'), ('Pacific/Wallis', 'Pacific/Wallis'), ('Pacific/Yap', 'Pacific/Yap'), ('Poland', 'Poland'), ('Portugal', 'Portugal'), ('ROC', 'ROC'), ('ROK', 'ROK'), ('Singapore', 'Singapore'), ('Turkey', 'Turkey'), ('UCT', 'UCT'), ('US/Alaska', 'US/Alaska'), ('US/Aleutian', 'US/Aleutian'), ('US/Arizona', 'US/Arizona'), ('US/Central', 'US/Central'), ('US/East-Indiana', 'US/East-Indiana'), ('US/Eastern', 'US/Eastern'), ('US/Hawaii', 'US/Hawaii'), ('US/Indiana-Starke', 'US/Indiana-Starke'), ('US/Michigan', 'US/Michigan'), ('US/Mountain', 'US/Mountain'), ('US/Pacific', 'US/Pacific'), ('US/Pacific-New', 'US/Pacific-New'), ('US/Samoa', 'US/Samoa'), ('Universal', 'Universal'), ('W-SU', 'W-SU'), ('WET', 'WET'), ('Zulu', 'Zulu')], default='America/Los_Angeles', help_text='The timezone of the dataset. Only used for managing the daylight saving time changes when combining several datasets.', max_length=24, verbose_name='Timezone')),
('done_flag', models.CharField(blank=True, default='', help_text='The done file for the data set. If the Done flag is not specified, then Oozie configures Hadoop to create a _SUCCESS file in the output directory. If Done flag is set to empty, then Coordinator looks for the existence of the directory itself.', max_length=64, verbose_name='Done flag')),
('instance_choice', models.CharField(default='default', help_text='Customize the date instance(s), e.g. define a range of dates, use EL functions...', max_length=10, verbose_name='Instance type')),
('advanced_start_instance', models.CharField(default='0', help_text='Shift the frequency for gettting past/future start date or enter verbatim the Oozie start instance, e.g. ${coord:current(0)}', max_length=128, verbose_name='Start instance')),
('advanced_end_instance', models.CharField(blank=True, default='0', help_text='Optional: Shift the frequency for gettting past/future end dates or enter verbatim the Oozie end instance.', max_length=128, verbose_name='End instance')),
],
),
migrations.CreateModel(
name='History',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('submission_date', models.DateTimeField(auto_now=True, db_index=True)),
('oozie_job_id', models.CharField(max_length=128)),
('properties', models.TextField()),
],
),
migrations.CreateModel(
name='Job',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('name', models.CharField(help_text='Name of the job, which must be unique per user.', max_length=255, validators=[django.core.validators.RegexValidator(message='Enter a valid value: combination of 2 - 40 letters and digits starting by a letter', regex='^[a-zA-Z_][\\-_a-zA-Z0-9]{1,39}$')], verbose_name='Name')),
('description', models.CharField(blank=True, help_text='The purpose of the job.', max_length=1024, verbose_name='Description')),
('last_modified', models.DateTimeField(auto_now=True, db_index=True, verbose_name='Last modified')),
('schema_version', models.CharField(help_text='The version of the XML schema used to talk to Oozie.', max_length=128, verbose_name='Schema version')),
('deployment_dir', models.CharField(blank=True, help_text='The path on the HDFS where all the workflows and dependencies must be uploaded.', max_length=1024, verbose_name='HDFS deployment directory')),
('is_shared', models.BooleanField(db_index=True, default=False, help_text='Enable other users to have access to this job.', verbose_name='Is shared')),
('parameters', models.TextField(default='[{"name":"oozie.use.system.libpath","value":"true"}]', help_text='Parameters used at the submission time (e.g. market=US, oozie.use.system.libpath=true).', verbose_name='Oozie parameters')),
('is_trashed', models.BooleanField(db_index=True, default=False, help_text='If this job is trashed.', verbose_name='Is trashed')),
('data', models.TextField(blank=True, default='{}')),
],
),
migrations.CreateModel(
name='Link',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('name', models.CharField(max_length=40)),
('comment', models.CharField(blank=True, default='', max_length=1024)),
],
),
migrations.CreateModel(
name='Node',
fields=[
('id', models.AutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')),
('name', models.CharField(help_text='Name of the action, which must be unique by workflow.', max_length=255, validators=[django.core.validators.RegexValidator(message='Enter a valid value: combination of 2 - 40 letters and digits starting by a letter', regex='^[a-zA-Z_][\\-_a-zA-Z0-9]{1,39}$')], verbose_name='Name')),
('description', models.CharField(blank=True, default='', help_text='The purpose of the action.', max_length=1024, verbose_name='Description')),
('node_type', models.CharField(help_text='The type of action (e.g. MapReduce, Pig...)', max_length=64, verbose_name='Type')),
('data', models.TextField(blank=True, default='{}')),
],
),
migrations.CreateModel(
name='Bundle',
fields=[
('job_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Job')),
('kick_off_time', models.DateTimeField(auto_now=True, help_text='When to start the first coordinators.', verbose_name='Start')),
],
bases=('oozie.job',),
),
migrations.CreateModel(
name='Coordinator',
fields=[
('job_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Job')),
('frequency_number', models.SmallIntegerField(choices=[(1, 1), (2, 2), (3, 3), (4, 4), (5, 5), (6, 6), (7, 7), (8, 8), (9, 9), (10, 10), (11, 11), (12, 12), (13, 13), (14, 14), (15, 15), (16, 16), (17, 17), (18, 18), (19, 19), (20, 20), (21, 21), (22, 22), (23, 23), (24, 24), (25, 25), (26, 26), (27, 27), (28, 28), (29, 29), (30, 30), (31, 31), (32, 32), (33, 33), (34, 34), (35, 35), (36, 36), (37, 37), (38, 38), (39, 39), (40, 40), (41, 41), (42, 42), (43, 43), (44, 44), (45, 45), (46, 46), (47, 47), (48, 48), (49, 49), (50, 50), (51, 51), (52, 52), (53, 53), (54, 54), (55, 55), (56, 56), (57, 57), (58, 58), (59, 59), (60, 60)], default=1, help_text='The number of units of the rate at which data is periodically created.', verbose_name='Frequency number')),
('frequency_unit', models.CharField(choices=[('minutes', 'Minutes'), ('hours', 'Hours'), ('days', 'Days'), ('months', 'Months')], default='days', help_text='The unit of the rate at which data is periodically created.', max_length=20, verbose_name='Frequency unit')),
('timezone', models.CharField(choices=[('Africa/Abidjan', 'Africa/Abidjan'), ('Africa/Accra', 'Africa/Accra'), ('Africa/Addis_Ababa', 'Africa/Addis_Ababa'), ('Africa/Algiers', 'Africa/Algiers'), ('Africa/Asmara', 'Africa/Asmara'), ('Africa/Asmera', 'Africa/Asmera'), ('Africa/Bamako', 'Africa/Bamako'), ('Africa/Bangui', 'Africa/Bangui'), ('Africa/Banjul', 'Africa/Banjul'), ('Africa/Bissau', 'Africa/Bissau'), ('Africa/Blantyre', 'Africa/Blantyre'), ('Africa/Brazzaville', 'Africa/Brazzaville'), ('Africa/Bujumbura', 'Africa/Bujumbura'), ('Africa/Cairo', 'Africa/Cairo'), ('Africa/Casablanca', 'Africa/Casablanca'), ('Africa/Ceuta', 'Africa/Ceuta'), ('Africa/Conakry', 'Africa/Conakry'), ('Africa/Dakar', 'Africa/Dakar'), ('Africa/Dar_es_Salaam', 'Africa/Dar_es_Salaam'), ('Africa/Djibouti', 'Africa/Djibouti'), ('Africa/Douala', 'Africa/Douala'), ('Africa/El_Aaiun', 'Africa/El_Aaiun'), ('Africa/Freetown', 'Africa/Freetown'), ('Africa/Gaborone', 'Africa/Gaborone'), ('Africa/Harare', 'Africa/Harare'), ('Africa/Johannesburg', 'Africa/Johannesburg'), ('Africa/Juba', 'Africa/Juba'), ('Africa/Kampala', 'Africa/Kampala'), ('Africa/Khartoum', 'Africa/Khartoum'), ('Africa/Kigali', 'Africa/Kigali'), ('Africa/Kinshasa', 'Africa/Kinshasa'), ('Africa/Lagos', 'Africa/Lagos'), ('Africa/Libreville', 'Africa/Libreville'), ('Africa/Lome', 'Africa/Lome'), ('Africa/Luanda', 'Africa/Luanda'), ('Africa/Lubumbashi', 'Africa/Lubumbashi'), ('Africa/Lusaka', 'Africa/Lusaka'), ('Africa/Malabo', 'Africa/Malabo'), ('Africa/Maputo', 'Africa/Maputo'), ('Africa/Maseru', 'Africa/Maseru'), ('Africa/Mbabane', 'Africa/Mbabane'), ('Africa/Mogadishu', 'Africa/Mogadishu'), ('Africa/Monrovia', 'Africa/Monrovia'), ('Africa/Nairobi', 'Africa/Nairobi'), ('Africa/Ndjamena', 'Africa/Ndjamena'), ('Africa/Niamey', 'Africa/Niamey'), ('Africa/Nouakchott', 'Africa/Nouakchott'), ('Africa/Ouagadougou', 'Africa/Ouagadougou'), ('Africa/Porto-Novo', 'Africa/Porto-Novo'), ('Africa/Sao_Tome', 'Africa/Sao_Tome'), ('Africa/Timbuktu', 'Africa/Timbuktu'), ('Africa/Tripoli', 'Africa/Tripoli'), ('Africa/Tunis', 'Africa/Tunis'), ('Africa/Windhoek', 'Africa/Windhoek'), ('America/Adak', 'America/Adak'), ('America/Anchorage', 'America/Anchorage'), ('America/Anguilla', 'America/Anguilla'), ('America/Antigua', 'America/Antigua'), ('America/Araguaina', 'America/Araguaina'), ('America/Argentina/Buenos_Aires', 'America/Argentina/Buenos_Aires'), ('America/Argentina/Catamarca', 'America/Argentina/Catamarca'), ('America/Argentina/ComodRivadavia', 'America/Argentina/ComodRivadavia'), ('America/Argentina/Cordoba', 'America/Argentina/Cordoba'), ('America/Argentina/Jujuy', 'America/Argentina/Jujuy'), ('America/Argentina/La_Rioja', 'America/Argentina/La_Rioja'), ('America/Argentina/Mendoza', 'America/Argentina/Mendoza'), ('America/Argentina/Rio_Gallegos', 'America/Argentina/Rio_Gallegos'), ('America/Argentina/Salta', 'America/Argentina/Salta'), ('America/Argentina/San_Juan', 'America/Argentina/San_Juan'), ('America/Argentina/San_Luis', 'America/Argentina/San_Luis'), ('America/Argentina/Tucuman', 'America/Argentina/Tucuman'), ('America/Argentina/Ushuaia', 'America/Argentina/Ushuaia'), ('America/Aruba', 'America/Aruba'), ('America/Asuncion', 'America/Asuncion'), ('America/Atikokan', 'America/Atikokan'), ('America/Atka', 'America/Atka'), ('America/Bahia', 'America/Bahia'), ('America/Bahia_Banderas', 'America/Bahia_Banderas'), ('America/Barbados', 'America/Barbados'), ('America/Belem', 'America/Belem'), ('America/Belize', 'America/Belize'), ('America/Blanc-Sablon', 'America/Blanc-Sablon'), ('America/Boa_Vista', 'America/Boa_Vista'), ('America/Bogota', 'America/Bogota'), ('America/Boise', 'America/Boise'), ('America/Buenos_Aires', 'America/Buenos_Aires'), ('America/Cambridge_Bay', 'America/Cambridge_Bay'), ('America/Campo_Grande', 'America/Campo_Grande'), ('America/Cancun', 'America/Cancun'), ('America/Caracas', 'America/Caracas'), ('America/Catamarca', 'America/Catamarca'), ('America/Cayenne', 'America/Cayenne'), ('America/Cayman', 'America/Cayman'), ('America/Chicago', 'America/Chicago'), ('America/Chihuahua', 'America/Chihuahua'), ('America/Coral_Harbour', 'America/Coral_Harbour'), ('America/Cordoba', 'America/Cordoba'), ('America/Costa_Rica', 'America/Costa_Rica'), ('America/Creston', 'America/Creston'), ('America/Cuiaba', 'America/Cuiaba'), ('America/Curacao', 'America/Curacao'), ('America/Danmarkshavn', 'America/Danmarkshavn'), ('America/Dawson', 'America/Dawson'), ('America/Dawson_Creek', 'America/Dawson_Creek'), ('America/Denver', 'America/Denver'), ('America/Detroit', 'America/Detroit'), ('America/Dominica', 'America/Dominica'), ('America/Edmonton', 'America/Edmonton'), ('America/Eirunepe', 'America/Eirunepe'), ('America/El_Salvador', 'America/El_Salvador'), ('America/Ensenada', 'America/Ensenada'), ('America/Fort_Wayne', 'America/Fort_Wayne'), ('America/Fortaleza', 'America/Fortaleza'), ('America/Glace_Bay', 'America/Glace_Bay'), ('America/Godtha', 'America/Godtha'), ('America/Goose_Bay', 'America/Goose_Bay'), ('America/Grand_Turk', 'America/Grand_Turk'), ('America/Grenada', 'America/Grenada'), ('America/Guadeloupe', 'America/Guadeloupe'), ('America/Guatemala', 'America/Guatemala'), ('America/Guayaquil', 'America/Guayaquil'), ('America/Guyana', 'America/Guyana'), ('America/Halifax', 'America/Halifax'), ('America/Havana', 'America/Havana'), ('America/Hermosillo', 'America/Hermosillo'), ('America/Indiana/Indianapolis', 'America/Indiana/Indianapolis'), ('America/Indiana/Knox', 'America/Indiana/Knox'), ('America/Indiana/Marengo', 'America/Indiana/Marengo'), ('America/Indiana/Petersburg', 'America/Indiana/Petersburg'), ('America/Indiana/Tell_City', 'America/Indiana/Tell_City'), ('America/Indiana/Vevay', 'America/Indiana/Vevay'), ('America/Indiana/Vincennes', 'America/Indiana/Vincennes'), ('America/Indiana/Winamac', 'America/Indiana/Winamac'), ('America/Indianapolis', 'America/Indianapolis'), ('America/Inuvik', 'America/Inuvik'), ('America/Iqaluit', 'America/Iqaluit'), ('America/Jamaica', 'America/Jamaica'), ('America/Jujuy', 'America/Jujuy'), ('America/Juneau', 'America/Juneau'), ('America/Kentucky/Louisville', 'America/Kentucky/Louisville'), ('America/Kentucky/Monticello', 'America/Kentucky/Monticello'), ('America/Knox_IN', 'America/Knox_IN'), ('America/Kralendijk', 'America/Kralendijk'), ('America/La_Paz', 'America/La_Paz'), ('America/Lima', 'America/Lima'), ('America/Los_Angeles', 'America/Los_Angeles'), ('America/Louisville', 'America/Louisville'), ('America/Lower_Princes', 'America/Lower_Princes'), ('America/Maceio', 'America/Maceio'), ('America/Managua', 'America/Managua'), ('America/Manaus', 'America/Manaus'), ('America/Marigot', 'America/Marigot'), ('America/Martinique', 'America/Martinique'), ('America/Matamoros', 'America/Matamoros'), ('America/Mazatlan', 'America/Mazatlan'), ('America/Mendoza', 'America/Mendoza'), ('America/Menominee', 'America/Menominee'), ('America/Merida', 'America/Merida'), ('America/Metlakatla', 'America/Metlakatla'), ('America/Mexico_City', 'America/Mexico_City'), ('America/Miquelon', 'America/Miquelon'), ('America/Moncton', 'America/Moncton'), ('America/Monterrey', 'America/Monterrey'), ('America/Montevideo', 'America/Montevideo'), ('America/Montreal', 'America/Montreal'), ('America/Montserrat', 'America/Montserrat'), ('America/Nassau', 'America/Nassau'), ('America/New_York', 'America/New_York'), ('America/Nipigon', 'America/Nipigon'), ('America/Nome', 'America/Nome'), ('America/Noronha', 'America/Noronha'), ('America/North_Dakota/Beulah', 'America/North_Dakota/Beulah'), ('America/North_Dakota/Center', 'America/North_Dakota/Center'), ('America/North_Dakota/New_Salem', 'America/North_Dakota/New_Salem'), ('America/Ojinaga', 'America/Ojinaga'), ('America/Panama', 'America/Panama'), ('America/Pangnirtung', 'America/Pangnirtung'), ('America/Paramaribo', 'America/Paramaribo'), ('America/Phoenix', 'America/Phoenix'), ('America/Port-au-Prince', 'America/Port-au-Prince'), ('America/Port_of_Spain', 'America/Port_of_Spain'), ('America/Porto_Acre', 'America/Porto_Acre'), ('America/Porto_Velho', 'America/Porto_Velho'), ('America/Puerto_Rico', 'America/Puerto_Rico'), ('America/Rainy_River', 'America/Rainy_River'), ('America/Rankin_Inlet', 'America/Rankin_Inlet'), ('America/Recife', 'America/Recife'), ('America/Regina', 'America/Regina'), ('America/Resolute', 'America/Resolute'), ('America/Rio_Branco', 'America/Rio_Branco'), ('America/Rosario', 'America/Rosario'), ('America/Santa_Isabel', 'America/Santa_Isabel'), ('America/Santarem', 'America/Santarem'), ('America/Santiago', 'America/Santiago'), ('America/Santo_Domingo', 'America/Santo_Domingo'), ('America/Sao_Paulo', 'America/Sao_Paulo'), ('America/Scoresbysund', 'America/Scoresbysund'), ('America/Shiprock', 'America/Shiprock'), ('America/Sitka', 'America/Sitka'), ('America/St_Barthelemy', 'America/St_Barthelemy'), ('America/St_Johns', 'America/St_Johns'), ('America/St_Kitts', 'America/St_Kitts'), ('America/St_Lucia', 'America/St_Lucia'), ('America/St_Thomas', 'America/St_Thomas'), ('America/St_Vincent', 'America/St_Vincent'), ('America/Swift_Current', 'America/Swift_Current'), ('America/Tegucigalpa', 'America/Tegucigalpa'), ('America/Thule', 'America/Thule'), ('America/Thunder_Bay', 'America/Thunder_Bay'), ('America/Tijuana', 'America/Tijuana'), ('America/Toronto', 'America/Toronto'), ('America/Tortola', 'America/Tortola'), ('America/Vancouver', 'America/Vancouver'), ('America/Virgin', 'America/Virgin'), ('America/Whitehorse', 'America/Whitehorse'), ('America/Winnipeg', 'America/Winnipeg'), ('America/Yakutat', 'America/Yakutat'), ('America/Yellowknife', 'America/Yellowknife'), ('Antarctica/Casey', 'Antarctica/Casey'), ('Antarctica/Davis', 'Antarctica/Davis'), ('Antarctica/DumontDUrville', 'Antarctica/DumontDUrville'), ('Antarctica/Macquarie', 'Antarctica/Macquarie'), ('Antarctica/Mawson', 'Antarctica/Mawson'), ('Antarctica/McMurdo', 'Antarctica/McMurdo'), ('Antarctica/Palmer', 'Antarctica/Palmer'), ('Antarctica/Rothera', 'Antarctica/Rothera'), ('Antarctica/South_Pole', 'Antarctica/South_Pole'), ('Antarctica/Syowa', 'Antarctica/Syowa'), ('Antarctica/Vostok', 'Antarctica/Vostok'), ('Arctic/Longyearbyen', 'Arctic/Longyearbyen'), ('Asia/Aden', 'Asia/Aden'), ('Asia/Almaty', 'Asia/Almaty'), ('Asia/Amman', 'Asia/Amman'), ('Asia/Anadyr', 'Asia/Anadyr'), ('Asia/Aqtau', 'Asia/Aqtau'), ('Asia/Aqtobe', 'Asia/Aqtobe'), ('Asia/Ashgabat', 'Asia/Ashgabat'), ('Asia/Ashkhabad', 'Asia/Ashkhabad'), ('Asia/Baghdad', 'Asia/Baghdad'), ('Asia/Bahrain', 'Asia/Bahrain'), ('Asia/Baku', 'Asia/Baku'), ('Asia/Bangkok', 'Asia/Bangkok'), ('Asia/Beijing', 'Asia/Beijing'), ('Asia/Beirut', 'Asia/Beirut'), ('Asia/Bishkek', 'Asia/Bishkek'), ('Asia/Brunei', 'Asia/Brunei'), ('Asia/Calcutta', 'Asia/Calcutta'), ('Asia/Choibalsan', 'Asia/Choibalsan'), ('Asia/Chongqing', 'Asia/Chongqing'), ('Asia/Chungking', 'Asia/Chungking'), ('Asia/Colombo', 'Asia/Colombo'), ('Asia/Dacca', 'Asia/Dacca'), ('Asia/Damascus', 'Asia/Damascus'), ('Asia/Dhaka', 'Asia/Dhaka'), ('Asia/Dili', 'Asia/Dili'), ('Asia/Dubai', 'Asia/Dubai'), ('Asia/Dushanbe', 'Asia/Dushanbe'), ('Asia/Gaza', 'Asia/Gaza'), ('Asia/Harbin', 'Asia/Harbin'), ('Asia/Hebron', 'Asia/Hebron'), ('Asia/Ho_Chi_Minh', 'Asia/Ho_Chi_Minh'), ('Asia/Hong_Kong', 'Asia/Hong_Kong'), ('Asia/Hovd', 'Asia/Hovd'), ('Asia/Irkutsk', 'Asia/Irkutsk'), ('Asia/Istanbul', 'Asia/Istanbul'), ('Asia/Jakarta', 'Asia/Jakarta'), ('Asia/Jayapura', 'Asia/Jayapura'), ('Asia/Jerusalem', 'Asia/Jerusalem'), ('Asia/Kabul', 'Asia/Kabul'), ('Asia/Kamchatka', 'Asia/Kamchatka'), ('Asia/Karachi', 'Asia/Karachi'), ('Asia/Kashgar', 'Asia/Kashgar'), ('Asia/Kathmandu', 'Asia/Kathmandu'), ('Asia/Katmandu', 'Asia/Katmandu'), ('Asia/Kolkata', 'Asia/Kolkata'), ('Asia/Krasnoyarsk', 'Asia/Krasnoyarsk'), ('Asia/Kuala_Lumpur', 'Asia/Kuala_Lumpur'), ('Asia/Kuching', 'Asia/Kuching'), ('Asia/Kuwait', 'Asia/Kuwait'), ('Asia/Macao', 'Asia/Macao'), ('Asia/Macau', 'Asia/Macau'), ('Asia/Magadan', 'Asia/Magadan'), ('Asia/Makassar', 'Asia/Makassar'), ('Asia/Manila', 'Asia/Manila'), ('Asia/Muscat', 'Asia/Muscat'), ('Asia/Nicosia', 'Asia/Nicosia'), ('Asia/Novokuznetsk', 'Asia/Novokuznetsk'), ('Asia/Novosibirsk', 'Asia/Novosibirsk'), ('Asia/Omsk', 'Asia/Omsk'), ('Asia/Oral', 'Asia/Oral'), ('Asia/Phnom_Penh', 'Asia/Phnom_Penh'), ('Asia/Pontianak', 'Asia/Pontianak'), ('Asia/Pyongyang', 'Asia/Pyongyang'), ('Asia/Qatar', 'Asia/Qatar'), ('Asia/Qyzylorda', 'Asia/Qyzylorda'), ('Asia/Rangoon', 'Asia/Rangoon'), ('Asia/Riyadh', 'Asia/Riyadh'), ('Asia/Riyadh87', 'Asia/Riyadh87'), ('Asia/Riyadh88', 'Asia/Riyadh88'), ('Asia/Riyadh89', 'Asia/Riyadh89'), ('Asia/Saigon', 'Asia/Saigon'), ('Asia/Sakhalin', 'Asia/Sakhalin'), ('Asia/Samarkand', 'Asia/Samarkand'), ('Asia/Seoul', 'Asia/Seoul'), ('Asia/Shanghai', 'Asia/Shanghai'), ('Asia/Singapore', 'Asia/Singapore'), ('Asia/Taipei', 'Asia/Taipei'), ('Asia/Tashkent', 'Asia/Tashkent'), ('Asia/Tbilisi', 'Asia/Tbilisi'), ('Asia/Tehran', 'Asia/Tehran'), ('Asia/Tel_Aviv', 'Asia/Tel_Aviv'), ('Asia/Thimbu', 'Asia/Thimbu'), ('Asia/Thimphu', 'Asia/Thimphu'), ('Asia/Tokyo', 'Asia/Tokyo'), ('Asia/Ujung_Pandang', 'Asia/Ujung_Pandang'), ('Asia/Ulaanbaatar', 'Asia/Ulaanbaatar'), ('Asia/Ulan_Bator', 'Asia/Ulan_Bator'), ('Asia/Urumqi', 'Asia/Urumqi'), ('Asia/Vientiane', 'Asia/Vientiane'), ('Asia/Vladivostok', 'Asia/Vladivostok'), ('Asia/Yakutsk', 'Asia/Yakutsk'), ('Asia/Yekaterinburg', 'Asia/Yekaterinburg'), ('Asia/Yerevan', 'Asia/Yerevan'), ('Atlantic/Azores', 'Atlantic/Azores'), ('Atlantic/Bermuda', 'Atlantic/Bermuda'), ('Atlantic/Canary', 'Atlantic/Canary'), ('Atlantic/Cape_Verde', 'Atlantic/Cape_Verde'), ('Atlantic/Faeroe', 'Atlantic/Faeroe'), ('Atlantic/Faroe', 'Atlantic/Faroe'), ('Atlantic/Jan_Mayen', 'Atlantic/Jan_Mayen'), ('Atlantic/Madeira', 'Atlantic/Madeira'), ('Atlantic/Reykjavik', 'Atlantic/Reykjavik'), ('Atlantic/South_Georgia', 'Atlantic/South_Georgia'), ('Atlantic/St_Helena', 'Atlantic/St_Helena'), ('Atlantic/Stanley', 'Atlantic/Stanley'), ('Australia/ACT', 'Australia/ACT'), ('Australia/Adelaide', 'Australia/Adelaide'), ('Australia/Brisbane', 'Australia/Brisbane'), ('Australia/Broken_Hill', 'Australia/Broken_Hill'), ('Australia/Canberra', 'Australia/Canberra'), ('Australia/Currie', 'Australia/Currie'), ('Australia/Darwin', 'Australia/Darwin'), ('Australia/Eucla', 'Australia/Eucla'), ('Australia/Hobart', 'Australia/Hobart'), ('Australia/LHI', 'Australia/LHI'), ('Australia/Lindeman', 'Australia/Lindeman'), ('Australia/Lord_Howe', 'Australia/Lord_Howe'), ('Australia/Melbourne', 'Australia/Melbourne'), ('Australia/NSW', 'Australia/NSW'), ('Australia/North', 'Australia/North'), ('Australia/Perth', 'Australia/Perth'), ('Australia/Queensland', 'Australia/Queensland'), ('Australia/South', 'Australia/South'), ('Australia/Sydney', 'Australia/Sydney'), ('Australia/Tasmania', 'Australia/Tasmania'), ('Australia/Victoria', 'Australia/Victoria'), ('Australia/West', 'Australia/West'), ('Australia/Yancowinna', 'Australia/Yancowinna'), ('Brazil/Acre', 'Brazil/Acre'), ('Brazil/DeNoronha', 'Brazil/DeNoronha'), ('Brazil/East', 'Brazil/East'), ('Brazil/West', 'Brazil/West'), ('CET', 'CET'), ('CST6CDT', 'CST6CDT'), ('Canada/Atlantic', 'Canada/Atlantic'), ('Canada/Central', 'Canada/Central'), ('Canada/East-Saskatchewan', 'Canada/East-Saskatchewan'), ('Canada/Eastern', 'Canada/Eastern'), ('Canada/Mountain', 'Canada/Mountain'), ('Canada/Newfoundland', 'Canada/Newfoundland'), ('Canada/Pacific', 'Canada/Pacific'), ('Canada/Saskatchewan', 'Canada/Saskatchewan'), ('Canada/Yukon', 'Canada/Yukon'), ('Chile/Continental', 'Chile/Continental'), ('Chile/EasterIsland', 'Chile/EasterIsland'), ('Cuba', 'Cuba'), ('EET', 'EET'), ('EST', 'EST'), ('EST5EDT', 'EST5EDT'), ('Egypt', 'Egypt'), ('Eire', 'Eire'), ('Etc/GMT', 'Etc/GMT'), ('Etc/GMT+0', 'Etc/GMT+0'), ('Etc/GMT+1', 'Etc/GMT+1'), ('Etc/GMT+10', 'Etc/GMT+10'), ('Etc/GMT+11', 'Etc/GMT+11'), ('Etc/GMT+12', 'Etc/GMT+12'), ('Etc/GMT+2', 'Etc/GMT+2'), ('Etc/GMT+3', 'Etc/GMT+3'), ('Etc/GMT+4', 'Etc/GMT+4'), ('Etc/GMT+5', 'Etc/GMT+5'), ('Etc/GMT+6', 'Etc/GMT+6'), ('Etc/GMT+7', 'Etc/GMT+7'), ('Etc/GMT+8', 'Etc/GMT+8'), ('Etc/GMT+9', 'Etc/GMT+9'), ('Etc/GMT-0', 'Etc/GMT-0'), ('Etc/GMT-1', 'Etc/GMT-1'), ('Etc/GMT-10', 'Etc/GMT-10'), ('Etc/GMT-11', 'Etc/GMT-11'), ('Etc/GMT-12', 'Etc/GMT-12'), ('Etc/GMT-13', 'Etc/GMT-13'), ('Etc/GMT-14', 'Etc/GMT-14'), ('Etc/GMT-2', 'Etc/GMT-2'), ('Etc/GMT-3', 'Etc/GMT-3'), ('Etc/GMT-4', 'Etc/GMT-4'), ('Etc/GMT-5', 'Etc/GMT-5'), ('Etc/GMT-6', 'Etc/GMT-6'), ('Etc/GMT-7', 'Etc/GMT-7'), ('Etc/GMT-8', 'Etc/GMT-8'), ('Etc/GMT-9', 'Etc/GMT-9'), ('Etc/GMT0', 'Etc/GMT0'), ('Etc/Greenwich', 'Etc/Greenwich'), ('Etc/UCT', 'Etc/UCT'), ('Etc/UTC', 'Etc/UTC'), ('Etc/Universal', 'Etc/Universal'), ('Etc/Zulu', 'Etc/Zulu'), ('Europe/Amsterdam', 'Europe/Amsterdam'), ('Europe/Andorra', 'Europe/Andorra'), ('Europe/Athens', 'Europe/Athens'), ('Europe/Belfast', 'Europe/Belfast'), ('Europe/Belgrade', 'Europe/Belgrade'), ('Europe/Berlin', 'Europe/Berlin'), ('Europe/Bratislava', 'Europe/Bratislava'), ('Europe/Brussels', 'Europe/Brussels'), ('Europe/Bucharest', 'Europe/Bucharest'), ('Europe/Budapest', 'Europe/Budapest'), ('Europe/Chisinau', 'Europe/Chisinau'), ('Europe/Copenhagen', 'Europe/Copenhagen'), ('Europe/Dublin', 'Europe/Dublin'), ('Europe/Gibraltar', 'Europe/Gibraltar'), ('Europe/Guernsey', 'Europe/Guernsey'), ('Europe/Helsinki', 'Europe/Helsinki'), ('Europe/Isle_of_Man', 'Europe/Isle_of_Man'), ('Europe/Istanbul', 'Europe/Istanbul'), ('Europe/Jersey', 'Europe/Jersey'), ('Europe/Kaliningrad', 'Europe/Kaliningrad'), ('Europe/Kiev', 'Europe/Kiev'), ('Europe/Lisbon', 'Europe/Lisbon'), ('Europe/Ljubljana', 'Europe/Ljubljana'), ('Europe/London', 'Europe/London'), ('Europe/Luxembourg', 'Europe/Luxembourg'), ('Europe/Madrid', 'Europe/Madrid'), ('Europe/Malta', 'Europe/Malta'), ('Europe/Mariehamn', 'Europe/Mariehamn'), ('Europe/Minsk', 'Europe/Minsk'), ('Europe/Monaco', 'Europe/Monaco'), ('Europe/Moscow', 'Europe/Moscow'), ('Europe/Nicosia', 'Europe/Nicosia'), ('Europe/Oslo', 'Europe/Oslo'), ('Europe/Paris', 'Europe/Paris'), ('Europe/Podgorica', 'Europe/Podgorica'), ('Europe/Prague', 'Europe/Prague'), ('Europe/Riga', 'Europe/Riga'), ('Europe/Rome', 'Europe/Rome'), ('Europe/Samara', 'Europe/Samara'), ('Europe/San_Marino', 'Europe/San_Marino'), ('Europe/Sarajevo', 'Europe/Sarajevo'), ('Europe/Simferopol', 'Europe/Simferopol'), ('Europe/Skopje', 'Europe/Skopje'), ('Europe/Sofia', 'Europe/Sofia'), ('Europe/Stockholm', 'Europe/Stockholm'), ('Europe/Tallinn', 'Europe/Tallinn'), ('Europe/Tirane', 'Europe/Tirane'), ('Europe/Tiraspol', 'Europe/Tiraspol'), ('Europe/Uzhgorod', 'Europe/Uzhgorod'), ('Europe/Vaduz', 'Europe/Vaduz'), ('Europe/Vatican', 'Europe/Vatican'), ('Europe/Vienna', 'Europe/Vienna'), ('Europe/Vilnius', 'Europe/Vilnius'), ('Europe/Volgograd', 'Europe/Volgograd'), ('Europe/Warsaw', 'Europe/Warsaw'), ('Europe/Zagre', 'Europe/Zagre'), ('Europe/Zaporozhye', 'Europe/Zaporozhye'), ('Europe/Zurich', 'Europe/Zurich'), ('Factory', 'Factory'), ('G', 'G'), ('GB-Eire', 'GB-Eire'), ('GMT', 'GMT'), ('GMT+0', 'GMT+0'), ('GMT+1', 'GMT+1'), ('GMT+10', 'GMT+10'), ('GMT+11', 'GMT+11'), ('GMT+12', 'GMT+12'), ('GMT+13', 'GMT+13'), ('GMT+14', 'GMT+14'), ('GMT+2', 'GMT+2'), ('GMT+3', 'GMT+3'), ('GMT+4', 'GMT+4'), ('GMT+5', 'GMT+5'), ('GMT+6', 'GMT+6'), ('GMT+7', 'GMT+7'), ('GMT+8', 'GMT+8'), ('GMT+9', 'GMT+9'), ('GMT-0', 'GMT-0'), ('GMT-1', 'GMT-1'), ('GMT-10', 'GMT-10'), ('GMT-11', 'GMT-11'), ('GMT-12', 'GMT-12'), ('GMT-2', 'GMT-2'), ('GMT-3', 'GMT-3'), ('GMT-4', 'GMT-4'), ('GMT-5', 'GMT-5'), ('GMT-6', 'GMT-6'), ('GMT-7', 'GMT-7'), ('GMT-8', 'GMT-8'), ('GMT-9', 'GMT-9'), ('GMT0', 'GMT0'), ('Greenwich', 'Greenwich'), ('HST', 'HST'), ('Hongkong', 'Hongkong'), ('Iceland', 'Iceland'), ('Indian/Antananarivo', 'Indian/Antananarivo'), ('Indian/Chagos', 'Indian/Chagos'), ('Indian/Christmas', 'Indian/Christmas'), ('Indian/Cocos', 'Indian/Cocos'), ('Indian/Comoro', 'Indian/Comoro'), ('Indian/Kerguelen', 'Indian/Kerguelen'), ('Indian/Mahe', 'Indian/Mahe'), ('Indian/Maldives', 'Indian/Maldives'), ('Indian/Mauritius', 'Indian/Mauritius'), ('Indian/Mayotte', 'Indian/Mayotte'), ('Indian/Reunion', 'Indian/Reunion'), ('Iran', 'Iran'), ('Israel', 'Israel'), ('Jamaica', 'Jamaica'), ('Japan', 'Japan'), ('Kwajalein', 'Kwajalein'), ('Libya', 'Libya'), ('MET', 'MET'), ('MST', 'MST'), ('MST7MDT', 'MST7MDT'), ('Mexico/BajaNorte', 'Mexico/BajaNorte'), ('Mexico/BajaSur', 'Mexico/BajaSur'), ('Mexico/General', 'Mexico/General'), ('Mideast/Riyadh87', 'Mideast/Riyadh87'), ('Mideast/Riyadh88', 'Mideast/Riyadh88'), ('Mideast/Riyadh89', 'Mideast/Riyadh89'), ('NZ', 'NZ'), ('NZ-CHAT', 'NZ-CHAT'), ('Navajo', 'Navajo'), ('PRC', 'PRC'), ('PST8PDT', 'PST8PDT'), ('Pacific/Apia', 'Pacific/Apia'), ('Pacific/Auckland', 'Pacific/Auckland'), ('Pacific/Chatham', 'Pacific/Chatham'), ('Pacific/Chuuk', 'Pacific/Chuuk'), ('Pacific/Easter', 'Pacific/Easter'), ('Pacific/Efate', 'Pacific/Efate'), ('Pacific/Enderbury', 'Pacific/Enderbury'), ('Pacific/Fakaofo', 'Pacific/Fakaofo'), ('Pacific/Fiji', 'Pacific/Fiji'), ('Pacific/Funafuti', 'Pacific/Funafuti'), ('Pacific/Galapagos', 'Pacific/Galapagos'), ('Pacific/Gambier', 'Pacific/Gambier'), ('Pacific/Guadalcanal', 'Pacific/Guadalcanal'), ('Pacific/Guam', 'Pacific/Guam'), ('Pacific/Honolulu', 'Pacific/Honolulu'), ('Pacific/Johnston', 'Pacific/Johnston'), ('Pacific/Kiritimati', 'Pacific/Kiritimati'), ('Pacific/Kosrae', 'Pacific/Kosrae'), ('Pacific/Kwajalein', 'Pacific/Kwajalein'), ('Pacific/Majuro', 'Pacific/Majuro'), ('Pacific/Marquesas', 'Pacific/Marquesas'), ('Pacific/Midway', 'Pacific/Midway'), ('Pacific/Nauru', 'Pacific/Nauru'), ('Pacific/Niue', 'Pacific/Niue'), ('Pacific/Norfolk', 'Pacific/Norfolk'), ('Pacific/Noumea', 'Pacific/Noumea'), ('Pacific/Pago_Pago', 'Pacific/Pago_Pago'), ('Pacific/Palau', 'Pacific/Palau'), ('Pacific/Pitcairn', 'Pacific/Pitcairn'), ('Pacific/Pohnpei', 'Pacific/Pohnpei'), ('Pacific/Ponape', 'Pacific/Ponape'), ('Pacific/Port_Moresby', 'Pacific/Port_Moresby'), ('Pacific/Rarotonga', 'Pacific/Rarotonga'), ('Pacific/Saipan', 'Pacific/Saipan'), ('Pacific/Samoa', 'Pacific/Samoa'), ('Pacific/Tahiti', 'Pacific/Tahiti'), ('Pacific/Tarawa', 'Pacific/Tarawa'), ('Pacific/Tongatapu', 'Pacific/Tongatapu'), ('Pacific/Truk', 'Pacific/Truk'), ('Pacific/Wake', 'Pacific/Wake'), ('Pacific/Wallis', 'Pacific/Wallis'), ('Pacific/Yap', 'Pacific/Yap'), ('Poland', 'Poland'), ('Portugal', 'Portugal'), ('ROC', 'ROC'), ('ROK', 'ROK'), ('Singapore', 'Singapore'), ('Turkey', 'Turkey'), ('UCT', 'UCT'), ('US/Alaska', 'US/Alaska'), ('US/Aleutian', 'US/Aleutian'), ('US/Arizona', 'US/Arizona'), ('US/Central', 'US/Central'), ('US/East-Indiana', 'US/East-Indiana'), ('US/Eastern', 'US/Eastern'), ('US/Hawaii', 'US/Hawaii'), ('US/Indiana-Starke', 'US/Indiana-Starke'), ('US/Michigan', 'US/Michigan'), ('US/Mountain', 'US/Mountain'), ('US/Pacific', 'US/Pacific'), ('US/Pacific-New', 'US/Pacific-New'), ('US/Samoa', 'US/Samoa'), ('Universal', 'Universal'), ('W-SU', 'W-SU'), ('WET', 'WET'), ('Zulu', 'Zulu')], default='America/Los_Angeles', help_text='The timezone of the coordinator. Only used for managing the daylight saving time changes when combining several coordinators.', max_length=24, verbose_name='Timezone')),
('start', models.DateTimeField(auto_now=True, help_text='When to start the first workflow.', verbose_name='Start')),
('end', models.DateTimeField(auto_now=True, help_text='When to start the last workflow.', verbose_name='End')),
('timeout', models.SmallIntegerField(blank=True, help_text='Number of minutes the coordinator action will be in WAITING or READY status before giving up on its execution.', null=True, verbose_name='Timeout')),
('concurrency', models.PositiveSmallIntegerField(blank=True, choices=[(1, 1), (2, 2), (3, 3), (4, 4), (5, 5), (6, 6), (7, 7), (8, 8), (9, 9), (10, 10), (11, 11), (12, 12), (13, 13), (14, 14), (15, 15), (16, 16), (17, 17), (18, 18), (19, 19), (20, 20), (21, 21), (22, 22), (23, 23), (24, 24), (25, 25), (26, 26), (27, 27), (28, 28), (29, 29), (30, 30), (31, 31), (32, 32), (33, 33), (34, 34), (35, 35), (36, 36), (37, 37), (38, 38), (39, 39), (40, 40), (41, 41), (42, 42), (43, 43), (44, 44), (45, 45), (46, 46), (47, 47), (48, 48), (49, 49), (50, 50), (51, 51), (52, 52), (53, 53), (54, 54), (55, 55), (56, 56), (57, 57), (58, 58), (59, 59), (60, 60)], help_text='The number of coordinator actions that are allowed to run concurrently (RUNNING status) before the coordinator engine starts throttling them.', null=True, verbose_name='Concurrency')),
('execution', models.CharField(blank=True, choices=[('FIFO', 'FIFO (oldest first) default'), ('LIFO', 'LIFO (newest first)'), ('LAST_ONLY', 'LAST_ONLY (discards all older materializations)')], help_text="Execution strategy of its coordinator actions when there is backlog of coordinator actions in the coordinator engine. The different execution strategies are 'oldest first', 'newest first' and 'last one only'. A backlog normally happens because of delayed input data, concurrency control or because manual re-runs of coordinator jobs.", max_length=10, null=True, verbose_name='Execution')),
('throttle', models.PositiveSmallIntegerField(blank=True, choices=[(1, 1), (2, 2), (3, 3), (4, 4), (5, 5), (6, 6), (7, 7), (8, 8), (9, 9), (10, 10), (11, 11), (12, 12), (13, 13), (14, 14), (15, 15), (16, 16), (17, 17), (18, 18), (19, 19), (20, 20), (21, 21), (22, 22), (23, 23), (24, 24), (25, 25), (26, 26), (27, 27), (28, 28), (29, 29), (30, 30), (31, 31), (32, 32), (33, 33), (34, 34), (35, 35), (36, 36), (37, 37), (38, 38), (39, 39), (40, 40), (41, 41), (42, 42), (43, 43), (44, 44), (45, 45), (46, 46), (47, 47), (48, 48), (49, 49), (50, 50), (51, 51), (52, 52), (53, 53), (54, 54), (55, 55), (56, 56), (57, 57), (58, 58), (59, 59), (60, 60)], help_text='The materialization or creation throttle value for its coordinator actions. Number of maximum coordinator actions that are allowed to be in WAITING state concurrently.', null=True, verbose_name='Throttle')),
('job_properties', models.TextField(default='[]', help_text='Additional properties to transmit to the workflow, e.g. limit=100, and EL functions, e.g. username=${coord:user()}', verbose_name='Workflow properties')),
],
bases=('oozie.job',),
),
migrations.CreateModel(
name='Decision',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='DecisionEnd',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='DistCp',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('params', models.TextField(default='[]', help_text='The arguments of the Distcp command. Put options first, then source paths, then destination path.', verbose_name='Arguments')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production', verbose_name='Hadoop job properties')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete then to create before starting the application. This should be used exclusively for directory cleanup', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Email',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('to', models.TextField(default='', help_text='Comma-separated values.', verbose_name='TO addresses')),
('cc', models.TextField(blank=True, default='', help_text='Comma-separated values.', verbose_name='CC addresses (optional)')),
('subject', models.TextField(default='', help_text='Plain-text.', verbose_name='Subject')),
('body', models.TextField(default='', help_text='Plain-text.', verbose_name='Body')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='End',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Fork',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Fs',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('deletes', models.TextField(blank=True, default='[]', help_text='Delete the specified path, if it is a directory it deletes recursively all its content and then deletes the directory.', verbose_name='Delete path')),
('mkdirs', models.TextField(blank=True, default='[]', help_text='Create the specified directory, it creates all missing directories in the path. If the directory already exist it does a no-op.', verbose_name='Create directory')),
('moves', models.TextField(blank=True, default='[]', help_text='Move a file or directory to another path.', verbose_name='Move file')),
('chmods', models.TextField(blank=True, default='[]', help_text='Change the permissions for the specified path. Permissions can be specified using the Unix Symbolic representation (e.g. -rwxrw-rw-) or an octal representation (755).', verbose_name='Change permissions')),
('touchzs', models.TextField(blank=True, default='[]', help_text='Creates a zero length file in the specified path if none exists or touch it.', verbose_name='Create or touch a file')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Generic',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('xml', models.TextField(default='', help_text='This will be inserted verbatim in the action <action name="email">...</action>. E.g. all the XML content like <email><cc>hue@hue.org</cc></email> will be inserted into the action and produce <action name="email"><email><cc>hue@hue.org</cc></email><ok/><error/></action>', verbose_name='XML of the custom action')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Hive',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('script_path', models.CharField(help_text='Script name or path to the Hive script. E.g. my_script.sql.', max_length=256, verbose_name='Script name')),
('params', models.TextField(default='[]', help_text='The Hive parameters of the script. E.g. N=5, INPUT=${inputDir}', verbose_name='Parameters')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete, then create, before starting the application. This should be used exclusively for directory cleanup.', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='hive-config.xml', help_text='Refer to a Hive hive-config.xml file bundled in the workflow deployment directory. Pick a name different than hive-site.xml.', max_length=512, verbose_name='Job XML')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Java',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('jar_path', models.CharField(help_text='Name or path to the Java jar file on HDFS. E.g. examples.jar.', max_length=512, verbose_name='Jar name')),
('main_class', models.CharField(help_text='Full name of the Java class. E.g. org.apache.hadoop.examples.Grep', max_length=256, verbose_name='Main class')),
('args', models.TextField(blank=True, help_text='Arguments of the main method. The value of each arg element is considered a single argument and they are passed to the main method in the same order.', verbose_name='Arguments')),
('java_opts', models.CharField(blank=True, help_text='Command-line parameters used to start the JVM that will execute the Java application. Using this element is equivalent to using the mapred.child.java.opts configuration property. E.g. -Dexample-property=hue', max_length=256, verbose_name='Java options')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete and then to create before starting the application. This should be used exclusively for directory cleanup.', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
('capture_output', models.BooleanField(default=False, help_text='Capture output of the stdout of the Java command execution. The Java command output must be in Java Properties file format and it must not exceed 2KB. From within the workflow definition, the output of an Java action node is accessible via the String action:output(String node, String key) function', verbose_name='Capture output')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Join',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Kill',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('message', models.CharField(default='Action failed, error message[${wf:errorMessage(wf:lastErrorNode())}]', max_length=256)),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Mapreduce',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('jar_path', models.CharField(help_text='Name or path to the MapReduce jar file on HDFS. E.g. examples.jar.', max_length=512, verbose_name='Jar name')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete and then to create before starting the application. This should be used exclusively for directory cleanup.', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Pig',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('script_path', models.CharField(help_text='Script name or path to the Pig script. E.g. my_script.pig.', max_length=256, verbose_name='Script name')),
('params', models.TextField(default='[]', help_text='The Pig parameters of the script. e.g. "-param", "INPUT=${inputDir}"', verbose_name='Parameters')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete and then to create before starting the application. This should be used exclusively for directory cleanup.', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Shell',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('command', models.CharField(help_text='The path of the Shell command to execute.', max_length=256, verbose_name='Shell command')),
('params', models.TextField(default='[]', help_text='The arguments of Shell command can then be specified using one or more argument element.', verbose_name='Arguments')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete then to create before starting the application. This should be used exclusively for directory cleanup', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
('capture_output', models.BooleanField(default=False, help_text='Capture output of the stdout of the Shell command execution. The Shell command output must be in Java Properties file format and it must not exceed 2KB. From within the workflow definition, the output of an Shell action node is accessible via the String action:output(String node, String key) function', verbose_name='Capture output')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Sqoop',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('script_path', models.TextField(blank=True, default='', help_text='The full Sqoop command. Either put it here or split it by spaces and insert the parts as multiple parameters below.', verbose_name='Command')),
('params', models.TextField(default='[]', help_text='If no command is specified, split the command by spaces and insert the Sqoop parameters here e.g. import, --connect, jdbc:hsqldb:file:db.hsqldb, ...', verbose_name='Parameters')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('prepares', models.TextField(default='[]', help_text='List of absolute paths to delete then to create before starting the application. This should be used exclusively for directory cleanup', verbose_name='Prepares')),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Ssh',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('user', models.CharField(help_text='User executing the shell command.', max_length=64, verbose_name='User')),
('host', models.CharField(help_text='Where the shell will be executed.', max_length=256, verbose_name='Host')),
('command', models.CharField(help_text='The command that will be executed.', max_length=256, verbose_name='Ssh command')),
('params', models.TextField(default='[]', help_text='The arguments of the Ssh command.', verbose_name='Arguments')),
('capture_output', models.BooleanField(default=False, help_text='Capture output of the stdout of the Ssh command execution. The Ssh command output must be in Java properties file format and it must not exceed 2KB. From within the workflow definition, the output of an Ssh action node is accessible via the String action:output(String node, String key) function', verbose_name='Capture output')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Start',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Streaming',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('files', models.TextField(default='[]', help_text='List of names or paths of files to be added to the distributed cache and the task running directory.', verbose_name='Files')),
('archives', models.TextField(default='[]', help_text='List of names or paths of the archives to be added to the distributed cache.', verbose_name='Archives')),
('job_properties', models.TextField(default='[]', help_text='For the job configuration (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('mapper', models.CharField(help_text='The executable/script to be used as mapper.', max_length=512, verbose_name='Mapper')),
('reducer', models.CharField(help_text='The executable/script to be used as reducer.', max_length=512, verbose_name='Reducer')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='SubWorkflow',
fields=[
('node_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Node')),
('propagate_configuration', models.BooleanField(default=True, help_text='If the workflow job configuration should be propagated to the child workflow.', verbose_name='Propagate configuration')),
('job_properties', models.TextField(default='[]', help_text='Can be used to specify the job properties that are required to run the child workflow job.', verbose_name='Hadoop job properties')),
],
options={
'abstract': False,
},
bases=('oozie.node',),
),
migrations.CreateModel(
name='Workflow',
fields=[
('job_ptr', models.OneToOneField(auto_created=True, on_delete=django.db.models.deletion.CASCADE, parent_link=True, primary_key=True, serialize=False, to='oozie.Job')),
('is_single', models.BooleanField(default=False)),
('job_xml', models.CharField(blank=True, default='', help_text='Refer to a Hadoop JobConf job.xml file bundled in the workflow deployment directory. Properties specified in the Job Properties element override properties specified in the files specified in the Job XML element.', max_length=512, verbose_name='Job XML')),
('job_properties', models.TextField(default='[]', help_text='Job configuration properties used by all the actions of the workflow (e.g. mapred.job.queue.name=production)', verbose_name='Hadoop job properties')),
('managed', models.BooleanField(default=True)),
('end', models.ForeignKey(blank=True, null=True, on_delete=django.db.models.deletion.CASCADE, related_name='end_workflow', to='oozie.End')),
('start', models.ForeignKey(blank=True, null=True, on_delete=django.db.models.deletion.CASCADE, related_name='start_workflow', to='oozie.Start')),
],
bases=('oozie.job',),
),
]
|
d0b587876aede958547ac4d56caebf22aa33749f
|
c5f8e61d3e4e161a17daa92efb6c88f2fe2b22a3
|
/shared/tests/integ/helpers.py
|
ffb2a604539debdeaf05c24b6d358c974015f686
|
[
"MIT-0"
] |
permissive
|
aws-samples/aws-serverless-ecommerce-platform
|
1d485a0ec211c79e4e5409ccc03c26d7255ce5b1
|
3b9ef36dd3e338c8ab697c2bcb1b672e064e303c
|
refs/heads/main
| 2023-07-31T04:37:57.289326
| 2022-03-27T14:34:41
| 2022-03-27T14:34:41
| 228,891,938
| 989
| 361
|
MIT-0
| 2023-05-23T02:05:14
| 2019-12-18T17:41:10
|
Python
|
UTF-8
|
Python
| false
| false
| 709
|
py
|
helpers.py
|
import json
import os
import boto3
def compare_dict(a: dict, b: dict):
"""
Compare two dicts
This compares only based on the keys in 'a'. Therefore, you should put the
test event as the first parameter.
"""
for key, value in a.items():
assert key in b
if key not in b:
continue
if isinstance(value, dict):
compare_dict(value, b[key])
else:
assert value == b[key]
def get_parameter(param_name: str):
"""
Retrieve an SSM parameter
"""
ssm = boto3.client("ssm")
return ssm.get_parameter(
Name=param_name.format(Environment=os.environ["ECOM_ENVIRONMENT"])
)["Parameter"]["Value"]
|
a64ba6c76bf17b7d08b8ad31066e82987037f947
|
fd52d20ad0f09113c79122b7aeb4b05f5fe748de
|
/aws_svc/s3_handler.py
|
abf9458265aa2b84619d846fdc90d09f67c0113a
|
[
"MIT"
] |
permissive
|
prisma-cloud/IAMFinder
|
a35a3f625e0245c7fa378b401c069540e67ecf5d
|
4c7c91a4f1c3ab9a82b2307bcb47284227545023
|
refs/heads/main
| 2023-01-18T17:57:19.824882
| 2020-11-19T20:15:02
| 2020-11-19T20:15:02
| 312,399,874
| 109
| 17
| null | null | null | null |
UTF-8
|
Python
| false
| false
| 5,853
|
py
|
s3_handler.py
|
from aws_svc.aws_service_base import AWS_SVC_BASE, AWS_SVC_TYPE
import boto3
import botocore
import random
import json
import string
import sys, os
import logging
from itertools import cycle
class S3Handler(AWS_SVC_BASE):
def __init__(self, boto3_session, s3_config):
super().__init__(AWS_SVC_TYPE.S3, boto3_session, s3_config)
self.s3_client = boto3_session.client('s3', config=AWS_SVC_BASE.aws_config)
self.created_bkt = list()
self.get_existing_workers()
self._set_worker_cycle(self.created_bkt)
def get_existing_workers(self):
try:
resp = self.s3_client.list_buckets()
if not self._check_boto3_response(resp):
logging.error('Fail to list existing S3 buckets.')
return
except botocore.exceptions.ClientError as error:
logging.error('Fail to list buckets. {}'.format(error))
return
key_count = self.svc_config['resource_count']
for bkt in resp['Buckets']:
bkt_name = bkt['Name']
if not bkt_name.startswith(self.rsc_prefix):
continue
# Find bucket region
try:
resp2 = self.s3_client.get_bucket_location(
Bucket = bkt_name
)
if not self._check_boto3_response(resp2):
continue
region = resp2['LocationConstraint']
self.created_bkt.append({'BucketName': bkt_name, 'Region':region})
key_count -= 1
if key_count <= 0:
break
except botocore.exceptions.ClientError as error:
logging.error('Fail to get bucket location.')
continue
return self.created_bkt
def create_workers(self):
''' Create multiple S3 buckets. Return a dictionary of bucketName and its region '''
bkt_count = self.svc_config['resource_count']
if len(self.created_bkt) >= bkt_count:
# Don't need to create more buckets
logging.info('No need to create more resources for S3')
return self.created_bkt
else:
needed = bkt_count - len(self.created_bkt)
for _ in range(0, needed, 1):
reg = self.session.region_name
bucketName = '{}-{}'.format(self.rsc_prefix, ''.join(random.choices(string.ascii_lowercase + string.digits, k=20)))
# AWS-CN needs additional permissions for this function call to work ....
if reg != 'us-east-1':
resp = self.s3_client.create_bucket(Bucket=bucketName, ACL='private',
CreateBucketConfiguration={'LocationConstraint': reg},
ObjectLockEnabledForBucket=True)
else:
resp = self.s3_client.create_bucket(Bucket=bucketName, ACL='private',
ObjectLockEnabledForBucket=True)
if not self._check_boto3_response(resp):
continue
# Block any access to the bucket
self.s3_client.put_public_access_block(
Bucket=bucketName,
PublicAccessBlockConfiguration={
'BlockPublicAcls': True,
'IgnorePublicAcls': True,
'BlockPublicPolicy': True,
'RestrictPublicBuckets': True
}
)
self.created_bkt.append({'BucketName': bucketName, 'Region':reg})
logging.info('S3 bucket {} has been successfully created in region {}'.format(bucketName, reg))
self._set_worker_cycle(self.created_bkt)
return self.created_bkt
def delete_workers(self):
for bkt in self.created_bkt:
bucketName = bkt['BucketName']
reg = bkt['Region']
resp = self.s3_client.delete_bucket(
Bucket=bucketName,
)
if self._check_boto3_response(resp):
logging.info('S3 bucket {} has been successfully deleted in region {}'.format(bucketName, reg))
else:
logging.info('Fail to delete S3 bucket {} in region {}'.format(bucketName, reg))
self.created_bkt = list()
self._set_worker_cycle(self.created_bkt)
def _check_existing_identity(self, identiy_arn):
''' Check if identiy_arn exists in AWS '''
s3_policy = '{{"Version":"2012-10-17","Statement":[{{"Sid":"iamcheck","Effect":"Deny","Principal":{{"AWS":"{}"}},"Action":["s3:*"],"Resource":["{}"]}}]}}'
bucketName = self._get_next_worker()['BucketName']
if bucketName is None:
logging.error('No available worker/resource in s3_handler')
return
# role_arn = 'arn:{}:iam::{}:role/{}'.format(aws_partition, aws_id, target_role)
aws_partition = identiy_arn.split(':')[1]
root_path = 'arn:{}:s3:::{}/*'.format(aws_partition, bucketName)
try:
resp = self.s3_client.put_bucket_policy(
Bucket=bucketName,
ConfirmRemoveSelfBucketAccess=True,
# Policy=json.dumps(policy_obj)
Policy=s3_policy.format(identiy_arn, root_path)
)
if self._check_boto3_response(resp):
return True
except botocore.exceptions.ClientError as e:
if e.response['Error']['Code'] == 'MalformedPolicy' and 'Invalid principal' in e.response['Error']['Message']:
logging.debug('Invalid principal identified using bucket {}!'.format(bucketName))
return False
except botocore.exceptions.ClientError as e:
logging.error(e)
return None
|
cce7fc99aae08edaef93703a316066f000a85499
|
820b6af9fd43b270749224bb278e5f714f655ac9
|
/Filters/Points/Testing/Python/TestStatisticalOutlierRemoval.py
|
5efd5c4c83a3cdc4d5b650245b90955e2af4c099
|
[
"BSD-3-Clause"
] |
permissive
|
Kitware/VTK
|
49dee7d4f83401efce8826f1759cd5d9caa281d1
|
dd4138e17f1ed5dfe6ef1eab0ff6643fdc07e271
|
refs/heads/master
| 2023-09-01T10:21:57.496189
| 2023-09-01T08:20:15
| 2023-09-01T08:21:05
| 631,615
| 2,253
| 1,243
|
NOASSERTION
| 2023-09-14T07:53:03
| 2010-04-27T15:12:58
|
C++
|
UTF-8
|
Python
| false
| false
| 4,300
|
py
|
TestStatisticalOutlierRemoval.py
|
#!/usr/bin/env python
from vtkmodules.vtkCommonCore import (
vtkFloatArray,
vtkMath,
vtkPoints,
)
from vtkmodules.vtkCommonDataModel import (
vtkPolyData,
vtkStaticPointLocator,
)
from vtkmodules.vtkCommonSystem import vtkTimerLog
from vtkmodules.vtkFiltersModeling import vtkOutlineFilter
from vtkmodules.vtkFiltersPoints import vtkStatisticalOutlierRemoval
from vtkmodules.vtkRenderingCore import (
vtkActor,
vtkPointGaussianMapper,
vtkPolyDataMapper,
vtkRenderWindow,
vtkRenderWindowInteractor,
vtkRenderer,
)
import vtkmodules.vtkInteractionStyle
import vtkmodules.vtkRenderingFreeType
import vtkmodules.vtkRenderingOpenGL2
from vtkmodules.util.misc import vtkGetDataRoot
VTK_DATA_ROOT = vtkGetDataRoot()
# Interpolate onto a volume
# Parameters for debugging
NPts = 20000
math = vtkMath()
math.RandomSeed(31415)
# create point cloud. A bunch of random points plus some outliers
# over the six faces of the bounding box
#
points = vtkPoints()
points.SetDataTypeToFloat()
points.SetNumberOfPoints(NPts+6)
scalars = vtkFloatArray()
scalars.SetNumberOfTuples(NPts+6)
scalars.SetName("scalars")
for i in range(0,NPts):
points.SetPoint(i,math.Random(-1,1),math.Random(-1,1),math.Random(-1,1))
scalars.SetValue(i,math.Random(0,1))
points.SetPoint(NPts, -5,0,0)
scalars.SetValue(NPts, 0.5)
points.SetPoint(NPts+1, 5,0,0)
scalars.SetValue(NPts+1, 0.5)
points.SetPoint(NPts+2, 0,-5,0)
scalars.SetValue(NPts+2, 0.5)
points.SetPoint(NPts+3, 0, 5,0)
scalars.SetValue(NPts+3, 0.5)
points.SetPoint(NPts+4, 0,0,-5)
scalars.SetValue(NPts+4, 0.5)
points.SetPoint(NPts+5, 0,0, 5)
scalars.SetValue(NPts+5, 0.5)
polydata = vtkPolyData()
polydata.SetPoints(points)
polydata.GetPointData().SetScalars(scalars)
# Reuse the locator
locator = vtkStaticPointLocator()
locator.SetDataSet(polydata)
locator.BuildLocator()
# Remove statistically isolated points
removal = vtkStatisticalOutlierRemoval()
removal.SetInputData(polydata)
removal.SetLocator(locator)
removal.SetSampleSize(20)
removal.SetStandardDeviationFactor(1.5)
removal.GenerateOutliersOn()
# Time execution
timer = vtkTimerLog()
timer.StartTimer()
removal.Update()
timer.StopTimer()
time = timer.GetElapsedTime()
print("Number of points processed: {0}".format(NPts))
print(" Time to remove outliers: {0}".format(time))
print(" Number removed: {0}".format(removal.GetNumberOfPointsRemoved()))
print(" Computed mean: {0}".format(removal.GetComputedMean()))
print(" Computed standard deviation: {0}".format(removal.GetComputedStandardDeviation()))
# First output are the non-outliers
remMapper = vtkPointGaussianMapper()
remMapper.SetInputConnection(removal.GetOutputPort())
remMapper.EmissiveOff()
remMapper.SetScaleFactor(0.0)
remActor = vtkActor()
remActor.SetMapper(remMapper)
# Create an outline
outline = vtkOutlineFilter()
outline.SetInputData(polydata)
outlineMapper = vtkPolyDataMapper()
outlineMapper.SetInputConnection(outline.GetOutputPort())
outlineActor = vtkActor()
outlineActor.SetMapper(outlineMapper)
# Second output are the outliers
remMapper1 = vtkPointGaussianMapper()
remMapper1.SetInputConnection(removal.GetOutputPort(1))
remMapper1.EmissiveOff()
remMapper1.SetScaleFactor(0.0)
remActor1 = vtkActor()
remActor1.SetMapper(remMapper1)
# Create an outline
outline1 = vtkOutlineFilter()
outline1.SetInputData(polydata)
outlineMapper1 = vtkPolyDataMapper()
outlineMapper1.SetInputConnection(outline1.GetOutputPort())
outlineActor1 = vtkActor()
outlineActor1.SetMapper(outlineMapper1)
# Create the RenderWindow, Renderer and both Actors
#
ren0 = vtkRenderer()
ren0.SetViewport(0,0,.5,1)
ren1 = vtkRenderer()
ren1.SetViewport(0.5,0,1,1)
renWin = vtkRenderWindow()
renWin.SetMultiSamples(0)
renWin.AddRenderer(ren0)
renWin.AddRenderer(ren1)
iren = vtkRenderWindowInteractor()
iren.SetRenderWindow(renWin)
# Add the actors to the renderer, set the background and size
#
ren0.AddActor(remActor)
ren0.AddActor(outlineActor)
ren0.SetBackground(0.1, 0.2, 0.4)
ren1.AddActor(remActor1)
ren1.AddActor(outlineActor1)
ren1.SetBackground(0.1, 0.2, 0.4)
renWin.SetSize(500,250)
cam = ren0.GetActiveCamera()
cam.SetFocalPoint(1,1,1)
cam.SetPosition(0,0,0)
ren0.ResetCamera()
ren1.SetActiveCamera(cam)
iren.Initialize()
# render the image
#
renWin.Render()
iren.Start()
|
7f558c7a37c05baf0f6cb82499f044221da7e5db
|
dacdebab897f9287f37a2e85c5705a926ddd36aa
|
/tests/test_config/Snakefile
|
46237e4e220a9a533ee0c4bb0474d3783a4fb054
|
[
"MIT",
"LicenseRef-scancode-unknown-license-reference"
] |
permissive
|
snakemake/snakemake
|
5d4528193d87786d7b372ca7653ece302ff46965
|
27b224ed12448df8aebc7d1ff8f25e3bf7622232
|
refs/heads/main
| 2023-09-02T08:37:04.323976
| 2023-08-11T10:02:34
| 2023-08-11T10:02:34
| 212,840,200
| 1,941
| 536
|
MIT
| 2023-09-11T09:51:44
| 2019-10-04T14:58:11
|
HTML
|
UTF-8
|
Python
| false
| false
| 132
|
Snakefile
|
include: "test.rules"
configfile: "test.json"
rule:
output:
config["outfile"]
shell:
"touch {output}"
|
|
73f4e05e3acf7ce814035532b779f7627461ab7f
|
08fb252e3f70e245cdd0e5a8fed47f6fada8b6f8
|
/examples/CircumbinaryOrbit/makeplot.py
|
14ebb6a1ec3141a63e59e61db2394c93f8d47a9c
|
[
"MIT"
] |
permissive
|
VirtualPlanetaryLaboratory/vplanet
|
3bba2126520cbe7bee1a512f87435064d3545517
|
cb683af69e80e07bc17c06e45678effdc98fc19a
|
refs/heads/main
| 2023-08-31T04:13:58.700282
| 2023-08-30T05:10:20
| 2023-08-30T05:10:20
| 138,067,409
| 128
| 54
|
MIT
| 2023-09-06T21:30:37
| 2018-06-20T17:53:00
|
C
|
UTF-8
|
Python
| false
| false
| 1,994
|
py
|
makeplot.py
|
"""
This script produces a reproduction of Figure 4 of Leung and Lee (2013), the orbital
dynamics of Kepler-16b, using VPLANET's binary module
David P. Fleming, University of Washington, 2018
"""
import pathlib
import sys
import matplotlib as mpl
import matplotlib.pyplot as plt
import numpy as np
import vplot
import vplanet
# Path hacks
path = pathlib.Path(__file__).parents[0].absolute()
sys.path.insert(1, str(path.parents[0]))
from get_args import get_args
# Typical plot parameters that make for pretty plot
mpl.rcParams["figure.figsize"] = (10, 8)
mpl.rcParams["font.size"] = 18.0
# Run vplanet
output = vplanet.run(path / "vpl.in", units=False)
# Extract data
time = output.cbp.Time
ecc = output.cbp.Eccentricity
longa = output.cbp.LongA
varpi = output.cbp.LongP
inc = output.cbp.Inc
# Plot
fig, axes = plt.subplots(nrows=2, ncols=2, sharex=True)
color = "k"
## Upper left: eccentricity ##
axes[0, 0].plot(time, ecc, color=color, zorder=-1)
# Format
axes[0, 0].set_xlim(time.min(), time.max())
axes[0, 0].set_ylabel("Eccentricity")
## Upper left: inclination ##
axes[0, 1].plot(time, inc, color=color, zorder=-1)
# Format
axes[0, 1].set_xlim(time.min(), time.max())
axes[0, 1].set_ylabel("Inclination [$^{\circ}$]")
## Lower left: Longitude of periapse ##
axes[1, 0].scatter(time, varpi, color=color, s=10, zorder=-1)
# Format
axes[1, 0].set_xlim(time.min(), time.max())
axes[1, 0].set_ylim(0, 360)
axes[1, 0].set_xlabel("Time [yr]")
axes[1, 0].set_ylabel("Longitude of Periapsis [$^{\circ}$]")
## Lower right: Longitude of the ascending node ##
axes[1, 1].scatter(time, longa, color=color, s=10, zorder=-1)
# Format
axes[1, 1].set_xlim(time.min(), time.max())
axes[1, 1].set_ylim(0, 360)
axes[1, 1].set_xlabel("Time [yr]")
axes[1, 1].set_ylabel("Longitude of\n Ascending Node [$^{\circ}$]")
for ax in axes.flatten():
ax.set_rasterization_zorder(0)
# Save the figure
ext = get_args().ext
fig.savefig(path / f"CircumbinaryOrbit.{ext}", bbox_inches="tight", dpi=600)
|
6a478535eea13f9f3e1d54853562a359bcea55e5
|
5ef6c8d47864f471e26b9902d61f8c687e941f05
|
/src/genie/libs/parser/iosxe/tests/ShowIpRouteDistributor/cli/equal/golden_output3_expected.py
|
0ce4aa8df4e65d462a4c943013ec5f7d6fab0929
|
[
"Apache-2.0"
] |
permissive
|
CiscoTestAutomation/genieparser
|
169c196558f1c1a0f0d10650876096f993224917
|
b531eff760b2e44cd69d7a2716db6f866907c239
|
refs/heads/master
| 2023-09-03T08:56:18.831340
| 2023-08-29T22:32:02
| 2023-08-29T22:32:02
| 131,621,824
| 247
| 409
|
Apache-2.0
| 2023-08-29T22:32:04
| 2018-04-30T16:51:50
|
Python
|
UTF-8
|
Python
| false
| false
| 5,143
|
py
|
golden_output3_expected.py
|
expected_output = {
"vrf": {
"default": {
"address_family": {
"ipv4": {
"routes": {
"10.34.0.1/32": {
"route": "10.34.0.1/32",
"active": True,
"metric": 0,
"route_preference": 1,
"source_protocol_codes": "S %",
"source_protocol": "static",
"next_hop": {
"next_hop_list": {
1: {
"index": 1,
"next_hop": "192.168.16.1"
}
}
}
},
"10.34.0.2/32": {
"route": "10.34.0.2/32",
"active": True,
"source_protocol_codes": "C p",
"source_protocol": "connected",
"next_hop": {
"outgoing_interface": {
"Loopback0": {
"outgoing_interface": "Loopback0"
}
}
}
},
"10.69.0.0/16": {
"route": "10.69.0.0/16",
"active": True,
"metric": 0,
"route_preference": 1,
"source_protocol_codes": "S &",
"source_protocol": "static",
"next_hop": {
"next_hop_list": {
1: {
"index": 1,
"next_hop": "10.34.0.1"
}
}
}
},
"10.186.1.0/24": {
"route": "10.186.1.0/24",
"active": True,
"metric": 0,
"route_preference": 1,
"source_protocol_codes": "S +",
"source_protocol": "static",
"next_hop": {
"next_hop_list": {
1: {
"index": 1,
"next_hop": "10.144.0.1",
"vrf": "red"
}
}
}
},
"192.168.16.0/24": {
"route": "192.168.16.0/24",
"active": True,
"source_protocol_codes": "C",
"source_protocol": "connected",
"next_hop": {
"outgoing_interface": {
"Ethernet0/1": {
"outgoing_interface": "Ethernet0/1"
}
}
}
},
"192.168.16.2/32": {
"route": "192.168.16.2/32",
"active": True,
"source_protocol_codes": "L",
"source_protocol": "local",
"next_hop": {
"outgoing_interface": {
"Ethernet0/1": {
"outgoing_interface": "Ethernet0/1"
}
}
}
},
"10.55.0.0/24": {
"route": "10.55.0.0/24",
"active": True,
"metric": 0,
"route_preference": 20,
"source_protocol_codes": "B +",
"source_protocol": "bgp",
"next_hop": {
"next_hop_list": {
1: {
"index": 1,
"next_hop": "10.144.0.1",
"updated": "00:00:09",
"vrf": "red"
}
}
}
}
}
}
}
}
}
}
|
53c44a33eff190d9ad1b187bdeda2c7573809d88
|
1180c0bfe29959d95f3c131e6e839950e528d4ee
|
/27/asutosh97/toptennews/setup.py
|
dfc67f40c0e2fd57e25674f062798e4be2051788
|
[] |
no_license
|
pybites/challenges
|
e3e461accd8e7f890aee8007ba5070086ef983fc
|
02b77652d0901e6e06cb9b1e7cb3e59c675445c2
|
refs/heads/community
| 2023-08-20T18:19:02.982214
| 2022-11-17T09:23:31
| 2022-11-17T09:23:31
| 78,264,928
| 764
| 3,115
| null | 2023-07-21T05:58:19
| 2017-01-07T07:17:50
|
Jupyter Notebook
|
UTF-8
|
Python
| false
| false
| 523
|
py
|
setup.py
|
#! /usr/bin/env python
import sys
from setuptools import setup
if sys.argv[-1] == "setup.py":
print("To install, run \'pip install ./toptennews\'")
if __name__ == "__main__":
setup(
name = "toptennews",
author ='Asutosh Sahoo',
author_email = 'asutoshsahoo786@gmail.com',
version = '1.0',
packages = ['toptennews'],
install_requires = ['praw'],
entry_points = {
'console_scripts' : [
'toptennews = toptennews.main:main'
]
}
)
|
5abe3d70f0f15b0d36c8df162ae86efd4659d2c2
|
ea57d267ab31480d8d731b2c095e9da9ad989133
|
/tests/test_packages/test_skills_integration/test_erc1155.py
|
59e6c2796d669ecf3b6f7d0b27c264d643684d7a
|
[
"Apache-2.0"
] |
permissive
|
fetchai/agents-aea
|
6d034f1db6f3beacf31dac2f5a1baaa60c8edb7d
|
bec49adaeba661d8d0f03ac9935dc89f39d95a0d
|
refs/heads/main
| 2023-08-08T23:19:06.276643
| 2023-02-04T10:46:39
| 2023-02-04T10:46:39
| 203,558,879
| 192
| 58
|
Apache-2.0
| 2023-07-19T04:45:26
| 2019-08-21T10:12:47
|
Python
|
UTF-8
|
Python
| false
| false
| 12,192
|
py
|
test_erc1155.py
|
# -*- coding: utf-8 -*-
# ------------------------------------------------------------------------------
#
# Copyright 2018-2023 Fetch.AI Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# ------------------------------------------------------------------------------
"""This test module contains the integration test for the generic buyer and seller skills."""
import json
from random import uniform
import pytest
from aea_ledger_ethereum import EthereumCrypto
from aea_ledger_fetchai import FetchAICrypto
from aea.test_tools.test_cases import AEATestCaseManyFlaky
from packages.fetchai.connections.p2p_libp2p.connection import LIBP2P_SUCCESS_MESSAGE
from tests.conftest import (
ETHEREUM_PRIVATE_KEY_FILE,
FETCHAI_PRIVATE_KEY_FILE_CONNECTION,
FUNDED_ETH_PRIVATE_KEY_2,
FUNDED_ETH_PRIVATE_KEY_3,
MAX_FLAKY_RERUNS_ETH,
NON_FUNDED_FETCHAI_PRIVATE_KEY_1,
NON_GENESIS_CONFIG,
UseGanache,
wait_for_localhost_ports_to_close,
)
@pytest.mark.integration
class TestERCSkillsEthereumLedger(AEATestCaseManyFlaky, UseGanache):
"""Test that erc1155 skills work."""
@pytest.mark.integration
@pytest.mark.ledger
@pytest.mark.flaky(reruns=MAX_FLAKY_RERUNS_ETH) # cause possible network issues
def test_generic(self):
"""Run the generic skills sequence."""
deploy_aea_name = "deploy_aea"
client_aea_name = "client_aea"
self.create_agents(deploy_aea_name, client_aea_name)
# add ethereum ledger in both configuration files
default_routing = {
"fetchai/ledger_api:1.1.7": "fetchai/ledger:0.21.5",
"fetchai/contract_api:1.1.7": "fetchai/ledger:0.21.5",
"fetchai/oef_search:1.1.7": "fetchai/soef:0.27.6",
}
# generate random location
location = {
"latitude": round(uniform(-90, 90), 2), # nosec
"longitude": round(uniform(-180, 180), 2), # nosec
}
# add packages for agent one
self.set_agent_context(deploy_aea_name)
self.add_item("connection", "fetchai/p2p_libp2p:0.27.5")
self.add_item("connection", "fetchai/ledger:0.21.5")
self.add_item("connection", "fetchai/soef:0.27.6")
self.set_config("agent.default_connection", "fetchai/p2p_libp2p:0.27.5")
self.set_config("agent.default_ledger", EthereumCrypto.identifier)
self.nested_set_config(
"agent.required_ledgers",
[FetchAICrypto.identifier, EthereumCrypto.identifier],
)
setting_path = "agent.default_routing"
self.nested_set_config(setting_path, default_routing)
self.add_item("skill", "fetchai/erc1155_deploy:0.31.6")
self.generate_private_key(EthereumCrypto.identifier)
self.add_private_key(EthereumCrypto.identifier, ETHEREUM_PRIVATE_KEY_FILE)
self.replace_private_key_in_file(
FUNDED_ETH_PRIVATE_KEY_3, ETHEREUM_PRIVATE_KEY_FILE
)
self.generate_private_key(
FetchAICrypto.identifier, FETCHAI_PRIVATE_KEY_FILE_CONNECTION
)
self.add_private_key(
FetchAICrypto.identifier,
FETCHAI_PRIVATE_KEY_FILE_CONNECTION,
connection=True,
)
self.replace_private_key_in_file(
NON_FUNDED_FETCHAI_PRIVATE_KEY_1, FETCHAI_PRIVATE_KEY_FILE_CONNECTION
)
setting_path = "vendor.fetchai.connections.soef.config.chain_identifier"
self.set_config(setting_path, "ethereum")
setting_path = "vendor.fetchai.connections.p2p_libp2p.cert_requests"
settings = json.dumps(
[
{
"identifier": "acn",
"ledger_id": EthereumCrypto.identifier,
"not_after": "2023-01-01",
"not_before": "2022-01-01",
"public_key": FetchAICrypto.identifier,
"message_format": "{public_key}",
"save_path": ".certs/conn_cert.txt",
}
]
)
self.set_config(setting_path, settings, type_="list")
self.run_install()
# replace location
setting_path = (
"vendor.fetchai.skills.erc1155_deploy.models.strategy.args.location"
)
self.nested_set_config(setting_path, location)
diff = self.difference_to_fetched_agent(
"fetchai/erc1155_deployer:0.34.5", deploy_aea_name
)
assert (
diff == []
), "Difference between created and fetched project for files={}".format(diff)
# add packages for agent two
self.set_agent_context(client_aea_name)
self.add_item("connection", "fetchai/p2p_libp2p:0.27.5")
self.add_item("connection", "fetchai/ledger:0.21.5")
self.add_item("connection", "fetchai/soef:0.27.6")
self.set_config("agent.default_connection", "fetchai/p2p_libp2p:0.27.5")
self.set_config("agent.default_ledger", EthereumCrypto.identifier)
self.nested_set_config(
"agent.required_ledgers",
[FetchAICrypto.identifier, EthereumCrypto.identifier],
)
setting_path = "agent.default_routing"
self.nested_set_config(setting_path, default_routing)
self.add_item("skill", "fetchai/erc1155_client:0.29.6")
self.generate_private_key(EthereumCrypto.identifier)
self.add_private_key(EthereumCrypto.identifier, ETHEREUM_PRIVATE_KEY_FILE)
self.replace_private_key_in_file(
FUNDED_ETH_PRIVATE_KEY_2, ETHEREUM_PRIVATE_KEY_FILE
)
self.generate_private_key(
FetchAICrypto.identifier, FETCHAI_PRIVATE_KEY_FILE_CONNECTION
)
self.add_private_key(
FetchAICrypto.identifier,
FETCHAI_PRIVATE_KEY_FILE_CONNECTION,
connection=True,
)
setting_path = "vendor.fetchai.connections.soef.config.chain_identifier"
self.set_config(setting_path, "ethereum")
setting_path = "vendor.fetchai.connections.p2p_libp2p.config"
self.nested_set_config(setting_path, NON_GENESIS_CONFIG)
setting_path = "vendor.fetchai.connections.p2p_libp2p.cert_requests"
settings = json.dumps(
[
{
"identifier": "acn",
"ledger_id": EthereumCrypto.identifier,
"not_after": "2023-01-01",
"not_before": "2022-01-01",
"public_key": FetchAICrypto.identifier,
"message_format": "{public_key}",
"save_path": ".certs/conn_cert.txt",
}
]
)
self.set_config(setting_path, settings, type_="list")
self.run_install()
# replace location
setting_path = (
"vendor.fetchai.skills.erc1155_client.models.strategy.args.location"
)
self.nested_set_config(setting_path, location)
diff = self.difference_to_fetched_agent(
"fetchai/erc1155_client:0.34.5", client_aea_name
)
assert (
diff == []
), "Difference between created and fetched project for files={}".format(diff)
# run agents
self.set_agent_context(deploy_aea_name)
self.run_cli_command("build", cwd=self._get_cwd())
self.run_cli_command("issue-certificates", cwd=self._get_cwd())
deploy_aea_process = self.run_agent()
check_strings = (
"Starting libp2p node...",
"Connecting to libp2p node...",
"Successfully connected to libp2p node!",
LIBP2P_SUCCESS_MESSAGE,
)
missing_strings = self.missing_from_output(
deploy_aea_process, check_strings, timeout=30, is_terminating=False
)
assert (
missing_strings == []
), "Strings {} didn't appear in deploy_aea output.".format(missing_strings)
check_strings = (
"starting balance on ethereum ledger=",
"received raw transaction=",
"proposing the transaction to the decision maker. Waiting for confirmation ...",
"transaction signing was successful.",
"sending transaction to ledger.",
"transaction was successfully submitted. Transaction digest=",
"requesting transaction receipt.",
"transaction was successfully settled. Transaction receipt=",
"requesting create batch transaction...",
"requesting mint batch transaction...",
"registering agent on SOEF.",
"registering agent's service on the SOEF.",
"registering agent's personality genus on the SOEF.",
"registering agent's personality classification on the SOEF.",
)
missing_strings = self.missing_from_output(
deploy_aea_process, check_strings, timeout=420, is_terminating=False
)
assert (
missing_strings == []
), "Strings {} didn't appear in deploy_aea output.".format(missing_strings)
self.set_agent_context(client_aea_name)
self.run_cli_command("build", cwd=self._get_cwd())
self.run_cli_command("issue-certificates", cwd=self._get_cwd())
client_aea_process = self.run_agent()
check_strings = (
"Starting libp2p node...",
"Connecting to libp2p node...",
"Successfully connected to libp2p node!",
LIBP2P_SUCCESS_MESSAGE,
)
missing_strings = self.missing_from_output(
client_aea_process, check_strings, timeout=30, is_terminating=False
)
assert (
missing_strings == []
), "Strings {} didn't appear in client_aea output.".format(missing_strings)
check_strings = (
"received CFP from sender=",
"sending PROPOSE to agent=",
"received ACCEPT_W_INFORM from sender=",
"requesting single atomic swap transaction...",
"received raw transaction=",
"proposing the transaction to the decision maker. Waiting for confirmation ...",
"transaction signing was successful.",
"sending transaction to ledger.",
"transaction was successfully submitted. Transaction digest=",
"requesting transaction receipt.",
"transaction was successfully settled. Transaction receipt=",
"demo finished!",
)
missing_strings = self.missing_from_output(
deploy_aea_process, check_strings, timeout=360, is_terminating=False
)
assert (
missing_strings == []
), "Strings {} didn't appear in deploy_aea output.".format(missing_strings)
check_strings = (
"found agents=",
"sending CFP to agent=",
"received valid PROPOSE from sender=",
"requesting single hash message from contract api...",
"received raw message=",
"proposing the transaction to the decision maker. Waiting for confirmation ...",
"sending ACCEPT_W_INFORM to agent=",
)
missing_strings = self.missing_from_output(
client_aea_process, check_strings, is_terminating=False
)
assert (
missing_strings == []
), "Strings {} didn't appear in client_aea output.".format(missing_strings)
self.terminate_agents(deploy_aea_process, client_aea_process)
assert (
self.is_successfully_terminated()
), "Agents weren't successfully terminated."
wait_for_localhost_ports_to_close([9000, 9001])
|
1e21ed60ec90190c780e2cf6ea556eac8f1defe7
|
15bb24d3230708b21bf76805ea2f8f04c24279f7
|
/mikeio/spatial/_grid_geometry.py
|
8f82ba60d3a8c5eca140dc65d528925328b8bc42
|
[
"BSD-3-Clause"
] |
permissive
|
DHI/mikeio
|
f4f3386a6adad9494714563bd20e43b3c122800d
|
61cff247b779d39213a0588701eaaea472822d0c
|
refs/heads/main
| 2023-08-31T20:47:26.427063
| 2023-08-23T08:09:52
| 2023-08-23T08:09:52
| 168,518,417
| 120
| 53
|
BSD-3-Clause
| 2023-09-12T06:29:49
| 2019-01-31T12:02:57
|
Python
|
UTF-8
|
Python
| false
| false
| 39,712
|
py
|
_grid_geometry.py
|
from __future__ import annotations
import warnings
from typing import Optional, Sequence, Tuple
from dataclasses import dataclass
import numpy as np
from mikecore.Projections import Cartography # type: ignore
from ..exceptions import OutsideModelDomainError
from ._geometry import (
BoundingBox,
GeometryPoint2D,
GeometryPoint3D,
GeometryUndefined,
_Geometry,
)
def _check_equidistant(x: np.ndarray) -> None:
d = np.diff(x)
if len(d) > 0 and not np.allclose(d, d[0]):
raise NotImplementedError("values must be equidistant")
def _parse_grid_axis(name, x, x0=0.0, dx=None, nx=None):
if x is not None:
x = np.asarray(x)
_check_equidistant(x)
if len(x) > 1 and x[0] > x[-1]:
raise ValueError(f"{name} values must be increasing")
x0 = x[0]
dx = x[1] - x[0] if len(x) > 1 else 1.0
nx = len(x)
else:
if nx is None:
raise ValueError(f"n{name} must be provided")
if dx is None:
raise ValueError(f"d{name} must be provided")
if dx <= 0:
raise ValueError(f"d{name} must be positive")
return x0, dx, nx
def _print_axis_txt(name, x, dx) -> str:
n = len(x)
txt = f"{name}: [{x[0]:0.4g}"
if n > 1:
txt = txt + f", {x[1]:0.4g}"
if n == 3:
txt = txt + f", {x[2]:0.4g}"
if n > 3:
txt = txt + f", ..., {x[-1]:0.4g}"
txt = txt + f"] (n{name}={n}, d{name}={dx:0.4g})"
return txt
@dataclass
class Grid1D(_Geometry):
"""1D grid (node-based)
axis is increasing and equidistant
Parameters
----------
x : array_like
node coordinates
x0 : float
first node coordinate
dx : float
grid spacing
nx : int
number of nodes
projection : str
projection string
origin : tuple
not commonly used
orientation : float
not commonly used
Examples
--------
>>> mikeio.Grid1D(nx=3,dx=0.1)
<mikeio.Grid1D>
x: [0, 0.1, 0.2] (nx=3, dx=0.1)
>>> mikeio.Grid1D(x=[0.1, 0.5, 0.9])
<mikeio.Grid1D>
x: [0.1, 0.5, 0.9] (nx=3, dx=0.4)
"""
_dx: float
_nx: int
_x0: float
_orientation: float
_origin: Tuple[float, float]
_projstr: str
def __init__(
self,
x=None,
*,
x0=0.0,
dx=None,
nx=None,
projection="NON-UTM",
origin: Tuple[float, float] = (0.0, 0.0),
orientation=0.0,
node_coordinates=None,
axis_name="x",
):
"""Create equidistant 1D spatial geometry"""
super().__init__(projection)
self._origin = (0.0, 0.0) if origin is None else (origin[0], origin[1])
assert len(self._origin) == 2, "origin must be a tuple of length 2"
self._orientation = orientation
self._x0, self._dx, self._nx = _parse_grid_axis("x", x, x0, dx, nx)
if node_coordinates is not None and len(node_coordinates) != self.nx:
raise ValueError("Length of node_coordinates must be n")
self._nc = node_coordinates
self._axis_name = axis_name
@property
def ndim(self) -> int:
return 1
def __repr__(self):
out = ["<mikeio.Grid1D>", _print_axis_txt("x", self.x, self.dx)]
return "\n".join(out)
def __str__(self):
return f"Grid1D (n={self.nx}, dx={self.dx:.4g})"
def find_index(self, x: float, **kwargs) -> int:
"""Find nearest point"""
d = (self.x - x) ** 2
return int(np.argmin(d))
def get_spatial_interpolant(self, coords, **kwargs):
x = coords[0][0] # TODO accept list of points
assert self.nx > 1, "Interpolation not possible for Grid1D with one point"
d = np.abs(self.x - x)
ids = np.argsort(d)[0:2]
if x > self.x.max() or x < self.x.min():
weights = np.array([np.nan, np.nan])
else:
weights = 1 - d[ids] / d[ids].sum()
assert np.allclose(weights.sum(), 1.0)
assert len(ids) == 2
assert len(weights) == 2
return ids, weights
def interp(self, data, ids, weights):
return np.dot(data[:, ids], weights)
@property
def dx(self) -> float:
"""grid spacing"""
return self._dx
@property
def x(self):
"""array of node coordinates"""
x1 = self._x0 + self.dx * (self.nx - 1)
return np.linspace(self._x0, x1, self.nx)
@property
def nx(self) -> int:
"""number of grid points"""
return self._nx
@property
def origin(self) -> Tuple[float, float]:
return self._origin
@property
def orientation(self) -> float:
return self._orientation
def isel(
self, idx, axis=None
) -> "Grid1D" | GeometryPoint2D | GeometryPoint3D | GeometryUndefined:
"""Get a subset geometry from this geometry
Parameters
----------
idx : int or slice
index or slice
axis : int, optional
Not used for Grid1D, by default None
Returns
-------
GeometryPoint2D or GeometryPoint3D or GeometryUndefined
The geometry of the selected point
Examples
--------
>>> g = mikeio.Grid1D(nx=3,dx=0.1)
>>> g
<mikeio.Grid1D>
x: [0, 0.1, 0.2] (nx=3, dx=0.1)
>>> g.isel([1,2])
<mikeio.Grid1D>
x: [0.1, 0.2] (nx=2, dx=0.1)
>>> g.isel(1)
GeometryUndefined()
"""
if not np.isscalar(idx):
nc = None if self._nc is None else self._nc[idx, :]
return Grid1D(
x=self.x[idx],
projection=self.projection,
origin=self.origin,
orientation=self.orientation,
node_coordinates=nc,
)
if self._nc is None:
return GeometryUndefined()
else:
coords = self._nc[idx, :]
if len(coords) == 3:
return GeometryPoint3D(*coords)
else:
return GeometryPoint2D(*coords)
class _Grid2DPlotter:
"""Plot GeometryFM
Examples
--------
>>> ds = mikeio.read("tests/testdata/waves.dfs2")
>>> g = ds.geometry
>>> ax = g.plot()
>>> ax = g.plot.outline()
"""
def __init__(self, geometry: "Grid2D") -> None:
self.g = geometry
def __call__(self, ax=None, figsize=None, **kwargs):
"""Plot bathymetry as coloured patches"""
ax = self._get_ax(ax, figsize)
return self._plot_grid(ax, **kwargs)
@staticmethod
def _get_ax(ax=None, figsize=None):
import matplotlib.pyplot as plt # type: ignore
if ax is None:
_, ax = plt.subplots(figsize=figsize)
return ax
def _plot_grid(self, ax, title=None, color="0.5", linewidth=0.6, **kwargs):
g = self.g
xn = g._centers_to_nodes(g.x)
yn = g._centers_to_nodes(g.y)
for yj in yn:
ax.plot(
xn, yj * np.ones_like(xn), color=color, linewidth=linewidth, **kwargs
)
for xj in xn:
ax.plot(
xj * np.ones_like(yn), yn, color=color, linewidth=linewidth, **kwargs
)
if title is not None:
ax.set_title(title)
self._set_aspect_and_labels(ax)
return ax
def outline(
self,
title="Outline",
ax=None,
figsize=None,
color="0.4",
linewidth=1.2,
**kwargs,
):
"""Plot Grid2D outline"""
ax = self._get_ax(ax, figsize)
g = self.g
xn = g._centers_to_nodes(g.x)
yn = g._centers_to_nodes(g.y)
for yj in [yn[0], yn[-1]]:
ax.plot(
xn, yj * np.ones_like(xn), color=color, linewidth=linewidth, **kwargs
)
for xj in [xn[0], xn[-1]]:
ax.plot(
xj * np.ones_like(yn), yn, color=color, linewidth=linewidth, **kwargs
)
if title is not None:
ax.set_title(title)
self._set_aspect_and_labels(ax)
return ax
def _set_aspect_and_labels(self, ax):
g = self.g
if g.is_spectral:
ax.set_xlabel("Frequency [Hz]")
ax.set_ylabel("Directions [degree]")
elif g._is_rotated:
ax.set_xlabel("[m]")
ax.set_ylabel("[m]")
elif g.projection == "NON-UTM":
ax.set_xlabel("[m]")
ax.set_ylabel("[m]")
elif g.is_geo:
ax.set_xlabel("Longitude [degrees]")
ax.set_ylabel("Latitude [degrees]")
mean_lat = np.mean(g.y)
aspect_ratio = 1.0 / np.cos(np.pi * mean_lat / 180)
ax.set_aspect(aspect_ratio)
else:
ax.set_xlabel("Easting [m]")
ax.set_ylabel("Northing [m]")
ax.set_aspect("equal")
@dataclass
class Grid2D(_Geometry):
"""2D grid
Origin in the center of cell in lower-left corner
x and y axes are increasing and equidistant
"""
_dx: float
_nx: int
_x0: float
_dy: float
_ny: int
_y0: float
_projstr: str
_origin: Tuple[float, float]
_orientation: float
is_spectral: bool
def __init__(
self,
*,
x: Optional[Sequence[float]] = None,
x0: float = 0.0,
dx: Optional[float] = None,
nx: Optional[int] = None,
y: Optional[Sequence[float]] = None,
y0: float = 0.0,
dy: Optional[float] = None,
ny: Optional[int] = None,
bbox=None,
projection="NON-UTM",
origin: Optional[Tuple[float, float]] = None,
orientation=0.0,
axis_names=("x", "y"),
is_spectral=False,
):
"""Create equidistant 2D spatial geometry
Parameters
----------
x : array_like, optional
x coordinates of cell centers
x0 : float, optional
x coordinate of lower-left corner of first cell
dx : float, optional
x cell size
nx : int, optional
number of cells in x direction
y : array_like, optional
y coordinates of cell centers
y0 : float, optional
y coordinate of lower-left corner of first cell
dy : float, optional
y cell size
ny : int, optional
number of cells in y direction
bbox : tuple, optional
(x0, y0, x1, y1) of bounding box
projection : str, optional
projection string, by default "NON-UTM"
origin : tuple, optional
user-defined origin, by default None
orientation : float, optional
rotation angle in degrees, by default 0.0
axis_names : tuple, optional
names of x and y axes, by default ("x", "y")
is_spectral : bool, optional
if True, the grid is spectral, by default False
Examples
--------
>>> mikeio.Grid2D(x0=12.0, nx=2, dx=0.25, y0=55.0, ny=3, dy=0.25, projection="LONG/LAT")
<mikeio.Grid2D>
x: [12, 12.25] (nx=2, dx=0.25)
y: [55, 55.25, 55.5] (ny=3, dy=0.25)
projection: LONG/LAT
"""
super().__init__(projection)
self._shift_origin_on_write = origin is None # user-constructed
self._origin = (0.0, 0.0) if origin is None else (origin[0], origin[1])
assert len(self._origin) == 2, "origin must be a tuple of length 2"
self._orientation = orientation
self.__xx = None
self.__yy = None
self._axis_names = axis_names
if bbox is not None:
if (x0 != 0.0) or (y0 != 0.0):
raise ValueError("x0,y0 cannot be provided together with bbox")
self._create_in_bbox(bbox, dx=dx, dy=dy, nx=nx, ny=ny)
else:
self._x0, self._dx, self._nx = _parse_grid_axis("x", x, x0, dx, nx)
dy = self._dx if dy is None else dy
self._y0, self._dy, self._ny = _parse_grid_axis("y", y, y0, dy, ny)
self.is_spectral = is_spectral
self.plot = _Grid2DPlotter(self)
@property
def ndim(self) -> int:
return 2
@property
def _is_rotated(self):
return np.abs(self._orientation) > 1e-5
def _create_in_bbox(self, bbox, dx=None, dy=None, nx=None, ny=None):
"""create 2d grid in bounding box, specifying spacing or shape
Parameters
----------
bbox : array(float)
[left, bottom, right, top] =
[x0-dx/2, y0-dy/2, x1+dx/2, y1+dy/2]
dx : float, optional
grid resolution in x-direction,
will overwrite left and right if given
dy : float, optional
grid resolution in y-direction,
will overwrite bottom and top if given
nx : int, optional
number of points in x-direction can be None,
in which case the value will be inferred
ny : int, optional
number of points in y-direction can be None,
in which case the value will be inferred
"""
left, bottom, right, top = self._parse_bbox(bbox)
xr = right - left # dx too large
yr = top - bottom # dy too large
if (dx is None and dy is None) and (nx is None and ny is None):
if xr <= yr:
nx = 10
ny = int(np.ceil(nx * yr / xr))
else:
ny = 10
nx = int(np.ceil(ny * xr / yr))
if nx is None and ny is not None:
nx = int(np.ceil(ny * xr / yr))
if ny is None and nx is not None:
ny = int(np.ceil(nx * yr / xr))
if isinstance(dx, tuple):
dx, dy = dx
dy = dx if dy is None else dy
self._x0, self._dx, self._nx = self._create_in_bbox_1d("x", left, right, dx, nx)
self._y0, self._dy, self._ny = self._create_in_bbox_1d("y", bottom, top, dy, ny)
@staticmethod
def _parse_bbox(bbox):
left = bbox[0]
bottom = bbox[1]
right = bbox[2]
top = bbox[3]
if left > right:
raise (
ValueError(
f"Invalid x axis, left: {left} must be smaller than right: {right}"
)
)
if bottom > top:
raise (
ValueError(
f"Invalid y axis, bottom: {bottom} must be smaller than top: {top}"
)
)
return left, bottom, right, top
@staticmethod
def _create_in_bbox_1d(axname, left, right, dx=None, nx=None):
xr = right - left
if dx is not None:
nx = int(np.ceil(xr / dx))
# overwrite left and right! to make dx fit
xcenter = left + xr / 2
left = xcenter - dx * nx / 2
right = xcenter + dx * nx / 2
elif nx is not None:
dx = xr / nx
else:
raise ValueError(f"Provide either d{axname} or n{axname}")
x0 = left + dx / 2
return x0, dx, nx
def __repr__(self):
out = (
["<mikeio.Grid2D> (spectral)"] if self.is_spectral else ["<mikeio.Grid2D>"]
)
out.append(_print_axis_txt("x", self.x, self.dx))
out.append(_print_axis_txt("y", self.y, self.dy))
if self._is_rotated:
ox, oy = self.origin
out.append(
f"origin: ({ox:.4g}, {oy:.4g}), orientation: {self._orientation:.3f}"
)
if self.projection_string:
out.append(f"projection: {self.projection_string}")
return "\n".join(out)
def __str__(self):
return f"Grid2D (ny={self.ny}, nx={self.nx})"
@property
def dx(self) -> float:
"""x grid spacing"""
return self._dx
@property
def dy(self) -> float:
"""y grid spacing"""
return self._dy
@property
def x(self):
"""array of x coordinates (element center)"""
if self.is_spectral and self.dx > 1:
return self._logarithmic_f(self.nx, self._x0, self.dx)
x1 = self._x0 + self.dx * (self.nx - 1)
x_local = np.linspace(self._x0, x1, self.nx)
if self._is_rotated or self.is_spectral:
return x_local
else:
return x_local + self._origin[0]
@staticmethod
def _logarithmic_f(n=25, f0=0.055, freq_factor=1.1):
"""Generate logarithmic frequency axis
Parameters
----------
n : int, optional
number of frequencies, by default 25
f0 : float, optional
Minimum frequency, by default 0.055
freq_factor : float, optional
Frequency factor, by default 1.1
Returns
-------
np.ndarray
array of logarithmic distributed discrete frequencies
"""
logf0 = np.log(f0)
logdf = np.log(f0 * freq_factor) - logf0
logf = logf0 + logdf * np.arange(n)
return np.exp(logf)
@property
def y(self):
"""array of y coordinates (element center)"""
y1 = self._y0 + self.dy * (self.ny - 1)
y_local = np.linspace(self._y0, y1, self.ny)
return y_local if self._is_rotated else y_local + self._origin[1]
@property
def nx(self) -> int:
"""number of x grid points"""
return self._nx
@property
def ny(self) -> int:
"""number of y grid points"""
return self._ny
@property
def origin(self) -> Tuple[float, float]:
"""Coordinates of grid origo (in projection)"""
return self._origin
@property
def orientation(self) -> float:
"""Grid orientation"""
return self._orientation
@property
def bbox(self):
"""bounding box (left, bottom, right, top)
Note: not the same as the cell center values (x0,y0,x1,y1)!
"""
if self._is_rotated:
raise NotImplementedError("Only available if orientation = 0")
if self.is_spectral:
raise NotImplementedError("Not available for spectral Grid2D")
left = self.x[0] - self.dx / 2
bottom = self.y[0] - self.dy / 2
right = self.x[-1] + self.dx / 2
top = self.y[-1] + self.dy / 2
return BoundingBox(left, bottom, right, top)
@property
def _xx(self):
"""2d array of all x-coordinates"""
if self.__xx is None:
self._create_meshgrid(self.x, self.y)
return self.__xx
@property
def _yy(self):
"""2d array of all y-coordinates"""
if self.__yy is None:
self._create_meshgrid(self.x, self.y)
return self.__yy
def _create_meshgrid(self, x, y):
self.__xx, self.__yy = np.meshgrid(x, y)
@property
def xy(self):
"""n-by-2 array of x- and y-coordinates"""
xcol = self._xx.reshape(-1, 1)
ycol = self._yy.reshape(-1, 1)
return np.column_stack([xcol, ycol])
@property
def coordinates(self):
# TODO: remove this?
"""n-by-2 array of x- and y-coordinates"""
return self.xy
@property
def _cart(self):
"""MIKE Core Cartography object"""
factory = (
Cartography.CreateGeoOrigin if self.is_geo else Cartography.CreateProjOrigin
)
return factory(self.projection_string, *self.origin, self.orientation)
def _shift_x0y0_to_origin(self):
"""Shift spatial axis to start at (0,0) adding the start to origin instead
Note: this will not change the x or y properties.
"""
if self._is_rotated:
raise ValueError("Only possible if orientation = 0")
# TODO: needs testing
# i0, j0 = self._x0/self.dx, self._y0/self.dy
# self._x0, self._y0 = 0.0, 0.0
# self._origin = self._cart.Xy2Proj(i0, j0)
elif self.is_spectral:
raise ValueError("Not possible for spectral Grid2D")
else:
x0, y0 = self._x0, self._y0
self._x0, self._y0 = 0.0, 0.0
self._origin = (self._origin[0] + x0, self._origin[1] + y0)
def contains(self, coords):
"""test if a list of points are inside grid
Parameters
----------
coords : array(float)
xy-coordinate of points given as n-by-2 array
Returns
-------
bool array
True for points inside, False otherwise
"""
coords = np.atleast_2d(coords)
y = coords[:, 1]
x = coords[:, 0]
xinside = (self.bbox.left <= x) & (x <= self.bbox.right)
yinside = (self.bbox.bottom <= y) & (y <= self.bbox.top)
return xinside & yinside
def __contains__(self, pt) -> bool:
return self.contains(pt)
def find_index(
self,
x: Optional[float] = None,
y: Optional[float] = None,
coords=None,
area=None,
):
"""Find nearest index (i,j) of point(s)
Parameters
----------
x : float
x-coordinate of point
y : float
y-coordinate of point
coords : array(float)
xy-coordinate of points given as n-by-2 array
area : array(float)
xy-coordinates of bounding box
Returns
-------
array(int), array(int)
i- and j-index of nearest cell
Raises
------
ValueError if x or y are not scalar values, use coords instead
OutsideModelDomainError if point is outside grid
"""
if x is None and y is not None and not np.isscalar(y):
raise ValueError(
f"{y=} is not a scalar value, use the coords argument instead"
)
if y is None and x is not None and not np.isscalar(x):
raise ValueError(
f"{x=} is not a scalar value, use the coords argument instead"
)
if x is not None and y is not None:
if coords is not None:
raise ValueError("x,y and coords cannot be given at the same time!")
coords = np.column_stack([np.atleast_1d(x), np.atleast_1d(y)])
elif x is not None:
return np.atleast_1d(np.argmin(np.abs(self.x - x))), None
elif y is not None:
return None, np.atleast_1d(np.argmin(np.abs(self.y - y)))
if coords is not None:
return self._xy_to_index(coords)
elif area is not None:
return self._bbox_to_index(area)
def _xy_to_index(self, xy):
"""Find specific points in this geometry"""
xy = np.atleast_2d(xy)
y = xy[:, 1]
x = xy[:, 0]
ii = (-999999999) * np.ones_like(x, dtype=int)
jj = (-999999999) * np.ones_like(y, dtype=int)
inside = self.contains(xy)
if np.any(~inside):
raise OutsideModelDomainError(x=x[~inside], y=y[~inside])
# get index in x, and y for points inside based on the grid spacing and origin
ii = np.floor((x - (self.x[0] - self.dx / 2)) / self.dx).astype(int)
jj = np.floor((y - (self.y[0] - self.dy / 2)) / self.dy).astype(int)
return ii, jj
def _bbox_to_index(
self, bbox: Tuple[float,float,float,float] | BoundingBox
) -> Tuple[range, range]:
"""Find subarea within this geometry"""
if not (len(bbox) == 4):
raise ValueError(
"area most be a bounding box of coordinates e.g. area=(-10.0, 10.0 20.0, 30.0)"
)
x0, y0, x1, y1 = bbox
if x0 > self.x[-1] or y0 > self.y[-1] or x1 < self.x[0] or y1 < self.y[0]:
raise ValueError("area is outside grid")
mask = (self.x >= x0) & (self.x <= x1)
ii = np.where(mask)[0]
mask = (self.y >= y0) & (self.y <= y1)
jj = np.where(mask)[0]
i = range(ii[0], ii[-1] + 1)
j = range(jj[0], jj[-1] + 1)
return i, j
def isel(
self, idx, axis: int | str
) -> "Grid2D" | "Grid1D" | "GeometryUndefined":
"""Return a new geometry as a subset of Grid2D along the given axis."""
if isinstance(axis, str):
if axis == "y":
axis = 0
elif axis == "x":
axis = 1
else:
raise ValueError(f"axis must be 'x' or 'y', not {axis}")
assert isinstance(axis, int), "axis must be an integer (or 'x' or 'y')"
axis = axis + 2 if axis < 0 else axis
if not np.isscalar(idx):
d = np.diff(idx)
if np.any(d < 1) or not np.allclose(d, d[0]):
return GeometryUndefined()
else:
ii = idx if axis == 1 else None
jj = idx if axis == 0 else None
return self._index_to_Grid2D(ii, jj)
if axis == 0:
# y is first axis! if we select an element from y-axis (axis 0),
# we return a "copy" of the x-axis
nc = np.column_stack([self.x, self.y[idx] * np.ones_like(self.x)])
return Grid1D(x=self.x, projection=self.projection, node_coordinates=nc)
elif axis == 1:
nc = np.column_stack([self.x[idx] * np.ones_like(self.y), self.y])
return Grid1D(
x=self.y, projection=self.projection, node_coordinates=nc, axis_name="y"
)
else:
raise ValueError(f"axis must be 0 or 1 (or 'x' or 'y'), not {axis}")
def _index_to_Grid2D(self, ii=None, jj=None):
ii = range(self.nx) if ii is None else ii
jj = range(self.ny) if jj is None else jj
assert len(ii) > 1 and len(jj) > 1, "Index must be at least len 2"
assert ii[-1] < self.nx and jj[-1] < self.ny, "Index out of bounds"
di = np.diff(ii)
dj = np.diff(jj)
if (np.any(di < 1) or not np.allclose(di, di[0])) or (
np.any(dj < 1) or not np.allclose(dj, dj[0])
):
warnings.warn("Axis not equidistant! Will return GeometryUndefined()")
return GeometryUndefined()
else:
dx = self.dx * di[0]
dy = self.dy * dj[0]
x0 = self._x0 + (self.x[ii[0]] - self.x[0])
y0 = self._y0 + (self.y[jj[0]] - self.y[0])
origin = None if self._shift_origin_on_write else self.origin
# if not self._is_rotated and not self._shift_origin_on_write:
if self._is_rotated:
origin = self._cart.Xy2Proj(ii[0], jj[0])
# what about the orientation if is_geo??
# orientationGeo = proj.Proj2GeoRotation(east, north, orientationProj)
x0, y0 = (0.0, 0.0)
elif not self.is_spectral:
origin = (self.origin[0] + x0, self.origin[1] + y0)
x0, y0 = (0.0, 0.0)
return Grid2D(
x0=x0,
y0=y0,
dx=dx,
dy=dy,
nx=len(ii),
ny=len(jj),
projection=self.projection,
orientation=self._orientation,
is_spectral=self.is_spectral,
origin=origin,
)
def _to_element_table(self, index_base=0):
elem_table = []
for elx in range(self.nx - 1):
# each col
for ely in range(self.ny - 1):
# each row (in this col)
n1 = ely * self.nx + elx + index_base
n2 = (ely + 1) * self.nx + elx + index_base
elem_table.append([n1, n1 + 1, n2 + 1, n2])
return elem_table
@staticmethod
def _centers_to_nodes(x):
"""Nodes will be placed mid-way between centers
If non-equidistant, new centers will hence not equal old centers!
"""
if len(x) == 1:
return np.array([x[0] - 0.5, x[0] + 0.5])
xinner = (x[1:] + x[:-1]) / 2
left = x[0] - (x[1] - x[0]) / 2
right = x[-1] + (x[-1] - x[-2]) / 2
return np.array([left, *xinner, right])
@staticmethod
def _nodes_to_centers(xn):
return (xn[1:] + xn[:-1]) / 2
def get_node_coordinates(self):
"""node coordinates for this grid
Returns
-------
array(float)
2d array with x,y-coordinates, length=(nx+1)*(ny+1)
"""
xn = self._centers_to_nodes(self.x)
yn = self._centers_to_nodes(self.y)
gn = Grid2D(x=xn, y=yn)
return gn.xy
def to_geometryFM(self, *, z=None, west=2, east=4, north=5, south=3):
"""convert Grid2D to GeometryFM
Parameters
----------
z : float, optional
bathymetry values for each node, by default 0
west: int, optional
code value for west boundary
east: int, optional
code value for east boundary
north: int, optional
code value for north boundary
south: int, optional
code value for south boundary
"""
from mikeio.spatial._FM_geometry import GeometryFM2D
# get node based grid
xn = self._centers_to_nodes(self.x)
yn = self._centers_to_nodes(self.y)
gn = Grid2D(x=xn, y=yn)
# node coordinates
x = gn.xy[:, 0]
y = gn.xy[:, 1]
n = gn.nx * gn.ny
zn = np.zeros_like(x)
if z is not None:
zn[:] = z
codes = np.zeros(n, dtype=int)
codes[y == y[-1]] = north
codes[x == x[-1]] = east
codes[y == y[0]] = south
codes[x == x[0]] = west
codes[(y == y[-1]) & (x == x[0])] = 5 # corner->north
nc = np.column_stack([x, y, zn])
elem_table = gn._to_element_table(index_base=0)
return GeometryFM2D(
node_coordinates=nc,
element_table=elem_table,
codes=codes,
projection=self.projection,
)
def to_mesh(self, outfilename, z=None):
"""export grid to mesh file
Parameters
----------
outfilename : str
path of new mesh file
z : float or array(float), optional
bathymetry values for each node, by default 0
if array: must have length=(nx+1)*(ny+1)
"""
g = self.to_geometryFM()
if z is not None:
if not np.isscalar(z):
if len(z) != g.n_nodes:
raise ValueError(
"z must either be scalar or have length of nodes ((nx+1)*(ny+1))"
)
g.node_coordinates[:, 2] = z
g.to_mesh(outfilename=outfilename)
@dataclass
class Grid3D(_Geometry):
"""3D grid
Origin in the center of cell in lower-left corner
x, y and z axes are increasing and equidistant
"""
_dx: float
_nx: int
_x0: float
_dy: float
_ny: int
_y0: float
_dz: float
_nz: int
_z0: float
_projstr: str
_origin: Tuple[float, float]
_orientation: float
def __init__(
self,
*,
x=None,
x0=0.0,
dx=None,
nx=None,
y=None,
y0=0.0,
dy=None,
ny=None,
z=None,
z0=0.0,
dz=None,
nz=None,
projection="NON-UTM",
origin: Tuple[float, float] = (0.0, 0.0),
orientation=0.0,
) -> None:
super().__init__()
self._origin = (0.0, 0.0) if origin is None else (origin[0], origin[1])
assert len(self._origin) == 2, "origin must be a tuple of length 2"
self._x0, self._dx, self._nx = _parse_grid_axis("x", x, x0, dx, nx)
self._y0, self._dy, self._ny = _parse_grid_axis("y", y, y0, dy, ny)
self._z0, self._dz, self._nz = _parse_grid_axis("z", z, z0, dz, nz)
self._projstr = projection # TODO handle other types than string
self._origin = origin
self._orientation = orientation
@property
def ndim(self) -> int:
return 3
@property
def _is_rotated(self):
return np.abs(self._orientation) > 1e-5
@property
def x(self):
"""array of x-axis coordinates (element center)"""
x1 = self._x0 + self.dx * (self.nx - 1)
x_local = np.linspace(self._x0, x1, self.nx)
return x_local if self._is_rotated else x_local + self.origin[0]
@property
def dx(self) -> float:
"""x-axis grid spacing"""
return self._dx
@property
def nx(self) -> int:
"""number of x grid points"""
return self._nx
@property
def y(self):
"""array of y-axis coordinates (element center)"""
y1 = self._y0 + self.dy * (self.ny - 1)
y_local = np.linspace(self._y0, y1, self.ny)
return y_local if self._is_rotated else y_local + self.origin[1]
@property
def dy(self) -> float:
"""y-axis grid spacing"""
return self._dy
@property
def ny(self) -> int:
"""number of y grid points"""
return self._ny
@property
def z(self):
"""array of z-axis node coordinates"""
z1 = self._z0 + self.dz * (self.nz - 1)
return np.linspace(self._z0, z1, self.nz)
@property
def dz(self) -> float:
"""z-axis grid spacing"""
return self._dz
@property
def nz(self) -> int:
"""number of z grid points"""
return self._nz
@property
def origin(self) -> Tuple[float, float]:
"""Coordinates of grid origo (in projection)"""
return self._origin
@property
def orientation(self) -> float:
"""Grid orientation"""
return self._orientation
def find_index(self, coords=None, layers=None, area=None):
if layers is not None:
raise NotImplementedError(
f"Layer slicing is not yet implemented. Use the mikeio.read('file.dfs3', layers='{layers}')"
)
raise NotImplementedError(
"Not yet implemented for Grid3D. Please use mikeio.read('file.dfs3') and its arguments instead."
)
def isel(self, idx, axis):
"""Get a subset geometry from this geometry"""
if isinstance(axis, str):
if axis == "z":
axis = 0
elif axis == "y":
axis = 1
elif axis == "x":
axis = 2
else:
raise ValueError(f"axis must be 'x', 'y' or 'z', not {axis}")
assert isinstance(axis, int), "axis must be an integer (or 'x', 'y' or 'z')"
axis = axis + 3 if axis < 0 else axis
if not np.isscalar(idx):
d = np.diff(idx)
if np.any(d < 1) or not np.allclose(d, d[0]):
return GeometryUndefined()
else:
ii = idx if axis == 2 else None
jj = idx if axis == 1 else None
kk = idx if axis == 0 else None
return self._index_to_Grid3D(ii, jj, kk)
if axis == 0:
# z is the first axis! return x-y Grid2D
# TODO: origin, how to pass self.z[idx]?
return Grid2D(
x0=self._x0,
y0=self._y0,
nx=self.nx,
ny=self.ny,
dx=self.dx,
dy=self.dy,
projection=self.projection,
origin=self.origin,
orientation=self.orientation,
)
elif axis == 1:
# y is the second axis! return x-z Grid2D
# TODO: origin, how to pass self.y[idx]?
return Grid2D(
x=self.x,
y=self.z,
# projection=self._projection,
)
elif axis == 2:
# x is the last axis! return y-z Grid2D
# TODO: origin, how to pass self.x[idx]?
return Grid2D(
x=self.y,
y=self.z,
# projection=self._projection,
)
else:
raise ValueError(f"axis must be 0, 1 or 2 (or 'x', 'y' or 'z'), not {axis}")
def _index_to_Grid3D(self, ii=None, jj=None, kk=None):
ii = range(self.nx) if ii is None else ii
jj = range(self.ny) if jj is None else jj
kk = range(self.nz) if kk is None else kk
assert (
len(ii) > 1 and len(jj) > 1 and len(kk) > 1
), "Index must be at least len 2"
assert (
ii[-1] < self.nx and jj[-1] < self.ny and kk[-1] < self.nz
), "Index out of bounds"
di = np.diff(ii)
dj = np.diff(jj)
dk = np.diff(kk)
if (
(np.any(di < 1) or not np.allclose(di, di[0]))
or (np.any(dj < 1) or not np.allclose(dj, dj[0]))
or (np.any(dk < 1) or not np.allclose(dk, dk[0]))
):
warnings.warn("Axis not equidistant! Will return GeometryUndefined()")
return GeometryUndefined()
else:
dx = self.dx * di[0]
dy = self.dy * dj[0]
dz = self.dz * dk[0]
x0 = self._x0 + (self.x[ii[0]] - self.x[0])
y0 = self._y0 + (self.y[jj[0]] - self.y[0])
z0 = self._z0 + (self.z[kk[0]] - self.z[0])
if self._is_rotated:
# rotated => most be projected
cart = Cartography.CreateProjOrigin(
self.projection, *self.origin, self.orientation
)
origin = cart.Xy2Proj(ii[0], jj[0])
else:
origin = (self.origin[0] + x0, self.origin[1] + y0)
x0, y0 = (0.0, 0.0)
return Grid3D(
x0=x0,
y0=y0,
z0=z0,
dx=dx,
dy=dy,
dz=dz,
nx=len(ii),
ny=len(jj),
nz=len(kk),
projection=self.projection,
orientation=self.orientation,
origin=origin,
)
def __repr__(self):
out = ["<mikeio.Grid3D>"]
out.append(_print_axis_txt("x", self.x, self.dx))
out.append(_print_axis_txt("y", self.y, self.dy))
out.append(_print_axis_txt("z", self.z, self.dz))
out.append(
f"origin: ({self._origin[0]:.4g}, {self._origin[1]:.4g}), orientation: {self._orientation:.3f}"
)
if self.projection_string:
out.append(f"projection: {self.projection_string}")
return "\n".join(out)
def __str__(self):
return f"Grid3D(nz={self.nz}, ny={self.ny}, nx={self.nx})"
def _geometry_for_layers(
self, layers, keepdims=False
) -> Grid2D | "Grid3D" | "GeometryUndefined":
if layers is None:
return self
g = self
if len(layers) == 1 and not keepdims:
geometry_2d = Grid2D(
dx=g._dx,
dy=g._dy,
nx=g._nx,
ny=g._ny,
x0=g._x0,
y0=g._y0,
origin=g.origin,
projection=g._projstr,
orientation=g.orientation,
)
return geometry_2d
d = np.diff(g.z[layers])
if len(d) > 0:
if np.any(d < 1) or not np.allclose(d, d[0]):
warnings.warn("Extracting non-equidistant layers! Cannot use Grid3D.")
return GeometryUndefined()
geometry = Grid3D(
x=g.x,
y=g.y,
z=g.z[layers],
origin=g._origin,
projection=g.projection,
orientation=g.orientation,
)
return geometry
|
8f6dbaafa46551155b6c543c12a3b8a38c13b801
|
8e68fa08e0275bb77a57f2dcb1b2082afbd928e9
|
/src/cutadapt/utils.py
|
79092e4e562f41e581a929eaac83d7d0f1843ab6
|
[
"MIT"
] |
permissive
|
marcelm/cutadapt
|
a892a871ed8b5b8491c2177ede43a6ebe0b43810
|
cefb3e0bc6bacf5e15a842174502852466bd6990
|
refs/heads/main
| 2023-09-01T08:14:21.694545
| 2023-08-31T08:18:46
| 2023-08-31T08:18:46
| 4,577,614
| 450
| 165
|
MIT
| 2023-09-11T06:48:19
| 2012-06-06T20:26:25
|
Python
|
UTF-8
|
Python
| false
| false
| 3,956
|
py
|
utils.py
|
import re
import sys
import time
import multiprocessing
import logging
logger = logging.getLogger(__name__)
def available_cpu_count():
"""
Return the number of available virtual or physical CPUs on this system.
The number of available CPUs can be smaller than the total number of CPUs
when the cpuset(7) mechanism is in use, as is the case on some cluster
systems.
Adapted from http://stackoverflow.com/a/1006301/715090
"""
try:
with open("/proc/self/status") as f:
status = f.read()
m = re.search(r"(?m)^Cpus_allowed:\s*(.*)$", status)
if m:
res = bin(int(m.group(1).replace(",", ""), 16)).count("1")
if res > 0:
return min(res, multiprocessing.cpu_count())
except OSError:
pass
return multiprocessing.cpu_count()
class Progress:
"""
Print an animated progress report to sys.stderr
"""
def __init__(self, every=1):
"""
every: minimum time to wait in seconds between progress updates
"""
self._every = every
self._animation = self.scissors()
self._n = 0
self._start_time = time.time()
# Time at which the progress was last updated
self._last_time = self._start_time
self._last_n = 0
def __repr__(self):
return (
f"Progress(_n={self._n}, elapsed={self._last_time - self._start_time:.3f})"
)
@staticmethod
def scissors(width=10):
while True:
for is_reverse, rang in [
(False, range(width + 1)),
(True, range(width + 1)),
]:
for position in rang:
for is_open in (True, False):
left = " " * position
right = "-" * (width - position)
if is_reverse:
sc = ">8" if is_open else "=8"
left, right = right, left
else:
sc = "8<" if is_open else "8="
yield "[" + left + sc + right + "]"
def update(self, increment, _final=False):
self._n += increment
current_time = time.time()
if _final:
time_delta = current_time - self._start_time
delta = self._n
else:
time_delta = current_time - self._last_time
delta = self._n - self._last_n
if delta < 1:
return
if time_delta == 0:
return
if not _final:
if time_delta < self._every:
return
t = current_time - self._start_time
hours = int(t) // 3600
minutes = (int(t) - hours * 3600) // 60
seconds = int(t) % 60
per_second = delta / time_delta
per_item = time_delta / delta
animation = next(self._animation)
if _final:
animation = "Done".ljust(len(animation))
print(
"\r"
"{animation} {hours:02d}:{minutes:02d}:{seconds:02d} "
"{total:13,d} reads @ {per_item:5.1F} µs/read; {per_minute:6.2F} M reads/minute"
"".format(
hours=hours,
minutes=minutes,
seconds=seconds,
total=self._n,
per_item=per_item * 1e6,
per_minute=per_second * 60 / 1e6,
animation=animation,
),
end="",
file=sys.stderr,
)
self._last_time = current_time
self._last_n = self._n
def close(self):
"""
Print final progress reflecting the final total
"""
self.update(0, _final=True)
print(file=sys.stderr)
class DummyProgress(Progress):
"""
Does not print anything
"""
def update(self, increment, _final=False):
pass
def close(self):
pass
|
ecc0e528b4fc44555f6448027b82111a50130ab9
|
a29d0a27054c1fc8d5b68f017db027243ee51664
|
/rollbar/examples/twisted/simpleserv.py
|
d2ade2d1a54980bcc14d760dda1529436f38c32e
|
[
"MIT"
] |
permissive
|
rollbar/pyrollbar
|
ea75ea43f8e5a49f2834b4f5c9b395bd919578e1
|
960b5cf55a0dc109e1329334fc290c57bdccd4dd
|
refs/heads/master
| 2023-08-31T19:14:26.979661
| 2023-08-23T11:23:48
| 2023-08-23T11:23:48
| 5,391,990
| 195
| 143
|
MIT
| 2023-09-01T22:02:08
| 2012-08-12T21:12:08
|
Python
|
UTF-8
|
Python
| false
| false
| 1,108
|
py
|
simpleserv.py
|
# Copyright (c) Twisted Matrix Laboratories.
# See LICENSE for details.
#
# From https://twistedmatrix.com/documents/current/_downloads/simpleserv.py
# NOTE: pyrollbar requires both `Twisted` and `treq` packages to be installed
from twisted.internet import reactor, protocol
import rollbar
def bar(p):
# These local variables will be sent to Rollbar and available in the UI
a = 33
b = a * 5
baz()
def foo():
hello = 'world'
bar(hello)
class Echo(protocol.Protocol):
"""This is just about the simplest possible protocol"""
def dataReceived(self, data):
"As soon as any data is received, write it back."
# Cause an uncaught exception to be sent to Rollbar
foo()
self.transport.write(data)
def main():
rollbar.init('ACCESS_TOKEN', environment='test', handler='twisted')
"""This runs the protocol on port 8000"""
factory = protocol.ServerFactory()
factory.protocol = Echo
reactor.listenTCP(8000, factory)
reactor.run()
# this only runs if the module was *not* imported
if __name__ == '__main__':
main()
|
57ad8a31b0a1fb186dba40d7e0e811785906a03c
|
7b7c570b30d6d7a0e9b904c7cb378cfb0d0f0e07
|
/tests/resources/mlflow-test-plugin/mlflow_test_plugin/file_store.py
|
3fac8d2d91697d0f3f99903868a5809fd849e52d
|
[
"Apache-2.0"
] |
permissive
|
mlflow/mlflow
|
ca97bfbbf32f8e59f454e428f5e46eb3d34d062f
|
37298ffafcd34002352d01d579d4524790544267
|
refs/heads/master
| 2023-09-01T13:15:53.902815
| 2023-09-01T09:00:42
| 2023-09-01T09:00:42
| 136,202,695
| 14,102
| 3,748
|
Apache-2.0
| 2023-09-14T21:52:42
| 2018-06-05T16:05:58
|
Python
|
UTF-8
|
Python
| false
| false
| 379
|
py
|
file_store.py
|
import urllib.parse
from mlflow.store.tracking.file_store import FileStore
class PluginFileStore(FileStore):
"""FileStore provided through entrypoints system"""
def __init__(self, store_uri=None, artifact_uri=None):
path = urllib.parse.urlparse(store_uri).path if store_uri else None
self.is_plugin = True
super().__init__(path, artifact_uri)
|
1c4df7790d72fcecfa59ac593e5a02a6baca70da
|
3ec38f732b21b0a00e822dac730bdc1748902144
|
/scar/logger.py
|
33a2bcb3d8b900cf6067a8001e80a86493af5073
|
[
"Apache-2.0"
] |
permissive
|
grycap/scar
|
e5594c1eb79a0730409c97d48bc511757a05dcbd
|
e6c8b06a43b310d2c1e58d7826239e259dd826d7
|
refs/heads/master
| 2023-08-22T00:39:28.004454
| 2023-05-22T11:01:10
| 2023-05-22T11:01:10
| 91,441,209
| 613
| 59
|
Apache-2.0
| 2022-11-29T06:36:46
| 2017-05-16T09:35:57
|
Python
|
UTF-8
|
Python
| false
| false
| 2,843
|
py
|
logger.py
|
# Copyright (C) GRyCAP - I3M - UPV
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import json
import logging
import os
log_folder_name = ".scar"
log_file_folder = os.path.join(os.path.expanduser("~"), log_folder_name)
if 'SCAR_LOG_PATH' in os.environ:
log_file_folder = os.environ['SCAR_LOG_PATH']
log_file_name = "scar.log"
log_file_path = os.path.join(log_file_folder, log_file_name)
# Create scar config dir
if not os.path.isdir(log_file_folder):
os.makedirs(log_file_folder, exist_ok=True)
loglevel = logging.INFO
FORMAT = '%(asctime)s - %(name)s - %(levelname)s - %(message)s'
logging.basicConfig(filename=log_file_path, level=loglevel, format=FORMAT)
def init_execution_trace():
logging.info('----------------------------------------------------')
logging.info('SCAR execution started')
def end_execution_trace():
logging.info('SCAR execution finished')
logging.info('----------------------------------------------------')
def end_execution_trace_with_errors():
logging.info('SCAR execution finished with errors')
logging.info('----------------------------------------------------')
def debug(cli_msg, log_msg=None):
if loglevel == logging.DEBUG:
print(cli_msg)
logging.debug(log_msg) if log_msg else logging.debug(cli_msg)
def info(cli_msg=None, log_msg=None):
if cli_msg and loglevel == logging.INFO:
print(cli_msg)
logging.info(log_msg) if log_msg else logging.info(cli_msg)
def warning(cli_msg, log_msg=None):
print(cli_msg)
logging.warning(log_msg) if log_msg else logging.warning(cli_msg)
def error(cli_msg, log_msg=None):
if log_msg:
print(log_msg)
logging.error(log_msg)
else:
print(cli_msg)
logging.error(cli_msg)
def exception(msg):
logging.exception(msg)
def log_exception(error_msg, exception):
error(error_msg, error_msg + ": {0}".format(exception))
def print_json(value):
print(json.dumps(value))
def info_json(cli_msg, log_msg=None):
print_json(cli_msg)
logging.info(log_msg) if log_msg else logging.info(cli_msg)
def warning_json(cli_msg, log_msg=None):
print_json(cli_msg)
logging.warning(log_msg) if log_msg else logging.warning(cli_msg)
def error_json(cli_msg, log_msg=None):
print_json(cli_msg)
logging.error(log_msg) if log_msg else logging.error(cli_msg)
|
832689ef09c3e484bedf0ccbe13b258c100e5064
|
993f18c21402d7a4ff21ddb7ff2ec6c80e466f20
|
/onnx/backend/test/case/node/gemm.py
|
11ff65ece06dfce48a352c45ba45d8ea7cdc1e96
|
[
"Apache-2.0"
] |
permissive
|
onnx/onnx
|
10d3916803c7babff89ec0fa9045127bcccad376
|
8a475b34cb3875df311a46f57571646498f5bda7
|
refs/heads/main
| 2023-08-18T18:50:03.388353
| 2023-08-16T22:18:46
| 2023-08-16T22:18:46
| 102,692,863
| 16,164
| 4,150
|
Apache-2.0
| 2023-09-14T17:10:38
| 2017-09-07T04:53:45
|
Python
|
UTF-8
|
Python
| false
| false
| 5,919
|
py
|
gemm.py
|
# Copyright (c) ONNX Project Contributors
#
# SPDX-License-Identifier: Apache-2.0
from typing import Optional
import numpy as np
import onnx
from onnx.backend.test.case.base import Base
from onnx.backend.test.case.node import expect
def gemm_reference_implementation(
A: np.ndarray,
B: np.ndarray,
C: Optional[np.ndarray] = None,
alpha: float = 1.0,
beta: float = 1.0,
transA: int = 0,
transB: int = 0,
) -> np.ndarray:
A = A if transA == 0 else A.T
B = B if transB == 0 else B.T
C = C if C is not None else np.array(0)
Y = alpha * np.dot(A, B) + beta * C
return Y
class Gemm(Base):
@staticmethod
def export_default_zero_bias() -> None:
node = onnx.helper.make_node("Gemm", inputs=["a", "b", "c"], outputs=["y"])
a = np.random.ranf([3, 5]).astype(np.float32)
b = np.random.ranf([5, 4]).astype(np.float32)
c = np.zeros([1, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c)
expect(node, inputs=[a, b, c], outputs=[y], name="test_gemm_default_zero_bias")
@staticmethod
def export_default_no_bias() -> None:
node = onnx.helper.make_node("Gemm", inputs=["a", "b"], outputs=["y"])
a = np.random.ranf([2, 10]).astype(np.float32)
b = np.random.ranf([10, 3]).astype(np.float32)
y = gemm_reference_implementation(a, b)
expect(node, inputs=[a, b], outputs=[y], name="test_gemm_default_no_bias")
@staticmethod
def export_default_scalar_bias() -> None:
node = onnx.helper.make_node("Gemm", inputs=["a", "b", "c"], outputs=["y"])
a = np.random.ranf([2, 3]).astype(np.float32)
b = np.random.ranf([3, 4]).astype(np.float32)
c = np.array(3.14).astype(np.float32)
y = gemm_reference_implementation(a, b, c)
expect(
node, inputs=[a, b, c], outputs=[y], name="test_gemm_default_scalar_bias"
)
@staticmethod
def export_default_single_elem_vector_bias() -> None:
node = onnx.helper.make_node("Gemm", inputs=["a", "b", "c"], outputs=["y"])
a = np.random.ranf([3, 7]).astype(np.float32)
b = np.random.ranf([7, 3]).astype(np.float32)
c = np.random.ranf([1]).astype(np.float32)
y = gemm_reference_implementation(a, b, c)
expect(
node,
inputs=[a, b, c],
outputs=[y],
name="test_gemm_default_single_elem_vector_bias",
)
@staticmethod
def export_default_vector_bias() -> None:
node = onnx.helper.make_node("Gemm", inputs=["a", "b", "c"], outputs=["y"])
a = np.random.ranf([2, 7]).astype(np.float32)
b = np.random.ranf([7, 4]).astype(np.float32)
c = np.random.ranf([1, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c)
expect(
node, inputs=[a, b, c], outputs=[y], name="test_gemm_default_vector_bias"
)
@staticmethod
def export_default_matrix_bias() -> None:
node = onnx.helper.make_node("Gemm", inputs=["a", "b", "c"], outputs=["y"])
a = np.random.ranf([3, 6]).astype(np.float32)
b = np.random.ranf([6, 4]).astype(np.float32)
c = np.random.ranf([3, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c)
expect(
node, inputs=[a, b, c], outputs=[y], name="test_gemm_default_matrix_bias"
)
@staticmethod
def export_transposeA() -> None:
node = onnx.helper.make_node(
"Gemm", inputs=["a", "b", "c"], outputs=["y"], transA=1
)
a = np.random.ranf([6, 3]).astype(np.float32)
b = np.random.ranf([6, 4]).astype(np.float32)
c = np.zeros([1, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c, transA=1)
expect(node, inputs=[a, b, c], outputs=[y], name="test_gemm_transposeA")
@staticmethod
def export_transposeB() -> None:
node = onnx.helper.make_node(
"Gemm", inputs=["a", "b", "c"], outputs=["y"], transB=1
)
a = np.random.ranf([3, 6]).astype(np.float32)
b = np.random.ranf([4, 6]).astype(np.float32)
c = np.zeros([1, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c, transB=1)
expect(node, inputs=[a, b, c], outputs=[y], name="test_gemm_transposeB")
@staticmethod
def export_alpha() -> None:
node = onnx.helper.make_node(
"Gemm", inputs=["a", "b", "c"], outputs=["y"], alpha=0.5
)
a = np.random.ranf([3, 5]).astype(np.float32)
b = np.random.ranf([5, 4]).astype(np.float32)
c = np.zeros([1, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c, alpha=0.5)
expect(node, inputs=[a, b, c], outputs=[y], name="test_gemm_alpha")
@staticmethod
def export_beta() -> None:
node = onnx.helper.make_node(
"Gemm", inputs=["a", "b", "c"], outputs=["y"], beta=0.5
)
a = np.random.ranf([2, 7]).astype(np.float32)
b = np.random.ranf([7, 4]).astype(np.float32)
c = np.random.ranf([1, 4]).astype(np.float32)
y = gemm_reference_implementation(a, b, c, beta=0.5)
expect(node, inputs=[a, b, c], outputs=[y], name="test_gemm_beta")
@staticmethod
def export_all_attributes() -> None:
node = onnx.helper.make_node(
"Gemm",
inputs=["a", "b", "c"],
outputs=["y"],
alpha=0.25,
beta=0.35,
transA=1,
transB=1,
)
a = np.random.ranf([4, 3]).astype(np.float32)
b = np.random.ranf([5, 4]).astype(np.float32)
c = np.random.ranf([1, 5]).astype(np.float32)
y = gemm_reference_implementation(
a, b, c, transA=1, transB=1, alpha=0.25, beta=0.35
)
expect(node, inputs=[a, b, c], outputs=[y], name="test_gemm_all_attributes")
|
b1fc9ff404c356543ed09cbd6b8eb5f8840b0d9c
|
f07e66293cc41a9fe71fc44f765b432fd7a0997c
|
/selfdrive/controls/lib/lateral_planner.py
|
939c6b7c395d1d96f86a269b3b8c0e63a0938274
|
[
"MIT",
"LicenseRef-scancode-warranty-disclaimer"
] |
permissive
|
kegman/openpilot
|
c9ba96a72d905956f02c684e065091e023942883
|
b35291c91783657a5fc83abfff012d3bb49dd89f
|
refs/heads/kegman-ultimate
| 2022-05-22T17:07:16.656336
| 2021-10-25T13:35:28
| 2021-10-25T13:35:28
| 229,979,925
| 105
| 212
|
MIT
| 2022-03-13T05:47:51
| 2019-12-24T17:27:11
|
C
|
UTF-8
|
Python
| false
| false
| 12,302
|
py
|
lateral_planner.py
|
import os
import math
import numpy as np
from common.realtime import sec_since_boot, DT_MDL
from common.numpy_fast import interp
from selfdrive.swaglog import cloudlog
from selfdrive.controls.lib.lateral_mpc import libmpc_py
from selfdrive.controls.lib.drive_helpers import MPC_COST_LAT, MPC_N, CAR_ROTATION_RADIUS
from selfdrive.controls.lib.lane_planner import LanePlanner, TRAJECTORY_SIZE
from selfdrive.config import Conversions as CV
from common.params import Params
import cereal.messaging as messaging
from cereal import log
from selfdrive.kegman_conf import kegman_conf
LaneChangeState = log.LateralPlan.LaneChangeState
LaneChangeDirection = log.LateralPlan.LaneChangeDirection
LOG_MPC = os.environ.get('LOG_MPC', False)
LANE_CHANGE_SPEED_MIN = 45 * CV.MPH_TO_MS
LANE_CHANGE_TIME_MAX = 10.
DESIRES = {
LaneChangeDirection.none: {
LaneChangeState.off: log.LateralPlan.Desire.none,
LaneChangeState.preLaneChange: log.LateralPlan.Desire.none,
LaneChangeState.laneChangeStarting: log.LateralPlan.Desire.none,
LaneChangeState.laneChangeFinishing: log.LateralPlan.Desire.none,
},
LaneChangeDirection.left: {
LaneChangeState.off: log.LateralPlan.Desire.none,
LaneChangeState.preLaneChange: log.LateralPlan.Desire.none,
LaneChangeState.laneChangeStarting: log.LateralPlan.Desire.laneChangeLeft,
LaneChangeState.laneChangeFinishing: log.LateralPlan.Desire.laneChangeLeft,
},
LaneChangeDirection.right: {
LaneChangeState.off: log.LateralPlan.Desire.none,
LaneChangeState.preLaneChange: log.LateralPlan.Desire.none,
LaneChangeState.laneChangeStarting: log.LateralPlan.Desire.laneChangeRight,
LaneChangeState.laneChangeFinishing: log.LateralPlan.Desire.laneChangeRight,
},
}
class LateralPlanner():
def __init__(self, CP):
self.LP = LanePlanner()
self.last_cloudlog_t = 0
self.steer_rate_cost = CP.steerRateCost
self.setup_mpc()
self.solution_invalid_cnt = 0
self.lane_change_enabled = Params().get('LaneChangeEnabled') == b'1'
self.lane_change_state = LaneChangeState.off
self.lane_change_direction = LaneChangeDirection.none
self.lane_change_timer = 0.0
self.lane_change_ll_prob = 1.0
self.prev_one_blinker = False
self.desire = log.LateralPlan.Desire.none
self.path_xyz = np.zeros((TRAJECTORY_SIZE,3))
self.path_xyz_stds = np.ones((TRAJECTORY_SIZE,3))
self.plan_yaw = np.zeros((TRAJECTORY_SIZE,))
self.t_idxs = np.arange(TRAJECTORY_SIZE)
self.y_pts = np.zeros(TRAJECTORY_SIZE)
self.kegman = kegman_conf(CP)
self.mpc_frame = 0
self.model_laneless = "0"
def setup_mpc(self):
self.libmpc = libmpc_py.libmpc
self.libmpc.init(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, self.steer_rate_cost)
self.mpc_solution = libmpc_py.ffi.new("log_t *")
self.cur_state = libmpc_py.ffi.new("state_t *")
self.cur_state[0].x = 0.0
self.cur_state[0].y = 0.0
self.cur_state[0].psi = 0.0
self.cur_state[0].curvature = 0.0
self.angle_steers_des = 0.0
self.angle_steers_des_mpc = 0.0
self.angle_steers_des_time = 0.0
def update(self, sm, CP, VM):
v_ego = sm['carState'].vEgo
active = sm['controlsState'].active
steering_wheel_angle_offset_deg = sm['liveParameters'].angleOffsetDeg
steering_wheel_angle_deg = sm['carState'].steeringAngleDeg
# Update vehicle model
x = max(sm['liveParameters'].stiffnessFactor, 0.1)
sr = max(sm['liveParameters'].steerRatio, 0.1)
VM.update_params(x, sr)
curvature_factor = VM.curvature_factor(v_ego)
measured_curvature = -curvature_factor * math.radians(steering_wheel_angle_deg - steering_wheel_angle_offset_deg) / VM.sR
md = sm['modelV2']
self.LP.parse_model(sm['modelV2'])
if len(md.position.x) == TRAJECTORY_SIZE and len(md.orientation.x) == TRAJECTORY_SIZE:
self.path_xyz = np.column_stack([md.position.x, md.position.y, md.position.z])
self.t_idxs = np.array(md.position.t)
self.plan_yaw = list(md.orientation.z)
if len(md.orientation.xStd) == TRAJECTORY_SIZE:
self.path_xyz_stds = np.column_stack([md.position.xStd, md.position.yStd, md.position.zStd])
# Lane change logic
one_blinker = sm['carState'].leftBlinker != sm['carState'].rightBlinker
below_lane_change_speed = v_ego < LANE_CHANGE_SPEED_MIN
if sm['carState'].leftBlinker:
self.lane_change_direction = LaneChangeDirection.left
elif sm['carState'].rightBlinker:
self.lane_change_direction = LaneChangeDirection.right
if (not active) or (self.lane_change_timer > LANE_CHANGE_TIME_MAX) or (not self.lane_change_enabled):
self.lane_change_state = LaneChangeState.off
self.lane_change_direction = LaneChangeDirection.none
else:
torque_applied = sm['carState'].steeringPressed and \
((sm['carState'].steeringTorque > 0 and self.lane_change_direction == LaneChangeDirection.left) or
(sm['carState'].steeringTorque < 0 and self.lane_change_direction == LaneChangeDirection.right))
blindspot_detected = ((sm['carState'].leftBlindspot and self.lane_change_direction == LaneChangeDirection.left) or
(sm['carState'].rightBlindspot and self.lane_change_direction == LaneChangeDirection.right))
lane_change_prob = self.LP.l_lane_change_prob + self.LP.r_lane_change_prob
# State transitions
# off
if self.lane_change_state == LaneChangeState.off and one_blinker and not self.prev_one_blinker and not below_lane_change_speed:
self.lane_change_state = LaneChangeState.preLaneChange
self.lane_change_ll_prob = 1.0
# pre
elif self.lane_change_state == LaneChangeState.preLaneChange:
if not one_blinker or below_lane_change_speed:
self.lane_change_state = LaneChangeState.off
elif torque_applied and not blindspot_detected:
self.lane_change_state = LaneChangeState.laneChangeStarting
# starting
elif self.lane_change_state == LaneChangeState.laneChangeStarting:
# fade out over .5s
self.lane_change_ll_prob = max(self.lane_change_ll_prob - 2*DT_MDL, 0.0)
# 98% certainty
if lane_change_prob < 0.02 and self.lane_change_ll_prob < 0.01:
self.lane_change_state = LaneChangeState.laneChangeFinishing
# finishing
elif self.lane_change_state == LaneChangeState.laneChangeFinishing:
# fade in laneline over 1s
self.lane_change_ll_prob = min(self.lane_change_ll_prob + DT_MDL, 1.0)
if one_blinker and self.lane_change_ll_prob > 0.99:
self.lane_change_state = LaneChangeState.preLaneChange
elif self.lane_change_ll_prob > 0.99:
self.lane_change_state = LaneChangeState.off
if self.lane_change_state in [LaneChangeState.off, LaneChangeState.preLaneChange]:
self.lane_change_timer = 0.0
else:
self.lane_change_timer += DT_MDL
self.prev_one_blinker = one_blinker
self.desire = DESIRES[self.lane_change_direction][self.lane_change_state]
# Turn off lanes during lane change
if self.desire == log.LateralPlan.Desire.laneChangeRight or self.desire == log.LateralPlan.Desire.laneChangeLeft:
self.LP.lll_prob *= self.lane_change_ll_prob
self.LP.rll_prob *= self.lane_change_ll_prob
self.mpc_frame += 1
if self.mpc_frame % 1000 == 0:
# live tuning through /data/openpilot/tune.py for laneless toggle
self.kegman = kegman_conf()
self.model_laneless = float(self.kegman.conf['laneLess'])
self.mpc_frame = 0
if self.model_laneless == 0:
d_path_xyz = self.LP.get_d_path(v_ego, self.t_idxs, self.path_xyz)
self.libmpc.init_weights(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, CP.steerRateCost)
else:
d_path_xyz = self.path_xyz
path_cost = np.clip(abs(self.path_xyz[0, 1] / self.path_xyz_stds[0, 1]), 0.5, 5.0) * MPC_COST_LAT.PATH
# Heading cost is useful at low speed, otherwise end of plan can be off-heading
heading_cost = interp(v_ego, [5.0, 10.0], [MPC_COST_LAT.HEADING, 0.0])
self.libmpc.init_weights(path_cost, heading_cost, CP.steerRateCost)
y_pts = np.interp(v_ego * self.t_idxs[:MPC_N+1], np.linalg.norm(d_path_xyz, axis=1), d_path_xyz[:,1])
heading_pts = np.interp(v_ego * self.t_idxs[:MPC_N+1], np.linalg.norm(self.path_xyz, axis=1), self.plan_yaw)
self.y_pts = y_pts
assert len(y_pts) == MPC_N + 1
assert len(heading_pts) == MPC_N + 1
self.libmpc.run_mpc(self.cur_state, self.mpc_solution,
float(v_ego),
CAR_ROTATION_RADIUS,
list(y_pts),
list(heading_pts))
# init state for next
self.cur_state.x = 0.0
self.cur_state.y = 0.0
self.cur_state.psi = 0.0
self.cur_state.curvature = interp(DT_MDL, self.t_idxs[:MPC_N+1], self.mpc_solution.curvature)
# TODO this needs more thought, use .2s extra for now to estimate other delays
delay = CP.steerActuatorDelay + .2
current_curvature = self.mpc_solution.curvature[0]
psi = interp(delay, self.t_idxs[:MPC_N+1], self.mpc_solution.psi)
next_curvature_rate = self.mpc_solution.curvature_rate[0]
# MPC can plan to turn the wheel and turn back before t_delay. This means
# in high delay cases some corrections never even get commanded. So just use
# psi to calculate a simple linearization of desired curvature
curvature_diff_from_psi = psi/(max(v_ego, 1e-1) * delay) - current_curvature
next_curvature = current_curvature + 2*curvature_diff_from_psi
# reset to current steer angle if not active or overriding
if active:
curvature_desired = next_curvature
desired_curvature_rate = next_curvature_rate
else:
curvature_desired = measured_curvature
desired_curvature_rate = 0.0
# negative sign, controls uses different convention
self.desired_steering_wheel_angle_deg = -float(math.degrees(curvature_desired * VM.sR)/curvature_factor) + steering_wheel_angle_offset_deg
self.desired_steering_wheel_angle_rate_deg = -float(math.degrees(desired_curvature_rate * VM.sR)/curvature_factor)
# Check for infeasable MPC solution
mpc_nans = any(math.isnan(x) for x in self.mpc_solution.curvature)
t = sec_since_boot()
if mpc_nans:
self.libmpc.init(MPC_COST_LAT.PATH, MPC_COST_LAT.HEADING, CP.steerRateCost)
self.cur_state.curvature = measured_curvature
if t > self.last_cloudlog_t + 5.0:
self.last_cloudlog_t = t
cloudlog.warning("Lateral mpc - nan: True")
if self.mpc_solution[0].cost > 20000. or mpc_nans: # TODO: find a better way to detect when MPC did not converge
self.solution_invalid_cnt += 1
else:
self.solution_invalid_cnt = 0
def publish(self, sm, pm):
plan_solution_valid = self.solution_invalid_cnt < 2
plan_send = messaging.new_message('lateralPlan')
plan_send.valid = sm.all_alive_and_valid(service_list=['carState', 'controlsState', 'liveParameters', 'modelV2'])
plan_send.lateralPlan.laneWidth = float(self.LP.lane_width)
plan_send.lateralPlan.dPathPoints = [float(x) for x in self.y_pts]
plan_send.lateralPlan.lProb = float(self.LP.lll_prob)
plan_send.lateralPlan.rProb = float(self.LP.rll_prob)
plan_send.lateralPlan.dProb = float(self.LP.d_prob)
plan_send.lateralPlan.steeringAngleDeg = float(self.desired_steering_wheel_angle_deg)
plan_send.lateralPlan.steeringRateDeg = float(self.desired_steering_wheel_angle_rate_deg)
plan_send.lateralPlan.angleOffsetDeg = float(sm['liveParameters'].angleOffsetAverageDeg)
plan_send.lateralPlan.mpcSolutionValid = bool(plan_solution_valid)
plan_send.lateralPlan.desire = self.desire
plan_send.lateralPlan.laneChangeState = self.lane_change_state
plan_send.lateralPlan.laneChangeDirection = self.lane_change_direction
pm.send('lateralPlan', plan_send)
if LOG_MPC:
dat = messaging.new_message('liveMpc')
dat.liveMpc.x = list(self.mpc_solution[0].x)
dat.liveMpc.y = list(self.mpc_solution[0].y)
dat.liveMpc.psi = list(self.mpc_solution[0].psi)
dat.liveMpc.tire_angle = list(self.mpc_solution[0].tire_angle)
dat.liveMpc.cost = self.mpc_solution[0].cost
pm.send('liveMpc', dat)
|
3a124d4de174e09470187512cce4651584ea8c80
|
f8dee139258b7d971bd1cfa16bd16e356537bbac
|
/Contents/Libraries/Shared/subzero/intent.py
|
174e68fee6b752c13b295a9b570105472503d270
|
[
"MIT"
] |
permissive
|
pannal/Sub-Zero.bundle
|
79673016ae68d1f2e9886fd30b8763b73a8f6cf8
|
4ced7d8c8f9f5fb47d12410f87fa33d782e9f0f4
|
refs/heads/master
| 2023-07-27T23:04:32.925845
| 2023-07-09T13:07:38
| 2023-07-09T13:08:04
| 21,959,699
| 1,820
| 178
|
NOASSERTION
| 2022-11-28T03:23:13
| 2014-07-17T22:19:13
|
Python
|
UTF-8
|
Python
| false
| false
| 2,994
|
py
|
intent.py
|
# coding=utf-8
import datetime
import threading
lock = threading.Lock()
class TempIntent(object):
timeout = 1000 # milliseconds
store = None
def __init__(self, timeout=1000, store=None):
self.timeout = timeout
if store is None:
raise NotImplementedError
self.store = store
def get(self, kind, *keys):
with lock:
# iter all requested keys
for key in keys:
hit = False
# skip key if invalid
if not key:
continue
# valid kind?
if kind in self.store:
now = datetime.datetime.now()
key = str(key)
# iter all known kinds (previously created)
for known_key in self.store[kind].keys():
# may need locking, for now just play it safe
data = self.store[kind].get(known_key, {})
ends = data.get("timeout")
if not ends:
continue
timed_out = False
if now > ends:
timed_out = True
# key and kind in storage, and not timed out = hit
if known_key == key and not timed_out:
hit = True
if timed_out:
try:
del self.store[kind][key]
except:
continue
if hit:
return True
return False
def resolve(self, kind, key):
with lock:
if kind in self.store and key in self.store[kind]:
del self.store[kind][key]
return True
return False
def set(self, kind, key, data=None, timeout=None):
with lock:
if kind not in self.store:
self.store[kind] = {}
key = str(key)
self.store[kind][key] = {
"data": data,
"timeout": datetime.datetime.now() + datetime.timedelta(milliseconds=timeout or self.timeout)
}
def has(self, kind, key):
with lock:
if kind not in self.store:
return False
return key in self.store[kind]
def cleanup(self):
now = datetime.datetime.now()
clear_all = False
for kind, info in self.store.items():
for key, intent_data in info.items():
# legacy intent data, clear everything
if not isinstance(intent_data, dict):
clear_all = True
continue
if now > intent_data["timeout"]:
del self.store[kind][key]
if clear_all:
self.store.clear()
self.store.save()
|
28d3bf86cba638580deffe0d98a8336c135425c0
|
5a52ccea88f90dd4f1acc2819997fce0dd5ffb7d
|
/alipay/aop/api/domain/IntentQueryRequest.py
|
4f45baa538068c9da9d8db5c0c9c1cf600dda814
|
[
"Apache-2.0"
] |
permissive
|
alipay/alipay-sdk-python-all
|
8bd20882852ffeb70a6e929038bf88ff1d1eff1c
|
1fad300587c9e7e099747305ba9077d4cd7afde9
|
refs/heads/master
| 2023-08-27T21:35:01.778771
| 2023-08-23T07:12:26
| 2023-08-23T07:12:26
| 133,338,689
| 247
| 70
|
Apache-2.0
| 2023-04-25T04:54:02
| 2018-05-14T09:40:54
|
Python
|
UTF-8
|
Python
| false
| false
| 6,731
|
py
|
IntentQueryRequest.py
|
#!/usr/bin/env python
# -*- coding: utf-8 -*-
import json
from alipay.aop.api.constant.ParamConstants import *
class IntentQueryRequest(object):
def __init__(self):
self._action_src = None
self._client_os = None
self._client_version = None
self._current_city = None
self._location = None
self._nlu_json_param = None
self._open_id = None
self._query = None
self._query_id = None
self._scene_code = None
self._search_src = None
self._session_id = None
self._uid = None
@property
def action_src(self):
return self._action_src
@action_src.setter
def action_src(self, value):
self._action_src = value
@property
def client_os(self):
return self._client_os
@client_os.setter
def client_os(self, value):
self._client_os = value
@property
def client_version(self):
return self._client_version
@client_version.setter
def client_version(self, value):
self._client_version = value
@property
def current_city(self):
return self._current_city
@current_city.setter
def current_city(self, value):
self._current_city = value
@property
def location(self):
return self._location
@location.setter
def location(self, value):
self._location = value
@property
def nlu_json_param(self):
return self._nlu_json_param
@nlu_json_param.setter
def nlu_json_param(self, value):
self._nlu_json_param = value
@property
def open_id(self):
return self._open_id
@open_id.setter
def open_id(self, value):
self._open_id = value
@property
def query(self):
return self._query
@query.setter
def query(self, value):
self._query = value
@property
def query_id(self):
return self._query_id
@query_id.setter
def query_id(self, value):
self._query_id = value
@property
def scene_code(self):
return self._scene_code
@scene_code.setter
def scene_code(self, value):
self._scene_code = value
@property
def search_src(self):
return self._search_src
@search_src.setter
def search_src(self, value):
self._search_src = value
@property
def session_id(self):
return self._session_id
@session_id.setter
def session_id(self, value):
self._session_id = value
@property
def uid(self):
return self._uid
@uid.setter
def uid(self, value):
self._uid = value
def to_alipay_dict(self):
params = dict()
if self.action_src:
if hasattr(self.action_src, 'to_alipay_dict'):
params['action_src'] = self.action_src.to_alipay_dict()
else:
params['action_src'] = self.action_src
if self.client_os:
if hasattr(self.client_os, 'to_alipay_dict'):
params['client_os'] = self.client_os.to_alipay_dict()
else:
params['client_os'] = self.client_os
if self.client_version:
if hasattr(self.client_version, 'to_alipay_dict'):
params['client_version'] = self.client_version.to_alipay_dict()
else:
params['client_version'] = self.client_version
if self.current_city:
if hasattr(self.current_city, 'to_alipay_dict'):
params['current_city'] = self.current_city.to_alipay_dict()
else:
params['current_city'] = self.current_city
if self.location:
if hasattr(self.location, 'to_alipay_dict'):
params['location'] = self.location.to_alipay_dict()
else:
params['location'] = self.location
if self.nlu_json_param:
if hasattr(self.nlu_json_param, 'to_alipay_dict'):
params['nlu_json_param'] = self.nlu_json_param.to_alipay_dict()
else:
params['nlu_json_param'] = self.nlu_json_param
if self.open_id:
if hasattr(self.open_id, 'to_alipay_dict'):
params['open_id'] = self.open_id.to_alipay_dict()
else:
params['open_id'] = self.open_id
if self.query:
if hasattr(self.query, 'to_alipay_dict'):
params['query'] = self.query.to_alipay_dict()
else:
params['query'] = self.query
if self.query_id:
if hasattr(self.query_id, 'to_alipay_dict'):
params['query_id'] = self.query_id.to_alipay_dict()
else:
params['query_id'] = self.query_id
if self.scene_code:
if hasattr(self.scene_code, 'to_alipay_dict'):
params['scene_code'] = self.scene_code.to_alipay_dict()
else:
params['scene_code'] = self.scene_code
if self.search_src:
if hasattr(self.search_src, 'to_alipay_dict'):
params['search_src'] = self.search_src.to_alipay_dict()
else:
params['search_src'] = self.search_src
if self.session_id:
if hasattr(self.session_id, 'to_alipay_dict'):
params['session_id'] = self.session_id.to_alipay_dict()
else:
params['session_id'] = self.session_id
if self.uid:
if hasattr(self.uid, 'to_alipay_dict'):
params['uid'] = self.uid.to_alipay_dict()
else:
params['uid'] = self.uid
return params
@staticmethod
def from_alipay_dict(d):
if not d:
return None
o = IntentQueryRequest()
if 'action_src' in d:
o.action_src = d['action_src']
if 'client_os' in d:
o.client_os = d['client_os']
if 'client_version' in d:
o.client_version = d['client_version']
if 'current_city' in d:
o.current_city = d['current_city']
if 'location' in d:
o.location = d['location']
if 'nlu_json_param' in d:
o.nlu_json_param = d['nlu_json_param']
if 'open_id' in d:
o.open_id = d['open_id']
if 'query' in d:
o.query = d['query']
if 'query_id' in d:
o.query_id = d['query_id']
if 'scene_code' in d:
o.scene_code = d['scene_code']
if 'search_src' in d:
o.search_src = d['search_src']
if 'session_id' in d:
o.session_id = d['session_id']
if 'uid' in d:
o.uid = d['uid']
return o
|
91e33313d50c64242d210dd643faad2cf65a6b43
|
dd9a51b3117907294c4ff501f8d9cfb68872ccbe
|
/napalm/iosxr/iosxr.py
|
475ad34840ae27ba39916919541daec7fc188a47
|
[
"Apache-2.0"
] |
permissive
|
napalm-automation/napalm
|
5f7c8e56d65021c515fcf2f5540c2919ec2a086e
|
cba44b7a534bc896572dbf6a9a3a7911cf34ed13
|
refs/heads/develop
| 2023-08-25T18:06:54.513063
| 2023-08-23T17:46:43
| 2023-08-23T17:46:43
| 32,737,992
| 2,043
| 675
|
Apache-2.0
| 2023-09-06T18:35:57
| 2015-03-23T14:43:45
|
Python
|
UTF-8
|
Python
| false
| false
| 95,444
|
py
|
iosxr.py
|
# -*- coding: utf-8 -*-
# Copyright 2015 Spotify AB. All rights reserved.
#
# The contents of this file are licensed under the Apache License, Version 2.0
# (the "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
# import stdlib
import re
import copy
import ipaddress
from collections import defaultdict
import logging
# import third party lib
from lxml import etree as ETREE
from napalm.pyIOSXR import IOSXR
from napalm.pyIOSXR.exceptions import ConnectError
from napalm.pyIOSXR.exceptions import TimeoutError
from napalm.pyIOSXR.exceptions import InvalidInputError
from napalm.pyIOSXR.exceptions import XMLCLIError
# import NAPALM base
import napalm.base.helpers
from napalm.base.netmiko_helpers import netmiko_args
from napalm.iosxr import constants as C
from napalm.base.base import NetworkDriver
from napalm.base.exceptions import ConnectionException
from napalm.base.exceptions import MergeConfigException
from napalm.base.exceptions import ReplaceConfigException
from napalm.base.exceptions import CommandTimeoutException
logger = logging.getLogger(__name__)
IP_RIBRoute = "IP_RIBRoute"
class IOSXRDriver(NetworkDriver):
"""IOS-XR driver class: inherits NetworkDriver from napalm.base."""
def __init__(self, hostname, username, password, timeout=60, optional_args=None):
self.hostname = hostname
self.username = username
self.password = password
self.timeout = timeout
self.pending_changes = False
self.replace = False
if optional_args is None:
optional_args = {}
self.lock_on_connect = optional_args.get("config_lock", False)
self.netmiko_optional_args = netmiko_args(optional_args)
try:
self.port = self.netmiko_optional_args.pop("port")
except KeyError:
self.port = 22
self.platform = "iosxr"
self.device = IOSXR(
hostname,
username,
password,
timeout=timeout,
port=self.port,
lock=self.lock_on_connect,
**self.netmiko_optional_args,
)
def open(self):
try:
self.device.open()
except ConnectError as conn_err:
logger.error(conn_err.args[0])
raise ConnectionException(conn_err.args[0])
def close(self):
logger.debug("Closed connection with device %s" % (self.hostname))
self.device.close()
def is_alive(self):
"""Returns a flag with the state of the connection."""
if self.device is None:
return {"is_alive": False}
# Simply returns the flag from pyIOSXR
return {"is_alive": self.device.is_alive()}
def load_replace_candidate(self, filename=None, config=None):
self.pending_changes = True
self.replace = True
if not self.lock_on_connect:
self.device.lock()
try:
self.device.load_candidate_config(filename=filename, config=config)
except InvalidInputError as e:
self.pending_changes = False
self.replace = False
logger.error(e.args[0])
raise ReplaceConfigException(e.args[0])
def load_merge_candidate(self, filename=None, config=None):
self.pending_changes = True
self.replace = False
if not self.lock_on_connect:
self.device.lock()
try:
self.device.load_candidate_config(filename=filename, config=config)
except InvalidInputError as e:
self.pending_changes = False
self.replace = False
logger.error(e.args[0])
raise MergeConfigException(e.args[0])
def compare_config(self):
if not self.pending_changes:
return ""
elif self.replace:
return self.device.compare_replace_config().strip()
else:
return self.device.compare_config().strip()
def commit_config(self, message="", revert_in=None):
if revert_in is not None:
raise NotImplementedError(
"Commit confirm has not been implemented on this platform."
)
commit_args = {"comment": message} if message else {}
if self.replace:
self.device.commit_replace_config(**commit_args)
else:
self.device.commit_config(**commit_args)
self.pending_changes = False
if not self.lock_on_connect:
self.device.unlock()
def discard_config(self):
self.device.discard_config()
self.pending_changes = False
if not self.lock_on_connect:
self.device.unlock()
def rollback(self):
self.device.rollback()
def get_facts(self):
facts = {
"vendor": "Cisco",
"os_version": "",
"hostname": "",
"uptime": -1.0,
"serial_number": "",
"fqdn": "",
"model": "",
"interface_list": [],
}
facts_rpc_request = """
<Get>
<Operational>
<SystemTime/>
<PlatformInventory>
<RackTable>
<Rack>
<Naming>
<Name>0</Name>
</Naming>
<Attributes>
<BasicInfo/>
</Attributes>
</Rack>
</RackTable>
</PlatformInventory>
</Operational>
</Get>
"""
# IOS-XR 7.3.3 and possibly other 7.X versions have this located in
# different location in the XML tree
facts_rpc_request_alt = """
<Get>
<Operational>
<SystemTime/>
<Inventory>
<Entities>
<Entity>
<Naming>
<Name>Rack 0</Name>
</Naming>
<Attributes>
<InvBasicBag></InvBasicBag>
</Attributes>
</Entity>
</Entities>
</Inventory>
</Operational>
</Get>
"""
system_time_xpath = ".//SystemTime/Uptime"
try:
facts_rpc_reply = ETREE.fromstring(
self.device.make_rpc_call(facts_rpc_request)
)
platform_attr_xpath = ".//RackTable/Rack/Attributes/BasicInfo"
except XMLCLIError:
facts_rpc_reply = ETREE.fromstring(
self.device.make_rpc_call(facts_rpc_request_alt)
)
platform_attr_xpath = ".//Entities/Entity/Attributes/InvBasicBag"
system_time_tree = facts_rpc_reply.xpath(system_time_xpath)[0]
try:
platform_attr_tree = facts_rpc_reply.xpath(platform_attr_xpath)[0]
except IndexError:
platform_attr_tree = facts_rpc_reply.xpath(platform_attr_xpath)
hostname = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(system_time_tree, "Hostname")
)
uptime = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(system_time_tree, "Uptime"), -1.0
)
serial = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(platform_attr_tree, "SerialNumber")
)
os_version = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(platform_attr_tree, "SoftwareRevision")
)
model = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(platform_attr_tree, "ModelName")
)
interface_list = sorted(list(self.get_interfaces().keys()))
facts.update(
{
"os_version": os_version,
"hostname": hostname,
"model": model,
"uptime": uptime,
"serial_number": serial,
"fqdn": hostname,
"interface_list": interface_list,
}
)
return facts
def get_interfaces(self):
interfaces = {}
INTERFACE_DEFAULTS = {
"is_enabled": False,
"is_up": False,
"mac_address": "",
"description": "",
"speed": -1.0,
"last_flapped": -1.0,
}
interfaces_rpc_request = "<Get><Operational><Interfaces/></Operational></Get>"
interfaces_rpc_reply = ETREE.fromstring(
self.device.make_rpc_call(interfaces_rpc_request)
)
for interface_tree in interfaces_rpc_reply.xpath(
".//Interfaces/InterfaceTable/Interface"
):
interface_name = napalm.base.helpers.find_txt(
interface_tree, "Naming/InterfaceName"
)
if not interface_name:
continue
is_up = (
napalm.base.helpers.find_txt(interface_tree, "LineState")
== "IM_STATE_UP"
)
enabled = (
napalm.base.helpers.find_txt(interface_tree, "State")
!= "IM_STATE_ADMINDOWN"
)
raw_mac = napalm.base.helpers.find_txt(interface_tree, "MACAddress/Address")
mac_address = napalm.base.helpers.convert(
napalm.base.helpers.mac, raw_mac, raw_mac
)
speed = napalm.base.helpers.convert(
float,
napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(interface_tree, "Bandwidth"), 0
)
* 1e-3,
)
mtu = int(napalm.base.helpers.find_txt(interface_tree, "MTU"))
description = napalm.base.helpers.find_txt(interface_tree, "Description")
interfaces[interface_name] = copy.deepcopy(INTERFACE_DEFAULTS)
interfaces[interface_name].update(
{
"is_up": is_up,
"speed": speed,
"mtu": mtu,
"is_enabled": enabled,
"mac_address": mac_address,
"description": description,
}
)
return interfaces
def get_interfaces_counters(self):
rpc_command = "<Get><Operational><Interfaces><InterfaceTable></InterfaceTable>\
</Interfaces></Operational></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
interface_counters = {}
for interface in result_tree.xpath(".//Interface"):
interface_name = napalm.base.helpers.find_txt(interface, "InterfaceHandle")
interface_stats = {}
if not interface.xpath("InterfaceStatistics"):
continue
else:
interface_stats = {}
interface_stats["tx_multicast_packets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface,
"InterfaceStatistics/FullInterfaceStats/MulticastPacketsSent",
),
)
interface_stats["tx_discards"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "InterfaceStatistics/FullInterfaceStats/OutputDrops"
),
)
interface_stats["tx_octets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "InterfaceStatistics/FullInterfaceStats/BytesSent"
),
)
interface_stats["tx_errors"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "InterfaceStatistics/FullInterfaceStats/OutputErrors"
),
)
interface_stats["rx_octets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface,
"InterfaceStatistics/FullInterfaceStats/BytesReceived",
),
)
interface_stats["tx_unicast_packets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "InterfaceStatistics/FullInterfaceStats/PacketsSent"
),
)
interface_stats["rx_errors"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "InterfaceStatistics/FullInterfaceStats/InputErrors"
),
)
interface_stats["tx_broadcast_packets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface,
"InterfaceStatistics/FullInterfaceStats/BroadcastPacketsSent",
),
)
interface_stats["rx_multicast_packets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface,
"InterfaceStatistics/FullInterfaceStats/MulticastPacketsReceived",
),
)
interface_stats["rx_broadcast_packets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface,
"InterfaceStatistics/FullInterfaceStats/BroadcastPacketsReceived",
),
)
interface_stats["rx_discards"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "InterfaceStatistics/FullInterfaceStats/InputDrops"
),
)
interface_stats["rx_unicast_packets"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface,
"InterfaceStatistics/FullInterfaceStats/PacketsReceived",
),
)
interface_counters[interface_name] = interface_stats
return interface_counters
def get_bgp_neighbors(self):
def generate_vrf_query(vrf_name):
"""
Helper to provide XML-query for the VRF-type we're interested in.
"""
if vrf_name == "global":
rpc_command = "<Get><Operational><BGP><InstanceTable><Instance><Naming>\
<InstanceName>default</InstanceName></Naming><InstanceActive><DefaultVRF>\
<GlobalProcessInfo></GlobalProcessInfo><NeighborTable></NeighborTable></DefaultVRF>\
</InstanceActive></Instance></InstanceTable></BGP></Operational></Get>"
else:
rpc_command = "<Get><Operational><BGP><InstanceTable><Instance><Naming>\
<InstanceName>default</InstanceName></Naming><InstanceActive><VRFTable><VRF>\
<Naming>{vrf_name}</Naming><GlobalProcessInfo></GlobalProcessInfo><NeighborTable>\
</NeighborTable></VRF></VRFTable></InstanceActive></Instance></InstanceTable>\
</BGP></Operational></Get>".format(
vrf_name=vrf_name
)
return rpc_command
"""
Initial run to figure out what VRF's are available
Decided to get this one from Configured-section
because bulk-getting all instance-data to do the same could get ridiculously heavy
Assuming we're always interested in the DefaultVRF
"""
active_vrfs = ["global"]
rpc_command = "<Get><Operational><BGP><ConfigInstanceTable><ConfigInstance><Naming>\
<InstanceName>default</InstanceName></Naming><ConfigInstanceVRFTable>\
</ConfigInstanceVRFTable></ConfigInstance></ConfigInstanceTable></BGP></Operational></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for node in result_tree.xpath(".//ConfigVRF"):
active_vrfs.append(napalm.base.helpers.find_txt(node, "Naming/VRFName"))
result = {}
for vrf in active_vrfs:
rpc_command = generate_vrf_query(vrf)
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
this_vrf = {}
this_vrf["peers"] = {}
if vrf == "global":
this_vrf["router_id"] = napalm.base.helpers.convert(
str,
napalm.base.helpers.find_txt(
result_tree,
"Get/Operational/BGP/InstanceTable/Instance/InstanceActive/DefaultVRF"
"/GlobalProcessInfo/VRF/RouterID",
),
)
else:
this_vrf["router_id"] = napalm.base.helpers.convert(
str,
napalm.base.helpers.find_txt(
result_tree,
"Get/Operational/BGP/InstanceTable/Instance/InstanceActive/VRFTable/VRF"
"/GlobalProcessInfo/VRF/RouterID",
),
)
neighbors = {}
for neighbor in result_tree.xpath(".//Neighbor"):
this_neighbor = {}
this_neighbor["local_as"] = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "LocalAS")
)
this_neighbor["remote_as"] = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "RemoteAS")
)
this_neighbor["remote_id"] = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "RouterID")
)
if (
napalm.base.helpers.find_txt(neighbor, "ConnectionAdminStatus")
== "1"
):
this_neighbor["is_enabled"] = True
try:
this_neighbor["description"] = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "Description")
)
except AttributeError:
logger.debug(
"No attribute 'description' for neighbor %s"
% (this_neighbor["remote_as"])
)
this_neighbor["description"] = ""
this_neighbor["is_enabled"] = (
napalm.base.helpers.find_txt(neighbor, "ConnectionAdminStatus")
== "1"
)
if (
str(napalm.base.helpers.find_txt(neighbor, "ConnectionAdminStatus"))
== "1"
):
this_neighbor["is_enabled"] = True
else:
this_neighbor["is_enabled"] = False
if (
str(napalm.base.helpers.find_txt(neighbor, "ConnectionState"))
== "BGP_ST_ESTAB"
):
this_neighbor["is_up"] = True
this_neighbor["uptime"] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "ConnectionEstablishedTime"
),
)
else:
this_neighbor["is_up"] = False
this_neighbor["uptime"] = -1
this_neighbor["address_family"] = {}
if (
napalm.base.helpers.find_txt(
neighbor, "ConnectionRemoteAddress/AFI"
)
== "IPv4"
):
this_afi = "ipv4"
elif (
napalm.base.helpers.find_txt(
neighbor, "ConnectionRemoteAddress/AFI"
)
== "IPv6"
):
this_afi = "ipv6"
else:
this_afi = napalm.base.helpers.find_txt(
neighbor, "ConnectionRemoteAddress/AFI"
)
this_neighbor["address_family"][this_afi] = {}
try:
this_neighbor["address_family"][this_afi][
"received_prefixes"
] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesAccepted"
),
0,
) + napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesDenied"
),
0,
)
this_neighbor["address_family"][this_afi][
"accepted_prefixes"
] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesAccepted"
),
0,
)
this_neighbor["address_family"][this_afi][
"sent_prefixes"
] = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesAdvertised"
),
0,
)
except AttributeError:
this_neighbor["address_family"][this_afi]["received_prefixes"] = -1
this_neighbor["address_family"][this_afi]["accepted_prefixes"] = -1
this_neighbor["address_family"][this_afi]["sent_prefixes"] = -1
neighbor_ip = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
neighbor, "Naming/NeighborAddress/IPV4Address"
)
or napalm.base.helpers.find_txt(
neighbor, "Naming/NeighborAddress/IPV6Address"
)
)
neighbors[neighbor_ip] = this_neighbor
this_vrf["peers"] = neighbors
result[vrf] = this_vrf
return result
def get_environment(self):
def get_module_xml_query(module, selection):
return "<Get><AdminOperational><EnvironmentalMonitoring><RackTable><Rack><Naming>\
<rack>0</rack></Naming><SlotTable><Slot><Naming><slot>{slot}</slot></Naming>{name}\
</Slot></SlotTable></Rack></RackTable></EnvironmentalMonitoring></AdminOperational>\
</Get>".format(
slot=module, name=selection
)
environment_status = {}
environment_status["fans"] = {}
environment_status["temperature"] = {}
environment_status["power"] = {}
environment_status["cpu"] = {}
environment_status["memory"] = 0.0
# finding slots with equipment we're interested in
rpc_command = "<Get><AdminOperational><PlatformInventory><RackTable><Rack><Naming>\
<Name>0</Name></Naming><SlotTable></SlotTable></Rack></RackTable></PlatformInventory>\
</AdminOperational></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
active_modules = defaultdict(list)
for slot in result_tree.xpath(".//Slot"):
for card in slot.xpath(".//CardTable"):
# find enabled slots, figoure out type and save for later
if (
napalm.base.helpers.find_txt(
card, "Card/Attributes/FRUInfo/ModuleAdministrativeState"
)
== "ADMIN_UP"
):
slot_name = napalm.base.helpers.find_txt(slot, "Naming/Name")
module_type = re.sub(r"\d+", "", slot_name)
if len(module_type) > 0:
active_modules[module_type].append(slot_name)
else:
active_modules["LC"].append(slot_name)
#
# PSU's
#
for psu in active_modules["PM"]:
if psu in ["PM6", "PM7"]: # Cisco bug, chassis difference V01<->V02
continue
rpc_command = get_module_xml_query(psu, "")
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
psu_status = {}
psu_status["status"] = False
psu_status["capacity"] = 0.0
psu_status["output"] = 0.0
for sensor in result_tree.xpath(".//SensorName"):
if napalm.base.helpers.find_txt(sensor, "Naming/Name") == "host__VOLT":
this_psu_voltage = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(sensor, "ValueBrief")
)
elif (
napalm.base.helpers.find_txt(sensor, "Naming/Name") == "host__CURR"
):
this_psu_current = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(sensor, "ValueBrief")
)
elif napalm.base.helpers.find_txt(sensor, "Naming/Name") == "host__PM":
this_psu_capacity = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(sensor, "ValueBrief")
)
if this_psu_capacity > 0:
psu_status["capacity"] = this_psu_capacity
psu_status["status"] = True
if this_psu_current and this_psu_voltage:
psu_status["output"] = (
this_psu_voltage * this_psu_current
) / 1_000_000.0
environment_status["power"][psu] = psu_status
#
# Memory
#
facts = self.get_facts()
router_model = facts.get("model")
xr_version = facts.get("os_version")
major_version = (
int(xr_version.split(".")[0])
if xr_version
and isinstance(xr_version, str)
and xr_version.split(".")[0].isnumeric()
else 0
)
is_xrv = router_model.lower().startswith("xrv")
environment_status["memory"] = {"available_ram": 0.0, "used_ram": 0.0}
if not is_xrv:
if major_version >= 7:
rpc_command = "<Get><Operational><MemorySummary>\
</MemorySummary></Operational></Get>"
else:
rpc_command = "<Get><AdminOperational><MemorySummary>\
</MemorySummary></AdminOperational></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for node in result_tree.xpath(".//Node"):
if (
napalm.base.helpers.find_txt(node, "Naming/NodeName/Slot")
== active_modules["RSP"][0]
):
available_ram = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(node, "Summary/SystemRAMMemory"),
)
free_ram = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
node, "Summary/FreeApplicationMemory"
),
)
break # we're only looking at one of the RSP's
if available_ram and free_ram:
used_ram = available_ram - free_ram
memory = {}
memory["available_ram"] = available_ram
memory["used_ram"] = used_ram
environment_status["memory"] = memory
#
# Fans
#
for fan in active_modules["FT"]:
rpc_command = get_module_xml_query(fan, "")
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for module in result_tree.xpath(".//Module"):
for sensortype in module.xpath(".//SensorType"):
for sensorname in sensortype.xpath(".//SensorNameTable"):
if (
napalm.base.helpers.find_txt(
sensorname, "SensorName/Naming/Name"
)
== "host__FanSpeed_0"
):
environment_status["fans"][fan] = {
"status": napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
sensorname,
"SensorName/ValueDetailed/Status",
),
)
== 1
}
#
# CPU
#
cpu = {}
rpc_command = "<Get><Operational><SystemMonitoring></SystemMonitoring></Operational></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for module in result_tree.xpath(".//CPUUtilization"):
this_cpu = {}
this_cpu["%usage"] = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(module, "TotalCPUFiveMinute")
)
rack = napalm.base.helpers.find_txt(module, "Naming/NodeName/Rack")
slot = napalm.base.helpers.find_txt(module, "Naming/NodeName/Slot")
instance = napalm.base.helpers.find_txt(module, "Naming/NodeName/Instance")
position = "%s/%s/%s" % (rack, slot, instance)
cpu[position] = this_cpu
environment_status["cpu"] = cpu
#
# Temperature
#
slot_list = set()
for category, slot in active_modules.items():
slot_list |= set(slot)
if not is_xrv:
for slot in slot_list:
rpc_command = get_module_xml_query(slot, "")
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for sensor in result_tree.xpath(".//SensorName"):
if (
not napalm.base.helpers.find_txt(sensor, "Naming/Name")
== "host__Inlet0"
):
continue
this_reading = {}
this_reading["temperature"] = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(sensor, "ValueBrief")
)
threshold_value = [
napalm.base.helpers.convert(float, x.text)
for x in sensor.xpath("ThresholdTable/Threshold/ValueBrief")
]
this_reading["is_alert"] = (
threshold_value[2]
<= this_reading["temperature"]
<= threshold_value[3]
)
this_reading["is_critical"] = (
threshold_value[4]
<= this_reading["temperature"]
<= threshold_value[5]
)
this_reading["temperature"] = this_reading["temperature"] / 10
environment_status["temperature"][slot] = this_reading
return environment_status
def get_lldp_neighbors(self):
# init result dict
lldp = {}
sh_lldp = self.device.show_lldp_neighbors().splitlines()[5:-3]
for n in sh_lldp:
local_interface = n.split()[1]
if local_interface not in lldp.keys():
lldp[local_interface] = []
lldp[local_interface].append(
{
"hostname": napalm.base.helpers.convert(str, n.split()[0]),
"port": napalm.base.helpers.convert(str, n.split()[4]),
}
)
return lldp
def get_lldp_neighbors_detail(self, interface=""):
lldp_neighbors = {}
rpc_command = (
"<Get><Operational>"
"<LLDP><NodeTable></NodeTable></LLDP>"
"</Operational></Get>"
)
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for neighbor in result_tree.xpath(".//Neighbors/DetailTable/Detail/Entry"):
interface_name = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "ReceivingInterfaceName")
)
parent_interface = napalm.base.helpers.convert(
str,
napalm.base.helpers.find_txt(neighbor, "ReceivingParentInterfaceName"),
)
chassis_id_raw = napalm.base.helpers.find_txt(neighbor, "ChassisID")
chassis_id = napalm.base.helpers.convert(
napalm.base.helpers.mac, chassis_id_raw, chassis_id_raw
)
port_id = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "PortIDDetail")
)
port_descr = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "Detail/PortDescription")
)
system_name = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "Detail/SystemName")
)
system_descr = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "Detail/SystemDescription")
)
system_capabilities = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(neighbor, "Detail/SystemCapabilities")
)
enabled_capabilities = napalm.base.helpers.convert(
str,
napalm.base.helpers.find_txt(neighbor, "Detail/EnabledCapabilities"),
)
if interface_name not in lldp_neighbors.keys():
lldp_neighbors[interface_name] = []
lldp_neighbors[interface_name].append(
{
"parent_interface": parent_interface,
"remote_chassis_id": chassis_id,
"remote_port": port_id,
"remote_port_description": port_descr,
"remote_system_name": system_name,
"remote_system_description": system_descr,
"remote_system_capab": napalm.base.helpers.transform_lldp_capab(
system_capabilities
),
"remote_system_enable_capab": napalm.base.helpers.transform_lldp_capab(
enabled_capabilities
),
}
)
return lldp_neighbors
def cli(self, commands, encoding="text"):
if encoding not in ("text",):
raise NotImplementedError("%s is not a supported encoding" % encoding)
cli_output = {}
if type(commands) is not list:
raise TypeError("Please enter a valid list of commands!")
for command in commands:
try:
cli_output[str(command)] = str(self.device._execute_show(command))
except TimeoutError:
cli_output[
str(command)
] = 'Execution of command \
"{command}" took too long! Please adjust your params!'.format(
command=command
)
logger.error(str(cli_output))
raise CommandTimeoutException(str(cli_output))
return cli_output
def get_bgp_config(self, group="", neighbor=""):
bgp_config = {}
# a helper
def build_prefix_limit(af_table, limit, prefix_percent, prefix_timeout):
prefix_limit = {}
inet = False
inet6 = False
preifx_type = "inet"
if "ipv4" in af_table.lower():
inet = True
if "ipv6" in af_table.lower():
inet6 = True
preifx_type = "inet6"
if inet or inet6:
prefix_limit = {
preifx_type: {
af_table[4:].lower(): {
"limit": limit,
"teardown": {
"threshold": prefix_percent,
"timeout": prefix_timeout,
},
}
}
}
return prefix_limit
# here begins actual method...
rpc_command = "<Get><Configuration><BGP><Instance><Naming>\
<InstanceName>default</InstanceName></Naming></Instance></BGP></Configuration></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
# Check if BGP is not configured.
get_tag = result_tree.find("./Get")
if get_tag is not None:
bgp_not_found = get_tag.attrib.get("ItemNotFound")
if bgp_not_found:
return {}
bgp_asn = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
result_tree,
"Get/Configuration/BGP/Instance[1]/InstanceAS/FourByteAS/Naming/AS",
),
0,
)
if not group:
neighbor = ""
bgp_group_neighbors = {}
for bgp_neighbor in result_tree.xpath(".//Neighbor"):
group_name = napalm.base.helpers.find_txt(
bgp_neighbor, "NeighborGroupAddMember"
)
peer = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
bgp_neighbor, "Naming/NeighborAddress/IPV4Address"
)
or napalm.base.helpers.find_txt(
bgp_neighbor, "Naming/NeighborAddress/IPV6Address"
)
)
if neighbor and peer != neighbor:
continue
description = napalm.base.helpers.find_txt(bgp_neighbor, "Description")
peer_as = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(bgp_neighbor, "RemoteAS/AS_YY"), 0
)
local_as = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(bgp_neighbor, "LocalAS/AS_YY"),
bgp_asn,
)
af_table = napalm.base.helpers.find_txt(
bgp_neighbor, "NeighborAFTable/NeighborAF/Naming/AFName"
)
prefix_limit = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_neighbor,
"NeighborAFTable/NeighborAF/MaximumPrefixes/PrefixLimit",
),
0,
)
prefix_percent = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_neighbor,
"NeighborAFTable/NeighborAF/MaximumPrefixes/WarningPercentage",
),
0,
)
prefix_timeout = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_neighbor,
"NeighborAFTable/NeighborAF/MaximumPrefixes/RestartTime",
),
0,
)
import_policy = napalm.base.helpers.find_txt(
bgp_neighbor, "NeighborAFTable/NeighborAF/RoutePolicyIn"
)
export_policy = napalm.base.helpers.find_txt(
bgp_neighbor, "NeighborAFTable/NeighborAF/RoutePolicyOut"
)
local_addr_raw = napalm.base.helpers.find_txt(
bgp_neighbor, "LocalAddress/LocalIPAddress/IPV4Address"
) or napalm.base.helpers.find_txt(
bgp_neighbor, "LocalAddress/LocalIPAddress/IPV6Address"
)
local_address = napalm.base.helpers.convert(
napalm.base.helpers.ip, local_addr_raw, local_addr_raw
)
password = napalm.base.helpers.find_txt(
bgp_neighbor, "Password/Password/Password"
)
nhs = False
route_reflector = False
if group_name not in bgp_group_neighbors.keys():
bgp_group_neighbors[group_name] = {}
bgp_group_neighbors[group_name][peer] = {
"description": description,
"remote_as": peer_as,
"prefix_limit": build_prefix_limit(
af_table, prefix_limit, prefix_percent, prefix_timeout
),
"export_policy": export_policy,
"import_policy": import_policy,
"local_address": local_address,
"local_as": local_as,
"authentication_key": password,
"nhs": nhs,
"route_reflector_client": route_reflector,
}
if neighbor and peer == neighbor:
break
for bgp_group in result_tree.xpath(".//NeighborGroup"):
group_name = napalm.base.helpers.find_txt(
bgp_group, "Naming/NeighborGroupName"
)
if group and group != group_name:
continue
bgp_type = "external" # by default external
# must check
description = napalm.base.helpers.find_txt(bgp_group, "Description")
import_policy = napalm.base.helpers.find_txt(
bgp_group, "NeighborGroupAFTable/NeighborGroupAF/RoutePolicyIn"
)
export_policy = napalm.base.helpers.find_txt(
bgp_group, "NeighborGroupAFTable/NeighborGroupAF/RoutePolicyOut"
)
multipath = (
napalm.base.helpers.find_txt(
bgp_group, "NeighborGroupAFTable/NeighborGroupAF/Multipath"
)
== "true"
)
peer_as = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(bgp_group, "RemoteAS/AS_YY"), 0
)
local_as = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(bgp_group, "LocalAS/AS_YY"), bgp_asn
)
multihop_ttl = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(bgp_group, "EBGPMultihop/MaxHopCount"),
0,
)
local_addr_raw = napalm.base.helpers.find_txt(
bgp_group, "LocalAddress/LocalIPAddress/IPV4Address"
) or napalm.base.helpers.find_txt(
bgp_group, "LocalAddress/LocalIPAddress/IPV6Address"
)
local_address = napalm.base.helpers.convert(
napalm.base.helpers.ip, local_addr_raw, local_addr_raw
)
af_table = napalm.base.helpers.find_txt(
bgp_group, "NeighborAFTable/NeighborAF/Naming/AFName"
)
prefix_limit = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_group,
"NeighborGroupAFTable/NeighborGroupAF/MaximumPrefixes/PrefixLimit",
),
0,
)
prefix_percent = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_group,
"NeighborGroupAFTable/NeighborGroupAF/MaximumPrefixes/WarningPercentage",
),
0,
)
prefix_timeout = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_group,
"NeighborGroupAFTable/NeighborGroupAF/MaximumPrefixes/RestartTime",
),
0,
)
remove_private = True # is it specified in the XML?
bgp_config[group_name] = {
"apply_groups": [], # on IOS-XR will always be empty list!
"description": description,
"local_as": local_as,
"type": str(bgp_type),
"import_policy": import_policy,
"export_policy": export_policy,
"local_address": local_address,
"multipath": multipath,
"multihop_ttl": multihop_ttl,
"remote_as": peer_as,
"remove_private_as": remove_private,
"prefix_limit": build_prefix_limit(
af_table, prefix_limit, prefix_percent, prefix_timeout
),
"neighbors": bgp_group_neighbors.get(group_name, {}),
}
if group and group == group_name:
break
bgp_config["_"] = {
"apply_groups": [],
"description": "",
"local_as": bgp_asn,
"type": "",
"import_policy": "",
"export_policy": "",
"local_address": "",
"multipath": False,
"multihop_ttl": 0,
"remote_as": 0,
"remove_private_as": False,
"prefix_limit": {},
"neighbors": bgp_group_neighbors.get("", {}),
}
return bgp_config
def get_bgp_neighbors_detail(self, neighbor_address=""):
bgp_neighbors_detail = {}
active_vrfs = ["default"]
active_vrfs_rpc_request = "<Get><Operational><BGP><ConfigInstanceTable><ConfigInstance>\
<Naming><InstanceName>default</InstanceName></Naming><ConfigInstanceVRFTable/>\
</ConfigInstance></ConfigInstanceTable></BGP></Operational></Get>"
active_vrfs_rpc_reply = ETREE.fromstring(
self.device.make_rpc_call(active_vrfs_rpc_request)
)
active_vrfs_tree = active_vrfs_rpc_reply.xpath(".//ConfigVRF")
for active_vrf_tree in active_vrfs_tree:
active_vrfs.append(
napalm.base.helpers.find_txt(active_vrf_tree, "Naming/VRFName")
)
unique_active_vrfs = sorted(set(active_vrfs))
bgp_neighbors_vrf_all_rpc = "<Get><Operational><BGP><InstanceTable><Instance><Naming>\
<InstanceName>default</InstanceName></Naming>"
for active_vrf in unique_active_vrfs:
vrf_rpc = "<InstanceActive><VRFTable><VRF><Naming>{vrf_name}</Naming>\
<GlobalProcessInfo/><NeighborTable/></VRF></VRFTable></InstanceActive>"
bgp_neighbors_vrf_all_rpc += vrf_rpc.format(vrf_name=active_vrf)
bgp_neighbors_vrf_all_rpc += (
"</Instance></InstanceTable></BGP></Operational></Get>"
)
bgp_neighbors_vrf_all_tree = ETREE.fromstring(
self.device.make_rpc_call(bgp_neighbors_vrf_all_rpc)
)
_BGP_STATE_ = {
"0": "Unknown",
"1": "Idle",
"2": "Connect",
"3": "OpenSent",
"4": "OpenConfirm",
"5": "Active",
"6": "Established",
}
instance_active_list = bgp_neighbors_vrf_all_tree.xpath(
".//InstanceTable/Instance/InstanceActive/VRFTable/VRF"
)
for vrf_tree in instance_active_list:
vrf_name = napalm.base.helpers.find_txt(vrf_tree, "Naming/VRFName")
vrf_keepalive = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
vrf_tree, "GlobalProcessInfo/VRF/KeepAliveTime"
),
)
vrf_holdtime = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
vrf_tree, "GlobalProcessInfo/VRF/HoldTime"
),
)
if vrf_name not in bgp_neighbors_detail.keys():
bgp_neighbors_detail[vrf_name] = {}
for neighbor in vrf_tree.xpath("NeighborTable/Neighbor"):
up = (
napalm.base.helpers.find_txt(neighbor, "ConnectionState")
== "BGP_ST_ESTAB"
)
local_as = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "LocalAS"), 0
)
remote_as = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "RemoteAS"), 0
)
router_id = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(neighbor, "RouterID")
)
remote_address = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
neighbor, "Naming/NeighborAddress/IPV4Address"
)
or napalm.base.helpers.find_txt(
neighbor, "Naming/NeighborAddress/IPV6Address"
)
)
local_address_configured = (
napalm.base.helpers.find_txt(neighbor, "IsLocalAddressConfigured")
== "true"
)
local_address = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
neighbor, "ConnectionLocalAddress/IPV4Address"
)
or napalm.base.helpers.find_txt(
neighbor, "ConnectionLocalAddress/IPV6Address"
)
)
local_port = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "ConnectionLocalPort")
)
remote_address = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
neighbor, "ConnectionRemoteAddress/IPV4Address"
)
or napalm.base.helpers.find_txt(
neighbor, "ConnectionRemoteAddress/IPV6Address"
)
)
remote_port = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "ConnectionRemotePort")
)
multihop = (
napalm.base.helpers.find_txt(
neighbor, "IsExternalNeighborNotDirectlyConnected"
)
== "true"
)
remove_private_as = (
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/RemovePrivateASFromUpdates"
)
== "true"
)
multipath = (
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/SelectiveMultipathEligible"
)
== "true"
)
import_policy = napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/RoutePolicyIn"
)
export_policy = napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/RoutePolicyOut"
)
input_messages = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "MessgesReceived"), 0
)
output_messages = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "MessagesSent"), 0
)
flap_count = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(neighbor, "ConnectionDownCount"),
0,
)
messages_queued_out = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "MessagesQueuedOut"), 0
)
connection_state = (
napalm.base.helpers.find_txt(neighbor, "ConnectionState")
.replace("BGP_ST_", "")
.title()
)
if connection_state == "Estab":
connection_state = "Established"
previous_connection_state = napalm.base.helpers.convert(
str,
_BGP_STATE_.get(
napalm.base.helpers.find_txt(
neighbor, "PreviousConnectionState", "0"
)
),
)
active_prefix_count = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/NumberOfBestpaths"
),
0,
)
accepted_prefix_count = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesAccepted"
),
0,
)
suppressed_prefix_count = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesDenied"
),
0,
)
received_prefix_count = accepted_prefix_count + suppressed_prefix_count
advertised_prefix_count = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
neighbor, "AFData/Entry/PrefixesAdvertised"
),
0,
)
suppress_4byte_as = (
napalm.base.helpers.find_txt(neighbor, "Suppress4ByteAs") == "true"
)
local_as_prepend = (
napalm.base.helpers.find_txt(neighbor, "LocalASNoPrepend") != "true"
)
holdtime = (
napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "HoldTime"), 0
)
or vrf_holdtime
)
configured_holdtime = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "ConfiguredHoldTime"), 0
)
keepalive = (
napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(neighbor, "KeepAliveTime"), 0
)
or vrf_keepalive
)
configured_keepalive = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(neighbor, "ConfiguredKeepalive"),
0,
)
if remote_as not in bgp_neighbors_detail[vrf_name].keys():
bgp_neighbors_detail[vrf_name][remote_as] = []
bgp_neighbors_detail[vrf_name][remote_as].append(
{
"up": up,
"local_as": local_as,
"remote_as": remote_as,
"router_id": router_id,
"local_address": local_address,
"routing_table": vrf_name,
"local_address_configured": local_address_configured,
"local_port": local_port,
"remote_address": remote_address,
"remote_port": remote_port,
"multihop": multihop,
"multipath": multipath,
"import_policy": import_policy,
"export_policy": export_policy,
"input_messages": input_messages,
"output_messages": output_messages,
"input_updates": 0,
"output_updates": 0,
"messages_queued_out": messages_queued_out,
"connection_state": connection_state,
"previous_connection_state": previous_connection_state,
"last_event": "",
"remove_private_as": remove_private_as,
"suppress_4byte_as": suppress_4byte_as,
"local_as_prepend": local_as_prepend,
"holdtime": holdtime,
"configured_holdtime": configured_holdtime,
"keepalive": keepalive,
"configured_keepalive": configured_keepalive,
"active_prefix_count": active_prefix_count,
"received_prefix_count": received_prefix_count,
"accepted_prefix_count": accepted_prefix_count,
"suppressed_prefix_count": suppressed_prefix_count,
"advertised_prefix_count": advertised_prefix_count,
"flap_count": flap_count,
}
)
bgp_neighbors_detail["global"] = bgp_neighbors_detail.pop("default")
return bgp_neighbors_detail
def get_arp_table(self, vrf=""):
if vrf:
msg = "VRF support has not been added for this getter on this platform."
raise NotImplementedError(msg)
arp_table = []
rpc_command = "<Get><Operational><ARP></ARP></Operational></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for arp_entry in result_tree.xpath(".//EntryTable/Entry"):
interface = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(arp_entry, ".//InterfaceName")
)
ip = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(arp_entry, ".//Address")
)
age = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(arp_entry, ".//Age"), -1.0
)
mac_raw = napalm.base.helpers.find_txt(arp_entry, ".//HardwareAddress")
arp_table.append(
{
"interface": interface,
"mac": napalm.base.helpers.mac(mac_raw),
"ip": napalm.base.helpers.ip(ip),
"age": age,
}
)
return arp_table
def get_ntp_peers(self):
ntp_peers = {}
rpc_command = "<Get><Configuration><NTP></NTP></Configuration></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for version in ["IPV4", "IPV6"]:
xpath = ".//Peer{version}Table/Peer{version}".format(version=version)
for peer in result_tree.xpath(xpath):
peer_type = napalm.base.helpers.find_txt(
peer, "PeerType{version}/Naming/PeerType".format(version=version)
)
if peer_type != "Peer":
continue
peer_address = napalm.base.helpers.find_txt(
peer, "Naming/Address{version}".format(version=version)
)
if not peer_address:
continue
ntp_peers[peer_address] = {}
return ntp_peers
def get_ntp_servers(self):
ntp_servers = {}
rpc_command = "<Get><Configuration><NTP></NTP></Configuration></Get>"
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for version in ["IPV4", "IPV6"]:
xpath = ".//Peer{version}Table/Peer{version}".format(version=version)
for peer in result_tree.xpath(xpath):
peer_type = napalm.base.helpers.find_txt(
peer, "PeerType{version}/Naming/PeerType".format(version=version)
)
if peer_type != "Server":
continue
server_address = napalm.base.helpers.find_txt(
peer, "Naming/Address{version}".format(version=version)
)
if not server_address:
continue
ntp_servers[server_address] = {}
return ntp_servers
def get_ntp_stats(self):
ntp_stats = []
rpc_command = (
"<Get><Operational><NTP><NodeTable></NodeTable></NTP></Operational></Get>"
)
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
xpath = ".//NodeTable/Node/Associations/PeerSummaryInfo/Entry/PeerInfoCommon"
for node in result_tree.xpath(xpath):
synchronized = napalm.base.helpers.find_txt(node, "IsSysPeer") == "true"
address = napalm.base.helpers.find_txt(node, "Address")
if address == "DLRSC node":
continue
referenceid = napalm.base.helpers.find_txt(node, "ReferenceID")
hostpoll = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(node, "HostPoll", "0")
)
reachability = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(node, "Reachability", "0")
)
stratum = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(node, "Stratum", "0")
)
delay = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(node, "Delay", "0.0")
)
offset = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(node, "Offset", "0.0")
)
jitter = napalm.base.helpers.convert(
float, napalm.base.helpers.find_txt(node, "Dispersion", "0.0")
)
ntp_stats.append(
{
"remote": address,
"synchronized": synchronized,
"referenceid": referenceid,
"stratum": stratum,
"type": "",
"when": "",
"hostpoll": hostpoll,
"reachability": reachability,
"delay": delay,
"offset": offset,
"jitter": jitter,
}
)
return ntp_stats
def get_interfaces_ip(self):
interfaces_ip = {}
rpc_command_ipv4_ipv6 = "<Get><Operational><IPV4Network></IPV4Network>\
<IPV6Network></IPV6Network></Operational></Get>"
# only one request
ipv4_ipv6_tree = ETREE.fromstring(
self.device.make_rpc_call(rpc_command_ipv4_ipv6)
)
# parsing IPv4
ipv4_xpath = ".//IPV4Network/InterfaceTable/Interface"
for interface in ipv4_ipv6_tree.xpath(ipv4_xpath):
interface_name = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(interface, "Naming/InterfaceName")
)
primary_ip = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
interface, "VRFTable/VRF/Detail/PrimaryAddress"
)
)
primary_prefix = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
interface, "VRFTable/VRF/Detail/PrefixLength"
),
)
if interface_name not in interfaces_ip.keys():
interfaces_ip[interface_name] = {}
if "ipv4" not in interfaces_ip[interface_name].keys():
interfaces_ip[interface_name]["ipv4"] = {}
if primary_ip not in interfaces_ip[interface_name].get("ipv4", {}).keys():
interfaces_ip[interface_name]["ipv4"][primary_ip] = {
"prefix_length": primary_prefix
}
for secondary_address in interface.xpath(
"VRFTable/VRF/Detail/SecondaryAddress/Entry"
):
secondary_ip = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(secondary_address, "Address")
)
secondary_prefix = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(secondary_address, "PrefixLength")
)
if secondary_ip not in interfaces_ip[interface_name]:
interfaces_ip[interface_name]["ipv4"][secondary_ip] = {
"prefix_length": secondary_prefix
}
# parsing IPv6
ipv6_xpath = (
".//IPV6Network/NodeTable/Node/InterfaceData"
"/VRFTable/VRF/GlobalDetailTable/GlobalDetail"
)
for interface in ipv4_ipv6_tree.xpath(ipv6_xpath):
interface_name = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(interface, "Naming/InterfaceName")
)
if interface_name not in interfaces_ip.keys():
interfaces_ip[interface_name] = {}
if "ipv6" not in interfaces_ip[interface_name].keys():
interfaces_ip[interface_name]["ipv6"] = {}
for address in interface.xpath("AddressList/Entry"):
address_ip = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(address, "Address")
)
address_prefix = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(address, "PrefixLength")
)
if (
address_ip
not in interfaces_ip[interface_name].get("ipv6", {}).keys()
):
interfaces_ip[interface_name]["ipv6"][address_ip] = {
"prefix_length": address_prefix
}
return interfaces_ip
def get_mac_address_table(self):
mac_table = []
rpc_command = (
"<Get><Operational><L2VPNForwarding></L2VPNForwarding></Operational></Get>"
)
result_tree = ETREE.fromstring(self.device.make_rpc_call(rpc_command))
for mac_entry in result_tree.xpath(".//L2FIBMACDetailTable/L2FIBMACDetail"):
mac_raw = napalm.base.helpers.find_txt(mac_entry, "Naming/Address")
vlan = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(mac_entry, "Naming/Name", "").replace(
"vlan", ""
),
0,
)
interface = napalm.base.helpers.find_txt(
mac_entry, "Segment/AC/InterfaceHandle", ""
)
mac_table.append(
{
"mac": napalm.base.helpers.mac(mac_raw),
"interface": interface,
"vlan": vlan,
"active": True,
"static": False,
"moves": 0,
"last_move": 0.0,
}
)
return mac_table
def get_route_to(self, destination="", protocol="", longer=False):
routes = {}
global IP_RIBRoute
if not isinstance(destination, str):
raise TypeError("Please specify a valid destination!")
if longer:
raise NotImplementedError("Longer prefixes not yet supported for IOS-XR")
protocol = protocol.lower()
if protocol == "direct":
protocol = "connected"
dest_split = destination.split("/")
network = dest_split[0]
prefix_tag = ""
if len(dest_split) == 2:
prefix_tag = "<PrefixLength>{prefix_length}</PrefixLength>".format(
prefix_length=dest_split[1]
)
ipv = 4
try:
ipv = ipaddress.ip_address(network).version
except ValueError:
logger.error("Wrong destination IP Address format supplied to get_route_to")
raise TypeError("Wrong destination IP Address!")
if ipv == 6:
route_info_rpc_command = (
"<Get><Operational><IPV6_RIB><VRFTable><VRF><Naming><VRFName>"
"default</VRFName></Naming><AFTable><AF><Naming><AFName>IPv6</AFName></Naming>"
"<SAFTable>"
"<SAF><Naming><SAFName>Unicast</SAFName></Naming><IP_RIBRouteTable><{ipribroute}>"
"<Naming>"
"<RouteTableName>default</RouteTableName></Naming><RouteTable><Route><Naming>"
"<Address>"
"{network}</Address>{prefix}</Naming></Route></RouteTable></{ipribroute}>"
"</IP_RIBRouteTable></SAF></SAFTable></AF></AFTable></VRF></VRFTable></IPV6_RIB>"
"</Operational></Get>"
).format(network=network, prefix=prefix_tag, ipribroute=IP_RIBRoute)
else:
route_info_rpc_command = (
"<Get><Operational><RIB><VRFTable><VRF><Naming><VRFName>"
"default"
"</VRFName></Naming><AFTable><AF><Naming><AFName>IPv4</AFName></Naming>"
"<SAFTable><SAF>"
"<Naming><SAFName>Unicast</SAFName></Naming><IP_RIBRouteTable><{ipribroute}>"
"<Naming>"
"<RouteTableName>default</RouteTableName></Naming><RouteTable><Route><Naming>"
"<Address>"
"{network}</Address>{prefix}</Naming></Route></RouteTable></{ipribroute}>"
"</IP_RIBRouteTable>"
"</SAF></SAFTable></AF></AFTable></VRF></VRFTable></RIB></Operational></Get>"
).format(network=network, prefix=prefix_tag, ipribroute=IP_RIBRoute)
try:
routes_tree = ETREE.fromstring(
self.device.make_rpc_call(route_info_rpc_command)
)
except Exception:
pass
# Some versions of IOS-XR use IP_RIBRouteTableName instead of IP_RIBRoute.
# If IP_RIBRoute throws an exception, try again with IP_RIBRouteTableName
# and have subsequent get_route_to calls use that.
IP_RIBRoute = "IP_RIBRouteTableName"
route_info_rpc_command = route_info_rpc_command.replace(
"IP_RIBRoute>", "{ipribroute}>".format(ipribroute=IP_RIBRoute)
)
routes_tree = ETREE.fromstring(
self.device.make_rpc_call(route_info_rpc_command)
)
for route in routes_tree.xpath(".//Route"):
route_protocol = napalm.base.helpers.convert(
str, napalm.base.helpers.find_txt(route, "ProtocolName").lower()
)
if protocol and route_protocol != protocol:
continue # ignore routes learned via a different protocol
# only in case the user requested a certain protocol
route_details = {}
address = napalm.base.helpers.find_txt(route, "Prefix")
length = napalm.base.helpers.find_txt(route, "PrefixLength")
priority = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(route, "Priority")
)
age = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(route, "RouteAge")
)
destination = napalm.base.helpers.convert(
str, "{prefix}/{length}".format(prefix=address, length=length)
)
if destination not in routes.keys():
routes[destination] = []
route_details = {
"current_active": False,
"last_active": False,
"age": age,
"next_hop": "",
"protocol": route_protocol,
"outgoing_interface": "",
"preference": priority,
"selected_next_hop": False,
"inactive_reason": "",
"routing_table": "default",
"protocol_attributes": {},
}
# from BGP will try to get some more information
if route_protocol == "bgp" and C.SR_638170159_SOLVED:
# looks like IOS-XR does not filter correctly
# !IMPORTANT
bgp_route_info_rpc_command = "<Get><Operational><BGP><Active><DefaultVRF><AFTable>\
<AF><Naming><AFName>IPv4Unicast</AFName></Naming><PathTable><Path><Naming><Network>\
<IPV4Address>{network}</IPV4Address><IPV4PrefixLength>{prefix_len}\
</IPV4PrefixLength></Network></Naming></Path></PathTable></AF></AFTable>\
</DefaultVRF></Active></BGP></Operational></Get>".format(
network=network, prefix_len=dest_split[-1]
)
bgp_route_tree = ETREE.fromstring(
self.device.make_rpc_call(bgp_route_info_rpc_command)
)
for bgp_path in bgp_route_tree.xpath(".//Path"):
single_route_details = route_details.copy()
if "NotFound" not in bgp_path.keys():
best_path = (
napalm.base.helpers.find_txt(
bgp_path, "PathInformation/IsBestPath"
)
== "true"
)
local_preference = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_path,
"AttributesAfterPolicyIn/CommonAttributes/LocalPreference",
),
0,
)
local_preference = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_path,
"AttributesAfterPolicyIn/CommonAttributes/LocalPreference",
),
0,
)
remote_as = napalm.base.helpers.convert(
int,
napalm.base.helpers.find_txt(
bgp_path,
"AttributesAfterPolicyIn/CommonAttributes/NeighborAS",
),
0,
)
remote_address = napalm.base.helpers.ip(
napalm.base.helpers.find_txt(
bgp_path, "PathInformation/NeighborAddress/IPV4Address"
)
or napalm.base.helpers.find_txt(
bgp_path, "PathInformation/NeighborAddress/IPV6Address"
)
)
as_path = " ".join(
[
bgp_as.text
for bgp_as in bgp_path.xpath(
"AttributesAfterPolicyIn/CommonAttributes/NeighborAS/Entry"
)
]
)
next_hop = napalm.base.helpers.find_txt(
bgp_path, "PathInformation/NextHop/IPV4Address"
) or napalm.base.helpers.find_txt(
bgp_path, "PathInformation/NextHop/IPV6Address"
)
single_route_details["current_active"] = best_path
single_route_details["next_hop"] = next_hop
single_route_details["protocol_attributes"] = {
"local_preference": local_preference,
"as_path": as_path,
"remote_as": remote_as,
"remote_address": remote_address,
}
routes[destination].append(single_route_details)
else:
first_route = True
for route_entry in route.xpath("RoutePath/Entry"):
# get all possible entries
next_hop = napalm.base.helpers.find_txt(route_entry, "Address")
outgoing_interface = napalm.base.helpers.find_txt(
route_entry, "InterfaceName"
)
single_route_details = {}
single_route_details.update(route_details)
single_route_details.update(
{
"current_active": first_route,
"next_hop": next_hop,
"outgoing_interface": outgoing_interface,
}
)
routes[destination].append(single_route_details)
first_route = False
return routes
def get_snmp_information(self):
snmp_information = {}
snmp_rpc_command = "<Get><Configuration><SNMP></SNMP></Configuration></Get>"
snmp_result_tree = ETREE.fromstring(self.device.make_rpc_call(snmp_rpc_command))
_PRIVILEGE_MODE_MAP_ = {"ReadOnly": "ro", "ReadWrite": "rw"}
snmp_information = {
"chassis_id": napalm.base.helpers.find_txt(
snmp_result_tree, ".//ChassisID"
),
"contact": napalm.base.helpers.find_txt(snmp_result_tree, ".//Contact"),
"location": napalm.base.helpers.find_txt(snmp_result_tree, ".//Location"),
"community": {},
}
for community in snmp_result_tree.xpath(".//DefaultCommunity"):
name = napalm.base.helpers.find_txt(community, "Naming/CommunityName")
privilege = napalm.base.helpers.find_txt(community, "Priviledge")
acl = napalm.base.helpers.find_txt(community, "AccessList")
snmp_information["community"][name] = {
"mode": _PRIVILEGE_MODE_MAP_.get(privilege, ""),
"acl": acl,
}
return snmp_information
def get_probes_config(self):
sla_config = {}
_PROBE_TYPE_XML_TAG_MAP_ = {
"ICMPEcho": "icmp-ping",
"UDPEcho": "udp-ping",
"ICMPJitter": "icmp-ping-timestamp",
"UDPJitter": "udp-ping-timestamp",
}
sla_config_rpc_command = (
"<Get><Configuration><IPSLA></IPSLA></Configuration></Get>"
)
sla_config_result_tree = ETREE.fromstring(
self.device.make_rpc_call(sla_config_rpc_command)
)
for probe in sla_config_result_tree.xpath(".//Definition"):
probe_name = napalm.base.helpers.find_txt(probe, "Naming/OperationID")
operation_type = probe.xpath("OperationType")[0].getchildren()[0].tag
probe_type = _PROBE_TYPE_XML_TAG_MAP_.get(operation_type, "")
operation_xpath = "OperationType/{op_type}".format(op_type=operation_type)
operation = probe.xpath(operation_xpath)[0]
test_name = napalm.base.helpers.find_txt(operation, "Tag")
source = napalm.base.helpers.find_txt(operation, "SourceAddress")
target = napalm.base.helpers.find_txt(operation, "DestAddress")
test_interval = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(operation, "Frequency", "0")
)
probe_count = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(operation, "History/Buckets", "0")
)
if probe_name not in sla_config.keys():
sla_config[probe_name] = {}
if test_name not in sla_config[probe_name]:
sla_config[probe_name][test_name] = {}
sla_config[probe_name][test_name] = {
"probe_type": probe_type,
"source": source,
"target": target,
"probe_count": probe_count,
"test_interval": test_interval,
}
return sla_config
def get_probes_results(self):
sla_results = {}
_PROBE_TYPE_XML_TAG_MAP_ = {
"ICMPEcho": "icmp-ping",
"UDPEcho": "udp-ping",
"ICMPJitter": "icmp-ping-timestamp",
"UDPJitter": "udp-ping-timestamp",
}
sla_results_rpc_command = (
"<Get><Operational><IPSLA></IPSLA></Operational></Get>"
)
sla_results_tree = ETREE.fromstring(
self.device.make_rpc_call(sla_results_rpc_command)
)
probes_config = (
self.get_probes_config()
) # need to retrieve also the configuration
# source and tag/test_name not provided
for probe in sla_results_tree.xpath(".//Operation"):
probe_name = napalm.base.helpers.find_txt(probe, "Naming/OperationID")
test_name = list(probes_config.get(probe_name).keys())[0]
target = napalm.base.helpers.find_txt(
probe,
"History/Target/LifeTable/Life/BucketTable/Bucket[0]/TargetAddress\
/IPv4AddressTarget",
)
source = probes_config.get(probe_name).get(test_name, {}).get("source", "")
probe_type = _PROBE_TYPE_XML_TAG_MAP_.get(
napalm.base.helpers.find_txt(
probe, "Statistics/Latest/Target/SpecificStats/op_type"
)
)
probe_count = (
probes_config.get(probe_name).get(test_name, {}).get("probe_count", 0)
)
response_times = probe.xpath(
"History/Target/LifeTable/Life[last()]/BucketTable/Bucket/ResponseTime"
)
response_times = [
napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(response_time, ".", "0")
)
for response_time in response_times
]
rtt = 0.0
if len(response_times):
rtt = sum(response_times, 0.0) / len(response_times)
return_codes = probe.xpath(
"History/Target/LifeTable/Life[last()]/BucketTable/Bucket/ReturnCode"
)
return_codes = [
napalm.base.helpers.find_txt(return_code, ".")
for return_code in return_codes
]
last_test_loss = 0.0
if len(return_codes):
last_test_loss = napalm.base.helpers.convert(
int,
100
* (
1
- return_codes.count("ipslaRetCodeOK")
/ napalm.base.helpers.convert(float, len(return_codes))
),
)
rms = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe,
"Statistics/Aggregated/HourTable/Hour\
/Distributed/Target/DistributionIntervalTable/DistributionInterval/CommonStats\
/Sum2ResponseTime",
),
)
global_test_updates = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe,
"Statistics/Aggregated/HourTable/Hour\
/Distributed/Target/DistributionIntervalTable/DistributionInterval/CommonStats\
/UpdateCount",
),
)
jitter = 0.0
if global_test_updates:
jitter = rtt - (rms / global_test_updates) ** 0.5
# jitter = max(rtt - max(response_times), rtt - min(response_times))
current_test_min_delay = 0.0 # no stats for undergoing test :(
current_test_max_delay = 0.0
current_test_avg_delay = 0.0
last_test_min_delay = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe, "Statistics/Latest/Target/CommonStats/MinResponseTime"
),
)
last_test_max_delay = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe, "Statistics/Latest/Target/CommonStats/MaxResponseTime"
),
)
last_test_sum_delay = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe, "Statistics/Latest/Target/CommonStats/SumResponseTime"
),
)
last_test_updates = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe, "Statistics/Latest/Target/CommonStats/UpdateCount"
),
)
last_test_avg_delay = 0.0
if last_test_updates:
last_test_avg_delay = last_test_sum_delay / last_test_updates
global_test_min_delay = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe,
"Statistics/Aggregated/HourTable/Hour/Distributed/Target\
/DistributionIntervalTable/DistributionInterval/CommonStats/MinResponseTime",
),
)
global_test_max_delay = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe,
"Statistics/Aggregated/HourTable/Hour/Distributed/Target\
/DistributionIntervalTable/DistributionInterval/CommonStats/MaxResponseTime",
),
)
global_test_sum_delay = napalm.base.helpers.convert(
float,
napalm.base.helpers.find_txt(
probe,
"Statistics/Aggregated/HourTable/Hour\
/Distributed/Target/DistributionIntervalTable/DistributionInterval\
/CommonStats/SumResponseTime",
),
)
global_test_avg_delay = 0.0
if global_test_updates:
global_test_avg_delay = global_test_sum_delay / global_test_updates
if probe_name not in sla_results.keys():
sla_results[probe_name] = {}
sla_results[probe_name][test_name] = {
"target": target,
"source": source,
"probe_type": probe_type,
"probe_count": probe_count,
"rtt": rtt,
"round_trip_jitter": jitter,
"last_test_loss": last_test_loss,
"current_test_min_delay": current_test_min_delay,
"current_test_max_delay": current_test_max_delay,
"current_test_avg_delay": current_test_avg_delay,
"last_test_min_delay": last_test_min_delay,
"last_test_max_delay": last_test_max_delay,
"last_test_avg_delay": last_test_avg_delay,
"global_test_min_delay": global_test_min_delay,
"global_test_max_delay": global_test_max_delay,
"global_test_avg_delay": global_test_avg_delay,
}
return sla_results
def traceroute(
self,
destination,
source=C.TRACEROUTE_SOURCE,
ttl=C.TRACEROUTE_TTL,
timeout=C.TRACEROUTE_TIMEOUT,
vrf=C.TRACEROUTE_VRF,
):
traceroute_result = {}
ipv = 4
try:
ipv = ipaddress.ip_address(destination).version
except ValueError:
logger.error(
"Incorrect format of IP Address in traceroute \
with value provided:%s"
% (str(destination))
)
return {"error": "Wrong destination IP Address!"}
source_tag = ""
ttl_tag = ""
timeout_tag = ""
vrf_tag = ""
if source:
source_tag = "<Source>{source}</Source>".format(source=source)
if ttl:
ttl_tag = "<MaxTTL>{maxttl}</MaxTTL>".format(maxttl=ttl)
if timeout:
timeout_tag = "<Timeout>{timeout}</Timeout>".format(timeout=timeout)
if vrf:
vrf_tag = "<VRFName>{vrf}</VRFName>".format(vrf=vrf)
traceroute_rpc_command = "<Set><Action><TraceRoute><IPV{version}><Destination>{destination}\
</Destination>{vrf_tag}{source_tag}{ttl_tag}{timeout_tag}</IPV{version}></TraceRoute></Action>\
</Set>".format(
version=ipv,
destination=destination,
vrf_tag=vrf_tag,
source_tag=source_tag,
ttl_tag=ttl_tag,
timeout_tag=timeout_tag,
)
xml_tree_txt = self.device.make_rpc_call(traceroute_rpc_command)
traceroute_tree = ETREE.fromstring(xml_tree_txt)
results_tree = traceroute_tree.xpath(".//Results")
if results_tree is None or not len(results_tree):
return {"error": "Device returned empty results."}
results_error = napalm.base.helpers.find_txt(results_tree[0], "Error")
if results_error:
return {"error": results_error}
traceroute_result["success"] = {}
last_hop_index = 1
last_probe_index = 1
last_probe_ip_address = "*"
last_probe_host_name = ""
last_hop_dict = {"probes": {}}
for thanks_cisco in results_tree[0].getchildren():
tag_name = thanks_cisco.tag
tag_value = thanks_cisco.text
if tag_name == "HopIndex":
new_hop_index = napalm.base.helpers.convert(
int, napalm.base.helpers.find_txt(thanks_cisco, ".", "-1")
)
if last_hop_index and last_hop_index != new_hop_index:
traceroute_result["success"][last_hop_index] = copy.deepcopy(
last_hop_dict
)
last_hop_dict = {"probes": {}}
last_probe_ip_address = "*"
last_probe_host_name = ""
last_hop_index = new_hop_index
continue
tag_value = napalm.base.helpers.find_txt(thanks_cisco, ".", "")
if tag_name == "ProbeIndex":
last_probe_index = napalm.base.helpers.convert(int, tag_value, 0) + 1
if last_probe_index not in last_hop_dict.get("probes").keys():
last_hop_dict["probes"][last_probe_index] = {}
if not last_probe_host_name:
last_probe_host_name = last_probe_ip_address
last_hop_dict["probes"][last_probe_index] = {
"ip_address": napalm.base.helpers.convert(
str, last_probe_ip_address
),
"host_name": napalm.base.helpers.convert(str, last_probe_host_name),
"rtt": timeout * 1000.0,
}
continue
if tag_name == "HopAddress":
last_probe_ip_address = tag_value
continue
if tag_name == "HopHostName":
last_probe_host_name = tag_value
continue
if tag_name == "DeltaTime":
last_hop_dict["probes"][last_probe_index][
"rtt"
] = napalm.base.helpers.convert(float, tag_value, 0.0)
continue
if last_hop_index:
traceroute_result["success"][last_hop_index] = last_hop_dict
return traceroute_result
def get_users(self):
users = {}
_CISCO_GROUP_TO_CISCO_PRIVILEGE_MAP = {
"root-system": 15,
"operator": 5,
"sysadmin": 1,
"serviceadmin": 1,
"root-lr": 15,
}
_DEFAULT_USER_DETAILS = {"level": 0, "password": "", "sshkeys": []}
users_xml_req = "<Get><Configuration><AAA></AAA></Configuration></Get>"
users_xml_reply = ETREE.fromstring(self.device.make_rpc_call(users_xml_req))
for user_entry in users_xml_reply.xpath(".//Username"):
username = napalm.base.helpers.find_txt(user_entry, "Naming/Name")
group = napalm.base.helpers.find_txt(
user_entry, "UsergroupsUnderUsername/UsergroupUnderUsername/Naming/Name"
)
level = _CISCO_GROUP_TO_CISCO_PRIVILEGE_MAP.get(group, 0)
password = napalm.base.helpers.find_txt(user_entry, "Password/Password")
user_details = _DEFAULT_USER_DETAILS.copy()
user_details.update({"level": level, "password": str(password)})
users[username] = user_details
return users
def get_config(self, retrieve="all", full=False, sanitized=False):
config = {"startup": "", "running": "", "candidate": ""} # default values
# IOS-XR only supports "all" on "show run"
run_full = " all" if full else ""
filter_strings = [r"^Building configuration.*$", r"^!! IOS XR Configuration.*$"]
filter_pattern = napalm.base.helpers.generate_regex_or(filter_strings)
if retrieve.lower() in ["running", "all"]:
running = str(
self.device._execute_config_show(f"show running-config{run_full}")
)
running = re.sub(filter_pattern, "", running, flags=re.M)
config["running"] = running
if retrieve.lower() in ["candidate", "all"]:
candidate = str(
self.device._execute_config_show("show configuration merge")
)
candidate = re.sub(filter_pattern, "", candidate, flags=re.M)
config["candidate"] = candidate
if sanitized:
return napalm.base.helpers.sanitize_configs(
config, C.CISCO_SANITIZE_FILTERS
)
return config
|
753860e6b078fcd38f023e68f56f209485712272
|
61673ab9a42f7151de7337608c442fa6247f13bb
|
/beautifulsoup/attribute-with-html/main.py
|
c5e681210744a39553d8b9cf77c70d794f3515d0
|
[
"MIT"
] |
permissive
|
furas/python-examples
|
22d101670ecd667a29376d7c7d7d86f8ec71f6cf
|
95cb53b664f312e0830f010c0c96be94d4a4db90
|
refs/heads/master
| 2022-08-23T23:55:08.313936
| 2022-08-01T14:48:33
| 2022-08-01T14:48:33
| 45,575,296
| 176
| 91
|
MIT
| 2021-02-17T23:33:37
| 2015-11-04T23:54:32
|
Python
|
UTF-8
|
Python
| false
| false
| 557
|
py
|
main.py
|
from bs4 import BeautifulSoup as BS
text = '''
<tr data-title='<img src="url1.jpg" alt="1">' >
<tr data-title='<img src="url2.jpg" alt="2">' >
'''
soup = BS(text, 'html.parser')
all_items = soup.find_all('tr', {"data-title": True})
for item in all_items:
print('item:', item['data-title'])
#print('item:', item.attrs.get('data-title'))
#print('item:', item.attrs['data-title'])
#print('item:', item.get('data-title'))
link = item.get('data-title')
s = BS(link, 'html.parser')
print('src:', s.find('img')['src'])
|
80366cef20f193beae54b305f25ee90c7173ab90
|
cb4f118412a55c52d720bc79e4074606622920ac
|
/tests/unit/physics_engine/test_physics_engine2.py
|
9b312f8a9dcdf2061ae28bce0e2791a3b4d07b69
|
[
"MIT"
] |
permissive
|
pythonarcade/arcade
|
3e536306f0c44f911de149b58958d8b609ffad4b
|
908664efc256697d3098a347f63d217d97841782
|
refs/heads/development
| 2023-08-29T02:53:01.599145
| 2023-08-26T16:54:34
| 2023-08-26T16:54:34
| 49,003,082
| 786
| 215
|
NOASSERTION
| 2023-09-12T18:38:54
| 2016-01-04T14:46:52
|
Python
|
UTF-8
|
Python
| false
| false
| 10,546
|
py
|
test_physics_engine2.py
|
""" Physics engine tests. """
import arcade
OUT_OF_THE_WAY = (250, 250)
def basic_tests(moving_sprite, wall_list, physics_engine):
"""Run basic tests that can be done by both engines."""
wall_sprite_1 = wall_list[0]
wall_sprite_2 = wall_list[1]
wall_sprite_2.position = OUT_OF_THE_WAY
# --- Collisions between a moving sprite and one wall block
# Two non-moving sprites side-by-side
wall_sprite_1.position = (10, 0)
wall_sprite_1.angle = 0
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 0
collisions = physics_engine.update()
assert moving_sprite.position == (0, 0)
assert len(collisions) == 0
# Move up to wall
wall_sprite_1.position = (11, 0)
moving_sprite.position = (0, 0)
moving_sprite.change_x = 1
moving_sprite.change_y = 0
collisions = physics_engine.update()
assert moving_sprite.position == (1, 0)
assert len(collisions) == 0
# Move into wall going left to right
for speed in range(2, 10):
wall_sprite_1.position = (11, 0)
moving_sprite.position = (0, 0)
moving_sprite.change_x = speed
moving_sprite.change_y = 0
collisions = physics_engine.update()
assert moving_sprite.position == (1, 0)
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
# Move into wall going right to left
for speed in range(2, 10):
wall_sprite_1.position = (-11, 0)
moving_sprite.position = (0, 0)
moving_sprite.change_x = -speed
moving_sprite.change_y = 0
collisions = physics_engine.update()
assert moving_sprite.position == (-1, 0)
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
# Move into wall going downwards
for speed in range(2, 10):
wall_sprite_1.position = (0, -11)
moving_sprite.position = (0, 0)
moving_sprite.change_x = 0
moving_sprite.change_y = -speed
collisions = physics_engine.update()
assert moving_sprite.position == (0, -1)
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
# Move into wall going up
for speed in range(2, 10, 1):
wall_sprite_1.position = (0, 11)
moving_sprite.position = (0, 0)
moving_sprite.change_x = 0
moving_sprite.change_y = speed
collisions = physics_engine.update()
assert moving_sprite.position == (0, 1)
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
# --- Check rotating collision
# - Rotate, with block to the right
# Check rotation one degree
wall_sprite_1.position = (10, 0)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 1
collisions = physics_engine.update()
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
assert moving_sprite.position == (-1, 0)
# Check rotation 45 degrees
wall_sprite_1.position = (10, 0)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 45
collisions = physics_engine.update()
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
assert moving_sprite.position == (-4, 0)
# - Rotate, with block to the left
# Check rotation one degree
wall_sprite_1.position = (-10, 0)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 1
collisions = physics_engine.update()
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
assert moving_sprite.position == (1, 0)
# Check rotation 45 degrees
wall_sprite_1.position = (-10, 0)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 45
collisions = physics_engine.update()
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
assert moving_sprite.position == (4, 0)
# - Rotate, with block above
# Check rotation one degree
wall_sprite_1.position = (0, 10)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 1
collisions = physics_engine.update()
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
assert moving_sprite.position == (0, -1)
# Check rotation 45 degrees
wall_sprite_1.position = (0, 10)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 45
collisions = physics_engine.update()
assert len(collisions) == 1
assert collisions[0] == wall_sprite_1
assert moving_sprite.position == (0, -4)
# - Rotate, between two blocks
# Check rotation one degree
wall_sprite_1.position = (10, 0)
wall_sprite_2.position = (-10, 0)
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 1
collisions = physics_engine.update()
assert len(collisions) == 2
assert wall_sprite_1 in collisions
assert wall_sprite_2 in collisions
assert moving_sprite.position == (0, 0)
# --- Check pre-existing collision
wall_sprite_1.position = (9, 0)
wall_sprite_2.position = OUT_OF_THE_WAY
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = 0
moving_sprite.change_y = 0
moving_sprite.change_angle = 0
collisions = physics_engine.update()
assert moving_sprite.position == (-1, 0)
assert len(collisions) == 0
def simple_engine_tests(moving_sprite, wall_list, physics_engine):
wall_sprite_1 = wall_list[0]
wall_sprite_2 = wall_list[1]
wall_sprite_2.position = OUT_OF_THE_WAY
# --- Collide on angle
wall_sprite_1.position = (15, -5)
wall_sprite_1.angle = 45
for speed in range(2, 10):
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = speed
moving_sprite.change_y = 0
moving_sprite.change_angle = 0
collisions = physics_engine.update()
assert moving_sprite.position == (2, 0)
if speed == 2:
assert len(collisions) == 0
else:
assert len(collisions) == 1
wall_sprite_1.position = (-15, -5)
wall_sprite_1.angle = 45
for speed in range(2, 10):
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = -speed
moving_sprite.change_y = 0
moving_sprite.change_angle = 0
collisions = physics_engine.update()
assert moving_sprite.position == (-2, 0)
if speed == 2:
assert len(collisions) == 0
else:
assert len(collisions) == 1
def platformer_tests(moving_sprite, wall_list, physics_engine):
wall_sprite_1 = wall_list[0]
wall_sprite_2 = wall_list[1]
wall_sprite_2.position = OUT_OF_THE_WAY
wall_sprite_1.position = (15, -5)
wall_sprite_1.angle = 45
moving_sprite.position = (3, 1)
moving_sprite.angle = 0
collisions = arcade.check_for_collision_with_list(moving_sprite, wall_list)
print(f"\n **** {len(collisions)}")
print("")
# --- Collide on angle
wall_sprite_1.position = (15, -5)
wall_sprite_1.angle = 45
for speed in range(2, 7):
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = speed
moving_sprite.change_y = 0
moving_sprite.change_angle = 0
collisions = physics_engine.update()
if speed == 2:
assert moving_sprite.position == (2, 0)
elif speed == 3:
assert moving_sprite.position == (3, 1)
elif speed == 4:
assert moving_sprite.position == (4, 2)
elif speed == 5:
assert moving_sprite.position == (5, 3)
elif speed == 6:
assert moving_sprite.position == (6, 4)
wall_sprite_1.position = (-15, -5)
wall_sprite_1.angle = 45
for speed in range(2, 7):
moving_sprite.position = (0, 0)
moving_sprite.angle = 0
moving_sprite.change_x = -speed
moving_sprite.change_y = 0
moving_sprite.change_angle = 0
collisions = physics_engine.update()
if speed == 2:
assert moving_sprite.position == (-2, 0)
elif speed == 3:
assert moving_sprite.position == (-3, 1)
elif speed == 4:
assert moving_sprite.position == (-4, 2)
elif speed == 5:
assert moving_sprite.position == (-5, 3)
elif speed == 6:
assert moving_sprite.position == (-6, 4)
# Move up to wall
wall_sprite_1.position = OUT_OF_THE_WAY
physics_engine.gravity_constant = 1
moving_sprite.position = (0, 0)
moving_sprite.change_x = 1
moving_sprite.change_y = 0
collisions = physics_engine.update()
assert moving_sprite.position == (1, -1)
collisions = physics_engine.update()
assert moving_sprite.position == (2, -3)
collisions = physics_engine.update()
assert moving_sprite.position == (3, -6)
def test_main(window: arcade.Window):
character_list = arcade.SpriteList()
wall_list = arcade.SpriteList()
moving_sprite = arcade.SpriteSolidColor(width=10, height=10, color=arcade.color.RED)
character_list.append(moving_sprite)
wall_sprite = arcade.SpriteSolidColor(width=10, height=10, color=arcade.color.BLUE)
wall_list.append(wall_sprite)
wall_sprite = arcade.SpriteSolidColor(10, 10, color=arcade.color.BLUE)
wall_sprite.position = OUT_OF_THE_WAY
wall_list.append(wall_sprite)
physics_engine = arcade.PhysicsEngineSimple(moving_sprite, wall_list)
basic_tests(moving_sprite, wall_list, physics_engine)
simple_engine_tests(moving_sprite, wall_list, physics_engine)
physics_engine = arcade.PhysicsEnginePlatformer(
moving_sprite, wall_list, gravity_constant=0.0
)
basic_tests(moving_sprite, wall_list, physics_engine)
platformer_tests(moving_sprite, wall_list, physics_engine)
|
f2c0ea5af722684985970d5293f7743f930286e9
|
e8846f706a428a91659ac6e24974dc696089fe4a
|
/pandapower/control/util/characteristic.py
|
bb714c7f7fc2157ebab790db62a299fe6ed773fe
|
[
"BSD-3-Clause"
] |
permissive
|
e2nIEE/pandapower
|
3e434bf81b29e9c88905abbd82fd0309e2191ffb
|
5592ba1f6fcd727053a37dcf246b9bf36874c24a
|
refs/heads/develop
| 2023-09-03T23:21:25.979973
| 2023-08-31T11:00:17
| 2023-08-31T11:00:17
| 78,748,060
| 608
| 481
|
NOASSERTION
| 2023-09-14T18:22:08
| 2017-01-12T13:27:53
|
Python
|
UTF-8
|
Python
| false
| false
| 6,752
|
py
|
characteristic.py
|
# -*- coding: utf-8 -*-
# Copyright (c) 2016-2023 by University of Kassel and Fraunhofer Institute for Energy Economics
# and Energy System Technology (IEE), Kassel. All rights reserved.
from builtins import zip
from builtins import object
from numpy import interp
from scipy.interpolate import interp1d
from pandapower.io_utils import JSONSerializableClass
class Characteristic(JSONSerializableClass):
"""
This class represents a characteristics curve. The curve is described as a piecewise linear function.
INPUT:
**pts** - Expects two (or more) points of the function (i.e. kneepoints)
OPTIONAL:
**eps** - An epsilon to compare the difference to
The class has an implementation of the ``__call__`` method, which allows using it interchangeably with other interpolator objects,
e.g. ``scipy.interpolate.interp1d``, ``scipy.interpolate.CubicSpline``, ``scipy.interpolate.PPoly``, etc.
Example usage:
Create a simple function from two points and ask for the target y-value for a
given x-value.
Assume a characteristics curve in which for voltages < 0.95pu a power of 10kW
is desired, linear rising to a max. of 20 kW at 1.05 pu
::
You can give points by lists of x/y-values
>>> c = Characteristic(net, x_values=[0.95, 1.05],y_values=[10, 20])
>>> c(x=1.0)
15.0
or pass a list of points (x,y)
>>> c = Characteristic.from_points(net,points=[(0.95, 10), (1.05, 20)])
>>> c(x=1.0)
15.0
or in a simple case from a gradient, its zero crossing and the maximal values for y
>>> c = Characteristic.from_gradient(net,zero_crossing=-85,gradient=100,y_min=10,y_max=20)
>>> c(x=1.0)
15.0
Values are constant beyond the first and last defined points
>>> c(x=42)
20.0
>>> c(x=-42)
10.0
Create a curve with many points and ask for the difference between the y-value being measured
and the expected y-value for a given x-value
>>> c = Characteristic.from_points(net,points=[(1,2),(2,4),(3,2),(42,24)])
>>> c.diff(x=2.5, measured=3)
0.0
You can also ask if a y-values satisfies the curve at a certain x-value. Note how the use of
an epsilon behaves (for x=2.5 we expect 3.0):
>>> c.satisfies(x=2.5, measured=3.099999999, epsilon=0.1)
True
>>> c.satisfies(x=2.5, measured=3.1, epsilon=0.1)
False
"""
def __init__(self, net, x_values, y_values, **kwargs):
super().__init__()
self.x_vals = x_values
self.y_vals = y_values
self.index = super().add_to_net(net, "characteristic")
@classmethod
def from_points(cls, net, points, **kwargs):
unzipped = list(zip(*points))
return cls(net, unzipped[0], unzipped[1], **kwargs)
@classmethod
def from_gradient(cls, net, zero_crossing, gradient, y_min, y_max, **kwargs):
x_left = (y_min - zero_crossing) / float(gradient)
x_right = (y_max - zero_crossing) / float(gradient)
return cls(net, [x_left, x_right], [y_min, y_max], **kwargs)
def diff(self, x, measured):
"""
INPUT:
**x** - The x-value at which the current y-value is measured
**actual** - The actual y-value being measured.
**return** - The difference between actual and expected value.
"""
return measured - self(x)
def satisfies(self, x, measured, epsilon):
"""
INPUT:
**x** - The x-value at which the current y-value is measured
**measured** - The actual y-value being measured.
OUTPUT:
Whether or not the point satisfies the characteristics curve with respect to the
epsilon being set
"""
if abs(self.diff(x, measured)) < epsilon:
return True
else:
return False
def __call__(self, x):
"""
INPUT:
**x** - An x-value
OUTPUT:
The corresponding target value of this characteristics
"""
return interp(x, self.x_vals, self.y_vals)
def __repr__(self):
return self.__class__.__name__
class SplineCharacteristic(Characteristic):
"""
SplineCharacteristic interpolates the y-value(s) for the given x-value(s) according to a non-linear function.
Internally the interpolator object interp1d from scipy.interpolate is used.
By default, the function is quadratic, but the user can specify other methods (refer to the documentation of
interp1d). The fill_value can be specified as "extrapolate" so that even x-values outside of the specified
range can be used and yield y-values outside the specified y range. Alternatively, the behavior of
Characteristic can be followed by providing a tuple for the fill value for x outside the specified range,
refer to the documentation of interp1d for more details. We set the parameter bounds_error to False.
INPUT:
**net**
**x_values**
**y_values**
**fill_value**
"""
json_excludes = ["self", "__class__", "_interpolator"]
def __init__(self, net, x_values, y_values, kind="quadratic", fill_value="extrapolate", **kwargs):
super().__init__(net, x_values=x_values, y_values=y_values, **kwargs)
self.fill_value = fill_value
self.kind = kind
@property
def interpolator(self):
"""
We need to store the interpolator in a property because we need to serialize
the characteristic. Instead of storing the serialized interpolator, we store the
x_values and y_values (the attribute _interpolator is ecluded from serialization by
adding it to json_excludes). For it to work, we need to recreate the interpolator on
demand. As soon as the characteristic is called, if the interpolator is there,
we can use it. If not, we recreate it.
"""
return self._interpolator
@interpolator.getter
def interpolator(self):
if not hasattr(self, '_interpolator'):
self._interpolator = interp1d(self.x_vals, self.y_vals, kind=self.kind, bounds_error=False,
fill_value=self.fill_value)
return self._interpolator
def __call__(self, x):
"""
This method allows calling the SciPy interpolator object directly.
Codacy is complaining about this, but it is not a problem.
INPUT:
**x** (float) - The x-value at which the current y-value is interpolated for.
OUTPUT:
The interpolated y-value.
"""
return self.interpolator(x)
|
30a6d1e8f4fde8ac9d62022fdb6da08919625314
|
6a8bc7da3104726f894ae360fce6a43a54b30812
|
/test/conftest.py
|
f2c672fbf0827e53c659b9b48a35f8282cbb5474
|
[
"Apache-2.0"
] |
permissive
|
gradio-app/gradio
|
0b6b29bb0029ad3b8fc1b143f111b1230b29d23a
|
e4e7a4319924aaf51dcb18d07d0c9953d4011074
|
refs/heads/main
| 2023-09-01T10:56:50.822550
| 2023-09-01T00:28:01
| 2023-09-01T00:28:01
| 162,405,963
| 21,224
| 1,537
|
Apache-2.0
| 2023-09-14T21:42:00
| 2018-12-19T08:24:04
|
Python
|
UTF-8
|
Python
| false
| false
| 1,820
|
py
|
conftest.py
|
import inspect
import pathlib
from contextlib import contextmanager
import pytest
from gradio_client import Client
import gradio as gr
def pytest_configure(config):
config.addinivalue_line(
"markers", "flaky: mark test as flaky. Failure will not cause te"
)
@pytest.fixture
def test_file_dir():
return pathlib.Path(pathlib.Path(__file__).parent, "test_files")
@pytest.fixture
def io_components():
classes_to_check = gr.components.IOComponent.__subclasses__()
subclasses = []
while classes_to_check:
subclass = classes_to_check.pop()
children = subclass.__subclasses__()
if children:
classes_to_check.extend(children)
if "value" in inspect.signature(subclass).parameters:
subclasses.append(subclass)
return subclasses
@pytest.fixture
def connect():
@contextmanager
def _connect(demo: gr.Blocks, serialize=True):
_, local_url, _ = demo.launch(prevent_thread_lock=True)
try:
yield Client(local_url, serialize=serialize)
finally:
# A more verbose version of .close()
# because we should set a timeout
# the tests that call .cancel() can get stuck
# waiting for the thread to join
if demo.enable_queue:
demo._queue.close()
demo.is_running = False
demo.server.should_exit = True
demo.server.thread.join(timeout=1)
return _connect
@pytest.fixture(autouse=True)
def gradio_temp_dir(monkeypatch, tmp_path):
"""tmp_path is unique to each test function.
It will be cleared automatically according to pytest docs: https://docs.pytest.org/en/6.2.x/reference.html#tmp-path
"""
monkeypatch.setenv("GRADIO_TEMP_DIR", str(tmp_path))
return tmp_path
|
9627e0437ae06a6c8da87542330743259c31d87d
|
1dcdb9301449b6d9fe704fcf630a4203758f0aac
|
/gravity/urls.py
|
71a8dbad5572082750ff34cca4e6a2bcadb54cde
|
[
"MIT",
"BSD-3-Clause",
"LicenseRef-scancode-other-permissive",
"GPL-3.0-only",
"PostgreSQL",
"BSD-2-Clause"
] |
permissive
|
thorrak/fermentrack
|
d6daeccbc2a4ea9189e6ee10c97ac4458a495585
|
1aea05b07b9445edce2f39480b03c93eced125e6
|
refs/heads/master
| 2023-09-06T09:43:18.143994
| 2023-09-04T21:51:51
| 2023-09-04T21:51:51
| 77,583,287
| 126
| 75
|
MIT
| 2023-09-04T21:51:52
| 2016-12-29T04:43:55
|
Python
|
UTF-8
|
Python
| false
| false
| 6,397
|
py
|
urls.py
|
from django.conf.urls import url
from django.contrib import admin
from django.conf import settings
from django.conf.urls.static import static
import gravity.views
import gravity.views_ispindel
import gravity.views_tilt
import gravity.api.sensors
app_name = "gravity"
# This gets added to the app's urlpatterns
gravity_urlpatterns = [
## Device Guided Setup Views
url(r'^gravity/$', gravity.views.gravity_list, name='gravity_list'),
url(r'^gravity/add/$', gravity.views.gravity_add_board, name='gravity_add_board'),
url(r'^gravity/manual_point/(?P<manual_sensor_id>[A-Za-z0-9]{1,20})/$', gravity.views.gravity_add_point, name='gravity_add_point'),
# url(r'^gravity/add/tilt/$', firmware_flash.views.firmware_refresh_list, name='firmware_flash_refresh_list'),
# url(r'^gravity/add/tilt/$', firmware_flash.views.firmware_refresh_list, name='firmware_flash_refresh_list'),
# Sensor Views
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/$', gravity.views.gravity_dashboard, name='gravity_dashboard'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/log/(?P<log_id>[A-Za-z0-9]{1,20})/view/$', gravity.views.gravity_dashboard, name='gravity_dashboard_log'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/attach/$', gravity.views.gravity_attach, name='gravity_attach'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/detach/$', gravity.views.gravity_detach, name='gravity_detach'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/uninstall/$', gravity.views.gravity_uninstall, name='gravity_uninstall'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/manage/$', gravity.views.gravity_manage, name='gravity_manage'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/log/(?P<log_id>[A-Za-z0-9]{1,20})/annotations.json$', gravity.views.almost_json_view, name='gravity_almost_json_view'),
# Sensor Log Views
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/log/create/$', gravity.views.gravity_log_create, name='gravity_log_create'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/log/stop/$', gravity.views.gravity_log_stop, name='gravity_log_stop'),
# Log Management
url(r'^gravity/logs/$', gravity.views.gravity_log_list, name='gravity_log_list'),
url(r'^gravity/logs/(?P<log_id>\d{1,20})/delete/$', gravity.views.gravity_log_delete, name='gravity_log_delete'),
# API Calls
url(r'^api/gravity/(?P<device_id>\d{1,20})/$', gravity.api.sensors.get_gravity_sensors, name="getSensor"), # For a single device
url(r'^api/gravity/$', gravity.api.sensors.get_gravity_sensors, name="getSensors"), # For all sensors
url(r'^api/gravity/ispindel/(?P<device_id>\d{1,20})/$', gravity.api.sensors.get_ispindel_extras, name="get_ispindel_extras"), # Specific to iSpindel devices, allows for easy calibration
url(r'^api/gravity/tilt/(?P<device_id>\d{1,20})/$', gravity.api.sensors.get_tilt_extras, name="get_tilt_extras"), # Specific to Tilt Hydrometers, allows for easy calibration
# iSpindel specific Views
url(r'^i[sS]{1}pind[el]{2}/?$', gravity.views_ispindel.ispindel_handler, name="gravity_ispindel"), # Handler for ispindel gravity readings
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/ispindel/setup/$', gravity.views_ispindel.gravity_ispindel_setup, name='gravity_ispindel_setup'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/ispindel/coefficients/$', gravity.views_ispindel.gravity_ispindel_coefficients, name='gravity_ispindel_coefficients'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/ispindel/calibration/add/$', gravity.views_ispindel.gravity_ispindel_add_calibration_point, name='gravity_ispindel_add_calibration_point'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/ispindel/calibration/delete/(?P<point_id>[A-Za-z0-9]{1,20})/$', gravity.views_ispindel.gravity_ispindel_delete_calibration_point, name='gravity_ispindel_delete_calibration_point'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/ispindel/calibration/calibrate/$', gravity.views_ispindel.gravity_ispindel_calibrate, name='gravity_ispindel_calibrate'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/ispindel/calibration/guided/(?P<step>[A-Za-z0-9]{1,20})$', gravity.views_ispindel.gravity_ispindel_guided_calibration, name='gravity_ispindel_guided_calibration'),
# Tilt specific Views
url(r'^[tT]{1}ilt[bB]{1}ridge/?$', gravity.views_tilt.tiltbridge_handler, name="gravity_tiltbridge"), # Handler for tiltbridge gravity readings
# url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/tilt/setup/$', gravity.views_tilt.gravity_tilt_setup, name='gravity_tilt_setup'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/tilt/coefficients/gravity/$', gravity.views_tilt.gravity_tilt_coefficients, name='gravity_tilt_coefficients'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/tilt/calibration/gravity/add/$', gravity.views_tilt.gravity_tilt_add_gravity_calibration_point, name='gravity_tilt_add_gravity_calibration_point'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/tilt/calibration/gravity/delete/(?P<point_id>[A-Za-z0-9]{1,20})/$', gravity.views_tilt.gravity_tilt_delete_gravity_calibration_point, name='gravity_tilt_delete_gravity_calibration_point'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/tilt/calibration/gravity/calibrate/$', gravity.views_tilt.gravity_tilt_calibrate, name='gravity_tilt_calibrate'),
url(r'^gravity/sensor/(?P<sensor_id>[A-Za-z0-9]{1,20})/tilt/calibration/gravity/guided/(?P<step>[A-Za-z0-9]{1,20})$', gravity.views_tilt.gravity_tilt_guided_calibration, name='gravity_tilt_guided_calibration'),
# TiltBridge specific views
url(r'^gravity/tiltbridge/add/$', gravity.views_tilt.gravity_tiltbridge_add, name='gravity_tiltbridge_add'),
url(r'^gravity/tiltbridge/update/(?P<tiltbridge_id>[A-Za-z0-9]{1,20})/set_url/$', gravity.views_tilt.gravity_tiltbridge_set_url, name='gravity_tiltbridge_set_url'),
url(r'^gravity/tiltbridge/update/(?P<tiltbridge_id>[A-Za-z0-9]{1,20})/set_url/(?P<sensor_id>[A-Za-z0-9]{1,20})$', gravity.views_tilt.gravity_tiltbridge_set_url, name='gravity_tiltbridge_set_url'),
url(r'^gravity/tiltbridge/urlerror/(?P<tiltbridge_id>[A-Za-z0-9]+)/$', gravity.views_tilt.gravity_tiltbridge_urlerror, name='gravity_tiltbridge_urlerror'),
]
|
e85bc81cab822a2a17a94423f71b393562985a05
|
771c1e2011a85a287c766b1a3d299ced2e6f799f
|
/src/electionguard_cli/mark_ballots/__init__.py
|
87037fc44ca73e4501f2df180b3349324f65dafb
|
[
"MIT"
] |
permissive
|
microsoft/electionguard-python
|
f50f64a473a8d77984a2faf4aa8db40cebb5c201
|
b3ddc2a732f6c5f078a3afbe05b00d632a2ff5e0
|
refs/heads/main
| 2023-08-03T12:44:35.322716
| 2022-10-28T12:47:18
| 2022-10-28T12:47:18
| 246,392,956
| 143
| 117
|
MIT
| 2023-08-02T00:24:32
| 2020-03-10T19:46:06
|
Python
|
UTF-8
|
Python
| false
| false
| 1,182
|
py
|
__init__.py
|
from electionguard_cli.mark_ballots import mark_ballot_inputs
from electionguard_cli.mark_ballots import mark_ballots_election_builder_step
from electionguard_cli.mark_ballots import mark_ballots_input_retrieval_step
from electionguard_cli.mark_ballots import mark_ballots_publish_step
from electionguard_cli.mark_ballots import mark_command
from electionguard_cli.mark_ballots.mark_ballot_inputs import (
MarkBallotInputs,
)
from electionguard_cli.mark_ballots.mark_ballots_election_builder_step import (
MarkBallotsElectionBuilderStep,
)
from electionguard_cli.mark_ballots.mark_ballots_input_retrieval_step import (
MarkBallotsInputRetrievalStep,
)
from electionguard_cli.mark_ballots.mark_ballots_publish_step import (
MarkBallotsPublishStep,
)
from electionguard_cli.mark_ballots.mark_command import (
MarkBallotsCommand,
)
__all__ = [
"MarkBallotInputs",
"MarkBallotsCommand",
"MarkBallotsElectionBuilderStep",
"MarkBallotsInputRetrievalStep",
"MarkBallotsPublishStep",
"mark_ballot_inputs",
"mark_ballots_election_builder_step",
"mark_ballots_input_retrieval_step",
"mark_ballots_publish_step",
"mark_command",
]
|
8f9aceaa83bede8101bed68650931ade636e7471
|
c83318a170bcf9728282820190918bd4c76ffaa6
|
/synology_api/__init__.py
|
6623863ce7114a7ef9f832aa34ace52e7d86bf8f
|
[
"MIT"
] |
permissive
|
N4S4/synology-api
|
9ae3ffb50f4a0d6aacff448a7fec000888076091
|
e355c443a05289c366f85915982eb5006b874a25
|
refs/heads/master
| 2023-05-25T21:59:50.721096
| 2023-05-05T19:42:35
| 2023-05-05T19:42:35
| 138,232,891
| 418
| 119
|
MIT
| 2023-09-13T07:58:39
| 2018-06-21T23:43:47
|
Python
|
UTF-8
|
Python
| false
| false
| 426
|
py
|
__init__.py
|
from . import \
audiostation,\
auth,\
base_api_core,\
directory_server,\
docker_api,\
drive_admin_console,\
core_active_backup,\
core_backup,\
core_certificate,\
core_sys_info,\
downloadstation,\
log_center,\
vpn,\
oauth,\
security_advisor,\
dhcp_server,\
notestation,\
filestation,\
photos,\
usb_copy,\
virtualization,\
universal_search
|
df217355452edce35331bc7e8dd5d2119ac63418
|
77861deda8b3046bdda221d3cb80b77e84b14523
|
/avx512-binomialcoef/python/overflow.py
|
ee425a84f23e22c727ed43287b9714ad29a04b05
|
[
"BSD-2-Clause"
] |
permissive
|
WojciechMula/toys
|
b73f09212ca19f1e76bbf2afaa5ad2efcea95175
|
6110b59de45dc1ce44388b21c6437eff49a7655c
|
refs/heads/master
| 2023-08-18T12:54:25.919406
| 2023-08-05T09:20:14
| 2023-08-05T09:20:14
| 14,905,115
| 302
| 44
|
BSD-2-Clause
| 2020-04-17T17:10:42
| 2013-12-03T20:35:37
|
C++
|
UTF-8
|
Python
| false
| false
| 3,056
|
py
|
overflow.py
|
#!/usr/bin/env python3
import sys
from PIL import Image, ImageDraw
from factor import FactorialNumber, precalculate
def binomial_fraction(n, k):
p = min(k, n - k)
num = 1
denom = 1
for i in range(p):
num *= n - p + (i + 1)
denom *= (i + 1)
return (num, denom)
numbers = list(precalculate())
primes = numbers[0].primes
def avx512_binomial_algorithm(n, k):
p = min(k, n - k)
num = FactorialNumber([], primes)
denom = FactorialNumber([], primes)
for i in range(p):
num_coef = n - p + (i + 1)
denom_coef = i + 1
num += numbers[num_coef]
denom += numbers[denom_coef]
num -= denom
return num
maxint = 2**64 - 1
def scalar_binomial_overflow(n, k):
num, denom = binomial_fraction(n, k)
return num > maxint or denom > maxint
def avx512_binomial_overflow(n, k):
divided = avx512_binomial_algorithm(n, k)
num = 1
denom = 1
for (base, power) in divided:
if power > 0:
num *= base**power
elif power < 0:
denom *= base**power
return num > maxint or denom > maxint
BOTH_VALID = 0
SCALAR_VALID = 1
AVX512_VALID = 2
NONE_VALID = 3
class Parameters:
def __init__(self):
self.cell_size = 3
self.spacing = 2
self.padding = 4
self.background = '#000'
self.colors = {
BOTH_VALID: '#0f0',
NONE_VALID: '#f00',
SCALAR_VALID: '#ff0',
AVX512_VALID: '#fff'
}
def size(self, n):
return self.cell_size * n + \
self.spacing * (n - 1) + \
self.padding * 2
def draw_grid(num_range, params, overflow):
size = params.size(num_range)
img = Image.new('RGB', (size, size))
draw = ImageDraw.Draw(img)
draw.rectangle((0, 0, img.width, img.height), fill=params.background)
for n in range(1, num_range + 1):
y = (n - 1) * (params.cell_size + params.spacing) + params.padding
for k in range(1, num_range + 1):
idx = overflow(n, k)
color = params.colors[idx]
x = (k - 1) * (params.cell_size + params.spacing) + params.padding
draw.rectangle((x, y, x + params.cell_size, y + params.cell_size), fill=color)
return img
def main():
if len(sys.argv) <= 1:
print(f"usage: {sys.argv[0]} output-file")
sys.exit(1)
params = Parameters()
num_range = 128
def overflow(n, k):
scalar_overflow = scalar_binomial_overflow(n, k)
avx512_overflow = avx512_binomial_overflow(n, k)
if scalar_overflow and avx512_overflow:
return NONE_VALID
if not scalar_overflow and not avx512_overflow:
return BOTH_VALID
if scalar_overflow:
assert not avx512_overflow
return AVX512_VALID
else:
assert avx512_overflow
return SCALAR_VALID
img = draw_grid(num_range, params, overflow)
img.save(sys.argv[1])
if __name__ == '__main__':
main()
|
ddb277aced9d788563df315dc80824d0cc002b6f
|
153a746ea3246cdc04ac0413c9793309ca924d08
|
/test/performance-plot.py
|
e491a7e8884e557a62a833e80e559bf2f1212c10
|
[
"MIT"
] |
permissive
|
GothenburgBitFactory/timewarrior
|
bfbc0e9960012ce47c1134ca60ba06077cfa8724
|
a72659f753af283879a5c3bfb71448583a2ba7b7
|
refs/heads/develop
| 2023-09-04T20:55:38.830794
| 2020-03-06T13:52:22
| 2023-08-11T18:50:29
| 120,080,436
| 1,082
| 129
|
MIT
| 2023-09-11T23:20:14
| 2018-02-03T10:15:22
|
C++
|
UTF-8
|
Python
| false
| false
| 1,198
|
py
|
performance-plot.py
|
#!/usr/bin/env python3
import os
import argparse
import matplotlib.pyplot as plt
import numpy as np
parser = argparse.ArgumentParser(description='Display performance plots.')
parser.add_argument('output_dir', help='directory containing the measurement files')
parser.add_argument('commands', nargs='*', type=str)
args = parser.parse_args()
output_directory = args.output_dir
commands = args.commands
plt.axes([0.1, 0.1, 0.6, 0.75])
plt.xlabel("# database entries")
plt.ylabel("time [s]")
plt.title(output_directory)
for filename in os.listdir(output_directory):
if filename.endswith(".log"):
cmd = "-".join(filename.split('-')[1:-1])
else:
continue
if len(commands) == 0 or cmd in commands:
try:
x, y = np.loadtxt(os.path.join(output_directory, filename),
delimiter='\t',
usecols=(1, 2),
unpack=True)
plt.plot(x, y, label=cmd, marker=".", linestyle='-')
except ValueError as e:
print("Invalid file: {} {}".format(filename, e))
plt.legend(bbox_to_anchor=(1.05, 1), loc='upper left', borderaxespad=0., ncol=2)
plt.show()
|
71b90e5ade682390fe348bbb4ec8b49ec3ba2c20
|
fba876caecb7a55254cf92434a9a8a629ed47b93
|
/scripts/migration/set_phase_code_name_unique.py
|
588b06d130a81ec348dc00d62a4d3e6fecb8c94d
|
[
"BSD-3-Clause"
] |
permissive
|
Cloud-CV/EvalAI
|
f6eb96509f679cb5765fd4b4a49e5b3f5a5551d6
|
7e3485f2f3c77b146b72cbbc8de1b15bf0dfe0db
|
refs/heads/master
| 2023-09-04T05:03:59.087293
| 2023-08-30T19:26:13
| 2023-08-30T19:26:13
| 71,516,397
| 1,722
| 983
|
NOASSERTION
| 2023-09-07T18:02:48
| 2016-10-21T00:51:45
|
Python
|
UTF-8
|
Python
| false
| false
| 821
|
py
|
set_phase_code_name_unique.py
|
# Command to run: python manage.py shell < scripts/migration/set_phase_code_name_unique.py
from challenges.models import ChallengePhase
def set_phase_code_name_unique():
challenge_phases = ChallengePhase.objects.all()
try:
for challenge_phase in challenge_phases:
new_phase_code_name = "{0}_{1}".format(
challenge_phase.code_name, challenge_phase.id
)
print(
"Modifying Challenge Phase Code Name: `%s` --> `%s` "
% (challenge_phase.code_name, new_phase_code_name)
)
challenge_phase.code_name = new_phase_code_name
challenge_phase.save()
print("Successfully modified Challenge Phase Code Name")
except Exception as e:
print(e)
set_phase_code_name_unique()
|
754836f03126734f05f0fef6a67bbf9d0cfea963
|
83da171ef6c1f8201a88534737c9e753247afee1
|
/tests/conftest.py
|
183f948dcb5cde5f0e7f4a2f434db1e0d8b96171
|
[
"BSD-3-Clause"
] |
permissive
|
OasisLMF/OasisLMF
|
7bb691eb08f11641887257fe154d5356509707c5
|
23e704c335629ccd010969b1090446cfa3f384d5
|
refs/heads/main
| 2023-08-25T12:14:44.449756
| 2023-08-23T10:08:17
| 2023-08-23T10:08:17
| 117,560,568
| 122
| 53
|
BSD-3-Clause
| 2023-09-14T09:37:17
| 2018-01-15T15:12:25
|
Python
|
UTF-8
|
Python
| false
| false
| 1,007
|
py
|
conftest.py
|
"""pytest configuration"""
def pytest_addoption(parser):
parser.addoption(
'--gul-rtol', type=float, default=1e-10,
help='Relative tolerance between expected values and results, default is "1e-10"'
)
parser.addoption(
'--gul-atol', type=float, default=1e-8,
help='Absolute tolerance between expected values and results, default is "1e-8"'
)
parser.addoption(
'--gulmc-generate-missing-expected', action='store_true', default=False,
help='If True, generate the expected files for the tests that lack them (e.g., newly added tests). Default: False.'
)
parser.addoption(
'--update-expected', action='store_true', default=False,
help='If True, update all the expected files, overwriting them if they exist. Default: False.'
)
parser.addoption(
'--fm-keep-output', action='store_true', default=False,
help='If True, keep the test results (useful for debugging purposes). Default: False.'
)
|
9c4f1ed2ec51bebd035df855d21718933f719747
|
1d88dfbd224ba0cdfaf4834dc4202410cba3db16
|
/examples/python/geometry/kd_tree_feature_matching.py
|
89f21f20245b46677319dbb37016030d516a094e
|
[
"MIT"
] |
permissive
|
isl-org/Open3D
|
5217d525f505839777078127b5da7adc7b4bba2f
|
b620539a445206a7e07fed33fb4dcc6dff06c1a5
|
refs/heads/master
| 2023-09-01T21:42:37.981501
| 2023-09-01T15:08:08
| 2023-09-01T15:08:08
| 75,413,130
| 4,535
| 908
|
NOASSERTION
| 2023-09-14T18:07:41
| 2016-12-02T16:40:38
|
C++
|
UTF-8
|
Python
| false
| false
| 2,136
|
py
|
kd_tree_feature_matching.py
|
# ----------------------------------------------------------------------------
# - Open3D: www.open3d.org -
# ----------------------------------------------------------------------------
# Copyright (c) 2018-2023 www.open3d.org
# SPDX-License-Identifier: MIT
# ----------------------------------------------------------------------------
import numpy as np
import open3d as o3d
if __name__ == "__main__":
print("Load two aligned point clouds.")
demo_data = o3d.data.DemoFeatureMatchingPointClouds()
pcd0 = o3d.io.read_point_cloud(demo_data.point_cloud_paths[0])
pcd1 = o3d.io.read_point_cloud(demo_data.point_cloud_paths[1])
pcd0.paint_uniform_color([1, 0.706, 0])
pcd1.paint_uniform_color([0, 0.651, 0.929])
o3d.visualization.draw_geometries([pcd0, pcd1])
print("Load their FPFH feature and evaluate.")
print("Black : matching distance > 0.2")
print("White : matching distance = 0")
feature0 = o3d.io.read_feature(demo_data.fpfh_feature_paths[0])
feature1 = o3d.io.read_feature(demo_data.fpfh_feature_paths[1])
fpfh_tree = o3d.geometry.KDTreeFlann(feature1)
for i in range(len(pcd0.points)):
[_, idx, _] = fpfh_tree.search_knn_vector_xd(feature0.data[:, i], 1)
dis = np.linalg.norm(pcd0.points[i] - pcd1.points[idx[0]])
c = (0.2 - np.fmin(dis, 0.2)) / 0.2
pcd0.colors[i] = [c, c, c]
o3d.visualization.draw_geometries([pcd0])
print("")
print("Load their L32D feature and evaluate.")
print("Black : matching distance > 0.2")
print("White : matching distance = 0")
feature0 = o3d.io.read_feature(demo_data.l32d_feature_paths[0])
feature1 = o3d.io.read_feature(demo_data.l32d_feature_paths[1])
fpfh_tree = o3d.geometry.KDTreeFlann(feature1)
for i in range(len(pcd0.points)):
[_, idx, _] = fpfh_tree.search_knn_vector_xd(feature0.data[:, i], 1)
dis = np.linalg.norm(pcd0.points[i] - pcd1.points[idx[0]])
c = (0.2 - np.fmin(dis, 0.2)) / 0.2
pcd0.colors[i] = [c, c, c]
o3d.visualization.draw_geometries([pcd0])
print("")
|
a8bd90724a7b1694832eea08f2b0ca104c6457c5
|
398caeba60b0f7fe6df0aae549daef4ac4f713d1
|
/tests/functional/test_inference.py
|
cf5979b370ca9cac6f0df670fccc821db6c0b055
|
[
"BSD-3-Clause"
] |
permissive
|
elfi-dev/elfi
|
008fcb51cc9d39713d42ba56f5768a2dd5ffbe46
|
aca8ba31cd054d00a5ff4e6e4c2425d6360b8ce2
|
refs/heads/dev
| 2023-03-10T02:45:05.039697
| 2023-03-07T19:00:26
| 2023-03-07T19:00:26
| 69,855,441
| 190
| 60
|
BSD-3-Clause
| 2023-09-11T19:12:08
| 2016-10-03T09:03:38
|
Python
|
UTF-8
|
Python
| false
| false
| 11,802
|
py
|
test_inference.py
|
"""Test inference methods point estimates with informative data from the MA2 process."""
from collections import OrderedDict
import numpy as np
import pytest
import elfi
from elfi.examples import ma2
from elfi.methods.bo.utils import minimize, stochastic_optimization
from elfi.methods.bsl.pre_sample_methods import estimate_whitening_matrix, select_penalty
from elfi.methods.bsl.pdf_methods import standard_likelihood, unbiased_likelihood, semiparametric_likelihood, robust_likelihood
from elfi.model.elfi_model import NodeReference
def setup_ma2_with_informative_data(n_obs=100):
true_params = OrderedDict([('t1', .6), ('t2', .2)])
# In our implementation, seed 4 gives informative (enough) synthetic observed
# data of length 100 for quite accurate inference of the true parameters using
# posterior mean as the point estimate
m = ma2.get_model(n_obs=n_obs, true_params=true_params.values(), seed_obs=4)
return m, true_params
def check_inference_with_informative_data(outputs, N, true_params, error_bound=0.05):
t1 = outputs['t1']
t2 = outputs['t2']
if N > 1:
assert len(t1) == N
assert np.abs(np.mean(t1) - true_params['t1']) < error_bound, \
"\n\nNot |{} - {}| < {}\n".format(np.mean(t1), true_params['t1'], error_bound)
assert np.abs(np.mean(t2) - true_params['t2']) < error_bound, \
"\n\nNot |{} - {}| < {}\n".format(np.mean(t2), true_params['t2'], error_bound)
@pytest.mark.usefixtures('with_all_clients')
def test_rejection_with_quantile():
m, true_params = setup_ma2_with_informative_data()
quantile = 0.01
N = 1000
batch_size = 20000
rej = elfi.Rejection(m['d'], batch_size=batch_size)
res = rej.sample(N, quantile=quantile)
check_inference_with_informative_data(res.samples, N, true_params)
# Check that there are no repeating values indicating a seeding problem
assert len(np.unique(res.discrepancies)) == N
assert res.accept_rate == quantile
assert res.n_sim == int(N / quantile)
@pytest.mark.usefixtures('with_all_clients')
def test_rejection_with_threshold():
m, true_params = setup_ma2_with_informative_data()
t = .1
N = 1000
rej = elfi.Rejection(m['d'], batch_size=20000)
res = rej.sample(N, threshold=t)
check_inference_with_informative_data(res.samples, N, true_params)
assert res.threshold <= t
# Test that we got unique samples (no repeating of batches).
assert len(np.unique(res.discrepancies)) == N
@pytest.mark.usefixtures('with_all_clients')
def test_smc_with_thresholds():
m, true_params = setup_ma2_with_informative_data()
thresholds = [.5, .25, .1]
N = 1000
smc = elfi.SMC(m['d'], batch_size=20000)
res = smc.sample(N, thresholds=thresholds)
check_inference_with_informative_data(res.samples, N, true_params)
# We should be able to carry out the inference in less than six batches
assert res.populations[-1].n_batches < 6
@pytest.mark.usefixtures('with_all_clients')
def test_smc_with_quantiles():
m, true_params = setup_ma2_with_informative_data()
quantiles = [.5, .5, .5]
N = 1000
smc = elfi.SMC(m['d'], batch_size=20000)
res = smc.sample(N, quantiles=quantiles)
check_inference_with_informative_data(res.samples, N, true_params)
@pytest.mark.usefixtures('with_all_clients')
def test_adaptivethresholdsmc():
m, true_params = setup_ma2_with_informative_data()
N = 1000
adathsmc = elfi.AdaptiveThresholdSMC(m['d'], batch_size=500)
res = adathsmc.sample(N, max_iter=4)
check_inference_with_informative_data(res.samples, N, true_params)
# We should be able to carry out the inference in less than six batches
# assert res.populations[-1].n_batches < 6
assert len(res.populations) == 4
@pytest.mark.usefixtures('with_all_clients')
def test_adaptive_distance_smc():
m, true_params = setup_ma2_with_informative_data()
# use adaptive distance:
m['d'].become(elfi.AdaptiveDistance(m['S1'], m['S2']))
N = 1000
rounds = 3
ad_smc = elfi.AdaptiveDistanceSMC(m['d'], batch_size=20000)
ad_res = ad_smc.sample(N, rounds)
check_inference_with_informative_data(ad_res.samples, N, true_params)
assert len(ad_res.populations) == rounds
# We should be able to carry out the inference in less than six batches
assert ad_res.populations[-1].n_batches < 6
@pytest.mark.slowtest
@pytest.mark.usefixtures('with_all_clients', 'skip_travis')
def test_BOLFI():
m, true_params = setup_ma2_with_informative_data()
# Log discrepancy tends to work better
log_d = NodeReference(m['d'], state=dict(_operation=np.log), model=m, name='log_d')
bolfi = elfi.BOLFI(
log_d,
initial_evidence=20,
update_interval=10,
batch_size=5,
bounds={'t1': (-2, 2),
't2': (-1, 1)},
acq_noise_var=.1)
n = 300
res = bolfi.infer(300)
assert bolfi.target_model.n_evidence == 300
acq_x = bolfi.target_model._gp.X
# check_inference_with_informative_data(res, 1, true_params, error_bound=.2)
assert np.abs(res.x_min['t1'] - true_params['t1']) < 0.2
assert np.abs(res.x_min['t2'] - true_params['t2']) < 0.2
# Test that you can continue the inference where we left off
res = bolfi.infer(n + 10)
assert bolfi.target_model.n_evidence == n + 10
assert np.array_equal(bolfi.target_model._gp.X[:n, :], acq_x)
post = bolfi.extract_posterior()
# TODO: make cleaner.
post_ml = minimize(
post._neg_unnormalized_loglikelihood,
post.model.bounds,
grad=post._gradient_neg_unnormalized_loglikelihood,
prior=post.prior,
n_start_points=post.n_inits,
maxiter=post.max_opt_iters,
random_state=post.random_state)[0]
# TODO: Here we cannot use the minimize method due to sharp edges in the posterior.
# If a MAP method is implemented, one must be able to set the optimizer and
# provide its options.
post_map = stochastic_optimization(post._neg_unnormalized_logposterior, post.model.bounds)[0]
vals_ml = dict(t1=np.array([post_ml[0]]), t2=np.array([post_ml[1]]))
check_inference_with_informative_data(vals_ml, 1, true_params, error_bound=.2)
vals_map = dict(t1=np.array([post_map[0]]), t2=np.array([post_map[1]]))
check_inference_with_informative_data(vals_map, 1, true_params, error_bound=.2)
n_samples = 400
n_chains = 4
res_sampling = bolfi.sample(n_samples, n_chains=n_chains)
check_inference_with_informative_data(
res_sampling.samples, n_samples // 2 * n_chains, true_params, error_bound=.2)
# check the cached predictions for RBF
x = np.random.random((1, len(true_params)))
bolfi.target_model.is_sampling = True
pred_mu, pred_var = bolfi.target_model._gp.predict(x)
pred_cached_mu, pred_cached_var = bolfi.target_model.predict(x)
assert (np.allclose(pred_mu, pred_cached_mu))
assert (np.allclose(pred_var, pred_cached_var))
grad_mu, grad_var = bolfi.target_model._gp.predictive_gradients(x)
grad_cached_mu, grad_cached_var = bolfi.target_model.predictive_gradients(x)
assert (np.allclose(grad_mu[:, :, 0], grad_cached_mu))
assert (np.allclose(grad_var, grad_cached_var))
# test calculation of prior logpdfs
true_logpdf_prior = ma2.CustomPrior1.logpdf(x[0, 0], 2)
true_logpdf_prior += ma2.CustomPrior2.logpdf(x[0, 1], x[0, 0, ], 1)
assert np.isclose(true_logpdf_prior, post.prior.logpdf(x[0, :]))
@pytest.mark.slowtest
def test_romc():
"""Test that ROMC provides sensible samples at the MA2 example."""
model, true_params = setup_ma2_with_informative_data()
# define romc inference method
bounds = [(-2, 2), (-2, 2)]
romc = elfi.ROMC(model, bounds=bounds, discrepancy_name="d")
# solve problems
n1 = 100
seed = 21
romc.solve_problems(n1=n1, seed=seed)
# estimate regions
eps_filter = .02
romc.estimate_regions(eps_filter=eps_filter, fit_models=True, eps_cutoff=0.1)
# sample from posterior
n2 = 50
romc.sample(n2=n2)
romc_mean = romc.result.sample_means_array
romc_cov = romc.result.samples_cov()
# Inference with Rejection
N = 10000
rej = elfi.Rejection(model, discrepancy_name="d", batch_size=10000, seed=seed)
result = rej.sample(N, threshold=.1)
rejection_mean = result.sample_means_array
rejection_cov = np.cov(result.samples_array.T)
# assert summary statistics of samples match the ground truth
assert np.allclose(romc_mean, rejection_mean, atol=.1)
assert np.allclose(romc_cov, rejection_cov, atol=.1)
def check_bsl(likelihood, n_sim, error_bound=.15):
n_obs = 50
m, true_params = setup_ma2_with_informative_data(n_obs=n_obs)
mcmc_iters = 2000
est_posterior_cov = np.array([[0.02, 0.01],
[0.01, 0.02]])
feature_names = ['MA2']
bsl = elfi.BSL(m, n_sim, feature_names, likelihood=likelihood, seed=123)
bsl_res = bsl.sample(mcmc_iters, sigma_proposals=est_posterior_cov,
params0=np.array([0.6, 0.2]))
check_inference_with_informative_data(bsl_res.samples, mcmc_iters,
true_params, error_bound)
def check_rbsl(likelihood, n_sim, error_bound=.15):
n_obs = 100 # as rbsl uses autocov
m, true_params = setup_ma2_with_informative_data(n_obs=n_obs)
mcmc_iters = 2000
est_posterior_cov = np.array([[0.02, 0.01],
[0.01, 0.02]])
feature_names = ['S1', 'S2']
rbsl = elfi.BSL(m, n_sim, feature_names, likelihood=likelihood, seed=123)
rbsl_res = rbsl.sample(mcmc_iters, sigma_proposals=est_posterior_cov,
params0=np.array([0.6, 0.2]))
check_inference_with_informative_data(rbsl_res.samples, mcmc_iters,
true_params, error_bound)
def test_sbsl():
"""Test standard BSL provides sensible samples at the MA2 example."""
likelihood = standard_likelihood()
check_bsl(likelihood, 500)
def test_ubsl():
"""Test unbiased BSL provides sensible samples at the MA2 example."""
likelihood = unbiased_likelihood()
check_bsl(likelihood, 500)
@pytest.mark.slowtest
def test_semibsl():
"""Test semiBSL provides sensible samples at the MA2 example."""
likelihood = semiparametric_likelihood()
check_bsl(likelihood, 500)
@pytest.mark.slowtest
def test_rbslm():
"""Test R-BSL-M provides sensible samples at the MA2 example."""
likelihood = robust_likelihood("mean")
check_rbsl(likelihood, 12)
@pytest.mark.slowtest
def test_rbslv():
"""Test R-BSL-V provides sensible samples at the MA2 example."""
likelihood = robust_likelihood("variance")
check_rbsl(likelihood, 10)
def test_wbsl():
"""Test wBSL provides sensible samples at the MA2 example."""
tmp_m, _ = setup_ma2_with_informative_data(n_obs=50)
true_params = np.array([0.6, 0.2])
feature_names = ['MA2']
W = estimate_whitening_matrix(tmp_m, 5000, true_params, feature_names, seed=1)
n_sim = 100
shrinkage = "warton"
penalty, std_value = select_penalty(model=tmp_m,
n_sim=n_sim,
theta=true_params,
feature_names=feature_names,
M=10,
shrinkage=shrinkage,
whitening=W,
sigma=1.5,
seed=1
)
likelihood = standard_likelihood(whitening=W, penalty=penalty, shrinkage=shrinkage)
check_bsl(likelihood, n_sim)
|
27050255e99f9f31c2093dd670aad67fb89d559b
|
686177a1034cee76ad040c62e3d3e49d44a9ee7a
|
/src/collectors/jcollectd/test/testjcollectd.py
|
5a810af7038c22bccc0b8c6cdc13d33c0ebaff38
|
[
"MIT"
] |
permissive
|
python-diamond/Diamond
|
8fce83a3d883dfa05b664fdd5cb6064f34c4ac41
|
461caf29e84db8cbf46f9fc4c895f56353e10c61
|
refs/heads/master
| 2023-07-20T01:44:18.504408
| 2023-01-29T19:46:36
| 2023-01-29T19:46:36
| 13,512,018
| 1,874
| 824
|
MIT
| 2023-07-10T11:06:38
| 2013-10-11T23:32:13
|
Python
|
UTF-8
|
Python
| false
| false
| 1,155
|
py
|
testjcollectd.py
|
#!/usr/bin/python
# coding=utf-8
###############################################################################
from test import CollectorTestCase
from test import get_collector_config
from test import unittest
from jcollectd import JCollectdCollector, sanitize_word
###############################################################################
class TestJCollectdCollector(CollectorTestCase):
def setUp(self):
config = get_collector_config('JCollectdCollector', {
})
self.collector = JCollectdCollector(config, None)
def test_import(self):
self.assertTrue(JCollectdCollector)
def test_sanitize(self):
self.assertEqual(sanitize_word('bla'), 'bla')
self.assertEqual(sanitize_word('bla:'), 'bla')
self.assertEqual(sanitize_word('foo:bar'), 'foo_bar')
self.assertEqual(sanitize_word('foo:!bar'), 'foo_bar')
self.assertEqual(sanitize_word('"ou812"'), 'ou812')
self.assertEqual(sanitize_word('Aap! N@@t mi_es'), 'Aap_N_t_mi_es')
###############################################################################
if __name__ == "__main__":
unittest.main()
|
7a2a59769fdeb98f810fd76db185e9038c4aa044
|
c46754b9600a12df4f9d7a6320dfc19aa96b1e1d
|
/examples/research_projects/onnx/summarization/bart_onnx/generation_onnx.py
|
5c1b0da700024bf8b184313b6fe7f3aa3d17f5bb
|
[
"Apache-2.0"
] |
permissive
|
huggingface/transformers
|
ccd52a0d7c59e5f13205f32fd96f55743ebc8814
|
4fa0aff21ee083d0197a898cdf17ff476fae2ac3
|
refs/heads/main
| 2023-09-05T19:47:38.981127
| 2023-09-05T19:21:33
| 2023-09-05T19:21:33
| 155,220,641
| 102,193
| 22,284
|
Apache-2.0
| 2023-09-14T20:44:49
| 2018-10-29T13:56:00
|
Python
|
UTF-8
|
Python
| false
| false
| 30,826
|
py
|
generation_onnx.py
|
import copy
import itertools
from typing import List, Optional, Tuple
import torch
import torch.nn.functional as F
from transformers import BartConfig
from transformers.generation import GenerationMixin
def _convert_past_list_to_tuple(past_key_values):
"""
In Bart model, the type of past_key_values is tuple(tuple(torch.FloatTensor)) which is not
TorchScript-compatible. To support this, we have to convert it during the export process.
This function will convert past values from a list to tuple(tuple(torch.FloatTensor)) for
the inner decoder.
According to the definition of past_key_values, each inner tuple(torch.FloatTensor) has 4 tensors,
so we convert every 4 elements in the list as a tuple(torch.FloatTensor).
"""
count_of_each_inner_tuple = 4
results = ()
temp_result = ()
count_n = len(past_key_values) // count_of_each_inner_tuple
for idx in range(count_n):
real_idx = idx * count_of_each_inner_tuple
temp_result = tuple(past_key_values[real_idx : real_idx + count_of_each_inner_tuple])
results += ((temp_result),)
return results
class EncoderForONNX(torch.nn.Module):
def __init__(self, encoder):
super().__init__()
self.encoder = encoder
def forward(self, input_ids, attention_mask):
return self.encoder(
input_ids=input_ids,
attention_mask=attention_mask,
return_dict=False,
)
class DecoderForONNX(torch.nn.Module):
def __init__(self, decoder):
super().__init__()
self.decoder = decoder
def forward(self, input_ids, encoder_state, attention_mask, past=None):
all_results = None
if past is not None:
all_results = _convert_past_list_to_tuple(past)
input_ids = input_ids[:, -1:]
last_hidden_state, past_key_values = self.decoder(
input_ids=input_ids,
encoder_hidden_states=encoder_state,
encoder_attention_mask=attention_mask,
past_key_values=all_results,
return_dict=False,
)
past_values = []
for past in past_key_values:
past_values = past_values + list(past)
return last_hidden_state, past_values
def _create_traced_encoder(encoder, input_ids, attention_mask):
encoder_c = copy.deepcopy(encoder)
encoder_for_onnx = EncoderForONNX(encoder_c)
return torch.jit.trace(encoder_for_onnx, (input_ids, attention_mask))
def _create_traced_decoder(decoder, input_ids, encoder_state, attention_mask, past=None):
decoder_c = copy.deepcopy(decoder)
decoder_for_onnx = DecoderForONNX(decoder_c)
past_values = list(itertools.chain.from_iterable(past or ()))
# Do this twice so we got 2 different decoders for further work.
if past_values:
return torch.jit.trace(decoder_for_onnx, (input_ids, encoder_state, attention_mask, past_values))
else:
return torch.jit.trace(decoder_for_onnx, (input_ids, encoder_state, attention_mask))
class BartConfigTS(BartConfig, torch.nn.Module):
"""
BartConfigTS is a TorchScript-compatible transformers.models.bart.configuration_bart.BartConfig.
TorchScript only supports sub-classes of torch.nn.Module.
"""
def __init__(self, config):
BartConfig.__init__(self, config)
torch.nn.Module.__init__(self)
class MinLengthLogitsProcessorTS(torch.nn.Module):
r"""
:class:`transformers.LogitsProcessor` enforcing a min-length by setting EOS probability to 0.
Args:
min_length (:obj:`int`):
The minimum length below which the score of :obj:`eos_token_id` is set to :obj:`-float("Inf")`.
eos_token_id (:obj:`int`):
The id of the `end-of-sequence` token.
"""
def __init__(self, min_length: int, eos_token_id: int):
super().__init__()
if not isinstance(min_length, int) or min_length < 0:
raise ValueError(f"`min_length` has to be a positive integer, but is {min_length}")
if not isinstance(eos_token_id, int) or eos_token_id < 0:
raise ValueError(f"`eos_token_id` has to be a positive integer, but is {eos_token_id}")
self.min_length = min_length
self.eos_token_id = eos_token_id
def forward(self, input_ids, scores) -> torch.Tensor:
cur_len = input_ids.shape[-1]
if cur_len < self.min_length:
scores[:, self.eos_token_id] = -float("inf")
return scores
class BARTGenerator(torch.nn.Module, GenerationMixin):
def __init__(self, model):
super().__init__()
self.config = BartConfigTS(model.config)
self.config.force_bos_token_to_be_generated = False
self._trace_modules(model)
self.logits_processor = MinLengthLogitsProcessorTS(self.config.min_length, self.config.eos_token_id)
self.final_logits_weight = model.model.shared.weight
self.final_logits_bias = model.final_logits_bias
self.decoder_layers = model.config.decoder_layers
def _trace_modules(self, model):
input_ids = torch.tensor(
[
[
19,
669,
18,
420,
8,
664,
57,
42,
8,
664,
21,
3028,
195,
4445,
331,
1293,
34,
21,
10,
6174,
1100,
6,
69,
104,
42,
32,
2621,
1638,
144,
4,
6174,
558,
108,
4419,
1091,
28,
4,
1668,
9,
1509,
1621,
279,
35,
867,
2734,
85,
11,
2216,
2734,
85,
203,
2244,
7,
6,
15,
8102,
7,
57,
8629,
5,
model.config.eos_token_id,
]
],
device=model.device,
dtype=torch.long,
)
attention_mask = torch.tensor(
[[True] * input_ids.shape[-1]],
device=model.device,
dtype=torch.bool,
)
self.encoder = _create_traced_encoder(model.get_encoder(), input_ids, attention_mask)
encoder_outputs = model.get_encoder()(input_ids, attention_mask=attention_mask, return_dict=True)
decoder = model.model.decoder
decoder_outputs = decoder(input_ids, attention_mask, encoder_outputs["last_hidden_state"], None, None, None)
self.decoder_no_past = _create_traced_decoder(
model.model.decoder, input_ids, encoder_outputs["last_hidden_state"], attention_mask
)
self.decoder_with_past = _create_traced_decoder(
model.model.decoder, input_ids, encoder_outputs["last_hidden_state"], attention_mask, decoder_outputs[1]
)
def _encoder_forward(self, input_ids, attention_mask):
return self.encoder(input_ids, attention_mask)[0]
@staticmethod
def _init_sequence_length_for_generation(
input_ids: torch.LongTensor, max_length: int
) -> Tuple[torch.Tensor, torch.Tensor, int]:
unfinished_sequences = torch.zeros(input_ids.shape[0], dtype=torch.long, device=input_ids.device) + 1
sequence_lengths = torch.zeros(input_ids.shape[0], dtype=torch.long, device=input_ids.device) + max_length
cur_len = input_ids.shape[-1]
return sequence_lengths, unfinished_sequences, cur_len
def _decoder_forward(self, input_ids, encoder_output, attention_mask, past: List[torch.Tensor]):
# Update here to use different decoder for different values of past.
if past is None or len(past) == 0:
decoder_output, past = self.decoder_no_past(
input_ids=input_ids, encoder_state=encoder_output, attention_mask=attention_mask
)
else:
decoder_output, past = self.decoder_with_past(
input_ids=input_ids, encoder_state=encoder_output, attention_mask=attention_mask, past=past
)
lm_logits = F.linear(decoder_output, self.final_logits_weight, bias=self.final_logits_bias)
return lm_logits, past
def greedy_search(
self, input_ids, encoder_output, attention_mask, max_length, pad_token_id: int, eos_token_id: int
):
# init sequence length tensors
sequence_lengths, unfinished_sequences, cur_len = self._init_sequence_length_for_generation(
input_ids, max_length
)
past: List[torch.Tensor] = []
while cur_len < max_length:
logits, past = self._decoder_forward(input_ids, encoder_output, attention_mask, past)
next_token_logits = logits[:, -1, :]
# pre-process distribution
scores = self.logits_processor(input_ids, next_token_logits)
# argmax
next_tokens = torch.argmax(scores, dim=-1)
# add code that transfomers next_tokens to tokens_to_add
if eos_token_id is not None:
assert pad_token_id is not None, "If eos_token_id is defined, make sure that pad_token_id is defined."
next_tokens = next_tokens * unfinished_sequences + (pad_token_id) * (1 - unfinished_sequences)
# add token and increase length by one
input_ids = torch.cat([input_ids, next_tokens[:, None]], dim=-1)
# update sequence length
if eos_token_id is not None:
sequence_lengths, unfinished_sequences = self._update_seq_length_for_generation(
sequence_lengths, unfinished_sequences, cur_len, next_tokens == eos_token_id
)
# stop when there is a </s> in each sentence, or if we exceed the maximul length
if unfinished_sequences.max() == 0:
break
# increase cur_len
cur_len = cur_len + 1
return input_ids
def _prepare_decoder_input_ids_for_generation(
self,
input_ids: torch.LongTensor,
decoder_start_token_id,
bos_token_id: Optional[int] = None,
) -> torch.LongTensor:
decoder_input_ids = (
torch.ones((input_ids.shape[0], 1), dtype=input_ids.dtype, device=input_ids.device)
* decoder_start_token_id
)
return decoder_input_ids
def forward(self, input_ids, attention_mask, max_length, decoder_start_token_id):
pad_token_id = self.config.pad_token_id
bos_token_id = self.config.bos_token_id
eos_token_id = self.config.eos_token_id
# special case if pad_token_id is not defined
if pad_token_id is None and eos_token_id is not None:
# Setting `pad_token_id` to `eos_token_id`:{eos_token_id} for open-end generation.
pad_token_id = eos_token_id
encoder_output = self._encoder_forward(input_ids, attention_mask)
input_ids = self._prepare_decoder_input_ids_for_generation(
input_ids,
decoder_start_token_id=decoder_start_token_id,
bos_token_id=bos_token_id,
)
return self.greedy_search(
input_ids,
encoder_output,
attention_mask,
max_length=max_length,
pad_token_id=pad_token_id,
eos_token_id=eos_token_id,
)
# TorchScript compatible BeamSearchScorer
class BeamSearchScorerTS(torch.nn.Module):
def __init__(self):
super().__init__()
self.max_length: int = 200
self.num_beams: int = 3
self.batch_size: int = 1
self.length_penalty: float = 1.0
self.do_early_stopping: bool = True
self.num_beam_hyps_to_keep: int = 1
self.num_beam_groups: int = 1
self.group_size: int = self.num_beams // self.num_beam_groups
self._done = torch.zeros(self.batch_size, dtype=torch.bool)
self._beam_hyps_count = torch.zeros(self.batch_size, dtype=torch.long)
self._beam_hyps_worst_scores = torch.zeros(self.batch_size) + 1e9
self._beam_hyps_max_length: int = self.max_length - 1
self._beam_hyps: List[torch.Tensor] = [torch.zeros(2)] # placeholder for TorchScript compatibility
self._beam_scores: List[torch.Tensor] = [torch.zeros(2)] # placeholder for TorchScript compatibility
def is_done(self) -> torch.Tensor:
return self._done.all()
def init(
self,
batch_size: int,
max_length: int,
num_beams: int,
device: torch.device,
length_penalty: float = 1.0,
do_early_stopping: bool = False,
num_beam_hyps_to_keep: int = 1,
num_beam_groups: int = 1,
):
self.max_length = max_length
self.num_beams = num_beams
self.batch_size = batch_size
self.length_penalty = length_penalty
self.do_early_stopping = do_early_stopping
self.num_beam_hyps_to_keep = num_beam_hyps_to_keep
self.num_beam_groups = num_beam_groups
self.group_size = self.num_beams // self.num_beam_groups
# NOTE: TorchScript does not support List of Modules
# Rewritten BeamHypotheses with tensors and list of tensors.
self._done = torch.zeros(batch_size, dtype=torch.bool, device=device)
self._beam_hyps_count = torch.zeros(batch_size, dtype=torch.long, device=device)
self._beam_hyps_worst_scores = torch.zeros(batch_size, device=device) + 1e9
self._beam_hyps = []
self._beam_scores = []
self._beam_hyps_max_length = max_length - 1 # ignoring bos_token
if not isinstance(num_beams, int) or num_beams <= 1:
raise ValueError(
f"`num_beams` has to be an integer strictly greater than 1, but is {num_beams}. For `num_beams` == 1,"
" one should make use of `greedy_search` instead."
)
if not isinstance(num_beam_groups, int) or (num_beam_groups > num_beams) or (num_beams % num_beam_groups != 0):
raise ValueError(
"`num_beam_groups` has to be an integer smaller or equal than `num_beams` and `num_beams` has to be"
f" divisible by `num_beam_groups`, but is {num_beam_groups} with `num_beams` being {num_beams}."
)
def hypo_len(self, hypo_idx: int):
"""
Number of hypotheses in the list.
"""
return self._beam_hyps_count[hypo_idx]
def hypo_add(self, hyp: torch.Tensor, sum_logprobs: float, hypo_idx: int):
"""
Add a new hypothesis to the list.
"""
score = sum_logprobs / (hyp.shape[-1] ** self.length_penalty)
hyps_count = self.hypo_len(hypo_idx)
if hyps_count < self.num_beams or score > self._beam_hyps_worst_scores[hypo_idx]:
# NOTE: work around difference of torch.sum(empty_tensor) == 0, while error in onnx.
# Bug: https://msdata.visualstudio.com/Vienna/_workitems/edit/1486599
beam_idx = (
torch.sum(self._beam_hyps_count[:hypo_idx]) if hypo_idx != 0 else torch.tensor(0, dtype=torch.long)
)
self._beam_scores.insert(beam_idx, torch.tensor([score]))
self._beam_hyps.insert(beam_idx, hyp)
if hyps_count + 1 > self.num_beams:
sorted_next_scores, sorted_indices = torch.topk(
torch.cat(self._beam_scores)[beam_idx : beam_idx + hyps_count + 1], hyps_count + 1, largest=False
)
del self._beam_hyps[int((sorted_indices[0] + beam_idx))]
del self._beam_scores[int((sorted_indices[0] + beam_idx))]
self._beam_hyps_worst_scores[hypo_idx] = sorted_next_scores[1]
else:
self._beam_hyps_worst_scores[hypo_idx] = min(score, self._beam_hyps_worst_scores[hypo_idx])
self._beam_hyps_count[hypo_idx] = hyps_count + 1
def hypo_is_done(self, hypo_idx: int, best_sum_logprobs: float, cur_len: int) -> bool:
"""
If there are enough hypotheses and that none of the hypotheses being generated can become better than the worst
one in the heap, then we are done with this sentence.
"""
if self.hypo_len(hypo_idx) < self.num_beams:
return False
elif self.do_early_stopping:
return True
else:
cur_score = best_sum_logprobs / cur_len**self.length_penalty
ret = self._beam_hyps_worst_scores[hypo_idx].item() >= cur_score
return ret
def process(
self,
input_ids: torch.Tensor,
next_scores: torch.Tensor,
next_tokens: torch.Tensor,
next_indices: torch.Tensor,
pad_token_id: Optional[int] = None,
eos_token_id: Optional[int] = None,
) -> Tuple[torch.Tensor, torch.Tensor, torch.Tensor]:
cur_len = input_ids.shape[-1]
batch_size = len(self._beam_hyps_count)
assert batch_size == (input_ids.shape[0] // self.group_size)
device = input_ids.device
next_beam_scores = torch.zeros((batch_size, self.group_size), dtype=next_scores.dtype, device=device)
next_beam_tokens = torch.zeros((batch_size, self.group_size), dtype=next_tokens.dtype, device=device)
next_beam_indices = torch.zeros((batch_size, self.group_size), dtype=next_indices.dtype, device=device)
for batch_idx in range(batch_size):
if self._done[batch_idx]:
assert (
self.hypo_len(batch_idx) >= self.num_beams
), "Batch can only be done if at least {} beams have been generated".format(self.num_beams)
assert (
eos_token_id is not None and pad_token_id is not None
), "generated beams >= num_beams -> eos_token_id and pad_token have to be defined"
# pad the batch
next_beam_scores[batch_idx, :] = 0
next_beam_tokens[batch_idx, :] = pad_token_id
next_beam_indices[batch_idx, :] = 0
continue
# next tokens for this sentence
beam_idx = 0
for beam_token_rank, (next_token, next_score, next_index) in enumerate(
zip(next_tokens[batch_idx], next_scores[batch_idx], next_indices[batch_idx])
):
batch_beam_idx = batch_idx * self.group_size + next_index
# add to generated hypotheses if end of sentence
if (eos_token_id is not None) and (next_token == eos_token_id):
# if beam_token does not belong to top num_beams tokens, it should not be added
is_beam_token_worse_than_top_num_beams = beam_token_rank >= self.group_size
if is_beam_token_worse_than_top_num_beams:
continue
self.hypo_add(
input_ids[batch_beam_idx].clone(),
next_score.item(),
batch_idx,
)
else:
# add next predicted token since it is not eos_token
next_beam_scores[batch_idx, beam_idx] = next_score
next_beam_tokens[batch_idx, beam_idx] = next_token
next_beam_indices[batch_idx, beam_idx] = batch_beam_idx
beam_idx += 1
# once the beam for next step is full, don't add more tokens to it.
if beam_idx == self.group_size:
break
if beam_idx < self.group_size:
raise ValueError(
f"At most {self.group_size} tokens in {next_tokens[batch_idx]} can be equal to `eos_token_id:"
f" {eos_token_id}`. Make sure {next_tokens[batch_idx]} are corrected."
)
# Check if we are done so that we can save a pad step if all(done)
self._done[batch_idx] = self._done[batch_idx] or self.hypo_is_done(
batch_idx,
next_scores[batch_idx].max().item(),
cur_len,
)
return next_beam_scores.view(-1), next_beam_tokens.view(-1), next_beam_indices.view(-1)
def finalize(
self,
input_ids: torch.Tensor,
final_beam_scores: torch.Tensor,
final_beam_tokens: torch.Tensor,
final_beam_indices: torch.Tensor,
pad_token_id: int,
eos_token_id: int,
) -> Tuple[torch.Tensor, torch.Tensor]:
batch_size = len(self._beam_hyps_count)
# finalize all open beam hypotheses and add to generated hypotheses
for batch_idx in range(batch_size):
if self._done[batch_idx]:
continue
# all open beam hypotheses are added to the beam hypothesis
# beam hypothesis class automatically keeps the best beams
for beam_id in range(self.num_beams):
batch_beam_idx = batch_idx * self.num_beams + beam_id
final_score = final_beam_scores[batch_beam_idx].item()
final_tokens = input_ids[batch_beam_idx]
self.hypo_add(final_tokens, final_score, batch_idx)
# select the best hypotheses
# NOTE: torch.Tensor.new_zeros() is not scriptable
sent_lengths = torch.zeros(batch_size * self.num_beam_hyps_to_keep, dtype=torch.long)
best = []
best_scores = torch.zeros(
batch_size * self.num_beam_hyps_to_keep, device=input_ids.device, dtype=torch.float32
)
# retrieve best hypotheses
for i in range(batch_size):
# NOTE: lambda is not scriptable
batch_hypo_start = torch.sum(self._beam_hyps_count[:i]) if i > 0 else torch.tensor(0, dtype=torch.long)
batch_hypo_end = torch.sum(self._beam_hyps_count[: i + 1])
beam_scores = torch.cat(self._beam_scores)[batch_hypo_start:batch_hypo_end]
sorted_next_scores, sorted_indices = torch.topk(beam_scores, len(beam_scores), largest=True)
for j in range(self.num_beam_hyps_to_keep):
best_score = beam_scores[sorted_indices[j]]
best_hyp = self._beam_hyps[batch_hypo_start + sorted_indices[j]]
sent_lengths[self.num_beam_hyps_to_keep * i + j] = len(best_hyp)
# append to lists
best.append(best_hyp)
best_scores[i * self.num_beam_hyps_to_keep + j] = best_score
# prepare for adding eos
sent_max_len = min(sent_lengths.max() + 1, self.max_length)
decoded = torch.zeros(batch_size * self.num_beam_hyps_to_keep, sent_max_len, dtype=torch.long)
# shorter batches are padded if needed
if sent_lengths.min() != sent_lengths.max():
assert pad_token_id is not None, "`pad_token_id` has to be defined"
decoded.fill_(pad_token_id)
# fill with hypotheses and eos_token_id if the latter fits in
for i, hypo in enumerate(best):
decoded[i, : sent_lengths[i]] = hypo
if sent_lengths[i] < self.max_length:
decoded[i, sent_lengths[i]] = eos_token_id
return decoded, best_scores
class BARTBeamSearchGenerator(BARTGenerator):
def __init__(self, model):
super().__init__(model)
self.beam_scorer = BeamSearchScorerTS()
self.device = model.device
@staticmethod
def _expand_inputs_for_generation(
input_ids: torch.Tensor,
attention_mask: torch.Tensor,
last_hidden_state: torch.Tensor,
expand_size: int = 1,
) -> Tuple[torch.Tensor, torch.Tensor, torch.Tensor]:
expanded_return_idx = (
torch.arange(input_ids.shape[0]).view(-1, 1).repeat(1, expand_size).view(-1).to(input_ids.device)
)
input_ids = input_ids.index_select(0, expanded_return_idx)
attention_mask = attention_mask.index_select(0, expanded_return_idx)
last_hidden_state = last_hidden_state.index_select(0, expanded_return_idx.to(last_hidden_state.device))
return input_ids, attention_mask, last_hidden_state
def adjust_logits_during_generation(self, logits, cur_len: int, max_length: int):
if cur_len == 1 and self.config.force_bos_token_to_be_generated:
logits = self._force_token_id_to_be_generated(logits, self.config.bos_token_id)
elif cur_len == max_length - 1 and self.config.eos_token_id is not None:
logits = self._force_token_id_to_be_generated(logits, self.config.eos_token_id)
return logits
@staticmethod
def _force_token_id_to_be_generated(scores, token_id: int):
"""force one of token_ids to be generated by setting prob of all other tokens to 0 (logprob=-float("inf"))"""
mask = torch.full_like(scores, 1, dtype=torch.bool)
mask[:, token_id] = False
return scores.masked_fill(mask, -float("inf"))
def _reorder_cache(self, past: List[torch.Tensor], beam_idx):
# if decoder past is not included in output
# speedy decoding is disabled and no need to reorder
reordered_decoder_past = []
for state in past:
reordered_decoder_past.append(state.index_select(0, beam_idx))
return reordered_decoder_past
def beam_search(
self, input_ids, encoder_output, attention_mask, num_beams, max_length, pad_token_id: int, eos_token_id: int
):
batch_size = self.beam_scorer.batch_size
num_beams = self.beam_scorer.num_beams
batch_beam_size, cur_len = input_ids.shape
assert (
num_beams * batch_size == batch_beam_size
), f"Batch dimension of `input_ids` should be {num_beams * batch_size}, but is {batch_beam_size}."
beam_scores = torch.zeros((batch_size, num_beams), dtype=torch.float, device=input_ids.device)
beam_scores[:, 1:] = -1e9
beam_scores = beam_scores.view((batch_size * num_beams,))
next_tokens = torch.zeros((batch_size, num_beams), dtype=torch.long, device=input_ids.device)
next_indices = torch.zeros((batch_size, num_beams), dtype=torch.long, device=input_ids.device)
past: List[torch.Tensor] = []
while cur_len < max_length:
logits, past = self._decoder_forward(input_ids, encoder_output, attention_mask, past)
next_token_logits = logits[:, -1, :]
# adjust tokens for Bart, *e.g.*
next_token_logits = self.adjust_logits_during_generation(
next_token_logits, cur_len=cur_len, max_length=max_length
)
next_token_scores = F.log_softmax(next_token_logits, dim=-1) # (batch_size * num_beams, vocab_size)
# pre-process distribution
next_token_scores = self.logits_processor(input_ids, next_token_scores)
next_token_scores = next_token_scores + beam_scores[:, None].expand_as(next_token_scores)
# reshape for beam search
vocab_size = next_token_scores.shape[-1]
next_token_scores = next_token_scores.view(batch_size, num_beams * vocab_size)
next_token_scores, next_tokens = torch.topk(
next_token_scores, 2 * num_beams, dim=1, largest=True, sorted=True
)
next_indices = next_tokens // vocab_size
next_tokens = next_tokens % vocab_size
beam_scores, beam_next_tokens, beam_idx = self.beam_scorer.process(
input_ids,
next_token_scores,
next_tokens,
next_indices,
pad_token_id=pad_token_id,
eos_token_id=eos_token_id,
)
input_ids = torch.cat([input_ids[beam_idx, :], beam_next_tokens.unsqueeze(-1)], dim=-1)
cur_len = cur_len + 1
if len(past) > 0:
past = self._reorder_cache(past, beam_idx)
if self.beam_scorer.is_done():
break
sequences, sequence_scores = self.beam_scorer.finalize(
input_ids,
beam_scores,
next_tokens,
next_indices,
pad_token_id=pad_token_id,
eos_token_id=eos_token_id,
)
return sequences
def forward(self, input_ids, attention_mask, num_beams, max_length, decoder_start_token_id):
pad_token_id = self.config.pad_token_id
bos_token_id = self.config.bos_token_id
eos_token_id = self.config.eos_token_id
# special case if pad_token_id is not defined
if pad_token_id is None and eos_token_id is not None:
# logger.warning(f"Setting `pad_token_id` to `eos_token_id`:{eos_token_id} for open-end generation.")
pad_token_id = eos_token_id
encoder_output = self._encoder_forward(input_ids, attention_mask)
input_ids = self._prepare_decoder_input_ids_for_generation(
input_ids,
decoder_start_token_id=decoder_start_token_id,
bos_token_id=bos_token_id,
)
batch_size = input_ids.shape[0]
length_penalty = self.config.length_penalty
num_return_sequences = self.config.num_return_sequences
early_stopping = True
self.beam_scorer.init(
batch_size=batch_size,
max_length=max_length,
num_beams=num_beams,
device=self.device,
length_penalty=length_penalty,
do_early_stopping=early_stopping,
num_beam_hyps_to_keep=num_return_sequences,
)
input_ids, attention_mask, encoder_output = self._expand_inputs_for_generation(
input_ids,
attention_mask,
encoder_output,
expand_size=num_beams,
)
return self.beam_search(
input_ids=input_ids,
encoder_output=encoder_output,
attention_mask=attention_mask,
num_beams=num_beams,
max_length=max_length,
pad_token_id=pad_token_id,
eos_token_id=eos_token_id,
)
|
a94a0e38090bfd9a7bbdefa14020c7dae2bf1e8d
|
0760fb4901a75766921a205b55686d6d6f049b30
|
/python/ray/train/tests/test_data_parallel_trainer.py
|
6437abff58afa95a8282639742a8dbcd5799bce1
|
[
"MIT",
"BSD-3-Clause",
"Apache-2.0"
] |
permissive
|
ray-project/ray
|
a4bb6940b08b59a61ef0b8e755a52d8563a2f867
|
edba68c3e7cf255d1d6479329f305adb7fa4c3ed
|
refs/heads/master
| 2023-08-31T03:36:48.164405
| 2023-08-31T03:20:38
| 2023-08-31T03:20:38
| 71,932,349
| 29,482
| 5,669
|
Apache-2.0
| 2023-09-14T21:48:14
| 2016-10-25T19:38:30
|
Python
|
UTF-8
|
Python
| false
| false
| 10,999
|
py
|
test_data_parallel_trainer.py
|
import os
import time
from unittest.mock import patch
import pytest
import ray
from ray import train, tune
from ray.train import ScalingConfig, RunConfig
from ray.train._internal.backend_executor import BackendExecutor
from ray.train._internal.worker_group import WorkerGroup
from ray.train.backend import Backend, BackendConfig
from ray.train.data_parallel_trainer import DataParallelTrainer
from ray.tune.tune_config import TuneConfig
from ray.tune.tuner import Tuner
from ray.tune.callback import Callback
from ray.train.tests.util import create_dict_checkpoint, load_dict_checkpoint
@pytest.fixture
def ray_start_4_cpus():
address_info = ray.init(num_cpus=4)
yield address_info
# The code after the yield will run as teardown code.
ray.shutdown()
@pytest.fixture
def ray_start_4_cpus_4_gpus_4_extra():
address_info = ray.init(num_cpus=4, num_gpus=4, resources={"extra": 4})
yield address_info
# The code after the yield will run as teardown code.
ray.shutdown()
def gen_execute_single_async_special(special_f):
def execute_single_async_special(self, i, f, *args, **kwargs):
assert len(self.workers) == 2
if i == 0 and hasattr(self, "should_fail") and self.should_fail:
kwargs["train_func"] = special_f
return (
self.workers[i]
.actor._RayTrainWorker__execute.options(name=f.__name__)
.remote(f, *args, **kwargs)
)
return execute_single_async_special
def gen_new_backend_executor(special_f):
"""Returns a BackendExecutor that runs special_f on worker 0 once."""
class TestBackendExecutor(BackendExecutor):
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
self._has_failed = False
def start_training(self, *args, **kwargs):
special_execute = gen_execute_single_async_special(special_f)
if not self._has_failed:
self.worker_group.should_fail = True
self._has_failed = True
else:
self.worker_group.should_fail = False
with patch.object(WorkerGroup, "execute_single_async", special_execute):
super().start_training(*args, **kwargs)
return TestBackendExecutor
class CaptureReportCallback(Callback):
def __init__(self):
self.result_list = []
def on_trial_result(self, iteration, trials, trial, result, **info):
self.result_list.append(result)
scale_config = ScalingConfig(num_workers=2)
def test_fit_train(ray_start_4_cpus):
def train_func():
train.report({"loss": 1})
trainer = DataParallelTrainer(
train_loop_per_worker=train_func, scaling_config=scale_config
)
assert trainer.fit().metrics["loss"] == 1
def test_scaling_config(ray_start_4_cpus):
def train_func():
assert ray.available_resources()["CPU"] == 1
train.report({"loss": 1})
assert ray.available_resources()["CPU"] == 4
trainer = DataParallelTrainer(
train_loop_per_worker=train_func, scaling_config=ScalingConfig(num_workers=2)
)
trainer.fit()
def test_fit_train_config(ray_start_4_cpus):
def train_func(config):
train.report({"loss": config["x"]})
trainer = DataParallelTrainer(
train_loop_per_worker=train_func,
scaling_config=scale_config,
train_loop_config={"x": 100},
)
assert trainer.fit().metrics["loss"] == 100
def test_datasets(ray_start_4_cpus):
num_train_data = 10
num_val_data = 6
train_dataset = ray.data.range(num_train_data)
val_dataset = ray.data.range(num_val_data)
def get_dataset():
# Train dataset should be sharded.
train_dataset = train.get_dataset_shard("train")
train_ds_count = len(list(train_dataset.iter_rows()))
assert train_ds_count == num_train_data / scale_config.num_workers
# All other datasets should not be sharded.
val_dataset = train.get_dataset_shard("val")
val_ds_count = len(list(val_dataset.iter_rows()))
assert val_ds_count == num_val_data / scale_config.num_workers
trainer = DataParallelTrainer(
train_loop_per_worker=get_dataset,
scaling_config=scale_config,
datasets={"train": train_dataset, "val": val_dataset},
)
trainer.fit()
def test_invalid_train_loop(ray_start_4_cpus):
def train_loop(config, extra_arg):
pass
with pytest.raises(ValueError):
DataParallelTrainer(train_loop_per_worker=train_loop)
def test_bad_return_in_train_loop(ray_start_4_cpus):
"""Test to check if returns from train loop are discarded."""
# Simulates what happens with eg. torch models
class FailOnUnpickle:
def __reduce__(self):
raise RuntimeError("Failing")
def train_loop(config):
train.report({"loss": 1})
return FailOnUnpickle()
trainer = DataParallelTrainer(
train_loop_per_worker=train_loop, scaling_config=scale_config
)
# No exception should happen here
trainer.fit()
def test_tune(ray_start_4_cpus):
def train_func(config):
train.report({"loss": config["x"]})
trainer = DataParallelTrainer(
train_loop_per_worker=train_func,
train_loop_config={"x": 100},
scaling_config=scale_config,
)
tuner = Tuner(
trainer,
param_space={"train_loop_config": {"x": tune.choice([200, 300])}},
tune_config=TuneConfig(num_samples=2),
)
result_grid = tuner.fit()
assert result_grid[0].metrics["loss"] in [200, 300]
# Make sure original Trainer is not affected.
assert trainer._train_loop_config["x"] == 100
def test_scaling_config_validation(ray_start_4_cpus):
def train_func(config):
train.report({"loss": config["x"]})
# Should be able to create a DataParallelTrainer w/o scaling_config,
# but it should fail on fit
trainer = DataParallelTrainer(
train_loop_per_worker=train_func,
train_loop_config={"x": 100},
)
with pytest.raises(ValueError):
trainer.fit()
# Scaling config must be passed in through Tuner param space if not
# included in the initial trainer
tuner = Tuner(trainer)
with pytest.raises(ValueError):
tuner.fit()
tuner = Tuner(trainer, param_space={"scaling_config": ScalingConfig(num_workers=1)})
results = tuner.fit()
assert not results.errors
def test_fast_slow(ray_start_4_cpus):
def train_func():
for i in range(2):
with create_dict_checkpoint({"epoch": i}) as checkpoint:
train.report(dict(index=i), checkpoint=checkpoint)
def train_slow():
for i in range(2):
with create_dict_checkpoint({"epoch": i}) as checkpoint:
train.report(dict(index=i), checkpoint=checkpoint)
time.sleep(5)
new_backend_executor_cls = gen_new_backend_executor(train_slow)
callback = CaptureReportCallback()
class DataParallelTrainerPatched(DataParallelTrainer):
_backend_executor_cls = new_backend_executor_cls
trainer = DataParallelTrainerPatched(
train_func,
scaling_config=scale_config,
run_config=RunConfig(callbacks=[callback]),
)
results = trainer.fit()
assert load_dict_checkpoint(results.checkpoint)["epoch"] == 1
result_list = callback.result_list
assert len(result_list) == 2
def test_mismatch_report(ray_start_4_cpus):
def train_func():
for _ in range(2):
train.report(dict(loss=1))
def train_mismatch():
train.report(dict(loss=1))
new_backend_executor_cls = gen_new_backend_executor(train_mismatch)
class DataParallelTrainerPatched(DataParallelTrainer):
_backend_executor_cls = new_backend_executor_cls
trainer = DataParallelTrainerPatched(
train_func,
scaling_config=scale_config,
)
with pytest.raises(RuntimeError):
trainer.fit()
def test_world_rank(ray_start_4_cpus, tmp_path):
def train_func():
world_rank = train.get_context().get_world_rank()
(tmp_path / f"{world_rank}").touch()
train.report(dict(world_rank=world_rank))
trainer = DataParallelTrainer(train_func, scaling_config=scale_config)
trainer.fit()
created_files = list(tmp_path.glob("*"))
assert len(created_files) == 2
assert {int(file.name) for file in created_files} == {0, 1}
def test_gpu_requests(ray_start_4_cpus_4_gpus_4_extra, tmp_path):
def get_visible_devices_for_workers():
return [file.read_text() for file in tmp_path.glob("*")]
class CudaTestBackend(Backend):
share_cuda_visible_devices = True
class CudaTestConfig(BackendConfig):
@property
def backend_cls(self):
return CudaTestBackend
def get_resources():
cuda_visible_devices = os.environ["CUDA_VISIBLE_DEVICES"]
world_rank = train.get_context().get_world_rank()
(tmp_path / f"{world_rank}").write_text(cuda_visible_devices)
train.report(dict(devices=cuda_visible_devices))
# 0 GPUs will be requested and should not raise an error.
trainer = DataParallelTrainer(
get_resources,
backend_config=CudaTestConfig(),
scaling_config=ScalingConfig(num_workers=2, use_gpu=False),
)
trainer.fit()
assert get_visible_devices_for_workers() == ["", ""]
# 1 GPU will be requested and should not raise an error.
trainer = DataParallelTrainer(
get_resources,
backend_config=CudaTestConfig(),
scaling_config=ScalingConfig(num_workers=2, use_gpu=True),
)
trainer.fit()
visible_devices = get_visible_devices_for_workers()
# Sort the cuda visible devices to have exact match with expected result.
visible_devices = [",".join(sorted(r.split(","))) for r in visible_devices]
assert visible_devices == ["0,1", "0,1"]
# Partial GPUs should not raise an error.
trainer = DataParallelTrainer(
get_resources,
backend_config=CudaTestConfig(),
scaling_config=ScalingConfig(
num_workers=2, use_gpu=True, resources_per_worker={"GPU": 0.1}
),
)
trainer.fit()
visible_devices = get_visible_devices_for_workers()
assert visible_devices == ["0", "0"]
# Multiple GPUs should not raise an error.
trainer = DataParallelTrainer(
get_resources,
backend_config=CudaTestConfig(),
scaling_config=ScalingConfig(
num_workers=2, use_gpu=True, resources_per_worker={"GPU": 2}
),
)
trainer.fit()
visible_devices = get_visible_devices_for_workers()
# Sort the cuda visible devices to have exact match with expected result.
visible_devices = [",".join(sorted(r.split(","))) for r in visible_devices]
assert visible_devices == ["0,1,2,3", "0,1,2,3"]
if __name__ == "__main__":
import sys
import pytest
sys.exit(pytest.main(["-v", "-x", __file__]))
|
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