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source | linux | * NXP LPC18xx OTP memory
Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
Required properties:
- compatible: Should be "nxp,lpc1850-otp"
- reg: Must contain an entry with the physical base address and length
for each entry in reg-names.
- address-cells: must be set to 1.
- size-ce... | Documentation/devicetree/bindings/nvmem/lpc1850-otp.txt | null | null | null | null | null |
source | linux | OpenRISC Generic SoC
====================
Boards and FPGA SoC's which support the OpenRISC standard platform. The
platform essentially follows the conventions of the OpenRISC architecture
specification, however some aspects, such as the boot protocol have been defined
by the Linux port.
Required properties
---------... | Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt | null | null | null | null | null |
source | linux | HiSilicon STB PCIe host bridge DT description
The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
It shares common functions with the DesignWare PCIe core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Additional properties are descri... | Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt | null | null | null | null | null |
source | linux | NVIDIA Tegra PCIe controller
Required properties:
- compatible: Must be:
- "nvidia,tegra20-pcie": for Tegra20
- "nvidia,tegra30-pcie": for Tegra30
- "nvidia,tegra124-pcie": for Tegra124 and Tegra132
- "nvidia,tegra210-pcie": for Tegra210
- "nvidia,tegra186-pcie": for Tegra186
- power-domains: To ungate power... | Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | null | null | null | null | null |
source | linux | * Mediatek/Ralink RT3883 PCI controller
1) Main node
Required properties:
- compatible: must be "ralink,rt3883-pci"
- reg: specifies the physical base address of the controller and
the length of the memory mapped region.
- #address-cells: specifies the number of cells needed to encode an
addr... | Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt | null | null | null | null | null |
source | linux | TI PCI Controllers
PCIe DesignWare Controller
- compatible: Should be "ti,dra7-pcie" for RC (deprecated)
Should be "ti,dra7-pcie-ep" for EP (deprecated)
Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
Should be "ti,dra... | Documentation/devicetree/bindings/pci/ti-pci.txt | null | null | null | null | null |
source | linux | This document explains only the device tree data binding. For general
information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
PHY device node
===============
Required Properties:
#phy-cells: Number of cells in a PHY specifier; The meaning of all those
cells is defined by the binding for the p... | Documentation/devicetree/bindings/phy/phy-bindings.txt | null | null | null | null | null |
source | linux | STMicroelectronics STi MIPHY28LP PHY binding
============================================
This binding describes a miphy device that is used to control PHY hardware
for SATA, PCIe or USB3.
Required properties (controller (parent) node):
- compatible : Should be "st,miphy28lp-phy".
- st,syscfg : Should be a phandle of... | Documentation/devicetree/bindings/phy/phy-miphy28lp.txt | null | null | null | null | null |
source | linux | STMicroelectronics STi MIPHY365x PHY binding
============================================
This binding describes a miphy device that is used to control PHY hardware
for SATA and PCIe.
Required properties (controller (parent) node):
- compatible : Should be "st,miphy365x-phy"
- st,syscfg : Phandle / integer arr... | Documentation/devicetree/bindings/phy/phy-miphy365x.txt | null | null | null | null | null |
source | linux | Abilis Systems TB10x pin controller
===================================
Required properties
-------------------
- compatible: should be "abilis,tb10x-iomux";
- reg: should contain the physical address and size of the pin controller's
register range.
Function definitions
--------------------
Functions are defined... | Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt | null | null | null | null | null |
source | linux | * Atmel PIO4 Controller
The Atmel PIO4 controller is used to select the function of a pin and to
configure it.
Required properties:
- compatible:
"atmel,sama5d2-pinctrl"
"microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"
"microchip,sama7g5-pinctrl"
- reg: base address and length of the PIO controller.
- int... | Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | null | null | null | null | null |
source | linux | Axis ARTPEC-6 Pin Controller
Required properties:
- compatible: "axis,artpec6-pinctrl".
- reg: Should contain the register physical address and length for the pin
controller.
A pinctrl node should contain at least one subnode representing the pinctrl
groups available on the machine. Each subnode will list the ... | Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt | null | null | null | null | null |
source | linux | Broadcom Cygnus IOMUX Controller
The Cygnus IOMUX controller supports group based mux configuration. In
addition, certain pins can be muxed to GPIO function individually.
Required properties:
- compatible:
Must be "brcm,cygnus-pinmux"
- reg:
Define the base and range of the I/O address space that contains t... | Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt | null | null | null | null | null |
source | linux | Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
Required properties:
- compatible:
Must be "brcm,nsp-gpio-a"
- reg:
Should contain the register physical address and length for each of
GPIO base, IO control registers
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
... | Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt | null | null | null | null | null |
source | linux | Broadcom NSP (Northstar plus) IOMUX Controller
The NSP IOMUX controller supports group based mux configuration. In
addition, certain pins can be muxed to GPIO function individually.
Required properties:
- compatible:
Must be "brcm,nsp-pinmux"
- reg:
Should contain the register physical address and length for... | Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt | null | null | null | null | null |
source | linux | Conexant Digicolor CX92755 General Purpose Pin Mapping
This document describes the device tree binding of the pin mapping hardware
modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
Digicolor series of SoCs.
=== Pin Controller Node ===
Required Properties:
- compatible: Must be "cnxt,cx92755-... | Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt | null | null | null | null | null |
source | linux | Cortina Systems Gemini pin controller
This pin controller is found in the Cortina Systems Gemini SoC family,
see further arm/gemini.txt. It is a purely group-based multiplexing pin
controller.
The pin controller node must be a subnode of the system controller node.
Required properties:
- compatible: "cortina,gemini-... | Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt | null | null | null | null | null |
source | linux | * Freescale IOMUX Controller (IOMUXC) for i.MX
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called ALT modes). Since different module... | Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | null | null | null | null | null |
source | linux | * Freescale IMX25 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
CONFIG bits definition:
PAD_CTL_HYS (1 << 8)
PAD_CTL_PKE (1 << 7)
PAD_CTL_PUE (1 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PU... | Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt | null | null | null | null | null |
source | linux | * Freescale IMX27 IOMUX Controller
Required properties:
- compatible: "fsl,imx27-iomuxc"
The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
Required properties for pin configuration node:
- fsl,pins: three integers array, represents a group of pins mux and config
setting. T... | Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt | null | null | null | null | null |
source | linux | Imagination Technologies Pistachio SoC pin controllers
======================================================
The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
interrupt controller, and pinmux + pinconf device. The system ("east") pin
controller on Pistachio has 99 pins, 90 of which are MFIOs whi... | Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt | null | null | null | null | null |
source | linux | Lantiq FALCON pinmux controller
Required properties:
- compatible: "lantiq,pinctrl-falcon"
- reg: Should contain the physical address and length of the gpio/pinmux
register range
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the m... | Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt | null | null | null | null | null |
source | linux | Lantiq XWAY pinmux controller
Required properties:
- compatible: "lantiq,<chip>-pinctrl", where <chip> is:
"ase" (XWAY AMAZON Family)
"danube" (XWAY DANUBE Family)
"xrx100" (XWAY xRX100 Family)
"xrx200" (XWAY xRX200 Family)
"xrx300" (XWAY xRX300 Family)
- reg: Should contain the physical address and length o... | Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt | null | null | null | null | null |
source | linux | * Marvell Armada 370 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6710-pinctrl"
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not pa... | Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Armada 375 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6720-pinctrl"
- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not pa... | Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Armada 380/385 SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
"marvell,88f6828-pinctrl" depending on the specific variant of the
SoC being... | Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Armada 39x SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
"marvell,88f6928-pinctrl" depending on the specific variant of the
SoC being use... | Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell 98dx3236 pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage
Required properties:
- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
- reg: register specifier of MPP registers
This driver supports all 98dx3236, 98dx3336 an... | Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Armada XP SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
"marvell,mv78460-pinctrl"
- reg: register specifier of MPP registers
Thi... | Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Dove SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,dove-pinctrl"
- clocks: (optional) phandle of pdma clock
- reg: register specifiers of MPP, MPP4, and PMU MPP registers
Available mpp pi... | Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Kirkwood SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f6180-pinctrl",
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
"marvell,88f6281-pinctrl", "marve... | Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell SoC pinctrl core driver for mpp
The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
(mpp) to a specific function. For each SoC family there is a SoC specific
driver using this core driver.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindin... | Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt | null | null | null | null | null |
source | linux | * Marvell Orion SoC pinctrl driver for mpp
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "marvell,88f5181-pinctrl",
"marvell,88f5181l-pinctrl",
"marvell,88f5182-pinctrl",
"marvell,88f5281-pinc... | Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt | null | null | null | null | null |
source | linux | * Microchip PIC32 Pin Controller
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.
PIC32 'pin configuration node' is a node of a group of pins which can be
used for a specific device or fun... | Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | null | null | null | null | null |
source | linux | Nuvoton NPCM7XX Pin Controllers
The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
the multiplexing block, Each pin supports GPIO functionality (GPIOx)
and multiple functions that directly connect the pin to different
hardware blocks.
Required properties:
- #address-cells : should be 1.
- #size-cell... | Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | null | null | null | null | null |
source | linux | Device tree binding for NVIDIA Tegra XUSB pad controller
========================================================
NOTE: It turns out that this binding isn't an accurate description of the XUSB
pad controller. While the description is good enough for the functional subset
required for PCIe and SATA, it lacks the flexib... | Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt | null | null | null | null | null |
source | linux | == Introduction ==
Hardware modules that control pin multiplexing or configuration parameters
such as pull-up/down, tri-state, drive-strength etc are designated as pin
controllers. Each pin controller must be represented as a node in device tree,
just like any other hardware module.
Hardware modules whose signals are... | Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | null | null | null | null | null |
source | linux | Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the... | Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt | null | null | null | null | null |
source | linux | Palmas Pincontrol bindings
The pins of Palmas device can be set on different option and provides
the configuration for Pull UP/DOWN, open drain etc.
Required properties:
- compatible: It must be one of following:
- "ti,palmas-pinctrl" for Palma series of the pincontrol.
- "ti,tps65913-pinctrl" for Palma series de... | Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt | null | null | null | null | null |
source | linux | Pincontrol driver for RK805 Power management IC.
RK805 has 2 pins which can be configured as GPIO output only.
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the meaning of the phrase "pin configuration node".
Optional... | Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt | null | null | null | null | null |
source | linux | CSR SiRFprimaII pinmux controller
Required properties:
- compatible : "sirf,prima2-pinctrl"
- reg : Address range of the pinctrl registers
- interrupts : Interrupts used by every GPIO group
- gpio-controller : Indicates this device is a GPIO controller
- interrupt-controller : Marks the device node as an interrup... | Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt | null | null | null | null | null |
source | linux | *ST pin controller.
Each multi-function pin is controlled, driven and routed through the
PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
and multiple alternate functions(ALT1 - ALTx) that directly connect
the pin to different hardware blocks.
When a pin is in GPIO mode, Output Enable (OE), Open Dr... | Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt | null | null | null | null | null |
source | linux | VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
Required properties:
- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
"wm8750-p... | Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt | null | null | null | null | null |
source | linux | ST Microelectronics, SPEAr pinmux controller
Required properties:
- compatible : "st,spear300-pinmux"
: "st,spear310-pinmux"
: "st,spear320-pinmux"
: "st,spear1310-pinmux"
: "st,spear1340-pinmux"
- reg : Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid f... | Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt | null | null | null | null | null |
source | linux | ST Ericsson abx500 pinmux controller
Required properties:
- compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio",
"stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including th... | Documentation/devicetree/bindings/pinctrl/ste,abx500.txt | null | null | null | null | null |
source | linux | ST Ericsson Nomadik pinmux controller
Required properties:
- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
"stericsson,stn8815-pinctrl"
- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
(these have the register ranges used by the pin controller)... | Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt | null | null | null | null | null |
source | linux | * Pin configuration for TI DA850/OMAP-L138/AM18x
These SoCs have a separate controller for setting bias (internal pullup/down).
Bias can only be selected for groups rather than individual pins.
Required Properties:
- compatible: Must be "ti,da850-pupd"
- reg: Base address and length of the memory resource used b... | Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt | null | null | null | null | null |
source | linux | * Pin configuration for TI IODELAY controller
TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
for each pin. For most part the IO delay values are programmed by the bootloader,
but some pins need to be configured dynamically by the kernel such as the
MMC pins.
Required Properties:
- com... | Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt | null | null | null | null | null |
source | linux | Amlogic Meson Power Controller (deprecated)
===========================================
The Amlogic Meson SoCs embeds an internal Power domain controller.
VPU Power Domain
----------------
The Video Processing Unit power domain is controlled by this power controller,
but the domain requires some external resources t... | Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt | null | null | null | null | null |
source | linux | * Generic system power control capability
Power-management integrated circuits or miscellaneous hardware components are
sometimes able to control the system power. The device driver associated with these
components might need to define this capability, which tells the kernel that
it can be used to switch off the syste... | Documentation/devicetree/bindings/power/power-controller.txt | null | null | null | null | null |
source | linux | * Generic PM domains
System on chip designs are often divided into multiple PM domains that can be
used for power gating of selected IP blocks for power saving by reduced leakage
current.
This device tree binding can be used to bind PM domain consumer devices with
their PM domains provided by PM domain providers. A P... | Documentation/devicetree/bindings/power/power_domain.txt | null | null | null | null | null |
source | linux | Texas Instruments SmartReflex binding
SmartReflex is used to set and adjust the SoC operating points.
Required properties:
compatible: Shall be one of the following:
"ti,omap3-smartreflex-core"
"ti,omap3-smartreflex-mpu-iva"
"ti,omap4-smartreflex-core"
"ti,omap4-smartreflex-mpu"
"ti,omap4-s... | Documentation/devicetree/bindings/power/ti-smartreflex.txt | null | null | null | null | null |
source | linux | Specifying wakeup capability for devices
============================================
Any device nodes
----------------
Nodes that describe devices which have wakeup capability may contain a
"wakeup-source" boolean property.
If the device is marked as a wakeup-source, interrupt wake capability depends
on the device s... | Documentation/devicetree/bindings/power/wakeup-source.txt | null | null | null | null | null |
source | linux | Axxia Restart Driver
This driver can do reset of the Axxia SoC. It uses the registers in the syscon
block to initiate a chip reset.
Required Properties:
-compatible: "lsi,axm55xx-reset"
-syscon: phandle to the syscon node.
Example:
syscon: syscon@2010030000 {
compatible = "lsi,axxia-syscon", "syscon";
reg ... | Documentation/devicetree/bindings/power/reset/axxia-reset.txt | null | null | null | null | null |
source | linux | * Device-Tree bindings for Cortina Systems Gemini Poweroff
This is a special IP block in the Cortina Gemini SoC that only
deals with different ways to power the system down.
Required properties:
- compatible: should be "cortina,gemini-power-controller"
- reg: should contain the physical memory base and size
- interru... | Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt | null | null | null | null | null |
source | linux | * Device tree bindings for Texas Instruments keystone reset
This node is intended to allow SoC reset in case of software reset
of selected watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux
block. The Reset Mux block can be conf... | Documentation/devicetree/bindings/power/reset/keystone-reset.txt | null | null | null | null | null |
source | linux | Binding for the LTC2952 PowerPath controller
This chip is used to externally trigger a system shut down. Once the trigger has
been sent, the chip's watchdog has to be reset to gracefully shut down.
A full powerdown can be triggered via the kill signal.
Required properties:
- compatible: Must contain: "lltc,ltc2952"... | Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt | null | null | null | null | null |
source | linux | Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
SoC core.
The reset registers are both present in the MSCC vcoreiii MIPS and
microchip Sparx5 armv8 SoC's.
Required Properties:
- compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
"mscc... | Documentation/devicetree/bindings/power/reset/ocelot-reset.txt | null | null | null | null | null |
source | linux | * QNAP Power Off
QNAP NAS devices have a microcontroller controlling the main power
supply. This microcontroller is connected to UART1 of the Kirkwood and
Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the
microcontroller to turn the power off.
Synology NAS devices use a similar scheme, but a different... | Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt | null | null | null | null | null |
source | linux | * Restart Power Off
Buffalo Linkstation LS-XHL and LS-CHLv2, and other devices power off
by restarting and letting u-boot keep hold of the machine until the
user presses a button.
Required Properties:
- compatible: Should be "restart-poweroff" | Documentation/devicetree/bindings/power/reset/restart-poweroff.txt | null | null | null | null | null |
source | linux | *Device-Tree bindings for ST SW reset functionality
Required properties:
- compatible: should be "stih407-restart".
- st,syscfg: should be a phandle of the syscfg node.
Example node:
restart {
compatible = "st,stih407-restart";
st,syscfg = <&syscfg_sbc_reg>;
}; | Documentation/devicetree/bindings/power/reset/st-reset.txt | null | null | null | null | null |
source | linux | *** NOTE ***
This document is copied from OPAL firmware
(skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
There is more complete overview and documentation of features in that
source tree. All patches and modifications should go there.
************
ibm,powerpc-cpu-features binding
======================... | Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt | null | null | null | null | null |
source | linux | * IBM Powerpc Virtual Accelerator Switchboard (VAS)
VAS is a hardware mechanism that allows kernel subsystems and user processes
to directly submit compression and other requests to Nest accelerators (NX)
or other coprocessors functions.
Required properties:
- compatible : should be "ibm,vas".
- ibm,vas-id : A unique... | Documentation/devicetree/bindings/powerpc/ibm,vas.txt | null | null | null | null | null |
source | linux | IBM Akebono board device tree
=============================
The IBM Akebono board is a development board for the PPC476GTR SoC.
0) The root node
Required properties:
- model : "ibm,akebono".
- compatible : "ibm,akebono" , "ibm,476gtr".
1.a) The Secure Digital Host Controller Interface (SDHCI) node
Repr... | Documentation/devicetree/bindings/powerpc/4xx/akebono.txt | null | null | null | null | null |
source | linux | PPC4xx Clock Power Management (CPM) node
Required properties:
- compatible : compatible list, currently only "ibm,cpm"
- dcr-access-method : "native"
- dcr-reg : < DCR register range >
Optional properties:
- er-offset : All 4xx SoCs with a CPM controller have
one of two different order for the CPM
... | Documentation/devicetree/bindings/powerpc/4xx/cpm.txt | null | null | null | null | null |
source | linux | ppc476gtr High Speed Serial Assist (HSTA) node
==============================================
The 476gtr SoC contains a high speed serial assist module attached
between the plb4 and plb6 system buses to provide high speed data
transfer between memory and system peripherals as well as support for
PCI message signalled ... | Documentation/devicetree/bindings/powerpc/4xx/hsta.txt | null | null | null | null | null |
source | linux | PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
Device nodes needed for operation of the ppc440spe-adma driver
are specified hereby. These are I2O/DMA, DMA and XOR nodes
for DMA engines and Memory Queue Module node. The latter is used
by ADMA driver for configuration of RAID-6 H/W capabilities of
the PPC440SPe.... | Documentation/devicetree/bindings/powerpc/4xx/ppc440spe-adma.txt | null | null | null | null | null |
source | linux | Reboot property to control system reboot on PPC4xx systems:
By setting "reset_type" to one of the following values, the default
software reset mechanism may be overridden. Here the possible values of
"reset_type":
1 - PPC4xx core reset
2 - PPC4xx chip reset
3 - PPC4xx system reset (default)
Example... | Documentation/devicetree/bindings/powerpc/4xx/reboot.txt | null | null | null | null | null |
source | linux | Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
DESCRIPTION
The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
that enables the implementation of coherent, multicore systems.
Required properties:
- compatible: <string list>
fsl,corenet1-cf - CoreNet coherency fabric version... | Documentation/devicetree/bindings/powerpc/fsl/ccf.txt | null | null | null | null | null |
source | linux | ===================================================================
Power Architecture CPU Binding
Copyright 2013 Freescale Semiconductor Inc.
Power Architecture CPUs in Freescale SOCs are represented in device trees as
per the definition in the Devicetree Specification.
In addition to the Devicetree Specification de... | Documentation/devicetree/bindings/powerpc/fsl/cpus.txt | null | null | null | null | null |
source | linux | ===================================================================
Debug Control and Status Register (DCSR) Binding
Copyright 2011 Freescale Semiconductor Inc.
NOTE: The bindings described in this document are preliminary and subject
to change. Some of the compatible strings that contain only generic names
may turn ... | Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt | null | null | null | null | null |
source | linux | * Freescale Display Interface Unit
The Freescale DIU is a LCD controller, with proper hardware, it can also
drive DVI monitors.
Required properties:
- compatible : should be "fsl,diu" or "fsl,mpc5121-diu".
- reg : should contain at least address and length of the DIU register
set.
- interrupts : one DIU interrupt s... | Documentation/devicetree/bindings/powerpc/fsl/diu.txt | null | null | null | null | null |
source | linux | =====================================================================
E500 LAW & Coherency Module Device Tree Binding
Copyright (C) 2009 Freescale Semiconductor Inc.
=====================================================================
Local Access Window (LAW) Node
The LAW node represents the region of CCSR space wh... | Documentation/devicetree/bindings/powerpc/fsl/ecm.txt | null | null | null | null | null |
source | linux | ===============================================================================
Freescale Interlaken Look-Aside Controller Device Bindings
Copyright 2012 Freescale Semiconductor Inc.
CONTENTS
- Interlaken Look-Aside Controller (LAC) Node
- Example LAC Node
- Interlaken Look-Aside Controller (LAC) Software Portal... | Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt | null | null | null | null | null |
source | linux | * Chipselect/Local Bus
Properties:
- name : Should be localbus
- #address-cells : Should be either two or three. The first cell is the
chipselect number, and the remaining cells are the
offset into the chipselect.
- #size-cells : Either one or two, depending on how large each chi... | Documentation/devicetree/bindings/powerpc/fsl/lbc.txt | null | null | null | null | null |
source | linux | =====================================================================
MPX LAW & Coherency Module Device Tree Binding
Copyright (C) 2009 Freescale Semiconductor Inc.
=====================================================================
Local Access Window (LAW) Node
The LAW node represents the region of CCSR space whe... | Documentation/devicetree/bindings/powerpc/fsl/mcm.txt | null | null | null | null | null |
source | linux | MPC5121 PSC Device Tree Bindings
PSC in UART mode
----------------
For PSC in UART mode the needed PSC serial devices
are specified by fsl,mpc5121-psc-uart nodes in the
fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
Controller node fsl,mpc5121-psc-fifo is required there:
fsl,mpc512x-psc-uart nodes
------------... | Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt | null | null | null | null | null |
source | linux | Freescale MPC512x LocalPlus Bus FIFO (called SCLPC in the Reference Manual)
Required properties:
- compatible: should be "fsl,mpc512x-lpbfifo";
- reg: should contain the offset and length of SCLPC register set;
- interrupts: should contain the interrupt specifier for SCLPC; syntax of an
interrupt client node is de... | Documentation/devicetree/bindings/powerpc/fsl/mpc512x_lpbfifo.txt | null | null | null | null | null |
source | linux | MPC5200 Device Tree Bindings
----------------------------
(c) 2006-2009 Secret Lab Technologies Ltd
Grant Likely <grant.likely@secretlab.ca>
Naming conventions
------------------
For mpc5200 on-chip devices, the format for each compatible value is
<chip>-<device>[-<mode>]. The OS should be able to match a device dri... | Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt | null | null | null | null | null |
source | linux | * FSL MPIC Message Registers
This binding specifies what properties must be available in the device tree
representation of the message register blocks found in some FSL MPIC
implementations.
Required properties:
- compatible: Specifies the compatibility list for the message register
block. The type shall ... | Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt | null | null | null | null | null |
source | linux | * Freescale MPIC timers
Required properties:
- compatible: "fsl,mpic-global-timer"
- reg : Contains two regions. The first is the main timer register bank
(GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
register (TCRx) for the group.
- fsl,available-ranges: use <start count> style section ... | Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt | null | null | null | null | null |
source | linux | Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding
DESCRIPTION
The PAMU is an I/O MMU that provides device-to-memory access control and
address translation capabilities.
Required properties:
- compatible : <string>
First entry is a version-specific string, such as
"fsl,pamu-v1.0". The s... | Documentation/devicetree/bindings/powerpc/fsl/pamu.txt | null | null | null | null | null |
source | linux | * Freescale 85xx RAID Engine nodes
RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
Engine should have a separate node.
Supported chips:
P5020, P5040
Required properties:
- compatible: Should contain "fsl,raideng-v1.0" as the value
This identifies RAID Engine block. 1 in 1.0 represe... | Documentation/devicetree/bindings/powerpc/fsl/raideng.txt | null | null | null | null | null |
source | linux | Freescale Supplement configuration unit (SCFG)
SCFG is the supplemental configuration unit, that provides SoC specific
configuration and status registers for the chip. Such as getting PEX port
status.
Required properties:
- compatible: should be "fsl,<chip>-scfg"
- reg: should contain base address and length of SCFG... | Documentation/devicetree/bindings/powerpc/fsl/scfg.txt | null | null | null | null | null |
source | linux | Message unit node:
For SRIO controllers that implement the message unit as part of the controller
this node is required. For devices with RMAN this node should NOT exist. The
node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
See srio.txt for mo... | Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt | null | null | null | null | null |
source | linux | * Freescale Serial RapidIO (SRIO) Controller
RapidIO port node:
Properties:
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,srio" for IP blocks with IP Block
Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
Optionally, a compatible string of "fsl,srio-vX.Y" where X is ... | Documentation/devicetree/bindings/powerpc/fsl/srio.txt | null | null | null | null | null |
source | linux | Nintendo GameCube device tree
=============================
1) The "flipper" node
This node represents the multi-function "Flipper" chip, which packages
many of the devices found in the Nintendo GameCube.
Required properties:
- compatible : Should be "nintendo,flipper"
1.a) The Video Interface (VI) node
... | Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt | null | null | null | null | null |
source | linux | Nintendo Wii device tree
========================
0) The root node
This node represents the Nintendo Wii video game console.
Required properties:
- model : Should be "nintendo,wii"
- compatible : Should be "nintendo,wii"
1) The "hollywood" node
This node represents the multi-function "Hollywood" chip,... | Documentation/devicetree/bindings/powerpc/nintendo/wii.txt | null | null | null | null | null |
source | linux | IBM OPAL Operator Panel Binding
-------------------------------
Required properties:
- compatible : Should be "ibm,opal-oppanel".
- #lines : Number of lines on the operator panel e.g. <0x2>.
- #length : Number of characters per line of the operator panel e.g. <0x10>.
Example:
oppanel {
compatible = "ibm,opa... | Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt | null | null | null | null | null |
source | linux | IBM Power-Management Bindings
=============================
Linux running on baremetal POWER machines has access to the processor
idle states. The description of these idle states is exposed via the
node @power-mgt in the device-tree by the firmware.
Definitions:
----------------
Typically each idle state has the fol... | Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt | null | null | null | null | null |
source | linux | IBM OPAL Sensor Groups Binding
-------------------------------
Node: /ibm,opal/sensor-groups
Description: Contains sensor groups available in the Powernv P9
servers. Each child node indicates a sensor group.
- compatible : Should be "ibm,opal-sensor-group"
Each child node contains below properties:
- type : String... | Documentation/devicetree/bindings/powerpc/opal/sensor-groups.txt | null | null | null | null | null |
source | linux | * Broadcom Digital Timing Engine(DTE) based PTP clock
Required properties:
- compatible: should contain the core compatibility string
and the SoC compatibility string. The SoC
compatibility string is to handle SoC specific
hardware differences.
Core compatibility... | Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt | null | null | null | null | null |
source | linux | ZHAW InES PTP time stamping IP core
The IP core needs two different kinds of nodes. The control node
lives somewhere in the memory map and specifies the address of the
control registers. There can be up to three port handles placed as
attributes of PHY nodes. These associate a particular MII bus with a
port index w... | Documentation/devicetree/bindings/ptp/ptp-ines.txt | null | null | null | null | null |
source | linux | Time stamps from MII bus snooping devices
This binding supports non-PHY devices that snoop the MII bus and
provide time stamps. In contrast to PHY time stamping drivers (which
can simply attach their interface directly to the PHY instance), stand
alone MII time stamping drivers use this binding to specify the
connect... | Documentation/devicetree/bindings/ptp/timestamper.txt | null | null | null | null | null |
source | linux | * Cirris Logic CLPS711X PWM controller
Required properties:
- compatible: Shall contain "cirrus,ep7209-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks: phandle + clock specifier pair of the PWM reference clock.
- #pwm-cells: Should be 1. The cell specifies the index of the channel... | Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt | null | null | null | null | null |
source | linux | *Imagination Technologies PWM DAC driver
Required properties:
- compatible: Should be "img,pistachio-pwm"
- reg: Should contain physical base address and length of pwm registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clock/clock-bindings.txt for details.
- clock-names: Must inc... | Documentation/devicetree/bindings/pwm/img-pwm.txt | null | null | null | null | null |
source | linux | NXP PCA9685 16-channel 12-bit PWM LED controller
================================================
Required properties:
- compatible: "nxp,pca9685-pwm"
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
the cells format.
The index 16 is the ALLCALL channel, that sets all PWM chan... | Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt | null | null | null | null | null |
source | linux | Hisilicon PWM controller
Required properties:
-compatible: should contain one SoC specific compatible string
The SoC specific strings supported including:
"hisilicon,hi3516cv300-pwm"
"hisilicon,hi3519v100-pwm"
"hisilicon,hi3559v100-shub-pwm"
"hisilicon,hi3559v100-pwm
- reg: physical base address and length of the... | Documentation/devicetree/bindings/pwm/pwm-hibvt.txt | null | null | null | null | null |
source | linux | TI/National Semiconductor LP3943 PWM controller
Required properties:
- compatible: "ti,lp3943-pwm"
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a
description of the cells format.
Note that this hardware limits the period length to the
range 6250~1600... | Documentation/devicetree/bindings/pwm/pwm-lp3943.txt | null | null | null | null | null |
source | linux | STMicroelectronics PWM driver bindings
--------------------------------------
Required parameters:
- compatible : "st,pwm"
- #pwm-cells : Number of cells used to specify a PWM. First cell
specifies the per-chip index of the PWM to use and the
second cell is the period in nanoseconds - fixed to 2
for STiH41... | Documentation/devicetree/bindings/pwm/pwm-st.txt | null | null | null | null | null |
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