[
  {
    "name": "Superblue Raw Circuit Data",
    "slug": "superblue-raw-circuit-data",
    "category": "asic_physical_design",
    "domain_module": "asic_physical_design",
    "description": "Raw integrated-circuit design metadata and source files for the Superblue family, including compressed cell metadata, settings, instance lists, and original design documentation.",
    "local_paths": [
      "/data/zhishang/data/superblue/raw_data",
      "/data/zhishang/data/superblue"
    ],
    "existing_local_paths": [
      "/data/zhishang/data/superblue/raw_data",
      "/data/zhishang/data/superblue"
    ],
    "formats": [
      "json.gz",
      "csv",
      "pdf",
      "json",
      "pt"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "cataloged_only"
  },
  {
    "name": "Superblue Processed Graph Features",
    "slug": "superblue-processed-graph-features",
    "category": "asic_physical_design",
    "domain_module": "asic_physical_design",
    "description": "Processed circuit graph artifacts for Superblue designs, including bipartite graphs, hypergraph star expansions, node and net features, targets, partitions, and global metadata.",
    "local_paths": [
      "/data/zhishang/data/superblue/2023-03-06_data"
    ],
    "existing_local_paths": [
      "/data/zhishang/data/superblue/2023-03-06_data"
    ],
    "formats": [
      "pkl",
      "pkl.gz"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "loader_supported"
  },
  {
    "name": "DEHNN Netlist Dataset",
    "slug": "dehnn-netlist-dataset",
    "category": "asic_physical_design|fpga_physical_design",
    "domain_module": "asic_physical_design|fpga_physical_design",
    "description": "Netlist and hypergraph data used by DE-HNN, derived from RocketTile and Superblue-style flows. Includes raw-to-processed graph builders, PyG datasets, embeddings, and netlist-level tensors.",
    "local_paths": [
      "/data/zhishang/DEHNN/de_hnn_tx/data/mlcad/all_designs_netlist_data",
      "/data/zhishang/DEHNN/de_hnn_tx/data/ispd/ispd16_netlist_data"
    ],
    "existing_local_paths": [
      "/data/zhishang/DEHNN/de_hnn_tx/data/mlcad/all_designs_netlist_data",
      "/data/zhishang/DEHNN/de_hnn_tx/data/ispd/ispd16_netlist_data"
    ],
    "formats": [
      "pt",
      "pkl",
      "npy",
      "csv"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "loader_supported"
  },
  {
    "name": "CircuitNet Design Graphs",
    "slug": "circuitnet-design-graphs",
    "category": "asic_physical_design",
    "domain_module": "asic_physical_design",
    "description": "CircuitNet-derived design representations, verilog metadata, macro indices, feature tensors, explanation artifacts, and design-level training/evaluation inputs for congestion and related tasks.",
    "local_paths": [
      "/data/zhishang/CircuitNet/de_hnn_qm/new_data/processed_standardized"
    ],
    "existing_local_paths": [
      "/data/zhishang/CircuitNet/de_hnn_qm/new_data/processed_standardized"
    ],
    "formats": [
      "pt",
      "npy",
      "json"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "loader_supported"
  },
  {
    "name": "DREAMPlace ASIC Benchmarks",
    "slug": "dreamplace-asic-benchmarks",
    "category": "asic_physical_design",
    "domain_module": "asic_physical_design",
    "description": "Benchmark inputs for ASIC placement experiments used by DREAMPlace, including benchmark definitions and placement-oriented design data.",
    "local_paths": [
      "/data/zhishang/DREAMPlace/benchmarks"
    ],
    "existing_local_paths": [
      "/data/zhishang/DREAMPlace/benchmarks"
    ],
    "formats": [
      "py",
      "txt",
      "tcl",
      "json"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "cataloged_only"
  },
  {
    "name": "DREAMPlaceFPGA Benchmarks",
    "slug": "dreamplacefpga-benchmarks",
    "category": "fpga_physical_design",
    "domain_module": "fpga_physical_design",
    "description": "FPGA benchmark netlists and associated placement inputs used by DREAMPlaceFPGA, including IF netlists and sample ISPD benchmarks.",
    "local_paths": [
      "/data/zhishang/DREAMPlaceFPGA/benchmarks"
    ],
    "existing_local_paths": [
      "/data/zhishang/DREAMPlaceFPGA/benchmarks"
    ],
    "formats": [
      "netlist",
      "txt",
      "json"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "cataloged_only"
  },
  {
    "name": "ChipDiffusion Graph Dataset",
    "slug": "chipdiffusion-graph-dataset",
    "category": "asic_physical_design",
    "domain_module": "asic_physical_design",
    "description": "Graph-format circuit dataset and placement-related assets used by ChipDiffusion, including a PyG graph object, parsing configs, placement outputs, and evaluation bundles.",
    "local_paths": [
      "/data/zhishang/chipdiffusion/datasets",
      "/data/zhishang/chipdiffusion/placements",
      "/data/zhishang/chipdiffusion/custom_evaluation_results"
    ],
    "existing_local_paths": [
      "/data/zhishang/chipdiffusion/datasets",
      "/data/zhishang/chipdiffusion/placements",
      "/data/zhishang/chipdiffusion/custom_evaluation_results"
    ],
    "formats": [
      "pt",
      "yaml",
      "json",
      "csv",
      "pkl"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "loader_supported"
  },
  {
    "name": "UnifiedLearning ChipGen Logs",
    "slug": "unifiedlearning-chipgen-logs",
    "category": "experiment_logs",
    "domain_module": "",
    "description": "Merged ChipGen regression and ablation outputs tracked under the UnifiedLearning workspace. These are primarily experiment logs and not yet normalized into a reusable dataset loader.",
    "local_paths": [
      "/data/zhishang/UnifiedLearning/data/chipgen/test_logs",
      "/data/zhishang/UnifiedLearning/data"
    ],
    "existing_local_paths": [
      "/data/zhishang/UnifiedLearning/data/chipgen/test_logs",
      "/data/zhishang/UnifiedLearning/data"
    ],
    "formats": [
      "log",
      "csv"
    ],
    "suggested_datapoint_type": "unmapped",
    "status": "logs_only"
  },
  {
    "name": "Shortest Paths Terrain Patches",
    "slug": "shortest-paths-terrain-patches",
    "category": "terrain_shortest_path",
    "domain_module": "terrain_shortest_path",
    "description": "Large terrain patch collections for shortest-path distance approximation, including Norway, Holland, and Phil terrain subsets stored as compressed NumPy archives.",
    "local_paths": [
      "/data/zhishang/shortest-paths-nn/norway_patches",
      "/data/zhishang/shortest-paths-nn/holland_patches",
      "/data/zhishang/shortest-paths-nn/phil_patches",
      "/data/zhishang/shortest-paths-nn/dataset"
    ],
    "existing_local_paths": [
      "/data/zhishang/shortest-paths-nn/norway_patches",
      "/data/zhishang/shortest-paths-nn/holland_patches",
      "/data/zhishang/shortest-paths-nn/phil_patches",
      "/data/zhishang/shortest-paths-nn/dataset"
    ],
    "formats": [
      "npz",
      "py"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "loader_supported"
  },
  {
    "name": "Synthetic Graph Benchmarks",
    "slug": "synthetic-graph-benchmarks",
    "category": "synthetic_graph_reasoning",
    "domain_module": "synthetic_graph_reasoning",
    "description": "Small graph-learning benchmarks with stored labels, features, NetworkX graph objects, and PyG tensors. These include BA shapes, tree-grid, tree-cycles, and shortest-path synthetic graphs.",
    "local_paths": [
      "/data/zhishang/to_merge/gnn_agop/data/datasets",
      "/data/zhishang/to_merge/graph-learning-merged/data"
    ],
    "existing_local_paths": [
      "/data/zhishang/to_merge/gnn_agop/data/datasets",
      "/data/zhishang/to_merge/graph-learning-merged/data"
    ],
    "formats": [
      "pt",
      "json",
      "gpickle",
      "png"
    ],
    "suggested_datapoint_type": "Graph_datapoint",
    "status": "loader_supported"
  },
  {
    "name": "Mirrored GitHub Research Datasets",
    "slug": "mirrored-github-research-datasets",
    "category": "mirrors",
    "domain_module": "",
    "description": "Mirror copies of active research repositories, useful for provenance and synchronization but not treated as canonical storage for loader development.",
    "local_paths": [
      "/data/zhishang/github/DEHNN",
      "/data/zhishang/github/chipdiffusion",
      "/data/zhishang/github/UnifiedLearning",
      "/data/zhishang/github/Algorithmic-Intelligence-Ecosystem"
    ],
    "existing_local_paths": [
      "/data/zhishang/github/DEHNN",
      "/data/zhishang/github/chipdiffusion",
      "/data/zhishang/github/UnifiedLearning",
      "/data/zhishang/github/Algorithmic-Intelligence-Ecosystem"
    ],
    "formats": [
      "mixed"
    ],
    "suggested_datapoint_type": "unmapped",
    "status": "mirror_only"
  }
]