Datasets:
File size: 4,016 Bytes
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="1" loc="(200,120)" name="AND Gate"/>
<comp lib="1" loc="(200,190)" name="AND Gate"/>
<comp lib="1" loc="(200,260)" name="AND Gate"/>
<comp lib="1" loc="(200,330)" name="AND Gate"/>
<comp lib="1" loc="(200,50)" name="AND Gate"/>
<comp lib="8" loc="(108,35)" name="Text">
<a name="text" val="A"/>
</comp>
<comp lib="8" loc="(108,75)" name="Text">
<a name="text" val="B"/>
</comp>
<comp lib="8" loc="(109,106)" name="Text">
<a name="text" val="a"/>
</comp>
<comp lib="8" loc="(109,144)" name="Text">
<a name="text" val="b"/>
</comp>
<comp lib="8" loc="(110,175)" name="Text">
<a name="text" val="X"/>
</comp>
<comp lib="8" loc="(110,215)" name="Text">
<a name="text" val="Y"/>
</comp>
<comp lib="8" loc="(110,244)" name="Text">
<a name="text" val="x"/>
</comp>
<comp lib="8" loc="(110,284)" name="Text">
<a name="text" val="y"/>
</comp>
<comp lib="8" loc="(235,265)" name="Text">
<a name="text" val="f"/>
</comp>
<comp lib="8" loc="(237,123)" name="Text">
<a name="text" val="y"/>
</comp>
<comp lib="8" loc="(237,195)" name="Text">
<a name="text" val="F"/>
</comp>
<comp lib="8" loc="(237,56)" name="Text">
<a name="text" val="Y"/>
</comp>
<wire from="(120,100)" to="(150,100)"/>
<wire from="(120,140)" to="(150,140)"/>
<wire from="(120,170)" to="(150,170)"/>
<wire from="(120,210)" to="(150,210)"/>
<wire from="(120,240)" to="(150,240)"/>
<wire from="(120,280)" to="(150,280)"/>
<wire from="(120,30)" to="(150,30)"/>
<wire from="(120,310)" to="(150,310)"/>
<wire from="(120,350)" to="(150,350)"/>
<wire from="(120,70)" to="(150,70)"/>
<wire from="(200,120)" to="(230,120)"/>
<wire from="(200,190)" to="(230,190)"/>
<wire from="(200,260)" to="(230,260)"/>
<wire from="(200,330)" to="(230,330)"/>
<wire from="(200,50)" to="(230,50)"/>
</circuit>
</project>
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