| test_case,name,circuit,num_gates,num_2q_gates,ideal_Z_p00,ideal_Z_p01,ideal_Z_p10,ideal_Z_p11,mr_valid_ideal_Z,ideal_X_p00,ideal_X_p01,ideal_X_p10,ideal_X_p11,mr_valid_ideal_X |
| TC1,Base Combination,"H(q0) -> CX(q0,q1)",2,1,0.5,0.0,0.0,0.5,True,0.5,0.0,0.0,0.5,True |
| TC2,Logical Equivalence,"X(q0) -> H(q0) -> CX(q0,q1)",3,1,0.5,0.0,0.0,0.5,True,0.0,0.5,0.5,0.0,False |
| TC3,Single Phase Flip,"Z(q0) -> H(q0) -> CX(q0,q1)",3,1,0.5,0.0,0.0,0.5,True,0.5,0.0,0.0,0.5,True |
| TC4,Double Phase Flip,"Z(q0) -> Z(q1) -> H(q0) -> CX(q0,q1)",4,1,0.5,0.0,0.0,0.5,True,0.5,0.0,0.0,0.5,True |
| TC5,Gate Invalidation,"H(q0) -> CX(q0,q1) -> H(q0) -> H(q0)",4,1,0.5,0.0,0.0,0.5,True,0.5,0.0,0.0,0.5,True |
| TC6,Swap Operations,"H(q1) -> CX(q1,q0)",2,1,0.5,0.0,0.0,0.5,True,0.5,0.0,0.0,0.5,True |
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