| Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
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| Here is the netlist of the circuit
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| .subckt OPAMP20_Pin_3 gnda vdda vinn vinp vout
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| xm1 net15 vinp ib1 vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
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| xm0 net9 vinn ib1 vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
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| xm6 vout net15 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
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| xm5 net14 net9 gnda gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
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| xm4 net19 net9 gnda gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
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| xm3 net15 vb1 net14 gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
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| xm2 net9 vb1 net19 gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
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| C0 vout net14 'CAPACITOR_0'
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| R0 vdda vout 'RESISTOR_0'
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| V0 vb1 gnda 'VB1'
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| I0 vdda ib1 'IB1'
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| .ends OPAMP20_Pin_3
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| Here are the design parameters and range.
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| parameter_bounds:
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| L_P1:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_P1:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_P1:
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| min: 1
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| max: 100
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| type: int
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| L_P2:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_P2:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_P2:
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| min: 1
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| max: 100
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| type: int
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| L_N1:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N1:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N1:
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| min: 1
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| max: 100
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| type: int
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| L_N2:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N2:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N2:
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| min: 1
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| max: 100
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| type: int
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| L_N3:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N3:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N3:
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| min: 1
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| max: 100
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| type: int
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| L_N4:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N4:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N4:
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| min: 1
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| max: 100
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| type: int
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| L_N5:
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| min: 0.13
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| max: 1.0
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| type: real
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| W_N5:
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| min: 0.2
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| max: 10.0
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| type: real
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| M_N5:
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| min: 1
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| max: 100
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| type: int
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| C0:
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| min: 1.0
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| max: 100.0
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| type: real
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| R0:
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| min: 0.1
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| max: 1000.0
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| type: real
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| V1:
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| min: 0.0
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| max: 1.8
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| type: real
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| Ib1:
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| min: 1e-6
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| max: 4e-5
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| type: real
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| Here is the design target
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| PSRP_target = -76 # dB (from VDD @ 1 kHz)
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| PSRN_target = -95 # dB (from VSS @ 1 kHz)
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| TC_target = 2e-5 # 20 ppm/°C
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| Power_target = 3.0e-4 # W ≈0.30 mW
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| vos_target = 5e-4 # V ≈0.5 mV
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| cmrrdc_target = -88 # dB
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| dcgain_target = 100 # dB
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| GBW_target = 1.6e7 # Hz (~16 MHz with CL≈10 pF)
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| phase_margin_target = 65 # deg
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| sr_target = 2.2e7 # V/s ≈22 V/µs
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| settlingTime_target = 4.8e-7 # s (≈0.1–0.5% to 10 pF)
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| Provide your design parameter in this format
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| parameters:
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| L_P1:
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| W_P1:
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| M_P1:
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| L_P2:
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| W_P2:
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| M_P2:
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| L_N1:
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| W_N1:
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| M_N1:
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| L_N2:
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| W_N2:
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| M_N2:
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| L_N3:
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| W_N3:
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| M_N3:
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| L_N4:
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| W_N4:
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| M_N4:
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| L_N5:
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| W_N5:
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| M_N5:
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| C0:
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| R0:
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| V1:
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| Ib1: |
