Design the sizing and biasing voltage of an Op-Amp in SKY130nm (VDD 1.8 V) as shown in the provided circuit image.
Here is the netlist of the circuit
.subckt OPAMP8_Pin_3 gnda vdda vinn vinp vout
xm8 vout ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P1_L' w='P1_W*1' m='P1_M'
xm7 net24 ib1 net29 vdda sky130_fd_pr__pfet_01v8 l='P2_L' w='P2_W*1' m='P2_M'
xm6 net19 ib1 net35 vdda sky130_fd_pr__pfet_01v8 l='P3_L' w='P3_W*1' m='P3_M'
xm5 net29 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P4_L' w='P4_W*1' m='P4_M'
xm4 net35 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P5_L' w='P5_W*1' m='P5_M'
xm3 net11 ib1 net39 vdda sky130_fd_pr__pfet_01v8 l='P6_L' w='P6_W*1' m='P6_M'
xm2 ib1 ib1 net40 vdda sky130_fd_pr__pfet_01v8 l='P7_L' w='P7_W*1' m='P7_M'
xm1 net39 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P8_L' w='P8_W*1' m='P8_M'
xm0 net40 ib1 vdda vdda sky130_fd_pr__pfet_01v8 l='P9_L' w='P9_W*1' m='P9_M'
xm17 vout net24 gnda gnda sky130_fd_pr__nfet_01v8 l='N1_L' w='N1_W*1' m='N1_M'
xm16 net19 net19 gnda gnda sky130_fd_pr__nfet_01v8 l='N2_L' w='N2_W*1' m='N2_M'
xm15 net24 net19 gnda gnda sky130_fd_pr__nfet_01v8 l='N3_L' w='N3_W*1' m='N3_M'
xm14 net29 vinp net16 gnda sky130_fd_pr__nfet_01v8 l='N4_L' w='N4_W*1' m='N4_M'
xm13 ib1 vinn net16 gnda sky130_fd_pr__nfet_01v8 l='N5_L' w='N5_W*1' m='N5_M'
xm9 net37 net11 gnda gnda sky130_fd_pr__nfet_01v8 l='N6_L' w='N6_W*1' m='N6_M'
xm12 net11 net11 net38 gnda sky130_fd_pr__nfet_01v8 l='N7_L' w='N7_W*1' m='N7_M'
xm11 net16 net11 net37 gnda sky130_fd_pr__nfet_01v8 l='N8_L' w='N8_W*1' m='N8_M'
xm10 net38 net11 gnda gnda sky130_fd_pr__nfet_01v8 l='N9_L' w='N9_W*1' m='N9_M'
C0 vout net24 'CAPACITOR_0'
I0 ib1 gnda 'IB1'
.ends OPAMP8_Pin_3
Here are the design parameters and range. 
parameter_bounds:
  L_P1:
    min: 0.13
    max: 1.0
    type: real
  W_P1:
    min: 0.2
    max: 10.0
    type: real
  M_P1:
    min: 1
    max: 100
    type: int
  L_P2:
    min: 0.13
    max: 1.0
    type: real
  W_P2:
    min: 0.2
    max: 10.0
    type: real
  M_P2:
    min: 1
    max: 100
    type: int
  L_P3:
    min: 0.13
    max: 1.0
    type: real
  W_P3:
    min: 0.2
    max: 10.0
    type: real
  M_P3:
    min: 1
    max: 100
    type: int
  L_P4:
    min: 0.13
    max: 1.0
    type: real
  W_P4:
    min: 0.2
    max: 10.0
    type: real
  M_P4:
    min: 1
    max: 100
    type: int
  L_P5:
    min: 0.13
    max: 1.0
    type: real
  W_P5:
    min: 0.2
    max: 10.0
    type: real
  M_P5:
    min: 1
    max: 100
    type: int
  L_P6:
    min: 0.13
    max: 1.0
    type: real
  W_P6:
    min: 0.2
    max: 10.0
    type: real
  M_P6:
    min: 1
    max: 100
    type: int
  L_P7:
    min: 0.13
    max: 1.0
    type: real
  W_P7:
    min: 0.2
    max: 10.0
    type: real
  M_P7:
    min: 1
    max: 100
    type: int
  L_P8:
    min: 0.13
    max: 1.0
    type: real
  W_P8:
    min: 0.2
    max: 10.0
    type: real
  M_P8:
    min: 1
    max: 100
    type: int
  L_P9:
    min: 0.13
    max: 1.0
    type: real
  W_P9:
    min: 0.2
    max: 10.0
    type: real
  M_P9:
    min: 1
    max: 100
    type: int
  L_N1:
    min: 0.13
    max: 1.0
    type: real
  W_N1:
    min: 0.2
    max: 10.0
    type: real
  M_N1:
    min: 1
    max: 100
    type: int
  L_N2:
    min: 0.13
    max: 1.0
    type: real
  W_N2:
    min: 0.2
    max: 10.0
    type: real
  M_N2:
    min: 1
    max: 100
    type: int
  L_N3:
    min: 0.13
    max: 1.0
    type: real
  W_N3:
    min: 0.2
    max: 10.0
    type: real
  M_N3:
    min: 1
    max: 100
    type: int
  L_N4:
    min: 0.13
    max: 1.0
    type: real
  W_N4:
    min: 0.2
    max: 10.0
    type: real
  M_N4:
    min: 1
    max: 100
    type: int
  L_N5:
    min: 0.13
    max: 1.0
    type: real
  W_N5:
    min: 0.2
    max: 10.0
    type: real
  M_N5:
    min: 1
    max: 100
    type: int
  L_N6:
    min: 0.13
    max: 1.0
    type: real
  W_N6:
    min: 0.2
    max: 10.0
    type: real
  M_N6:
    min: 1
    max: 100
    type: int
  L_N7:
    min: 0.13
    max: 1.0
    type: real
  W_N7:
    min: 0.2
    max: 10.0
    type: real
  M_N7:
    min: 1
    max: 100
    type: int
  L_N8:
    min: 0.13
    max: 1.0
    type: real
  W_N8:
    min: 0.2
    max: 10.0
    type: real
  M_N8:
    min: 1
    max: 100
    type: int
  L_N9:
    min: 0.13
    max: 1.0
    type: real
  W_N9:
    min: 0.2
    max: 10.0
    type: real
  M_N9:
    min: 1
    max: 100
    type: int
  C0:
    min: 1.0
    max: 100.0
    type: real
  Ib1:
    min: 1e-6
    max: 4e-5
    type: real
Here is the design target
PSRP_target = -78          # dB @1 kHz (from VDD)
PSRN_target = -95          # dB @1 kHz (from VSS)
TC_target = 2e-5           # 20 ppm/°C
Power_target = 3e-4        # W  ≈0.30 mW
vos_target = 5e-4          # V  ≈0.5 mV
cmrrdc_target = -88        # dB
dcgain_target = 102        # dB
GBW_target = 1.2e7         # Hz  (~12 MHz with 10 pF)
phase_margin_target = 60   # deg
sr_target = 1.5e7          # V/s  ≈15 V/µs
settlingTime_target = 6e-7 # s  (~0.1–0.5% to 10 pF)
Provide your design parameter in this format
parameters:
  L_P1:
  W_P1:
  M_P1:
  L_P2:
  W_P2:
  M_P2:
  L_P3:
  W_P3:
  M_P3:
  L_P4:
  W_P4:
  M_P4:
  L_P5:
  W_P5:
  M_P5:
  L_P6:
  W_P6:
  M_P6:
  L_P7:
  W_P7:
  M_P7:
  L_P8:
  W_P8:
  M_P8:
  L_P9:
  W_P9:
  M_P9:
  L_N1:
  W_N1:
  M_N1:
  L_N2:
  W_N2:
  M_N2:
  L_N3:
  W_N3:
  M_N3:
  L_N4:
  W_N4:
  M_N4:
  L_N5:
  W_N5:
  M_N5:
  L_N6:
  W_N6:
  M_N6:
  L_N7:
  W_N7:
  M_N7:
  L_N8:
  W_N8:
  M_N8:
  L_N9:
  W_N9:
  M_N9:
  C0:
  Ib1: