hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /1 /fetch.stat.0.out
| /* -*- Mode: c -*- */ | |
| #################################################################################################### | |
| Core 0 | |
| #################################################################################################### | |
| Cumulative: Cycles: 40347914 Instructions: 9981748 IPC: 0.24739 | |
| Periodic: Cycles: 40347914 Instructions: 9981748 IPC: 0.24739 | |
| MISS_WAIT_TIME 140363581874 140363581874 | |
| ICACHE_STAGE_MISS 4454 4454 | |
| ICACHE_CYCLE 40347914 40347914 | |
| TCACHE_CYCLE 0 0 | |
| ICACHE_SERVING_CYCLE_ON_PATH 95241 95241 | |
| ICACHE_SERVING_CYCLE_OFF_PATH 125102 125102 | |
| UCACHE_SERVING_CYCLE_ON_PATH 39423166 39423166 | |
| UCACHE_SERVING_CYCLE_OFF_PATH 301095 301095 | |
| ICACHE_CYCLE_ONPATH 39847773 98.760% 39847773 98.760% | |
| ICACHE_CYCLE_OFFPATH 500141 1.240% 500141 1.240% | |
| 40347914 100.000% 40347914 100.000% | |
| 0.01 0.11 0.01 0.11 | |
| FETCH_ON_PATH 39860215 98.791% 39860215 98.791% | |
| FETCH_OFF_PATH 487699 1.209% 487699 1.209% | |
| 40347914 100.000% 40347914 100.000% | |
| 0.01 0.11 0.01 0.11 | |
| FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% | |
| FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| INST_LOST_FETCH 10583034 2.970% 10583034 2.970% | |
| INST_LOST_OFF_PATH 1247907 0.350% 1247907 0.350% | |
| INST_LOST_FULL_WINDOW 901038 0.253% 901038 0.253% | |
| INST_LOST_ROB_STALL_OTHER 194591528 54.607% 194591528 54.607% | |
| INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 104888716 29.434% 104888716 29.434% | |
| INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 1600462 0.449% 1600462 0.449% | |
| INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% | |
| INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_DONT 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_FT_UNAVAILABLE 151603 0.043% 151603 0.043% | |
| INST_LOST_BREAK_ICACHE_STAGE_RESTEER 4767 0.001% 4767 0.001% | |
| INST_LOST_BREAK_ICACHE_MISS_REQ_SUCCESS 19942 0.006% 19942 0.006% | |
| INST_LOST_BREAK_ICACHE_MISS_REQ_FAILURE 83785 0.024% 83785 0.024% | |
| INST_LOST_BREAK_ICACHE_WAIT_FOR_MISS 2059244 0.578% 2059244 0.578% | |
| INST_LOST_BREAK_ICACHE_STALLED 150970 0.042% 150970 0.042% | |
| INST_LOST_BREAK_ICACHE_TO_UOP_CACHE_SWITCH 33108 0.009% 33108 0.009% | |
| INST_LOST_BREAK_ICACHE_READ_LIMIT 43790 0.012% 43790 0.012% | |
| INST_LOST_BREAK_ICACHE_ISSUE_WIDTH 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_UOP_CACHE_STALLED 36411450 10.218% 36411450 10.218% | |
| INST_LOST_BREAK_UOP_CACHE_TO_ICACHE_SWITCH 39816 0.011% 39816 0.011% | |
| INST_LOST_BREAK_UOP_CACHE_READ_LIMIT 3535430 0.992% 3535430 0.992% | |
| INST_LOST_BREAK_UOP_CACHE_ISSUE_WIDTH 0 0.000% 0 0.000% | |
| 356346590 100.000% 356346590 100.000% | |
| 6.65 5.99 6.65 5.99 | |
| INST_LOST_TOTAL 321542518 321542518 | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_NOT_PREFETCHED 793800 45.606% 793800 45.606% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH 0 0.000% 0 0.000% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP 0 0.000% 0 0.000% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_MSHR_HIT_PREF_OFFPATH 32010 1.839% 32010 1.839% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_MSHR_HIT_PREF_ONPATH 914766 52.555% 914766 52.555% | |
| 1740576 100.000% 1740576 100.000% | |
| 2.16 2.06 2.16 2.06 | |
| FETCH_0_OPS 401881 0.996% 401881 0.996% | |
| FETCH_1_OPS 17956 0.045% 17956 0.045% | |
| FETCH_2_OPS 4890862 12.122% 4890862 12.122% | |
| FETCH_3_OPS 70778 0.175% 70778 0.175% | |
| FETCH_4_OPS 91427 0.227% 91427 0.227% | |
| FETCH_5_OPS 114988 0.285% 114988 0.285% | |
| FETCH_6_OPS 4820934 11.948% 4820934 11.948% | |
| FETCH_7_OPS 382357 0.948% 382357 0.948% | |
| FETCH_8_OPS 29556731 73.255% 29556731 73.255% | |
| FETCH_9_OPS 0 0.000% 0 0.000% | |
| FETCH_10_OPS 0 0.000% 0 0.000% | |
| FETCH_11_OPS 0 0.000% 0 0.000% | |
| FETCH_12_OPS 0 0.000% 0 0.000% | |
| FETCH_13_OPS 0 0.000% 0 0.000% | |
| FETCH_14_OPS 0 0.000% 0 0.000% | |
| FETCH_15_OPS 0 0.000% 0 0.000% | |
| FETCH_16_OPS 0 0.000% 0 0.000% | |
| 40347914 100.000% 40347914 100.000% | |
| 6.92 1.99 6.92 1.99 | |
| ST_BREAK_DONT 0 0.000% 0 0.000% | |
| ST_BREAK_FT_UNAVAILABLE 25760 0.064% 25760 0.064% | |
| ST_BREAK_ICACHE_STAGE_RESTEER 1214 0.003% 1214 0.003% | |
| ST_BREAK_ICACHE_MISS_REQ_SUCCESS 4454 0.011% 4454 0.011% | |
| ST_BREAK_ICACHE_MISS_REQ_FAILURE 14022 0.035% 14022 0.035% | |
| ST_BREAK_ICACHE_WAIT_FOR_MISS 343218 0.851% 343218 0.851% | |
| ST_BREAK_ICACHE_STALLED 101161 0.251% 101161 0.251% | |
| ST_BREAK_ICACHE_TO_UOP_CACHE_SWITCH 10634 0.026% 10634 0.026% | |
| ST_BREAK_ICACHE_READ_LIMIT 16075 0.040% 16075 0.040% | |
| ST_BREAK_ICACHE_ISSUE_WIDTH 105527 0.262% 105527 0.262% | |
| ST_BREAK_UOP_CACHE_STALLED 37891001 93.911% 37891001 93.911% | |
| ST_BREAK_UOP_CACHE_TO_ICACHE_SWITCH 9006 0.022% 9006 0.022% | |
| ST_BREAK_UOP_CACHE_READ_LIMIT 923346 2.288% 923346 2.288% | |
| ST_BREAK_UOP_CACHE_ISSUE_WIDTH 902496 2.237% 902496 2.237% | |
| 40347914 100.000% 40347914 100.000% | |
| 10.05 1.70 10.05 1.70 | |
| ORACLE_ON_PATH_INST 10583034 89.452% 10583034 89.452% | |
| ORACLE_OFF_PATH_INST 1247907 10.548% 1247907 10.548% | |
| 11830941 100.000% 11830941 100.000% | |
| 0.11 0.29 0.11 0.29 | |
| ORACLE_ON_PATH_INST_MEM 3349683 28.313% 3349683 28.313% | |
| ORACLE_ON_PATH_INST_NOTMEM 7233351 61.139% 7233351 61.139% | |
| ORACLE_OFF_PATH_INST_MEM 343994 2.908% 343994 2.908% | |
| ORACLE_OFF_PATH_INST_NOTMEM 903913 7.640% 903913 7.640% | |
| 11830941 100.000% 11830941 100.000% | |
| 0.90 0.66 0.90 0.66 | |
| ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 | |
| FETCH_ALL_INST 11830941 11830941 | |
| EXEC_ALL_INST 10865062 10865062 | |
| RET_ALL_INST 10582823 10582823 | |
| EXEC_ON_PATH_INST 10582930 97.403% 10582930 97.403% | |
| EXEC_OFF_PATH_INST 282132 2.597% 282132 2.597% | |
| 10865062 100.000% 10865062 100.000% | |
| 0.03 0.16 0.03 0.16 | |
| EXEC_ON_PATH_INST_MEM 3349639 30.829% 3349639 30.829% | |
| EXEC_ON_PATH_INST_NOTMEM 7233291 66.574% 7233291 66.574% | |
| EXEC_OFF_PATH_INST_MEM 65894 0.606% 65894 0.606% | |
| EXEC_OFF_PATH_INST_NOTMEM 216238 1.990% 216238 1.990% | |
| 10865062 100.000% 10865062 100.000% | |
| 0.74 0.41 0.74 0.41 | |
| EXEC_RA_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_INST 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% | |
| EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% | |
| EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_THROTTLE_CYCLE 0 0 | |
| FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% | |
| FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% | |
| FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_TH_ADJUST__0 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__1 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__2 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__3 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__4 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__5 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__6 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__7 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__8 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__9 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__MAX 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_TH_ADJUST_UP 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 | |
| LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_RESTEER_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_RESTEER_RECOVER_AT_EXEC_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_EXEC_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_UOC_IC_SWITCH 0 0 | |