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hpca2027-database-validated-traces-20260711

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hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /1 /memory.stat.0.out
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/* -*- Mode: c -*- */
####################################################################################################
Core 0
####################################################################################################
Cumulative: Cycles: 40347914 Instructions: 9981748 IPC: 0.24739
Periodic: Cycles: 40347914 Instructions: 9981748 IPC: 0.24739
ICACHE_MISS 4475 5.993% 4475 5.993%
ICACHE_HIT 70191 94.007% 70191 94.007%
 74666 100.000% 74666 100.000%
 0.94 0.91 0.94 0.91
ICACHE_MISS_ONPATH 2649 59.196% 2649 59.196%
ICACHE_MISS_OFFPATH 1826 40.804% 1826 40.804%
 4475 100.000% 4475 100.000%
 0.41 0.46 0.41 0.46
ICACHE_MISS_NOT_PREFETCHED 710 17.453% 710 17.453%
ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH 0 0.000% 0 0.000%
ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP 0 0.000% 0 0.000%
ICACHE_MISS_MSHR_HIT_PREFETCHED_OFFPATH 1471 36.160% 1471 36.160%
ICACHE_MISS_MSHR_HIT_PREFETCHED_ONPATH 1887 46.386% 1887 46.386%
 4068 100.000% 4068 100.000%
 2.94 2.13 2.94 2.13
ICACHE_HIT_ONPATH 43393 61.821% 43393 61.821%
ICACHE_HIT_OFFPATH 26798 38.179% 26798 38.179%
 70191 100.000% 70191 100.000%
 0.38 0.45 0.38 0.45
ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan%
ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan%
ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_HIT_BY_FDIP_ONPATH 0 -nan% 0 -nan%
ICACHE_HIT_BY_FDIP_OFFPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_MISS_MSHR_HIT_BY_FDIP_ONPATH 1558 46.397% 1558 46.397%
ICACHE_MISS_MSHR_HIT_BY_FDIP_OFFPATH 1800 53.603% 1800 53.603%
 3358 100.000% 3358 100.000%
 0.54 0.52 0.54 0.52
ICACHE_HIT_ONPATH_BY_FDIP 0 0.000% 0 0.000%
ICACHE_HIT_OFFPATH_BY_FDIP 0 0.000% 0 0.000%
ICACHE_MISS_MSHR_HIT_ONPATH_BY_FDIP 1939 43.330% 1939 43.330%
ICACHE_MISS_MSHR_HIT_OFFPATH_BY_FDIP 1419 31.709% 1419 31.709%
ICACHE_MISS_TOO_EARLY_ONPATH 0 0.000% 0 0.000%
ICACHE_MISS_TOO_EARLY_OFFPATH 0 0.000% 0 0.000%
ICACHE_MISS_NOT_PREFETCHED_ONPATH 710 15.866% 710 15.866%
ICACHE_MISS_NOT_PREFETCHED_OFFPATH 407 9.095% 407 9.095%
 4475 100.000% 4475 100.000%
 3.41 2.05 3.41 2.05
ICACHE_MISS_MEM_REQ_FAIL_ON_PATH 9244 92.867% 9244 92.867%
ICACHE_MISS_MEM_REQ_SUCCESS_ON_PATH 710 7.133% 710 7.133%
 9954 100.000% 9954 100.000%
 0.07 0.25 0.07 0.25
ICACHE_UNIQUE_MISSED_LINES 1939 1939
ICACHE_UNIQUE_HIT_LINES 0 0
ICACHE_OVERTAKE_FDIP 0 0
FT_UOP_CACHE_HIT_ON_PATH 1954745 97.699% 1954745 97.699%
FT_UOP_CACHE_MISS_ICACHE_HIT_ON_PATH 43393 2.169% 43393 2.169%
FT_UOP_CACHE_MISS_ICACHE_MISS_ON_PATH 2649 0.132% 2649 0.132%
 2000787 100.000% 2000787 100.000%
 0.02 0.16 0.02 0.16
FT_UOP_CACHE_HIT_OFF_PATH 109937 79.342% 109937 79.342%
FT_UOP_CACHE_MISS_ICACHE_HIT_OFF_PATH 26798 19.340% 26798 19.340%
FT_UOP_CACHE_MISS_ICACHE_MISS_OFF_PATH 1826 1.318% 1826 1.318%
 138561 100.000% 138561 100.000%
 0.22 0.40 0.22 0.40
UOPS_SERVED_BY_ICACHE_ON_PATH 340777 3.220% 340777 3.220%
UOPS_SERVED_BY_UOP_CACHE_ON_PATH 10242257 96.780% 10242257 96.780%
 10583034 100.000% 10583034 100.000%
 0.97 0.95 0.97 0.95
UOPS_SERVED_BY_ICACHE_OFF_PATH 385444 30.887% 385444 30.887%
UOPS_SERVED_BY_UOP_CACHE_OFF_PATH 862463 69.113% 862463 69.113%
 1247907 100.000% 1247907 100.000%
 0.69 0.63 0.69 0.63
UOP_CACHE_FT_INSERTED_ONPATH_USED_ONPATH 10559 10559
UOP_CACHE_FT_INSERTED_OFFPATH_USED_ONPATH 6459 6459
UOP_CACHE_LINE_INSERTED_ONPATH_USED_ONPATH 16605 16605
UOP_CACHE_LINE_INSERTED_OFFPATH_USED_ONPATH 9861 9861
UOP_CACHE_PREFETCH 0 0
UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_ON_PATH 5538 12.403% 5538 12.403%
UOP_CACHE_FT_INSERT_SUCCEEDED_ON_PATH 39114 87.597% 39114 87.597%
 44652 100.000% 44652 100.000%
 2.88 2.71 2.88 2.71
UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_OFF_PATH 1183 6.161% 1183 6.161%
UOP_CACHE_FT_INSERT_SUCCEEDED_OFF_PATH 18018 93.839% 18018 93.839%
 19201 100.000% 19201 100.000%
 2.94 2.86 2.94 2.86
UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_ON_PATH 7192 10.516% 7192 10.516%
UOP_CACHE_LINE_INSERT_SUCCEEDED_ON_PATH 61196 89.484% 61196 89.484%
 68388 100.000% 68388 100.000%
 2.89 2.76 2.89 2.76
UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_OFF_PATH 1427 3.742% 1427 3.742%
UOP_CACHE_LINE_INSERT_SUCCEEDED_OFF_PATH 36708 96.258% 36708 96.258%
 38135 100.000% 38135 100.000%
 2.96 2.91 2.96 2.91
UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_RESTEERED 0 -nan% 0 -nan%
UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_CORRECT_PRED 0 -nan% 0 -nan%
UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_RESTEERED 0 -nan% 0 -nan%
UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_CORRECT_PRED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
UOP_CACHE_FT_LINES_1_ON_PATH 27350 61.251% 27350 61.251%
UOP_CACHE_FT_LINES_2_ON_PATH 11730 26.270% 11730 26.270%
UOP_CACHE_FT_LINES_3_ON_PATH 4713 10.555% 4713 10.555%
UOP_CACHE_FT_LINES_4_ON_PATH 856 1.917% 856 1.917%
UOP_CACHE_FT_LINES_5_ON_PATH 3 0.007% 3 0.007%
UOP_CACHE_FT_LINES_6_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_7_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_8_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_9_AND_MORE_ON_PATH 0 0.000% 0 0.000%
 44652 100.000% 44652 100.000%
 0.53 0.63 0.53 0.63
UOP_CACHE_FT_LINES_1_OFF_PATH 7799 40.618% 7799 40.618%
UOP_CACHE_FT_LINES_2_OFF_PATH 4048 21.082% 4048 21.082%
UOP_CACHE_FT_LINES_3_OFF_PATH 7178 37.383% 7178 37.383%
UOP_CACHE_FT_LINES_4_OFF_PATH 174 0.906% 174 0.906%
UOP_CACHE_FT_LINES_5_OFF_PATH 2 0.010% 2 0.010%
UOP_CACHE_FT_LINES_6_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_7_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_8_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_9_AND_MORE_OFF_PATH 0 0.000% 0 0.000%
 19201 100.000% 19201 100.000%
 0.99 0.65 0.99 0.65
UOP_CACHE_PREFETCH_PW_LENGTH_1 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_2 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_3 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_4 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_5 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_6 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_7 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_8 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_9 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_10 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_11 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_12 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_13 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_14 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_15 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_16 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_17 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_18 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_19 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_20 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_21 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_22 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_23 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_24 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DCACHE_MISS 2331168 69.595% 2331168 69.595%
DCACHE_ST_BUFFER_HIT 976 0.029% 976 0.029%
DCACHE_HIT 1017491 30.376% 1017491 30.376%
 3349635 100.000% 3349635 100.000%
 0.61 0.84 0.61 0.84
DCACHE_MISS_ONPATH 2331168 99.861% 2331168 99.861%
DCACHE_MISS_OFFPATH 3244 0.139% 3244 0.139%
 2334412 100.000% 2334412 100.000%
 0.00 0.04 0.00 0.04
DCACHE_ST_BUFFER_HIT_ONPATH 976 88.246% 976 88.246%
DCACHE_ST_BUFFER_HIT_OFFPATH 130 11.754% 130 11.754%
 1106 100.000% 1106 100.000%
 0.12 0.31 0.12 0.31
DCACHE_HIT_ONPATH 1017491 94.696% 1017491 94.696%
DCACHE_HIT_OFFPATH 56992 5.304% 56992 5.304%
 1074483 100.000% 1074483 100.000%
 0.05 0.22 0.05 0.22
DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 408 0.040% 408 0.040%
DCACHE_HIT_ONPATH_SAT_BY_ONPATH 1017083 99.960% 1017083 99.960%
 1017491 100.000% 1017491 100.000%
 1.00 1.00 1.00 1.00
DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 1609 2.823% 1609 2.823%
DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 55383 97.177% 55383 97.177%
 56992 100.000% 56992 100.000%
 0.97 0.96 0.97 0.96
DCACHE_MISS_LD 56645 2.430% 56645 2.430%
DCACHE_MISS_ST 2274523 97.570% 2274523 97.570%
 2331168 100.000% 2331168 100.000%
 0.98 0.96 0.98 0.96
DCACHE_MISS_LD_ONPATH 56645 95.940% 56645 95.940%
DCACHE_MISS_LD_OFFPATH 2397 4.060% 2397 4.060%
 59042 100.000% 59042 100.000%
 0.04 0.19 0.04 0.19
DCACHE_MISS_ST_ONPATH 2274523 99.963% 2274523 99.963%
DCACHE_MISS_ST_OFFPATH 847 0.037% 847 0.037%
 2275370 100.000% 2275370 100.000%
 0.00 0.02 0.00 0.02
DCACHE_MISS_WAITMEM 47725159 47725159
MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan%
MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan%
MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
SHADOW_ROW_BUFFER_HITS 0 0
SHADOW_ROW_HIT_STALL_TIME 0 0
CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL6_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL7_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CHANNEL_IDLE_DESPITE_READY_CMD 0 0
MEM_NUM_TOTAL_BUS_CYCLES 0 0
MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CORE_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
RAMULATOR_QUEUE_ENQUEUED 0 0
RAMULATOR_QUEUE_FULL 0 0
BUS_DEMAND_ACCESS 1144770 1144770
BUS_PREF_ACCESS 72684 72684
BUS_ACCESS 0 0
L1_DEMAND_ACCESS 4685106 4685106
L1_PREF_ACCESS 152249 152249
L1_ACCESS 3567730 3567730
MLC_DEMAND_ACCESS 2369042 2369042
MLC_PREF_ACCESS 27726 27726
MLC_ACCESS 2396768 2396768
L1_HIT 4700 0.391% 4700 0.391%
L1_MISS 1196138 99.609% 1196138 99.609%
 1200838 100.000% 1200838 100.000%
 1.00 0.99 1.00 0.99
L1_HIT_ALL 1198392 49.538% 1198392 49.538%
L1_MISS_ALL 1220765 50.462% 1220765 50.462%
 2419157 100.000% 2419157 100.000%
 0.50 0.50 0.50 0.50
L1_DEMAND_MISS 1134636 92.945% 1134636 92.945%
L1_PREF_REQ_MISS 72684 5.954% 72684 5.954%
L1_WB_MISS 13445 1.101% 13445 1.101%
 1220765 100.000% 1220765 100.000%
 0.08 0.30 0.08 0.30
L1_DEMAND_HIT 4693 0.392% 4693 0.392%
L1_PREF_REQ_HIT 3269 0.273% 3269 0.273%
L1_WB_HIT 1190430 99.336% 1190430 99.336%
 1198392 100.000% 1198392 100.000%
 1.99 1.98 1.99 1.98
L1_MISS_ONPATH 1195970 99.986% 1195970 99.986%
L1_MISS_OFFPATH 168 0.014% 168 0.014%
 1196138 100.000% 1196138 100.000%
 0.00 0.01 0.00 0.01
L1_MISS_ALL_ONPATH 1210577 99.165% 1210577 99.165%
L1_MISS_ALL_OFFPATH 10188 0.835% 10188 0.835%
 1220765 100.000% 1220765 100.000%
 0.01 0.09 0.01 0.09
L1_HIT_ONPATH 4688 99.745% 4688 99.745%
L1_HIT_OFFPATH 12 0.255% 12 0.255%
 4700 100.000% 4700 100.000%
 0.00 0.05 0.00 0.05
L1_HIT_ALL_ONPATH 1198313 99.993% 1198313 99.993%
L1_HIT_ALL_OFFPATH 79 0.007% 79 0.007%
 1198392 100.000% 1198392 100.000%
 0.00 0.01 0.00 0.01
L1_HIT_ONPATH_SAT_BY_OFFPATH 15 0.001% 15 0.001%
L1_HIT_ONPATH_SAT_BY_ONPATH 1198298 99.999% 1198298 99.999%
 1198313 100.000% 1198313 100.000%
 1.00 1.00 1.00 1.00
L1_HIT_OFFPATH_SAT_BY_OFFPATH 70 88.608% 70 88.608%
L1_HIT_OFFPATH_SAT_BY_ONPATH 9 11.392% 9 11.392%
 79 100.000% 79 100.000%
 0.11 0.30 0.11 0.30
L1_HIT_ONPATH_IFETCH_SAT_BY_OFFPATH 10 90.909% 10 90.909%
L1_HIT_ONPATH_IFETCH_SAT_BY_ONPATH 1 9.091% 1 9.091%
 11 100.000% 11 100.000%
 0.09 0.29 0.09 0.29
L1_HIT_ONPATH_DATA_SAT_BY_OFFPATH 0 0.000% 0 0.000%
L1_HIT_ONPATH_DATA_SAT_BY_ONPATH 4677 100.000% 4677 100.000%
 4677 100.000% 4677 100.000%
 1.00 1.00 1.00 1.00
L1_FILL_OFFPATH_IFETCH 108 108
L1_FILL_OFFPATH_DATA 37 37
L1_FILL_OFFPATH 10165 10165
L1_USE_OFFPATH_IFETCH 10 0.0926 10 0.0926
L1_USE_OFFPATH_DATA 16 0.4324 16 0.4324
L1_USE_OFFPATH 31 0.0030 31 0.0030
JUST_L1_USE_OFFPATH 19 0.0019 19 0.0019
L1_FILL_ONPATH_IFETCH 592 592
L1_FILL_ONPATH_DATA 1196626 1196626
L1_FILL_ONPATH 1197332 1197332
L1_USE_ONPATH_IFETCH 1 0.0017 1 0.0017
L1_USE_ONPATH_DATA 4677 0.0039 4677 0.0039
L1_USE_ONPATH 1198298 1.0008 1198298 1.0008
L1_CYCLE 40347914 40347914
L1_LINES 1314179522263 32571.1887 1314179522263 32571.1887
MLC_HIT 23455 2.017% 23455 2.017%
MLC_MISS 1139287 97.983% 1139287 97.983%
 1162742 100.000% 1162742 100.000%
 0.98 0.97 0.98 0.97
MLC_HIT_ALL 1247052 52.034% 1247052 52.034%
MLC_MISS_ALL 1149540 47.966% 1149540 47.966%
 2396592 100.000% 2396592 100.000%
 0.48 0.49 0.48 0.49
MLC_DEMAND_MISS 1139287 99.108% 1139287 99.108%
MLC_PREF_REQ_MISS 0 0.000% 0 0.000%
MLC_WB_MISS 10253 0.892% 10253 0.892%
 1149540 100.000% 1149540 100.000%
 0.02 0.19 0.02 0.19
MLC_DEMAND_HIT 23455 1.881% 23455 1.881%
MLC_PREF_REQ_HIT 0 0.000% 0 0.000%
MLC_WB_HIT 1223597 98.119% 1223597 98.119%
 1247052 100.000% 1247052 100.000%
 1.96 1.94 1.96 1.94
MLC_MISS_ONPATH 1139083 99.982% 1139083 99.982%
MLC_MISS_OFFPATH 204 0.018% 204 0.018%
 1139287 100.000% 1139287 100.000%
 0.00 0.01 0.00 0.01
MLC_MISS_ALL_ONPATH 1139210 99.101% 1139210 99.101%
MLC_MISS_ALL_OFFPATH 10330 0.899% 10330 0.899%
 1149540 100.000% 1149540 100.000%
 0.01 0.09 0.01 0.09
MLC_HIT_ONPATH 21979 93.707% 21979 93.707%
MLC_HIT_OFFPATH 1476 6.293% 1476 6.293%
 23455 100.000% 23455 100.000%
 0.06 0.24 0.06 0.24
MLC_HIT_ALL_ONPATH 1232717 98.850% 1232717 98.850%
MLC_HIT_ALL_OFFPATH 14335 1.150% 14335 1.150%
 1247052 100.000% 1247052 100.000%
 0.01 0.11 0.01 0.11
L1_QUEUE_OCCUPANCY 90740461 2.2490 90740461 2.2490
MLC_QUEUE_OCCUPANCY 88322332 2.1890 88322332 2.1890
DCACHE_FILL_PORT_UNAVAILABLE_ONPATH 599507 599507
DCACHE_FILL_PORT_UNAVAILABLE_OFFPATH 103 103
DCACHE_READ_PORT_UNAVAILABLE_ONPATH 28273554 28273554
DCACHE_READ_PORT_UNAVAILABLE_OFFPATH 8680 8680
DCACHE_FILL_OFFPATH 982 982
DCACHE_USE_OFFPATH 408 0.4155 408 0.4155
DCACHE_FILL_ONPATH 1221443 1221443
DCACHE_USE_ONPATH 1017083 0.8327 1017083 0.8327
ICACHE_FILL_OFFPATH 23587 23587
ICACHE_USE_OFFPATH 0 0.0000 0 0.0000
ICACHE_FILL_ONPATH 5141 5141
ICACHE_USE_ONPATH 0 0.0000 0 0.0000
REQBUF_CREATE_ONPATH 4820433 4820433
REQBUF_ONPATH_MATCH_OFFPATH 167 0.0000 167 0.0000
REQBUF_CREATE_ONPATH_DATA 1158656 1158656
REQBUF_ONPATH_MATCH_OFFPATH_DATA 52 0.0000 52 0.0000
REQBUF_CREATE_ONPATH_IFETCH 710 710
REQBUF_ONPATH_MATCH_OFFPATH_IFETCH 115 0.1620 115 0.1620
REQBUF_CREATE_OFFPATH 24862 24862
ONPATH_KICKED_OUT_OFFPATH 0 0
ONPATH_KICKED_OUT_PREFETCH 0 0
DIST_ICACHE_FILL_OFFPATH_USED 0 0.000% 0 0.000%
DIST_ICACHE_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_ICACHE_FILL_ONPATH_PARTIAL 115 2.237% 115 2.237%
DIST_ICACHE_FILL_ONPATH 5026 97.763% 5026 97.763%
 5141 100.000% 5141 100.000%
 2.98 2.95 2.98 2.95
DIST_DCACHE_FILL_OFFPATH_USED 408 0.033% 408 0.033%
DIST_DCACHE_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_DCACHE_FILL_ONPATH_PARTIAL 52 0.004% 52 0.004%
DIST_DCACHE_FILL_ONPATH 1221391 99.962% 1221391 99.962%
 1221851 100.000% 1221851 100.000%
 3.00 3.00 3.00 3.00
DIST_L1_FILL_OFFPATH_USED 31 0.003% 31 0.003%
DIST_L1_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_L1_FILL_ONPATH_PARTIAL 100 0.008% 100 0.008%
DIST_L1_FILL_ONPATH 1197232 99.989% 1197232 99.989%
 1197363 100.000% 1197363 100.000%
 3.00 3.00 3.00 3.00
DIST_JUST_L1_FILL_OFFPATH_USED 0 -nan% 0 -nan%
DIST_JUST_L1_FILL_OFFPATH_NOTUSED 0 -nan% 0 -nan%
DIST_JUST_L1_FILL_ONPATH_PARTIAL 0 -nan% 0 -nan%
DIST_JUST_L1_FILL_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_REQBUF_OFFPATH_USED 590 0.048% 590 0.048%
DIST_REQBUF_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_REQBUF_ONPATH 1239509 99.952% 1239509 99.952%
 1240099 100.000% 1240099 100.000%
 2.00 2.00 2.00 2.00
DIST2_REQBUF_OFFPATH_USED_PARTIAL 167 0.013% 167 0.013%
DIST2_REQBUF_OFFPATH_USED_FULL 423 0.034% 423 0.034%
DIST2_REQBUF_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST2_REQBUF_ONPATH 1239509 99.952% 1239509 99.952%
 1240099 100.000% 1240099 100.000%
 3.00 3.00 3.00 3.00
DIST_ICACHE_FILL 28728 28728
DIST_DCACHE_FILL 1222425 1222425
DIST_L1_FILL 1207497 1207497
DIST_USED_OFFPATH_ICACHE 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_ICACHE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_USED_OFFPATH_DCACHE 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_DCACHE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_USED_OFFPATH_L1 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_L1 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_USED_OFFPATH_JUST_L1 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_JUST_L1 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_ICACHE_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_ICACHE_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_ICACHE_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_DCACHE_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_DCACHE_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_DCACHE_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_L1_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_L1_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_L1_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_JUST_L1_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_JUST_L1_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_JUST_L1_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_MISS_ONPATH_IFETCH 544 0.048% 544 0.048%
MLC_MISS_ONPATH_DFETCH 4199 0.369% 4199 0.369%
MLC_MISS_ONPATH_DSTORE 1134340 99.573% 1134340 99.573%
MLC_MISS_ONPATH_IPRF 0 0.000% 0 0.000%
MLC_MISS_ONPATH_DPRF 0 0.000% 0 0.000%
MLC_MISS_ONPATH_WB 119 0.010% 119 0.010%
MLC_MISS_ONPATH_WB_NODIRTY 8 0.001% 8 0.001%
 1139210 100.000% 1139210 100.000%
 2.00 0.07 2.00 0.07
MLC_MISS_OFFPATH_IFETCH 128 1.239% 128 1.239%
MLC_MISS_OFFPATH_DFETCH 57 0.552% 57 0.552%
MLC_MISS_OFFPATH_DSTORE 19 0.184% 19 0.184%
MLC_MISS_OFFPATH_IPRF 0 0.000% 0 0.000%
MLC_MISS_OFFPATH_DPRF 0 0.000% 0 0.000%
MLC_MISS_OFFPATH_WB 10126 98.025% 10126 98.025%
MLC_MISS_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 10330 100.000% 10330 100.000%
 4.91 0.33 4.91 0.33
MLC_HIT_ONPATH_IFETCH 1840 0.149% 1840 0.149%
MLC_HIT_ONPATH_DFETCH 10653 0.864% 10653 0.864%
MLC_HIT_ONPATH_DSTORE 9486 0.770% 9486 0.770%
MLC_HIT_ONPATH_IPRF 0 0.000% 0 0.000%
MLC_HIT_ONPATH_DPRF 0 0.000% 0 0.000%
MLC_HIT_ONPATH_WB 2572 0.209% 2572 0.209%
MLC_HIT_ONPATH_WB_NODIRTY 1208166 98.008% 1208166 98.008%
 1232717 100.000% 1232717 100.000%
 5.91 5.88 5.91 5.88
MLC_HIT_OFFPATH_IFETCH 540 3.767% 540 3.767%
MLC_HIT_OFFPATH_DFETCH 724 5.051% 724 5.051%
MLC_HIT_OFFPATH_DSTORE 212 1.479% 212 1.479%
MLC_HIT_OFFPATH_IPRF 0 0.000% 0 0.000%
MLC_HIT_OFFPATH_DPRF 0 0.000% 0 0.000%
MLC_HIT_OFFPATH_WB 12859 89.704% 12859 89.704%
MLC_HIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 14335 100.000% 14335 100.000%
 4.57 0.95 4.57 0.95
L1_MISS_ONPATH_IFETCH 573 0.047% 573 0.047%
L1_MISS_ONPATH_DFETCH 1638 0.135% 1638 0.135%
L1_MISS_ONPATH_DSTORE 1193759 98.611% 1193759 98.611%
L1_MISS_ONPATH_IPRF 0 0.000% 0 0.000%
L1_MISS_ONPATH_DPRF 0 0.000% 0 0.000%
L1_MISS_ONPATH_WB 114 0.009% 114 0.009%
L1_MISS_ONPATH_WB_NODIRTY 14493 1.197% 14493 1.197%
 1210577 100.000% 1210577 100.000%
 2.05 0.49 2.05 0.49
L1_MISS_OFFPATH_IFETCH 127 1.247% 127 1.247%
L1_MISS_OFFPATH_DFETCH 30 0.294% 30 0.294%
L1_MISS_OFFPATH_DSTORE 11 0.108% 11 0.108%
L1_MISS_OFFPATH_IPRF 0 0.000% 0 0.000%
L1_MISS_OFFPATH_DPRF 0 0.000% 0 0.000%
L1_MISS_OFFPATH_WB 10020 98.351% 10020 98.351%
L1_MISS_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 10188 100.000% 10188 100.000%
 4.92 0.25 4.92 0.25
L1_HIT_ONPATH_IFETCH 11 0.001% 11 0.001%
L1_HIT_ONPATH_DFETCH 2622 0.219% 2622 0.219%
L1_HIT_ONPATH_DSTORE 2055 0.171% 2055 0.171%
L1_HIT_ONPATH_IPRF 0 0.000% 0 0.000%
L1_HIT_ONPATH_DPRF 0 0.000% 0 0.000%
L1_HIT_ONPATH_WB 2 0.000% 2 0.000%
L1_HIT_ONPATH_WB_NODIRTY 1193623 99.609% 1193623 99.609%
 1198313 100.000% 1198313 100.000%
 5.98 5.98 5.98 5.98
L1_HIT_OFFPATH_IFETCH 3 3.797% 3 3.797%
L1_HIT_OFFPATH_DFETCH 6 7.595% 6 7.595%
L1_HIT_OFFPATH_DSTORE 3 3.797% 3 3.797%
L1_HIT_OFFPATH_IPRF 0 0.000% 0 0.000%
L1_HIT_OFFPATH_DPRF 0 0.000% 0 0.000%
L1_HIT_OFFPATH_WB 67 84.810% 67 84.810%
L1_HIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 79 100.000% 79 100.000%
 4.39 1.19 4.39 1.19
DRAM_CYCLES 0 0
DRAM_UNBLOCK_CYCLES 0 -nan 0 -nan
DRAM_UNBLOCK_PERIODS 0 0
MEM_REQ_BUFFER_FULL 112012845 112012845
MEM_REQ_BUFFER_FULL_DENIED_DEMAND 47739181 47739181
CORE_MEM_BLOCKED 38325606 38325606
MEM_REQ_BUFFER_FULL_DENIED_IFETCH 14022 0.029% 14022 0.029%
MEM_REQ_BUFFER_FULL_DENIED_DFETCH 117272 0.246% 117272 0.246%
MEM_REQ_BUFFER_FULL_DENIED_DSTORE 47607887 99.721% 47607887 99.721%
MEM_REQ_BUFFER_FULL_DENIED_IPRF 0 0.000% 0 0.000%
MEM_REQ_BUFFER_FULL_DENIED_DPRF 0 0.000% 0 0.000%
MEM_REQ_BUFFER_FULL_DENIED_WB 1831 0.004% 1831 0.004%
MEM_REQ_BUFFER_FULL_DENIED_WB_NODIRTY 0 0.000% 0 0.000%
 47741012 100.000% 47741012 100.000%
 2.00 0.05 2.00 0.05
MEM_QUEUE_FULL 39240552 39240552
MEM_REQ_BUFFER_MISS 29876576 92.882% 29876576 92.882%
MEM_REQ_BUFFER_HIT 2289552 7.118% 2289552 7.118%
 32166128 100.000% 32166128 100.000%
 0.07 0.25 0.07 0.25
MEM_REQ_FDIP_BUFFER_HIT 16627 16627
MEM_REQ_FDIP_CYCLE_DELTA 3000798 3000798
MEM_REQ_DEMAND_ICACHE_BUFFER_HIT 569 569
MEM_REQ_DEMAND_ICACHE_CYCLE_DELTA 31799 31799
MEM_REQ_IFETCH 1096 0.023% 1096 0.023%
MEM_REQ_DFETCH 15632 0.323% 15632 0.323%
MEM_REQ_DSTORE 1144058 23.612% 1144058 23.612%
MEM_REQ_IPRF 0 0.000% 0 0.000%
MEM_REQ_DPRF 0 0.000% 0 0.000%
MEM_REQ_WB 27632 0.570% 27632 0.570%
MEM_REQ_WB_NODIRTY 3656877 75.473% 3656877 75.473%
 4845295 100.000% 4845295 100.000%
 5.03 4.70 5.03 4.70
LD_NO_FORWARD 480966 63.636% 480966 63.636%
FORWARDED_LD 274847 36.364% 274847 36.364%
 755813 100.000% 755813 100.000%
 0.36 0.44 0.36 0.44
WRONGPATH_L1Q_REMOVALS 0 -nan% 0 -nan%
WRONGPATH_BUSQ_REMOVALS 0 -nan% 0 -nan%
WRONGPATH_MEMQ_REMOVALS 0 -nan% 0 -nan%
WRONGPATH_L1FILLQ_REMOVALS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
WRONGPATH_L1Q_DEMOTIONS 0 -nan% 0 -nan%
WRONGPATH_BUSQ_DEMOTIONS 0 -nan% 0 -nan%
WRONGPATH_MEMQ_DEMOTIONS 0 -nan% 0 -nan%
WRONGPATH_L1FILLQ_DEMOTIONS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
PROMOTION_QMLC 1957 3.082% 1957 3.082%
PROMOTION_QL1 61551 96.918% 61551 96.918%
 63508 100.000% 63508 100.000%
 0.97 0.95 0.97 0.95
PROMOTION_QBUSOUT 0 0
PROMOTION_QMEM 0 0
PROMOTION_QL1FILL 26 26
PROMOTION_QMLC_FILL 27 27
NOPROMOTION_QMEM 0 0
NOPROMOTION_QL1FILL 0 -nan% 0 -nan%
NOPROMOTION_QMLC_FILL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
PROMOTION_FROM_FDIP_OFF_TO_ON 0 0
ICACHE_FILL_CORRECT_REQ 3675 12.792% 3675 12.792%
ICACHE_FILL_INCORRECT_REQ 25053 87.208% 25053 87.208%
 28728 100.000% 28728 100.000%
 0.87 0.82 0.87 0.82
ICACHE_FILL_CORRECT_REQ_BY_FDIP 2749 9.569% 2749 9.569%
ICACHE_FILL_INCORRECT_REQ_BY_FDIP 24883 86.616% 24883 86.616%
ICACHE_FILL_CORRECT_REQ_BY_ICACHE_DEMAND 926 3.223% 926 3.223%
ICACHE_FILL_INCORRECT_REQ_BY_ICACHE_DEMAND 170 0.592% 170 0.592%
 28728 100.000% 28728 100.000%
 0.95 0.26 0.95 0.26
ICACHE_FILL_CORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 1479 1479
ICACHE_FILL_CORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 13 13
ICACHE_FILL_INCORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 397 397
ICACHE_FILL_INCORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA 105453957457 105453957457
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND 164896 164896
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_FDIP 645180 645180
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 98219 98219
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 3060 3060
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA 952699218912 952699218912
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND 55516 55516
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_FDIP 6983581 6983581
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 0 0
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0
MEM_REQ_INIT 4845295 4845295
MEM_REQ_COMPLETE 3665189 0.7564 3665189 0.7564
MEM_REQ_KILLED 1180105 0.2436 1180105 0.2436
MEM_REQ_COMPLETE_MLC 1247060 0.2574 1247060 0.2574
MEM_REQ_COMPLETE_L1 1195906 0.2468 1195906 0.2468
MEM_REQ_COMPLETE_MEM 1222223 0.2522 1222223 0.2522
MEM_REQ_INIT_ONPATH 4820433 0.9949 4820433 0.9949
MEM_REQ_INIT_OFFPATH 24862 0.0051 24862 0.0051
MEM_REQ_COMPLETE_ONPATH 3640620 0.9933 3640620 0.9933
MEM_REQ_COMPLETE_OFFPATH 24569 0.0067 24569 0.0067
MEM_REQ_INIT_IFETCH 1096 0.092% 1096 0.092%
MEM_REQ_INIT_DFETCH 15632 1.315% 15632 1.315%
MEM_REQ_INIT_DSTORE 1144058 96.267% 1144058 96.267%
MEM_REQ_INIT_IPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_DPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_WB 27632 2.325% 27632 2.325%
MEM_REQ_INIT_WB_NODIRTY 0 0.000% 0 0.000%
 1188418 100.000% 1188418 100.000%
 2.05 0.47 2.05 0.47
MEM_REQ_COMPLETE_IFETCH 79081 1.611% 79081 1.611%
MEM_REQ_COMPLETE_DFETCH 3597053 73.289% 3597053 73.289%
MEM_REQ_COMPLETE_DSTORE 1206296 24.578% 1206296 24.578%
MEM_REQ_COMPLETE_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_WB 25600 0.522% 25600 0.522%
MEM_REQ_COMPLETE_WB_NODIRTY 0 0.000% 0 0.000%
 4908030 100.000% 4908030 100.000%
 1.25 0.51 1.25 0.51
MEM_REQ_KILLED_IFETCH 2414036 100.000% 2414036 100.000%
MEM_REQ_KILLED_DFETCH 0 0.000% 0 0.000%
MEM_REQ_KILLED_DSTORE 0 0.000% 0 0.000%
MEM_REQ_KILLED_IPRF 0 0.000% 0 0.000%
MEM_REQ_KILLED_DPRF 0 0.000% 0 0.000%
MEM_REQ_KILLED_WB 0 0.000% 0 0.000%
MEM_REQ_KILLED_WB_NODIRTY 0 0.000% 0 0.000%
 2414036 100.000% 2414036 100.000%
 0.00 0.00 0.00 0.00
MEM_REQ_INIT_OFFPATH_IFETCH 1180491 97.969% 1180491 97.969%
MEM_REQ_INIT_OFFPATH_DFETCH 799 0.066% 799 0.066%
MEM_REQ_INIT_OFFPATH_DSTORE 235 0.020% 235 0.020%
MEM_REQ_INIT_OFFPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_OFFPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_OFFPATH_WB 23442 1.945% 23442 1.945%
MEM_REQ_INIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 1204967 100.000% 1204967 100.000%
 0.10 0.68 0.10 0.68
MEM_REQ_INIT_ONPATH_IFETCH 710 0.061% 710 0.061%
MEM_REQ_INIT_ONPATH_DFETCH 14833 1.275% 14833 1.275%
MEM_REQ_INIT_ONPATH_DSTORE 1143823 98.304% 1143823 98.304%
MEM_REQ_INIT_ONPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_ONPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_ONPATH_WB 4190 0.360% 4190 0.360%
MEM_REQ_INIT_ONPATH_WB_NODIRTY 0 0.000% 0 0.000%
 1163556 100.000% 1163556 100.000%
 2.00 0.21 2.00 0.21
MEM_REQ_MATCH_IFETCH 77987 1.317% 77987 1.317%
MEM_REQ_MATCH_DFETCH 3623491 61.178% 3623491 61.178%
MEM_REQ_MATCH_DSTORE 2141406 36.155% 2141406 36.155%
MEM_REQ_MATCH_IPRF 0 0.000% 0 0.000%
MEM_REQ_MATCH_DPRF 0 0.000% 0 0.000%
MEM_REQ_MATCH_WB 18436 0.311% 18436 0.311%
MEM_REQ_MATCH_WB_NODIRTY 61510 1.039% 61510 1.039%
 5922830 100.000% 5922830 100.000%
 1.41 0.71 1.41 0.71
MEM_REQ_COMPLETE_OFFPATH_IFETCH 675 2.747% 675 2.747%
MEM_REQ_COMPLETE_OFFPATH_DFETCH 756 3.077% 756 3.077%
MEM_REQ_COMPLETE_OFFPATH_DSTORE 226 0.920% 226 0.920%
MEM_REQ_COMPLETE_OFFPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_WB 22912 93.256% 22912 93.256%
MEM_REQ_COMPLETE_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 24569 100.000% 24569 100.000%
 4.71 0.75 4.71 0.75
MEM_REQ_COMPLETE_ONPATH_IFETCH 2453 0.200% 2453 0.200%
MEM_REQ_COMPLETE_ONPATH_DFETCH 15373 1.253% 15373 1.253%
MEM_REQ_COMPLETE_ONPATH_DSTORE 1206070 98.328% 1206070 98.328%
MEM_REQ_COMPLETE_ONPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_ONPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_ONPATH_WB 2688 0.219% 2688 0.219%
MEM_REQ_COMPLETE_ONPATH_WB_NODIRTY 0 0.000% 0 0.000%
 1226584 100.000% 1226584 100.000%
 1.99 0.18 1.99 0.18
MEM_REQ_COMPLETE_MEM_IFETCH 2414784 66.591% 2414784 66.591%
MEM_REQ_COMPLETE_MEM_DFETCH 4752 0.131% 4752 0.131%
MEM_REQ_COMPLETE_MEM_DSTORE 1196598 32.998% 1196598 32.998%
MEM_REQ_COMPLETE_MEM_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MEM_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MEM_WB 10169 0.280% 10169 0.280%
MEM_REQ_COMPLETE_MEM_WB_NODIRTY 0 0.000% 0 0.000%
 3626303 100.000% 3626303 100.000%
 0.68 0.79 0.68 0.79
MEM_REQ_COMPLETE_MEM_BW_PREFETCHABLE 1142572 1142572
MEM_REQ_COMPLETE_MEM_MATCHED_BW_PREF 61984 61984
MEM_REQ_COMPLETE_L1_IFETCH 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_DFETCH 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_DSTORE 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_IPRF 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_DPRF 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_WB 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_COMPLETE_MLC_IFETCH 1198286 97.044% 1198286 97.044%
MEM_REQ_COMPLETE_MLC_DFETCH 11377 0.921% 11377 0.921%
MEM_REQ_COMPLETE_MLC_DSTORE 9698 0.785% 9698 0.785%
MEM_REQ_COMPLETE_MLC_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_WB 15431 1.250% 15431 1.250%
MEM_REQ_COMPLETE_MLC_WB_NODIRTY 0 0.000% 0 0.000%
 1234792 100.000% 1234792 100.000%
 0.09 0.58 0.09 0.58
CORE_MLP_CLUSTERS 1208174 1208174
CORE_MLP 1030256318 1030256318
CORE_MLP_IFETCH 0 0
CORE_MLP_DFETCH 0 0
CORE_MLP_DSTORE 0 0
CORE_MLP_IPRF 0 0
CORE_MLP_DPRF 0 0
CORE_MLP_WB 0 0
CORE_MLP_WB_NODIRTY 0 0
CORE_MLP_0 590105 1.463% 590105 1.463%
CORE_MLP_1 60433 0.150% 60433 0.150%
CORE_MLP_2 37375 0.093% 37375 0.093%
CORE_MLP_3 14554 0.036% 14554 0.036%
CORE_MLP_4 14919 0.037% 14919 0.037%
CORE_MLP_5 17678 0.044% 17678 0.044%
CORE_MLP_6 16006 0.040% 16006 0.040%
CORE_MLP_7 14595 0.036% 14595 0.036%
CORE_MLP_8 46170 0.114% 46170 0.114%
CORE_MLP_9 81408 0.202% 81408 0.202%
CORE_MLP_10 75120 0.186% 75120 0.186%
CORE_MLP_11 127832 0.317% 127832 0.317%
CORE_MLP_12 152177 0.377% 152177 0.377%
CORE_MLP_13 217299 0.539% 217299 0.539%
CORE_MLP_14 300803 0.746% 300803 0.746%
CORE_MLP_15 355916 0.882% 355916 0.882%
CORE_MLP_16 401502 0.995% 401502 0.995%
CORE_MLP_17 385133 0.955% 385133 0.955%
CORE_MLP_18 430928 1.068% 430928 1.068%
CORE_MLP_19 684321 1.696% 684321 1.696%
CORE_MLP_20 1245194 3.086% 1245194 3.086%
CORE_MLP_21 1649565 4.088% 1649565 4.088%
CORE_MLP_22 2148028 5.324% 2148028 5.324%
CORE_MLP_23 5408320 13.404% 5408320 13.404%
CORE_MLP_24 1442728 3.576% 1442728 3.576%
CORE_MLP_25 1492682 3.700% 1492682 3.700%
CORE_MLP_26 1351187 3.349% 1351187 3.349%
CORE_MLP_27 1279963 3.172% 1279963 3.172%
CORE_MLP_28 1034357 2.564% 1034357 2.564%
CORE_MLP_29 1394849 3.457% 1394849 3.457%
CORE_MLP_30 17876767 44.307% 17876767 44.307%
CORE_MLP_31 0 0.000% 0 0.000%
CORE_MLP_32 0 0.000% 0 0.000%
 40347914 100.000% 40347914 100.000%
 25.53 4.86 25.53 4.86
MEM_QUEUE_OCC_0 0 -nan% 0 -nan%
MEM_QUEUE_OCC_4 0 -nan% 0 -nan%
MEM_QUEUE_OCC_8 0 -nan% 0 -nan%
MEM_QUEUE_OCC_12 0 -nan% 0 -nan%
MEM_QUEUE_OCC_16 0 -nan% 0 -nan%
MEM_QUEUE_OCC_20 0 -nan% 0 -nan%
MEM_QUEUE_OCC_24 0 -nan% 0 -nan%
MEM_QUEUE_OCC_28 0 -nan% 0 -nan%
MEM_QUEUE_OCC_32 0 -nan% 0 -nan%
MEM_QUEUE_OCC_36 0 -nan% 0 -nan%
MEM_QUEUE_OCC_40 0 -nan% 0 -nan%
MEM_QUEUE_OCC_44 0 -nan% 0 -nan%
MEM_QUEUE_OCC_48 0 -nan% 0 -nan%
MEM_QUEUE_OCC_52 0 -nan% 0 -nan%
MEM_QUEUE_OCC_56 0 -nan% 0 -nan%
MEM_QUEUE_OCC_60 0 -nan% 0 -nan%
MEM_QUEUE_OCC_64 0 -nan% 0 -nan%
MEM_QUEUE_OCC_68 0 -nan% 0 -nan%
MEM_QUEUE_OCC_72 0 -nan% 0 -nan%
MEM_QUEUE_OCC_76 0 -nan% 0 -nan%
MEM_QUEUE_OCC_80 0 -nan% 0 -nan%
MEM_QUEUE_OCC_84 0 -nan% 0 -nan%
MEM_QUEUE_OCC_88 0 -nan% 0 -nan%
MEM_QUEUE_OCC_92 0 -nan% 0 -nan%
MEM_QUEUE_OCC_96 0 -nan% 0 -nan%
MEM_QUEUE_OCC_100 0 -nan% 0 -nan%
MEM_QUEUE_OCC_104 0 -nan% 0 -nan%
MEM_QUEUE_OCC_108 0 -nan% 0 -nan%
MEM_QUEUE_OCC_112 0 -nan% 0 -nan%
MEM_QUEUE_OCC_116 0 -nan% 0 -nan%
MEM_QUEUE_OCC_120 0 -nan% 0 -nan%
MEM_QUEUE_OCC_124 0 -nan% 0 -nan%
MEM_QUEUE_OCC_128 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
OPEN_PAGE_HIT 0 -nan% 0 -nan%
CLOSED_PAGE_MISS 0 -nan% 0 -nan%
WRONG_PAGE_MISS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_LD_BANK_BLOCK 0 -nan% 0 -nan%
L0_LD_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_ST_BANK_BLOCK 0 -nan% 0 -nan%
L0_ST_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_LD_CACHE_BLOCK 0 -nan% 0 -nan%
L0_LD_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_LD_BANK_BLOCK 175 0.015% 175 0.015%
MLC_LD_BANK_AVAIL 1188418 99.985% 1188418 99.985%
 1188593 100.000% 1188593 100.000%
 1.00 1.00 1.00 1.00
MLC_ST_BANK_BLOCK 0 0.000% 0 0.000%
MLC_ST_BANK_AVAIL 1208175 100.000% 1208175 100.000%
 1208175 100.000% 1208175 100.000%
 1.00 1.00 1.00 1.00
MLC_LD_CACHE_BLOCK 0 -nan% 0 -nan%
MLC_LD_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_ST_CACHE_BLOCK 0 -nan% 0 -nan%
MLC_ST_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_LD_BANK_BLOCK 57 0.005% 57 0.005%
L1_LD_BANK_AVAIL 1225485 99.995% 1225485 99.995%
 1225542 100.000% 1225542 100.000%
 1.00 1.00 1.00 1.00
L1_ST_BANK_BLOCK 12 0.001% 12 0.001%
L1_ST_BANK_AVAIL 1192644 99.999% 1192644 99.999%
 1192656 100.000% 1192656 100.000%
 1.00 1.00 1.00 1.00
L1_LD_CACHE_BLOCK 0 -nan% 0 -nan%
L1_LD_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_ST_CACHE_BLOCK 0 -nan% 0 -nan%
L1_ST_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_LD_BANK_BLOCK 0 -nan% 0 -nan%
MEM_LD_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_ST_BANK_BLOCK 0 -nan% 0 -nan%
MEM_ST_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_PF_BANK_BLOCK 0 -nan% 0 -nan%
MEM_PF_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_FILL 0 0
L1_FILL 1217454 99.813% 1217454 99.813%
L1_WB_FILL 2283 0.187% 2283 0.187%
 1219737 100.000% 1219737 100.000%
 0.00 0.04 0.00 0.04
L1_DEMAND_FILL 1144770 94.030% 1144770 94.030%
L1_PREF_FILL 72684 5.970% 72684 5.970%
 1217454 100.000% 1217454 100.000%
 0.06 0.23 0.06 0.23
MLC_FILL 13333854 100.000% 13333854 100.000%
MLC_WB_FILL 8 0.000% 8 0.000%
 13333862 100.000% 13333862 100.000%
 0.00 0.00 0.00 0.00
MLC_DEMAND_FILL 12682836 95.118% 12682836 95.118%
MLC_PREF_FILL 651018 4.882% 651018 4.882%
 13333854 100.000% 13333854 100.000%
 0.05 0.21 0.05 0.21
NORESET_L1_FILL 1219737 1219737
NORESET_L1_FILL_NONPREF 1136919 1136919
NORESET_L1_FILL_PREF 82818 82818
NORESET_L1_EVICT 1186969 1186969
NORESET_L1_EVICT_NONPREF 1123920 1123920
NORESET_L1_EVICT_PREF_USED 61787 61787
NORESET_L1_EVICT_PREF_UNUSED 1262 1262
NORESET_L1_PREF_USED 4627 4627
ORACLE_OFFPATH_DC_FILL 0 0
ORACLE_OFFPATH_IC_FILL 0 0
ORACLE_OFFPATH_L1_FILL 0 0
UPDATE_EVENT_QUEUE_PROCESS 0 0
INSERT_EVENT_QUEUE_PROCESS 0 0
ICFILL_AFTER_REDIRECT 0 0
EVENT_QUEUE_MATCH_ADD_REQ 0 0
DC_PREF_CACHE_INSERT_REQ 0 0
DC_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan%
DC_PREF_REQ_PREF_CACHE_HIT 0 -nan% 0 -nan%
DC_PREF_REQ_L1_MISS 0 -nan% 0 -nan%
DC_PREF_REQ_CORR 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DC_PREF_CACHE_INSERT 0 0
DC_PREF_CACHE_HIT_PER 0 0.000% 0 0.000%
DC_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000%
DC_PREF_CACHE_HIT 0 0
DC_PREF_CACHE_HIT_OFFPATH 0 0
DC_PREF_HIT_L1_MISS 0 0
IC_PREF_CACHE_HIT_PER 0 0.000% 0 0.000%
IC_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000%
IC_PREF_CACHE_HIT 0 0
IC_PREF_CACHE_HIT_OFFPATH 0 0
L1_PREF_CACHE_HIT_PER 0 0.000% 0 0.000%
L1_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000%
L1_PREF_CACHE_HIT 0 0
L1_PREF_CACHE_HIT_OFFPATH 0 0
DC_PREF_CACHE_FILL 0 0
DC_PREF_MOVE_DC 0 -nan% 0 -nan%
DC_PREF_MOVE_L1 0 -nan% 0 -nan%
IC_PREF_CACHE_FILL 0 0
IC_PREF_MOVE_IC 0 -nan% 0 -nan%
IC_PREF_MOVE_L1 0 -nan% 0 -nan%
L1_PREF_CACHE_FILL 0 0
L1_PREF_MOVE_L1 0 -nan% 0 -nan%
OFF_PATH_CONFIRMED 377754 377754
OFF_PATH_NO_FILL_L1 0 0
WB_L1_MISS_FILL_L1 3311 3311
WB_MLC_MISS_FILL_MLC 8 8
ICACHE_EVICT_REQ_WB_L1 0 0
DCACHE_EVICT_REQ_WB_L1 0 0
DCACHE_EVICT_REQ_WB_L1_NOREAD 0 0
L1_FILL_SKIPPED 0 0
MLC_FILL_SKIPPED 0 0
DCACHE_FILL 1222425 1222425
DCACHE_WB_REQ 1208175 0.9883 1208175 0.9883
DCACHE_WB_REQ_DIRTY 1208175 100.000% 1208175 100.000%
DCACHE_WB_REQ_NODIRTY 0 0.000% 0 0.000%
 1208175 100.000% 1208175 100.000%
 0.00 0.00 0.00 0.00
ICACHE_FILL 28728 28728
ICACHE_WB_REQ 0 0.0000 0 0.0000
L1_FILL_DIRTY 1179040 0.9684 1179040 0.9684
MLC_FILL_DIRTY 1192644 0.0894 1192644 0.0894
ICACHE_UNUSEFUL_CL_CYC 14675452250 14675452250
ICACHE_UNUSEFUL_CL 26324 26324
ICACHE_EVICT_MISS_ONPATH_BY_FDIP 16551 65.008% 16551 65.008%
ICACHE_EVICT_MISS_OFFPATH_BY_FDIP 8909 34.992% 8909 34.992%
 25460 100.000% 25460 100.000%
 0.35 0.44 0.35 0.44
ICACHE_EVICT_MISS_BY_FDIP_ONPATH 3850 15.122% 3850 15.122%
ICACHE_EVICT_MISS_BY_FDIP_OFFPATH 21610 84.878% 21610 84.878%
 25460 100.000% 25460 100.000%
 0.85 0.79 0.85 0.79
ICACHE_EVICT_HIT_ONPATH_BY_FDIP 1203 63.584% 1203 63.584%
ICACHE_EVICT_HIT_OFFPATH_BY_FDIP 689 36.416% 689 36.416%
 1892 100.000% 1892 100.000%
 0.36 0.44 0.36 0.44
ICACHE_EVICT_HIT_BY_FDIP_ONPATH 1879 99.313% 1879 99.313%
ICACHE_EVICT_HIT_BY_FDIP_OFFPATH 13 0.687% 13 0.687%
 1892 100.000% 1892 100.000%
 0.01 0.08 0.01 0.08
MEM_REQ_DENIED_NULL 0 -nan% 0 -nan%
MEM_REQ_DENIED_INST_OUTOF_CS 0 -nan% 0 -nan%
MEM_REQ_DENIED_DATA_IN_CS 0 -nan% 0 -nan%
MEM_REQ_DENIED_DATA_OUTOF_RANGE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_DENIED 0 -nan% 0 -nan%
MEM_REQ_NOT_DENIED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_HIT_WB_STALL 0 0
EXCLUSION_VIOLATED_OSR 0 -nan% 0 -nan%
EXCLUSION_VIOLATED_NOTOSR 0 -nan% 0 -nan%
EXCLUSION_NOT_VIOLATED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIRTY_WRITE_TO_ICACHE 0 0
STREAM_DC_HIT_NOSEND 0 -nan% 0 -nan%
STREAM_WBQDC_HIT_NOSEND 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
STREAM_DCACHE_PREF_HIT 0 0
PREF_DC_HIT_ON_INSERT 0 -nan% 0 -nan%
PREF_L1_HIT_ON_INSERT 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_NEWREQ_MATCHED_MLC_REQ 1094808 1094808
MLC_NEWREQ_MATCHED_L2_PREF 62735 62735
MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT 8 0.0001 8 0.0001
NEWREQ_WB_MATCH_IGNORED 0 0
DEMAND_MATCH_WB_NEW_DONE_FUNC 0 -nan% 0 -nan%
DEMAND_MATCH_WB_NEW_DONE_FUNC_NULL 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DONE_FUNC_NOT_SAME 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DONE_FUNC_SAME 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WBALL_IFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_DFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_DSTORE 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_IPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_DPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WB_IFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DSTORE 0 -nan% 0 -nan%
DEMAND_MATCH_WB_IPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WB_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WB_ND_IFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_DFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_DSTORE 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_IPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_DPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
WB_MATCH_DEMAND 0 0.000% 0 0.000%
WB_MATCH_PREF 0 0.000% 0 0.000%
WB_MATCH_WB 0 0.000% 0 0.000%
WB_MATCH_WB_FILTERED 1102393 100.000% 1102393 100.000%
 1102393 100.000% 1102393 100.000%
 3.00 3.00 3.00 3.00
WB_COMING_BACK_FROM_MEM 0 0
WB_COMING_BACK_FROM_L1 0 0
WB_COMING_BACK_FROM_MLC 0 0
MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH 52 0.004% 52 0.004%
MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_ETC 1174670 99.996% 1174670 99.996%
 1174722 100.000% 1174722 100.000%
 1.00 1.00 1.00 1.00
TOTAL_ONPATH_ICACHE_FILLS 0 0
TOTAL_ONPATH_DCACHE_FILLS 0 0
TOTAL_ONPATH_L1_FILLS 0 0
PER1K_ONPATH_ICACHE_FILLS 0 0.0000 0 0.0000
PER1K_ONPATH_DCACHE_FILLS 0 0.0000 0 0.0000
PER1K_ONPATH_L1_FILLS 0 0.0000 0 0.0000
PER1K_L1_DEMAND_MISS_ONPATH 1195970 119.5969 1195970 119.5969
PER1K_L1_DEMAND_MISS_OFFPATH 168 0.0168 168 0.0168
L2_IDEAL_FILL_L1 0 -nan% 0 -nan%
L2_IDEAL_MISS_L2 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L2_IDEAL_FILL_ICACHE 0 -nan% 0 -nan%
L2_IDEAL_MISS_ICACHE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
HPS_MISS_DELTA__0 0 -nan% 0 -nan%
HPS_MISS_DELTA__1 0 -nan% 0 -nan%
HPS_MISS_DELTA__2 0 -nan% 0 -nan%
HPS_MISS_DELTA__3 0 -nan% 0 -nan%
HPS_MISS_DELTA__4 0 -nan% 0 -nan%
HPS_MISS_DELTA__5 0 -nan% 0 -nan%
HPS_MISS_DELTA__6 0 -nan% 0 -nan%
HPS_MISS_DELTA__7 0 -nan% 0 -nan%
HPS_MISS_DELTA__8 0 -nan% 0 -nan%
HPS_MISS_DELTA__9 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
HPS_HIT_DELTA__0 0 -nan% 0 -nan%
HPS_HIT_DELTA__1 0 -nan% 0 -nan%
HPS_HIT_DELTA__2 0 -nan% 0 -nan%
HPS_HIT_DELTA__3 0 -nan% 0 -nan%
HPS_HIT_DELTA__4 0 -nan% 0 -nan%
HPS_HIT_DELTA__5 0 -nan% 0 -nan%
HPS_HIT_DELTA__6 0 -nan% 0 -nan%
HPS_HIT_DELTA__7 0 -nan% 0 -nan%
HPS_HIT_DELTA__8 0 -nan% 0 -nan%
HPS_HIT_DELTA__9 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DC_MISS_DELTA__0 0 -nan% 0 -nan%
DC_MISS_DELTA__1 0 -nan% 0 -nan%
DC_MISS_DELTA__2 0 -nan% 0 -nan%
DC_MISS_DELTA__3 0 -nan% 0 -nan%
DC_MISS_DELTA__4 0 -nan% 0 -nan%
DC_MISS_DELTA__5 0 -nan% 0 -nan%
DC_MISS_DELTA__6 0 -nan% 0 -nan%
DC_MISS_DELTA__7 0 -nan% 0 -nan%
DC_MISS_DELTA__8 0 -nan% 0 -nan%
DC_MISS_DELTA__9 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ONE_MORE_SUCESS 0 -nan% 0 -nan%
ONE_MORE_DISCARDED_L0CACHE 0 -nan% 0 -nan%
ONE_MORE_DISCARDED_MEM_REQ_FULL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
PREF_L1_TOTAL_SENT 72684 72684
PREF_L1_TOTAL_USED 4627 6.366% 4627 6.366%
PREF_L1_TOTAL_PARTIAL_USED 62727 86.301% 62727 86.301%
PREF_L1_TOTAL_NOT_USED 5330 7.333% 5330 7.333%
PREF_L1_TOTAL_DROPPED 0 0.000% 0 0.000%
 72684 100.000% 72684 100.000%
 1.01 0.27 1.01 0.27
PREF_MLC_TOTAL_SENT 0 0
PREF_MLC_TOTAL_USED 3023 0.462% 3023 0.462%
PREF_MLC_TOTAL_PARTIAL_USED 651018 99.538% 651018 99.538%
PREF_MLC_TOTAL_NOT_USED 0 0.000% 0 0.000%
PREF_MLC_TOTAL_DROPPED 0 0.000% 0 0.000%
 654041 100.000% 654041 100.000%
 1.00 0.00 1.00 0.00
CORE_MLC_PREF_REQ_MISS 0 0.000% 0 0.000%
CORE_MLC_DEMAND_MISS 1139287 99.108% 1139287 99.108%
CORE_MLC_WB_MISS 10253 0.892% 10253 0.892%
 1149540 100.000% 1149540 100.000%
 1.01 0.13 1.01 0.13
CORE_MLC_PREF_REQ_HIT 0 0.000% 0 0.000%
CORE_MLC_DEMAND_HIT 23455 1.881% 23455 1.881%
CORE_MLC_WB_HIT 1223597 98.119% 1223597 98.119%
 1247052 100.000% 1247052 100.000%
 1.98 1.97 1.98 1.97
CORE_MLC_HIT 23455 2.017% 23455 2.017%
CORE_MLC_MISS 1139287 97.983% 1139287 97.983%
 1162742 100.000% 1162742 100.000%
 0.98 0.97 0.98 0.97
CORE_MLC_FILL 13333854 100.000% 13333854 100.000%
CORE_MLC_WB_FILL 8 0.000% 8 0.000%
 13333862 100.000% 13333862 100.000%
 0.00 0.00 0.00 0.00
CORE_MLC_DEMAND_FILL 12682836 95.118% 12682836 95.118%
CORE_MLC_PREF_FILL 651018 4.882% 651018 4.882%
 13333854 100.000% 13333854 100.000%
 0.05 0.21 0.05 0.21
CORE_MLC_PREF_FILL_USED 3023 0.462% 3023 0.462%
CORE_MLC_PREF_FILL_PARTIAL_USED 651018 99.538% 651018 99.538%
CORE_MLC_PREF_FILL_NOT_USED 0 0.000% 0 0.000%
 654041 100.000% 654041 100.000%
 1.00 0.00 1.00 0.00
CORE_L1_PREF_REQ_MISS 72684 5.954% 72684 5.954%
CORE_L1_DEMAND_MISS 1134636 92.945% 1134636 92.945%
CORE_L1_WB_MISS 13445 1.101% 13445 1.101%
 1220765 100.000% 1220765 100.000%
 0.95 0.16 0.95 0.16
CORE_L1_PREF_REQ_HIT 3269 0.273% 3269 0.273%
CORE_L1_DEMAND_HIT 4693 0.392% 4693 0.392%
CORE_L1_WB_HIT 1190430 99.336% 1190430 99.336%
 1198392 100.000% 1198392 100.000%
 1.99 1.98 1.99 1.98
CORE_L1_HIT 4700 0.391% 4700 0.391%
CORE_L1_MISS 1196138 99.609% 1196138 99.609%
 1200838 100.000% 1200838 100.000%
 1.00 0.99 1.00 0.99
CORE_L1_FILL 1217454 99.813% 1217454 99.813%
CORE_L1_WB_FILL 2283 0.187% 2283 0.187%
 1219737 100.000% 1219737 100.000%
 0.00 0.04 0.00 0.04
CORE_L1_DEMAND_FILL 1144770 94.030% 1144770 94.030%
CORE_L1_PREF_FILL 72684 5.970% 72684 5.970%
 1217454 100.000% 1217454 100.000%
 0.06 0.23 0.06 0.23
CORE_L1_PREF_FILL_USED 4627 6.366% 4627 6.366%
CORE_L1_PREF_FILL_PARTIAL_USED 62727 86.301% 62727 86.301%
CORE_L1_PREF_FILL_NOT_USED 5330 7.333% 5330 7.333%
 72684 100.000% 72684 100.000%
 1.01 0.38 1.01 0.38
CORE_L1_DEMAND_USED_POS0 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS1 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS2 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS3 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS4 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS5 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS6 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS7 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS8 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS9 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS10 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS11 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS12 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS13 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS14 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS15 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS16 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS17 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS18 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS19 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS20 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS21 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS22 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS23 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS24 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS25 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS26 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS27 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS28 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS29 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS30 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS31 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS32 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS33 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS34 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS35 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS36 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS37 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS38 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS39 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS40 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS41 0 -nan% 0 -nan%
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L1_SHADOW_STALLING_HIT_POS8 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS9 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS10 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS11 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS12 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS13 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS14 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS15 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS16 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS17 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS18 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS19 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS20 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS21 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS22 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS23 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS24 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS25 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS26 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS27 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS28 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS29 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS30 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS31 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS32 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS33 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS34 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS35 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS36 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS37 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS38 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS39 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS40 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS41 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS42 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS43 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS44 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS45 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS46 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS47 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS48 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS49 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS50 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS51 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS52 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS53 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS54 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS55 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS56 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS57 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS58 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS59 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS60 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS61 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS62 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS63 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS64 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS65 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS66 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS67 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS68 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS69 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS70 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS71 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS72 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS73 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS74 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS75 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS76 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS77 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS78 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS79 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS80 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS81 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS82 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS83 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS84 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS85 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS86 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS87 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS88 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS89 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS90 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS91 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS92 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS93 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS94 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS95 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS96 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS97 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS98 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS99 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS100 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS101 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS102 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS103 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS104 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS105 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS106 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS107 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS108 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS109 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS110 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS111 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS112 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS113 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS114 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS115 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS116 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS117 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS118 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS119 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS120 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS121 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS122 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS123 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS124 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS125 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS126 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS127 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_SHADOW_DEMAND_HIT_POS0 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS1 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS2 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS3 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS4 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS5 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS6 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS7 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS8 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS9 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS10 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS11 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS12 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS13 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS14 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS15 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS16 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS17 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS18 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS19 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS20 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS21 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS22 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS23 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS24 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS25 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS26 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS27 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS28 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS29 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS30 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS31 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS32 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS33 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS34 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS35 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS36 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS37 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS38 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS39 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS40 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS41 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS42 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS43 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS44 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS45 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS46 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS47 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS48 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS49 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS50 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS51 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS52 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS53 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS54 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS55 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS56 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS57 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS58 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS59 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS60 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS61 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS62 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS63 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS64 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS65 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS66 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS67 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS68 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS69 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS70 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS71 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS72 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS73 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS74 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS75 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS76 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS77 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS78 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS79 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS80 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS81 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS82 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS83 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS84 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS85 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS86 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS87 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS88 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS89 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS90 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS91 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS92 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS93 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS94 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS95 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS96 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS97 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS98 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS99 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS100 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS101 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS102 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS103 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS104 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS105 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS106 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS107 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS108 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS109 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS110 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS111 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS112 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS113 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS114 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS115 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS116 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS117 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS118 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS119 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS120 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS121 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS122 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS123 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS124 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS125 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS126 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS127 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_MLC_SENT 0 0
CORE_PREF_MLC_USED 3023 0.462% 3023 0.462%
CORE_PREF_MLC_PARTIAL_USED 651018 99.538% 651018 99.538%
CORE_PREF_MLC_NOT_USED 0 0.000% 0 0.000%
CORE_PREF_MLC_DROPPED 0 0.000% 0 0.000%
 654041 100.000% 654041 100.000%
 1.00 0.00 1.00 0.00
CORE_PREF_L1_SENT 72684 72684
CORE_PREF_L1_USED 4627 6.257% 4627 6.257%
CORE_PREF_L1_PARTIAL_USED 62727 84.828% 62727 84.828%
CORE_PREF_L1_NOT_USED 6592 8.915% 6592 8.915%
CORE_PREF_L1_DROPPED 0 0.000% 0 0.000%
 73946 100.000% 73946 100.000%
 1.03 0.29 1.03 0.29
TOTAL_MEM_LATENCY 14091852846 11574.8544 14091852846 11574.8544
TOTAL_MEM_LATENCY_DEMAND 13617235178 11895.1712 13617235178 11895.1712
TOTAL_MEM_LATENCY_PREF 474617668 6529.8782 474617668 6529.8782
CORE_MEM_LATENCY 14091852846 11574.8544 14091852846 11574.8544
CORE_MEM_LATENCY_DEMAND 13617235178 11895.1712 13617235178 11895.1712
CORE_MEM_LATENCY_PREF 474617668 6529.8782 474617668 6529.8782
CORE_MEM_LATENCY_IFETCH 278294 0.027% 278294 0.027%
CORE_MEM_LATENCY_DFETCH 698112 0.068% 698112 0.068%
CORE_MEM_LATENCY_DSTORE 1017755614 98.670% 1017755614 98.670%
CORE_MEM_LATENCY_IPRF 0 0.000% 0 0.000%
CORE_MEM_LATENCY_UOCPRF 0 0.000% 0 0.000%
CORE_MEM_LATENCY_FDIPPRF 6644738 0.644% 6644738 0.644%
CORE_MEM_LATENCY_DPRF 0 0.000% 0 0.000%
CORE_MEM_LATENCY_WB 6097014 0.591% 6097014 0.591%
CORE_MEM_LATENCY_WB_NODIRTY 0 0.000% 0 0.000%
 1031473772 100.000% 1031473772 100.000%
 2.05 0.45 2.05 0.45
CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
TOTAL_L1_MISS_LATENCY 1031473809 847.2384 1031473809 847.2384
TOTAL_L1_MISS_LATENCY_DEMAND 986243390 861.5210 986243390 861.5210
TOTAL_L1_MISS_LATENCY_PREF 45230419 622.2885 45230419 622.2885
CORE_L1_MISS_LATENCY 1031473809 847.2384 1031473809 847.2384
CORE_L1_MISS_LATENCY_DEMAND 986243390 861.5210 986243390 861.5210
CORE_L1_MISS_LATENCY_PREF 45230419 622.2885 45230419 622.2885
CORE_EVICTED_L1_DEMAND 1123920 94.688% 1123920 94.688%
CORE_EVICTED_L1_PREF_USED 61787 5.205% 61787 5.205%
CORE_EVICTED_L1_PREF_NOT_USED 1262 0.106% 1262 0.106%
 1186969 100.000% 1186969 100.000%
 0.05 0.22 0.05 0.22
CORE_EVICTED_MLC_DEMAND 1132101 94.504% 1132101 94.504%
CORE_EVICTED_MLC_PREF_USED 62414 5.210% 62414 5.210%
CORE_EVICTED_MLC_PREF_NOT_USED 3423 0.286% 3423 0.286%
 1197938 100.000% 1197938 100.000%
 0.06 0.24 0.06 0.24
CORE_MEM_LATENCY_AVE_DEMAND 2002448272 1781.6644 2002448272 1781.6644
CORE_MEM_LATENCY_AVE_PREF_USED 80257552 1298.9391 80257552 1298.9391
CORE_MEM_LATENCY_AVE_PREF_NOT_USED 3479096 2756.8114 3479096 2756.8114
DRAM_LATENCY 0 0
TOTAL_DRAM_LATENCY 0 0
DRAM_CLOSED_PAGE_POLICY_CMD 0 0
DRAM_ACTIVATE_STALLING 0 0
DRAM_PRECHARGE_STALLING 0 0
DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0
L1_STAY_DEMAND 1212082519213 1078441.9881 1212082519213 1078441.9881
L1_STAY_PREF_USED 67146275861 1086737.9200 67146275861 1086737.9200
L1_STAY_PREF_NOT_USED 803048007 636329.6410 803048007 636329.6410
TOTAL_DATA_MISS_LATENCY 1019136563 1019136563
TOTAL_DATA_MISS_COUNT 1201415 1201415
CORE_PREF_L1_NOT_USED_LATENCY200 151 11.965% 151 11.965%
CORE_PREF_L1_NOT_USED_LATENCY400 52 4.120% 52 4.120%
CORE_PREF_L1_NOT_USED_LATENCY600 258 20.444% 258 20.444%
CORE_PREF_L1_NOT_USED_LATENCY800 326 25.832% 326 25.832%
CORE_PREF_L1_NOT_USED_LATENCY1000 143 11.331% 143 11.331%
CORE_PREF_L1_NOT_USED_LATENCY1200 81 6.418% 81 6.418%
CORE_PREF_L1_NOT_USED_LATENCY1400 139 11.014% 139 11.014%
CORE_PREF_L1_NOT_USED_LATENCY1600 58 4.596% 58 4.596%
CORE_PREF_L1_NOT_USED_LATENCY1600MORE 54 4.279% 54 4.279%
 1262 100.000% 1262 100.000%
 3.32 1.91 3.32 1.91
CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000%
CORE_PREF_L1_NOT_USED_DISTANCE_2 0 0.000% 0 0.000%
CORE_PREF_L1_NOT_USED_DISTANCE_4 15 1.189% 15 1.189%
CORE_PREF_L1_NOT_USED_DISTANCE_8 21 1.664% 21 1.664%
CORE_PREF_L1_NOT_USED_DISTANCE_16 70 5.547% 70 5.547%
CORE_PREF_L1_NOT_USED_DISTANCE_32 109 8.637% 109 8.637%
CORE_PREF_L1_NOT_USED_DISTANCE_MORE 1047 82.964% 1047 82.964%
 1262 100.000% 1262 100.000%
 5.71 5.25 5.71 5.25
CORE_PREF_L1_USED_LATENCY200 2194 3.551% 2194 3.551%
CORE_PREF_L1_USED_LATENCY400 259 0.419% 259 0.419%
CORE_PREF_L1_USED_LATENCY600 31884 51.603% 31884 51.603%
CORE_PREF_L1_USED_LATENCY800 21590 34.943% 21590 34.943%
CORE_PREF_L1_USED_LATENCY1000 3190 5.163% 3190 5.163%
CORE_PREF_L1_USED_LATENCY1200 488 0.790% 488 0.790%
CORE_PREF_L1_USED_LATENCY1400 188 0.304% 188 0.304%
CORE_PREF_L1_USED_LATENCY1600 83 0.134% 83 0.134%
CORE_PREF_L1_USED_LATENCY1600MORE 1911 3.093% 1911 3.093%
 61787 100.000% 61787 100.000%
 2.61 1.25 2.61 1.25
CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000%
CORE_PREF_L1_USED_DISTANCE_2 0 0.000% 0 0.000%
CORE_PREF_L1_USED_DISTANCE_4 7 0.011% 7 0.011%
CORE_PREF_L1_USED_DISTANCE_8 25 0.040% 25 0.040%
CORE_PREF_L1_USED_DISTANCE_16 65 0.105% 65 0.105%
CORE_PREF_L1_USED_DISTANCE_32 56 0.091% 56 0.091%
CORE_PREF_L1_USED_DISTANCE_MORE 61634 99.752% 61634 99.752%
 61787 100.000% 61787 100.000%
 6.00 5.99 6.00 5.99
CORE_PREF_L1_DEMAND_LATENCY300 74205 6.602% 74205 6.602%
CORE_PREF_L1_DEMAND_LATENCY400 16578 1.475% 16578 1.475%
CORE_PREF_L1_DEMAND_LATENCY500 53123 4.727% 53123 4.727%
CORE_PREF_L1_DEMAND_LATENCY600 140124 12.467% 140124 12.467%
CORE_PREF_L1_DEMAND_LATENCY700 154175 13.718% 154175 13.718%
CORE_PREF_L1_DEMAND_LATENCY800 185279 16.485% 185279 16.485%
CORE_PREF_L1_DEMAND_LATENCY900 113648 10.112% 113648 10.112%
CORE_PREF_L1_DEMAND_LATENCY1000 49121 4.371% 49121 4.371%
CORE_PREF_L1_DEMAND_LATENCY1000MORE 337667 30.044% 337667 30.044%
 1123920 100.000% 1123920 100.000%
 5.17 3.49 5.17 3.49
CORE_PREF_MLC_NOT_USED_LATENCY200 312 9.115% 312 9.115%
CORE_PREF_MLC_NOT_USED_LATENCY400 371 10.838% 371 10.838%
CORE_PREF_MLC_NOT_USED_LATENCY600 532 15.542% 532 15.542%
CORE_PREF_MLC_NOT_USED_LATENCY800 1022 29.857% 1022 29.857%
CORE_PREF_MLC_NOT_USED_LATENCY1000 548 16.009% 548 16.009%
CORE_PREF_MLC_NOT_USED_LATENCY1200 261 7.625% 261 7.625%
CORE_PREF_MLC_NOT_USED_LATENCY1400 205 5.989% 205 5.989%
CORE_PREF_MLC_NOT_USED_LATENCY1600 57 1.665% 57 1.665%
CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 115 3.360% 115 3.360%
 3423 100.000% 3423 100.000%
 3.08 1.72 3.08 1.72
CORE_PREF_MLC_USED_LATENCY200 2355 3.773% 2355 3.773%
CORE_PREF_MLC_USED_LATENCY400 173 0.277% 173 0.277%
CORE_PREF_MLC_USED_LATENCY600 22789 36.513% 22789 36.513%
CORE_PREF_MLC_USED_LATENCY800 30704 49.194% 30704 49.194%
CORE_PREF_MLC_USED_LATENCY1000 3705 5.936% 3705 5.936%
CORE_PREF_MLC_USED_LATENCY1200 524 0.840% 524 0.840%
CORE_PREF_MLC_USED_LATENCY1400 179 0.287% 179 0.287%
CORE_PREF_MLC_USED_LATENCY1600 50 0.080% 50 0.080%
CORE_PREF_MLC_USED_LATENCY1600MORE 1935 3.100% 1935 3.100%
 62414 100.000% 62414 100.000%
 2.76 1.23 2.76 1.23
CORE_PREF_MLC_DEMAND_LATENCY300 73902 6.528% 73902 6.528%
CORE_PREF_MLC_DEMAND_LATENCY400 8291 0.732% 8291 0.732%
CORE_PREF_MLC_DEMAND_LATENCY500 25745 2.274% 25745 2.274%
CORE_PREF_MLC_DEMAND_LATENCY600 87669 7.744% 87669 7.744%
CORE_PREF_MLC_DEMAND_LATENCY700 179552 15.860% 179552 15.860%
CORE_PREF_MLC_DEMAND_LATENCY800 167891 14.830% 167891 14.830%
CORE_PREF_MLC_DEMAND_LATENCY900 173113 15.291% 173113 15.291%
CORE_PREF_MLC_DEMAND_LATENCY1000 50960 4.501% 50960 4.501%
CORE_PREF_MLC_DEMAND_LATENCY1000MORE 364978 32.239% 364978 32.239%
 1132101 100.000% 1132101 100.000%
 5.47 3.62 5.47 3.62
TOTAL_BATCH_FORMED 0 0
TOTAL_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan
CORE_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan
CORE_BATCH_MEM_REQ_MARKED_DEMAND 0 -nan 0 -nan
CORE_BATCH_MEM_REQ_MARKED_PREF 0 -nan 0 -nan
DRAM_ROW_BATCHES 0 0
REJECTED_QUEUE_MLC 0 0
REJECTED_QUEUE_L1 2 2
REJECTED_QUEUE_BUS_OUT 0 0
LEADING_LOAD_LATENCY 0 0.0000 0 0.0000
LEADING_LOADS 0 0.0000 0 0.0000
MEM_REQ_CRITICAL_PATH_LENGTH 0 0.0000 0 0.0000
TOTAL_MEM_REQ_LATENCY 0 0
TOTAL_CRITICAL_MEM_REQ_LATENCY 0 -nan 0 -nan
TOTAL_CRITICAL_BANK_LATENCY 0 -nan 0 -nan
TOTAL_MEMORY_SLACK 0 0.0000 0 0.0000
TOTAL_CHIP_UTILIZATION 0 0.0000 0 0.0000
CHIP_BUSY_UNDER_CRITICAL_REQS 0 0.0000 0 0.0000
PERF_PRED_NUM_STAT_RESETS 0 0
PERF_PRED_RESET_STATS_CYCLE 0 0
PERF_PRED_CYCLE 40347914 40347914
ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000
NUM_WINDOWS_WITH_DCACHE_MISS 3695 3695
LONGEST_DCACHE_MISS_CHAIN 14005 14005
NUM_DCACHE_MISSES_IN_WINDOW_1 727 19.675% 727 19.675%
NUM_DCACHE_MISSES_IN_WINDOW_2 183 4.953% 183 4.953%
NUM_DCACHE_MISSES_IN_WINDOW_3 591 15.995% 591 15.995%
NUM_DCACHE_MISSES_IN_WINDOW_4 554 14.993% 554 14.993%
NUM_DCACHE_MISSES_IN_WINDOW_5 1003 27.145% 1003 27.145%
NUM_DCACHE_MISSES_IN_WINDOW_6 84 2.273% 84 2.273%
NUM_DCACHE_MISSES_IN_WINDOW_7 68 1.840% 68 1.840%
NUM_DCACHE_MISSES_IN_WINDOW_8 43 1.164% 43 1.164%
NUM_DCACHE_MISSES_IN_WINDOW_9 44 1.191% 44 1.191%
NUM_DCACHE_MISSES_IN_WINDOW_10 36 0.974% 36 0.974%
NUM_DCACHE_MISSES_IN_WINDOW_11 30 0.812% 30 0.812%
NUM_DCACHE_MISSES_IN_WINDOW_12 45 1.218% 45 1.218%
NUM_DCACHE_MISSES_IN_WINDOW_13 29 0.785% 29 0.785%
NUM_DCACHE_MISSES_IN_WINDOW_14 23 0.622% 23 0.622%
NUM_DCACHE_MISSES_IN_WINDOW_15 26 0.704% 26 0.704%
NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 209 5.656% 209 5.656%
 3695 100.000% 3695 100.000%
 3.73 3.53 3.73 3.53
DCACHE_MLP_IN_WINDOW_1_0 2096 56.725% 2096 56.725%
DCACHE_MLP_IN_WINDOW_1_5 1046 28.309% 1046 28.309%
DCACHE_MLP_IN_WINDOW_2_0 269 7.280% 269 7.280%
DCACHE_MLP_IN_WINDOW_2_5 121 3.275% 121 3.275%
DCACHE_MLP_IN_WINDOW_3_0 115 3.112% 115 3.112%
DCACHE_MLP_IN_WINDOW_3_5 17 0.460% 17 0.460%
DCACHE_MLP_IN_WINDOW_4_0 10 0.271% 10 0.271%
DCACHE_MLP_IN_WINDOW_4_5 9 0.244% 9 0.244%
DCACHE_MLP_IN_WINDOW_5_0 9 0.244% 9 0.244%
DCACHE_MLP_IN_WINDOW_5_5 1 0.027% 1 0.027%
DCACHE_MLP_IN_WINDOW_6_0 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_6_5 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_7_0 1 0.027% 1 0.027%
DCACHE_MLP_IN_WINDOW_7_5 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_8_0 1 0.027% 1 0.027%
DCACHE_MLP_IN_WINDOW_8_5_OR_MORE 0 0.000% 0 0.000%
 3695 100.000% 3695 100.000%
 0.74 1.06 0.74 1.06
PARAM_CHIP_CYCLE_TIME 0 0
PARAM_CORE_CYCLE_TIME 312500 312500
PARAM_L1_CYCLE_TIME 312500 312500
PARAM_MEMORY_CYCLE_TIME 833333 833333
MEM_REQ_NON_SCHEDULED__0 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED__4 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED__8 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_12 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_16 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_20 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_24 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_28 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_32 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_36 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_40 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_44 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_48 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_52 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_56 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_60 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_64 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_DEMANDS__0 1226210 3.039% 1226210 3.039%
MEM_REQ_DEMANDS__4 98546 0.244% 98546 0.244%
MEM_REQ_DEMANDS__8 30774 0.076% 30774 0.076%
MEM_REQ_DEMANDS_12 52726 0.131% 52726 0.131%
MEM_REQ_DEMANDS_16 178644 0.443% 178644 0.443%
MEM_REQ_DEMANDS_20 625476 1.550% 625476 1.550%
MEM_REQ_DEMANDS_24 12093658 29.973% 12093658 29.973%
MEM_REQ_DEMANDS_28 26041880 64.543% 26041880 64.543%
MEM_REQ_DEMANDS_32 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_36 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_40 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_44 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_48 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_52 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_56 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_60 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_64 0 0.000% 0 0.000%
 40347914 100.000% 40347914 100.000%
 6.42 0.66 6.42 0.66
MEM_REQ_PREFS__0 39577025 98.089% 39577025 98.089%
MEM_REQ_PREFS__4 118608 0.294% 118608 0.294%
MEM_REQ_PREFS__8 77871 0.193% 77871 0.193%
MEM_REQ_PREFS_12 68691 0.170% 68691 0.170%
MEM_REQ_PREFS_16 79892 0.198% 79892 0.198%
MEM_REQ_PREFS_20 94875 0.235% 94875 0.235%
MEM_REQ_PREFS_24 303088 0.751% 303088 0.751%
MEM_REQ_PREFS_28 27864 0.069% 27864 0.069%
MEM_REQ_PREFS_32 0 0.000% 0 0.000%
MEM_REQ_PREFS_36 0 0.000% 0 0.000%
MEM_REQ_PREFS_40 0 0.000% 0 0.000%
MEM_REQ_PREFS_44 0 0.000% 0 0.000%
MEM_REQ_PREFS_48 0 0.000% 0 0.000%
MEM_REQ_PREFS_52 0 0.000% 0 0.000%
MEM_REQ_PREFS_56 0 0.000% 0 0.000%
MEM_REQ_PREFS_60 0 0.000% 0 0.000%
MEM_REQ_PREFS_64 0 0.000% 0 0.000%
 40347914 100.000% 40347914 100.000%
 0.08 0.64 0.08 0.64
MEM_REQ_WRITEBACKS__0 32571017 80.725% 32571017 80.725%
MEM_REQ_WRITEBACKS__4 7166217 17.761% 7166217 17.761%
MEM_REQ_WRITEBACKS__8 511489 1.268% 511489 1.268%
MEM_REQ_WRITEBACKS_12 82818 0.205% 82818 0.205%
MEM_REQ_WRITEBACKS_16 16297 0.040% 16297 0.040%
MEM_REQ_WRITEBACKS_20 52 0.000% 52 0.000%
MEM_REQ_WRITEBACKS_24 24 0.000% 24 0.000%
MEM_REQ_WRITEBACKS_28 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_32 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_36 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_40 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_44 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_48 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_52 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_56 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_60 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_64 0 0.000% 0 0.000%
 40347914 100.000% 40347914 100.000%
 0.21 0.42 0.21 0.42
MEM_REQ_DEMAND_CYCLES 1114997520 1114997520
MEM_REQ_PREF_CYCLES 14850472 14850472
MEM_REQ_WB_CYCLES 64667841 64667841
DRAM_CHANNEL_REQS 0 0
DRAM_CHANNEL_CRIT_REQS 0 0
DRAM_CHANNEL_CRIT_DIR_SWITCHES 0 0
DRAM_BANK_CRIT_REQS 0 0
DRAM_INSTA_MLP_SAMPLES 0 0
DRAM_INSTA_MLP_UNIQUE_REQS 0 -nan 0 -nan
DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000 0 -nan 0 -nan
DRAM_GLOBAL_MLP 0 -nan 0 -nan
DRAM_GLOBAL_MLP_0 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_1 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_2 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_3 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_4 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_5 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_6 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_7 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_8 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_9 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_10 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_11 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_12 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_13 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_14 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_15 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_16 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_TOTAL_GLOBAL_MLP_0 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_1 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_2 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_3 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_4 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_5 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_6 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_7 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_8 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_9 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_10 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_11 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_12 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_13 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_14 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_15 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_16 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_17 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_18 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_19 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_20 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_21 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_22 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_23 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_24 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_25 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_26 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_27 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_28 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_29 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_30 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_31 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_32 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
UNIQUE_ROWS_PER_BANK_0 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_1 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_2 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_3 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_4 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_5 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_6 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_7 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_UNIQUE_ROWS_PER_BANK_0 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_1 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_2 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_3 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_4 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_5 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_6 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_7 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORES_PER_BANK_0 0 -nan% 0 -nan%
CORES_PER_BANK_1 0 -nan% 0 -nan%
CORES_PER_BANK_2 0 -nan% 0 -nan%
CORES_PER_BANK_3 0 -nan% 0 -nan%
CORES_PER_BANK_4 0 -nan% 0 -nan%
CORES_PER_BANK_5 0 -nan% 0 -nan%
CORES_PER_BANK_6 0 -nan% 0 -nan%
CORES_PER_BANK_7 0 -nan% 0 -nan%
CORES_PER_BANK_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_BANKS_WITH_REQS_0 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_1 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_2 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_3 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_4 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_5 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_6 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_7 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_8 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_9 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_10 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_11 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_12 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_13 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_14 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_15 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_16 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_BANKS_WITH_REQS 0 0
DRAM_CHANNEL_IN_DEMAND 0 0
DRAM_BUS_IN_DEMAND 0 0
DRAM_BANK_IN_DEMAND 0 0
DRAM_BANK_IN_DEMAND_STALLING 0 0
DRAM_ANY_BANK_IN_DEMAND 0 0
DRAM_BANK_IN_DEMAND_BANK_0 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_1 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_2 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_3 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_4 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_5 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_6 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_7 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_8 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_9 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_10 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_11 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_12 0 -nan% 0 -nan%
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DRAM_STALLED_BY_OTHER_CORE 0 0
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DRAM_BANK_WAIT_CYCLES_ROW_MISS 0 0
DRAM_BANK_WAIT_CYCLES_ROW_HIT 0 0
DRAM_ROW_OPEN_WAIT 0 0
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EQUAL_USE_BW_BUS_PLUS_FAW2 0 0
EQUAL_USE_BW_BUS_PLUS_FAW3 0 0
EQUAL_USE_BW_CRIT_PATH 0 0
EQUAL_USE_BW_BLACK_BOX 0 0
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DRAM_ACTIVATE_TO_COLUMN_LATENCY 0 0
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DRAM_ACTIVATE_TO_READ_LATENCY 0 -nan 0 -nan
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DRAM_NUM_REQS_10_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_10_WB 0 -nan 0 -nan
DRAM_NUM_REQS_10_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_11_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_11_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_11_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_11_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_11_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_11_WB 0 -nan 0 -nan
DRAM_NUM_REQS_11_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_12_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_12_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_12_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_12_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_12_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_12_WB 0 -nan 0 -nan
DRAM_NUM_REQS_12_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_13_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_13_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_13_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_13_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_13_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_13_WB 0 -nan 0 -nan
DRAM_NUM_REQS_13_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_14_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_14_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_14_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_14_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_14_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_14_WB 0 -nan 0 -nan
DRAM_NUM_REQS_14_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_15_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_15_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_15_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_15_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_15_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_15_WB 0 -nan 0 -nan
DRAM_NUM_REQS_15_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_16_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_16_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_16_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_16_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_16_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_16_WB 0 -nan 0 -nan
DRAM_NUM_REQS_16_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_17_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_17_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_17_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_17_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_17_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_17_WB 0 -nan 0 -nan
DRAM_NUM_REQS_17_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_18_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_18_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_18_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_18_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_18_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_18_WB 0 -nan 0 -nan
DRAM_NUM_REQS_18_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_19_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_19_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_19_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_19_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_19_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_19_WB 0 -nan 0 -nan
DRAM_NUM_REQS_19_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_20_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_20_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_20_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_20_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_20_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_20_WB 0 -nan 0 -nan
DRAM_NUM_REQS_20_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_21_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_21_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_21_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_21_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_21_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_21_WB 0 -nan 0 -nan
DRAM_NUM_REQS_21_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_22_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_22_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_22_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_22_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_22_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_22_WB 0 -nan 0 -nan
DRAM_NUM_REQS_22_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_23_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_23_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_23_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_23_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_23_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_23_WB 0 -nan 0 -nan
DRAM_NUM_REQS_23_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_24_WB 0 -nan 0 -nan
DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_25_WB 0 -nan 0 -nan
DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_26_WB 0 -nan 0 -nan
DRAM_NUM_REQS_26_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_27_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_27_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_27_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_27_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_27_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_27_WB 0 -nan 0 -nan
DRAM_NUM_REQS_27_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_28_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_28_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_28_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_28_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_28_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_28_WB 0 -nan 0 -nan
DRAM_NUM_REQS_28_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_29_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_29_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_29_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_29_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_29_WB 0 -nan 0 -nan
DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_30_WB 0 -nan 0 -nan
DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_31_WB 0 -nan 0 -nan
DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_32_WB 0 -nan 0 -nan
DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan
DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0
KNOWN_BAD_ADDRESS 0 0.000% 0 0.000%
GOOD_ADDRESS 99368332 100.000% 99368332 100.000%
 99368332 100.000% 99368332 100.000%
 1.00 1.00 1.00 1.00
BBL_LENGTH_1 0 -nan% 0 -nan%
BBL_LENGTH_2 0 -nan% 0 -nan%
BBL_LENGTH_3 0 -nan% 0 -nan%
BBL_LENGTH_4 0 -nan% 0 -nan%
BBL_LENGTH_5 0 -nan% 0 -nan%
BBL_LENGTH_6 0 -nan% 0 -nan%
BBL_LENGTH_7 0 -nan% 0 -nan%
BBL_LENGTH_8 0 -nan% 0 -nan%
BBL_LENGTH_9 0 -nan% 0 -nan%
BBL_LENGTH_10 0 -nan% 0 -nan%
BBL_LENGTH_11 0 -nan% 0 -nan%
BBL_LENGTH_12 0 -nan% 0 -nan%
BBL_LENGTH_13 0 -nan% 0 -nan%
BBL_LENGTH_14 0 -nan% 0 -nan%
BBL_LENGTH_15 0 -nan% 0 -nan%
BBL_LENGTH_16 0 -nan% 0 -nan%
BBL_LENGTH_17 0 -nan% 0 -nan%
BBL_LENGTH_18 0 -nan% 0 -nan%
BBL_LENGTH_19 0 -nan% 0 -nan%
BBL_LENGTH_20 0 -nan% 0 -nan%
BBL_LENGTH_21 0 -nan% 0 -nan%
BBL_LENGTH_22 0 -nan% 0 -nan%
BBL_LENGTH_23 0 -nan% 0 -nan%
BBL_LENGTH_24 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
BBL_DONT_END_PRED_NT_LENGTH_1 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_2 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_3 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_4 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_5 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_6 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_7 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_8 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_9 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_10 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_11 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_12 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_13 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_14 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_15 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_16 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_17 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_18 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_19 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_20 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_21 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_22 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_23 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_24 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DATA_LD_CYCLES_ONPATH 1115293520 1115293520
DATA_LD_CYCLES_OFFPATH 33864 33864
DATA_LD_MLC_CYCLES_ONPATH 404558 404558
DATA_LD_MLC_CYCLES_OFFPATH 18865 18865
DATA_LD_MLC_ACCESSES_ONPATH 20139 20139
DATA_LD_MLC_ACCESSES_OFFPATH 936 936
DATA_LD_L1_CYCLES_ONPATH 299328 299328
DATA_LD_L1_CYCLES_OFFPATH 568 568
DATA_LD_L1_ACCESSES_ONPATH 4677 4677
DATA_LD_L1_ACCESSES_OFFPATH 9 9
DATA_LD_MEM_CYCLES_ONPATH 1114589634 1114589634
DATA_LD_MEM_CYCLES_OFFPATH 14431 14431
DATA_LD_MEM_ACCESSES_ONPATH 1196627 1196627
DATA_LD_MEM_ACCESSES_OFFPATH 37 37
DATA_LD_PREF_CYCLES_ONPATH 0 0
DATA_LD_PREF_CYCLES_OFFPATH 0 0
DATA_LD_PREF_MLC_CYCLES_ONPATH 0 0
DATA_LD_PREF_MLC_CYCLES_OFFPATH 0 0
DATA_LD_PREF_L1_CYCLES_ONPATH 0 0
DATA_LD_PREF_L1_CYCLES_OFFPATH 0 0
DATA_LD_PREF_MEM_CYCLES_ONPATH 0 0
DATA_LD_PREF_MEM_CYCLES_OFFPATH 0 0
UOP_CACHE_LINE_EVICTED_USEFUL 26211 26.907% 26211 26.907%
UOP_CACHE_LINE_EVICTED_USELESS 71203 73.093% 71203 73.093%
 97414 100.000% 97414 100.000%
 0.73 0.67 0.73 0.67