hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /12 /core.stat.0.csv
| Core, 0, 0 | |
| Cumulative_Cycles, 0, 336256 | |
| Cumulative_Instructions, 0, 961103 | |
| Periodic_Cycles, 0, 336256 | |
| Periodic_Instructions, 0, 961103 | |
| EXECUTION_TIME_count, 0, 105080000000 | |
| EXECUTION_TIME_total_count, 0, 105080000000 | |
| SIM_HOST_WALL_SECONDS_value, 0, 2.612259 | |
| SIM_HOST_WALL_SECONDS_total_value, 0, 2.612259 | |
| NODE_CYCLE_count, 0, 336256 | |
| NODE_CYCLE_total_count, 0, 336256 | |
| NODE_INST_COUNT_count, 0, 961103 | |
| NODE_INST_COUNT_total_count, 0, 961103 | |
| NODE_INST_COUNT_FETCHED_count, 0, 961103 | |
| NODE_INST_COUNT_FETCHED_total_count, 0, 961103 | |
| NODE_UOP_COUNT_count, 0, 1261450 | |
| NODE_UOP_COUNT_total_count, 0, 1261450 | |
| EXEC_STAGE_NO_ISSUE_STALL_CYCLE_count, 0, 294298 | |
| EXEC_STAGE_NO_ISSUE_STALL_CYCLE_total_count, 0, 294298 | |
| EXEC_STAGE_NO_ISSUE_STALL_CYCLE_ONPATH_count, 0, 293944 | |
| EXEC_STAGE_NO_ISSUE_STALL_CYCLE_ONPATH_total_count, 0, 293944 | |
| FULL_WINDOW_STALL_count, 0, 0 | |
| FULL_WINDOW_STALL_pct, 0, 0.000 | |
| FULL_WINDOW_STALL_total_count, 0, 0 | |
| FULL_WINDOW_STALL_total_pct, 0, 0.000 | |
| FULL_WINDOW_MEM_OP_count, 401, 0 | |
| FULL_WINDOW_MEM_OP_total_count, 401, 0 | |
| FULL_WINDOW_FP_OP_count, 401, 0 | |
| FULL_WINDOW_FP_OP_total_count, 401, 0 | |
| FULL_WINDOW_OTHER_OP_count, 401, 0 | |
| FULL_WINDOW_OTHER_OP_total_count, 401, 0 | |
| RET_BLOCKED_DC_MISS_count, 0, 66524 | |
| RET_BLOCKED_DC_MISS_pct, 0, 19.784 | |
| RET_BLOCKED_DC_MISS_total_count, 0, 66524 | |
| RET_BLOCKED_DC_MISS_total_pct, 0, 19.784 | |
| RET_BLOCKED_L1_MISS_count, 0, 14156 | |
| RET_BLOCKED_L1_MISS_pct, 0, 4.210 | |
| RET_BLOCKED_L1_MISS_total_count, 0, 14156 | |
| RET_BLOCKED_L1_MISS_total_pct, 0, 4.210 | |
| RET_BLOCKED_L1_MISS_BW_PREF_count, 0, 12922 | |
| RET_BLOCKED_L1_MISS_BW_PREF_pct, 0, 3.843 | |
| RET_BLOCKED_L1_MISS_BW_PREF_total_count, 0, 12922 | |
| RET_BLOCKED_L1_MISS_BW_PREF_total_pct, 0, 3.843 | |
| RET_BLOCKED_L1_ACCESS_count, 0, 52368 | |
| RET_BLOCKED_L1_ACCESS_pct, 0, 15.574 | |
| RET_BLOCKED_L1_ACCESS_total_count, 0, 52368 | |
| RET_BLOCKED_L1_ACCESS_total_pct, 0, 15.574 | |
| RET_BLOCKED_MEM_STALL_count, 0, 14156 | |
| RET_BLOCKED_MEM_STALL_pct, 0, 4.210 | |
| RET_BLOCKED_MEM_STALL_total_count, 0, 14156 | |
| RET_BLOCKED_MEM_STALL_total_pct, 0, 4.210 | |
| RET_BLOCKED_OFFCHIP_DEMAND_count, 0, 0 | |
| RET_BLOCKED_OFFCHIP_DEMAND_pct, 0, 0.000 | |
| RET_BLOCKED_OFFCHIP_DEMAND_total_count, 0, 0 | |
| RET_BLOCKED_OFFCHIP_DEMAND_total_pct, 0, 0.000 | |
| OP_ISSUED_count, 0, 1262930 | |
| OP_ISSUED_total_count, 0, 1262930 | |
| OP_RETIRED_count, 0, 1261450 | |
| OP_RETIRED_total_count, 0, 1261450 | |
| OP_MACRO_FUSION_ONPATH_count, 0, 90103 | |
| OP_MACRO_FUSION_ONPATH_total_count, 0, 90103 | |
| OP_MACRO_FUSION_OFFPATH_count, 0, 40 | |
| OP_MACRO_FUSION_OFFPATH_total_count, 0, 40 | |
| REPLAY_SIGNALED_count, 0, 0 | |
| REPLAY_SIGNALED_total_count, 0, 0 | |
| REPLAY_COUNTED_count, 0, 0 | |
| REPLAY_COUNTED_total_count, 0, 0 | |
| OFF_CRITICAL_PATH_count, 402, 0 | |
| OFF_CRITICAL_PATH_total_count, 402, 0 | |
| ON_CRITICAL_PATH_count, 402, 0 | |
| ON_CRITICAL_PATH_total_count, 402, 0 | |
| LD_NO_DEPENDENTS_count, 403, 7 | |
| LD_NO_DEPENDENTS_total_count, 403, 7 | |
| LD_DEPENDENTS_count, 403, 240272 | |
| LD_DEPENDENTS_total_count, 403, 240272 | |
| LD_EXEC_CYCLES_0_count, 404, 0 | |
| LD_EXEC_CYCLES_0_total_count, 404, 0 | |
| LD_EXEC_CYCLES_1_count, 404, 0 | |
| LD_EXEC_CYCLES_1_total_count, 404, 0 | |
| LD_EXEC_CYCLES_2_count, 404, 0 | |
| LD_EXEC_CYCLES_2_total_count, 404, 0 | |
| LD_EXEC_CYCLES_3_count, 404, 0 | |
| LD_EXEC_CYCLES_3_total_count, 404, 0 | |
| LD_EXEC_CYCLES_4_count, 404, 0 | |
| LD_EXEC_CYCLES_4_total_count, 404, 0 | |
| ICACHE_STAGE_STARVED_count, 405, 1440 | |
| ICACHE_STAGE_STARVED_total_count, 405, 1440 | |
| ICACHE_STAGE_NOT_STARVED_count, 405, 333847 | |
| ICACHE_STAGE_NOT_STARVED_total_count, 405, 333847 | |
| ICACHE_STAGE_STALLED_count, 406, 138624 | |
| ICACHE_STAGE_STALLED_total_count, 406, 138624 | |
| ICACHE_STAGE_NOT_STALLED_count, 406, 196663 | |
| ICACHE_STAGE_NOT_STALLED_total_count, 406, 196663 | |
| ICACHE_STAGE_OFF_PATH_count, 406, 969 | |
| ICACHE_STAGE_OFF_PATH_total_count, 406, 969 | |
| DECODE_STAGE_STARVED_count, 407, 335332 | |
| DECODE_STAGE_STARVED_total_count, 407, 335332 | |
| DECODE_STAGE_NOT_STARVED_count, 407, 22 | |
| DECODE_STAGE_NOT_STARVED_total_count, 407, 22 | |
| DECODE_STAGE_STALLED_count, 408, 7 | |
| DECODE_STAGE_STALLED_total_count, 408, 7 | |
| DECODE_STAGE_NOT_STALLED_count, 408, 335347 | |
| DECODE_STAGE_NOT_STALLED_total_count, 408, 335347 | |
| DECODE_STAGE_OFF_PATH_count, 408, 902 | |
| DECODE_STAGE_OFF_PATH_total_count, 408, 902 | |
| UOPQ_STAGE_STARVED_count, 409, 2035 | |
| UOPQ_STAGE_STARVED_total_count, 409, 2035 | |
| UOPQ_STAGE_NOT_STARVED_count, 409, 195211 | |
| UOPQ_STAGE_NOT_STARVED_total_count, 409, 195211 | |
| UOPQ_STAGE_STALLED_count, 410, 138624 | |
| UOPQ_STAGE_STALLED_total_count, 410, 138624 | |
| UOPQ_STAGE_NOT_STALLED_count, 410, 197246 | |
| UOPQ_STAGE_NOT_STALLED_total_count, 410, 197246 | |
| UOPQ_STAGE_OFF_PATH_count, 410, 386 | |
| UOPQ_STAGE_OFF_PATH_total_count, 410, 386 | |
| RS_OP_READY_NOT_ISSUED_TOTAL_count, 0, 242290 | |
| RS_OP_READY_NOT_ISSUED_TOTAL_total_count, 0, 242290 | |
| RS_0_OP_READY_NOT_ISSUED_count, 0, 93472 | |
| RS_0_OP_READY_NOT_ISSUED_total_count, 0, 93472 | |
| RS_1_OP_READY_NOT_ISSUED_count, 0, 807 | |
| RS_1_OP_READY_NOT_ISSUED_total_count, 0, 807 | |
| RS_2_OP_READY_NOT_ISSUED_count, 0, 148011 | |
| RS_2_OP_READY_NOT_ISSUED_total_count, 0, 148011 | |
| RS_3_OP_READY_NOT_ISSUED_count, 0, 0 | |
| RS_3_OP_READY_NOT_ISSUED_total_count, 0, 0 | |
| RS_4_OP_READY_NOT_ISSUED_count, 0, 0 | |
| RS_4_OP_READY_NOT_ISSUED_total_count, 0, 0 | |
| RS_5_OP_READY_NOT_ISSUED_count, 0, 0 | |
| RS_5_OP_READY_NOT_ISSUED_total_count, 0, 0 | |
| RS_6_OP_READY_NOT_ISSUED_count, 0, 0 | |
| RS_6_OP_READY_NOT_ISSUED_total_count, 0, 0 | |
| RS_7_OP_READY_NOT_ISSUED_count, 0, 0 | |
| RS_7_OP_READY_NOT_ISSUED_total_count, 0, 0 | |
| RS_7_PLUS_OP_READY_NOT_ISSUED_count, 0, 0 | |
| RS_7_PLUS_OP_READY_NOT_ISSUED_total_count, 0, 0 | |
| FU_IDLE_NO_READY_OPS_TOTAL_count, 0, 996891 | |
| FU_IDLE_NO_READY_OPS_TOTAL_total_count, 0, 996891 | |
| FU_0_IDLE_NO_READY_OPS_count, 0, 36384 | |
| FU_0_IDLE_NO_READY_OPS_total_count, 0, 36384 | |
| FU_1_IDLE_NO_READY_OPS_count, 0, 51508 | |
| FU_1_IDLE_NO_READY_OPS_total_count, 0, 51508 | |
| FU_2_IDLE_NO_READY_OPS_count, 0, 135668 | |
| FU_2_IDLE_NO_READY_OPS_total_count, 0, 135668 | |
| FU_3_IDLE_NO_READY_OPS_count, 0, 135714 | |
| FU_3_IDLE_NO_READY_OPS_total_count, 0, 135714 | |
| FU_4_IDLE_NO_READY_OPS_count, 0, 54045 | |
| FU_4_IDLE_NO_READY_OPS_total_count, 0, 54045 | |
| FU_5_IDLE_NO_READY_OPS_count, 0, 34695 | |
| FU_5_IDLE_NO_READY_OPS_total_count, 0, 34695 | |
| FU_6_IDLE_NO_READY_OPS_count, 0, 177617 | |
| FU_6_IDLE_NO_READY_OPS_total_count, 0, 177617 | |
| FU_7_IDLE_NO_READY_OPS_count, 0, 182705 | |
| FU_7_IDLE_NO_READY_OPS_total_count, 0, 182705 | |
| FU_8_IDLE_NO_READY_OPS_count, 0, 52892 | |
| FU_8_IDLE_NO_READY_OPS_total_count, 0, 52892 | |
| FU_9_IDLE_NO_READY_OPS_count, 0, 135663 | |
| FU_9_IDLE_NO_READY_OPS_total_count, 0, 135663 | |
| FU_10_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_10_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_11_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_11_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_12_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_12_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_13_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_13_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_14_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_14_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_15_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_15_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_16_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_16_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_17_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_17_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_18_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_18_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_19_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_19_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_20_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_20_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_21_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_21_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_22_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_22_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_23_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_23_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_24_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_24_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_25_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_25_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_26_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_26_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_27_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_27_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_28_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_28_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_29_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_29_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_30_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_30_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_31_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_31_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| FU_31_PLUS_IDLE_NO_READY_OPS_count, 0, 0 | |
| FU_31_PLUS_IDLE_NO_READY_OPS_total_count, 0, 0 | |
| MAP_STAGE_STARVED_count, 411, 1455 | |
| MAP_STAGE_STARVED_total_count, 411, 1455 | |
| MAP_STAGE_NOT_STARVED_count, 411, 210248 | |
| MAP_STAGE_NOT_STARVED_total_count, 411, 210248 | |
| MAP_STAGE_STALLED_count, 412, 0 | |
| MAP_STAGE_STALLED_total_count, 412, 0 | |
| MAP_STAGE_NOT_STALLED_count, 412, 211703 | |
| MAP_STAGE_NOT_STALLED_total_count, 412, 211703 | |
| MAP_STAGE_OFF_PATH_count, 412, 660 | |
| MAP_STAGE_OFF_PATH_total_count, 412, 660 | |
| MAP_STAGE_STALL_ITSELF_count, 413, 123893 | |
| MAP_STAGE_STALL_ITSELF_total_count, 413, 123893 | |
| MAP_STAGE_NOT_STALL_ITSELF_count, 413, 212363 | |
| MAP_STAGE_NOT_STALL_ITSELF_total_count, 413, 212363 | |
| MAP_STAGE_LATE_ALLOCATE_SEND_BACK_count, 0, 0 | |
| MAP_STAGE_LATE_ALLOCATE_SEND_BACK_total_count, 0, 0 | |
| MAP_STAGE_RENAME_OP_ONPATH_count, 0, 1261450 | |
| MAP_STAGE_RENAME_OP_ONPATH_total_count, 0, 1261450 | |
| MAP_STAGE_RENAME_OP_OFFPATH_count, 0, 1600 | |
| MAP_STAGE_RENAME_OP_OFFPATH_total_count, 0, 1600 | |
| MAP_STAGE_RENAME_INT_REG_ONPATH_count, 0, 1066229 | |
| MAP_STAGE_RENAME_INT_REG_ONPATH_total_count, 0, 1066229 | |
| MAP_STAGE_RENAME_INT_REG_OFFPATH_count, 0, 511 | |
| MAP_STAGE_RENAME_INT_REG_OFFPATH_total_count, 0, 511 | |
| MAP_STAGE_RENAME_VEC_REG_ONPATH_count, 0, 0 | |
| MAP_STAGE_RENAME_VEC_REG_ONPATH_total_count, 0, 0 | |
| MAP_STAGE_RENAME_VEC_REG_OFFPATH_count, 0, 0 | |
| MAP_STAGE_RENAME_VEC_REG_OFFPATH_total_count, 0, 0 | |
| MAP_STAGE_RENAME_MOVE_ELIM_ONPATH_count, 0, 0 | |
| MAP_STAGE_RENAME_MOVE_ELIM_ONPATH_total_count, 0, 0 | |
| MAP_STAGE_RENAME_MOVE_ELIM_OFFPATH_count, 0, 0 | |
| MAP_STAGE_RENAME_MOVE_ELIM_OFFPATH_total_count, 0, 0 | |
| REG_FILE_UTIL_SAMPLES_count, 0, 336256 | |
| REG_FILE_UTIL_SAMPLES_total_count, 0, 336256 | |
| REG_FILE_INT_PHYS_REGS_SUM_count, 0, 94151680 | |
| REG_FILE_INT_PHYS_REGS_SUM_total_count, 0, 94151680 | |
| REG_FILE_VEC_PHYS_REGS_SUM_count, 0, 111636992 | |
| REG_FILE_VEC_PHYS_REGS_SUM_total_count, 0, 111636992 | |
| REG_FILE_INT_OCCUPIED_SUM_count, 0, 83986628 | |
| REG_FILE_INT_OCCUPIED_SUM_total_count, 0, 83986628 | |
| REG_FILE_VEC_OCCUPIED_SUM_count, 0, 10760192 | |
| REG_FILE_VEC_OCCUPIED_SUM_total_count, 0, 10760192 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_ALLOC_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_ALLOC_total_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_ALLOC_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_ALLOC_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_SHORTLIVE_count, 0, 431885 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_SHORTLIVE_total_count, 0, 431885 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_SHORTLIVE_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_SHORTLIVE_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_0_count, 0, 195224 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_0_total_count, 0, 195224 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_0_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_0_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_1_count, 0, 570649 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_1_total_count, 0, 570649 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_1_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_1_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_2_count, 0, 195226 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_2_total_count, 0, 195226 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_2_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_2_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_3_count, 0, 90102 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_3_total_count, 0, 90102 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_3_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_3_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_4_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_4_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_4_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_4_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_5_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_5_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_5_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_5_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_6_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_6_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_6_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_6_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_7_PLUS_count, 0, 15017 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_7_PLUS_total_count, 0, 15017 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_7_PLUS_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_7_PLUS_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_0_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_0_pct, 0, 0.000 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_0_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_0_total_pct, 0, 0.000 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_0_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_0_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_0_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_0_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_1_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_1_pct, 0, 0.000 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_1_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_1_total_pct, 0, 0.000 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_1_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_1_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_1_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_1_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_2_count, 0, 83873 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_2_pct, 0, 0.430 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_2_total_count, 0, 83873 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_2_total_pct, 0, 0.430 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_2_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_2_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_2_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_2_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_3_count, 0, 1910863 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_3_pct, 0, 21.208 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_3_total_count, 0, 1910863 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_3_total_pct, 0, 21.208 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_3_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_3_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_3_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_3_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_4_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_4_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_4_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_4_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_4_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_4_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_4_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_4_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_5_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_5_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_5_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_5_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_5_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_5_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_5_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_5_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_6_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_6_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_6_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_6_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_6_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_6_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_6_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_6_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_7_PLUS_count, 0, 90983 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_7_PLUS_pct, 0, 6.059 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_7_PLUS_total_count, 0, 90983 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_7_PLUS_total_pct, 0, 6.059 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_7_PLUS_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_7_PLUS_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_7_PLUS_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_7_PLUS_total_pct, 0, -nan | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_count, 0, 1352074 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_pct, 0, 4.594 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_total_count, 0, 1352074 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_total_pct, 0, 4.594 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_pct, 0, 0.000 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_total_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_total_pct, 0, 0.000 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_count, 0, 480752 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_pct, 0, 1.634 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_total_count, 0, 480752 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_total_pct, 0, 1.634 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_pct, 0, 0.000 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_total_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_total_pct, 0, 0.000 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_count, 0, 245167 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_pct, 0, 0.833 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_total_count, 0, 245167 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_total_pct, 0, 0.833 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_pct, 0, 0.000 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_total_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_total_pct, 0, 0.000 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_count, 0, 1351554 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_pct, 0, 4.598 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_total_count, 0, 1351554 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_total_pct, 0, 4.598 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_pct, 0, 0.000 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_total_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH_total_pct, 0, 0.000 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_count, 0, 480551 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_pct, 0, 1.635 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_total_count, 0, 480551 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_total_pct, 0, 1.635 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_pct, 0, 0.000 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_total_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH_total_pct, 0, 0.000 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_count, 0, 245052 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_pct, 0, 0.834 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_total_count, 0, 245052 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_total_pct, 0, 0.834 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_pct, 0, 0.000 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_total_count, 0, 0 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH_total_pct, 0, 0.000 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_EMPTY_count, 0, 22991462 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_EMPTY_total_count, 0, 22991462 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_EMPTY_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_EMPTY_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_IN_USE_count, 0, 36517183 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_IN_USE_total_count, 0, 36517183 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_IN_USE_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_IN_USE_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_SPEC_RELEASE_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_SPEC_RELEASE_total_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_SPEC_RELEASE_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_SPEC_RELEASE_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_NONSPEC_RELEASE_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_NONSPEC_RELEASE_total_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_NONSPEC_RELEASE_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_NONSPEC_RELEASE_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_TOTAL_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_TOTAL_total_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_TOTAL_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_TOTAL_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_NONBRANCH_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_NONBRANCH_total_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_NONBRANCH_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_NONBRANCH_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_NONEXCEPT_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_NONEXCEPT_total_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_NONEXCEPT_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_NONEXCEPT_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_ATOMIC_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_ATOMIC_total_count, 0, 1066218 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_ATOMIC_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_ATOMIC_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_REDEFINED_DIST_TOTAL_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_REDEFINED_DIST_TOTAL_pct, 0, 75.292 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_REDEFINED_DIST_TOTAL_total_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_REDEFINED_DIST_TOTAL_total_pct, 0, 75.292 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_REDEFINED_DIST_TOTAL_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_REDEFINED_DIST_TOTAL_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_REDEFINED_DIST_TOTAL_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_REDEFINED_DIST_TOTAL_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_CONSUMED_DIST_TOTAL_count, 0, 36517183 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_CONSUMED_DIST_TOTAL_pct, 0, 34.249 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_CONSUMED_DIST_TOTAL_total_count, 0, 36517183 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_CONSUMED_DIST_TOTAL_total_pct, 0, 34.249 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_CONSUMED_DIST_TOTAL_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_CONSUMED_DIST_TOTAL_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_CONSUMED_DIST_TOTAL_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_CONSUMED_DIST_TOTAL_total_pct, 0, -nan | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_RELEASE_DIST_TOTAL_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_RELEASE_DIST_TOTAL_pct, 0, 75.292 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_RELEASE_DIST_TOTAL_total_count, 0, 80277162 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_RELEASE_DIST_TOTAL_total_pct, 0, 75.292 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_RELEASE_DIST_TOTAL_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_RELEASE_DIST_TOTAL_pct, 0, -nan | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_RELEASE_DIST_TOTAL_total_count, 0, 0 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_RELEASE_DIST_TOTAL_total_pct, 0, -nan | |
| EXEC_STAGE_STARVED_count, 414, 274106 | |
| EXEC_STAGE_STARVED_total_count, 414, 274106 | |
| EXEC_STAGE_NOT_STARVED_count, 414, 61315 | |
| EXEC_STAGE_NOT_STARVED_total_count, 414, 61315 | |
| EXEC_STAGE_OFF_PATH_count, 414, 835 | |
| EXEC_STAGE_OFF_PATH_total_count, 414, 835 | |
| FU_BUSY_0_count, 0, 176960 | |
| FU_BUSY_0_total_count, 0, 176960 | |
| FU_BUSY_1_count, 0, 148562 | |
| FU_BUSY_1_total_count, 0, 148562 | |
| FU_BUSY_2_count, 0, 91349 | |
| FU_BUSY_2_total_count, 0, 91349 | |
| FU_BUSY_3_count, 0, 91267 | |
| FU_BUSY_3_total_count, 0, 91267 | |
| FU_BUSY_4_count, 0, 141698 | |
| FU_BUSY_4_total_count, 0, 141698 | |
| FU_BUSY_5_count, 0, 191634 | |
| FU_BUSY_5_total_count, 0, 191634 | |
| FU_BUSY_6_count, 0, 124344 | |
| FU_BUSY_6_total_count, 0, 124344 | |
| FU_BUSY_7_count, 0, 114430 | |
| FU_BUSY_7_total_count, 0, 114430 | |
| FU_BUSY_8_count, 0, 153373 | |
| FU_BUSY_8_total_count, 0, 153373 | |
| FU_BUSY_9_count, 0, 91312 | |
| FU_BUSY_9_total_count, 0, 91312 | |
| FU_BUSY_10_count, 0, 0 | |
| FU_BUSY_10_total_count, 0, 0 | |
| FU_BUSY_11_count, 0, 0 | |
| FU_BUSY_11_total_count, 0, 0 | |
| FU_BUSY_12_count, 0, 0 | |
| FU_BUSY_12_total_count, 0, 0 | |
| FU_BUSY_13_count, 0, 0 | |
| FU_BUSY_13_total_count, 0, 0 | |
| FU_BUSY_14_count, 0, 0 | |
| FU_BUSY_14_total_count, 0, 0 | |
| FU_BUSY_15_count, 0, 0 | |
| FU_BUSY_15_total_count, 0, 0 | |
| FU_BUSY_16_count, 0, 0 | |
| FU_BUSY_16_total_count, 0, 0 | |
| FU_BUSY_17_count, 0, 0 | |
| FU_BUSY_17_total_count, 0, 0 | |
| FU_BUSY_18_count, 0, 0 | |
| FU_BUSY_18_total_count, 0, 0 | |
| FU_BUSY_19_count, 0, 0 | |
| FU_BUSY_19_total_count, 0, 0 | |
| FU_BUSY_20_count, 0, 0 | |
| FU_BUSY_20_total_count, 0, 0 | |
| FU_BUSY_21_count, 0, 0 | |
| FU_BUSY_21_total_count, 0, 0 | |
| FU_BUSY_22_count, 0, 0 | |
| FU_BUSY_22_total_count, 0, 0 | |
| FU_BUSY_23_count, 0, 0 | |
| FU_BUSY_23_total_count, 0, 0 | |
| FU_BUSY_24_count, 0, 0 | |
| FU_BUSY_24_total_count, 0, 0 | |
| FU_BUSY_25_count, 0, 0 | |
| FU_BUSY_25_total_count, 0, 0 | |
| FU_BUSY_26_count, 0, 0 | |
| FU_BUSY_26_total_count, 0, 0 | |
| FU_BUSY_27_count, 0, 0 | |
| FU_BUSY_27_total_count, 0, 0 | |
| FU_BUSY_28_count, 0, 0 | |
| FU_BUSY_28_total_count, 0, 0 | |
| FU_BUSY_29_count, 0, 0 | |
| FU_BUSY_29_total_count, 0, 0 | |
| FU_BUSY_30_count, 0, 0 | |
| FU_BUSY_30_total_count, 0, 0 | |
| FU_BUSY_31_count, 0, 0 | |
| FU_BUSY_31_total_count, 0, 0 | |
| FU_REJECTED_OP_INV_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_INV_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOP_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOP_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_CF_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_CF_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_MOV_NOT_SIMD_count, 415, 1 | |
| FU_REJECTED_OP_MOV_NOT_SIMD_total_count, 415, 1 | |
| FU_REJECTED_OP_CMOV_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_CMOV_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_LDA_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_LDA_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_IMEM_NOT_SIMD_count, 415, 788 | |
| FU_REJECTED_OP_IMEM_NOT_SIMD_total_count, 415, 788 | |
| FU_REJECTED_OP_IADD_NOT_SIMD_count, 415, 8182 | |
| FU_REJECTED_OP_IADD_NOT_SIMD_total_count, 415, 8182 | |
| FU_REJECTED_OP_IMUL_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_IMUL_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_IDIV_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_IDIV_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_ICMP_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_ICMP_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_LOGIC_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_LOGIC_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_SHIFT_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_SHIFT_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FMEM_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FMEM_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FCVT_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FCVT_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FADD_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FADD_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FMUL_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FMUL_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FMA_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FMA_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FDIV_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FDIV_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FCMP_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FCMP_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FCMOV_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FCMOV_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_GATHER_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_GATHER_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_SCATTER_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_SCATTER_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_FAST_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_FAST_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_MEDIUM_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_MEDIUM_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_SLOW_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_SLOW_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_MEDIUM_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_MEDIUM_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_SLOW_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_SLOW_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_VERY_SLOW_NOT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_VERY_SLOW_NOT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_INV_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_INV_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOP_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOP_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_CF_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_CF_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_MOV_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_MOV_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_CMOV_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_CMOV_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_LDA_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_LDA_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_IMEM_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_IMEM_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_IADD_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_IADD_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_IMUL_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_IMUL_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_IDIV_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_IDIV_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_ICMP_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_ICMP_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_LOGIC_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_LOGIC_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_SHIFT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_SHIFT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FMEM_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FMEM_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FCVT_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FCVT_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FADD_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FADD_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FMUL_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FMUL_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FMA_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FMA_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FDIV_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FDIV_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FCMP_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FCMP_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_FCMOV_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_FCMOV_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_GATHER_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_GATHER_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_SCATTER_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_SCATTER_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_FAST_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_FAST_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_MEDIUM_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_MEDIUM_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_SLOW_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_PIPELINED_SLOW_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_MEDIUM_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_MEDIUM_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_SLOW_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_SLOW_SIMD_total_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_VERY_SLOW_SIMD_count, 415, 0 | |
| FU_REJECTED_OP_NOTPIPELINED_VERY_SLOW_SIMD_total_count, 415, 0 | |
| LSQ_FULL_TOTAL_count, 0, 0 | |
| LSQ_FULL_TOTAL_total_count, 0, 0 | |
| LSQ_FULL_LOAD_QUEUE_count, 0, 0 | |
| LSQ_FULL_LOAD_QUEUE_total_count, 0, 0 | |
| LSQ_FULL_STORE_QUEUE_count, 0, 0 | |
| LSQ_FULL_STORE_QUEUE_total_count, 0, 0 | |
| OP_WAIT_0_count, 0, 962825 | |
| OP_WAIT_0_total_count, 0, 962825 | |
| OP_WAIT_1_count, 0, 211545 | |
| OP_WAIT_1_total_count, 0, 211545 | |
| OP_WAIT_2_count, 0, 39517 | |
| OP_WAIT_2_total_count, 0, 39517 | |
| OP_WAIT_3_count, 0, 33149 | |
| OP_WAIT_3_total_count, 0, 33149 | |
| OP_WAIT_4_count, 0, 12922 | |
| OP_WAIT_4_total_count, 0, 12922 | |
| OP_WAIT_5_count, 0, 880 | |
| OP_WAIT_5_total_count, 0, 880 | |
| OP_WAIT_6_count, 0, 606 | |
| OP_WAIT_6_total_count, 0, 606 | |
| OP_WAIT_7_count, 0, 2 | |
| OP_WAIT_7_total_count, 0, 2 | |
| OP_WAIT_8_count, 0, 1 | |
| OP_WAIT_8_total_count, 0, 1 | |
| OP_WAIT_9_count, 0, 3 | |
| OP_WAIT_9_total_count, 0, 3 | |
| OP_WAIT_10_count, 0, 0 | |
| OP_WAIT_10_total_count, 0, 0 | |
| OP_WAIT_11_count, 0, 0 | |
| OP_WAIT_11_total_count, 0, 0 | |
| OP_WAIT_12_count, 0, 0 | |
| OP_WAIT_12_total_count, 0, 0 | |
| OP_WAIT_13_count, 0, 0 | |
| OP_WAIT_13_total_count, 0, 0 | |
| OP_WAIT_14_count, 0, 0 | |
| OP_WAIT_14_total_count, 0, 0 | |
| OP_WAIT_15_count, 0, 0 | |
| OP_WAIT_15_total_count, 0, 0 | |
| OP_WAIT_16_count, 0, 0 | |
| OP_WAIT_16_total_count, 0, 0 | |
| OP_WAIT_17_count, 0, 0 | |
| OP_WAIT_17_total_count, 0, 0 | |
| OP_WAIT_18_count, 0, 0 | |
| OP_WAIT_18_total_count, 0, 0 | |
| OP_WAIT_19_count, 0, 0 | |
| OP_WAIT_19_total_count, 0, 0 | |
| OP_WAIT_20_count, 0, 0 | |
| OP_WAIT_20_total_count, 0, 0 | |
| OP_WAIT_21_count, 0, 0 | |
| OP_WAIT_21_total_count, 0, 0 | |
| OP_WAIT_22_count, 0, 0 | |
| OP_WAIT_22_total_count, 0, 0 | |
| OP_WAIT_23_count, 0, 0 | |
| OP_WAIT_23_total_count, 0, 0 | |
| OP_WAIT_24_count, 0, 0 | |
| OP_WAIT_24_total_count, 0, 0 | |
| OP_WAIT_25_count, 0, 0 | |
| OP_WAIT_25_total_count, 0, 0 | |
| OP_WAIT_26_count, 0, 0 | |
| OP_WAIT_26_total_count, 0, 0 | |
| OP_WAIT_27_count, 0, 0 | |
| OP_WAIT_27_total_count, 0, 0 | |
| OP_WAIT_28_count, 0, 0 | |
| OP_WAIT_28_total_count, 0, 0 | |
| OP_WAIT_29_count, 0, 0 | |
| OP_WAIT_29_total_count, 0, 0 | |
| OP_WAIT_30_count, 0, 0 | |
| OP_WAIT_30_total_count, 0, 0 | |
| OP_WAIT_31_count, 0, 0 | |
| OP_WAIT_31_total_count, 0, 0 | |
| ROW_SIZE_0_count, 0, 127544 | |
| ROW_SIZE_0_total_count, 0, 127544 | |
| ROW_SIZE_1_count, 0, 28186 | |
| ROW_SIZE_1_total_count, 0, 28186 | |
| ROW_SIZE_2_count, 0, 28178 | |
| ROW_SIZE_2_total_count, 0, 28178 | |
| ROW_SIZE_3_count, 0, 21 | |
| ROW_SIZE_3_total_count, 0, 21 | |
| ROW_SIZE_4_count, 0, 912 | |
| ROW_SIZE_4_total_count, 0, 912 | |
| ROW_SIZE_5_count, 0, 5 | |
| ROW_SIZE_5_total_count, 0, 5 | |
| ROW_SIZE_6_count, 0, 14059 | |
| ROW_SIZE_6_total_count, 0, 14059 | |
| ROW_SIZE_7_count, 0, 22 | |
| ROW_SIZE_7_total_count, 0, 22 | |
| ROW_SIZE_8_count, 0, 136083 | |
| ROW_SIZE_8_total_count, 0, 136083 | |
| ROW_SIZE_9_count, 0, 0 | |
| ROW_SIZE_9_total_count, 0, 0 | |
| ROW_SIZE_10_count, 0, 0 | |
| ROW_SIZE_10_total_count, 0, 0 | |
| ROW_SIZE_11_count, 0, 0 | |
| ROW_SIZE_11_total_count, 0, 0 | |
| ROW_SIZE_12_count, 0, 0 | |
| ROW_SIZE_12_total_count, 0, 0 | |
| ROW_SIZE_13_count, 0, 0 | |
| ROW_SIZE_13_total_count, 0, 0 | |
| ROW_SIZE_14_count, 0, 0 | |
| ROW_SIZE_14_total_count, 0, 0 | |
| ROW_SIZE_15_count, 0, 0 | |
| ROW_SIZE_15_total_count, 0, 0 | |
| ROW_SIZE_16_count, 0, 0 | |
| ROW_SIZE_16_total_count, 0, 0 | |
| ROW_SIZE_17_count, 0, 0 | |
| ROW_SIZE_17_total_count, 0, 0 | |
| ROW_SIZE_18_count, 0, 0 | |
| ROW_SIZE_18_total_count, 0, 0 | |
| ROW_SIZE_19_count, 0, 0 | |
| ROW_SIZE_19_total_count, 0, 0 | |
| ROW_SIZE_20_count, 0, 0 | |
| ROW_SIZE_20_total_count, 0, 0 | |
| ROW_SIZE_21_count, 0, 0 | |
| ROW_SIZE_21_total_count, 0, 0 | |
| ROW_SIZE_22_count, 0, 0 | |
| ROW_SIZE_22_total_count, 0, 0 | |
| ROW_SIZE_23_count, 0, 0 | |
| ROW_SIZE_23_total_count, 0, 0 | |
| ROW_SIZE_24_count, 0, 0 | |
| ROW_SIZE_24_total_count, 0, 0 | |
| ROW_SIZE_25_count, 0, 0 | |
| ROW_SIZE_25_total_count, 0, 0 | |
| ROW_SIZE_26_count, 0, 0 | |
| ROW_SIZE_26_total_count, 0, 0 | |
| ROW_SIZE_27_count, 0, 0 | |
| ROW_SIZE_27_total_count, 0, 0 | |
| ROW_SIZE_28_count, 0, 0 | |
| ROW_SIZE_28_total_count, 0, 0 | |
| ROW_SIZE_29_count, 0, 0 | |
| ROW_SIZE_29_total_count, 0, 0 | |
| ROW_SIZE_30_count, 0, 0 | |
| ROW_SIZE_30_total_count, 0, 0 | |
| ROW_SIZE_31_count, 0, 0 | |
| ROW_SIZE_31_total_count, 0, 0 | |
| RET_OP_EXEC_COUNT_0_count, 416, 0 | |
| RET_OP_EXEC_COUNT_0_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_1_count, 416, 1261450 | |
| RET_OP_EXEC_COUNT_1_total_count, 416, 1261450 | |
| RET_OP_EXEC_COUNT_2_count, 416, 0 | |
| RET_OP_EXEC_COUNT_2_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_3_count, 416, 0 | |
| RET_OP_EXEC_COUNT_3_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_4_count, 416, 0 | |
| RET_OP_EXEC_COUNT_4_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_5_count, 416, 0 | |
| RET_OP_EXEC_COUNT_5_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_6_count, 416, 0 | |
| RET_OP_EXEC_COUNT_6_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_7_count, 416, 0 | |
| RET_OP_EXEC_COUNT_7_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_8_count, 416, 0 | |
| RET_OP_EXEC_COUNT_8_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_9_count, 416, 0 | |
| RET_OP_EXEC_COUNT_9_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_10_count, 416, 0 | |
| RET_OP_EXEC_COUNT_10_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_11_count, 416, 0 | |
| RET_OP_EXEC_COUNT_11_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_12_count, 416, 0 | |
| RET_OP_EXEC_COUNT_12_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_13_count, 416, 0 | |
| RET_OP_EXEC_COUNT_13_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_14_count, 416, 0 | |
| RET_OP_EXEC_COUNT_14_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_15_count, 416, 0 | |
| RET_OP_EXEC_COUNT_15_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_16_count, 416, 0 | |
| RET_OP_EXEC_COUNT_16_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_17_count, 416, 0 | |
| RET_OP_EXEC_COUNT_17_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_18_count, 416, 0 | |
| RET_OP_EXEC_COUNT_18_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_19_count, 416, 0 | |
| RET_OP_EXEC_COUNT_19_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_20_count, 416, 0 | |
| RET_OP_EXEC_COUNT_20_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_21_count, 416, 0 | |
| RET_OP_EXEC_COUNT_21_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_22_count, 416, 0 | |
| RET_OP_EXEC_COUNT_22_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_23_count, 416, 0 | |
| RET_OP_EXEC_COUNT_23_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_24_count, 416, 0 | |
| RET_OP_EXEC_COUNT_24_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_25_count, 416, 0 | |
| RET_OP_EXEC_COUNT_25_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_26_count, 416, 0 | |
| RET_OP_EXEC_COUNT_26_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_27_count, 416, 0 | |
| RET_OP_EXEC_COUNT_27_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_28_count, 416, 0 | |
| RET_OP_EXEC_COUNT_28_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_29_count, 416, 0 | |
| RET_OP_EXEC_COUNT_29_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_30_count, 416, 0 | |
| RET_OP_EXEC_COUNT_30_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_31_count, 416, 0 | |
| RET_OP_EXEC_COUNT_31_total_count, 416, 0 | |
| RET_OP_EXEC_COUNT_32_count, 416, 0 | |
| RET_OP_EXEC_COUNT_32_total_count, 416, 0 | |
| RET_STALL_LENGTH_0_count, 417, 1261430 | |
| RET_STALL_LENGTH_0_total_count, 417, 1261430 | |
| RET_STALL_LENGTH_100_count, 417, 7 | |
| RET_STALL_LENGTH_100_total_count, 417, 7 | |
| RET_STALL_LENGTH_200_count, 417, 0 | |
| RET_STALL_LENGTH_200_total_count, 417, 0 | |
| RET_STALL_LENGTH_300_count, 417, 0 | |
| RET_STALL_LENGTH_300_total_count, 417, 0 | |
| RET_STALL_LENGTH_400_count, 417, 0 | |
| RET_STALL_LENGTH_400_total_count, 417, 0 | |
| RET_STALL_LENGTH_500_count, 417, 0 | |
| RET_STALL_LENGTH_500_total_count, 417, 0 | |
| RET_STALL_LENGTH_600_count, 417, 0 | |
| RET_STALL_LENGTH_600_total_count, 417, 0 | |
| RET_STALL_LENGTH_700_count, 417, 0 | |
| RET_STALL_LENGTH_700_total_count, 417, 0 | |
| RET_STALL_LENGTH_800_count, 417, 0 | |
| RET_STALL_LENGTH_800_total_count, 417, 0 | |
| RET_STALL_LENGTH_900_count, 417, 9 | |
| RET_STALL_LENGTH_900_total_count, 417, 9 | |
| RET_STALL_LENGTH_1000_count, 417, 4 | |
| RET_STALL_LENGTH_1000_total_count, 417, 4 | |
| RET_STALL_LENGTH_1100_count, 417, 0 | |
| RET_STALL_LENGTH_1100_total_count, 417, 0 | |
| RET_STALL_LENGTH_1200_count, 417, 0 | |
| RET_STALL_LENGTH_1200_total_count, 417, 0 | |
| RET_STALL_LENGTH_1300_count, 417, 0 | |
| RET_STALL_LENGTH_1300_total_count, 417, 0 | |
| RET_STALL_LENGTH_1400_count, 417, 0 | |
| RET_STALL_LENGTH_1400_total_count, 417, 0 | |
| RET_STALL_LENGTH_1500_count, 417, 0 | |
| RET_STALL_LENGTH_1500_total_count, 417, 0 | |
| RET_STALL_LENGTH_1600_count, 417, 0 | |
| RET_STALL_LENGTH_1600_total_count, 417, 0 | |
| RET_STALL_LENGTH_1700_count, 417, 0 | |
| RET_STALL_LENGTH_1700_total_count, 417, 0 | |
| RET_STALL_LENGTH_1800_count, 417, 0 | |
| RET_STALL_LENGTH_1800_total_count, 417, 0 | |
| RET_STALL_LENGTH_1900_count, 417, 0 | |
| RET_STALL_LENGTH_1900_total_count, 417, 0 | |
| RET_STALL_LENGTH_2000_count, 417, 0 | |
| RET_STALL_LENGTH_2000_total_count, 417, 0 | |
| RET_STALL_LENGTH_2100_count, 417, 0 | |
| RET_STALL_LENGTH_2100_total_count, 417, 0 | |
| RET_STALL_LENGTH_2200_count, 417, 0 | |
| RET_STALL_LENGTH_2200_total_count, 417, 0 | |
| RET_STALL_LENGTH_2300_count, 417, 0 | |
| RET_STALL_LENGTH_2300_total_count, 417, 0 | |
| RET_STALL_LENGTH_2400_count, 417, 0 | |
| RET_STALL_LENGTH_2400_total_count, 417, 0 | |
| RET_STALL_LENGTH_2500_count, 417, 0 | |
| RET_STALL_LENGTH_2500_total_count, 417, 0 | |
| RET_STALL_LENGTH_2600_count, 417, 0 | |
| RET_STALL_LENGTH_2600_total_count, 417, 0 | |
| RET_STALL_LENGTH_2700_count, 417, 0 | |
| RET_STALL_LENGTH_2700_total_count, 417, 0 | |
| RET_STALL_LENGTH_2800_count, 417, 0 | |
| RET_STALL_LENGTH_2800_total_count, 417, 0 | |
| RET_STALL_LENGTH_2900_count, 417, 0 | |
| RET_STALL_LENGTH_2900_total_count, 417, 0 | |
| RET_STALL_LENGTH_3000_count, 417, 0 | |
| RET_STALL_LENGTH_3000_total_count, 417, 0 | |
| RET_STALL_LENGTH_3100_count, 417, 0 | |
| RET_STALL_LENGTH_3100_total_count, 417, 0 | |
| RET_STALL_LENGTH_3200_count, 417, 0 | |
| RET_STALL_LENGTH_3200_total_count, 417, 0 | |
| RET_STALL_LENGTH_3300_count, 417, 0 | |
| RET_STALL_LENGTH_3300_total_count, 417, 0 | |
| RET_STALL_LENGTH_3400_count, 417, 0 | |
| RET_STALL_LENGTH_3400_total_count, 417, 0 | |
| RET_STALL_LENGTH_3500_count, 417, 0 | |
| RET_STALL_LENGTH_3500_total_count, 417, 0 | |
| RET_STALL_LENGTH_3600_count, 417, 0 | |
| RET_STALL_LENGTH_3600_total_count, 417, 0 | |
| RET_STALL_LENGTH_3700_count, 417, 0 | |
| RET_STALL_LENGTH_3700_total_count, 417, 0 | |
| RET_STALL_LENGTH_3800_count, 417, 0 | |
| RET_STALL_LENGTH_3800_total_count, 417, 0 | |
| RET_STALL_LENGTH_3900_count, 417, 0 | |
| RET_STALL_LENGTH_3900_total_count, 417, 0 | |
| RET_STALL_LENGTH_4000_count, 417, 0 | |
| RET_STALL_LENGTH_4000_total_count, 417, 0 | |
| RET_STALL_LENGTH_4100_count, 417, 0 | |
| RET_STALL_LENGTH_4100_total_count, 417, 0 | |
| RET_STALL_LENGTH_4200_count, 417, 0 | |
| RET_STALL_LENGTH_4200_total_count, 417, 0 | |
| RET_STALL_LENGTH_4300_count, 417, 0 | |
| RET_STALL_LENGTH_4300_total_count, 417, 0 | |
| RET_STALL_LENGTH_4400_count, 417, 0 | |
| RET_STALL_LENGTH_4400_total_count, 417, 0 | |
| RET_STALL_LENGTH_4500_count, 417, 0 | |
| RET_STALL_LENGTH_4500_total_count, 417, 0 | |
| RET_STALL_LENGTH_4600_count, 417, 0 | |
| RET_STALL_LENGTH_4600_total_count, 417, 0 | |
| RET_STALL_LENGTH_4700_count, 417, 0 | |
| RET_STALL_LENGTH_4700_total_count, 417, 0 | |
| RET_STALL_LENGTH_4800_count, 417, 0 | |
| RET_STALL_LENGTH_4800_total_count, 417, 0 | |
| RET_STALL_LENGTH_4900_count, 417, 0 | |
| RET_STALL_LENGTH_4900_total_count, 417, 0 | |
| RET_STALL_LENGTH_5000_count, 417, 0 | |
| RET_STALL_LENGTH_5000_total_count, 417, 0 | |
| MEM_BLOCK_LENGTH_0_count, 418, 1 | |
| MEM_BLOCK_LENGTH_0_total_count, 418, 1 | |
| MEM_BLOCK_LENGTH_100_count, 418, 0 | |
| MEM_BLOCK_LENGTH_100_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_200_count, 418, 0 | |
| MEM_BLOCK_LENGTH_200_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_300_count, 418, 0 | |
| MEM_BLOCK_LENGTH_300_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_400_count, 418, 0 | |
| MEM_BLOCK_LENGTH_400_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_500_count, 418, 0 | |
| MEM_BLOCK_LENGTH_500_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_600_count, 418, 0 | |
| MEM_BLOCK_LENGTH_600_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_700_count, 418, 0 | |
| MEM_BLOCK_LENGTH_700_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_800_count, 418, 0 | |
| MEM_BLOCK_LENGTH_800_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_900_count, 418, 0 | |
| MEM_BLOCK_LENGTH_900_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1000_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1000_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1100_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1100_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1200_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1200_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1300_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1300_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1400_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1400_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1500_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1500_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1600_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1600_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1700_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1700_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1800_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1800_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1900_count, 418, 0 | |
| MEM_BLOCK_LENGTH_1900_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2000_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2000_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2100_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2100_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2200_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2200_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2300_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2300_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2400_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2400_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2500_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2500_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2600_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2600_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2700_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2700_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2800_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2800_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2900_count, 418, 0 | |
| MEM_BLOCK_LENGTH_2900_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3000_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3000_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3100_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3100_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3200_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3200_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3300_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3300_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3400_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3400_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3500_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3500_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3600_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3600_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3700_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3700_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3800_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3800_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3900_count, 418, 0 | |
| MEM_BLOCK_LENGTH_3900_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4000_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4000_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4100_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4100_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4200_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4200_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4300_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4300_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4400_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4400_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4500_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4500_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4600_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4600_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4700_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4700_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4800_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4800_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4900_count, 418, 0 | |
| MEM_BLOCK_LENGTH_4900_total_count, 418, 0 | |
| MEM_BLOCK_LENGTH_5000_count, 418, 0 | |
| MEM_BLOCK_LENGTH_5000_total_count, 418, 0 | |
| FUS_BUSY_ON_PATH_count, 0, 1323427 | |
| FUS_BUSY_ON_PATH_pct, 0, 3.936 | |
| FUS_BUSY_ON_PATH_total_count, 0, 1323427 | |
| FUS_BUSY_ON_PATH_total_pct, 0, 3.936 | |
| FUS_BUSY_OFF_PATH_count, 0, 1502 | |
| FUS_BUSY_OFF_PATH_pct, 0, 0.004 | |
| FUS_BUSY_OFF_PATH_total_count, 0, 1502 | |
| FUS_BUSY_OFF_PATH_total_pct, 0, 0.004 | |
| FU_BUSY_MEM_STALL_count, 0, 61999 | |
| FU_BUSY_MEM_STALL_pct, 0, 0.184 | |
| FU_BUSY_MEM_STALL_total_count, 0, 61999 | |
| FU_BUSY_MEM_STALL_total_pct, 0, 0.184 | |
| FUS_EMPTY_count, 0, 2037631 | |
| FUS_EMPTY_pct, 0, 6.060 | |
| FUS_EMPTY_total_count, 0, 2037631 | |
| FUS_EMPTY_total_pct, 0, 6.060 | |
| FU_UNAVAILABLE_count, 0, 1 | |
| FU_UNAVAILABLE_pct, 0, 0.000 | |
| FU_UNAVAILABLE_total_count, 0, 1 | |
| FU_UNAVAILABLE_total_pct, 0, 0.000 | |
| FU_MEM_UNAVAILABLE_count, 0, 8970 | |
| FU_MEM_UNAVAILABLE_pct, 0, 0.027 | |
| FU_MEM_UNAVAILABLE_total_count, 0, 8970 | |
| FU_MEM_UNAVAILABLE_total_pct, 0, 0.027 | |
| FU_OTHER_UNAVAILABLE_count, 0, 0 | |
| FU_OTHER_UNAVAILABLE_pct, 0, 0.000 | |
| FU_OTHER_UNAVAILABLE_total_count, 0, 0 | |
| FU_OTHER_UNAVAILABLE_total_pct, 0, 0.000 | |
| FU_REPLAY_count, 0, 0 | |
| FU_REPLAY_pct, 0, 0.000 | |
| FU_REPLAY_total_count, 0, 0 | |
| FU_REPLAY_total_pct, 0, 0.000 | |
| FU_STARVED_count, 0, 2037613 | |
| FU_STARVED_pct, 0, 6.060 | |
| FU_STARVED_total_count, 0, 2037613 | |
| FU_STARVED_total_pct, 0, 6.060 | |
| CHIP_UTILIZATION_count, 0, 0 | |
| CHIP_UTILIZATION_pct, 0, 0.000 | |
| CHIP_UTILIZATION_total_count, 0, 0 | |
| CHIP_UTILIZATION_total_pct, 0, 0.000 | |
| CYCLES_UNDER_MEM_REQ_count, 0, 0 | |
| CYCLES_UNDER_MEM_REQ_total_count, 0, 0 | |
| CYCLES_UNDER_NO_MEM_REQ_count, 0, 0 | |
| CYCLES_UNDER_NO_MEM_REQ_total_count, 0, 0 | |
| CYCLES_UNDER_CRITICAL_MEM_REQ_count, 0, 0 | |
| CYCLES_UNDER_CRITICAL_MEM_REQ_total_count, 0, 0 | |
| CYCLES_UNDER_NONCRITICAL_MEM_REQ_count, 0, 0 | |
| CYCLES_UNDER_NONCRITICAL_MEM_REQ_total_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_MEM_REQ_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_MEM_REQ_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_MEM_REQ_total_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_MEM_REQ_total_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_NO_MEM_REQ_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_NO_MEM_REQ_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_NO_MEM_REQ_total_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_NO_MEM_REQ_total_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ_total_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ_total_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ_pct, 0, -nan | |
| CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ_total_count, 0, 0 | |
| CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ_total_pct, 0, -nan | |
| CYCLES_NOT_WAITING_FOR_OFF_CHIP_count, 0, 0 | |
| CYCLES_NOT_WAITING_FOR_OFF_CHIP_pct, 0, 0.000 | |
| CYCLES_NOT_WAITING_FOR_OFF_CHIP_total_count, 0, 0 | |
| CYCLES_NOT_WAITING_FOR_OFF_CHIP_total_pct, 0, 0.000 | |
| FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP_count, 0, 0 | |
| FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP_pct, 0, -nan | |
| FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP_total_count, 0, 0 | |
| FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP_total_pct, 0, -nan | |
| CYCLES_WAITING_FOR_OFF_CHIP_count, 0, 0 | |
| CYCLES_WAITING_FOR_OFF_CHIP_pct, 0, 0.000 | |
| CYCLES_WAITING_FOR_OFF_CHIP_total_count, 0, 0 | |
| CYCLES_WAITING_FOR_OFF_CHIP_total_pct, 0, 0.000 | |
| FUS_BUSY_WAITING_FOR_OFF_CHIP_count, 0, 0 | |
| FUS_BUSY_WAITING_FOR_OFF_CHIP_pct, 0, -nan | |
| FUS_BUSY_WAITING_FOR_OFF_CHIP_total_count, 0, 0 | |
| FUS_BUSY_WAITING_FOR_OFF_CHIP_total_pct, 0, -nan | |
| TOTAL_OFF_CHIP_DELAYS_LEFT_count, 0, 0 | |
| TOTAL_OFF_CHIP_DELAYS_LEFT_total_count, 0, 0 | |
| WRONG_IO_SCHED_count, 0, 0 | |
| WRONG_IO_SCHED_total_count, 0, 0 | |
| DVFS_CONFIG_SWITCH_count, 0, 0 | |
| DVFS_CONFIG_SWITCH_total_count, 0, 0 | |
| MAP_STAGE_RECEIVED_OPS_0_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_0_total_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_1_count, 419, 1 | |
| MAP_STAGE_RECEIVED_OPS_1_total_count, 419, 1 | |
| MAP_STAGE_RECEIVED_OPS_2_count, 419, 1 | |
| MAP_STAGE_RECEIVED_OPS_2_total_count, 419, 1 | |
| MAP_STAGE_RECEIVED_OPS_3_count, 419, 3 | |
| MAP_STAGE_RECEIVED_OPS_3_total_count, 419, 3 | |
| MAP_STAGE_RECEIVED_OPS_4_count, 419, 1 | |
| MAP_STAGE_RECEIVED_OPS_4_total_count, 419, 1 | |
| MAP_STAGE_RECEIVED_OPS_5_count, 419, 2 | |
| MAP_STAGE_RECEIVED_OPS_5_total_count, 419, 2 | |
| MAP_STAGE_RECEIVED_OPS_6_count, 419, 210234 | |
| MAP_STAGE_RECEIVED_OPS_6_total_count, 419, 210234 | |
| MAP_STAGE_RECEIVED_OPS_7_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_7_total_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_8_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_8_total_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_MAX_count, 419, 0 | |
| MAP_STAGE_RECEIVED_OPS_MAX_total_count, 419, 0 | |
| MAP_STAGE_WAIT_FOR_DECODE_count, 420, 0 | |
| MAP_STAGE_WAIT_FOR_DECODE_total_count, 420, 0 | |
| MAP_STAGE_CONSUME_DECODE_count, 420, 0 | |
| MAP_STAGE_CONSUME_DECODE_total_count, 420, 0 | |
| MAP_STAGE_WAIT_FOR_DECODE2_count, 421, 0 | |
| MAP_STAGE_WAIT_FOR_DECODE2_total_count, 421, 0 | |
| MAP_STAGE_CONSUME_DECODE2_count, 421, 0 | |
| MAP_STAGE_CONSUME_DECODE2_total_count, 421, 0 | |
| FTQ_RECOVER_EXEC_count, 0, 6 | |
| FTQ_RECOVER_EXEC_total_count, 0, 6 | |
| FTQ_RECOVER_DECODE_count, 0, 1 | |
| FTQ_RECOVER_DECODE_total_count, 0, 1 | |
| FTQ_OFFPATH_CYCLES_count, 0, 2341 | |
| FTQ_OFFPATH_CYCLES_total_count, 0, 2341 | |
| FTQ_CYCLES_OFFPATH_count, 0, 2341 | |
| FTQ_CYCLES_OFFPATH_total_count, 0, 2341 | |
| FTQ_CYCLES_ONPATH_count, 0, 333915 | |
| FTQ_CYCLES_ONPATH_total_count, 0, 333915 | |
| FTQ_FETCHED_INS_ONPATH_count, 0, 1261450 | |
| FTQ_FETCHED_INS_ONPATH_total_count, 0, 1261450 | |
| FTQ_FETCHED_INS_OFFPATH_count, 0, 5749 | |
| FTQ_FETCHED_INS_OFFPATH_total_count, 0, 5749 | |
| FTQ_BREAK_FULL_FT_ONPATH_count, 0, 333486 | |
| FTQ_BREAK_FULL_FT_ONPATH_total_count, 0, 333486 | |
| FTQ_BREAK_FULL_FT_OFFPATH_count, 0, 2143 | |
| FTQ_BREAK_FULL_FT_OFFPATH_total_count, 0, 2143 | |
| FTQ_BREAK_PRED_BR_ONPATH_count, 0, 0 | |
| FTQ_BREAK_PRED_BR_ONPATH_total_count, 0, 0 | |
| FTQ_BREAK_PRED_BR_OFFPATH_count, 0, 0 | |
| FTQ_BREAK_PRED_BR_OFFPATH_total_count, 0, 0 | |
| FTQ_BREAK_BAR_FETCH_ONPATH_count, 0, 0 | |
| FTQ_BREAK_BAR_FETCH_ONPATH_total_count, 0, 0 | |
| FTQ_BREAK_BAR_FETCH_OFFPATH_count, 0, 0 | |
| FTQ_BREAK_BAR_FETCH_OFFPATH_total_count, 0, 0 | |
| FTQ_BREAK_MAX_CFS_TAKEN_ONPATH_count, 0, 0 | |
| FTQ_BREAK_MAX_CFS_TAKEN_ONPATH_total_count, 0, 0 | |
| FTQ_BREAK_MAX_CFS_TAKEN_OFFPATH_count, 0, 0 | |
| FTQ_BREAK_MAX_CFS_TAKEN_OFFPATH_total_count, 0, 0 | |
| FTQ_BREAK_MAX_FT_ONPATH_count, 0, 236 | |
| FTQ_BREAK_MAX_FT_ONPATH_total_count, 0, 236 | |
| FTQ_BREAK_MAX_FT_OFFPATH_count, 0, 198 | |
| FTQ_BREAK_MAX_FT_OFFPATH_total_count, 0, 198 | |
| DFE_GEN_ON_PATH_FT_count, 0, 150177 | |
| DFE_GEN_ON_PATH_FT_total_count, 0, 150177 | |
| DFE_GEN_OFF_PATH_FT_count, 0, 427 | |
| DFE_GEN_OFF_PATH_FT_total_count, 0, 427 | |
| DFE_L0_ENABLED_PREDICTIONS_count, 0, 1261450 | |
| DFE_L0_ENABLED_PREDICTIONS_total_count, 0, 1261450 | |
| DFE_L0_WRONG_MAIN_CORRECT_count, 0, 4 | |
| DFE_L0_WRONG_MAIN_CORRECT_total_count, 0, 4 | |
| DFE_L0_WRONG_MAIN_WRONG_count, 0, 6 | |
| DFE_L0_WRONG_MAIN_WRONG_total_count, 0, 6 | |
| DFE_L0_CORRECT_MAIN_WRONG_count, 0, 1 | |
| DFE_L0_CORRECT_MAIN_WRONG_total_count, 0, 1 | |
| DFE_L0_CORRECT_MAIN_CORRECT_count, 0, 1261439 | |
| DFE_L0_CORRECT_MAIN_CORRECT_total_count, 0, 1261439 | |
| DFE_L0_WRONG_MAIN_CORRECT_RECOVERY_SCHEDULED_count, 0, 0 | |
| DFE_L0_WRONG_MAIN_CORRECT_RECOVERY_SCHEDULED_total_count, 0, 0 | |
| FTQ_SAW_BAR_FETCH_OFFPATH_count, 0, 0 | |
| FTQ_SAW_BAR_FETCH_OFFPATH_total_count, 0, 0 | |
| FTQ_SAW_BAR_FETCH_ONPATH_count, 0, 0 | |
| FTQ_SAW_BAR_FETCH_ONPATH_total_count, 0, 0 | |
| DFE_CONF_0_RECOVER_AT_EXEC_count, 422, 0 | |
| DFE_CONF_0_RECOVER_AT_EXEC_total_count, 422, 0 | |
| DFE_CONF_1_RECOVER_AT_EXEC_count, 422, 0 | |
| DFE_CONF_1_RECOVER_AT_EXEC_total_count, 422, 0 | |
| DFE_CONF_2_RECOVER_AT_EXEC_count, 422, 0 | |
| DFE_CONF_2_RECOVER_AT_EXEC_total_count, 422, 0 | |
| DFE_CONF_3_RECOVER_AT_EXEC_count, 422, 0 | |
| DFE_CONF_3_RECOVER_AT_EXEC_total_count, 422, 0 | |
| DFE_CONF_0_CORRECT_count, 422, 0 | |
| DFE_CONF_0_CORRECT_total_count, 422, 0 | |
| DFE_CONF_1_CORRECT_count, 422, 0 | |
| DFE_CONF_1_CORRECT_total_count, 422, 0 | |
| DFE_CONF_2_CORRECT_count, 422, 0 | |
| DFE_CONF_2_CORRECT_total_count, 422, 0 | |
| DFE_CONF_3_CORRECT_count, 422, 0 | |
| DFE_CONF_3_CORRECT_total_count, 422, 0 | |
| DFE_ON_CONF_ON_OPS_count, 423, 0 | |
| DFE_ON_CONF_ON_OPS_total_count, 423, 0 | |
| DFE_ON_CONF_OFF_OPS_count, 423, 0 | |
| DFE_ON_CONF_OFF_OPS_total_count, 423, 0 | |
| DFE_OFF_CONF_ON_OPS_count, 423, 0 | |
| DFE_OFF_CONF_ON_OPS_total_count, 423, 0 | |
| DFE_OFF_CONF_OFF_REALISTIC_OPS_count, 423, 0 | |
| DFE_OFF_CONF_OFF_REALISTIC_OPS_total_count, 423, 0 | |
| DFE_OFF_CONF_OFF_PERFECT_OPS_count, 423, 0 | |
| DFE_OFF_CONF_OFF_PERFECT_OPS_total_count, 423, 0 | |
| DFE_ON_CONF_ON_FETCH_TARGETS_count, 424, 0 | |
| DFE_ON_CONF_ON_FETCH_TARGETS_total_count, 424, 0 | |
| DFE_ON_CONF_OFF_FETCH_TARGETS_count, 424, 0 | |
| DFE_ON_CONF_OFF_FETCH_TARGETS_total_count, 424, 0 | |
| DFE_OFF_CONF_ON_FETCH_TARGETS_count, 424, 0 | |
| DFE_OFF_CONF_ON_FETCH_TARGETS_total_count, 424, 0 | |
| DFE_OFF_CONF_OFF_REALISTIC_FETCH_TARGETS_count, 424, 0 | |
| DFE_OFF_CONF_OFF_REALISTIC_FETCH_TARGETS_total_count, 424, 0 | |
| DFE_OFF_CONF_OFF_PERFECT_FETCH_TARGETS_count, 424, 0 | |
| DFE_OFF_CONF_OFF_PERFECT_FETCH_TARGETS_total_count, 424, 0 | |
| DFE_ON_CONF_ON_CYCLES_count, 425, 0 | |
| DFE_ON_CONF_ON_CYCLES_total_count, 425, 0 | |
| DFE_ON_CONF_OFF_CYCLES_count, 425, 0 | |
| DFE_ON_CONF_OFF_CYCLES_total_count, 425, 0 | |
| DFE_OFF_CONF_ON_CYCLES_count, 425, 0 | |
| DFE_OFF_CONF_ON_CYCLES_total_count, 425, 0 | |
| DFE_OFF_CONF_OFF_REALISTIC_CYCLES_count, 425, 0 | |
| DFE_OFF_CONF_OFF_REALISTIC_CYCLES_total_count, 425, 0 | |
| DFE_OFF_CONF_OFF_PERFECT_CYCLES_count, 425, 0 | |
| DFE_OFF_CONF_OFF_PERFECT_CYCLES_total_count, 425, 0 | |
| DFE_OFF_CONF_ON_NUM_EVENTS_count, 0, 0 | |
| DFE_OFF_CONF_ON_NUM_EVENTS_total_count, 0, 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_EVENTS_count, 426, 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_EVENTS_total_count, 426, 0 | |
| DFE_OFF_CONF_ON_IBTB_MISS_EVENTS_count, 426, 0 | |
| DFE_OFF_CONF_ON_IBTB_MISS_EVENTS_total_count, 426, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_EVENTS_count, 426, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_EVENTS_total_count, 426, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_EVENTS_count, 426, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_EVENTS_total_count, 426, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_EVENTS_count, 426, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_EVENTS_total_count, 426, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_EVENTS_count, 426, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_EVENTS_total_count, 426, 0 | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_EVENTS_count, 0, 0 | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_EVENTS_total_count, 0, 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_CYCLES_count, 427, 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_CYCLES_total_count, 427, 0 | |
| DFE_OFF_CONF_ON_IBTB_MISS_CYCLES_count, 427, 0 | |
| DFE_OFF_CONF_ON_IBTB_MISS_CYCLES_total_count, 427, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CYCLES_count, 427, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CYCLES_total_count, 427, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_CYCLES_count, 427, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_CYCLES_total_count, 427, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_CYCLES_count, 427, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_CYCLES_total_count, 427, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_CYCLES_count, 427, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_CYCLES_total_count, 427, 0 | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_CYCLES_count, 0, 0 | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_CYCLES_total_count, 0, 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_FETCH_TARGETS_count, 428, 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_FETCH_TARGETS_total_count, 428, 0 | |
| DFE_OFF_CONF_ON_IBTB_MISS_FETCH_TARGETS_count, 428, 0 | |
| DFE_OFF_CONF_ON_IBTB_MISS_FETCH_TARGETS_total_count, 428, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_FETCH_TARGETS_count, 428, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_FETCH_TARGETS_total_count, 428, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_FETCH_TARGETS_count, 428, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_FETCH_TARGETS_total_count, 428, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_FETCH_TARGETS_count, 428, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_FETCH_TARGETS_total_count, 428, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_FETCH_TARGETS_count, 428, 0 | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_FETCH_TARGETS_total_count, 428, 0 | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_FETCH_TARGETS_count, 0, 0 | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_FETCH_TARGETS_total_count, 0, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_0_CONF_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_0_CONF_total_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_1_CONF_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_1_CONF_total_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_2_CONF_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_2_CONF_total_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_3_CONF_count, 429, 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_3_CONF_total_count, 429, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_0_CONF_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_0_CONF_total_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_1_CONF_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_1_CONF_total_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_2_CONF_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_2_CONF_total_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_3_CONF_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_3_CONF_total_count, 430, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_NOT_CF_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_NOT_CF_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_BR_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_BR_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_CBR_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_CBR_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_CALL_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_CALL_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_IBR_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_IBR_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_ICALL_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_ICALL_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_ICO_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_ICO_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_RET_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_RET_total_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_SYS_count, 431, 0 | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_SYS_total_count, 431, 0 | |
| DFE_ON_CONF_OFF_NUM_EVENTS_count, 0, 0 | |
| DFE_ON_CONF_OFF_NUM_EVENTS_total_count, 0, 0 | |
| CONF_BTB_NUM_CYCLES_OFF_PATH_EVENT_count, 0, 0 | |
| CONF_BTB_NUM_CYCLES_OFF_PATH_EVENT_total_count, 0, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_count, 432, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_count, 432, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_count, 432, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_count, 432, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_count, 432, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_INV_CONF_INC_count, 432, 0 | |
| DFE_ON_CONF_OFF_INV_CONF_INC_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_PERFECT_CONF_count, 432, 0 | |
| DFE_ON_CONF_OFF_PERFECT_CONF_total_count, 432, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_INV_CONF_INC_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_INV_CONF_INC_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_PERFECT_CONF_CYCLES_count, 433, 0 | |
| DFE_ON_CONF_OFF_PERFECT_CONF_CYCLES_total_count, 433, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_INV_CONF_INC_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_INV_CONF_INC_FETCH_TARGETS_total_count, 434, 0 | |
| DFE_ON_CONF_OFF_PERFECT_CONF_FETCH_TARGETS_count, 434, 0 | |
| DFE_ON_CONF_OFF_PERFECT_CONF_FETCH_TARGETS_total_count, 434, 0 | |
| CONF_OFF_IBTB_MISS_BP_TAKEN_count, 435, 0 | |
| CONF_OFF_IBTB_MISS_BP_TAKEN_total_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_total_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_total_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_total_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_count, 435, 0 | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_total_count, 435, 0 | |
| CONF_OFF_BTB_MISS_RATE_count, 435, 0 | |
| CONF_OFF_BTB_MISS_RATE_total_count, 435, 0 | |
| CONF_OFF_IBTB_MISS_RATE_count, 435, 0 | |
| CONF_OFF_IBTB_MISS_RATE_total_count, 435, 0 | |
| CONF_OFF_RECOVER_AT_DECODE_RATE_count, 435, 0 | |
| CONF_OFF_RECOVER_AT_DECODE_RATE_total_count, 435, 0 | |
| CONF_OFF_RECOVER_AT_EXEC_RATE_count, 435, 0 | |
| CONF_OFF_RECOVER_AT_EXEC_RATE_total_count, 435, 0 | |
| CONF_OFF_INV_CONF_INC_count, 435, 0 | |
| CONF_OFF_INV_CONF_INC_total_count, 435, 0 | |
| CONF_OFF_PERFECT_CONF_count, 435, 0 | |
| CONF_OFF_PERFECT_CONF_total_count, 435, 0 | |
| TOPDOWN_TOTAL_SLOTS_count, 0, 2017536 | |
| TOPDOWN_TOTAL_SLOTS_total_count, 0, 2017536 | |
| TOPDOWN_ISSUED_SLOTS_count, 0, 1263161 | |
| TOPDOWN_ISSUED_SLOTS_total_count, 0, 1263161 | |
| TOPDOWN_RETIRED_SLOTS_count, 0, 1261450 | |
| TOPDOWN_RETIRED_SLOTS_total_count, 0, 1261450 | |
| TOPDOWN_FETCH_BUBBLES_SLOTS_count, 0, 10939 | |
| TOPDOWN_FETCH_BUBBLES_SLOTS_total_count, 0, 10939 | |
| TOPDOWN_RECOVERY_BUBBLES_SLOTS_count, 0, 126 | |
| TOPDOWN_RECOVERY_BUBBLES_SLOTS_total_count, 0, 126 | |
| TOPDOWN_MEM_LOAD_STALLS_CYCLES_count, 0, 123885 | |
| TOPDOWN_MEM_LOAD_STALLS_CYCLES_total_count, 0, 123885 | |
| TOPDOWN_MEM_STORE_STALLS_CYCLES_count, 0, 0 | |
| TOPDOWN_MEM_STORE_STALLS_CYCLES_total_count, 0, 0 | |
| TOPDOWN_EXEC_STALLS_CYCLES_count, 0, 40701 | |
| TOPDOWN_EXEC_STALLS_CYCLES_total_count, 0, 40701 | |
| TOPDOWN_BACKEND_STALLS_CYCLES_count, 0, 123885 | |
| TOPDOWN_BACKEND_STALLS_CYCLES_total_count, 0, 123885 | |
| TOPDOWN_FETCH_BUBBLES_GT_MIW_CYCLES_count, 0, 1805 | |
| TOPDOWN_FETCH_BUBBLES_GT_MIW_CYCLES_total_count, 0, 1805 | |
| TOPDOWN_BR_RECOVER_AT_EXEC_RETIRED_CYCLES_count, 0, 6 | |
| TOPDOWN_BR_RECOVER_AT_EXEC_RETIRED_CYCLES_total_count, 0, 6 | |
| TOPDOWN_MACHINE_CLEAR_CYCLES_count, 0, 11 | |
| TOPDOWN_MACHINE_CLEAR_CYCLES_total_count, 0, 11 | |
| TOPDOWN_FRONTEND_BOUND_count, 0, 54 | |
| TOPDOWN_FRONTEND_BOUND_total_count, 0, 54 | |
| TOPDOWN_BACKEND_BOUND_count, 0, 3685 | |
| TOPDOWN_BACKEND_BOUND_total_count, 0, 3685 | |
| TOPDOWN_BAD_SPEC_BOUND_count, 0, 9 | |
| TOPDOWN_BAD_SPEC_BOUND_total_count, 0, 9 | |
| TOPDOWN_RETIRING_BOUND_count, 0, 6252 | |
| TOPDOWN_RETIRING_BOUND_total_count, 0, 6252 | |
| TOPDOWN_FETCH_LATENCY_BOUND_count, 0, 53 | |
| TOPDOWN_FETCH_LATENCY_BOUND_total_count, 0, 53 | |
| TOPDOWN_FETCH_BANDWIDTH_BOUND_count, 0, 1 | |
| TOPDOWN_FETCH_BANDWIDTH_BOUND_total_count, 0, 1 | |
| TOPDOWN_MEM_BOUND_count, 0, 3685 | |
| TOPDOWN_MEM_BOUND_total_count, 0, 3685 | |
| TOPDOWN_CORE_BOUND_count, 0, 0 | |
| TOPDOWN_CORE_BOUND_total_count, 0, 0 | |
| TOPDOWN_BR_RECOVER_AT_EXEC_BOUND_count, 0, 3 | |
| TOPDOWN_BR_RECOVER_AT_EXEC_BOUND_total_count, 0, 3 | |
| TOPDOWN_MACHINE_CLEARS_BOUND_count, 0, 6 | |
| TOPDOWN_MACHINE_CLEARS_BOUND_total_count, 0, 6 | |
| H2P_SEEN_MAIN_count, 0, 0 | |
| H2P_SEEN_MAIN_total_count, 0, 0 | |