hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /12 /fetch.stat.0.out
| /* -*- Mode: c -*- */ | |
| #################################################################################################### | |
| Core 0 | |
| #################################################################################################### | |
| Cumulative: Cycles: 336256 Instructions: 961103 IPC: 2.85825 | |
| Periodic: Cycles: 336256 Instructions: 961103 IPC: 2.85825 | |
| MISS_WAIT_TIME 21923 21923 | |
| ICACHE_STAGE_MISS 34 34 | |
| ICACHE_CYCLE 336256 336256 | |
| TCACHE_CYCLE 0 0 | |
| ICACHE_SERVING_CYCLE_ON_PATH 20 20 | |
| ICACHE_SERVING_CYCLE_OFF_PATH 339 339 | |
| UCACHE_SERVING_CYCLE_ON_PATH 333834 333834 | |
| UCACHE_SERVING_CYCLE_OFF_PATH 230 230 | |
| ICACHE_CYCLE_ONPATH 335287 99.712% 335287 99.712% | |
| ICACHE_CYCLE_OFFPATH 969 0.288% 969 0.288% | |
| 336256 100.000% 336256 100.000% | |
| 0.00 0.05 0.00 0.05 | |
| FETCH_ON_PATH 335294 99.714% 335294 99.714% | |
| FETCH_OFF_PATH 962 0.286% 962 0.286% | |
| 336256 100.000% 336256 100.000% | |
| 0.00 0.05 0.00 0.05 | |
| FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% | |
| FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| INST_LOST_FETCH 1261450 46.974% 1261450 46.974% | |
| INST_LOST_OFF_PATH 2363 0.088% 2363 0.088% | |
| INST_LOST_FULL_WINDOW 239704 8.926% 239704 8.926% | |
| INST_LOST_ROB_STALL_OTHER 734784 27.362% 734784 27.362% | |
| INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 134504 5.009% 134504 5.009% | |
| INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% | |
| INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_DONT 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_FT_UNAVAILABLE 42 0.002% 42 0.002% | |
| INST_LOST_BREAK_ICACHE_STAGE_RESTEER 756 0.028% 756 0.028% | |
| INST_LOST_BREAK_ICACHE_MISS_REQ_SUCCESS 117 0.004% 117 0.004% | |
| INST_LOST_BREAK_ICACHE_MISS_REQ_FAILURE 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_ICACHE_WAIT_FOR_MISS 10158 0.378% 10158 0.378% | |
| INST_LOST_BREAK_ICACHE_STALLED 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_ICACHE_TO_UOP_CACHE_SWITCH 7 0.000% 7 0.000% | |
| INST_LOST_BREAK_ICACHE_READ_LIMIT 15 0.001% 15 0.001% | |
| INST_LOST_BREAK_ICACHE_ISSUE_WIDTH 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_UOP_CACHE_STALLED 972 0.036% 972 0.036% | |
| INST_LOST_BREAK_UOP_CACHE_TO_ICACHE_SWITCH 28 0.001% 28 0.001% | |
| INST_LOST_BREAK_UOP_CACHE_READ_LIMIT 300526 11.191% 300526 11.191% | |
| INST_LOST_BREAK_UOP_CACHE_ISSUE_WIDTH 0 0.000% 0 0.000% | |
| 2685426 100.000% 2685426 100.000% | |
| 4.21 6.82 4.21 6.82 | |
| INST_LOST_TOTAL 2685880 2685880 | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_NOT_PREFETCHED 3690 47.271% 3690 47.271% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH 0 0.000% 0 0.000% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP 0 0.000% 0 0.000% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_MSHR_HIT_PREF_OFFPATH 78 0.999% 78 0.999% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_MSHR_HIT_PREF_ONPATH 4038 51.729% 4038 51.729% | |
| 7806 100.000% 7806 100.000% | |
| 2.10 2.04 2.10 2.04 | |
| FETCH_0_OPS 1833 0.545% 1833 0.545% | |
| FETCH_1_OPS 113 0.034% 113 0.034% | |
| FETCH_2_OPS 3 0.001% 3 0.001% | |
| FETCH_3_OPS 15075 4.483% 15075 4.483% | |
| FETCH_4_OPS 30068 8.942% 30068 8.942% | |
| FETCH_5_OPS 15052 4.476% 15052 4.476% | |
| FETCH_6_OPS 30256 8.998% 30256 8.998% | |
| FETCH_7_OPS 1 0.000% 1 0.000% | |
| FETCH_8_OPS 243855 72.521% 243855 72.521% | |
| FETCH_9_OPS 0 0.000% 0 0.000% | |
| FETCH_10_OPS 0 0.000% 0 0.000% | |
| FETCH_11_OPS 0 0.000% 0 0.000% | |
| FETCH_12_OPS 0 0.000% 0 0.000% | |
| FETCH_13_OPS 0 0.000% 0 0.000% | |
| FETCH_14_OPS 0 0.000% 0 0.000% | |
| FETCH_15_OPS 0 0.000% 0 0.000% | |
| FETCH_16_OPS 0 0.000% 0 0.000% | |
| 336256 100.000% 336256 100.000% | |
| 7.06 1.59 7.06 1.59 | |
| ST_BREAK_DONT 0 0.000% 0 0.000% | |
| ST_BREAK_FT_UNAVAILABLE 7 0.002% 7 0.002% | |
| ST_BREAK_ICACHE_STAGE_RESTEER 126 0.037% 126 0.037% | |
| ST_BREAK_ICACHE_MISS_REQ_SUCCESS 34 0.010% 34 0.010% | |
| ST_BREAK_ICACHE_MISS_REQ_FAILURE 0 0.000% 0 0.000% | |
| ST_BREAK_ICACHE_WAIT_FOR_MISS 1693 0.503% 1693 0.503% | |
| ST_BREAK_ICACHE_STALLED 35 0.010% 35 0.010% | |
| ST_BREAK_ICACHE_TO_UOP_CACHE_SWITCH 4 0.001% 4 0.001% | |
| ST_BREAK_ICACHE_READ_LIMIT 6 0.002% 6 0.002% | |
| ST_BREAK_ICACHE_ISSUE_WIDTH 179 0.053% 179 0.053% | |
| ST_BREAK_UOP_CACHE_STALLED 138776 41.271% 138776 41.271% | |
| ST_BREAK_UOP_CACHE_TO_ICACHE_SWITCH 4 0.001% 4 0.001% | |
| ST_BREAK_UOP_CACHE_READ_LIMIT 90155 26.811% 90155 26.811% | |
| ST_BREAK_UOP_CACHE_ISSUE_WIDTH 105237 31.297% 105237 31.297% | |
| 336256 100.000% 336256 100.000% | |
| 11.45 6.55 11.45 6.55 | |
| ORACLE_ON_PATH_INST 1261450 99.813% 1261450 99.813% | |
| ORACLE_OFF_PATH_INST 2363 0.187% 2363 0.187% | |
| 1263813 100.000% 1263813 100.000% | |
| 0.00 0.04 0.00 0.04 | |
| ORACLE_ON_PATH_INST_MEM 450518 35.648% 450518 35.648% | |
| ORACLE_ON_PATH_INST_NOTMEM 810932 64.166% 810932 64.166% | |
| ORACLE_OFF_PATH_INST_MEM 451 0.036% 451 0.036% | |
| ORACLE_OFF_PATH_INST_NOTMEM 1912 0.151% 1912 0.151% | |
| 1263813 100.000% 1263813 100.000% | |
| 0.65 0.30 0.65 0.30 | |
| ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 | |
| FETCH_ALL_INST 1263813 1263813 | |
| EXEC_ALL_INST 1262930 1262930 | |
| RET_ALL_INST 1261450 1261450 | |
| EXEC_ON_PATH_INST 1261450 99.883% 1261450 99.883% | |
| EXEC_OFF_PATH_INST 1480 0.117% 1480 0.117% | |
| 1262930 100.000% 1262930 100.000% | |
| 0.00 0.03 0.00 0.03 | |
| EXEC_ON_PATH_INST_MEM 450518 35.672% 450518 35.672% | |
| EXEC_ON_PATH_INST_NOTMEM 810932 64.210% 810932 64.210% | |
| EXEC_OFF_PATH_INST_MEM 185 0.015% 185 0.015% | |
| EXEC_OFF_PATH_INST_NOTMEM 1295 0.103% 1295 0.103% | |
| 1262930 100.000% 1262930 100.000% | |
| 0.65 0.30 0.65 0.30 | |
| EXEC_RA_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_INST 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% | |
| EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% | |
| EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_THROTTLE_CYCLE 0 0 | |
| FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% | |
| FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% | |
| FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_TH_ADJUST__0 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__1 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__2 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__3 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__4 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__5 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__6 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__7 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__8 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__9 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__MAX 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_TH_ADJUST_UP 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 | |
| LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_RESTEER_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_RESTEER_RECOVER_AT_EXEC_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_EXEC_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_UOC_IC_SWITCH 0 0 | |