hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /12 /memory.stat.0.csv
| Core, 0, 0 | |
| Cumulative_Cycles, 0, 336256 | |
| Cumulative_Instructions, 0, 961103 | |
| Periodic_Cycles, 0, 336256 | |
| Periodic_Instructions, 0, 961103 | |
| ICACHE_MISS_count, 197, 34 | |
| ICACHE_MISS_total_count, 197, 34 | |
| ICACHE_HIT_count, 197, 45 | |
| ICACHE_HIT_total_count, 197, 45 | |
| ICACHE_MISS_ONPATH_count, 198, 7 | |
| ICACHE_MISS_ONPATH_total_count, 198, 7 | |
| ICACHE_MISS_OFFPATH_count, 198, 27 | |
| ICACHE_MISS_OFFPATH_total_count, 198, 27 | |
| ICACHE_MISS_NOT_PREFETCHED_count, 199, 2 | |
| ICACHE_MISS_NOT_PREFETCHED_total_count, 199, 2 | |
| ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH_count, 199, 0 | |
| ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH_total_count, 199, 0 | |
| ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP_count, 199, 0 | |
| ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP_total_count, 199, 0 | |
| ICACHE_MISS_MSHR_HIT_PREFETCHED_OFFPATH_count, 199, 27 | |
| ICACHE_MISS_MSHR_HIT_PREFETCHED_OFFPATH_total_count, 199, 27 | |
| ICACHE_MISS_MSHR_HIT_PREFETCHED_ONPATH_count, 199, 4 | |
| ICACHE_MISS_MSHR_HIT_PREFETCHED_ONPATH_total_count, 199, 4 | |
| ICACHE_HIT_ONPATH_count, 200, 9 | |
| ICACHE_HIT_ONPATH_total_count, 200, 9 | |
| ICACHE_HIT_OFFPATH_count, 200, 36 | |
| ICACHE_HIT_OFFPATH_total_count, 200, 36 | |
| ICACHE_HIT_ONPATH_SAT_BY_OFFPATH_count, 201, 0 | |
| ICACHE_HIT_ONPATH_SAT_BY_OFFPATH_total_count, 201, 0 | |
| ICACHE_HIT_ONPATH_SAT_BY_ONPATH_count, 201, 0 | |
| ICACHE_HIT_ONPATH_SAT_BY_ONPATH_total_count, 201, 0 | |
| ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH_count, 202, 0 | |
| ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH_total_count, 202, 0 | |
| ICACHE_HIT_OFFPATH_SAT_BY_ONPATH_count, 202, 0 | |
| ICACHE_HIT_OFFPATH_SAT_BY_ONPATH_total_count, 202, 0 | |
| ICACHE_HIT_BY_FDIP_ONPATH_count, 203, 0 | |
| ICACHE_HIT_BY_FDIP_ONPATH_total_count, 203, 0 | |
| ICACHE_HIT_BY_FDIP_OFFPATH_count, 203, 0 | |
| ICACHE_HIT_BY_FDIP_OFFPATH_total_count, 203, 0 | |
| ICACHE_MISS_MSHR_HIT_BY_FDIP_ONPATH_count, 204, 3 | |
| ICACHE_MISS_MSHR_HIT_BY_FDIP_ONPATH_total_count, 204, 3 | |
| ICACHE_MISS_MSHR_HIT_BY_FDIP_OFFPATH_count, 204, 28 | |
| ICACHE_MISS_MSHR_HIT_BY_FDIP_OFFPATH_total_count, 204, 28 | |
| ICACHE_HIT_ONPATH_BY_FDIP_count, 205, 0 | |
| ICACHE_HIT_ONPATH_BY_FDIP_total_count, 205, 0 | |
| ICACHE_HIT_OFFPATH_BY_FDIP_count, 205, 0 | |
| ICACHE_HIT_OFFPATH_BY_FDIP_total_count, 205, 0 | |
| ICACHE_MISS_MSHR_HIT_ONPATH_BY_FDIP_count, 205, 5 | |
| ICACHE_MISS_MSHR_HIT_ONPATH_BY_FDIP_total_count, 205, 5 | |
| ICACHE_MISS_MSHR_HIT_OFFPATH_BY_FDIP_count, 205, 26 | |
| ICACHE_MISS_MSHR_HIT_OFFPATH_BY_FDIP_total_count, 205, 26 | |
| ICACHE_MISS_TOO_EARLY_ONPATH_count, 205, 0 | |
| ICACHE_MISS_TOO_EARLY_ONPATH_total_count, 205, 0 | |
| ICACHE_MISS_TOO_EARLY_OFFPATH_count, 205, 0 | |
| ICACHE_MISS_TOO_EARLY_OFFPATH_total_count, 205, 0 | |
| ICACHE_MISS_NOT_PREFETCHED_ONPATH_count, 205, 2 | |
| ICACHE_MISS_NOT_PREFETCHED_ONPATH_total_count, 205, 2 | |
| ICACHE_MISS_NOT_PREFETCHED_OFFPATH_count, 205, 1 | |
| ICACHE_MISS_NOT_PREFETCHED_OFFPATH_total_count, 205, 1 | |
| ICACHE_MISS_MEM_REQ_FAIL_ON_PATH_count, 206, 0 | |
| ICACHE_MISS_MEM_REQ_FAIL_ON_PATH_total_count, 206, 0 | |
| ICACHE_MISS_MEM_REQ_SUCCESS_ON_PATH_count, 206, 2 | |
| ICACHE_MISS_MEM_REQ_SUCCESS_ON_PATH_total_count, 206, 2 | |
| ICACHE_UNIQUE_MISSED_LINES_count, 0, 5 | |
| ICACHE_UNIQUE_MISSED_LINES_total_count, 0, 5 | |
| ICACHE_UNIQUE_HIT_LINES_count, 0, 0 | |
| ICACHE_UNIQUE_HIT_LINES_total_count, 0, 0 | |
| ICACHE_OVERTAKE_FDIP_count, 0, 0 | |
| ICACHE_OVERTAKE_FDIP_total_count, 0, 0 | |
| FT_UOP_CACHE_HIT_ON_PATH_count, 207, 150162 | |
| FT_UOP_CACHE_HIT_ON_PATH_total_count, 207, 150162 | |
| FT_UOP_CACHE_MISS_ICACHE_HIT_ON_PATH_count, 207, 9 | |
| FT_UOP_CACHE_MISS_ICACHE_HIT_ON_PATH_total_count, 207, 9 | |
| FT_UOP_CACHE_MISS_ICACHE_MISS_ON_PATH_count, 207, 7 | |
| FT_UOP_CACHE_MISS_ICACHE_MISS_ON_PATH_total_count, 207, 7 | |
| FT_UOP_CACHE_HIT_OFF_PATH_count, 208, 132 | |
| FT_UOP_CACHE_HIT_OFF_PATH_total_count, 208, 132 | |
| FT_UOP_CACHE_MISS_ICACHE_HIT_OFF_PATH_count, 208, 36 | |
| FT_UOP_CACHE_MISS_ICACHE_HIT_OFF_PATH_total_count, 208, 36 | |
| FT_UOP_CACHE_MISS_ICACHE_MISS_OFF_PATH_count, 208, 27 | |
| FT_UOP_CACHE_MISS_ICACHE_MISS_OFF_PATH_total_count, 208, 27 | |
| UOPS_SERVED_BY_ICACHE_ON_PATH_count, 209, 101 | |
| UOPS_SERVED_BY_ICACHE_ON_PATH_total_count, 209, 101 | |
| UOPS_SERVED_BY_UOP_CACHE_ON_PATH_count, 209, 1261349 | |
| UOPS_SERVED_BY_UOP_CACHE_ON_PATH_total_count, 209, 1261349 | |
| UOPS_SERVED_BY_ICACHE_OFF_PATH_count, 210, 1098 | |
| UOPS_SERVED_BY_ICACHE_OFF_PATH_total_count, 210, 1098 | |
| UOPS_SERVED_BY_UOP_CACHE_OFF_PATH_count, 210, 1265 | |
| UOPS_SERVED_BY_UOP_CACHE_OFF_PATH_total_count, 210, 1265 | |
| UOP_CACHE_FT_INSERTED_ONPATH_USED_ONPATH_count, 0, 4 | |
| UOP_CACHE_FT_INSERTED_ONPATH_USED_ONPATH_total_count, 0, 4 | |
| UOP_CACHE_FT_INSERTED_OFFPATH_USED_ONPATH_count, 0, 6 | |
| UOP_CACHE_FT_INSERTED_OFFPATH_USED_ONPATH_total_count, 0, 6 | |
| UOP_CACHE_LINE_INSERTED_ONPATH_USED_ONPATH_count, 0, 9 | |
| UOP_CACHE_LINE_INSERTED_ONPATH_USED_ONPATH_total_count, 0, 9 | |
| UOP_CACHE_LINE_INSERTED_OFFPATH_USED_ONPATH_count, 0, 7 | |
| UOP_CACHE_LINE_INSERTED_OFFPATH_USED_ONPATH_total_count, 0, 7 | |
| UOP_CACHE_PREFETCH_count, 0, 0 | |
| UOP_CACHE_PREFETCH_total_count, 0, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_ON_PATH_count, 211, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_ON_PATH_total_count, 211, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_ON_PATH_count, 211, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_ON_PATH_total_count, 211, 0 | |
| UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_ON_PATH_count, 211, 1 | |
| UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_ON_PATH_total_count, 211, 1 | |
| UOP_CACHE_FT_INSERT_SUCCEEDED_ON_PATH_count, 211, 14 | |
| UOP_CACHE_FT_INSERT_SUCCEEDED_ON_PATH_total_count, 211, 14 | |
| UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_OFF_PATH_count, 212, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_OFF_PATH_total_count, 212, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_OFF_PATH_count, 212, 0 | |
| UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_OFF_PATH_total_count, 212, 0 | |
| UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_OFF_PATH_count, 212, 0 | |
| UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_OFF_PATH_total_count, 212, 0 | |
| UOP_CACHE_FT_INSERT_SUCCEEDED_OFF_PATH_count, 212, 51 | |
| UOP_CACHE_FT_INSERT_SUCCEEDED_OFF_PATH_total_count, 212, 51 | |
| UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_ON_PATH_count, 213, 0 | |
| UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_ON_PATH_total_count, 213, 0 | |
| UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_ON_PATH_count, 213, 0 | |
| UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_ON_PATH_total_count, 213, 0 | |
| UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_ON_PATH_count, 213, 1 | |
| UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_ON_PATH_total_count, 213, 1 | |
| UOP_CACHE_LINE_INSERT_SUCCEEDED_ON_PATH_count, 213, 25 | |
| UOP_CACHE_LINE_INSERT_SUCCEEDED_ON_PATH_total_count, 213, 25 | |
| UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_OFF_PATH_count, 214, 0 | |
| UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_OFF_PATH_total_count, 214, 0 | |
| UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_OFF_PATH_count, 214, 0 | |
| UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_OFF_PATH_total_count, 214, 0 | |
| UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_OFF_PATH_count, 214, 0 | |
| UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_OFF_PATH_total_count, 214, 0 | |
| UOP_CACHE_LINE_INSERT_SUCCEEDED_OFF_PATH_count, 214, 141 | |
| UOP_CACHE_LINE_INSERT_SUCCEEDED_OFF_PATH_total_count, 214, 141 | |
| UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_RESTEERED_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_RESTEERED_total_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_CORRECT_PRED_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_CORRECT_PRED_total_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_RESTEERED_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_RESTEERED_total_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_CORRECT_PRED_count, 215, 0 | |
| UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_CORRECT_PRED_total_count, 215, 0 | |
| UOP_CACHE_FT_LINES_1_ON_PATH_count, 216, 8 | |
| UOP_CACHE_FT_LINES_1_ON_PATH_total_count, 216, 8 | |
| UOP_CACHE_FT_LINES_2_ON_PATH_count, 216, 3 | |
| UOP_CACHE_FT_LINES_2_ON_PATH_total_count, 216, 3 | |
| UOP_CACHE_FT_LINES_3_ON_PATH_count, 216, 4 | |
| UOP_CACHE_FT_LINES_3_ON_PATH_total_count, 216, 4 | |
| UOP_CACHE_FT_LINES_4_ON_PATH_count, 216, 0 | |
| UOP_CACHE_FT_LINES_4_ON_PATH_total_count, 216, 0 | |
| UOP_CACHE_FT_LINES_5_ON_PATH_count, 216, 0 | |
| UOP_CACHE_FT_LINES_5_ON_PATH_total_count, 216, 0 | |
| UOP_CACHE_FT_LINES_6_ON_PATH_count, 216, 0 | |
| UOP_CACHE_FT_LINES_6_ON_PATH_total_count, 216, 0 | |
| UOP_CACHE_FT_LINES_7_ON_PATH_count, 216, 0 | |
| UOP_CACHE_FT_LINES_7_ON_PATH_total_count, 216, 0 | |
| UOP_CACHE_FT_LINES_8_ON_PATH_count, 216, 0 | |
| UOP_CACHE_FT_LINES_8_ON_PATH_total_count, 216, 0 | |
| UOP_CACHE_FT_LINES_9_AND_MORE_ON_PATH_count, 216, 0 | |
| UOP_CACHE_FT_LINES_9_AND_MORE_ON_PATH_total_count, 216, 0 | |
| UOP_CACHE_FT_LINES_1_OFF_PATH_count, 217, 5 | |
| UOP_CACHE_FT_LINES_1_OFF_PATH_total_count, 217, 5 | |
| UOP_CACHE_FT_LINES_2_OFF_PATH_count, 217, 3 | |
| UOP_CACHE_FT_LINES_2_OFF_PATH_total_count, 217, 3 | |
| UOP_CACHE_FT_LINES_3_OFF_PATH_count, 217, 42 | |
| UOP_CACHE_FT_LINES_3_OFF_PATH_total_count, 217, 42 | |
| UOP_CACHE_FT_LINES_4_OFF_PATH_count, 217, 1 | |
| UOP_CACHE_FT_LINES_4_OFF_PATH_total_count, 217, 1 | |
| UOP_CACHE_FT_LINES_5_OFF_PATH_count, 217, 0 | |
| UOP_CACHE_FT_LINES_5_OFF_PATH_total_count, 217, 0 | |
| UOP_CACHE_FT_LINES_6_OFF_PATH_count, 217, 0 | |
| UOP_CACHE_FT_LINES_6_OFF_PATH_total_count, 217, 0 | |
| UOP_CACHE_FT_LINES_7_OFF_PATH_count, 217, 0 | |
| UOP_CACHE_FT_LINES_7_OFF_PATH_total_count, 217, 0 | |
| UOP_CACHE_FT_LINES_8_OFF_PATH_count, 217, 0 | |
| UOP_CACHE_FT_LINES_8_OFF_PATH_total_count, 217, 0 | |
| UOP_CACHE_FT_LINES_9_AND_MORE_OFF_PATH_count, 217, 0 | |
| UOP_CACHE_FT_LINES_9_AND_MORE_OFF_PATH_total_count, 217, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_1_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_1_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_2_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_2_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_3_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_3_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_4_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_4_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_5_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_5_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_6_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_6_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_7_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_7_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_8_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_8_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_9_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_9_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_10_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_10_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_11_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_11_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_12_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_12_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_13_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_13_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_14_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_14_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_15_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_15_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_16_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_16_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_17_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_17_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_18_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_18_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_19_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_19_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_20_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_20_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_21_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_21_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_22_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_22_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_23_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_23_total_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_24_count, 218, 0 | |
| UOP_CACHE_PREFETCH_PW_LENGTH_24_total_count, 218, 0 | |
| DCACHE_MISS_count, 219, 30047 | |
| DCACHE_MISS_total_count, 219, 30047 | |
| DCACHE_ST_BUFFER_HIT_count, 219, 0 | |
| DCACHE_ST_BUFFER_HIT_total_count, 219, 0 | |
| DCACHE_HIT_count, 219, 420471 | |
| DCACHE_HIT_total_count, 219, 420471 | |
| DCACHE_MISS_ONPATH_count, 220, 30047 | |
| DCACHE_MISS_ONPATH_total_count, 220, 30047 | |
| DCACHE_MISS_OFFPATH_count, 220, 14 | |
| DCACHE_MISS_OFFPATH_total_count, 220, 14 | |
| DCACHE_ST_BUFFER_HIT_ONPATH_count, 221, 0 | |
| DCACHE_ST_BUFFER_HIT_ONPATH_total_count, 221, 0 | |
| DCACHE_ST_BUFFER_HIT_OFFPATH_count, 221, 0 | |
| DCACHE_ST_BUFFER_HIT_OFFPATH_total_count, 221, 0 | |
| DCACHE_HIT_ONPATH_count, 222, 420471 | |
| DCACHE_HIT_ONPATH_total_count, 222, 420471 | |
| DCACHE_HIT_OFFPATH_count, 222, 167 | |
| DCACHE_HIT_OFFPATH_total_count, 222, 167 | |
| DCACHE_HIT_ONPATH_SAT_BY_OFFPATH_count, 223, 0 | |
| DCACHE_HIT_ONPATH_SAT_BY_OFFPATH_total_count, 223, 0 | |
| DCACHE_HIT_ONPATH_SAT_BY_ONPATH_count, 223, 420471 | |
| DCACHE_HIT_ONPATH_SAT_BY_ONPATH_total_count, 223, 420471 | |
| DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH_count, 224, 0 | |
| DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH_total_count, 224, 0 | |
| DCACHE_HIT_OFFPATH_SAT_BY_ONPATH_count, 224, 167 | |
| DCACHE_HIT_OFFPATH_SAT_BY_ONPATH_total_count, 224, 167 | |
| DCACHE_MISS_LD_count, 225, 30044 | |
| DCACHE_MISS_LD_total_count, 225, 30044 | |
| DCACHE_MISS_ST_count, 225, 3 | |
| DCACHE_MISS_ST_total_count, 225, 3 | |
| DCACHE_MISS_LD_ONPATH_count, 226, 30044 | |
| DCACHE_MISS_LD_ONPATH_total_count, 226, 30044 | |
| DCACHE_MISS_LD_OFFPATH_count, 226, 8 | |
| DCACHE_MISS_LD_OFFPATH_total_count, 226, 8 | |
| DCACHE_MISS_ST_ONPATH_count, 227, 3 | |
| DCACHE_MISS_ST_ONPATH_total_count, 227, 3 | |
| DCACHE_MISS_ST_OFFPATH_count, 227, 6 | |
| DCACHE_MISS_ST_OFFPATH_total_count, 227, 6 | |
| DCACHE_MISS_WAITMEM_count, 0, 1 | |
| DCACHE_MISS_WAITMEM_total_count, 0, 1 | |
| MEM_REQ_ROW_BUFFER_HITS_count, 228, 0 | |
| MEM_REQ_ROW_BUFFER_HITS_total_count, 228, 0 | |
| MEM_REQ_ROW_BUFFER_MISSES_count, 228, 0 | |
| MEM_REQ_ROW_BUFFER_MISSES_total_count, 228, 0 | |
| MEM_REQ_ROW_BUFFER_CONFLICTS_count, 228, 0 | |
| MEM_REQ_ROW_BUFFER_CONFLICTS_total_count, 228, 0 | |
| SHADOW_ROW_BUFFER_HITS_count, 0, 0 | |
| SHADOW_ROW_BUFFER_HITS_total_count, 0, 0 | |
| SHADOW_ROW_HIT_STALL_TIME_count, 0, 0 | |
| SHADOW_ROW_HIT_STALL_TIME_total_count, 0, 0 | |
| CHANNEL0_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL0_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL1_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL1_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL2_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL2_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL3_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL3_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL4_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL4_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL5_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL5_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL6_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL6_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL7_BUS_BUSY_CYCLES_count, 229, 0 | |
| CHANNEL7_BUS_BUSY_CYCLES_total_count, 229, 0 | |
| CHANNEL_IDLE_DESPITE_READY_CMD_count, 0, 0 | |
| CHANNEL_IDLE_DESPITE_READY_CMD_total_count, 0, 0 | |
| MEM_NUM_TOTAL_BUS_CYCLES_count, 0, 0 | |
| MEM_NUM_TOTAL_BUS_CYCLES_total_count, 0, 0 | |
| MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CORE_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CORE_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CORE_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CORE_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES_count, 230, 0 | |
| CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES_total_count, 230, 0 | |
| CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_count, 0, 0 | |
| CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_pct, 0, -nan | |
| CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_count, 0, 0 | |
| CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE_total_pct, 0, -nan | |
| RAMULATOR_QUEUE_ENQUEUED_count, 0, 0 | |
| RAMULATOR_QUEUE_ENQUEUED_total_count, 0, 0 | |
| RAMULATOR_QUEUE_FULL_count, 0, 0 | |
| RAMULATOR_QUEUE_FULL_total_count, 0, 0 | |
| BUS_DEMAND_ACCESS_count, 0, 117 | |
| BUS_DEMAND_ACCESS_total_count, 0, 117 | |
| BUS_PREF_ACCESS_count, 0, 15026 | |
| BUS_PREF_ACCESS_total_count, 0, 15026 | |
| BUS_ACCESS_count, 0, 0 | |
| BUS_ACCESS_total_count, 0, 0 | |
| L1_DEMAND_ACCESS_count, 0, 30542 | |
| L1_DEMAND_ACCESS_total_count, 0, 30542 | |
| L1_PREF_ACCESS_count, 0, 30150 | |
| L1_PREF_ACCESS_total_count, 0, 30150 | |
| L1_ACCESS_count, 0, 44985 | |
| L1_ACCESS_total_count, 0, 44985 | |
| MLC_DEMAND_ACCESS_count, 0, 29052 | |
| MLC_DEMAND_ACCESS_total_count, 0, 29052 | |
| MLC_PREF_ACCESS_count, 0, 100 | |
| MLC_PREF_ACCESS_total_count, 0, 100 | |
| MLC_ACCESS_count, 0, 29152 | |
| MLC_ACCESS_total_count, 0, 29152 | |
| L1_HIT_count, 231, 14521 | |
| L1_HIT_total_count, 231, 14521 | |
| L1_MISS_count, 231, 21 | |
| L1_MISS_total_count, 231, 21 | |
| L1_HIT_ALL_count, 232, 15202 | |
| L1_HIT_ALL_total_count, 232, 15202 | |
| L1_MISS_ALL_count, 232, 15143 | |
| L1_MISS_ALL_total_count, 232, 15143 | |
| L1_DEMAND_MISS_count, 233, 20 | |
| L1_DEMAND_MISS_total_count, 233, 20 | |
| L1_PREF_REQ_MISS_count, 233, 15026 | |
| L1_PREF_REQ_MISS_total_count, 233, 15026 | |
| L1_WB_MISS_count, 233, 97 | |
| L1_WB_MISS_total_count, 233, 97 | |
| L1_DEMAND_HIT_count, 234, 14521 | |
| L1_DEMAND_HIT_total_count, 234, 14521 | |
| L1_PREF_REQ_HIT_count, 234, 0 | |
| L1_PREF_REQ_HIT_total_count, 234, 0 | |
| L1_WB_HIT_count, 234, 681 | |
| L1_WB_HIT_total_count, 234, 681 | |
| L1_MISS_ONPATH_count, 235, 21 | |
| L1_MISS_ONPATH_total_count, 235, 21 | |
| L1_MISS_OFFPATH_count, 235, 0 | |
| L1_MISS_OFFPATH_total_count, 235, 0 | |
| L1_MISS_ALL_ONPATH_count, 236, 15047 | |
| L1_MISS_ALL_ONPATH_total_count, 236, 15047 | |
| L1_MISS_ALL_OFFPATH_count, 236, 96 | |
| L1_MISS_ALL_OFFPATH_total_count, 236, 96 | |
| L1_HIT_ONPATH_count, 237, 14521 | |
| L1_HIT_ONPATH_total_count, 237, 14521 | |
| L1_HIT_OFFPATH_count, 237, 0 | |
| L1_HIT_OFFPATH_total_count, 237, 0 | |
| L1_HIT_ALL_ONPATH_count, 238, 15202 | |
| L1_HIT_ALL_ONPATH_total_count, 238, 15202 | |
| L1_HIT_ALL_OFFPATH_count, 238, 0 | |
| L1_HIT_ALL_OFFPATH_total_count, 238, 0 | |
| L1_HIT_ONPATH_SAT_BY_OFFPATH_count, 239, 0 | |
| L1_HIT_ONPATH_SAT_BY_OFFPATH_total_count, 239, 0 | |
| L1_HIT_ONPATH_SAT_BY_ONPATH_count, 239, 15202 | |
| L1_HIT_ONPATH_SAT_BY_ONPATH_total_count, 239, 15202 | |
| L1_HIT_OFFPATH_SAT_BY_OFFPATH_count, 240, 0 | |
| L1_HIT_OFFPATH_SAT_BY_OFFPATH_total_count, 240, 0 | |
| L1_HIT_OFFPATH_SAT_BY_ONPATH_count, 240, 0 | |
| L1_HIT_OFFPATH_SAT_BY_ONPATH_total_count, 240, 0 | |
| L1_HIT_ONPATH_IFETCH_SAT_BY_OFFPATH_count, 241, 0 | |
| L1_HIT_ONPATH_IFETCH_SAT_BY_OFFPATH_total_count, 241, 0 | |
| L1_HIT_ONPATH_IFETCH_SAT_BY_ONPATH_count, 241, 0 | |
| L1_HIT_ONPATH_IFETCH_SAT_BY_ONPATH_total_count, 241, 0 | |
| L1_HIT_ONPATH_DATA_SAT_BY_OFFPATH_count, 242, 0 | |
| L1_HIT_ONPATH_DATA_SAT_BY_OFFPATH_total_count, 242, 0 | |
| L1_HIT_ONPATH_DATA_SAT_BY_ONPATH_count, 242, 14521 | |
| L1_HIT_ONPATH_DATA_SAT_BY_ONPATH_total_count, 242, 14521 | |
| L1_FILL_OFFPATH_IFETCH_count, 0, 0 | |
| L1_FILL_OFFPATH_IFETCH_total_count, 0, 0 | |
| L1_FILL_OFFPATH_DATA_count, 0, 0 | |
| L1_FILL_OFFPATH_DATA_total_count, 0, 0 | |
| L1_FILL_OFFPATH_count, 0, 96 | |
| L1_FILL_OFFPATH_total_count, 0, 96 | |
| L1_USE_OFFPATH_IFETCH_count, 0, 0 | |
| L1_USE_OFFPATH_IFETCH_pct, 0, -nan | |
| L1_USE_OFFPATH_IFETCH_total_count, 0, 0 | |
| L1_USE_OFFPATH_IFETCH_total_pct, 0, -nan | |
| L1_USE_OFFPATH_DATA_count, 0, 0 | |
| L1_USE_OFFPATH_DATA_pct, 0, -nan | |
| L1_USE_OFFPATH_DATA_total_count, 0, 0 | |
| L1_USE_OFFPATH_DATA_total_pct, 0, -nan | |
| L1_USE_OFFPATH_count, 0, 0 | |
| L1_USE_OFFPATH_pct, 0, 0.000 | |
| L1_USE_OFFPATH_total_count, 0, 0 | |
| L1_USE_OFFPATH_total_pct, 0, 0.000 | |
| JUST_L1_USE_OFFPATH_count, 0, 0 | |
| JUST_L1_USE_OFFPATH_pct, 0, 0.000 | |
| JUST_L1_USE_OFFPATH_total_count, 0, 0 | |
| JUST_L1_USE_OFFPATH_total_pct, 0, 0.000 | |
| L1_FILL_ONPATH_IFETCH_count, 0, 6 | |
| L1_FILL_ONPATH_IFETCH_total_count, 0, 6 | |
| L1_FILL_ONPATH_DATA_count, 0, 505 | |
| L1_FILL_ONPATH_DATA_total_count, 0, 505 | |
| L1_FILL_ONPATH_count, 0, 512 | |
| L1_FILL_ONPATH_total_count, 0, 512 | |
| L1_USE_ONPATH_IFETCH_count, 0, 0 | |
| L1_USE_ONPATH_IFETCH_pct, 0, 0.000 | |
| L1_USE_ONPATH_IFETCH_total_count, 0, 0 | |
| L1_USE_ONPATH_IFETCH_total_pct, 0, 0.000 | |
| L1_USE_ONPATH_DATA_count, 0, 14521 | |
| L1_USE_ONPATH_DATA_pct, 0, 28.754 | |
| L1_USE_ONPATH_DATA_total_count, 0, 14521 | |
| L1_USE_ONPATH_DATA_total_pct, 0, 28.754 | |
| L1_USE_ONPATH_count, 0, 15202 | |
| L1_USE_ONPATH_pct, 0, 29.691 | |
| L1_USE_ONPATH_total_count, 0, 15202 | |
| L1_USE_ONPATH_total_pct, 0, 29.691 | |
| L1_CYCLE_count, 0, 336256 | |
| L1_CYCLE_total_count, 0, 336256 | |
| L1_LINES_count, 0, 2551878659 | |
| L1_LINES_pct, 0, 7589.095 | |
| L1_LINES_total_count, 0, 2551878659 | |
| L1_LINES_total_pct, 0, 7589.095 | |
| MLC_HIT_count, 243, 0 | |
| MLC_HIT_total_count, 243, 0 | |
| MLC_MISS_count, 243, 14541 | |
| MLC_MISS_total_count, 243, 14541 | |
| MLC_HIT_ALL_count, 244, 14513 | |
| MLC_HIT_ALL_total_count, 244, 14513 | |
| MLC_MISS_ALL_count, 244, 14638 | |
| MLC_MISS_ALL_total_count, 244, 14638 | |
| MLC_DEMAND_MISS_count, 245, 14541 | |
| MLC_DEMAND_MISS_total_count, 245, 14541 | |
| MLC_PREF_REQ_MISS_count, 245, 0 | |
| MLC_PREF_REQ_MISS_total_count, 245, 0 | |
| MLC_WB_MISS_count, 245, 97 | |
| MLC_WB_MISS_total_count, 245, 97 | |
| MLC_DEMAND_HIT_count, 246, 0 | |
| MLC_DEMAND_HIT_total_count, 246, 0 | |
| MLC_PREF_REQ_HIT_count, 246, 0 | |
| MLC_PREF_REQ_HIT_total_count, 246, 0 | |
| MLC_WB_HIT_count, 246, 14513 | |
| MLC_WB_HIT_total_count, 246, 14513 | |
| MLC_MISS_ONPATH_count, 247, 14540 | |
| MLC_MISS_ONPATH_total_count, 247, 14540 | |
| MLC_MISS_OFFPATH_count, 247, 1 | |
| MLC_MISS_OFFPATH_total_count, 247, 1 | |
| MLC_MISS_ALL_ONPATH_count, 248, 14541 | |
| MLC_MISS_ALL_ONPATH_total_count, 248, 14541 | |
| MLC_MISS_ALL_OFFPATH_count, 248, 97 | |
| MLC_MISS_ALL_OFFPATH_total_count, 248, 97 | |
| MLC_HIT_ONPATH_count, 249, 0 | |
| MLC_HIT_ONPATH_total_count, 249, 0 | |
| MLC_HIT_OFFPATH_count, 249, 0 | |
| MLC_HIT_OFFPATH_total_count, 249, 0 | |
| MLC_HIT_ALL_ONPATH_count, 250, 14513 | |
| MLC_HIT_ALL_ONPATH_total_count, 250, 14513 | |
| MLC_HIT_ALL_OFFPATH_count, 250, 0 | |
| MLC_HIT_ALL_OFFPATH_total_count, 250, 0 | |
| L1_QUEUE_OCCUPANCY_count, 0, 1138509 | |
| L1_QUEUE_OCCUPANCY_pct, 0, 3.386 | |
| L1_QUEUE_OCCUPANCY_total_count, 0, 1138509 | |
| L1_QUEUE_OCCUPANCY_total_pct, 0, 3.386 | |
| MLC_QUEUE_OCCUPANCY_count, 0, 1108164 | |
| MLC_QUEUE_OCCUPANCY_pct, 0, 3.296 | |
| MLC_QUEUE_OCCUPANCY_total_count, 0, 1108164 | |
| MLC_QUEUE_OCCUPANCY_total_pct, 0, 3.296 | |
| DCACHE_FILL_PORT_UNAVAILABLE_ONPATH_count, 0, 0 | |
| DCACHE_FILL_PORT_UNAVAILABLE_ONPATH_total_count, 0, 0 | |
| DCACHE_FILL_PORT_UNAVAILABLE_OFFPATH_count, 0, 0 | |
| DCACHE_FILL_PORT_UNAVAILABLE_OFFPATH_total_count, 0, 0 | |
| DCACHE_READ_PORT_UNAVAILABLE_ONPATH_count, 0, 93381 | |
| DCACHE_READ_PORT_UNAVAILABLE_ONPATH_total_count, 0, 93381 | |
| DCACHE_READ_PORT_UNAVAILABLE_OFFPATH_count, 0, 31 | |
| DCACHE_READ_PORT_UNAVAILABLE_OFFPATH_total_count, 0, 31 | |
| DCACHE_FILL_OFFPATH_count, 0, 0 | |
| DCACHE_FILL_OFFPATH_total_count, 0, 0 | |
| DCACHE_USE_OFFPATH_count, 0, 0 | |
| DCACHE_USE_OFFPATH_pct, 0, -nan | |
| DCACHE_USE_OFFPATH_total_count, 0, 0 | |
| DCACHE_USE_OFFPATH_total_pct, 0, -nan | |
| DCACHE_FILL_ONPATH_count, 0, 15026 | |
| DCACHE_FILL_ONPATH_total_count, 0, 15026 | |
| DCACHE_USE_ONPATH_count, 0, 420471 | |
| DCACHE_USE_ONPATH_pct, 0, 27.983 | |
| DCACHE_USE_ONPATH_total_count, 0, 420471 | |
| DCACHE_USE_ONPATH_total_pct, 0, 27.983 | |
| ICACHE_FILL_OFFPATH_count, 0, 96 | |
| ICACHE_FILL_OFFPATH_total_count, 0, 96 | |
| ICACHE_USE_OFFPATH_count, 0, 0 | |
| ICACHE_USE_OFFPATH_pct, 0, 0.000 | |
| ICACHE_USE_OFFPATH_total_count, 0, 0 | |
| ICACHE_USE_OFFPATH_total_pct, 0, 0.000 | |
| ICACHE_FILL_ONPATH_count, 0, 7 | |
| ICACHE_FILL_ONPATH_total_count, 0, 7 | |
| ICACHE_USE_ONPATH_count, 0, 0 | |
| ICACHE_USE_ONPATH_pct, 0, 0.000 | |
| ICACHE_USE_ONPATH_total_count, 0, 0 | |
| ICACHE_USE_ONPATH_total_pct, 0, 0.000 | |
| REQBUF_CREATE_ONPATH_count, 0, 44764 | |
| REQBUF_CREATE_ONPATH_total_count, 0, 44764 | |
| REQBUF_ONPATH_MATCH_OFFPATH_count, 0, 1 | |
| REQBUF_ONPATH_MATCH_OFFPATH_pct, 0, 0.000 | |
| REQBUF_ONPATH_MATCH_OFFPATH_total_count, 0, 1 | |
| REQBUF_ONPATH_MATCH_OFFPATH_total_pct, 0, 0.000 | |
| REQBUF_CREATE_ONPATH_DATA_count, 0, 14535 | |
| REQBUF_CREATE_ONPATH_DATA_total_count, 0, 14535 | |
| REQBUF_ONPATH_MATCH_OFFPATH_DATA_count, 0, 0 | |
| REQBUF_ONPATH_MATCH_OFFPATH_DATA_pct, 0, 0.000 | |
| REQBUF_ONPATH_MATCH_OFFPATH_DATA_total_count, 0, 0 | |
| REQBUF_ONPATH_MATCH_OFFPATH_DATA_total_pct, 0, 0.000 | |
| REQBUF_CREATE_ONPATH_IFETCH_count, 0, 2 | |
| REQBUF_CREATE_ONPATH_IFETCH_total_count, 0, 2 | |
| REQBUF_ONPATH_MATCH_OFFPATH_IFETCH_count, 0, 1 | |
| REQBUF_ONPATH_MATCH_OFFPATH_IFETCH_pct, 0, 0.500 | |
| REQBUF_ONPATH_MATCH_OFFPATH_IFETCH_total_count, 0, 1 | |
| REQBUF_ONPATH_MATCH_OFFPATH_IFETCH_total_pct, 0, 0.500 | |
| REQBUF_CREATE_OFFPATH_count, 0, 97 | |
| REQBUF_CREATE_OFFPATH_total_count, 0, 97 | |
| ONPATH_KICKED_OUT_OFFPATH_count, 0, 0 | |
| ONPATH_KICKED_OUT_OFFPATH_total_count, 0, 0 | |
| ONPATH_KICKED_OUT_PREFETCH_count, 0, 0 | |
| ONPATH_KICKED_OUT_PREFETCH_total_count, 0, 0 | |
| DIST_ICACHE_FILL_OFFPATH_USED_count, 251, 0 | |
| DIST_ICACHE_FILL_OFFPATH_USED_total_count, 251, 0 | |
| DIST_ICACHE_FILL_OFFPATH_NOTUSED_count, 251, 0 | |
| DIST_ICACHE_FILL_OFFPATH_NOTUSED_total_count, 251, 0 | |
| DIST_ICACHE_FILL_ONPATH_PARTIAL_count, 251, 1 | |
| DIST_ICACHE_FILL_ONPATH_PARTIAL_total_count, 251, 1 | |
| DIST_ICACHE_FILL_ONPATH_count, 251, 6 | |
| DIST_ICACHE_FILL_ONPATH_total_count, 251, 6 | |
| DIST_DCACHE_FILL_OFFPATH_USED_count, 252, 0 | |
| DIST_DCACHE_FILL_OFFPATH_USED_total_count, 252, 0 | |
| DIST_DCACHE_FILL_OFFPATH_NOTUSED_count, 252, 0 | |
| DIST_DCACHE_FILL_OFFPATH_NOTUSED_total_count, 252, 0 | |
| DIST_DCACHE_FILL_ONPATH_PARTIAL_count, 252, 0 | |
| DIST_DCACHE_FILL_ONPATH_PARTIAL_total_count, 252, 0 | |
| DIST_DCACHE_FILL_ONPATH_count, 252, 15026 | |
| DIST_DCACHE_FILL_ONPATH_total_count, 252, 15026 | |
| DIST_L1_FILL_OFFPATH_USED_count, 253, 0 | |
| DIST_L1_FILL_OFFPATH_USED_total_count, 253, 0 | |
| DIST_L1_FILL_OFFPATH_NOTUSED_count, 253, 0 | |
| DIST_L1_FILL_OFFPATH_NOTUSED_total_count, 253, 0 | |
| DIST_L1_FILL_ONPATH_PARTIAL_count, 253, 1 | |
| DIST_L1_FILL_ONPATH_PARTIAL_total_count, 253, 1 | |
| DIST_L1_FILL_ONPATH_count, 253, 511 | |
| DIST_L1_FILL_ONPATH_total_count, 253, 511 | |
| DIST_JUST_L1_FILL_OFFPATH_USED_count, 254, 0 | |
| DIST_JUST_L1_FILL_OFFPATH_USED_total_count, 254, 0 | |
| DIST_JUST_L1_FILL_OFFPATH_NOTUSED_count, 254, 0 | |
| DIST_JUST_L1_FILL_OFFPATH_NOTUSED_total_count, 254, 0 | |
| DIST_JUST_L1_FILL_ONPATH_PARTIAL_count, 254, 0 | |
| DIST_JUST_L1_FILL_ONPATH_PARTIAL_total_count, 254, 0 | |
| DIST_JUST_L1_FILL_ONPATH_count, 254, 0 | |
| DIST_JUST_L1_FILL_ONPATH_total_count, 254, 0 | |
| DIST_REQBUF_OFFPATH_USED_count, 255, 1 | |
| DIST_REQBUF_OFFPATH_USED_total_count, 255, 1 | |
| DIST_REQBUF_OFFPATH_NOTUSED_count, 255, 0 | |
| DIST_REQBUF_OFFPATH_NOTUSED_total_count, 255, 0 | |
| DIST_REQBUF_ONPATH_count, 255, 29568 | |
| DIST_REQBUF_ONPATH_total_count, 255, 29568 | |
| DIST2_REQBUF_OFFPATH_USED_PARTIAL_count, 256, 1 | |
| DIST2_REQBUF_OFFPATH_USED_PARTIAL_total_count, 256, 1 | |
| DIST2_REQBUF_OFFPATH_USED_FULL_count, 256, 0 | |
| DIST2_REQBUF_OFFPATH_USED_FULL_total_count, 256, 0 | |
| DIST2_REQBUF_OFFPATH_NOTUSED_count, 256, 0 | |
| DIST2_REQBUF_OFFPATH_NOTUSED_total_count, 256, 0 | |
| DIST2_REQBUF_ONPATH_count, 256, 29568 | |
| DIST2_REQBUF_ONPATH_total_count, 256, 29568 | |
| DIST_ICACHE_FILL_count, 0, 103 | |
| DIST_ICACHE_FILL_total_count, 0, 103 | |
| DIST_DCACHE_FILL_count, 0, 15026 | |
| DIST_DCACHE_FILL_total_count, 0, 15026 | |
| DIST_L1_FILL_count, 0, 608 | |
| DIST_L1_FILL_total_count, 0, 608 | |
| DIST_USED_OFFPATH_ICACHE_count, 257, 0 | |
| DIST_USED_OFFPATH_ICACHE_total_count, 257, 0 | |
| DIST_NOTUSED_OFFPATH_ICACHE_count, 257, 0 | |
| DIST_NOTUSED_OFFPATH_ICACHE_total_count, 257, 0 | |
| DIST_USED_OFFPATH_DCACHE_count, 258, 0 | |
| DIST_USED_OFFPATH_DCACHE_total_count, 258, 0 | |
| DIST_NOTUSED_OFFPATH_DCACHE_count, 258, 0 | |
| DIST_NOTUSED_OFFPATH_DCACHE_total_count, 258, 0 | |
| DIST_USED_OFFPATH_L1_count, 259, 0 | |
| DIST_USED_OFFPATH_L1_total_count, 259, 0 | |
| DIST_NOTUSED_OFFPATH_L1_count, 259, 0 | |
| DIST_NOTUSED_OFFPATH_L1_total_count, 259, 0 | |
| DIST_USED_OFFPATH_JUST_L1_count, 260, 0 | |
| DIST_USED_OFFPATH_JUST_L1_total_count, 260, 0 | |
| DIST_NOTUSED_OFFPATH_JUST_L1_count, 260, 0 | |
| DIST_NOTUSED_OFFPATH_JUST_L1_total_count, 260, 0 | |
| DIST_OFFPATH_ICACHE_FULL_count, 261, 0 | |
| DIST_OFFPATH_ICACHE_FULL_total_count, 261, 0 | |
| DIST_OFFPATH_ICACHE_PARTIAL_count, 261, 0 | |
| DIST_OFFPATH_ICACHE_PARTIAL_total_count, 261, 0 | |
| DIST_OFFPATH_ICACHE_NOTUSED_count, 261, 0 | |
| DIST_OFFPATH_ICACHE_NOTUSED_total_count, 261, 0 | |
| DIST_OFFPATH_DCACHE_FULL_count, 262, 0 | |
| DIST_OFFPATH_DCACHE_FULL_total_count, 262, 0 | |
| DIST_OFFPATH_DCACHE_PARTIAL_count, 262, 0 | |
| DIST_OFFPATH_DCACHE_PARTIAL_total_count, 262, 0 | |
| DIST_OFFPATH_DCACHE_NOTUSED_count, 262, 0 | |
| DIST_OFFPATH_DCACHE_NOTUSED_total_count, 262, 0 | |
| DIST_OFFPATH_L1_FULL_count, 263, 0 | |
| DIST_OFFPATH_L1_FULL_total_count, 263, 0 | |
| DIST_OFFPATH_L1_PARTIAL_count, 263, 0 | |
| DIST_OFFPATH_L1_PARTIAL_total_count, 263, 0 | |
| DIST_OFFPATH_L1_NOTUSED_count, 263, 0 | |
| DIST_OFFPATH_L1_NOTUSED_total_count, 263, 0 | |
| DIST_OFFPATH_JUST_L1_FULL_count, 264, 0 | |
| DIST_OFFPATH_JUST_L1_FULL_total_count, 264, 0 | |
| DIST_OFFPATH_JUST_L1_PARTIAL_count, 264, 0 | |
| DIST_OFFPATH_JUST_L1_PARTIAL_total_count, 264, 0 | |
| DIST_OFFPATH_JUST_L1_NOTUSED_count, 264, 0 | |
| DIST_OFFPATH_JUST_L1_NOTUSED_total_count, 264, 0 | |
| MLC_MISS_ONPATH_IFETCH_count, 265, 5 | |
| MLC_MISS_ONPATH_IFETCH_total_count, 265, 5 | |
| MLC_MISS_ONPATH_DFETCH_count, 265, 14533 | |
| MLC_MISS_ONPATH_DFETCH_total_count, 265, 14533 | |
| MLC_MISS_ONPATH_DSTORE_count, 265, 2 | |
| MLC_MISS_ONPATH_DSTORE_total_count, 265, 2 | |
| MLC_MISS_ONPATH_IPRF_count, 265, 0 | |
| MLC_MISS_ONPATH_IPRF_total_count, 265, 0 | |
| MLC_MISS_ONPATH_DPRF_count, 265, 0 | |
| MLC_MISS_ONPATH_DPRF_total_count, 265, 0 | |
| MLC_MISS_ONPATH_WB_count, 265, 1 | |
| MLC_MISS_ONPATH_WB_total_count, 265, 1 | |
| MLC_MISS_ONPATH_WB_NODIRTY_count, 265, 0 | |
| MLC_MISS_ONPATH_WB_NODIRTY_total_count, 265, 0 | |
| MLC_MISS_OFFPATH_IFETCH_count, 266, 1 | |
| MLC_MISS_OFFPATH_IFETCH_total_count, 266, 1 | |
| MLC_MISS_OFFPATH_DFETCH_count, 266, 0 | |
| MLC_MISS_OFFPATH_DFETCH_total_count, 266, 0 | |
| MLC_MISS_OFFPATH_DSTORE_count, 266, 0 | |
| MLC_MISS_OFFPATH_DSTORE_total_count, 266, 0 | |
| MLC_MISS_OFFPATH_IPRF_count, 266, 0 | |
| MLC_MISS_OFFPATH_IPRF_total_count, 266, 0 | |
| MLC_MISS_OFFPATH_DPRF_count, 266, 0 | |
| MLC_MISS_OFFPATH_DPRF_total_count, 266, 0 | |
| MLC_MISS_OFFPATH_WB_count, 266, 96 | |
| MLC_MISS_OFFPATH_WB_total_count, 266, 96 | |
| MLC_MISS_OFFPATH_WB_NODIRTY_count, 266, 0 | |
| MLC_MISS_OFFPATH_WB_NODIRTY_total_count, 266, 0 | |
| MLC_HIT_ONPATH_IFETCH_count, 267, 0 | |
| MLC_HIT_ONPATH_IFETCH_total_count, 267, 0 | |
| MLC_HIT_ONPATH_DFETCH_count, 267, 0 | |
| MLC_HIT_ONPATH_DFETCH_total_count, 267, 0 | |
| MLC_HIT_ONPATH_DSTORE_count, 267, 0 | |
| MLC_HIT_ONPATH_DSTORE_total_count, 267, 0 | |
| MLC_HIT_ONPATH_IPRF_count, 267, 0 | |
| MLC_HIT_ONPATH_IPRF_total_count, 267, 0 | |
| MLC_HIT_ONPATH_DPRF_count, 267, 0 | |
| MLC_HIT_ONPATH_DPRF_total_count, 267, 0 | |
| MLC_HIT_ONPATH_WB_count, 267, 0 | |
| MLC_HIT_ONPATH_WB_total_count, 267, 0 | |
| MLC_HIT_ONPATH_WB_NODIRTY_count, 267, 14513 | |
| MLC_HIT_ONPATH_WB_NODIRTY_total_count, 267, 14513 | |
| MLC_HIT_OFFPATH_IFETCH_count, 268, 0 | |
| MLC_HIT_OFFPATH_IFETCH_total_count, 268, 0 | |
| MLC_HIT_OFFPATH_DFETCH_count, 268, 0 | |
| MLC_HIT_OFFPATH_DFETCH_total_count, 268, 0 | |
| MLC_HIT_OFFPATH_DSTORE_count, 268, 0 | |
| MLC_HIT_OFFPATH_DSTORE_total_count, 268, 0 | |
| MLC_HIT_OFFPATH_IPRF_count, 268, 0 | |
| MLC_HIT_OFFPATH_IPRF_total_count, 268, 0 | |
| MLC_HIT_OFFPATH_DPRF_count, 268, 0 | |
| MLC_HIT_OFFPATH_DPRF_total_count, 268, 0 | |
| MLC_HIT_OFFPATH_WB_count, 268, 0 | |
| MLC_HIT_OFFPATH_WB_total_count, 268, 0 | |
| MLC_HIT_OFFPATH_WB_NODIRTY_count, 268, 0 | |
| MLC_HIT_OFFPATH_WB_NODIRTY_total_count, 268, 0 | |
| L1_MISS_ONPATH_IFETCH_count, 269, 6 | |
| L1_MISS_ONPATH_IFETCH_total_count, 269, 6 | |
| L1_MISS_ONPATH_DFETCH_count, 269, 13 | |
| L1_MISS_ONPATH_DFETCH_total_count, 269, 13 | |
| L1_MISS_ONPATH_DSTORE_count, 269, 2 | |
| L1_MISS_ONPATH_DSTORE_total_count, 269, 2 | |
| L1_MISS_ONPATH_IPRF_count, 269, 0 | |
| L1_MISS_ONPATH_IPRF_total_count, 269, 0 | |
| L1_MISS_ONPATH_DPRF_count, 269, 0 | |
| L1_MISS_ONPATH_DPRF_total_count, 269, 0 | |
| L1_MISS_ONPATH_WB_count, 269, 1 | |
| L1_MISS_ONPATH_WB_total_count, 269, 1 | |
| L1_MISS_ONPATH_WB_NODIRTY_count, 269, 15025 | |
| L1_MISS_ONPATH_WB_NODIRTY_total_count, 269, 15025 | |
| L1_MISS_OFFPATH_IFETCH_count, 270, 0 | |
| L1_MISS_OFFPATH_IFETCH_total_count, 270, 0 | |
| L1_MISS_OFFPATH_DFETCH_count, 270, 0 | |
| L1_MISS_OFFPATH_DFETCH_total_count, 270, 0 | |
| L1_MISS_OFFPATH_DSTORE_count, 270, 0 | |
| L1_MISS_OFFPATH_DSTORE_total_count, 270, 0 | |
| L1_MISS_OFFPATH_IPRF_count, 270, 0 | |
| L1_MISS_OFFPATH_IPRF_total_count, 270, 0 | |
| L1_MISS_OFFPATH_DPRF_count, 270, 0 | |
| L1_MISS_OFFPATH_DPRF_total_count, 270, 0 | |
| L1_MISS_OFFPATH_WB_count, 270, 96 | |
| L1_MISS_OFFPATH_WB_total_count, 270, 96 | |
| L1_MISS_OFFPATH_WB_NODIRTY_count, 270, 0 | |
| L1_MISS_OFFPATH_WB_NODIRTY_total_count, 270, 0 | |
| L1_HIT_ONPATH_IFETCH_count, 271, 0 | |
| L1_HIT_ONPATH_IFETCH_total_count, 271, 0 | |
| L1_HIT_ONPATH_DFETCH_count, 271, 14521 | |
| L1_HIT_ONPATH_DFETCH_total_count, 271, 14521 | |
| L1_HIT_ONPATH_DSTORE_count, 271, 0 | |
| L1_HIT_ONPATH_DSTORE_total_count, 271, 0 | |
| L1_HIT_ONPATH_IPRF_count, 271, 0 | |
| L1_HIT_ONPATH_IPRF_total_count, 271, 0 | |
| L1_HIT_ONPATH_DPRF_count, 271, 0 | |
| L1_HIT_ONPATH_DPRF_total_count, 271, 0 | |
| L1_HIT_ONPATH_WB_count, 271, 0 | |
| L1_HIT_ONPATH_WB_total_count, 271, 0 | |
| L1_HIT_ONPATH_WB_NODIRTY_count, 271, 681 | |
| L1_HIT_ONPATH_WB_NODIRTY_total_count, 271, 681 | |
| L1_HIT_OFFPATH_IFETCH_count, 272, 0 | |
| L1_HIT_OFFPATH_IFETCH_total_count, 272, 0 | |
| L1_HIT_OFFPATH_DFETCH_count, 272, 0 | |
| L1_HIT_OFFPATH_DFETCH_total_count, 272, 0 | |
| L1_HIT_OFFPATH_DSTORE_count, 272, 0 | |
| L1_HIT_OFFPATH_DSTORE_total_count, 272, 0 | |
| L1_HIT_OFFPATH_IPRF_count, 272, 0 | |
| L1_HIT_OFFPATH_IPRF_total_count, 272, 0 | |
| L1_HIT_OFFPATH_DPRF_count, 272, 0 | |
| L1_HIT_OFFPATH_DPRF_total_count, 272, 0 | |
| L1_HIT_OFFPATH_WB_count, 272, 0 | |
| L1_HIT_OFFPATH_WB_total_count, 272, 0 | |
| L1_HIT_OFFPATH_WB_NODIRTY_count, 272, 0 | |
| L1_HIT_OFFPATH_WB_NODIRTY_total_count, 272, 0 | |
| DRAM_CYCLES_count, 0, 0 | |
| DRAM_CYCLES_total_count, 0, 0 | |
| DRAM_UNBLOCK_CYCLES_count, 0, 0 | |
| DRAM_UNBLOCK_CYCLES_pct, 0, -nan | |
| DRAM_UNBLOCK_CYCLES_total_count, 0, 0 | |
| DRAM_UNBLOCK_CYCLES_total_pct, 0, -nan | |
| DRAM_UNBLOCK_PERIODS_count, 0, 0 | |
| DRAM_UNBLOCK_PERIODS_total_count, 0, 0 | |
| MEM_REQ_BUFFER_FULL_count, 0, 5 | |
| MEM_REQ_BUFFER_FULL_total_count, 0, 5 | |
| MEM_REQ_BUFFER_FULL_DENIED_DEMAND_count, 0, 1 | |
| MEM_REQ_BUFFER_FULL_DENIED_DEMAND_total_count, 0, 1 | |
| CORE_MEM_BLOCKED_count, 0, 11 | |
| CORE_MEM_BLOCKED_total_count, 0, 11 | |
| MEM_REQ_BUFFER_FULL_DENIED_IFETCH_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_IFETCH_total_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_DFETCH_count, 273, 1 | |
| MEM_REQ_BUFFER_FULL_DENIED_DFETCH_total_count, 273, 1 | |
| MEM_REQ_BUFFER_FULL_DENIED_DSTORE_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_DSTORE_total_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_IPRF_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_IPRF_total_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_DPRF_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_DPRF_total_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_WB_count, 273, 4 | |
| MEM_REQ_BUFFER_FULL_DENIED_WB_total_count, 273, 4 | |
| MEM_REQ_BUFFER_FULL_DENIED_WB_NODIRTY_count, 273, 0 | |
| MEM_REQ_BUFFER_FULL_DENIED_WB_NODIRTY_total_count, 273, 0 | |
| MEM_QUEUE_FULL_count, 0, 0 | |
| MEM_QUEUE_FULL_total_count, 0, 0 | |
| MEM_REQ_BUFFER_MISS_count, 274, 44861 | |
| MEM_REQ_BUFFER_MISS_total_count, 274, 44861 | |
| MEM_REQ_BUFFER_HIT_count, 274, 15598 | |
| MEM_REQ_BUFFER_HIT_total_count, 274, 15598 | |
| MEM_REQ_FDIP_BUFFER_HIT_count, 0, 59 | |
| MEM_REQ_FDIP_BUFFER_HIT_total_count, 0, 59 | |
| MEM_REQ_FDIP_CYCLE_DELTA_count, 0, 9049 | |
| MEM_REQ_FDIP_CYCLE_DELTA_total_count, 0, 9049 | |
| MEM_REQ_DEMAND_ICACHE_BUFFER_HIT_count, 0, 13 | |
| MEM_REQ_DEMAND_ICACHE_BUFFER_HIT_total_count, 0, 13 | |
| MEM_REQ_DEMAND_ICACHE_CYCLE_DELTA_count, 0, 222 | |
| MEM_REQ_DEMAND_ICACHE_CYCLE_DELTA_total_count, 0, 222 | |
| MEM_REQ_IFETCH_count, 275, 3 | |
| MEM_REQ_IFETCH_total_count, 275, 3 | |
| MEM_REQ_DFETCH_count, 275, 14533 | |
| MEM_REQ_DFETCH_total_count, 275, 14533 | |
| MEM_REQ_DSTORE_count, 275, 2 | |
| MEM_REQ_DSTORE_total_count, 275, 2 | |
| MEM_REQ_IPRF_count, 275, 0 | |
| MEM_REQ_IPRF_total_count, 275, 0 | |
| MEM_REQ_DPRF_count, 275, 0 | |
| MEM_REQ_DPRF_total_count, 275, 0 | |
| MEM_REQ_WB_count, 275, 100 | |
| MEM_REQ_WB_total_count, 275, 100 | |
| MEM_REQ_WB_NODIRTY_count, 275, 30223 | |
| MEM_REQ_WB_NODIRTY_total_count, 275, 30223 | |
| LD_NO_FORWARD_count, 276, 120197 | |
| LD_NO_FORWARD_total_count, 276, 120197 | |
| FORWARDED_LD_count, 276, 120188 | |
| FORWARDED_LD_total_count, 276, 120188 | |
| WRONGPATH_L1Q_REMOVALS_count, 277, 0 | |
| WRONGPATH_L1Q_REMOVALS_total_count, 277, 0 | |
| WRONGPATH_BUSQ_REMOVALS_count, 277, 0 | |
| WRONGPATH_BUSQ_REMOVALS_total_count, 277, 0 | |
| WRONGPATH_MEMQ_REMOVALS_count, 277, 0 | |
| WRONGPATH_MEMQ_REMOVALS_total_count, 277, 0 | |
| WRONGPATH_L1FILLQ_REMOVALS_count, 277, 0 | |
| WRONGPATH_L1FILLQ_REMOVALS_total_count, 277, 0 | |
| WRONGPATH_L1Q_DEMOTIONS_count, 278, 0 | |
| WRONGPATH_L1Q_DEMOTIONS_total_count, 278, 0 | |
| WRONGPATH_BUSQ_DEMOTIONS_count, 278, 0 | |
| WRONGPATH_BUSQ_DEMOTIONS_total_count, 278, 0 | |
| WRONGPATH_MEMQ_DEMOTIONS_count, 278, 0 | |
| WRONGPATH_MEMQ_DEMOTIONS_total_count, 278, 0 | |
| WRONGPATH_L1FILLQ_DEMOTIONS_count, 278, 0 | |
| WRONGPATH_L1FILLQ_DEMOTIONS_total_count, 278, 0 | |
| PROMOTION_QMLC_count, 279, 3 | |
| PROMOTION_QMLC_total_count, 279, 3 | |
| PROMOTION_QL1_count, 279, 1 | |
| PROMOTION_QL1_total_count, 279, 1 | |
| PROMOTION_QBUSOUT_count, 0, 0 | |
| PROMOTION_QBUSOUT_total_count, 0, 0 | |
| PROMOTION_QMEM_count, 0, 0 | |
| PROMOTION_QMEM_total_count, 0, 0 | |
| PROMOTION_QL1FILL_count, 0, 0 | |
| PROMOTION_QL1FILL_total_count, 0, 0 | |
| PROMOTION_QMLC_FILL_count, 0, 0 | |
| PROMOTION_QMLC_FILL_total_count, 0, 0 | |
| NOPROMOTION_QMEM_count, 0, 0 | |
| NOPROMOTION_QMEM_total_count, 0, 0 | |
| NOPROMOTION_QL1FILL_count, 280, 0 | |
| NOPROMOTION_QL1FILL_total_count, 280, 0 | |
| NOPROMOTION_QMLC_FILL_count, 280, 0 | |
| NOPROMOTION_QMLC_FILL_total_count, 280, 0 | |
| PROMOTION_FROM_FDIP_OFF_TO_ON_count, 0, 0 | |
| PROMOTION_FROM_FDIP_OFF_TO_ON_total_count, 0, 0 | |
| ICACHE_FILL_CORRECT_REQ_count, 281, 31 | |
| ICACHE_FILL_CORRECT_REQ_total_count, 281, 31 | |
| ICACHE_FILL_INCORRECT_REQ_count, 281, 72 | |
| ICACHE_FILL_INCORRECT_REQ_total_count, 281, 72 | |
| ICACHE_FILL_CORRECT_REQ_BY_FDIP_count, 282, 28 | |
| ICACHE_FILL_CORRECT_REQ_BY_FDIP_total_count, 282, 28 | |
| ICACHE_FILL_INCORRECT_REQ_BY_FDIP_count, 282, 72 | |
| ICACHE_FILL_INCORRECT_REQ_BY_FDIP_total_count, 282, 72 | |
| ICACHE_FILL_CORRECT_REQ_BY_ICACHE_DEMAND_count, 282, 3 | |
| ICACHE_FILL_CORRECT_REQ_BY_ICACHE_DEMAND_total_count, 282, 3 | |
| ICACHE_FILL_INCORRECT_REQ_BY_ICACHE_DEMAND_count, 282, 0 | |
| ICACHE_FILL_INCORRECT_REQ_BY_ICACHE_DEMAND_total_count, 282, 0 | |
| ICACHE_FILL_CORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 1 | |
| ICACHE_FILL_CORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 1 | |
| ICACHE_FILL_CORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 0 | |
| ICACHE_FILL_CORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 3 | |
| ICACHE_FILL_INCORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 3 | |
| ICACHE_FILL_INCORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 0 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_count, 0, 19673 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_total_count, 0, 19673 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND_count, 0, 845 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND_total_count, 0, 845 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_FDIP_count, 0, 8003 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_FDIP_total_count, 0, 8003 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 153 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 153 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 0 | |
| ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_count, 0, 67613 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_total_count, 0, 67613 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND_total_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_FDIP_count, 0, 27109 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_FDIP_total_count, 0, 27109 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_count, 0, 0 | |
| ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD_total_count, 0, 0 | |
| MEM_REQ_INIT_count, 0, 44861 | |
| MEM_REQ_INIT_total_count, 0, 44861 | |
| MEM_REQ_COMPLETE_count, 0, 44855 | |
| MEM_REQ_COMPLETE_pct, 0, 1.000 | |
| MEM_REQ_COMPLETE_total_count, 0, 44855 | |
| MEM_REQ_COMPLETE_total_pct, 0, 1.000 | |
| MEM_REQ_KILLED_count, 0, 0 | |
| MEM_REQ_KILLED_pct, 0, 0.000 | |
| MEM_REQ_KILLED_total_count, 0, 0 | |
| MEM_REQ_KILLED_total_pct, 0, 0.000 | |
| MEM_REQ_COMPLETE_MLC_count, 0, 14513 | |
| MEM_REQ_COMPLETE_MLC_pct, 0, 0.324 | |
| MEM_REQ_COMPLETE_MLC_total_count, 0, 14513 | |
| MEM_REQ_COMPLETE_MLC_total_pct, 0, 0.324 | |
| MEM_REQ_COMPLETE_L1_count, 0, 681 | |
| MEM_REQ_COMPLETE_L1_pct, 0, 0.015 | |
| MEM_REQ_COMPLETE_L1_total_count, 0, 681 | |
| MEM_REQ_COMPLETE_L1_total_pct, 0, 0.015 | |
| MEM_REQ_COMPLETE_MEM_count, 0, 29661 | |
| MEM_REQ_COMPLETE_MEM_pct, 0, 0.661 | |
| MEM_REQ_COMPLETE_MEM_total_count, 0, 29661 | |
| MEM_REQ_COMPLETE_MEM_total_pct, 0, 0.661 | |
| MEM_REQ_INIT_ONPATH_count, 0, 44764 | |
| MEM_REQ_INIT_ONPATH_pct, 0, 0.998 | |
| MEM_REQ_INIT_ONPATH_total_count, 0, 44764 | |
| MEM_REQ_INIT_ONPATH_total_pct, 0, 0.998 | |
| MEM_REQ_INIT_OFFPATH_count, 0, 97 | |
| MEM_REQ_INIT_OFFPATH_pct, 0, 0.002 | |
| MEM_REQ_INIT_OFFPATH_total_count, 0, 97 | |
| MEM_REQ_INIT_OFFPATH_total_pct, 0, 0.002 | |
| MEM_REQ_COMPLETE_ONPATH_count, 0, 44759 | |
| MEM_REQ_COMPLETE_ONPATH_pct, 0, 0.998 | |
| MEM_REQ_COMPLETE_ONPATH_total_count, 0, 44759 | |
| MEM_REQ_COMPLETE_ONPATH_total_pct, 0, 0.998 | |
| MEM_REQ_COMPLETE_OFFPATH_count, 0, 96 | |
| MEM_REQ_COMPLETE_OFFPATH_pct, 0, 0.002 | |
| MEM_REQ_COMPLETE_OFFPATH_total_count, 0, 96 | |
| MEM_REQ_COMPLETE_OFFPATH_total_pct, 0, 0.002 | |
| MEM_REQ_INIT_IFETCH_count, 283, 3 | |
| MEM_REQ_INIT_IFETCH_total_count, 283, 3 | |
| MEM_REQ_INIT_DFETCH_count, 283, 14533 | |
| MEM_REQ_INIT_DFETCH_total_count, 283, 14533 | |
| MEM_REQ_INIT_DSTORE_count, 283, 2 | |
| MEM_REQ_INIT_DSTORE_total_count, 283, 2 | |
| MEM_REQ_INIT_IPRF_count, 283, 0 | |
| MEM_REQ_INIT_IPRF_total_count, 283, 0 | |
| MEM_REQ_INIT_DPRF_count, 283, 0 | |
| MEM_REQ_INIT_DPRF_total_count, 283, 0 | |
| MEM_REQ_INIT_WB_count, 283, 100 | |
| MEM_REQ_INIT_WB_total_count, 283, 100 | |
| MEM_REQ_INIT_WB_NODIRTY_count, 283, 0 | |
| MEM_REQ_INIT_WB_NODIRTY_total_count, 283, 0 | |
| MEM_REQ_COMPLETE_IFETCH_count, 284, 15033 | |
| MEM_REQ_COMPLETE_IFETCH_total_count, 284, 15033 | |
| MEM_REQ_COMPLETE_DFETCH_count, 284, 30220 | |
| MEM_REQ_COMPLETE_DFETCH_total_count, 284, 30220 | |
| MEM_REQ_COMPLETE_DSTORE_count, 284, 2 | |
| MEM_REQ_COMPLETE_DSTORE_total_count, 284, 2 | |
| MEM_REQ_COMPLETE_IPRF_count, 284, 0 | |
| MEM_REQ_COMPLETE_IPRF_total_count, 284, 0 | |
| MEM_REQ_COMPLETE_DPRF_count, 284, 0 | |
| MEM_REQ_COMPLETE_DPRF_total_count, 284, 0 | |
| MEM_REQ_COMPLETE_WB_count, 284, 97 | |
| MEM_REQ_COMPLETE_WB_total_count, 284, 97 | |
| MEM_REQ_COMPLETE_WB_NODIRTY_count, 284, 0 | |
| MEM_REQ_COMPLETE_WB_NODIRTY_total_count, 284, 0 | |
| MEM_REQ_KILLED_IFETCH_count, 285, 29726 | |
| MEM_REQ_KILLED_IFETCH_total_count, 285, 29726 | |
| MEM_REQ_KILLED_DFETCH_count, 285, 0 | |
| MEM_REQ_KILLED_DFETCH_total_count, 285, 0 | |
| MEM_REQ_KILLED_DSTORE_count, 285, 0 | |
| MEM_REQ_KILLED_DSTORE_total_count, 285, 0 | |
| MEM_REQ_KILLED_IPRF_count, 285, 0 | |
| MEM_REQ_KILLED_IPRF_total_count, 285, 0 | |
| MEM_REQ_KILLED_DPRF_count, 285, 0 | |
| MEM_REQ_KILLED_DPRF_total_count, 285, 0 | |
| MEM_REQ_KILLED_WB_count, 285, 0 | |
| MEM_REQ_KILLED_WB_total_count, 285, 0 | |
| MEM_REQ_KILLED_WB_NODIRTY_count, 285, 0 | |
| MEM_REQ_KILLED_WB_NODIRTY_total_count, 285, 0 | |
| MEM_REQ_INIT_OFFPATH_IFETCH_count, 286, 1 | |
| MEM_REQ_INIT_OFFPATH_IFETCH_total_count, 286, 1 | |
| MEM_REQ_INIT_OFFPATH_DFETCH_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_DFETCH_total_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_DSTORE_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_DSTORE_total_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_IPRF_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_IPRF_total_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_DPRF_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_DPRF_total_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_WB_count, 286, 96 | |
| MEM_REQ_INIT_OFFPATH_WB_total_count, 286, 96 | |
| MEM_REQ_INIT_OFFPATH_WB_NODIRTY_count, 286, 0 | |
| MEM_REQ_INIT_OFFPATH_WB_NODIRTY_total_count, 286, 0 | |
| MEM_REQ_INIT_ONPATH_IFETCH_count, 287, 2 | |
| MEM_REQ_INIT_ONPATH_IFETCH_total_count, 287, 2 | |
| MEM_REQ_INIT_ONPATH_DFETCH_count, 287, 14533 | |
| MEM_REQ_INIT_ONPATH_DFETCH_total_count, 287, 14533 | |
| MEM_REQ_INIT_ONPATH_DSTORE_count, 287, 2 | |
| MEM_REQ_INIT_ONPATH_DSTORE_total_count, 287, 2 | |
| MEM_REQ_INIT_ONPATH_IPRF_count, 287, 0 | |
| MEM_REQ_INIT_ONPATH_IPRF_total_count, 287, 0 | |
| MEM_REQ_INIT_ONPATH_DPRF_count, 287, 0 | |
| MEM_REQ_INIT_ONPATH_DPRF_total_count, 287, 0 | |
| MEM_REQ_INIT_ONPATH_WB_count, 287, 4 | |
| MEM_REQ_INIT_ONPATH_WB_total_count, 287, 4 | |
| MEM_REQ_INIT_ONPATH_WB_NODIRTY_count, 287, 0 | |
| MEM_REQ_INIT_ONPATH_WB_NODIRTY_total_count, 287, 0 | |
| MEM_REQ_MATCH_IFETCH_count, 288, 15071 | |
| MEM_REQ_MATCH_IFETCH_total_count, 288, 15071 | |
| MEM_REQ_MATCH_DFETCH_count, 288, 29728 | |
| MEM_REQ_MATCH_DFETCH_total_count, 288, 29728 | |
| MEM_REQ_MATCH_DSTORE_count, 288, 5 | |
| MEM_REQ_MATCH_DSTORE_total_count, 288, 5 | |
| MEM_REQ_MATCH_IPRF_count, 288, 0 | |
| MEM_REQ_MATCH_IPRF_total_count, 288, 0 | |
| MEM_REQ_MATCH_DPRF_count, 288, 0 | |
| MEM_REQ_MATCH_DPRF_total_count, 288, 0 | |
| MEM_REQ_MATCH_WB_count, 288, 32 | |
| MEM_REQ_MATCH_WB_total_count, 288, 32 | |
| MEM_REQ_MATCH_WB_NODIRTY_count, 288, 1 | |
| MEM_REQ_MATCH_WB_NODIRTY_total_count, 288, 1 | |
| MEM_REQ_COMPLETE_OFFPATH_IFETCH_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_IFETCH_total_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_DFETCH_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_DFETCH_total_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_DSTORE_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_DSTORE_total_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_IPRF_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_IPRF_total_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_DPRF_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_DPRF_total_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_WB_count, 289, 96 | |
| MEM_REQ_COMPLETE_OFFPATH_WB_total_count, 289, 96 | |
| MEM_REQ_COMPLETE_OFFPATH_WB_NODIRTY_count, 289, 0 | |
| MEM_REQ_COMPLETE_OFFPATH_WB_NODIRTY_total_count, 289, 0 | |
| MEM_REQ_COMPLETE_ONPATH_IFETCH_count, 290, 6 | |
| MEM_REQ_COMPLETE_ONPATH_IFETCH_total_count, 290, 6 | |
| MEM_REQ_COMPLETE_ONPATH_DFETCH_count, 290, 15024 | |
| MEM_REQ_COMPLETE_ONPATH_DFETCH_total_count, 290, 15024 | |
| MEM_REQ_COMPLETE_ONPATH_DSTORE_count, 290, 2 | |
| MEM_REQ_COMPLETE_ONPATH_DSTORE_total_count, 290, 2 | |
| MEM_REQ_COMPLETE_ONPATH_IPRF_count, 290, 0 | |
| MEM_REQ_COMPLETE_ONPATH_IPRF_total_count, 290, 0 | |
| MEM_REQ_COMPLETE_ONPATH_DPRF_count, 290, 0 | |
| MEM_REQ_COMPLETE_ONPATH_DPRF_total_count, 290, 0 | |
| MEM_REQ_COMPLETE_ONPATH_WB_count, 290, 1 | |
| MEM_REQ_COMPLETE_ONPATH_WB_total_count, 290, 1 | |
| MEM_REQ_COMPLETE_ONPATH_WB_NODIRTY_count, 290, 0 | |
| MEM_REQ_COMPLETE_ONPATH_WB_NODIRTY_total_count, 290, 0 | |
| MEM_REQ_COMPLETE_MEM_IFETCH_count, 291, 29732 | |
| MEM_REQ_COMPLETE_MEM_IFETCH_total_count, 291, 29732 | |
| MEM_REQ_COMPLETE_MEM_DFETCH_count, 291, 15024 | |
| MEM_REQ_COMPLETE_MEM_DFETCH_total_count, 291, 15024 | |
| MEM_REQ_COMPLETE_MEM_DSTORE_count, 291, 2 | |
| MEM_REQ_COMPLETE_MEM_DSTORE_total_count, 291, 2 | |
| MEM_REQ_COMPLETE_MEM_IPRF_count, 291, 0 | |
| MEM_REQ_COMPLETE_MEM_IPRF_total_count, 291, 0 | |
| MEM_REQ_COMPLETE_MEM_DPRF_count, 291, 0 | |
| MEM_REQ_COMPLETE_MEM_DPRF_total_count, 291, 0 | |
| MEM_REQ_COMPLETE_MEM_WB_count, 291, 97 | |
| MEM_REQ_COMPLETE_MEM_WB_total_count, 291, 97 | |
| MEM_REQ_COMPLETE_MEM_WB_NODIRTY_count, 291, 0 | |
| MEM_REQ_COMPLETE_MEM_WB_NODIRTY_total_count, 291, 0 | |
| MEM_REQ_COMPLETE_MEM_BW_PREFETCHABLE_count, 0, 29053 | |
| MEM_REQ_COMPLETE_MEM_BW_PREFETCHABLE_total_count, 0, 29053 | |
| MEM_REQ_COMPLETE_MEM_MATCHED_BW_PREF_count, 0, 479 | |
| MEM_REQ_COMPLETE_MEM_MATCHED_BW_PREF_total_count, 0, 479 | |
| MEM_REQ_COMPLETE_L1_IFETCH_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_IFETCH_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_DFETCH_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_DFETCH_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_DSTORE_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_DSTORE_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_IPRF_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_IPRF_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_DPRF_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_DPRF_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_WB_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_WB_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_WB_NODIRTY_count, 292, 0 | |
| MEM_REQ_COMPLETE_L1_WB_NODIRTY_total_count, 292, 0 | |
| MEM_REQ_COMPLETE_MLC_IFETCH_count, 293, 681 | |
| MEM_REQ_COMPLETE_MLC_IFETCH_total_count, 293, 681 | |
| MEM_REQ_COMPLETE_MLC_DFETCH_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_DFETCH_total_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_DSTORE_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_DSTORE_total_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_IPRF_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_IPRF_total_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_DPRF_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_DPRF_total_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_WB_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_WB_total_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_WB_NODIRTY_count, 293, 0 | |
| MEM_REQ_COMPLETE_MLC_WB_NODIRTY_total_count, 293, 0 | |
| CORE_MLP_CLUSTERS_count, 0, 14513 | |
| CORE_MLP_CLUSTERS_total_count, 0, 14513 | |
| CORE_MLP_count, 0, 1365238 | |
| CORE_MLP_total_count, 0, 1365238 | |
| CORE_MLP_IFETCH_count, 0, 0 | |
| CORE_MLP_IFETCH_total_count, 0, 0 | |
| CORE_MLP_DFETCH_count, 0, 0 | |
| CORE_MLP_DFETCH_total_count, 0, 0 | |
| CORE_MLP_DSTORE_count, 0, 0 | |
| CORE_MLP_DSTORE_total_count, 0, 0 | |
| CORE_MLP_IPRF_count, 0, 0 | |
| CORE_MLP_IPRF_total_count, 0, 0 | |
| CORE_MLP_DPRF_count, 0, 0 | |
| CORE_MLP_DPRF_total_count, 0, 0 | |
| CORE_MLP_WB_count, 0, 0 | |
| CORE_MLP_WB_total_count, 0, 0 | |
| CORE_MLP_WB_NODIRTY_count, 0, 0 | |
| CORE_MLP_WB_NODIRTY_total_count, 0, 0 | |
| CORE_MLP_0_count, 294, 403 | |
| CORE_MLP_0_total_count, 294, 403 | |
| CORE_MLP_1_count, 294, 1014 | |
| CORE_MLP_1_total_count, 294, 1014 | |
| CORE_MLP_2_count, 294, 85622 | |
| CORE_MLP_2_total_count, 294, 85622 | |
| CORE_MLP_3_count, 294, 161715 | |
| CORE_MLP_3_total_count, 294, 161715 | |
| CORE_MLP_4_count, 294, 42408 | |
| CORE_MLP_4_total_count, 294, 42408 | |
| CORE_MLP_5_count, 294, 10317 | |
| CORE_MLP_5_total_count, 294, 10317 | |
| CORE_MLP_6_count, 294, 7324 | |
| CORE_MLP_6_total_count, 294, 7324 | |
| CORE_MLP_7_count, 294, 2659 | |
| CORE_MLP_7_total_count, 294, 2659 | |
| CORE_MLP_8_count, 294, 906 | |
| CORE_MLP_8_total_count, 294, 906 | |
| CORE_MLP_9_count, 294, 643 | |
| CORE_MLP_9_total_count, 294, 643 | |
| CORE_MLP_10_count, 294, 592 | |
| CORE_MLP_10_total_count, 294, 592 | |
| CORE_MLP_11_count, 294, 725 | |
| CORE_MLP_11_total_count, 294, 725 | |
| CORE_MLP_12_count, 294, 710 | |
| CORE_MLP_12_total_count, 294, 710 | |
| CORE_MLP_13_count, 294, 1052 | |
| CORE_MLP_13_total_count, 294, 1052 | |
| CORE_MLP_14_count, 294, 2598 | |
| CORE_MLP_14_total_count, 294, 2598 | |
| CORE_MLP_15_count, 294, 2345 | |
| CORE_MLP_15_total_count, 294, 2345 | |
| CORE_MLP_16_count, 294, 801 | |
| CORE_MLP_16_total_count, 294, 801 | |
| CORE_MLP_17_count, 294, 212 | |
| CORE_MLP_17_total_count, 294, 212 | |
| CORE_MLP_18_count, 294, 502 | |
| CORE_MLP_18_total_count, 294, 502 | |
| CORE_MLP_19_count, 294, 436 | |
| CORE_MLP_19_total_count, 294, 436 | |
| CORE_MLP_20_count, 294, 12143 | |
| CORE_MLP_20_total_count, 294, 12143 | |
| CORE_MLP_21_count, 294, 17 | |
| CORE_MLP_21_total_count, 294, 17 | |
| CORE_MLP_22_count, 294, 161 | |
| CORE_MLP_22_total_count, 294, 161 | |
| CORE_MLP_23_count, 294, 370 | |
| CORE_MLP_23_total_count, 294, 370 | |
| CORE_MLP_24_count, 294, 380 | |
| CORE_MLP_24_total_count, 294, 380 | |
| CORE_MLP_25_count, 294, 111 | |
| CORE_MLP_25_total_count, 294, 111 | |
| CORE_MLP_26_count, 294, 12 | |
| CORE_MLP_26_total_count, 294, 12 | |
| CORE_MLP_27_count, 294, 12 | |
| CORE_MLP_27_total_count, 294, 12 | |
| CORE_MLP_28_count, 294, 66 | |
| CORE_MLP_28_total_count, 294, 66 | |
| CORE_MLP_29_count, 294, 0 | |
| CORE_MLP_29_total_count, 294, 0 | |
| CORE_MLP_30_count, 294, 0 | |
| CORE_MLP_30_total_count, 294, 0 | |
| CORE_MLP_31_count, 294, 0 | |
| CORE_MLP_31_total_count, 294, 0 | |
| CORE_MLP_32_count, 294, 0 | |
| CORE_MLP_32_total_count, 294, 0 | |
| MEM_QUEUE_OCC_0_count, 295, 0 | |
| MEM_QUEUE_OCC_0_total_count, 295, 0 | |
| MEM_QUEUE_OCC_4_count, 295, 0 | |
| MEM_QUEUE_OCC_4_total_count, 295, 0 | |
| MEM_QUEUE_OCC_8_count, 295, 0 | |
| MEM_QUEUE_OCC_8_total_count, 295, 0 | |
| MEM_QUEUE_OCC_12_count, 295, 0 | |
| MEM_QUEUE_OCC_12_total_count, 295, 0 | |
| MEM_QUEUE_OCC_16_count, 295, 0 | |
| MEM_QUEUE_OCC_16_total_count, 295, 0 | |
| MEM_QUEUE_OCC_20_count, 295, 0 | |
| MEM_QUEUE_OCC_20_total_count, 295, 0 | |
| MEM_QUEUE_OCC_24_count, 295, 0 | |
| MEM_QUEUE_OCC_24_total_count, 295, 0 | |
| MEM_QUEUE_OCC_28_count, 295, 0 | |
| MEM_QUEUE_OCC_28_total_count, 295, 0 | |
| MEM_QUEUE_OCC_32_count, 295, 0 | |
| MEM_QUEUE_OCC_32_total_count, 295, 0 | |
| MEM_QUEUE_OCC_36_count, 295, 0 | |
| MEM_QUEUE_OCC_36_total_count, 295, 0 | |
| MEM_QUEUE_OCC_40_count, 295, 0 | |
| MEM_QUEUE_OCC_40_total_count, 295, 0 | |
| MEM_QUEUE_OCC_44_count, 295, 0 | |
| MEM_QUEUE_OCC_44_total_count, 295, 0 | |
| MEM_QUEUE_OCC_48_count, 295, 0 | |
| MEM_QUEUE_OCC_48_total_count, 295, 0 | |
| MEM_QUEUE_OCC_52_count, 295, 0 | |
| MEM_QUEUE_OCC_52_total_count, 295, 0 | |
| MEM_QUEUE_OCC_56_count, 295, 0 | |
| MEM_QUEUE_OCC_56_total_count, 295, 0 | |
| MEM_QUEUE_OCC_60_count, 295, 0 | |
| MEM_QUEUE_OCC_60_total_count, 295, 0 | |
| MEM_QUEUE_OCC_64_count, 295, 0 | |
| MEM_QUEUE_OCC_64_total_count, 295, 0 | |
| MEM_QUEUE_OCC_68_count, 295, 0 | |
| MEM_QUEUE_OCC_68_total_count, 295, 0 | |
| MEM_QUEUE_OCC_72_count, 295, 0 | |
| MEM_QUEUE_OCC_72_total_count, 295, 0 | |
| MEM_QUEUE_OCC_76_count, 295, 0 | |
| MEM_QUEUE_OCC_76_total_count, 295, 0 | |
| MEM_QUEUE_OCC_80_count, 295, 0 | |
| MEM_QUEUE_OCC_80_total_count, 295, 0 | |
| MEM_QUEUE_OCC_84_count, 295, 0 | |
| MEM_QUEUE_OCC_84_total_count, 295, 0 | |
| MEM_QUEUE_OCC_88_count, 295, 0 | |
| MEM_QUEUE_OCC_88_total_count, 295, 0 | |
| MEM_QUEUE_OCC_92_count, 295, 0 | |
| MEM_QUEUE_OCC_92_total_count, 295, 0 | |
| MEM_QUEUE_OCC_96_count, 295, 0 | |
| MEM_QUEUE_OCC_96_total_count, 295, 0 | |
| MEM_QUEUE_OCC_100_count, 295, 0 | |
| MEM_QUEUE_OCC_100_total_count, 295, 0 | |
| MEM_QUEUE_OCC_104_count, 295, 0 | |
| MEM_QUEUE_OCC_104_total_count, 295, 0 | |
| MEM_QUEUE_OCC_108_count, 295, 0 | |
| MEM_QUEUE_OCC_108_total_count, 295, 0 | |
| MEM_QUEUE_OCC_112_count, 295, 0 | |
| MEM_QUEUE_OCC_112_total_count, 295, 0 | |
| MEM_QUEUE_OCC_116_count, 295, 0 | |
| MEM_QUEUE_OCC_116_total_count, 295, 0 | |
| MEM_QUEUE_OCC_120_count, 295, 0 | |
| MEM_QUEUE_OCC_120_total_count, 295, 0 | |
| MEM_QUEUE_OCC_124_count, 295, 0 | |
| MEM_QUEUE_OCC_124_total_count, 295, 0 | |
| MEM_QUEUE_OCC_128_count, 295, 0 | |
| MEM_QUEUE_OCC_128_total_count, 295, 0 | |
| OPEN_PAGE_HIT_count, 296, 0 | |
| OPEN_PAGE_HIT_total_count, 296, 0 | |
| CLOSED_PAGE_MISS_count, 296, 0 | |
| CLOSED_PAGE_MISS_total_count, 296, 0 | |
| WRONG_PAGE_MISS_count, 296, 0 | |
| WRONG_PAGE_MISS_total_count, 296, 0 | |
| L0_LD_BANK_BLOCK_count, 297, 0 | |
| L0_LD_BANK_BLOCK_total_count, 297, 0 | |
| L0_LD_BANK_AVAIL_count, 297, 0 | |
| L0_LD_BANK_AVAIL_total_count, 297, 0 | |
| L0_ST_BANK_BLOCK_count, 298, 0 | |
| L0_ST_BANK_BLOCK_total_count, 298, 0 | |
| L0_ST_BANK_AVAIL_count, 298, 0 | |
| L0_ST_BANK_AVAIL_total_count, 298, 0 | |
| L0_LD_CACHE_BLOCK_count, 299, 0 | |
| L0_LD_CACHE_BLOCK_total_count, 299, 0 | |
| L0_LD_CACHE_AVAIL_count, 299, 0 | |
| L0_LD_CACHE_AVAIL_total_count, 299, 0 | |
| MLC_LD_BANK_BLOCK_count, 300, 0 | |
| MLC_LD_BANK_BLOCK_total_count, 300, 0 | |
| MLC_LD_BANK_AVAIL_count, 300, 14638 | |
| MLC_LD_BANK_AVAIL_total_count, 300, 14638 | |
| MLC_ST_BANK_BLOCK_count, 301, 0 | |
| MLC_ST_BANK_BLOCK_total_count, 301, 0 | |
| MLC_ST_BANK_AVAIL_count, 301, 14514 | |
| MLC_ST_BANK_AVAIL_total_count, 301, 14514 | |
| MLC_LD_CACHE_BLOCK_count, 302, 0 | |
| MLC_LD_CACHE_BLOCK_total_count, 302, 0 | |
| MLC_LD_CACHE_AVAIL_count, 302, 0 | |
| MLC_LD_CACHE_AVAIL_total_count, 302, 0 | |
| MLC_ST_CACHE_BLOCK_count, 303, 0 | |
| MLC_ST_CACHE_BLOCK_total_count, 303, 0 | |
| MLC_ST_CACHE_AVAIL_count, 303, 0 | |
| MLC_ST_CACHE_AVAIL_total_count, 303, 0 | |
| L1_LD_BANK_BLOCK_count, 304, 0 | |
| L1_LD_BANK_BLOCK_total_count, 304, 0 | |
| L1_LD_BANK_AVAIL_count, 304, 29665 | |
| L1_LD_BANK_AVAIL_total_count, 304, 29665 | |
| L1_ST_BANK_BLOCK_count, 305, 0 | |
| L1_ST_BANK_BLOCK_total_count, 305, 0 | |
| L1_ST_BANK_AVAIL_count, 305, 682 | |
| L1_ST_BANK_AVAIL_total_count, 305, 682 | |
| L1_LD_CACHE_BLOCK_count, 306, 0 | |
| L1_LD_CACHE_BLOCK_total_count, 306, 0 | |
| L1_LD_CACHE_AVAIL_count, 306, 0 | |
| L1_LD_CACHE_AVAIL_total_count, 306, 0 | |
| L1_ST_CACHE_BLOCK_count, 307, 0 | |
| L1_ST_CACHE_BLOCK_total_count, 307, 0 | |
| L1_ST_CACHE_AVAIL_count, 307, 0 | |
| L1_ST_CACHE_AVAIL_total_count, 307, 0 | |
| MEM_LD_BANK_BLOCK_count, 308, 0 | |
| MEM_LD_BANK_BLOCK_total_count, 308, 0 | |
| MEM_LD_BANK_AVAIL_count, 308, 0 | |
| MEM_LD_BANK_AVAIL_total_count, 308, 0 | |
| MEM_ST_BANK_BLOCK_count, 309, 0 | |
| MEM_ST_BANK_BLOCK_total_count, 309, 0 | |
| MEM_ST_BANK_AVAIL_count, 309, 0 | |
| MEM_ST_BANK_AVAIL_total_count, 309, 0 | |
| MEM_PF_BANK_BLOCK_count, 310, 0 | |
| MEM_PF_BANK_BLOCK_total_count, 310, 0 | |
| MEM_PF_BANK_AVAIL_count, 310, 0 | |
| MEM_PF_BANK_AVAIL_total_count, 310, 0 | |
| L0_FILL_count, 0, 0 | |
| L0_FILL_total_count, 0, 0 | |
| L1_FILL_count, 311, 15140 | |
| L1_FILL_total_count, 311, 15140 | |
| L1_WB_FILL_count, 311, 0 | |
| L1_WB_FILL_total_count, 311, 0 | |
| L1_DEMAND_FILL_count, 312, 117 | |
| L1_DEMAND_FILL_total_count, 312, 117 | |
| L1_PREF_FILL_count, 312, 15023 | |
| L1_PREF_FILL_total_count, 312, 15023 | |
| MLC_FILL_count, 313, 15129 | |
| MLC_FILL_total_count, 313, 15129 | |
| MLC_WB_FILL_count, 313, 0 | |
| MLC_WB_FILL_total_count, 313, 0 | |
| MLC_DEMAND_FILL_count, 314, 14638 | |
| MLC_DEMAND_FILL_total_count, 314, 14638 | |
| MLC_PREF_FILL_count, 314, 491 | |
| MLC_PREF_FILL_total_count, 314, 491 | |
| NORESET_L1_FILL_count, 0, 15140 | |
| NORESET_L1_FILL_total_count, 0, 15140 | |
| NORESET_L1_FILL_NONPREF_count, 0, 20 | |
| NORESET_L1_FILL_NONPREF_total_count, 0, 20 | |
| NORESET_L1_FILL_PREF_count, 0, 15120 | |
| NORESET_L1_FILL_PREF_total_count, 0, 15120 | |
| NORESET_L1_EVICT_count, 0, 0 | |
| NORESET_L1_EVICT_total_count, 0, 0 | |
| NORESET_L1_EVICT_NONPREF_count, 0, 0 | |
| NORESET_L1_EVICT_NONPREF_total_count, 0, 0 | |
| NORESET_L1_EVICT_PREF_USED_count, 0, 0 | |
| NORESET_L1_EVICT_PREF_USED_total_count, 0, 0 | |
| NORESET_L1_EVICT_PREF_UNUSED_count, 0, 0 | |
| NORESET_L1_EVICT_PREF_UNUSED_total_count, 0, 0 | |
| NORESET_L1_PREF_USED_count, 0, 14521 | |
| NORESET_L1_PREF_USED_total_count, 0, 14521 | |
| ORACLE_OFFPATH_DC_FILL_count, 0, 0 | |
| ORACLE_OFFPATH_DC_FILL_total_count, 0, 0 | |
| ORACLE_OFFPATH_IC_FILL_count, 0, 0 | |
| ORACLE_OFFPATH_IC_FILL_total_count, 0, 0 | |
| ORACLE_OFFPATH_L1_FILL_count, 0, 0 | |
| ORACLE_OFFPATH_L1_FILL_total_count, 0, 0 | |
| UPDATE_EVENT_QUEUE_PROCESS_count, 0, 0 | |
| UPDATE_EVENT_QUEUE_PROCESS_total_count, 0, 0 | |
| INSERT_EVENT_QUEUE_PROCESS_count, 0, 0 | |
| INSERT_EVENT_QUEUE_PROCESS_total_count, 0, 0 | |
| ICFILL_AFTER_REDIRECT_count, 0, 0 | |
| ICFILL_AFTER_REDIRECT_total_count, 0, 0 | |
| EVENT_QUEUE_MATCH_ADD_REQ_count, 0, 0 | |
| EVENT_QUEUE_MATCH_ADD_REQ_total_count, 0, 0 | |
| DC_PREF_CACHE_INSERT_REQ_count, 0, 0 | |
| DC_PREF_CACHE_INSERT_REQ_total_count, 0, 0 | |
| DC_PREF_REQ_DCACHE_HIT_count, 315, 0 | |
| DC_PREF_REQ_DCACHE_HIT_total_count, 315, 0 | |
| DC_PREF_REQ_PREF_CACHE_HIT_count, 315, 0 | |
| DC_PREF_REQ_PREF_CACHE_HIT_total_count, 315, 0 | |
| DC_PREF_REQ_L1_MISS_count, 315, 0 | |
| DC_PREF_REQ_L1_MISS_total_count, 315, 0 | |
| DC_PREF_REQ_CORR_count, 315, 0 | |
| DC_PREF_REQ_CORR_total_count, 315, 0 | |
| DC_PREF_CACHE_INSERT_count, 0, 0 | |
| DC_PREF_CACHE_INSERT_total_count, 0, 0 | |
| DC_PREF_CACHE_HIT_PER_count, 0, 0 | |
| DC_PREF_CACHE_HIT_PER_pct, 0, 0.000 | |
| DC_PREF_CACHE_HIT_PER_total_count, 0, 0 | |
| DC_PREF_CACHE_HIT_PER_total_pct, 0, 0.000 | |
| DC_PREF_CACHE_HIT_PER_OFFPATH_count, 0, 0 | |
| DC_PREF_CACHE_HIT_PER_OFFPATH_pct, 0, 0.000 | |
| DC_PREF_CACHE_HIT_PER_OFFPATH_total_count, 0, 0 | |
| DC_PREF_CACHE_HIT_PER_OFFPATH_total_pct, 0, 0.000 | |
| DC_PREF_CACHE_HIT_count, 0, 0 | |
| DC_PREF_CACHE_HIT_total_count, 0, 0 | |
| DC_PREF_CACHE_HIT_OFFPATH_count, 0, 0 | |
| DC_PREF_CACHE_HIT_OFFPATH_total_count, 0, 0 | |
| DC_PREF_HIT_L1_MISS_count, 0, 0 | |
| DC_PREF_HIT_L1_MISS_total_count, 0, 0 | |
| IC_PREF_CACHE_HIT_PER_count, 0, 0 | |
| IC_PREF_CACHE_HIT_PER_pct, 0, 0.000 | |
| IC_PREF_CACHE_HIT_PER_total_count, 0, 0 | |
| IC_PREF_CACHE_HIT_PER_total_pct, 0, 0.000 | |
| IC_PREF_CACHE_HIT_PER_OFFPATH_count, 0, 0 | |
| IC_PREF_CACHE_HIT_PER_OFFPATH_pct, 0, 0.000 | |
| IC_PREF_CACHE_HIT_PER_OFFPATH_total_count, 0, 0 | |
| IC_PREF_CACHE_HIT_PER_OFFPATH_total_pct, 0, 0.000 | |
| IC_PREF_CACHE_HIT_count, 0, 0 | |
| IC_PREF_CACHE_HIT_total_count, 0, 0 | |
| IC_PREF_CACHE_HIT_OFFPATH_count, 0, 0 | |
| IC_PREF_CACHE_HIT_OFFPATH_total_count, 0, 0 | |
| L1_PREF_CACHE_HIT_PER_count, 0, 0 | |
| L1_PREF_CACHE_HIT_PER_pct, 0, 0.000 | |
| L1_PREF_CACHE_HIT_PER_total_count, 0, 0 | |
| L1_PREF_CACHE_HIT_PER_total_pct, 0, 0.000 | |
| L1_PREF_CACHE_HIT_PER_OFFPATH_count, 0, 0 | |
| L1_PREF_CACHE_HIT_PER_OFFPATH_pct, 0, 0.000 | |
| L1_PREF_CACHE_HIT_PER_OFFPATH_total_count, 0, 0 | |
| L1_PREF_CACHE_HIT_PER_OFFPATH_total_pct, 0, 0.000 | |
| L1_PREF_CACHE_HIT_count, 0, 0 | |
| L1_PREF_CACHE_HIT_total_count, 0, 0 | |
| L1_PREF_CACHE_HIT_OFFPATH_count, 0, 0 | |
| L1_PREF_CACHE_HIT_OFFPATH_total_count, 0, 0 | |
| DC_PREF_CACHE_FILL_count, 0, 0 | |
| DC_PREF_CACHE_FILL_total_count, 0, 0 | |
| DC_PREF_MOVE_DC_count, 0, 0 | |
| DC_PREF_MOVE_DC_pct, 0, -nan | |
| DC_PREF_MOVE_DC_total_count, 0, 0 | |
| DC_PREF_MOVE_DC_total_pct, 0, -nan | |
| DC_PREF_MOVE_L1_count, 0, 0 | |
| DC_PREF_MOVE_L1_pct, 0, -nan | |
| DC_PREF_MOVE_L1_total_count, 0, 0 | |
| DC_PREF_MOVE_L1_total_pct, 0, -nan | |
| IC_PREF_CACHE_FILL_count, 0, 0 | |
| IC_PREF_CACHE_FILL_total_count, 0, 0 | |
| IC_PREF_MOVE_IC_count, 0, 0 | |
| IC_PREF_MOVE_IC_pct, 0, -nan | |
| IC_PREF_MOVE_IC_total_count, 0, 0 | |
| IC_PREF_MOVE_IC_total_pct, 0, -nan | |
| IC_PREF_MOVE_L1_count, 0, 0 | |
| IC_PREF_MOVE_L1_pct, 0, -nan | |
| IC_PREF_MOVE_L1_total_count, 0, 0 | |
| IC_PREF_MOVE_L1_total_pct, 0, -nan | |
| L1_PREF_CACHE_FILL_count, 0, 0 | |
| L1_PREF_CACHE_FILL_total_count, 0, 0 | |
| L1_PREF_MOVE_L1_count, 0, 0 | |
| L1_PREF_MOVE_L1_pct, 0, -nan | |
| L1_PREF_MOVE_L1_total_count, 0, 0 | |
| L1_PREF_MOVE_L1_total_pct, 0, -nan | |
| OFF_PATH_CONFIRMED_count, 0, 136 | |
| OFF_PATH_CONFIRMED_total_count, 0, 136 | |
| OFF_PATH_NO_FILL_L1_count, 0, 0 | |
| OFF_PATH_NO_FILL_L1_total_count, 0, 0 | |
| WB_L1_MISS_FILL_L1_count, 0, 0 | |
| WB_L1_MISS_FILL_L1_total_count, 0, 0 | |
| WB_MLC_MISS_FILL_MLC_count, 0, 0 | |
| WB_MLC_MISS_FILL_MLC_total_count, 0, 0 | |
| ICACHE_EVICT_REQ_WB_L1_count, 0, 0 | |
| ICACHE_EVICT_REQ_WB_L1_total_count, 0, 0 | |
| DCACHE_EVICT_REQ_WB_L1_count, 0, 0 | |
| DCACHE_EVICT_REQ_WB_L1_total_count, 0, 0 | |
| DCACHE_EVICT_REQ_WB_L1_NOREAD_count, 0, 0 | |
| DCACHE_EVICT_REQ_WB_L1_NOREAD_total_count, 0, 0 | |
| L1_FILL_SKIPPED_count, 0, 0 | |
| L1_FILL_SKIPPED_total_count, 0, 0 | |
| MLC_FILL_SKIPPED_count, 0, 0 | |
| MLC_FILL_SKIPPED_total_count, 0, 0 | |
| DCACHE_FILL_count, 0, 15026 | |
| DCACHE_FILL_total_count, 0, 15026 | |
| DCACHE_WB_REQ_count, 0, 14514 | |
| DCACHE_WB_REQ_pct, 0, 0.966 | |
| DCACHE_WB_REQ_total_count, 0, 14514 | |
| DCACHE_WB_REQ_total_pct, 0, 0.966 | |
| DCACHE_WB_REQ_DIRTY_count, 316, 14514 | |
| DCACHE_WB_REQ_DIRTY_total_count, 316, 14514 | |
| DCACHE_WB_REQ_NODIRTY_count, 316, 0 | |
| DCACHE_WB_REQ_NODIRTY_total_count, 316, 0 | |
| ICACHE_FILL_count, 0, 103 | |
| ICACHE_FILL_total_count, 0, 103 | |
| ICACHE_WB_REQ_count, 0, 0 | |
| ICACHE_WB_REQ_pct, 0, 0.000 | |
| ICACHE_WB_REQ_total_count, 0, 0 | |
| ICACHE_WB_REQ_total_pct, 0, 0.000 | |
| L1_FILL_DIRTY_count, 0, 0 | |
| L1_FILL_DIRTY_pct, 0, 0.000 | |
| L1_FILL_DIRTY_total_count, 0, 0 | |
| L1_FILL_DIRTY_total_pct, 0, 0.000 | |
| MLC_FILL_DIRTY_count, 0, 682 | |
| MLC_FILL_DIRTY_pct, 0, 0.045 | |
| MLC_FILL_DIRTY_total_count, 0, 682 | |
| MLC_FILL_DIRTY_total_pct, 0, 0.045 | |
| ICACHE_UNUSEFUL_CL_CYC_count, 0, 0 | |
| ICACHE_UNUSEFUL_CL_CYC_total_count, 0, 0 | |
| ICACHE_UNUSEFUL_CL_count, 0, 0 | |
| ICACHE_UNUSEFUL_CL_total_count, 0, 0 | |
| ICACHE_EVICT_MISS_ONPATH_BY_FDIP_count, 317, 0 | |
| ICACHE_EVICT_MISS_ONPATH_BY_FDIP_total_count, 317, 0 | |
| ICACHE_EVICT_MISS_OFFPATH_BY_FDIP_count, 317, 0 | |
| ICACHE_EVICT_MISS_OFFPATH_BY_FDIP_total_count, 317, 0 | |
| ICACHE_EVICT_MISS_BY_FDIP_ONPATH_count, 318, 0 | |
| ICACHE_EVICT_MISS_BY_FDIP_ONPATH_total_count, 318, 0 | |
| ICACHE_EVICT_MISS_BY_FDIP_OFFPATH_count, 318, 0 | |
| ICACHE_EVICT_MISS_BY_FDIP_OFFPATH_total_count, 318, 0 | |
| ICACHE_EVICT_HIT_ONPATH_BY_FDIP_count, 319, 0 | |
| ICACHE_EVICT_HIT_ONPATH_BY_FDIP_total_count, 319, 0 | |
| ICACHE_EVICT_HIT_OFFPATH_BY_FDIP_count, 319, 0 | |
| ICACHE_EVICT_HIT_OFFPATH_BY_FDIP_total_count, 319, 0 | |
| ICACHE_EVICT_HIT_BY_FDIP_ONPATH_count, 320, 0 | |
| ICACHE_EVICT_HIT_BY_FDIP_ONPATH_total_count, 320, 0 | |
| ICACHE_EVICT_HIT_BY_FDIP_OFFPATH_count, 320, 0 | |
| ICACHE_EVICT_HIT_BY_FDIP_OFFPATH_total_count, 320, 0 | |
| MEM_REQ_DENIED_NULL_count, 321, 0 | |
| MEM_REQ_DENIED_NULL_total_count, 321, 0 | |
| MEM_REQ_DENIED_INST_OUTOF_CS_count, 321, 0 | |
| MEM_REQ_DENIED_INST_OUTOF_CS_total_count, 321, 0 | |
| MEM_REQ_DENIED_DATA_IN_CS_count, 321, 0 | |
| MEM_REQ_DENIED_DATA_IN_CS_total_count, 321, 0 | |
| MEM_REQ_DENIED_DATA_OUTOF_RANGE_count, 321, 0 | |
| MEM_REQ_DENIED_DATA_OUTOF_RANGE_total_count, 321, 0 | |
| MEM_REQ_DENIED_count, 322, 0 | |
| MEM_REQ_DENIED_total_count, 322, 0 | |
| MEM_REQ_NOT_DENIED_count, 322, 0 | |
| MEM_REQ_NOT_DENIED_total_count, 322, 0 | |
| DEMAND_HIT_WB_STALL_count, 0, 0 | |
| DEMAND_HIT_WB_STALL_total_count, 0, 0 | |
| EXCLUSION_VIOLATED_OSR_count, 323, 0 | |
| EXCLUSION_VIOLATED_OSR_total_count, 323, 0 | |
| EXCLUSION_VIOLATED_NOTOSR_count, 323, 0 | |
| EXCLUSION_VIOLATED_NOTOSR_total_count, 323, 0 | |
| EXCLUSION_NOT_VIOLATED_count, 323, 0 | |
| EXCLUSION_NOT_VIOLATED_total_count, 323, 0 | |
| DIRTY_WRITE_TO_ICACHE_count, 0, 0 | |
| DIRTY_WRITE_TO_ICACHE_total_count, 0, 0 | |
| STREAM_DC_HIT_NOSEND_count, 324, 0 | |
| STREAM_DC_HIT_NOSEND_total_count, 324, 0 | |
| STREAM_WBQDC_HIT_NOSEND_count, 324, 0 | |
| STREAM_WBQDC_HIT_NOSEND_total_count, 324, 0 | |
| STREAM_DCACHE_PREF_HIT_count, 0, 0 | |
| STREAM_DCACHE_PREF_HIT_total_count, 0, 0 | |
| PREF_DC_HIT_ON_INSERT_count, 325, 0 | |
| PREF_DC_HIT_ON_INSERT_total_count, 325, 0 | |
| PREF_L1_HIT_ON_INSERT_count, 325, 0 | |
| PREF_L1_HIT_ON_INSERT_total_count, 325, 0 | |
| L1_NEWREQ_MATCHED_MLC_REQ_count, 0, 0 | |
| L1_NEWREQ_MATCHED_MLC_REQ_total_count, 0, 0 | |
| MLC_NEWREQ_MATCHED_L2_PREF_count, 0, 491 | |
| MLC_NEWREQ_MATCHED_L2_PREF_total_count, 0, 491 | |
| MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT_count, 0, 0 | |
| MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT_pct, 0, 0.000 | |
| MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT_total_count, 0, 0 | |
| MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT_total_pct, 0, 0.000 | |
| NEWREQ_WB_MATCH_IGNORED_count, 0, 0 | |
| NEWREQ_WB_MATCH_IGNORED_total_count, 0, 0 | |
| DEMAND_MATCH_WB_NEW_DONE_FUNC_count, 326, 0 | |
| DEMAND_MATCH_WB_NEW_DONE_FUNC_total_count, 326, 0 | |
| DEMAND_MATCH_WB_NEW_DONE_FUNC_NULL_count, 326, 0 | |
| DEMAND_MATCH_WB_NEW_DONE_FUNC_NULL_total_count, 326, 0 | |
| DEMAND_MATCH_WB_DONE_FUNC_NOT_SAME_count, 326, 0 | |
| DEMAND_MATCH_WB_DONE_FUNC_NOT_SAME_total_count, 326, 0 | |
| DEMAND_MATCH_WB_DONE_FUNC_SAME_count, 326, 0 | |
| DEMAND_MATCH_WB_DONE_FUNC_SAME_total_count, 326, 0 | |
| DEMAND_MATCH_WB_count, 327, 0 | |
| DEMAND_MATCH_WB_total_count, 327, 0 | |
| DEMAND_MATCH_WB_NODIRTY_count, 327, 0 | |
| DEMAND_MATCH_WB_NODIRTY_total_count, 327, 0 | |
| DEMAND_MATCH_WBALL_IFETCH_count, 328, 0 | |
| DEMAND_MATCH_WBALL_IFETCH_total_count, 328, 0 | |
| DEMAND_MATCH_WBALL_DFETCH_count, 328, 0 | |
| DEMAND_MATCH_WBALL_DFETCH_total_count, 328, 0 | |
| DEMAND_MATCH_WBALL_DSTORE_count, 328, 0 | |
| DEMAND_MATCH_WBALL_DSTORE_total_count, 328, 0 | |
| DEMAND_MATCH_WBALL_IPRF_count, 328, 0 | |
| DEMAND_MATCH_WBALL_IPRF_total_count, 328, 0 | |
| DEMAND_MATCH_WBALL_DPRF_count, 328, 0 | |
| DEMAND_MATCH_WBALL_DPRF_total_count, 328, 0 | |
| DEMAND_MATCH_WBALL_WB_count, 328, 0 | |
| DEMAND_MATCH_WBALL_WB_total_count, 328, 0 | |
| DEMAND_MATCH_WBALL_WB_NODIRTY_count, 328, 0 | |
| DEMAND_MATCH_WBALL_WB_NODIRTY_total_count, 328, 0 | |
| DEMAND_MATCH_WB_IFETCH_count, 329, 0 | |
| DEMAND_MATCH_WB_IFETCH_total_count, 329, 0 | |
| DEMAND_MATCH_WB_DFETCH_count, 329, 0 | |
| DEMAND_MATCH_WB_DFETCH_total_count, 329, 0 | |
| DEMAND_MATCH_WB_DSTORE_count, 329, 0 | |
| DEMAND_MATCH_WB_DSTORE_total_count, 329, 0 | |
| DEMAND_MATCH_WB_IPRF_count, 329, 0 | |
| DEMAND_MATCH_WB_IPRF_total_count, 329, 0 | |
| DEMAND_MATCH_WB_DPRF_count, 329, 0 | |
| DEMAND_MATCH_WB_DPRF_total_count, 329, 0 | |
| DEMAND_MATCH_WB_WB_count, 329, 0 | |
| DEMAND_MATCH_WB_WB_total_count, 329, 0 | |
| DEMAND_MATCH_WB_WB_NODIRTY_count, 329, 0 | |
| DEMAND_MATCH_WB_WB_NODIRTY_total_count, 329, 0 | |
| DEMAND_MATCH_WB_ND_IFETCH_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_IFETCH_total_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_DFETCH_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_DFETCH_total_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_DSTORE_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_DSTORE_total_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_IPRF_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_IPRF_total_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_DPRF_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_DPRF_total_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_WB_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_WB_total_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_WB_NODIRTY_count, 330, 0 | |
| DEMAND_MATCH_WB_ND_WB_NODIRTY_total_count, 330, 0 | |
| WB_MATCH_DEMAND_count, 331, 0 | |
| WB_MATCH_DEMAND_total_count, 331, 0 | |
| WB_MATCH_PREF_count, 331, 0 | |
| WB_MATCH_PREF_total_count, 331, 0 | |
| WB_MATCH_WB_count, 331, 0 | |
| WB_MATCH_WB_total_count, 331, 0 | |
| WB_MATCH_WB_FILTERED_count, 331, 14567 | |
| WB_MATCH_WB_FILTERED_total_count, 331, 14567 | |
| WB_COMING_BACK_FROM_MEM_count, 0, 0 | |
| WB_COMING_BACK_FROM_MEM_total_count, 0, 0 | |
| WB_COMING_BACK_FROM_L1_count, 0, 0 | |
| WB_COMING_BACK_FROM_L1_total_count, 0, 0 | |
| WB_COMING_BACK_FROM_MLC_count, 0, 0 | |
| WB_COMING_BACK_FROM_MLC_total_count, 0, 0 | |
| MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_count, 332, 0 | |
| MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_total_count, 332, 0 | |
| MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_ETC_count, 332, 15526 | |
| MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_ETC_total_count, 332, 15526 | |
| TOTAL_ONPATH_ICACHE_FILLS_count, 0, 0 | |
| TOTAL_ONPATH_ICACHE_FILLS_total_count, 0, 0 | |
| TOTAL_ONPATH_DCACHE_FILLS_count, 0, 0 | |
| TOTAL_ONPATH_DCACHE_FILLS_total_count, 0, 0 | |
| TOTAL_ONPATH_L1_FILLS_count, 0, 0 | |
| TOTAL_ONPATH_L1_FILLS_total_count, 0, 0 | |
| PER1K_ONPATH_ICACHE_FILLS_count, 0, 0 | |
| PER1K_ONPATH_ICACHE_FILLS_pct, 0, 0.000 | |
| PER1K_ONPATH_ICACHE_FILLS_total_count, 0, 0 | |
| PER1K_ONPATH_ICACHE_FILLS_total_pct, 0, 0.000 | |
| PER1K_ONPATH_DCACHE_FILLS_count, 0, 0 | |
| PER1K_ONPATH_DCACHE_FILLS_pct, 0, 0.000 | |
| PER1K_ONPATH_DCACHE_FILLS_total_count, 0, 0 | |
| PER1K_ONPATH_DCACHE_FILLS_total_pct, 0, 0.000 | |
| PER1K_ONPATH_L1_FILLS_count, 0, 0 | |
| PER1K_ONPATH_L1_FILLS_pct, 0, 0.000 | |
| PER1K_ONPATH_L1_FILLS_total_count, 0, 0 | |
| PER1K_ONPATH_L1_FILLS_total_pct, 0, 0.000 | |
| PER1K_L1_DEMAND_MISS_ONPATH_count, 0, 21 | |
| PER1K_L1_DEMAND_MISS_ONPATH_pct, 0, 0.022 | |
| PER1K_L1_DEMAND_MISS_ONPATH_total_count, 0, 21 | |
| PER1K_L1_DEMAND_MISS_ONPATH_total_pct, 0, 0.022 | |
| PER1K_L1_DEMAND_MISS_OFFPATH_count, 0, 0 | |
| PER1K_L1_DEMAND_MISS_OFFPATH_pct, 0, 0.000 | |
| PER1K_L1_DEMAND_MISS_OFFPATH_total_count, 0, 0 | |
| PER1K_L1_DEMAND_MISS_OFFPATH_total_pct, 0, 0.000 | |
| L2_IDEAL_FILL_L1_count, 333, 0 | |
| L2_IDEAL_FILL_L1_total_count, 333, 0 | |
| L2_IDEAL_MISS_L2_count, 333, 0 | |
| L2_IDEAL_MISS_L2_total_count, 333, 0 | |
| L2_IDEAL_FILL_ICACHE_count, 334, 0 | |
| L2_IDEAL_FILL_ICACHE_total_count, 334, 0 | |
| L2_IDEAL_MISS_ICACHE_count, 334, 0 | |
| L2_IDEAL_MISS_ICACHE_total_count, 334, 0 | |
| HPS_MISS_DELTA__0_count, 335, 0 | |
| HPS_MISS_DELTA__0_total_count, 335, 0 | |
| HPS_MISS_DELTA__1_count, 335, 0 | |
| HPS_MISS_DELTA__1_total_count, 335, 0 | |
| HPS_MISS_DELTA__2_count, 335, 0 | |
| HPS_MISS_DELTA__2_total_count, 335, 0 | |
| HPS_MISS_DELTA__3_count, 335, 0 | |
| HPS_MISS_DELTA__3_total_count, 335, 0 | |
| HPS_MISS_DELTA__4_count, 335, 0 | |
| HPS_MISS_DELTA__4_total_count, 335, 0 | |
| HPS_MISS_DELTA__5_count, 335, 0 | |
| HPS_MISS_DELTA__5_total_count, 335, 0 | |
| HPS_MISS_DELTA__6_count, 335, 0 | |
| HPS_MISS_DELTA__6_total_count, 335, 0 | |
| HPS_MISS_DELTA__7_count, 335, 0 | |
| HPS_MISS_DELTA__7_total_count, 335, 0 | |
| HPS_MISS_DELTA__8_count, 335, 0 | |
| HPS_MISS_DELTA__8_total_count, 335, 0 | |
| HPS_MISS_DELTA__9_count, 335, 0 | |
| HPS_MISS_DELTA__9_total_count, 335, 0 | |
| HPS_HIT_DELTA__0_count, 336, 0 | |
| HPS_HIT_DELTA__0_total_count, 336, 0 | |
| HPS_HIT_DELTA__1_count, 336, 0 | |
| HPS_HIT_DELTA__1_total_count, 336, 0 | |
| HPS_HIT_DELTA__2_count, 336, 0 | |
| HPS_HIT_DELTA__2_total_count, 336, 0 | |
| HPS_HIT_DELTA__3_count, 336, 0 | |
| HPS_HIT_DELTA__3_total_count, 336, 0 | |
| HPS_HIT_DELTA__4_count, 336, 0 | |
| HPS_HIT_DELTA__4_total_count, 336, 0 | |
| HPS_HIT_DELTA__5_count, 336, 0 | |
| HPS_HIT_DELTA__5_total_count, 336, 0 | |
| HPS_HIT_DELTA__6_count, 336, 0 | |
| HPS_HIT_DELTA__6_total_count, 336, 0 | |
| HPS_HIT_DELTA__7_count, 336, 0 | |
| HPS_HIT_DELTA__7_total_count, 336, 0 | |
| HPS_HIT_DELTA__8_count, 336, 0 | |
| HPS_HIT_DELTA__8_total_count, 336, 0 | |
| HPS_HIT_DELTA__9_count, 336, 0 | |
| HPS_HIT_DELTA__9_total_count, 336, 0 | |
| DC_MISS_DELTA__0_count, 337, 0 | |
| DC_MISS_DELTA__0_total_count, 337, 0 | |
| DC_MISS_DELTA__1_count, 337, 0 | |
| DC_MISS_DELTA__1_total_count, 337, 0 | |
| DC_MISS_DELTA__2_count, 337, 0 | |
| DC_MISS_DELTA__2_total_count, 337, 0 | |
| DC_MISS_DELTA__3_count, 337, 0 | |
| DC_MISS_DELTA__3_total_count, 337, 0 | |
| DC_MISS_DELTA__4_count, 337, 0 | |
| DC_MISS_DELTA__4_total_count, 337, 0 | |
| DC_MISS_DELTA__5_count, 337, 0 | |
| DC_MISS_DELTA__5_total_count, 337, 0 | |
| DC_MISS_DELTA__6_count, 337, 0 | |
| DC_MISS_DELTA__6_total_count, 337, 0 | |
| DC_MISS_DELTA__7_count, 337, 0 | |
| DC_MISS_DELTA__7_total_count, 337, 0 | |
| DC_MISS_DELTA__8_count, 337, 0 | |
| DC_MISS_DELTA__8_total_count, 337, 0 | |
| DC_MISS_DELTA__9_count, 337, 0 | |
| DC_MISS_DELTA__9_total_count, 337, 0 | |
| ONE_MORE_SUCESS_count, 338, 0 | |
| ONE_MORE_SUCESS_total_count, 338, 0 | |
| ONE_MORE_DISCARDED_L0CACHE_count, 338, 0 | |
| ONE_MORE_DISCARDED_L0CACHE_total_count, 338, 0 | |
| ONE_MORE_DISCARDED_MEM_REQ_FULL_count, 338, 0 | |
| ONE_MORE_DISCARDED_MEM_REQ_FULL_total_count, 338, 0 | |
| PREF_L1_TOTAL_SENT_count, 0, 15026 | |
| PREF_L1_TOTAL_SENT_total_count, 0, 15026 | |
| PREF_L1_TOTAL_USED_count, 339, 14521 | |
| PREF_L1_TOTAL_USED_total_count, 339, 14521 | |
| PREF_L1_TOTAL_PARTIAL_USED_count, 339, 491 | |
| PREF_L1_TOTAL_PARTIAL_USED_total_count, 339, 491 | |
| PREF_L1_TOTAL_NOT_USED_count, 339, 11 | |
| PREF_L1_TOTAL_NOT_USED_total_count, 339, 11 | |
| PREF_L1_TOTAL_DROPPED_count, 339, 0 | |
| PREF_L1_TOTAL_DROPPED_total_count, 339, 0 | |
| PREF_MLC_TOTAL_SENT_count, 0, 0 | |
| PREF_MLC_TOTAL_SENT_total_count, 0, 0 | |
| PREF_MLC_TOTAL_USED_count, 340, 0 | |
| PREF_MLC_TOTAL_USED_total_count, 340, 0 | |
| PREF_MLC_TOTAL_PARTIAL_USED_count, 340, 491 | |
| PREF_MLC_TOTAL_PARTIAL_USED_total_count, 340, 491 | |
| PREF_MLC_TOTAL_NOT_USED_count, 340, 0 | |
| PREF_MLC_TOTAL_NOT_USED_total_count, 340, 0 | |
| PREF_MLC_TOTAL_DROPPED_count, 340, 0 | |
| PREF_MLC_TOTAL_DROPPED_total_count, 340, 0 | |
| CORE_MLC_PREF_REQ_MISS_count, 341, 0 | |
| CORE_MLC_PREF_REQ_MISS_total_count, 341, 0 | |
| CORE_MLC_DEMAND_MISS_count, 341, 14541 | |
| CORE_MLC_DEMAND_MISS_total_count, 341, 14541 | |
| CORE_MLC_WB_MISS_count, 341, 97 | |
| CORE_MLC_WB_MISS_total_count, 341, 97 | |
| CORE_MLC_PREF_REQ_HIT_count, 342, 0 | |
| CORE_MLC_PREF_REQ_HIT_total_count, 342, 0 | |
| CORE_MLC_DEMAND_HIT_count, 342, 0 | |
| CORE_MLC_DEMAND_HIT_total_count, 342, 0 | |
| CORE_MLC_WB_HIT_count, 342, 14513 | |
| CORE_MLC_WB_HIT_total_count, 342, 14513 | |
| CORE_MLC_HIT_count, 343, 0 | |
| CORE_MLC_HIT_total_count, 343, 0 | |
| CORE_MLC_MISS_count, 343, 14541 | |
| CORE_MLC_MISS_total_count, 343, 14541 | |
| CORE_MLC_FILL_count, 344, 15129 | |
| CORE_MLC_FILL_total_count, 344, 15129 | |
| CORE_MLC_WB_FILL_count, 344, 0 | |
| CORE_MLC_WB_FILL_total_count, 344, 0 | |
| CORE_MLC_DEMAND_FILL_count, 345, 14638 | |
| CORE_MLC_DEMAND_FILL_total_count, 345, 14638 | |
| CORE_MLC_PREF_FILL_count, 345, 491 | |
| CORE_MLC_PREF_FILL_total_count, 345, 491 | |
| CORE_MLC_PREF_FILL_USED_count, 346, 0 | |
| CORE_MLC_PREF_FILL_USED_total_count, 346, 0 | |
| CORE_MLC_PREF_FILL_PARTIAL_USED_count, 346, 491 | |
| CORE_MLC_PREF_FILL_PARTIAL_USED_total_count, 346, 491 | |
| CORE_MLC_PREF_FILL_NOT_USED_count, 346, 0 | |
| CORE_MLC_PREF_FILL_NOT_USED_total_count, 346, 0 | |
| CORE_L1_PREF_REQ_MISS_count, 347, 15026 | |
| CORE_L1_PREF_REQ_MISS_total_count, 347, 15026 | |
| CORE_L1_DEMAND_MISS_count, 347, 20 | |
| CORE_L1_DEMAND_MISS_total_count, 347, 20 | |
| CORE_L1_WB_MISS_count, 347, 97 | |
| CORE_L1_WB_MISS_total_count, 347, 97 | |
| CORE_L1_PREF_REQ_HIT_count, 348, 0 | |
| CORE_L1_PREF_REQ_HIT_total_count, 348, 0 | |
| CORE_L1_DEMAND_HIT_count, 348, 14521 | |
| CORE_L1_DEMAND_HIT_total_count, 348, 14521 | |
| CORE_L1_WB_HIT_count, 348, 681 | |
| CORE_L1_WB_HIT_total_count, 348, 681 | |
| CORE_L1_HIT_count, 349, 14521 | |
| CORE_L1_HIT_total_count, 349, 14521 | |
| CORE_L1_MISS_count, 349, 21 | |
| CORE_L1_MISS_total_count, 349, 21 | |
| CORE_L1_FILL_count, 350, 15140 | |
| CORE_L1_FILL_total_count, 350, 15140 | |
| CORE_L1_WB_FILL_count, 350, 0 | |
| CORE_L1_WB_FILL_total_count, 350, 0 | |
| CORE_L1_DEMAND_FILL_count, 351, 117 | |
| CORE_L1_DEMAND_FILL_total_count, 351, 117 | |
| CORE_L1_PREF_FILL_count, 351, 15023 | |
| CORE_L1_PREF_FILL_total_count, 351, 15023 | |
| CORE_L1_PREF_FILL_USED_count, 352, 14521 | |
| CORE_L1_PREF_FILL_USED_total_count, 352, 14521 | |
| CORE_L1_PREF_FILL_PARTIAL_USED_count, 352, 491 | |
| CORE_L1_PREF_FILL_PARTIAL_USED_total_count, 352, 491 | |
| CORE_L1_PREF_FILL_NOT_USED_count, 352, 11 | |
| CORE_L1_PREF_FILL_NOT_USED_total_count, 352, 11 | |
| CORE_L1_DEMAND_USED_POS0_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS0_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS1_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS1_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS2_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS2_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS3_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS3_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS4_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS4_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS5_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS5_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS6_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS6_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS7_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS7_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS8_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS8_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS9_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS9_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS10_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS10_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS11_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS11_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS12_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS12_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS13_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS13_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS14_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS14_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS15_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS15_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS16_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS16_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS17_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS17_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS18_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS18_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS19_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS19_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS20_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS20_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS21_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS21_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS22_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS22_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS23_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS23_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS24_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS24_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS25_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS25_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS26_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS26_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS27_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS27_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS28_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS28_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS29_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS29_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS30_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS30_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS31_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS31_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS32_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS32_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS33_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS33_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS34_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS34_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS35_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS35_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS36_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS36_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS37_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS37_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS38_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS38_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS39_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS39_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS40_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS40_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS41_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS41_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS42_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS42_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS43_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS43_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS44_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS44_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS45_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS45_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS46_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS46_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS47_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS47_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS48_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS48_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS49_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS49_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS50_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS50_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS51_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS51_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS52_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS52_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS53_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS53_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS54_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS54_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS55_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS55_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS56_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS56_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS57_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS57_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS58_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS58_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS59_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS59_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS60_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS60_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS61_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS61_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS62_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS62_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS63_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS63_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS64_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS64_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS65_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS65_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS66_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS66_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS67_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS67_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS68_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS68_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS69_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS69_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS70_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS70_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS71_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS71_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS72_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS72_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS73_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS73_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS74_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS74_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS75_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS75_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS76_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS76_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS77_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS77_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS78_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS78_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS79_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS79_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS80_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS80_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS81_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS81_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS82_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS82_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS83_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS83_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS84_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS84_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS85_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS85_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS86_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS86_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS87_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS87_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS88_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS88_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS89_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS89_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS90_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS90_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS91_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS91_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS92_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS92_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS93_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS93_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS94_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS94_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS95_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS95_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS96_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS96_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS97_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS97_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS98_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS98_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS99_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS99_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS100_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS100_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS101_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS101_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS102_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS102_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS103_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS103_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS104_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS104_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS105_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS105_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS106_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS106_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS107_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS107_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS108_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS108_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS109_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS109_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS110_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS110_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS111_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS111_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS112_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS112_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS113_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS113_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS114_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS114_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS115_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS115_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS116_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS116_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS117_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS117_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS118_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS118_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS119_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS119_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS120_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS120_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS121_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS121_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS122_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS122_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS123_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS123_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS124_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS124_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS125_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS125_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS126_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS126_total_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS127_count, 353, 0 | |
| CORE_L1_DEMAND_USED_POS127_total_count, 353, 0 | |
| CORE_L1_PREF_USED_POS0_count, 354, 0 | |
| CORE_L1_PREF_USED_POS0_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS1_count, 354, 0 | |
| CORE_L1_PREF_USED_POS1_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS2_count, 354, 0 | |
| CORE_L1_PREF_USED_POS2_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS3_count, 354, 0 | |
| CORE_L1_PREF_USED_POS3_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS4_count, 354, 0 | |
| CORE_L1_PREF_USED_POS4_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS5_count, 354, 0 | |
| CORE_L1_PREF_USED_POS5_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS6_count, 354, 0 | |
| CORE_L1_PREF_USED_POS6_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS7_count, 354, 0 | |
| CORE_L1_PREF_USED_POS7_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS8_count, 354, 0 | |
| CORE_L1_PREF_USED_POS8_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS9_count, 354, 0 | |
| CORE_L1_PREF_USED_POS9_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS10_count, 354, 0 | |
| CORE_L1_PREF_USED_POS10_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS11_count, 354, 0 | |
| CORE_L1_PREF_USED_POS11_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS12_count, 354, 0 | |
| CORE_L1_PREF_USED_POS12_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS13_count, 354, 0 | |
| CORE_L1_PREF_USED_POS13_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS14_count, 354, 0 | |
| CORE_L1_PREF_USED_POS14_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS15_count, 354, 0 | |
| CORE_L1_PREF_USED_POS15_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS16_count, 354, 0 | |
| CORE_L1_PREF_USED_POS16_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS17_count, 354, 0 | |
| CORE_L1_PREF_USED_POS17_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS18_count, 354, 0 | |
| CORE_L1_PREF_USED_POS18_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS19_count, 354, 0 | |
| CORE_L1_PREF_USED_POS19_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS20_count, 354, 0 | |
| CORE_L1_PREF_USED_POS20_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS21_count, 354, 0 | |
| CORE_L1_PREF_USED_POS21_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS22_count, 354, 0 | |
| CORE_L1_PREF_USED_POS22_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS23_count, 354, 0 | |
| CORE_L1_PREF_USED_POS23_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS24_count, 354, 0 | |
| CORE_L1_PREF_USED_POS24_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS25_count, 354, 0 | |
| CORE_L1_PREF_USED_POS25_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS26_count, 354, 0 | |
| CORE_L1_PREF_USED_POS26_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS27_count, 354, 0 | |
| CORE_L1_PREF_USED_POS27_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS28_count, 354, 0 | |
| CORE_L1_PREF_USED_POS28_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS29_count, 354, 0 | |
| CORE_L1_PREF_USED_POS29_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS30_count, 354, 0 | |
| CORE_L1_PREF_USED_POS30_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS31_count, 354, 0 | |
| CORE_L1_PREF_USED_POS31_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS32_count, 354, 0 | |
| CORE_L1_PREF_USED_POS32_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS33_count, 354, 0 | |
| CORE_L1_PREF_USED_POS33_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS34_count, 354, 0 | |
| CORE_L1_PREF_USED_POS34_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS35_count, 354, 0 | |
| CORE_L1_PREF_USED_POS35_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS36_count, 354, 0 | |
| CORE_L1_PREF_USED_POS36_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS37_count, 354, 0 | |
| CORE_L1_PREF_USED_POS37_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS38_count, 354, 0 | |
| CORE_L1_PREF_USED_POS38_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS39_count, 354, 0 | |
| CORE_L1_PREF_USED_POS39_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS40_count, 354, 0 | |
| CORE_L1_PREF_USED_POS40_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS41_count, 354, 0 | |
| CORE_L1_PREF_USED_POS41_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS42_count, 354, 0 | |
| CORE_L1_PREF_USED_POS42_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS43_count, 354, 0 | |
| CORE_L1_PREF_USED_POS43_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS44_count, 354, 0 | |
| CORE_L1_PREF_USED_POS44_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS45_count, 354, 0 | |
| CORE_L1_PREF_USED_POS45_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS46_count, 354, 0 | |
| CORE_L1_PREF_USED_POS46_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS47_count, 354, 0 | |
| CORE_L1_PREF_USED_POS47_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS48_count, 354, 0 | |
| CORE_L1_PREF_USED_POS48_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS49_count, 354, 0 | |
| CORE_L1_PREF_USED_POS49_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS50_count, 354, 0 | |
| CORE_L1_PREF_USED_POS50_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS51_count, 354, 0 | |
| CORE_L1_PREF_USED_POS51_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS52_count, 354, 0 | |
| CORE_L1_PREF_USED_POS52_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS53_count, 354, 0 | |
| CORE_L1_PREF_USED_POS53_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS54_count, 354, 0 | |
| CORE_L1_PREF_USED_POS54_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS55_count, 354, 0 | |
| CORE_L1_PREF_USED_POS55_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS56_count, 354, 0 | |
| CORE_L1_PREF_USED_POS56_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS57_count, 354, 0 | |
| CORE_L1_PREF_USED_POS57_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS58_count, 354, 0 | |
| CORE_L1_PREF_USED_POS58_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS59_count, 354, 0 | |
| CORE_L1_PREF_USED_POS59_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS60_count, 354, 0 | |
| CORE_L1_PREF_USED_POS60_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS61_count, 354, 0 | |
| CORE_L1_PREF_USED_POS61_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS62_count, 354, 0 | |
| CORE_L1_PREF_USED_POS62_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS63_count, 354, 0 | |
| CORE_L1_PREF_USED_POS63_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS64_count, 354, 0 | |
| CORE_L1_PREF_USED_POS64_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS65_count, 354, 0 | |
| CORE_L1_PREF_USED_POS65_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS66_count, 354, 0 | |
| CORE_L1_PREF_USED_POS66_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS67_count, 354, 0 | |
| CORE_L1_PREF_USED_POS67_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS68_count, 354, 0 | |
| CORE_L1_PREF_USED_POS68_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS69_count, 354, 0 | |
| CORE_L1_PREF_USED_POS69_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS70_count, 354, 0 | |
| CORE_L1_PREF_USED_POS70_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS71_count, 354, 0 | |
| CORE_L1_PREF_USED_POS71_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS72_count, 354, 0 | |
| CORE_L1_PREF_USED_POS72_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS73_count, 354, 0 | |
| CORE_L1_PREF_USED_POS73_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS74_count, 354, 0 | |
| CORE_L1_PREF_USED_POS74_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS75_count, 354, 0 | |
| CORE_L1_PREF_USED_POS75_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS76_count, 354, 0 | |
| CORE_L1_PREF_USED_POS76_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS77_count, 354, 0 | |
| CORE_L1_PREF_USED_POS77_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS78_count, 354, 0 | |
| CORE_L1_PREF_USED_POS78_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS79_count, 354, 0 | |
| CORE_L1_PREF_USED_POS79_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS80_count, 354, 0 | |
| CORE_L1_PREF_USED_POS80_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS81_count, 354, 0 | |
| CORE_L1_PREF_USED_POS81_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS82_count, 354, 0 | |
| CORE_L1_PREF_USED_POS82_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS83_count, 354, 0 | |
| CORE_L1_PREF_USED_POS83_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS84_count, 354, 0 | |
| CORE_L1_PREF_USED_POS84_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS85_count, 354, 0 | |
| CORE_L1_PREF_USED_POS85_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS86_count, 354, 0 | |
| CORE_L1_PREF_USED_POS86_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS87_count, 354, 0 | |
| CORE_L1_PREF_USED_POS87_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS88_count, 354, 0 | |
| CORE_L1_PREF_USED_POS88_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS89_count, 354, 0 | |
| CORE_L1_PREF_USED_POS89_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS90_count, 354, 0 | |
| CORE_L1_PREF_USED_POS90_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS91_count, 354, 0 | |
| CORE_L1_PREF_USED_POS91_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS92_count, 354, 0 | |
| CORE_L1_PREF_USED_POS92_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS93_count, 354, 0 | |
| CORE_L1_PREF_USED_POS93_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS94_count, 354, 0 | |
| CORE_L1_PREF_USED_POS94_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS95_count, 354, 0 | |
| CORE_L1_PREF_USED_POS95_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS96_count, 354, 0 | |
| CORE_L1_PREF_USED_POS96_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS97_count, 354, 0 | |
| CORE_L1_PREF_USED_POS97_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS98_count, 354, 0 | |
| CORE_L1_PREF_USED_POS98_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS99_count, 354, 0 | |
| CORE_L1_PREF_USED_POS99_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS100_count, 354, 0 | |
| CORE_L1_PREF_USED_POS100_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS101_count, 354, 0 | |
| CORE_L1_PREF_USED_POS101_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS102_count, 354, 0 | |
| CORE_L1_PREF_USED_POS102_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS103_count, 354, 0 | |
| CORE_L1_PREF_USED_POS103_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS104_count, 354, 0 | |
| CORE_L1_PREF_USED_POS104_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS105_count, 354, 0 | |
| CORE_L1_PREF_USED_POS105_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS106_count, 354, 0 | |
| CORE_L1_PREF_USED_POS106_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS107_count, 354, 0 | |
| CORE_L1_PREF_USED_POS107_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS108_count, 354, 0 | |
| CORE_L1_PREF_USED_POS108_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS109_count, 354, 0 | |
| CORE_L1_PREF_USED_POS109_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS110_count, 354, 0 | |
| CORE_L1_PREF_USED_POS110_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS111_count, 354, 0 | |
| CORE_L1_PREF_USED_POS111_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS112_count, 354, 0 | |
| CORE_L1_PREF_USED_POS112_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS113_count, 354, 0 | |
| CORE_L1_PREF_USED_POS113_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS114_count, 354, 0 | |
| CORE_L1_PREF_USED_POS114_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS115_count, 354, 0 | |
| CORE_L1_PREF_USED_POS115_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS116_count, 354, 0 | |
| CORE_L1_PREF_USED_POS116_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS117_count, 354, 0 | |
| CORE_L1_PREF_USED_POS117_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS118_count, 354, 0 | |
| CORE_L1_PREF_USED_POS118_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS119_count, 354, 0 | |
| CORE_L1_PREF_USED_POS119_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS120_count, 354, 0 | |
| CORE_L1_PREF_USED_POS120_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS121_count, 354, 0 | |
| CORE_L1_PREF_USED_POS121_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS122_count, 354, 0 | |
| CORE_L1_PREF_USED_POS122_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS123_count, 354, 0 | |
| CORE_L1_PREF_USED_POS123_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS124_count, 354, 0 | |
| CORE_L1_PREF_USED_POS124_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS125_count, 354, 0 | |
| CORE_L1_PREF_USED_POS125_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS126_count, 354, 0 | |
| CORE_L1_PREF_USED_POS126_total_count, 354, 0 | |
| CORE_L1_PREF_USED_POS127_count, 354, 0 | |
| CORE_L1_PREF_USED_POS127_total_count, 354, 0 | |
| CORE_TOTAL_SETS_ALL_INTERVALS_count, 0, 0 | |
| CORE_TOTAL_SETS_ALL_INTERVALS_total_count, 0, 0 | |
| CORE_L1_AVG_NUM_WAYS_count, 0, 0 | |
| CORE_L1_AVG_NUM_WAYS_pct, 0, -nan | |
| CORE_L1_AVG_NUM_WAYS_total_count, 0, 0 | |
| CORE_L1_AVG_NUM_WAYS_total_pct, 0, -nan | |
| L1_PARTITION_INTERVALS_count, 0, 0 | |
| L1_PARTITION_INTERVALS_total_count, 0, 0 | |
| NORESET_L1_PARTITION_count, 0, 0 | |
| NORESET_L1_PARTITION_total_count, 0, 0 | |
| L1_SHADOW_ACCESS_count, 0, 0 | |
| L1_SHADOW_ACCESS_total_count, 0, 0 | |
| L1_SHADOW_ACCESS_STALLING_count, 0, 0 | |
| L1_SHADOW_ACCESS_STALLING_total_count, 0, 0 | |
| L1_SHADOW_ACCESS_DEMAND_count, 0, 0 | |
| L1_SHADOW_ACCESS_DEMAND_total_count, 0, 0 | |
| L1_SHADOW_HIT_count, 0, 0 | |
| L1_SHADOW_HIT_total_count, 0, 0 | |
| L1_SHADOW_HIT_STALLING_count, 0, 0 | |
| L1_SHADOW_HIT_STALLING_total_count, 0, 0 | |
| L1_SHADOW_HIT_DEMAND_count, 0, 0 | |
| L1_SHADOW_HIT_DEMAND_total_count, 0, 0 | |
| L1_SHADOW_UNTIMELY_HIT_count, 0, 0 | |
| L1_SHADOW_UNTIMELY_HIT_total_count, 0, 0 | |
| L1_SHADOW_UNTIMELY_HIT_STALLING_count, 0, 0 | |
| L1_SHADOW_UNTIMELY_HIT_STALLING_total_count, 0, 0 | |
| L1_SHADOW_UNTIMELY_HIT_DEMAND_count, 0, 0 | |
| L1_SHADOW_UNTIMELY_HIT_DEMAND_total_count, 0, 0 | |
| L1_SHADOW_HIT_POS0_count, 355, 0 | |
| L1_SHADOW_HIT_POS0_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS1_count, 355, 0 | |
| L1_SHADOW_HIT_POS1_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS2_count, 355, 0 | |
| L1_SHADOW_HIT_POS2_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS3_count, 355, 0 | |
| L1_SHADOW_HIT_POS3_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS4_count, 355, 0 | |
| L1_SHADOW_HIT_POS4_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS5_count, 355, 0 | |
| L1_SHADOW_HIT_POS5_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS6_count, 355, 0 | |
| L1_SHADOW_HIT_POS6_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS7_count, 355, 0 | |
| L1_SHADOW_HIT_POS7_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS8_count, 355, 0 | |
| L1_SHADOW_HIT_POS8_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS9_count, 355, 0 | |
| L1_SHADOW_HIT_POS9_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS10_count, 355, 0 | |
| L1_SHADOW_HIT_POS10_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS11_count, 355, 0 | |
| L1_SHADOW_HIT_POS11_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS12_count, 355, 0 | |
| L1_SHADOW_HIT_POS12_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS13_count, 355, 0 | |
| L1_SHADOW_HIT_POS13_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS14_count, 355, 0 | |
| L1_SHADOW_HIT_POS14_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS15_count, 355, 0 | |
| L1_SHADOW_HIT_POS15_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS16_count, 355, 0 | |
| L1_SHADOW_HIT_POS16_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS17_count, 355, 0 | |
| L1_SHADOW_HIT_POS17_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS18_count, 355, 0 | |
| L1_SHADOW_HIT_POS18_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS19_count, 355, 0 | |
| L1_SHADOW_HIT_POS19_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS20_count, 355, 0 | |
| L1_SHADOW_HIT_POS20_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS21_count, 355, 0 | |
| L1_SHADOW_HIT_POS21_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS22_count, 355, 0 | |
| L1_SHADOW_HIT_POS22_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS23_count, 355, 0 | |
| L1_SHADOW_HIT_POS23_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS24_count, 355, 0 | |
| L1_SHADOW_HIT_POS24_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS25_count, 355, 0 | |
| L1_SHADOW_HIT_POS25_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS26_count, 355, 0 | |
| L1_SHADOW_HIT_POS26_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS27_count, 355, 0 | |
| L1_SHADOW_HIT_POS27_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS28_count, 355, 0 | |
| L1_SHADOW_HIT_POS28_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS29_count, 355, 0 | |
| L1_SHADOW_HIT_POS29_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS30_count, 355, 0 | |
| L1_SHADOW_HIT_POS30_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS31_count, 355, 0 | |
| L1_SHADOW_HIT_POS31_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS32_count, 355, 0 | |
| L1_SHADOW_HIT_POS32_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS33_count, 355, 0 | |
| L1_SHADOW_HIT_POS33_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS34_count, 355, 0 | |
| L1_SHADOW_HIT_POS34_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS35_count, 355, 0 | |
| L1_SHADOW_HIT_POS35_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS36_count, 355, 0 | |
| L1_SHADOW_HIT_POS36_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS37_count, 355, 0 | |
| L1_SHADOW_HIT_POS37_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS38_count, 355, 0 | |
| L1_SHADOW_HIT_POS38_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS39_count, 355, 0 | |
| L1_SHADOW_HIT_POS39_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS40_count, 355, 0 | |
| L1_SHADOW_HIT_POS40_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS41_count, 355, 0 | |
| L1_SHADOW_HIT_POS41_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS42_count, 355, 0 | |
| L1_SHADOW_HIT_POS42_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS43_count, 355, 0 | |
| L1_SHADOW_HIT_POS43_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS44_count, 355, 0 | |
| L1_SHADOW_HIT_POS44_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS45_count, 355, 0 | |
| L1_SHADOW_HIT_POS45_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS46_count, 355, 0 | |
| L1_SHADOW_HIT_POS46_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS47_count, 355, 0 | |
| L1_SHADOW_HIT_POS47_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS48_count, 355, 0 | |
| L1_SHADOW_HIT_POS48_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS49_count, 355, 0 | |
| L1_SHADOW_HIT_POS49_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS50_count, 355, 0 | |
| L1_SHADOW_HIT_POS50_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS51_count, 355, 0 | |
| L1_SHADOW_HIT_POS51_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS52_count, 355, 0 | |
| L1_SHADOW_HIT_POS52_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS53_count, 355, 0 | |
| L1_SHADOW_HIT_POS53_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS54_count, 355, 0 | |
| L1_SHADOW_HIT_POS54_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS55_count, 355, 0 | |
| L1_SHADOW_HIT_POS55_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS56_count, 355, 0 | |
| L1_SHADOW_HIT_POS56_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS57_count, 355, 0 | |
| L1_SHADOW_HIT_POS57_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS58_count, 355, 0 | |
| L1_SHADOW_HIT_POS58_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS59_count, 355, 0 | |
| L1_SHADOW_HIT_POS59_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS60_count, 355, 0 | |
| L1_SHADOW_HIT_POS60_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS61_count, 355, 0 | |
| L1_SHADOW_HIT_POS61_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS62_count, 355, 0 | |
| L1_SHADOW_HIT_POS62_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS63_count, 355, 0 | |
| L1_SHADOW_HIT_POS63_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS64_count, 355, 0 | |
| L1_SHADOW_HIT_POS64_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS65_count, 355, 0 | |
| L1_SHADOW_HIT_POS65_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS66_count, 355, 0 | |
| L1_SHADOW_HIT_POS66_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS67_count, 355, 0 | |
| L1_SHADOW_HIT_POS67_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS68_count, 355, 0 | |
| L1_SHADOW_HIT_POS68_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS69_count, 355, 0 | |
| L1_SHADOW_HIT_POS69_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS70_count, 355, 0 | |
| L1_SHADOW_HIT_POS70_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS71_count, 355, 0 | |
| L1_SHADOW_HIT_POS71_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS72_count, 355, 0 | |
| L1_SHADOW_HIT_POS72_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS73_count, 355, 0 | |
| L1_SHADOW_HIT_POS73_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS74_count, 355, 0 | |
| L1_SHADOW_HIT_POS74_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS75_count, 355, 0 | |
| L1_SHADOW_HIT_POS75_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS76_count, 355, 0 | |
| L1_SHADOW_HIT_POS76_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS77_count, 355, 0 | |
| L1_SHADOW_HIT_POS77_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS78_count, 355, 0 | |
| L1_SHADOW_HIT_POS78_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS79_count, 355, 0 | |
| L1_SHADOW_HIT_POS79_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS80_count, 355, 0 | |
| L1_SHADOW_HIT_POS80_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS81_count, 355, 0 | |
| L1_SHADOW_HIT_POS81_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS82_count, 355, 0 | |
| L1_SHADOW_HIT_POS82_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS83_count, 355, 0 | |
| L1_SHADOW_HIT_POS83_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS84_count, 355, 0 | |
| L1_SHADOW_HIT_POS84_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS85_count, 355, 0 | |
| L1_SHADOW_HIT_POS85_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS86_count, 355, 0 | |
| L1_SHADOW_HIT_POS86_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS87_count, 355, 0 | |
| L1_SHADOW_HIT_POS87_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS88_count, 355, 0 | |
| L1_SHADOW_HIT_POS88_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS89_count, 355, 0 | |
| L1_SHADOW_HIT_POS89_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS90_count, 355, 0 | |
| L1_SHADOW_HIT_POS90_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS91_count, 355, 0 | |
| L1_SHADOW_HIT_POS91_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS92_count, 355, 0 | |
| L1_SHADOW_HIT_POS92_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS93_count, 355, 0 | |
| L1_SHADOW_HIT_POS93_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS94_count, 355, 0 | |
| L1_SHADOW_HIT_POS94_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS95_count, 355, 0 | |
| L1_SHADOW_HIT_POS95_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS96_count, 355, 0 | |
| L1_SHADOW_HIT_POS96_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS97_count, 355, 0 | |
| L1_SHADOW_HIT_POS97_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS98_count, 355, 0 | |
| L1_SHADOW_HIT_POS98_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS99_count, 355, 0 | |
| L1_SHADOW_HIT_POS99_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS100_count, 355, 0 | |
| L1_SHADOW_HIT_POS100_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS101_count, 355, 0 | |
| L1_SHADOW_HIT_POS101_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS102_count, 355, 0 | |
| L1_SHADOW_HIT_POS102_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS103_count, 355, 0 | |
| L1_SHADOW_HIT_POS103_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS104_count, 355, 0 | |
| L1_SHADOW_HIT_POS104_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS105_count, 355, 0 | |
| L1_SHADOW_HIT_POS105_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS106_count, 355, 0 | |
| L1_SHADOW_HIT_POS106_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS107_count, 355, 0 | |
| L1_SHADOW_HIT_POS107_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS108_count, 355, 0 | |
| L1_SHADOW_HIT_POS108_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS109_count, 355, 0 | |
| L1_SHADOW_HIT_POS109_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS110_count, 355, 0 | |
| L1_SHADOW_HIT_POS110_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS111_count, 355, 0 | |
| L1_SHADOW_HIT_POS111_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS112_count, 355, 0 | |
| L1_SHADOW_HIT_POS112_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS113_count, 355, 0 | |
| L1_SHADOW_HIT_POS113_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS114_count, 355, 0 | |
| L1_SHADOW_HIT_POS114_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS115_count, 355, 0 | |
| L1_SHADOW_HIT_POS115_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS116_count, 355, 0 | |
| L1_SHADOW_HIT_POS116_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS117_count, 355, 0 | |
| L1_SHADOW_HIT_POS117_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS118_count, 355, 0 | |
| L1_SHADOW_HIT_POS118_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS119_count, 355, 0 | |
| L1_SHADOW_HIT_POS119_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS120_count, 355, 0 | |
| L1_SHADOW_HIT_POS120_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS121_count, 355, 0 | |
| L1_SHADOW_HIT_POS121_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS122_count, 355, 0 | |
| L1_SHADOW_HIT_POS122_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS123_count, 355, 0 | |
| L1_SHADOW_HIT_POS123_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS124_count, 355, 0 | |
| L1_SHADOW_HIT_POS124_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS125_count, 355, 0 | |
| L1_SHADOW_HIT_POS125_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS126_count, 355, 0 | |
| L1_SHADOW_HIT_POS126_total_count, 355, 0 | |
| L1_SHADOW_HIT_POS127_count, 355, 0 | |
| L1_SHADOW_HIT_POS127_total_count, 355, 0 | |
| L1_SHADOW_STALLING_HIT_POS0_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS0_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS1_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS1_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS2_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS2_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS3_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS3_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS4_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS4_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS5_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS5_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS6_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS6_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS7_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS7_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS8_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS8_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS9_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS9_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS10_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS10_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS11_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS11_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS12_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS12_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS13_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS13_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS14_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS14_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS15_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS15_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS16_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS16_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS17_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS17_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS18_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS18_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS19_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS19_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS20_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS20_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS21_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS21_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS22_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS22_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS23_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS23_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS24_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS24_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS25_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS25_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS26_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS26_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS27_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS27_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS28_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS28_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS29_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS29_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS30_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS30_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS31_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS31_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS32_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS32_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS33_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS33_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS34_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS34_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS35_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS35_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS36_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS36_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS37_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS37_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS38_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS38_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS39_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS39_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS40_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS40_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS41_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS41_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS42_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS42_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS43_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS43_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS44_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS44_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS45_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS45_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS46_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS46_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS47_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS47_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS48_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS48_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS49_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS49_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS50_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS50_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS51_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS51_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS52_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS52_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS53_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS53_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS54_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS54_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS55_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS55_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS56_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS56_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS57_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS57_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS58_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS58_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS59_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS59_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS60_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS60_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS61_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS61_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS62_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS62_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS63_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS63_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS64_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS64_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS65_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS65_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS66_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS66_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS67_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS67_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS68_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS68_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS69_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS69_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS70_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS70_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS71_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS71_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS72_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS72_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS73_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS73_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS74_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS74_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS75_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS75_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS76_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS76_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS77_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS77_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS78_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS78_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS79_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS79_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS80_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS80_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS81_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS81_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS82_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS82_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS83_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS83_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS84_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS84_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS85_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS85_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS86_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS86_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS87_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS87_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS88_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS88_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS89_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS89_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS90_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS90_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS91_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS91_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS92_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS92_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS93_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS93_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS94_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS94_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS95_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS95_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS96_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS96_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS97_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS97_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS98_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS98_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS99_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS99_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS100_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS100_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS101_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS101_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS102_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS102_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS103_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS103_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS104_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS104_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS105_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS105_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS106_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS106_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS107_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS107_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS108_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS108_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS109_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS109_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS110_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS110_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS111_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS111_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS112_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS112_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS113_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS113_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS114_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS114_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS115_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS115_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS116_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS116_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS117_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS117_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS118_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS118_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS119_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS119_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS120_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS120_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS121_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS121_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS122_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS122_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS123_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS123_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS124_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS124_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS125_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS125_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS126_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS126_total_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS127_count, 356, 0 | |
| L1_SHADOW_STALLING_HIT_POS127_total_count, 356, 0 | |
| L1_SHADOW_DEMAND_HIT_POS0_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS0_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS1_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS1_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS2_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS2_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS3_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS3_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS4_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS4_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS5_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS5_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS6_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS6_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS7_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS7_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS8_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS8_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS9_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS9_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS10_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS10_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS11_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS11_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS12_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS12_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS13_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS13_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS14_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS14_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS15_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS15_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS16_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS16_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS17_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS17_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS18_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS18_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS19_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS19_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS20_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS20_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS21_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS21_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS22_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS22_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS23_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS23_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS24_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS24_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS25_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS25_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS26_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS26_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS27_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS27_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS28_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS28_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS29_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS29_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS30_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS30_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS31_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS31_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS32_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS32_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS33_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS33_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS34_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS34_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS35_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS35_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS36_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS36_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS37_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS37_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS38_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS38_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS39_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS39_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS40_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS40_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS41_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS41_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS42_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS42_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS43_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS43_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS44_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS44_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS45_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS45_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS46_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS46_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS47_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS47_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS48_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS48_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS49_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS49_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS50_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS50_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS51_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS51_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS52_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS52_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS53_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS53_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS54_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS54_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS55_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS55_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS56_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS56_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS57_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS57_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS58_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS58_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS59_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS59_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS60_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS60_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS61_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS61_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS62_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS62_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS63_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS63_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS64_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS64_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS65_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS65_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS66_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS66_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS67_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS67_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS68_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS68_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS69_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS69_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS70_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS70_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS71_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS71_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS72_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS72_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS73_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS73_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS74_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS74_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS75_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS75_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS76_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS76_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS77_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS77_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS78_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS78_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS79_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS79_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS80_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS80_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS81_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS81_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS82_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS82_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS83_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS83_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS84_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS84_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS85_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS85_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS86_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS86_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS87_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS87_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS88_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS88_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS89_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS89_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS90_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS90_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS91_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS91_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS92_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS92_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS93_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS93_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS94_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS94_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS95_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS95_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS96_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS96_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS97_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS97_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS98_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS98_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS99_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS99_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS100_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS100_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS101_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS101_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS102_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS102_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS103_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS103_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS104_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS104_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS105_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS105_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS106_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS106_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS107_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS107_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS108_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS108_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS109_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS109_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS110_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS110_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS111_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS111_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS112_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS112_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS113_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS113_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS114_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS114_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS115_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS115_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS116_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS116_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS117_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS117_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS118_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS118_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS119_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS119_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS120_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS120_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS121_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS121_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS122_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS122_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS123_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS123_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS124_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS124_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS125_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS125_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS126_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS126_total_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS127_count, 357, 0 | |
| L1_SHADOW_DEMAND_HIT_POS127_total_count, 357, 0 | |
| CORE_PREF_MLC_SENT_count, 0, 0 | |
| CORE_PREF_MLC_SENT_total_count, 0, 0 | |
| CORE_PREF_MLC_USED_count, 358, 0 | |
| CORE_PREF_MLC_USED_total_count, 358, 0 | |
| CORE_PREF_MLC_PARTIAL_USED_count, 358, 491 | |
| CORE_PREF_MLC_PARTIAL_USED_total_count, 358, 491 | |
| CORE_PREF_MLC_NOT_USED_count, 358, 0 | |
| CORE_PREF_MLC_NOT_USED_total_count, 358, 0 | |
| CORE_PREF_MLC_DROPPED_count, 358, 0 | |
| CORE_PREF_MLC_DROPPED_total_count, 358, 0 | |
| CORE_PREF_L1_SENT_count, 0, 15026 | |
| CORE_PREF_L1_SENT_total_count, 0, 15026 | |
| CORE_PREF_L1_USED_count, 359, 14521 | |
| CORE_PREF_L1_USED_total_count, 359, 14521 | |
| CORE_PREF_L1_PARTIAL_USED_count, 359, 491 | |
| CORE_PREF_L1_PARTIAL_USED_total_count, 359, 491 | |
| CORE_PREF_L1_NOT_USED_count, 359, 11 | |
| CORE_PREF_L1_NOT_USED_total_count, 359, 11 | |
| CORE_PREF_L1_DROPPED_count, 359, 0 | |
| CORE_PREF_L1_DROPPED_total_count, 359, 0 | |
| TOTAL_MEM_LATENCY_count, 0, 2039840 | |
| TOTAL_MEM_LATENCY_pct, 0, 134.732 | |
| TOTAL_MEM_LATENCY_total_count, 0, 2039840 | |
| TOTAL_MEM_LATENCY_total_pct, 0, 134.732 | |
| TOTAL_MEM_LATENCY_DEMAND_count, 0, 591024 | |
| TOTAL_MEM_LATENCY_DEMAND_pct, 0, 5051.487 | |
| TOTAL_MEM_LATENCY_DEMAND_total_count, 0, 591024 | |
| TOTAL_MEM_LATENCY_DEMAND_total_pct, 0, 5051.487 | |
| TOTAL_MEM_LATENCY_PREF_count, 0, 1448816 | |
| TOTAL_MEM_LATENCY_PREF_pct, 0, 96.440 | |
| TOTAL_MEM_LATENCY_PREF_total_count, 0, 1448816 | |
| TOTAL_MEM_LATENCY_PREF_total_pct, 0, 96.440 | |
| CORE_MEM_LATENCY_count, 0, 2039840 | |
| CORE_MEM_LATENCY_pct, 0, 134.732 | |
| CORE_MEM_LATENCY_total_count, 0, 2039840 | |
| CORE_MEM_LATENCY_total_pct, 0, 134.732 | |
| CORE_MEM_LATENCY_DEMAND_count, 0, 591024 | |
| CORE_MEM_LATENCY_DEMAND_pct, 0, 5051.487 | |
| CORE_MEM_LATENCY_DEMAND_total_count, 0, 591024 | |
| CORE_MEM_LATENCY_DEMAND_total_pct, 0, 5051.487 | |
| CORE_MEM_LATENCY_PREF_count, 0, 1448816 | |
| CORE_MEM_LATENCY_PREF_pct, 0, 96.440 | |
| CORE_MEM_LATENCY_PREF_total_count, 0, 1448816 | |
| CORE_MEM_LATENCY_PREF_total_pct, 0, 96.440 | |
| CORE_MEM_LATENCY_IFETCH_count, 360, 967 | |
| CORE_MEM_LATENCY_IFETCH_total_count, 360, 967 | |
| CORE_MEM_LATENCY_DFETCH_count, 360, 351273 | |
| CORE_MEM_LATENCY_DFETCH_total_count, 360, 351273 | |
| CORE_MEM_LATENCY_DSTORE_count, 360, 162 | |
| CORE_MEM_LATENCY_DSTORE_total_count, 360, 162 | |
| CORE_MEM_LATENCY_IPRF_count, 360, 0 | |
| CORE_MEM_LATENCY_IPRF_total_count, 360, 0 | |
| CORE_MEM_LATENCY_UOCPRF_count, 360, 0 | |
| CORE_MEM_LATENCY_UOCPRF_total_count, 360, 0 | |
| CORE_MEM_LATENCY_FDIPPRF_count, 360, 29119 | |
| CORE_MEM_LATENCY_FDIPPRF_total_count, 360, 29119 | |
| CORE_MEM_LATENCY_DPRF_count, 360, 0 | |
| CORE_MEM_LATENCY_DPRF_total_count, 360, 0 | |
| CORE_MEM_LATENCY_WB_count, 360, 998782 | |
| CORE_MEM_LATENCY_WB_total_count, 360, 998782 | |
| CORE_MEM_LATENCY_WB_NODIRTY_count, 360, 0 | |
| CORE_MEM_LATENCY_WB_NODIRTY_total_count, 360, 0 | |
| CORE_MEM_STALLING_LATENCY_IFETCH_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_IFETCH_total_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_DFETCH_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_DFETCH_total_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_DSTORE_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_DSTORE_total_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_IPRF_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_IPRF_total_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_DPRF_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_DPRF_total_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_WB_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_WB_total_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_WB_NODIRTY_count, 361, 0 | |
| CORE_MEM_STALLING_LATENCY_WB_NODIRTY_total_count, 361, 0 | |
| TOTAL_L1_MISS_LATENCY_count, 0, 1380303 | |
| TOTAL_L1_MISS_LATENCY_pct, 0, 91.169 | |
| TOTAL_L1_MISS_LATENCY_total_count, 0, 1380303 | |
| TOTAL_L1_MISS_LATENCY_total_pct, 0, 91.169 | |
| TOTAL_L1_MISS_LATENCY_DEMAND_count, 0, 31891 | |
| TOTAL_L1_MISS_LATENCY_DEMAND_pct, 0, 272.573 | |
| TOTAL_L1_MISS_LATENCY_DEMAND_total_count, 0, 31891 | |
| TOTAL_L1_MISS_LATENCY_DEMAND_total_pct, 0, 272.573 | |
| TOTAL_L1_MISS_LATENCY_PREF_count, 0, 1348412 | |
| TOTAL_L1_MISS_LATENCY_PREF_pct, 0, 89.757 | |
| TOTAL_L1_MISS_LATENCY_PREF_total_count, 0, 1348412 | |
| TOTAL_L1_MISS_LATENCY_PREF_total_pct, 0, 89.757 | |
| CORE_L1_MISS_LATENCY_count, 0, 1380303 | |
| CORE_L1_MISS_LATENCY_pct, 0, 91.169 | |
| CORE_L1_MISS_LATENCY_total_count, 0, 1380303 | |
| CORE_L1_MISS_LATENCY_total_pct, 0, 91.169 | |
| CORE_L1_MISS_LATENCY_DEMAND_count, 0, 31891 | |
| CORE_L1_MISS_LATENCY_DEMAND_pct, 0, 272.573 | |
| CORE_L1_MISS_LATENCY_DEMAND_total_count, 0, 31891 | |
| CORE_L1_MISS_LATENCY_DEMAND_total_pct, 0, 272.573 | |
| CORE_L1_MISS_LATENCY_PREF_count, 0, 1348412 | |
| CORE_L1_MISS_LATENCY_PREF_pct, 0, 89.757 | |
| CORE_L1_MISS_LATENCY_PREF_total_count, 0, 1348412 | |
| CORE_L1_MISS_LATENCY_PREF_total_pct, 0, 89.757 | |
| CORE_EVICTED_L1_DEMAND_count, 362, 0 | |
| CORE_EVICTED_L1_DEMAND_total_count, 362, 0 | |
| CORE_EVICTED_L1_PREF_USED_count, 362, 0 | |
| CORE_EVICTED_L1_PREF_USED_total_count, 362, 0 | |
| CORE_EVICTED_L1_PREF_NOT_USED_count, 362, 0 | |
| CORE_EVICTED_L1_PREF_NOT_USED_total_count, 362, 0 | |
| CORE_EVICTED_MLC_DEMAND_count, 363, 793 | |
| CORE_EVICTED_MLC_DEMAND_total_count, 363, 793 | |
| CORE_EVICTED_MLC_PREF_USED_count, 363, 0 | |
| CORE_EVICTED_MLC_PREF_USED_total_count, 363, 0 | |
| CORE_EVICTED_MLC_PREF_NOT_USED_count, 363, 0 | |
| CORE_EVICTED_MLC_PREF_NOT_USED_total_count, 363, 0 | |
| CORE_MEM_LATENCY_AVE_DEMAND_count, 0, 1183 | |
| CORE_MEM_LATENCY_AVE_DEMAND_pct, 0, inf | |
| CORE_MEM_LATENCY_AVE_DEMAND_total_count, 0, 1183 | |
| CORE_MEM_LATENCY_AVE_DEMAND_total_pct, 0, inf | |
| CORE_MEM_LATENCY_AVE_PREF_USED_count, 0, 0 | |
| CORE_MEM_LATENCY_AVE_PREF_USED_pct, 0, -nan | |
| CORE_MEM_LATENCY_AVE_PREF_USED_total_count, 0, 0 | |
| CORE_MEM_LATENCY_AVE_PREF_USED_total_pct, 0, -nan | |
| CORE_MEM_LATENCY_AVE_PREF_NOT_USED_count, 0, 0 | |
| CORE_MEM_LATENCY_AVE_PREF_NOT_USED_pct, 0, -nan | |
| CORE_MEM_LATENCY_AVE_PREF_NOT_USED_total_count, 0, 0 | |
| CORE_MEM_LATENCY_AVE_PREF_NOT_USED_total_pct, 0, -nan | |
| DRAM_LATENCY_count, 0, 0 | |
| DRAM_LATENCY_total_count, 0, 0 | |
| TOTAL_DRAM_LATENCY_count, 0, 0 | |
| TOTAL_DRAM_LATENCY_total_count, 0, 0 | |
| DRAM_CLOSED_PAGE_POLICY_CMD_count, 0, 0 | |
| DRAM_CLOSED_PAGE_POLICY_CMD_total_count, 0, 0 | |
| DRAM_ACTIVATE_STALLING_count, 0, 0 | |
| DRAM_ACTIVATE_STALLING_total_count, 0, 0 | |
| DRAM_PRECHARGE_STALLING_count, 0, 0 | |
| DRAM_PRECHARGE_STALLING_total_count, 0, 0 | |
| DRAM_PRECHARGE_STALLING_WAIT_CYCLES_count, 0, 0 | |
| DRAM_PRECHARGE_STALLING_WAIT_CYCLES_total_count, 0, 0 | |
| L1_STAY_DEMAND_count, 0, 0 | |
| L1_STAY_DEMAND_pct, 0, -nan | |
| L1_STAY_DEMAND_total_count, 0, 0 | |
| L1_STAY_DEMAND_total_pct, 0, -nan | |
| L1_STAY_PREF_USED_count, 0, 0 | |
| L1_STAY_PREF_USED_pct, 0, -nan | |
| L1_STAY_PREF_USED_total_count, 0, 0 | |
| L1_STAY_PREF_USED_total_pct, 0, -nan | |
| L1_STAY_PREF_NOT_USED_count, 0, 0 | |
| L1_STAY_PREF_NOT_USED_pct, 0, -nan | |
| L1_STAY_PREF_NOT_USED_total_count, 0, 0 | |
| L1_STAY_PREF_NOT_USED_total_pct, 0, -nan | |
| TOTAL_DATA_MISS_LATENCY_count, 0, 976629 | |
| TOTAL_DATA_MISS_LATENCY_total_count, 0, 976629 | |
| TOTAL_DATA_MISS_COUNT_count, 0, 15529 | |
| TOTAL_DATA_MISS_COUNT_total_count, 0, 15529 | |
| CORE_PREF_L1_NOT_USED_LATENCY200_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY200_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY400_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY400_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY600_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY600_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY800_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY800_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1000_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1000_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1200_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1200_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1400_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1400_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1600_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1600_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1600MORE_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_LATENCY1600MORE_total_count, 364, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_1_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_1_total_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_2_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_2_total_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_4_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_4_total_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_8_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_8_total_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_16_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_16_total_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_32_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_32_total_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_MORE_count, 365, 0 | |
| CORE_PREF_L1_NOT_USED_DISTANCE_MORE_total_count, 365, 0 | |
| CORE_PREF_L1_USED_LATENCY200_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY200_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY400_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY400_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY600_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY600_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY800_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY800_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1000_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1000_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1200_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1200_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1400_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1400_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1600_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1600_total_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1600MORE_count, 366, 0 | |
| CORE_PREF_L1_USED_LATENCY1600MORE_total_count, 366, 0 | |
| CORE_PREF_L1_USED_DISTANCE_1_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_1_total_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_2_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_2_total_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_4_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_4_total_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_8_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_8_total_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_16_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_16_total_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_32_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_32_total_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_MORE_count, 367, 0 | |
| CORE_PREF_L1_USED_DISTANCE_MORE_total_count, 367, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY300_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY300_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY400_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY400_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY500_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY500_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY600_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY600_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY700_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY700_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY800_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY800_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY900_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY900_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY1000_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY1000_total_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY1000MORE_count, 368, 0 | |
| CORE_PREF_L1_DEMAND_LATENCY1000MORE_total_count, 368, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY200_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY200_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY400_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY400_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY600_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY600_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY800_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY800_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1000_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1000_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1200_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1200_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1400_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1400_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1600_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1600_total_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1600MORE_count, 369, 0 | |
| CORE_PREF_MLC_NOT_USED_LATENCY1600MORE_total_count, 369, 0 | |
| CORE_PREF_MLC_USED_LATENCY200_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY200_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY400_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY400_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY600_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY600_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY800_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY800_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1000_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1000_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1200_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1200_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1400_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1400_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1600_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1600_total_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1600MORE_count, 370, 0 | |
| CORE_PREF_MLC_USED_LATENCY1600MORE_total_count, 370, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY300_count, 371, 792 | |
| CORE_PREF_MLC_DEMAND_LATENCY300_total_count, 371, 792 | |
| CORE_PREF_MLC_DEMAND_LATENCY400_count, 371, 1 | |
| CORE_PREF_MLC_DEMAND_LATENCY400_total_count, 371, 1 | |
| CORE_PREF_MLC_DEMAND_LATENCY500_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY500_total_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY600_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY600_total_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY700_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY700_total_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY800_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY800_total_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY900_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY900_total_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY1000_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY1000_total_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY1000MORE_count, 371, 0 | |
| CORE_PREF_MLC_DEMAND_LATENCY1000MORE_total_count, 371, 0 | |
| TOTAL_BATCH_FORMED_count, 0, 0 | |
| TOTAL_BATCH_FORMED_total_count, 0, 0 | |
| TOTAL_BATCH_MEM_REQ_MARKED_count, 0, 0 | |
| TOTAL_BATCH_MEM_REQ_MARKED_pct, 0, -nan | |
| TOTAL_BATCH_MEM_REQ_MARKED_total_count, 0, 0 | |
| TOTAL_BATCH_MEM_REQ_MARKED_total_pct, 0, -nan | |
| CORE_BATCH_MEM_REQ_MARKED_count, 0, 0 | |
| CORE_BATCH_MEM_REQ_MARKED_pct, 0, -nan | |
| CORE_BATCH_MEM_REQ_MARKED_total_count, 0, 0 | |
| CORE_BATCH_MEM_REQ_MARKED_total_pct, 0, -nan | |
| CORE_BATCH_MEM_REQ_MARKED_DEMAND_count, 0, 0 | |
| CORE_BATCH_MEM_REQ_MARKED_DEMAND_pct, 0, -nan | |
| CORE_BATCH_MEM_REQ_MARKED_DEMAND_total_count, 0, 0 | |
| CORE_BATCH_MEM_REQ_MARKED_DEMAND_total_pct, 0, -nan | |
| CORE_BATCH_MEM_REQ_MARKED_PREF_count, 0, 0 | |
| CORE_BATCH_MEM_REQ_MARKED_PREF_pct, 0, -nan | |
| CORE_BATCH_MEM_REQ_MARKED_PREF_total_count, 0, 0 | |
| CORE_BATCH_MEM_REQ_MARKED_PREF_total_pct, 0, -nan | |
| DRAM_ROW_BATCHES_count, 0, 0 | |
| DRAM_ROW_BATCHES_total_count, 0, 0 | |
| REJECTED_QUEUE_MLC_count, 0, 0 | |
| REJECTED_QUEUE_MLC_total_count, 0, 0 | |
| REJECTED_QUEUE_L1_count, 0, 0 | |
| REJECTED_QUEUE_L1_total_count, 0, 0 | |
| REJECTED_QUEUE_BUS_OUT_count, 0, 0 | |
| REJECTED_QUEUE_BUS_OUT_total_count, 0, 0 | |
| LEADING_LOAD_LATENCY_count, 0, 0 | |
| LEADING_LOAD_LATENCY_pct, 0, 0.000 | |
| LEADING_LOAD_LATENCY_total_count, 0, 0 | |
| LEADING_LOAD_LATENCY_total_pct, 0, 0.000 | |
| LEADING_LOADS_count, 0, 0 | |
| LEADING_LOADS_pct, 0, 0.000 | |
| LEADING_LOADS_total_count, 0, 0 | |
| LEADING_LOADS_total_pct, 0, 0.000 | |
| MEM_REQ_CRITICAL_PATH_LENGTH_count, 0, 0 | |
| MEM_REQ_CRITICAL_PATH_LENGTH_pct, 0, 0.000 | |
| MEM_REQ_CRITICAL_PATH_LENGTH_total_count, 0, 0 | |
| MEM_REQ_CRITICAL_PATH_LENGTH_total_pct, 0, 0.000 | |
| TOTAL_MEM_REQ_LATENCY_count, 0, 0 | |
| TOTAL_MEM_REQ_LATENCY_total_count, 0, 0 | |
| TOTAL_CRITICAL_MEM_REQ_LATENCY_count, 0, 0 | |
| TOTAL_CRITICAL_MEM_REQ_LATENCY_pct, 0, -nan | |
| TOTAL_CRITICAL_MEM_REQ_LATENCY_total_count, 0, 0 | |
| TOTAL_CRITICAL_MEM_REQ_LATENCY_total_pct, 0, -nan | |
| TOTAL_CRITICAL_BANK_LATENCY_count, 0, 0 | |
| TOTAL_CRITICAL_BANK_LATENCY_pct, 0, -nan | |
| TOTAL_CRITICAL_BANK_LATENCY_total_count, 0, 0 | |
| TOTAL_CRITICAL_BANK_LATENCY_total_pct, 0, -nan | |
| TOTAL_MEMORY_SLACK_count, 0, 0 | |
| TOTAL_MEMORY_SLACK_pct, 0, 0.000 | |
| TOTAL_MEMORY_SLACK_total_count, 0, 0 | |
| TOTAL_MEMORY_SLACK_total_pct, 0, 0.000 | |
| TOTAL_CHIP_UTILIZATION_count, 0, 0 | |
| TOTAL_CHIP_UTILIZATION_pct, 0, 0.000 | |
| TOTAL_CHIP_UTILIZATION_total_count, 0, 0 | |
| TOTAL_CHIP_UTILIZATION_total_pct, 0, 0.000 | |
| CHIP_BUSY_UNDER_CRITICAL_REQS_count, 0, 0 | |
| CHIP_BUSY_UNDER_CRITICAL_REQS_pct, 0, 0.000 | |
| CHIP_BUSY_UNDER_CRITICAL_REQS_total_count, 0, 0 | |
| CHIP_BUSY_UNDER_CRITICAL_REQS_total_pct, 0, 0.000 | |
| PERF_PRED_NUM_STAT_RESETS_count, 0, 0 | |
| PERF_PRED_NUM_STAT_RESETS_total_count, 0, 0 | |
| PERF_PRED_RESET_STATS_CYCLE_count, 0, 0 | |
| PERF_PRED_RESET_STATS_CYCLE_total_count, 0, 0 | |
| PERF_PRED_CYCLE_count, 0, 336256 | |
| PERF_PRED_CYCLE_total_count, 0, 336256 | |
| ESTIMATED_ALONE_CYCLES_count, 0, 0 | |
| ESTIMATED_ALONE_CYCLES_pct, 0, 0.000 | |
| ESTIMATED_ALONE_CYCLES_total_count, 0, 0 | |
| ESTIMATED_ALONE_CYCLES_total_pct, 0, 0.000 | |
| NUM_WINDOWS_WITH_DCACHE_MISS_count, 0, 2163 | |
| NUM_WINDOWS_WITH_DCACHE_MISS_total_count, 0, 2163 | |
| LONGEST_DCACHE_MISS_CHAIN_count, 0, 4230 | |
| LONGEST_DCACHE_MISS_CHAIN_total_count, 0, 4230 | |
| NUM_DCACHE_MISSES_IN_WINDOW_1_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_1_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_2_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_2_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_3_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_3_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_4_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_4_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_5_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_5_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_6_count, 372, 131 | |
| NUM_DCACHE_MISSES_IN_WINDOW_6_total_count, 372, 131 | |
| NUM_DCACHE_MISSES_IN_WINDOW_7_count, 372, 2029 | |
| NUM_DCACHE_MISSES_IN_WINDOW_7_total_count, 372, 2029 | |
| NUM_DCACHE_MISSES_IN_WINDOW_8_count, 372, 2 | |
| NUM_DCACHE_MISSES_IN_WINDOW_8_total_count, 372, 2 | |
| NUM_DCACHE_MISSES_IN_WINDOW_9_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_9_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_10_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_10_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_11_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_11_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_12_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_12_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_13_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_13_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_14_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_14_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_15_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_15_total_count, 372, 0 | |
| NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE_count, 372, 1 | |
| NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE_total_count, 372, 1 | |
| DCACHE_MLP_IN_WINDOW_1_0_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_1_0_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_1_5_count, 373, 1 | |
| DCACHE_MLP_IN_WINDOW_1_5_total_count, 373, 1 | |
| DCACHE_MLP_IN_WINDOW_2_0_count, 373, 2 | |
| DCACHE_MLP_IN_WINDOW_2_0_total_count, 373, 2 | |
| DCACHE_MLP_IN_WINDOW_2_5_count, 373, 1 | |
| DCACHE_MLP_IN_WINDOW_2_5_total_count, 373, 1 | |
| DCACHE_MLP_IN_WINDOW_3_0_count, 373, 21 | |
| DCACHE_MLP_IN_WINDOW_3_0_total_count, 373, 21 | |
| DCACHE_MLP_IN_WINDOW_3_5_count, 373, 2026 | |
| DCACHE_MLP_IN_WINDOW_3_5_total_count, 373, 2026 | |
| DCACHE_MLP_IN_WINDOW_4_0_count, 373, 1 | |
| DCACHE_MLP_IN_WINDOW_4_0_total_count, 373, 1 | |
| DCACHE_MLP_IN_WINDOW_4_5_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_4_5_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_5_0_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_5_0_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_5_5_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_5_5_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_6_0_count, 373, 109 | |
| DCACHE_MLP_IN_WINDOW_6_0_total_count, 373, 109 | |
| DCACHE_MLP_IN_WINDOW_6_5_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_6_5_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_7_0_count, 373, 2 | |
| DCACHE_MLP_IN_WINDOW_7_0_total_count, 373, 2 | |
| DCACHE_MLP_IN_WINDOW_7_5_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_7_5_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_8_0_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_8_0_total_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_8_5_OR_MORE_count, 373, 0 | |
| DCACHE_MLP_IN_WINDOW_8_5_OR_MORE_total_count, 373, 0 | |
| PARAM_CHIP_CYCLE_TIME_count, 0, 0 | |
| PARAM_CHIP_CYCLE_TIME_total_count, 0, 0 | |
| PARAM_CORE_CYCLE_TIME_count, 0, 312500 | |
| PARAM_CORE_CYCLE_TIME_total_count, 0, 312500 | |
| PARAM_L1_CYCLE_TIME_count, 0, 312500 | |
| PARAM_L1_CYCLE_TIME_total_count, 0, 312500 | |
| PARAM_MEMORY_CYCLE_TIME_count, 0, 833333 | |
| PARAM_MEMORY_CYCLE_TIME_total_count, 0, 833333 | |
| MEM_REQ_NON_SCHEDULED__0_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED__0_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED__4_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED__4_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED__8_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED__8_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_12_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_12_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_16_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_16_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_20_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_20_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_24_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_24_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_28_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_28_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_32_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_32_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_36_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_36_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_40_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_40_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_44_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_44_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_48_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_48_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_52_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_52_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_56_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_56_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_60_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_60_total_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_64_count, 374, 0 | |
| MEM_REQ_NON_SCHEDULED_64_total_count, 374, 0 | |
| MEM_REQ_DEMANDS__0_count, 375, 321760 | |
| MEM_REQ_DEMANDS__0_total_count, 375, 321760 | |
| MEM_REQ_DEMANDS__4_count, 375, 14496 | |
| MEM_REQ_DEMANDS__4_total_count, 375, 14496 | |
| MEM_REQ_DEMANDS__8_count, 375, 0 | |
| MEM_REQ_DEMANDS__8_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_12_count, 375, 0 | |
| MEM_REQ_DEMANDS_12_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_16_count, 375, 0 | |
| MEM_REQ_DEMANDS_16_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_20_count, 375, 0 | |
| MEM_REQ_DEMANDS_20_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_24_count, 375, 0 | |
| MEM_REQ_DEMANDS_24_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_28_count, 375, 0 | |
| MEM_REQ_DEMANDS_28_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_32_count, 375, 0 | |
| MEM_REQ_DEMANDS_32_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_36_count, 375, 0 | |
| MEM_REQ_DEMANDS_36_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_40_count, 375, 0 | |
| MEM_REQ_DEMANDS_40_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_44_count, 375, 0 | |
| MEM_REQ_DEMANDS_44_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_48_count, 375, 0 | |
| MEM_REQ_DEMANDS_48_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_52_count, 375, 0 | |
| MEM_REQ_DEMANDS_52_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_56_count, 375, 0 | |
| MEM_REQ_DEMANDS_56_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_60_count, 375, 0 | |
| MEM_REQ_DEMANDS_60_total_count, 375, 0 | |
| MEM_REQ_DEMANDS_64_count, 375, 0 | |
| MEM_REQ_DEMANDS_64_total_count, 375, 0 | |
| MEM_REQ_PREFS__0_count, 376, 11910 | |
| MEM_REQ_PREFS__0_total_count, 376, 11910 | |
| MEM_REQ_PREFS__4_count, 376, 291762 | |
| MEM_REQ_PREFS__4_total_count, 376, 291762 | |
| MEM_REQ_PREFS__8_count, 376, 10208 | |
| MEM_REQ_PREFS__8_total_count, 376, 10208 | |
| MEM_REQ_PREFS_12_count, 376, 6725 | |
| MEM_REQ_PREFS_12_total_count, 376, 6725 | |
| MEM_REQ_PREFS_16_count, 376, 14464 | |
| MEM_REQ_PREFS_16_total_count, 376, 14464 | |
| MEM_REQ_PREFS_20_count, 376, 68 | |
| MEM_REQ_PREFS_20_total_count, 376, 68 | |
| MEM_REQ_PREFS_24_count, 376, 1054 | |
| MEM_REQ_PREFS_24_total_count, 376, 1054 | |
| MEM_REQ_PREFS_28_count, 376, 65 | |
| MEM_REQ_PREFS_28_total_count, 376, 65 | |
| MEM_REQ_PREFS_32_count, 376, 0 | |
| MEM_REQ_PREFS_32_total_count, 376, 0 | |
| MEM_REQ_PREFS_36_count, 376, 0 | |
| MEM_REQ_PREFS_36_total_count, 376, 0 | |
| MEM_REQ_PREFS_40_count, 376, 0 | |
| MEM_REQ_PREFS_40_total_count, 376, 0 | |
| MEM_REQ_PREFS_44_count, 376, 0 | |
| MEM_REQ_PREFS_44_total_count, 376, 0 | |
| MEM_REQ_PREFS_48_count, 376, 0 | |
| MEM_REQ_PREFS_48_total_count, 376, 0 | |
| MEM_REQ_PREFS_52_count, 376, 0 | |
| MEM_REQ_PREFS_52_total_count, 376, 0 | |
| MEM_REQ_PREFS_56_count, 376, 0 | |
| MEM_REQ_PREFS_56_total_count, 376, 0 | |
| MEM_REQ_PREFS_60_count, 376, 0 | |
| MEM_REQ_PREFS_60_total_count, 376, 0 | |
| MEM_REQ_PREFS_64_count, 376, 0 | |
| MEM_REQ_PREFS_64_total_count, 376, 0 | |
| MEM_REQ_WRITEBACKS__0_count, 377, 336080 | |
| MEM_REQ_WRITEBACKS__0_total_count, 377, 336080 | |
| MEM_REQ_WRITEBACKS__4_count, 377, 176 | |
| MEM_REQ_WRITEBACKS__4_total_count, 377, 176 | |
| MEM_REQ_WRITEBACKS__8_count, 377, 0 | |
| MEM_REQ_WRITEBACKS__8_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_12_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_12_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_16_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_16_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_20_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_20_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_24_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_24_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_28_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_28_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_32_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_32_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_36_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_36_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_40_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_40_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_44_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_44_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_48_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_48_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_52_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_52_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_56_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_56_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_60_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_60_total_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_64_count, 377, 0 | |
| MEM_REQ_WRITEBACKS_64_total_count, 377, 0 | |
| MEM_REQ_DEMAND_CYCLES_count, 0, 932466 | |
| MEM_REQ_DEMAND_CYCLES_total_count, 0, 932466 | |
| MEM_REQ_PREF_CYCLES_count, 0, 1898375 | |
| MEM_REQ_PREF_CYCLES_total_count, 0, 1898375 | |
| MEM_REQ_WB_CYCLES_count, 0, 271949 | |
| MEM_REQ_WB_CYCLES_total_count, 0, 271949 | |
| DRAM_CHANNEL_REQS_count, 0, 0 | |
| DRAM_CHANNEL_REQS_total_count, 0, 0 | |
| DRAM_CHANNEL_CRIT_REQS_count, 0, 0 | |
| DRAM_CHANNEL_CRIT_REQS_total_count, 0, 0 | |
| DRAM_CHANNEL_CRIT_DIR_SWITCHES_count, 0, 0 | |
| DRAM_CHANNEL_CRIT_DIR_SWITCHES_total_count, 0, 0 | |
| DRAM_BANK_CRIT_REQS_count, 0, 0 | |
| DRAM_BANK_CRIT_REQS_total_count, 0, 0 | |
| DRAM_INSTA_MLP_SAMPLES_count, 0, 0 | |
| DRAM_INSTA_MLP_SAMPLES_total_count, 0, 0 | |
| DRAM_INSTA_MLP_UNIQUE_REQS_count, 0, 0 | |
| DRAM_INSTA_MLP_UNIQUE_REQS_pct, 0, -nan | |
| DRAM_INSTA_MLP_UNIQUE_REQS_total_count, 0, 0 | |
| DRAM_INSTA_MLP_UNIQUE_REQS_total_pct, 0, -nan | |
| DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000_count, 0, 0 | |
| DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000_pct, 0, -nan | |
| DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000_total_count, 0, 0 | |
| DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000_total_pct, 0, -nan | |
| DRAM_GLOBAL_MLP_count, 0, 0 | |
| DRAM_GLOBAL_MLP_pct, 0, -nan | |
| DRAM_GLOBAL_MLP_total_count, 0, 0 | |
| DRAM_GLOBAL_MLP_total_pct, 0, -nan | |
| DRAM_GLOBAL_MLP_0_count, 378, 0 | |
| DRAM_GLOBAL_MLP_0_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_1_count, 378, 0 | |
| DRAM_GLOBAL_MLP_1_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_2_count, 378, 0 | |
| DRAM_GLOBAL_MLP_2_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_3_count, 378, 0 | |
| DRAM_GLOBAL_MLP_3_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_4_count, 378, 0 | |
| DRAM_GLOBAL_MLP_4_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_5_count, 378, 0 | |
| DRAM_GLOBAL_MLP_5_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_6_count, 378, 0 | |
| DRAM_GLOBAL_MLP_6_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_7_count, 378, 0 | |
| DRAM_GLOBAL_MLP_7_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_8_count, 378, 0 | |
| DRAM_GLOBAL_MLP_8_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_9_count, 378, 0 | |
| DRAM_GLOBAL_MLP_9_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_10_count, 378, 0 | |
| DRAM_GLOBAL_MLP_10_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_11_count, 378, 0 | |
| DRAM_GLOBAL_MLP_11_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_12_count, 378, 0 | |
| DRAM_GLOBAL_MLP_12_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_13_count, 378, 0 | |
| DRAM_GLOBAL_MLP_13_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_14_count, 378, 0 | |
| DRAM_GLOBAL_MLP_14_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_15_count, 378, 0 | |
| DRAM_GLOBAL_MLP_15_total_count, 378, 0 | |
| DRAM_GLOBAL_MLP_16_count, 378, 0 | |
| DRAM_GLOBAL_MLP_16_total_count, 378, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_0_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_0_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_1_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_1_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_2_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_2_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_3_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_3_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_4_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_4_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_5_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_5_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_6_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_6_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_7_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_7_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_8_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_8_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_9_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_9_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_10_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_10_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_11_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_11_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_12_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_12_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_13_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_13_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_14_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_14_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_15_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_15_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_16_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_16_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_17_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_17_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_18_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_18_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_19_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_19_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_20_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_20_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_21_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_21_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_22_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_22_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_23_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_23_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_24_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_24_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_25_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_25_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_26_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_26_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_27_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_27_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_28_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_28_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_29_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_29_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_30_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_30_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_31_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_31_total_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_32_count, 379, 0 | |
| DRAM_TOTAL_GLOBAL_MLP_32_total_count, 379, 0 | |
| UNIQUE_ROWS_PER_BANK_0_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_0_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_1_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_1_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_2_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_2_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_3_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_3_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_4_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_4_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_5_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_5_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_6_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_6_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_7_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_7_total_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_MORE_count, 380, 0 | |
| UNIQUE_ROWS_PER_BANK_MORE_total_count, 380, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_0_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_0_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_1_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_1_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_2_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_2_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_3_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_3_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_4_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_4_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_5_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_5_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_6_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_6_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_7_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_7_total_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_MORE_count, 381, 0 | |
| CORE_UNIQUE_ROWS_PER_BANK_MORE_total_count, 381, 0 | |
| CORES_PER_BANK_0_count, 382, 0 | |
| CORES_PER_BANK_0_total_count, 382, 0 | |
| CORES_PER_BANK_1_count, 382, 0 | |
| CORES_PER_BANK_1_total_count, 382, 0 | |
| CORES_PER_BANK_2_count, 382, 0 | |
| CORES_PER_BANK_2_total_count, 382, 0 | |
| CORES_PER_BANK_3_count, 382, 0 | |
| CORES_PER_BANK_3_total_count, 382, 0 | |
| CORES_PER_BANK_4_count, 382, 0 | |
| CORES_PER_BANK_4_total_count, 382, 0 | |
| CORES_PER_BANK_5_count, 382, 0 | |
| CORES_PER_BANK_5_total_count, 382, 0 | |
| CORES_PER_BANK_6_count, 382, 0 | |
| CORES_PER_BANK_6_total_count, 382, 0 | |
| CORES_PER_BANK_7_count, 382, 0 | |
| CORES_PER_BANK_7_total_count, 382, 0 | |
| CORES_PER_BANK_MORE_count, 382, 0 | |
| CORES_PER_BANK_MORE_total_count, 382, 0 | |
| MEM_BANKS_WITH_REQS_0_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_0_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_1_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_1_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_2_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_2_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_3_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_3_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_4_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_4_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_5_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_5_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_6_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_6_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_7_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_7_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_8_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_8_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_9_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_9_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_10_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_10_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_11_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_11_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_12_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_12_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_13_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_13_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_14_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_14_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_15_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_15_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_16_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_16_total_count, 383, 0 | |
| MEM_BANKS_WITH_REQS_count, 0, 0 | |
| MEM_BANKS_WITH_REQS_total_count, 0, 0 | |
| DRAM_CHANNEL_IN_DEMAND_count, 0, 0 | |
| DRAM_CHANNEL_IN_DEMAND_total_count, 0, 0 | |
| DRAM_BUS_IN_DEMAND_count, 0, 0 | |
| DRAM_BUS_IN_DEMAND_total_count, 0, 0 | |
| DRAM_BANK_IN_DEMAND_count, 0, 0 | |
| DRAM_BANK_IN_DEMAND_total_count, 0, 0 | |
| DRAM_BANK_IN_DEMAND_STALLING_count, 0, 0 | |
| DRAM_BANK_IN_DEMAND_STALLING_total_count, 0, 0 | |
| DRAM_ANY_BANK_IN_DEMAND_count, 0, 0 | |
| DRAM_ANY_BANK_IN_DEMAND_total_count, 0, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_0_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_0_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_1_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_1_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_2_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_2_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_3_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_3_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_4_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_4_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_5_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_5_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_6_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_6_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_7_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_7_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_8_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_8_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_9_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_9_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_10_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_10_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_11_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_11_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_12_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_12_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_13_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_13_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_14_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_14_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_15_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_15_total_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_16_count, 384, 0 | |
| DRAM_BANK_IN_DEMAND_BANK_16_total_count, 384, 0 | |
| DRAM_CONTENTION_BUS_count, 0, 0 | |
| DRAM_CONTENTION_BUS_pct, 0, -nan | |
| DRAM_CONTENTION_BUS_total_count, 0, 0 | |
| DRAM_CONTENTION_BUS_total_pct, 0, -nan | |
| DRAM_CONTENTION_BANKS_count, 0, 0 | |
| DRAM_CONTENTION_BANKS_pct, 0, -nan | |
| DRAM_CONTENTION_BANKS_total_count, 0, 0 | |
| DRAM_CONTENTION_BANKS_total_pct, 0, -nan | |
| DRAM_CONTENTION_FAW_count, 0, 0 | |
| DRAM_CONTENTION_FAW_pct, 0, -nan | |
| DRAM_CONTENTION_FAW_total_count, 0, 0 | |
| DRAM_CONTENTION_FAW_total_pct, 0, -nan | |
| DRAM_CONTENTION_BANKS_TIMES_1000_count, 0, 0 | |
| DRAM_CONTENTION_BANKS_TIMES_1000_pct, 0, -nan | |
| DRAM_CONTENTION_BANKS_TIMES_1000_total_count, 0, 0 | |
| DRAM_CONTENTION_BANKS_TIMES_1000_total_pct, 0, -nan | |
| DRAM_STALL_OTHER_CORE_count, 0, 0 | |
| DRAM_STALL_OTHER_CORE_total_count, 0, 0 | |
| DRAM_STALLED_BY_OTHER_CORE_count, 0, 0 | |
| DRAM_STALLED_BY_OTHER_CORE_total_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_total_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BUS_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BUS_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_BUS_total_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BUS_total_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_BANK_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BANK_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_BANK_total_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BANK_total_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_BANK_TRAS_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BANK_TRAS_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_BANK_TRAS_total_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_BANK_TRAS_total_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_FAW_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_FAW_pct, 0, -nan | |
| DRAM_MP_CRIT_PATH_FAW_total_count, 0, 0 | |
| DRAM_MP_CRIT_PATH_FAW_total_pct, 0, -nan | |
| DRAM_BLACK_BOX_SERVICE_TIMES_1000_count, 0, 0 | |
| DRAM_BLACK_BOX_SERVICE_TIMES_1000_total_count, 0, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_0_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_0_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_1_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_1_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_2_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_2_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_3_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_3_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_4_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_4_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_5_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_5_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_6_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_6_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_7_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_7_total_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_8_count, 385, 0 | |
| DRAM_BLACK_BOX_REQS_BUSY_8_total_count, 385, 0 | |
| NUM_MEM_SCHED_DECISIONS_count, 0, 0 | |
| NUM_MEM_SCHED_DECISIONS_total_count, 0, 0 | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_count, 0, 0 | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_pct, 0, -nan | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_total_count, 0, 0 | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_total_pct, 0, -nan | |
| NUM_MEM_SCHED_DECISIONS_PER_BANK_count, 0, 0 | |
| NUM_MEM_SCHED_DECISIONS_PER_BANK_total_count, 0, 0 | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK_count, 0, 0 | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK_pct, 0, -nan | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK_total_count, 0, 0 | |
| MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK_total_pct, 0, -nan | |
| ROW_BUFFER_HITS_BANK_0_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_0_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_1_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_1_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_2_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_2_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_3_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_3_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_4_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_4_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_5_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_5_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_6_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_6_total_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_7_count, 386, 0 | |
| ROW_BUFFER_HITS_BANK_7_total_count, 386, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_0_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_0_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_1_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_1_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_2_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_2_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_3_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_3_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_4_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_4_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_5_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_5_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_6_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_6_total_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_7_count, 387, 0 | |
| ROW_BUFFER_CONFLICTS_BANK_7_total_count, 387, 0 | |
| MEM_BANK_WAITING_CYCLES_count, 0, 0 | |
| MEM_BANK_WAITING_CYCLES_total_count, 0, 0 | |
| MEM_WAITING_CYCLES_TIMES_840_count, 0, 0 | |
| MEM_WAITING_CYCLES_TIMES_840_total_count, 0, 0 | |
| MEM_PROB_WAITING_CYCLES_count, 0, 0 | |
| MEM_PROB_WAITING_CYCLES_total_count, 0, 0 | |
| DRAM_SCHED_QUANTA_count, 0, 0 | |
| DRAM_SCHED_QUANTA_total_count, 0, 0 | |
| DRAM_SCHED_CORE_PRIORITY_0_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_0_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_1_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_1_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_2_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_2_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_3_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_3_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_4_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_4_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_5_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_5_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_6_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_6_total_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_7_count, 388, 0 | |
| DRAM_SCHED_CORE_PRIORITY_7_total_count, 388, 0 | |
| DRAM_SCHED_CMD_SCHEDULED_count, 0, 0 | |
| DRAM_SCHED_CMD_SCHEDULED_pct, 0, -nan | |
| DRAM_SCHED_CMD_SCHEDULED_total_count, 0, 0 | |
| DRAM_SCHED_CMD_SCHEDULED_total_pct, 0, -nan | |
| DRAM_SCHED_DIFF_CORE_AVAILABLE_count, 0, 0 | |
| DRAM_SCHED_DIFF_CORE_AVAILABLE_pct, 0, -nan | |
| DRAM_SCHED_DIFF_CORE_AVAILABLE_total_count, 0, 0 | |
| DRAM_SCHED_DIFF_CORE_AVAILABLE_total_pct, 0, -nan | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_1_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_1_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_2_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_2_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_3_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_3_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_4_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_4_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_5_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_5_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_6_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_6_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_7_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_7_total_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_8_count, 389, 0 | |
| DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_8_total_count, 389, 0 | |
| DRAM_BANK_WAIT_CYCLES_ROW_CONFLICT_count, 0, 0 | |
| DRAM_BANK_WAIT_CYCLES_ROW_CONFLICT_total_count, 0, 0 | |
| DRAM_BANK_WAIT_CYCLES_ROW_MISS_count, 0, 0 | |
| DRAM_BANK_WAIT_CYCLES_ROW_MISS_total_count, 0, 0 | |
| DRAM_BANK_WAIT_CYCLES_ROW_HIT_count, 0, 0 | |
| DRAM_BANK_WAIT_CYCLES_ROW_HIT_total_count, 0, 0 | |
| DRAM_ROW_OPEN_WAIT_count, 0, 0 | |
| DRAM_ROW_OPEN_WAIT_total_count, 0, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_0_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_0_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_10_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_10_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_20_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_20_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_30_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_30_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_40_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_40_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_50_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_50_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_60_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_60_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_70_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_70_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_80_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_80_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_90_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_90_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_100_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_100_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_110_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_110_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_120_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_120_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_130_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_130_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_140_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_140_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_150_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_150_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_160_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_160_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_170_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_170_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_180_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_180_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_190_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_190_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_200_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_200_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_210_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_210_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_220_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_220_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_230_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_230_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_240_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_240_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_250_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_250_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_260_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_260_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_270_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_270_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_280_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_280_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_290_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_290_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_300_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_300_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_310_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_310_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_320_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_320_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_330_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_330_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_340_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_340_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_350_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_350_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_360_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_360_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_370_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_370_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_380_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_380_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_390_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_390_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_400_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_400_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_410_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_410_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_420_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_420_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_430_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_430_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_440_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_440_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_450_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_450_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_460_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_460_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_470_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_470_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_480_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_480_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_490_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_490_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_500_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_500_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_510_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_510_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_520_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_520_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_530_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_530_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_540_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_540_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_550_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_550_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_560_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_560_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_570_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_570_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_580_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_580_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_590_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_590_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_600_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_600_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_610_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_610_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_620_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_620_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_630_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_630_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_640_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_640_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_650_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_650_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_660_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_660_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_670_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_670_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_680_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_680_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_690_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_690_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_700_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_700_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_710_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_710_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_720_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_720_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_730_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_730_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_740_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_740_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_750_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_750_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_760_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_760_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_770_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_770_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_780_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_780_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_790_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_790_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_800_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_800_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_810_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_810_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_820_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_820_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_830_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_830_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_840_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_840_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_850_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_850_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_860_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_860_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_870_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_870_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_880_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_880_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_890_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_890_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_900_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_900_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_910_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_910_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_920_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_920_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_930_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_930_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_940_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_940_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_950_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_950_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_960_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_960_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_970_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_970_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_980_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_980_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_990_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_990_total_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_1000_count, 390, 0 | |
| MEM_QUEUE_ARRIVAL_DISTANCE_1000_total_count, 390, 0 | |
| EQUAL_USE_QUANTUMS_count, 0, 0 | |
| EQUAL_USE_QUANTUMS_total_count, 0, 0 | |
| EQUAL_USE_BW_MEASURE_PERIODS_count, 0, 0 | |
| EQUAL_USE_BW_MEASURE_PERIODS_total_count, 0, 0 | |
| EQUAL_USE_BW_count, 0, 0 | |
| EQUAL_USE_BW_total_count, 0, 0 | |
| EQUAL_USE_BOTTLENECK_BUS_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_BUS_total_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_BANK_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_BANK_total_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_FAW_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_FAW_total_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_BUS_PLUS_FAW_count, 391, 0 | |
| EQUAL_USE_BOTTLENECK_BUS_PLUS_FAW_total_count, 391, 0 | |
| EQUAL_USE_BW_BUS_count, 0, 0 | |
| EQUAL_USE_BW_BUS_total_count, 0, 0 | |
| EQUAL_USE_BW_BANK_count, 0, 0 | |
| EQUAL_USE_BW_BANK_total_count, 0, 0 | |
| EQUAL_USE_BW_FAW_count, 0, 0 | |
| EQUAL_USE_BW_FAW_total_count, 0, 0 | |
| EQUAL_USE_BW_BUS_PLUS_FAW_count, 0, 0 | |
| EQUAL_USE_BW_BUS_PLUS_FAW_total_count, 0, 0 | |
| EQUAL_USE_BW_BUS_PLUS_FAW2_count, 0, 0 | |
| EQUAL_USE_BW_BUS_PLUS_FAW2_total_count, 0, 0 | |
| EQUAL_USE_BW_BUS_PLUS_FAW3_count, 0, 0 | |
| EQUAL_USE_BW_BUS_PLUS_FAW3_total_count, 0, 0 | |
| EQUAL_USE_BW_CRIT_PATH_count, 0, 0 | |
| EQUAL_USE_BW_CRIT_PATH_total_count, 0, 0 | |
| EQUAL_USE_BW_BLACK_BOX_count, 0, 0 | |
| EQUAL_USE_BW_BLACK_BOX_total_count, 0, 0 | |
| DRAM_BANK_SERVICE_count, 0, 0 | |
| DRAM_BANK_SERVICE_total_count, 0, 0 | |
| DRAM_CONTENDED_BANK_SERVICE_count, 0, 0 | |
| DRAM_CONTENDED_BANK_SERVICE_total_count, 0, 0 | |
| DRAM_BUS_DIR_SWITCHES_count, 0, 0 | |
| DRAM_BUS_DIR_SWITCHES_total_count, 0, 0 | |
| DRAM_ACTIVATE_TO_COLUMN_LATENCY_count, 0, 0 | |
| DRAM_ACTIVATE_TO_COLUMN_LATENCY_total_count, 0, 0 | |
| DRAM_ACTIVATE_TO_READ_count, 0, 0 | |
| DRAM_ACTIVATE_TO_READ_total_count, 0, 0 | |
| DRAM_ACTIVATE_TO_READ_LATENCY_count, 0, 0 | |
| DRAM_ACTIVATE_TO_READ_LATENCY_pct, 0, -nan | |
| DRAM_ACTIVATE_TO_READ_LATENCY_total_count, 0, 0 | |
| DRAM_ACTIVATE_TO_READ_LATENCY_total_pct, 0, -nan | |
| DRAM_ACTIVATE_TO_WRITE_count, 0, 0 | |
| DRAM_ACTIVATE_TO_WRITE_total_count, 0, 0 | |
| DRAM_ACTIVATE_TO_WRITE_LATENCY_count, 0, 0 | |
| DRAM_ACTIVATE_TO_WRITE_LATENCY_pct, 0, -nan | |
| DRAM_ACTIVATE_TO_WRITE_LATENCY_total_count, 0, 0 | |
| DRAM_ACTIVATE_TO_WRITE_LATENCY_total_pct, 0, -nan | |
| EQUAL_USE_PRIORITY_0_count, 392, 0 | |
| EQUAL_USE_PRIORITY_0_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_1_count, 392, 0 | |
| EQUAL_USE_PRIORITY_1_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_2_count, 392, 0 | |
| EQUAL_USE_PRIORITY_2_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_3_count, 392, 0 | |
| EQUAL_USE_PRIORITY_3_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_4_count, 392, 0 | |
| EQUAL_USE_PRIORITY_4_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_5_count, 392, 0 | |
| EQUAL_USE_PRIORITY_5_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_6_count, 392, 0 | |
| EQUAL_USE_PRIORITY_6_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_7_count, 392, 0 | |
| EQUAL_USE_PRIORITY_7_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_8_count, 392, 0 | |
| EQUAL_USE_PRIORITY_8_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_9_count, 392, 0 | |
| EQUAL_USE_PRIORITY_9_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_10_count, 392, 0 | |
| EQUAL_USE_PRIORITY_10_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_11_count, 392, 0 | |
| EQUAL_USE_PRIORITY_11_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_12_count, 392, 0 | |
| EQUAL_USE_PRIORITY_12_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_13_count, 392, 0 | |
| EQUAL_USE_PRIORITY_13_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_14_count, 392, 0 | |
| EQUAL_USE_PRIORITY_14_total_count, 392, 0 | |
| EQUAL_USE_PRIORITY_15_count, 392, 0 | |
| EQUAL_USE_PRIORITY_15_total_count, 392, 0 | |
| DRAM_ROW_ACCESSES_0_count, 393, 0 | |
| DRAM_ROW_ACCESSES_0_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_1_count, 393, 0 | |
| DRAM_ROW_ACCESSES_1_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_2_count, 393, 0 | |
| DRAM_ROW_ACCESSES_2_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_3_count, 393, 0 | |
| DRAM_ROW_ACCESSES_3_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_4_count, 393, 0 | |
| DRAM_ROW_ACCESSES_4_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_5_count, 393, 0 | |
| DRAM_ROW_ACCESSES_5_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_6_count, 393, 0 | |
| DRAM_ROW_ACCESSES_6_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_7_count, 393, 0 | |
| DRAM_ROW_ACCESSES_7_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_8_count, 393, 0 | |
| DRAM_ROW_ACCESSES_8_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_9_count, 393, 0 | |
| DRAM_ROW_ACCESSES_9_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_10_count, 393, 0 | |
| DRAM_ROW_ACCESSES_10_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_11_count, 393, 0 | |
| DRAM_ROW_ACCESSES_11_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_12_count, 393, 0 | |
| DRAM_ROW_ACCESSES_12_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_13_count, 393, 0 | |
| DRAM_ROW_ACCESSES_13_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_14_count, 393, 0 | |
| DRAM_ROW_ACCESSES_14_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_15_count, 393, 0 | |
| DRAM_ROW_ACCESSES_15_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_16_count, 393, 0 | |
| DRAM_ROW_ACCESSES_16_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_17_count, 393, 0 | |
| DRAM_ROW_ACCESSES_17_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_18_count, 393, 0 | |
| DRAM_ROW_ACCESSES_18_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_19_count, 393, 0 | |
| DRAM_ROW_ACCESSES_19_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_20_count, 393, 0 | |
| DRAM_ROW_ACCESSES_20_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_21_count, 393, 0 | |
| DRAM_ROW_ACCESSES_21_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_22_count, 393, 0 | |
| DRAM_ROW_ACCESSES_22_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_23_count, 393, 0 | |
| DRAM_ROW_ACCESSES_23_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_24_count, 393, 0 | |
| DRAM_ROW_ACCESSES_24_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_25_count, 393, 0 | |
| DRAM_ROW_ACCESSES_25_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_26_count, 393, 0 | |
| DRAM_ROW_ACCESSES_26_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_27_count, 393, 0 | |
| DRAM_ROW_ACCESSES_27_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_28_count, 393, 0 | |
| DRAM_ROW_ACCESSES_28_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_29_count, 393, 0 | |
| DRAM_ROW_ACCESSES_29_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_30_count, 393, 0 | |
| DRAM_ROW_ACCESSES_30_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_31_count, 393, 0 | |
| DRAM_ROW_ACCESSES_31_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_32_count, 393, 0 | |
| DRAM_ROW_ACCESSES_32_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_33_count, 393, 0 | |
| DRAM_ROW_ACCESSES_33_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_34_count, 393, 0 | |
| DRAM_ROW_ACCESSES_34_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_35_count, 393, 0 | |
| DRAM_ROW_ACCESSES_35_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_36_count, 393, 0 | |
| DRAM_ROW_ACCESSES_36_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_37_count, 393, 0 | |
| DRAM_ROW_ACCESSES_37_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_38_count, 393, 0 | |
| DRAM_ROW_ACCESSES_38_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_39_count, 393, 0 | |
| DRAM_ROW_ACCESSES_39_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_40_count, 393, 0 | |
| DRAM_ROW_ACCESSES_40_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_41_count, 393, 0 | |
| DRAM_ROW_ACCESSES_41_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_42_count, 393, 0 | |
| DRAM_ROW_ACCESSES_42_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_43_count, 393, 0 | |
| DRAM_ROW_ACCESSES_43_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_44_count, 393, 0 | |
| DRAM_ROW_ACCESSES_44_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_45_count, 393, 0 | |
| DRAM_ROW_ACCESSES_45_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_46_count, 393, 0 | |
| DRAM_ROW_ACCESSES_46_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_47_count, 393, 0 | |
| DRAM_ROW_ACCESSES_47_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_48_count, 393, 0 | |
| DRAM_ROW_ACCESSES_48_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_49_count, 393, 0 | |
| DRAM_ROW_ACCESSES_49_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_50_count, 393, 0 | |
| DRAM_ROW_ACCESSES_50_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_51_count, 393, 0 | |
| DRAM_ROW_ACCESSES_51_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_52_count, 393, 0 | |
| DRAM_ROW_ACCESSES_52_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_53_count, 393, 0 | |
| DRAM_ROW_ACCESSES_53_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_54_count, 393, 0 | |
| DRAM_ROW_ACCESSES_54_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_55_count, 393, 0 | |
| DRAM_ROW_ACCESSES_55_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_56_count, 393, 0 | |
| DRAM_ROW_ACCESSES_56_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_57_count, 393, 0 | |
| DRAM_ROW_ACCESSES_57_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_58_count, 393, 0 | |
| DRAM_ROW_ACCESSES_58_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_59_count, 393, 0 | |
| DRAM_ROW_ACCESSES_59_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_60_count, 393, 0 | |
| DRAM_ROW_ACCESSES_60_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_61_count, 393, 0 | |
| DRAM_ROW_ACCESSES_61_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_62_count, 393, 0 | |
| DRAM_ROW_ACCESSES_62_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_63_count, 393, 0 | |
| DRAM_ROW_ACCESSES_63_total_count, 393, 0 | |
| DRAM_ROW_ACCESSES_64_count, 393, 0 | |
| DRAM_ROW_ACCESSES_64_total_count, 393, 0 | |
| DRAM_NUM_REQS_0_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_0_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_1_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_2_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_3_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_4_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_5_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_6_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_7_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_8_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_9_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_10_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_11_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_12_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_13_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_14_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_15_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_16_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_17_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_18_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_19_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_20_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_21_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_22_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_23_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_24_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_25_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_26_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_27_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_28_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_29_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_30_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_31_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_TOTAL_count, 0, 0 | |
| DRAM_NUM_REQS_32_TOTAL_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_0_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_0_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_0_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_0_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_0_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_0_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_0_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_0_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_0_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_0_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_0_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_0_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_0_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_0_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_0_WB_count, 0, 0 | |
| DRAM_NUM_REQS_0_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_0_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_0_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_0_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_0_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_0_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_1_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_1_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_1_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_1_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_1_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_1_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_1_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_1_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_1_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_1_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_WB_count, 0, 0 | |
| DRAM_NUM_REQS_1_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_1_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_1_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_1_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_1_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_1_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_2_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_2_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_2_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_2_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_2_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_2_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_2_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_2_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_2_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_2_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_WB_count, 0, 0 | |
| DRAM_NUM_REQS_2_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_2_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_2_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_2_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_2_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_2_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_3_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_3_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_3_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_3_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_3_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_3_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_3_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_3_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_3_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_3_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_WB_count, 0, 0 | |
| DRAM_NUM_REQS_3_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_3_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_3_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_3_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_3_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_3_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_4_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_4_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_4_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_4_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_4_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_4_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_4_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_4_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_4_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_4_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_WB_count, 0, 0 | |
| DRAM_NUM_REQS_4_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_4_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_4_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_4_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_4_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_4_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_5_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_5_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_5_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_5_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_5_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_5_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_5_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_5_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_5_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_5_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_WB_count, 0, 0 | |
| DRAM_NUM_REQS_5_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_5_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_5_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_5_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_5_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_5_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_6_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_6_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_6_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_6_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_6_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_6_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_6_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_6_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_6_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_6_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_WB_count, 0, 0 | |
| DRAM_NUM_REQS_6_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_6_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_6_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_6_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_6_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_6_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_7_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_7_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_7_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_7_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_7_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_7_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_7_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_7_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_7_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_7_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_WB_count, 0, 0 | |
| DRAM_NUM_REQS_7_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_7_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_7_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_7_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_7_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_7_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_8_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_8_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_8_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_8_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_8_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_8_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_8_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_8_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_8_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_8_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_WB_count, 0, 0 | |
| DRAM_NUM_REQS_8_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_8_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_8_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_8_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_8_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_8_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_9_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_9_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_9_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_9_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_9_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_9_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_9_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_9_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_9_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_9_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_WB_count, 0, 0 | |
| DRAM_NUM_REQS_9_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_9_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_9_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_9_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_9_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_9_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_10_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_10_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_10_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_10_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_10_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_10_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_10_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_10_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_10_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_10_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_WB_count, 0, 0 | |
| DRAM_NUM_REQS_10_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_10_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_10_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_10_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_10_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_10_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_11_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_11_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_11_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_11_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_11_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_11_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_11_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_11_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_11_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_11_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_WB_count, 0, 0 | |
| DRAM_NUM_REQS_11_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_11_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_11_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_11_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_11_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_11_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_12_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_12_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_12_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_12_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_12_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_12_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_12_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_12_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_12_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_12_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_WB_count, 0, 0 | |
| DRAM_NUM_REQS_12_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_12_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_12_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_12_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_12_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_12_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_13_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_13_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_13_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_13_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_13_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_13_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_13_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_13_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_13_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_13_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_WB_count, 0, 0 | |
| DRAM_NUM_REQS_13_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_13_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_13_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_13_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_13_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_13_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_14_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_14_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_14_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_14_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_14_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_14_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_14_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_14_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_14_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_14_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_WB_count, 0, 0 | |
| DRAM_NUM_REQS_14_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_14_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_14_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_14_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_14_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_14_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_15_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_15_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_15_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_15_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_15_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_15_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_15_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_15_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_15_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_15_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_WB_count, 0, 0 | |
| DRAM_NUM_REQS_15_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_15_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_15_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_15_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_15_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_15_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_16_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_16_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_16_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_16_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_16_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_16_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_16_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_16_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_16_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_16_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_WB_count, 0, 0 | |
| DRAM_NUM_REQS_16_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_16_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_16_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_16_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_16_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_16_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_17_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_17_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_17_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_17_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_17_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_17_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_17_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_17_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_17_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_17_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_WB_count, 0, 0 | |
| DRAM_NUM_REQS_17_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_17_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_17_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_17_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_17_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_17_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_18_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_18_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_18_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_18_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_18_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_18_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_18_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_18_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_18_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_18_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_WB_count, 0, 0 | |
| DRAM_NUM_REQS_18_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_18_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_18_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_18_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_18_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_18_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_19_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_19_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_19_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_19_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_19_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_19_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_19_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_19_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_19_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_19_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_WB_count, 0, 0 | |
| DRAM_NUM_REQS_19_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_19_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_19_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_19_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_19_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_19_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_20_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_20_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_20_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_20_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_20_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_20_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_20_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_20_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_20_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_20_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_WB_count, 0, 0 | |
| DRAM_NUM_REQS_20_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_20_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_20_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_20_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_20_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_20_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_21_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_21_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_21_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_21_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_21_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_21_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_21_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_21_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_21_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_21_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_WB_count, 0, 0 | |
| DRAM_NUM_REQS_21_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_21_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_21_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_21_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_21_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_21_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_22_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_22_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_22_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_22_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_22_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_22_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_22_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_22_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_22_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_22_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_WB_count, 0, 0 | |
| DRAM_NUM_REQS_22_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_22_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_22_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_22_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_22_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_22_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_23_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_23_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_23_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_23_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_23_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_23_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_23_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_23_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_23_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_23_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_WB_count, 0, 0 | |
| DRAM_NUM_REQS_23_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_23_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_23_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_23_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_23_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_23_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_24_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_24_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_24_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_24_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_24_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_24_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_24_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_24_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_24_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_24_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_WB_count, 0, 0 | |
| DRAM_NUM_REQS_24_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_24_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_24_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_24_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_24_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_24_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_25_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_25_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_25_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_25_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_25_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_25_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_25_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_25_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_25_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_25_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_WB_count, 0, 0 | |
| DRAM_NUM_REQS_25_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_25_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_25_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_25_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_25_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_25_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_26_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_26_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_26_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_26_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_26_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_26_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_26_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_26_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_26_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_26_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_WB_count, 0, 0 | |
| DRAM_NUM_REQS_26_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_26_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_26_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_26_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_26_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_26_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_27_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_27_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_27_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_27_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_27_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_27_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_27_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_27_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_27_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_27_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_WB_count, 0, 0 | |
| DRAM_NUM_REQS_27_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_27_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_27_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_27_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_27_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_27_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_28_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_28_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_28_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_28_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_28_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_28_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_28_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_28_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_28_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_28_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_WB_count, 0, 0 | |
| DRAM_NUM_REQS_28_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_28_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_28_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_28_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_28_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_28_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_29_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_29_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_29_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_29_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_29_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_29_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_29_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_29_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_29_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_29_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_WB_count, 0, 0 | |
| DRAM_NUM_REQS_29_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_29_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_29_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_29_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_29_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_29_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_30_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_30_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_30_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_30_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_30_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_30_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_30_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_30_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_30_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_30_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_WB_count, 0, 0 | |
| DRAM_NUM_REQS_30_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_30_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_30_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_30_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_30_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_30_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_31_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_31_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_31_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_31_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_31_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_31_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_31_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_31_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_31_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_31_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_WB_count, 0, 0 | |
| DRAM_NUM_REQS_31_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_31_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_31_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_31_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_31_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_31_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_IFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_32_IFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_32_IFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_IFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_DFETCH_count, 0, 0 | |
| DRAM_NUM_REQS_32_DFETCH_pct, 0, -nan | |
| DRAM_NUM_REQS_32_DFETCH_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_DFETCH_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_DSTORE_count, 0, 0 | |
| DRAM_NUM_REQS_32_DSTORE_pct, 0, -nan | |
| DRAM_NUM_REQS_32_DSTORE_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_DSTORE_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_IPRF_count, 0, 0 | |
| DRAM_NUM_REQS_32_IPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_32_IPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_IPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_DPRF_count, 0, 0 | |
| DRAM_NUM_REQS_32_DPRF_pct, 0, -nan | |
| DRAM_NUM_REQS_32_DPRF_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_DPRF_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_WB_count, 0, 0 | |
| DRAM_NUM_REQS_32_WB_pct, 0, -nan | |
| DRAM_NUM_REQS_32_WB_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_WB_total_pct, 0, -nan | |
| DRAM_NUM_REQS_32_WB_NODIRTY_count, 0, 0 | |
| DRAM_NUM_REQS_32_WB_NODIRTY_pct, 0, -nan | |
| DRAM_NUM_REQS_32_WB_NODIRTY_total_count, 0, 0 | |
| DRAM_NUM_REQS_32_WB_NODIRTY_total_pct, 0, -nan | |
| DRAM_BOTTLENECK_BUS_0_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_0_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_10_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_10_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_20_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_20_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_30_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_30_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_40_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_40_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_50_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_50_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_60_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_60_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_70_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_70_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_80_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_80_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_90_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_90_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_100_count, 394, 0 | |
| DRAM_BOTTLENECK_BUS_100_total_count, 394, 0 | |
| DRAM_BOTTLENECK_BANKS_0_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_0_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_10_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_10_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_20_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_20_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_30_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_30_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_40_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_40_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_50_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_50_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_60_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_60_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_70_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_70_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_80_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_80_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_90_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_90_total_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_100_count, 395, 0 | |
| DRAM_BOTTLENECK_BANKS_100_total_count, 395, 0 | |
| DRAM_BOTTLENECK_FAW_0_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_0_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_10_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_10_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_20_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_20_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_30_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_30_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_40_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_40_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_50_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_50_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_60_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_60_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_70_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_70_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_80_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_80_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_90_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_90_total_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_100_count, 396, 0 | |
| DRAM_BOTTLENECK_FAW_100_total_count, 396, 0 | |
| DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING_count, 0, 0 | |
| DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING_total_count, 0, 0 | |
| KNOWN_BAD_ADDRESS_count, 397, 0 | |
| KNOWN_BAD_ADDRESS_total_count, 397, 0 | |
| GOOD_ADDRESS_count, 397, 393319 | |
| GOOD_ADDRESS_total_count, 397, 393319 | |
| BBL_LENGTH_1_count, 398, 0 | |
| BBL_LENGTH_1_total_count, 398, 0 | |
| BBL_LENGTH_2_count, 398, 0 | |
| BBL_LENGTH_2_total_count, 398, 0 | |
| BBL_LENGTH_3_count, 398, 0 | |
| BBL_LENGTH_3_total_count, 398, 0 | |
| BBL_LENGTH_4_count, 398, 0 | |
| BBL_LENGTH_4_total_count, 398, 0 | |
| BBL_LENGTH_5_count, 398, 0 | |
| BBL_LENGTH_5_total_count, 398, 0 | |
| BBL_LENGTH_6_count, 398, 0 | |
| BBL_LENGTH_6_total_count, 398, 0 | |
| BBL_LENGTH_7_count, 398, 0 | |
| BBL_LENGTH_7_total_count, 398, 0 | |
| BBL_LENGTH_8_count, 398, 0 | |
| BBL_LENGTH_8_total_count, 398, 0 | |
| BBL_LENGTH_9_count, 398, 0 | |
| BBL_LENGTH_9_total_count, 398, 0 | |
| BBL_LENGTH_10_count, 398, 0 | |
| BBL_LENGTH_10_total_count, 398, 0 | |
| BBL_LENGTH_11_count, 398, 0 | |
| BBL_LENGTH_11_total_count, 398, 0 | |
| BBL_LENGTH_12_count, 398, 0 | |
| BBL_LENGTH_12_total_count, 398, 0 | |
| BBL_LENGTH_13_count, 398, 0 | |
| BBL_LENGTH_13_total_count, 398, 0 | |
| BBL_LENGTH_14_count, 398, 0 | |
| BBL_LENGTH_14_total_count, 398, 0 | |
| BBL_LENGTH_15_count, 398, 0 | |
| BBL_LENGTH_15_total_count, 398, 0 | |
| BBL_LENGTH_16_count, 398, 0 | |
| BBL_LENGTH_16_total_count, 398, 0 | |
| BBL_LENGTH_17_count, 398, 0 | |
| BBL_LENGTH_17_total_count, 398, 0 | |
| BBL_LENGTH_18_count, 398, 0 | |
| BBL_LENGTH_18_total_count, 398, 0 | |
| BBL_LENGTH_19_count, 398, 0 | |
| BBL_LENGTH_19_total_count, 398, 0 | |
| BBL_LENGTH_20_count, 398, 0 | |
| BBL_LENGTH_20_total_count, 398, 0 | |
| BBL_LENGTH_21_count, 398, 0 | |
| BBL_LENGTH_21_total_count, 398, 0 | |
| BBL_LENGTH_22_count, 398, 0 | |
| BBL_LENGTH_22_total_count, 398, 0 | |
| BBL_LENGTH_23_count, 398, 0 | |
| BBL_LENGTH_23_total_count, 398, 0 | |
| BBL_LENGTH_24_count, 398, 0 | |
| BBL_LENGTH_24_total_count, 398, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_1_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_1_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_2_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_2_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_3_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_3_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_4_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_4_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_5_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_5_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_6_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_6_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_7_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_7_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_8_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_8_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_9_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_9_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_10_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_10_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_11_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_11_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_12_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_12_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_13_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_13_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_14_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_14_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_15_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_15_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_16_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_16_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_17_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_17_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_18_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_18_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_19_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_19_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_20_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_20_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_21_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_21_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_22_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_22_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_23_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_23_total_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_24_count, 399, 0 | |
| BBL_DONT_END_PRED_NT_LENGTH_24_total_count, 399, 0 | |
| DATA_LD_CYCLES_ONPATH_count, 0, 1228654 | |
| DATA_LD_CYCLES_ONPATH_total_count, 0, 1228654 | |
| DATA_LD_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_MLC_CYCLES_ONPATH_count, 0, 0 | |
| DATA_LD_MLC_CYCLES_ONPATH_total_count, 0, 0 | |
| DATA_LD_MLC_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_MLC_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_MLC_ACCESSES_ONPATH_count, 0, 0 | |
| DATA_LD_MLC_ACCESSES_ONPATH_total_count, 0, 0 | |
| DATA_LD_MLC_ACCESSES_OFFPATH_count, 0, 0 | |
| DATA_LD_MLC_ACCESSES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_L1_CYCLES_ONPATH_count, 0, 856739 | |
| DATA_LD_L1_CYCLES_ONPATH_total_count, 0, 856739 | |
| DATA_LD_L1_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_L1_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_L1_ACCESSES_ONPATH_count, 0, 14521 | |
| DATA_LD_L1_ACCESSES_ONPATH_total_count, 0, 14521 | |
| DATA_LD_L1_ACCESSES_OFFPATH_count, 0, 0 | |
| DATA_LD_L1_ACCESSES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_MEM_CYCLES_ONPATH_count, 0, 371915 | |
| DATA_LD_MEM_CYCLES_ONPATH_total_count, 0, 371915 | |
| DATA_LD_MEM_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_MEM_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_MEM_ACCESSES_ONPATH_count, 0, 505 | |
| DATA_LD_MEM_ACCESSES_ONPATH_total_count, 0, 505 | |
| DATA_LD_MEM_ACCESSES_OFFPATH_count, 0, 0 | |
| DATA_LD_MEM_ACCESSES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_PREF_CYCLES_ONPATH_count, 0, 0 | |
| DATA_LD_PREF_CYCLES_ONPATH_total_count, 0, 0 | |
| DATA_LD_PREF_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_PREF_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_PREF_MLC_CYCLES_ONPATH_count, 0, 0 | |
| DATA_LD_PREF_MLC_CYCLES_ONPATH_total_count, 0, 0 | |
| DATA_LD_PREF_MLC_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_PREF_MLC_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_PREF_L1_CYCLES_ONPATH_count, 0, 0 | |
| DATA_LD_PREF_L1_CYCLES_ONPATH_total_count, 0, 0 | |
| DATA_LD_PREF_L1_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_PREF_L1_CYCLES_OFFPATH_total_count, 0, 0 | |
| DATA_LD_PREF_MEM_CYCLES_ONPATH_count, 0, 0 | |
| DATA_LD_PREF_MEM_CYCLES_ONPATH_total_count, 0, 0 | |
| DATA_LD_PREF_MEM_CYCLES_OFFPATH_count, 0, 0 | |
| DATA_LD_PREF_MEM_CYCLES_OFFPATH_total_count, 0, 0 | |
| UOP_CACHE_LINE_EVICTED_USEFUL_count, 400, 0 | |
| UOP_CACHE_LINE_EVICTED_USEFUL_total_count, 400, 0 | |
| UOP_CACHE_LINE_EVICTED_USELESS_count, 400, 7 | |
| UOP_CACHE_LINE_EVICTED_USELESS_total_count, 400, 7 | |