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hpca2027-database-validated-traces-20260711

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hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /12 /memory.stat.0.out
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/* -*- Mode: c -*- */
####################################################################################################
Core 0
####################################################################################################
Cumulative: Cycles: 336256 Instructions: 961103 IPC: 2.85825
Periodic: Cycles: 336256 Instructions: 961103 IPC: 2.85825
ICACHE_MISS 34 43.038% 34 43.038%
ICACHE_HIT 45 56.962% 45 56.962%
 79 100.000% 79 100.000%
 0.57 0.54 0.57 0.54
ICACHE_MISS_ONPATH 7 20.588% 7 20.588%
ICACHE_MISS_OFFPATH 27 79.412% 27 79.412%
 34 100.000% 34 100.000%
 0.79 0.74 0.79 0.74
ICACHE_MISS_NOT_PREFETCHED 2 6.061% 2 6.061%
ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH 0 0.000% 0 0.000%
ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP 0 0.000% 0 0.000%
ICACHE_MISS_MSHR_HIT_PREFETCHED_OFFPATH 27 81.818% 27 81.818%
ICACHE_MISS_MSHR_HIT_PREFETCHED_ONPATH 4 12.121% 4 12.121%
 33 100.000% 33 100.000%
 2.94 1.11 2.94 1.11
ICACHE_HIT_ONPATH 9 20.000% 9 20.000%
ICACHE_HIT_OFFPATH 36 80.000% 36 80.000%
 45 100.000% 45 100.000%
 0.80 0.75 0.80 0.75
ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan%
ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan%
ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_HIT_BY_FDIP_ONPATH 0 -nan% 0 -nan%
ICACHE_HIT_BY_FDIP_OFFPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_MISS_MSHR_HIT_BY_FDIP_ONPATH 3 9.677% 3 9.677%
ICACHE_MISS_MSHR_HIT_BY_FDIP_OFFPATH 28 90.323% 28 90.323%
 31 100.000% 31 100.000%
 0.90 0.88 0.90 0.88
ICACHE_HIT_ONPATH_BY_FDIP 0 0.000% 0 0.000%
ICACHE_HIT_OFFPATH_BY_FDIP 0 0.000% 0 0.000%
ICACHE_MISS_MSHR_HIT_ONPATH_BY_FDIP 5 14.706% 5 14.706%
ICACHE_MISS_MSHR_HIT_OFFPATH_BY_FDIP 26 76.471% 26 76.471%
ICACHE_MISS_TOO_EARLY_ONPATH 0 0.000% 0 0.000%
ICACHE_MISS_TOO_EARLY_OFFPATH 0 0.000% 0 0.000%
ICACHE_MISS_NOT_PREFETCHED_ONPATH 2 5.882% 2 5.882%
ICACHE_MISS_NOT_PREFETCHED_OFFPATH 1 2.941% 1 2.941%
 34 100.000% 34 100.000%
 3.15 1.21 3.15 1.21
ICACHE_MISS_MEM_REQ_FAIL_ON_PATH 0 0.000% 0 0.000%
ICACHE_MISS_MEM_REQ_SUCCESS_ON_PATH 2 100.000% 2 100.000%
 2 100.000% 2 100.000%
 1.00 1.41 1.00 1.41
ICACHE_UNIQUE_MISSED_LINES 5 5
ICACHE_UNIQUE_HIT_LINES 0 0
ICACHE_OVERTAKE_FDIP 0 0
FT_UOP_CACHE_HIT_ON_PATH 150162 99.989% 150162 99.989%
FT_UOP_CACHE_MISS_ICACHE_HIT_ON_PATH 9 0.006% 9 0.006%
FT_UOP_CACHE_MISS_ICACHE_MISS_ON_PATH 7 0.005% 7 0.005%
 150178 100.000% 150178 100.000%
 0.00 0.02 0.00 0.02
FT_UOP_CACHE_HIT_OFF_PATH 132 67.692% 132 67.692%
FT_UOP_CACHE_MISS_ICACHE_HIT_OFF_PATH 36 18.462% 36 18.462%
FT_UOP_CACHE_MISS_ICACHE_MISS_OFF_PATH 27 13.846% 27 13.846%
 195 100.000% 195 100.000%
 0.46 0.64 0.46 0.64
UOPS_SERVED_BY_ICACHE_ON_PATH 101 0.008% 101 0.008%
UOPS_SERVED_BY_UOP_CACHE_ON_PATH 1261349 99.992% 1261349 99.992%
 1261450 100.000% 1261450 100.000%
 1.00 1.00 1.00 1.00
UOPS_SERVED_BY_ICACHE_OFF_PATH 1098 46.466% 1098 46.466%
UOPS_SERVED_BY_UOP_CACHE_OFF_PATH 1265 53.534% 1265 53.534%
 2363 100.000% 2363 100.000%
 0.54 0.52 0.54 0.52
UOP_CACHE_FT_INSERTED_ONPATH_USED_ONPATH 4 4
UOP_CACHE_FT_INSERTED_OFFPATH_USED_ONPATH 6 6
UOP_CACHE_LINE_INSERTED_ONPATH_USED_ONPATH 9 9
UOP_CACHE_LINE_INSERTED_OFFPATH_USED_ONPATH 7 7
UOP_CACHE_PREFETCH 0 0
UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_ON_PATH 1 6.667% 1 6.667%
UOP_CACHE_FT_INSERT_SUCCEEDED_ON_PATH 14 93.333% 14 93.333%
 15 100.000% 15 100.000%
 2.93 2.94 2.93 2.94
UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_INSERT_SUCCEEDED_OFF_PATH 51 100.000% 51 100.000%
 51 100.000% 51 100.000%
 3.00 3.03 3.00 3.03
UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_ON_PATH 1 3.846% 1 3.846%
UOP_CACHE_LINE_INSERT_SUCCEEDED_ON_PATH 25 96.154% 25 96.154%
 26 100.000% 26 100.000%
 2.96 2.97 2.96 2.97
UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_LINE_INSERT_SUCCEEDED_OFF_PATH 141 100.000% 141 100.000%
 141 100.000% 141 100.000%
 3.00 3.01 3.00 3.01
UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_RESTEERED 0 -nan% 0 -nan%
UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_CORRECT_PRED 0 -nan% 0 -nan%
UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_RESTEERED 0 -nan% 0 -nan%
UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_CORRECT_PRED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
UOP_CACHE_FT_LINES_1_ON_PATH 8 53.333% 8 53.333%
UOP_CACHE_FT_LINES_2_ON_PATH 3 20.000% 3 20.000%
UOP_CACHE_FT_LINES_3_ON_PATH 4 26.667% 4 26.667%
UOP_CACHE_FT_LINES_4_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_5_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_6_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_7_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_8_ON_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_9_AND_MORE_ON_PATH 0 0.000% 0 0.000%
 15 100.000% 15 100.000%
 0.73 0.69 0.73 0.69
UOP_CACHE_FT_LINES_1_OFF_PATH 5 9.804% 5 9.804%
UOP_CACHE_FT_LINES_2_OFF_PATH 3 5.882% 3 5.882%
UOP_CACHE_FT_LINES_3_OFF_PATH 42 82.353% 42 82.353%
UOP_CACHE_FT_LINES_4_OFF_PATH 1 1.961% 1 1.961%
UOP_CACHE_FT_LINES_5_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_6_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_7_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_8_OFF_PATH 0 0.000% 0 0.000%
UOP_CACHE_FT_LINES_9_AND_MORE_OFF_PATH 0 0.000% 0 0.000%
 51 100.000% 51 100.000%
 1.76 0.33 1.76 0.33
UOP_CACHE_PREFETCH_PW_LENGTH_1 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_2 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_3 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_4 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_5 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_6 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_7 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_8 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_9 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_10 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_11 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_12 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_13 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_14 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_15 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_16 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_17 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_18 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_19 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_20 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_21 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_22 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_23 0 -nan% 0 -nan%
UOP_CACHE_PREFETCH_PW_LENGTH_24 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DCACHE_MISS 30047 6.669% 30047 6.669%
DCACHE_ST_BUFFER_HIT 0 0.000% 0 0.000%
DCACHE_HIT 420471 93.331% 420471 93.331%
 450518 100.000% 450518 100.000%
 1.87 1.81 1.87 1.81
DCACHE_MISS_ONPATH 30047 99.953% 30047 99.953%
DCACHE_MISS_OFFPATH 14 0.047% 14 0.047%
 30061 100.000% 30061 100.000%
 0.00 0.02 0.00 0.02
DCACHE_ST_BUFFER_HIT_ONPATH 0 -nan% 0 -nan%
DCACHE_ST_BUFFER_HIT_OFFPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DCACHE_HIT_ONPATH 420471 99.960% 420471 99.960%
DCACHE_HIT_OFFPATH 167 0.040% 167 0.040%
 420638 100.000% 420638 100.000%
 0.00 0.02 0.00 0.02
DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 0.000% 0 0.000%
DCACHE_HIT_ONPATH_SAT_BY_ONPATH 420471 100.000% 420471 100.000%
 420471 100.000% 420471 100.000%
 1.00 1.00 1.00 1.00
DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 0.000% 0 0.000%
DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 167 100.000% 167 100.000%
 167 100.000% 167 100.000%
 1.00 1.00 1.00 1.00
DCACHE_MISS_LD 30044 99.990% 30044 99.990%
DCACHE_MISS_ST 3 0.010% 3 0.010%
 30047 100.000% 30047 100.000%
 0.00 0.01 0.00 0.01
DCACHE_MISS_LD_ONPATH 30044 99.973% 30044 99.973%
DCACHE_MISS_LD_OFFPATH 8 0.027% 8 0.027%
 30052 100.000% 30052 100.000%
 0.00 0.02 0.00 0.02
DCACHE_MISS_ST_ONPATH 3 33.333% 3 33.333%
DCACHE_MISS_ST_OFFPATH 6 66.667% 6 66.667%
 9 100.000% 9 100.000%
 0.67 0.65 0.67 0.65
DCACHE_MISS_WAITMEM 1 1
MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan%
MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan%
MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
SHADOW_ROW_BUFFER_HITS 0 0
SHADOW_ROW_HIT_STALL_TIME 0 0
CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL6_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
CHANNEL7_BUS_BUSY_CYCLES 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CHANNEL_IDLE_DESPITE_READY_CMD 0 0
MEM_NUM_TOTAL_BUS_CYCLES 0 0
MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CORE_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan
RAMULATOR_QUEUE_ENQUEUED 0 0
RAMULATOR_QUEUE_FULL 0 0
BUS_DEMAND_ACCESS 117 117
BUS_PREF_ACCESS 15026 15026
BUS_ACCESS 0 0
L1_DEMAND_ACCESS 30542 30542
L1_PREF_ACCESS 30150 30150
L1_ACCESS 44985 44985
MLC_DEMAND_ACCESS 29052 29052
MLC_PREF_ACCESS 100 100
MLC_ACCESS 29152 29152
L1_HIT 14521 99.856% 14521 99.856%
L1_MISS 21 0.144% 21 0.144%
 14542 100.000% 14542 100.000%
 0.00 0.04 0.00 0.04
L1_HIT_ALL 15202 50.097% 15202 50.097%
L1_MISS_ALL 15143 49.903% 15143 49.903%
 30345 100.000% 30345 100.000%
 0.50 0.50 0.50 0.50
L1_DEMAND_MISS 20 0.132% 20 0.132%
L1_PREF_REQ_MISS 15026 99.227% 15026 99.227%
L1_WB_MISS 97 0.641% 97 0.641%
 15143 100.000% 15143 100.000%
 1.01 0.11 1.01 0.11
L1_DEMAND_HIT 14521 95.520% 14521 95.520%
L1_PREF_REQ_HIT 0 0.000% 0 0.000%
L1_WB_HIT 681 4.480% 681 4.480%
 15202 100.000% 15202 100.000%
 0.09 0.40 0.09 0.40
L1_MISS_ONPATH 21 100.000% 21 100.000%
L1_MISS_OFFPATH 0 0.000% 0 0.000%
 21 100.000% 21 100.000%
 0.00 0.00 0.00 0.00
L1_MISS_ALL_ONPATH 15047 99.366% 15047 99.366%
L1_MISS_ALL_OFFPATH 96 0.634% 96 0.634%
 15143 100.000% 15143 100.000%
 0.01 0.08 0.01 0.08
L1_HIT_ONPATH 14521 100.000% 14521 100.000%
L1_HIT_OFFPATH 0 0.000% 0 0.000%
 14521 100.000% 14521 100.000%
 0.00 0.00 0.00 0.00
L1_HIT_ALL_ONPATH 15202 100.000% 15202 100.000%
L1_HIT_ALL_OFFPATH 0 0.000% 0 0.000%
 15202 100.000% 15202 100.000%
 0.00 0.00 0.00 0.00
L1_HIT_ONPATH_SAT_BY_OFFPATH 0 0.000% 0 0.000%
L1_HIT_ONPATH_SAT_BY_ONPATH 15202 100.000% 15202 100.000%
 15202 100.000% 15202 100.000%
 1.00 1.00 1.00 1.00
L1_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan%
L1_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_HIT_ONPATH_IFETCH_SAT_BY_OFFPATH 0 -nan% 0 -nan%
L1_HIT_ONPATH_IFETCH_SAT_BY_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_HIT_ONPATH_DATA_SAT_BY_OFFPATH 0 0.000% 0 0.000%
L1_HIT_ONPATH_DATA_SAT_BY_ONPATH 14521 100.000% 14521 100.000%
 14521 100.000% 14521 100.000%
 1.00 1.00 1.00 1.00
L1_FILL_OFFPATH_IFETCH 0 0
L1_FILL_OFFPATH_DATA 0 0
L1_FILL_OFFPATH 96 96
L1_USE_OFFPATH_IFETCH 0 -nan 0 -nan
L1_USE_OFFPATH_DATA 0 -nan 0 -nan
L1_USE_OFFPATH 0 0.0000 0 0.0000
JUST_L1_USE_OFFPATH 0 0.0000 0 0.0000
L1_FILL_ONPATH_IFETCH 6 6
L1_FILL_ONPATH_DATA 505 505
L1_FILL_ONPATH 512 512
L1_USE_ONPATH_IFETCH 0 0.0000 0 0.0000
L1_USE_ONPATH_DATA 14521 28.7545 14521 28.7545
L1_USE_ONPATH 15202 29.6914 15202 29.6914
L1_CYCLE 336256 336256
L1_LINES 2551878659 7589.0948 2551878659 7589.0948
MLC_HIT 0 0.000% 0 0.000%
MLC_MISS 14541 100.000% 14541 100.000%
 14541 100.000% 14541 100.000%
 1.00 1.00 1.00 1.00
MLC_HIT_ALL 14513 49.786% 14513 49.786%
MLC_MISS_ALL 14638 50.214% 14638 50.214%
 29151 100.000% 29151 100.000%
 0.50 0.50 0.50 0.50
MLC_DEMAND_MISS 14541 99.337% 14541 99.337%
MLC_PREF_REQ_MISS 0 0.000% 0 0.000%
MLC_WB_MISS 97 0.663% 97 0.663%
 14638 100.000% 14638 100.000%
 0.01 0.16 0.01 0.16
MLC_DEMAND_HIT 0 0.000% 0 0.000%
MLC_PREF_REQ_HIT 0 0.000% 0 0.000%
MLC_WB_HIT 14513 100.000% 14513 100.000%
 14513 100.000% 14513 100.000%
 2.00 2.00 2.00 2.00
MLC_MISS_ONPATH 14540 99.993% 14540 99.993%
MLC_MISS_OFFPATH 1 0.007% 1 0.007%
 14541 100.000% 14541 100.000%
 0.00 0.01 0.00 0.01
MLC_MISS_ALL_ONPATH 14541 99.337% 14541 99.337%
MLC_MISS_ALL_OFFPATH 97 0.663% 97 0.663%
 14638 100.000% 14638 100.000%
 0.01 0.08 0.01 0.08
MLC_HIT_ONPATH 0 -nan% 0 -nan%
MLC_HIT_OFFPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_HIT_ALL_ONPATH 14513 100.000% 14513 100.000%
MLC_HIT_ALL_OFFPATH 0 0.000% 0 0.000%
 14513 100.000% 14513 100.000%
 0.00 0.00 0.00 0.00
L1_QUEUE_OCCUPANCY 1138509 3.3858 1138509 3.3858
MLC_QUEUE_OCCUPANCY 1108164 3.2956 1108164 3.2956
DCACHE_FILL_PORT_UNAVAILABLE_ONPATH 0 0
DCACHE_FILL_PORT_UNAVAILABLE_OFFPATH 0 0
DCACHE_READ_PORT_UNAVAILABLE_ONPATH 93381 93381
DCACHE_READ_PORT_UNAVAILABLE_OFFPATH 31 31
DCACHE_FILL_OFFPATH 0 0
DCACHE_USE_OFFPATH 0 -nan 0 -nan
DCACHE_FILL_ONPATH 15026 15026
DCACHE_USE_ONPATH 420471 27.9829 420471 27.9829
ICACHE_FILL_OFFPATH 96 96
ICACHE_USE_OFFPATH 0 0.0000 0 0.0000
ICACHE_FILL_ONPATH 7 7
ICACHE_USE_ONPATH 0 0.0000 0 0.0000
REQBUF_CREATE_ONPATH 44764 44764
REQBUF_ONPATH_MATCH_OFFPATH 1 0.0000 1 0.0000
REQBUF_CREATE_ONPATH_DATA 14535 14535
REQBUF_ONPATH_MATCH_OFFPATH_DATA 0 0.0000 0 0.0000
REQBUF_CREATE_ONPATH_IFETCH 2 2
REQBUF_ONPATH_MATCH_OFFPATH_IFETCH 1 0.5000 1 0.5000
REQBUF_CREATE_OFFPATH 97 97
ONPATH_KICKED_OUT_OFFPATH 0 0
ONPATH_KICKED_OUT_PREFETCH 0 0
DIST_ICACHE_FILL_OFFPATH_USED 0 0.000% 0 0.000%
DIST_ICACHE_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_ICACHE_FILL_ONPATH_PARTIAL 1 14.286% 1 14.286%
DIST_ICACHE_FILL_ONPATH 6 85.714% 6 85.714%
 7 100.000% 7 100.000%
 2.86 2.88 2.86 2.88
DIST_DCACHE_FILL_OFFPATH_USED 0 0.000% 0 0.000%
DIST_DCACHE_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_DCACHE_FILL_ONPATH_PARTIAL 0 0.000% 0 0.000%
DIST_DCACHE_FILL_ONPATH 15026 100.000% 15026 100.000%
 15026 100.000% 15026 100.000%
 3.00 3.00 3.00 3.00
DIST_L1_FILL_OFFPATH_USED 0 0.000% 0 0.000%
DIST_L1_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_L1_FILL_ONPATH_PARTIAL 1 0.195% 1 0.195%
DIST_L1_FILL_ONPATH 511 99.805% 511 99.805%
 512 100.000% 512 100.000%
 3.00 3.00 3.00 3.00
DIST_JUST_L1_FILL_OFFPATH_USED 0 -nan% 0 -nan%
DIST_JUST_L1_FILL_OFFPATH_NOTUSED 0 -nan% 0 -nan%
DIST_JUST_L1_FILL_ONPATH_PARTIAL 0 -nan% 0 -nan%
DIST_JUST_L1_FILL_ONPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_REQBUF_OFFPATH_USED 1 0.003% 1 0.003%
DIST_REQBUF_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST_REQBUF_ONPATH 29568 99.997% 29568 99.997%
 29569 100.000% 29569 100.000%
 2.00 2.00 2.00 2.00
DIST2_REQBUF_OFFPATH_USED_PARTIAL 1 0.003% 1 0.003%
DIST2_REQBUF_OFFPATH_USED_FULL 0 0.000% 0 0.000%
DIST2_REQBUF_OFFPATH_NOTUSED 0 0.000% 0 0.000%
DIST2_REQBUF_ONPATH 29568 99.997% 29568 99.997%
 29569 100.000% 29569 100.000%
 3.00 3.00 3.00 3.00
DIST_ICACHE_FILL 103 103
DIST_DCACHE_FILL 15026 15026
DIST_L1_FILL 608 608
DIST_USED_OFFPATH_ICACHE 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_ICACHE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_USED_OFFPATH_DCACHE 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_DCACHE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_USED_OFFPATH_L1 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_L1 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_USED_OFFPATH_JUST_L1 0 -nan% 0 -nan%
DIST_NOTUSED_OFFPATH_JUST_L1 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_ICACHE_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_ICACHE_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_ICACHE_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_DCACHE_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_DCACHE_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_DCACHE_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_L1_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_L1_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_L1_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIST_OFFPATH_JUST_L1_FULL 0 -nan% 0 -nan%
DIST_OFFPATH_JUST_L1_PARTIAL 0 -nan% 0 -nan%
DIST_OFFPATH_JUST_L1_NOTUSED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_MISS_ONPATH_IFETCH 5 0.034% 5 0.034%
MLC_MISS_ONPATH_DFETCH 14533 99.945% 14533 99.945%
MLC_MISS_ONPATH_DSTORE 2 0.014% 2 0.014%
MLC_MISS_ONPATH_IPRF 0 0.000% 0 0.000%
MLC_MISS_ONPATH_DPRF 0 0.000% 0 0.000%
MLC_MISS_ONPATH_WB 1 0.007% 1 0.007%
MLC_MISS_ONPATH_WB_NODIRTY 0 0.000% 0 0.000%
 14541 100.000% 14541 100.000%
 1.00 0.04 1.00 0.04
MLC_MISS_OFFPATH_IFETCH 1 1.031% 1 1.031%
MLC_MISS_OFFPATH_DFETCH 0 0.000% 0 0.000%
MLC_MISS_OFFPATH_DSTORE 0 0.000% 0 0.000%
MLC_MISS_OFFPATH_IPRF 0 0.000% 0 0.000%
MLC_MISS_OFFPATH_DPRF 0 0.000% 0 0.000%
MLC_MISS_OFFPATH_WB 96 98.969% 96 98.969%
MLC_MISS_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 97 100.000% 97 100.000%
 4.95 0.05 4.95 0.05
MLC_HIT_ONPATH_IFETCH 0 0.000% 0 0.000%
MLC_HIT_ONPATH_DFETCH 0 0.000% 0 0.000%
MLC_HIT_ONPATH_DSTORE 0 0.000% 0 0.000%
MLC_HIT_ONPATH_IPRF 0 0.000% 0 0.000%
MLC_HIT_ONPATH_DPRF 0 0.000% 0 0.000%
MLC_HIT_ONPATH_WB 0 0.000% 0 0.000%
MLC_HIT_ONPATH_WB_NODIRTY 14513 100.000% 14513 100.000%
 14513 100.000% 14513 100.000%
 6.00 6.00 6.00 6.00
MLC_HIT_OFFPATH_IFETCH 0 -nan% 0 -nan%
MLC_HIT_OFFPATH_DFETCH 0 -nan% 0 -nan%
MLC_HIT_OFFPATH_DSTORE 0 -nan% 0 -nan%
MLC_HIT_OFFPATH_IPRF 0 -nan% 0 -nan%
MLC_HIT_OFFPATH_DPRF 0 -nan% 0 -nan%
MLC_HIT_OFFPATH_WB 0 -nan% 0 -nan%
MLC_HIT_OFFPATH_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_MISS_ONPATH_IFETCH 6 0.040% 6 0.040%
L1_MISS_ONPATH_DFETCH 13 0.086% 13 0.086%
L1_MISS_ONPATH_DSTORE 2 0.013% 2 0.013%
L1_MISS_ONPATH_IPRF 0 0.000% 0 0.000%
L1_MISS_ONPATH_DPRF 0 0.000% 0 0.000%
L1_MISS_ONPATH_WB 1 0.007% 1 0.007%
L1_MISS_ONPATH_WB_NODIRTY 15025 99.854% 15025 99.854%
 15047 100.000% 15047 100.000%
 5.99 5.99 5.99 5.99
L1_MISS_OFFPATH_IFETCH 0 0.000% 0 0.000%
L1_MISS_OFFPATH_DFETCH 0 0.000% 0 0.000%
L1_MISS_OFFPATH_DSTORE 0 0.000% 0 0.000%
L1_MISS_OFFPATH_IPRF 0 0.000% 0 0.000%
L1_MISS_OFFPATH_DPRF 0 0.000% 0 0.000%
L1_MISS_OFFPATH_WB 96 100.000% 96 100.000%
L1_MISS_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 96 100.000% 96 100.000%
 5.00 0.00 5.00 0.00
L1_HIT_ONPATH_IFETCH 0 0.000% 0 0.000%
L1_HIT_ONPATH_DFETCH 14521 95.520% 14521 95.520%
L1_HIT_ONPATH_DSTORE 0 0.000% 0 0.000%
L1_HIT_ONPATH_IPRF 0 0.000% 0 0.000%
L1_HIT_ONPATH_DPRF 0 0.000% 0 0.000%
L1_HIT_ONPATH_WB 0 0.000% 0 0.000%
L1_HIT_ONPATH_WB_NODIRTY 681 4.480% 681 4.480%
 15202 100.000% 15202 100.000%
 1.22 1.07 1.22 1.07
L1_HIT_OFFPATH_IFETCH 0 -nan% 0 -nan%
L1_HIT_OFFPATH_DFETCH 0 -nan% 0 -nan%
L1_HIT_OFFPATH_DSTORE 0 -nan% 0 -nan%
L1_HIT_OFFPATH_IPRF 0 -nan% 0 -nan%
L1_HIT_OFFPATH_DPRF 0 -nan% 0 -nan%
L1_HIT_OFFPATH_WB 0 -nan% 0 -nan%
L1_HIT_OFFPATH_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_CYCLES 0 0
DRAM_UNBLOCK_CYCLES 0 -nan 0 -nan
DRAM_UNBLOCK_PERIODS 0 0
MEM_REQ_BUFFER_FULL 5 5
MEM_REQ_BUFFER_FULL_DENIED_DEMAND 1 1
CORE_MEM_BLOCKED 11 11
MEM_REQ_BUFFER_FULL_DENIED_IFETCH 0 0.000% 0 0.000%
MEM_REQ_BUFFER_FULL_DENIED_DFETCH 1 20.000% 1 20.000%
MEM_REQ_BUFFER_FULL_DENIED_DSTORE 0 0.000% 0 0.000%
MEM_REQ_BUFFER_FULL_DENIED_IPRF 0 0.000% 0 0.000%
MEM_REQ_BUFFER_FULL_DENIED_DPRF 0 0.000% 0 0.000%
MEM_REQ_BUFFER_FULL_DENIED_WB 4 80.000% 4 80.000%
MEM_REQ_BUFFER_FULL_DENIED_WB_NODIRTY 0 0.000% 0 0.000%
 5 100.000% 5 100.000%
 4.20 1.79 4.20 1.79
MEM_QUEUE_FULL 0 0
MEM_REQ_BUFFER_MISS 44861 74.201% 44861 74.201%
MEM_REQ_BUFFER_HIT 15598 25.799% 15598 25.799%
 60459 100.000% 60459 100.000%
 0.26 0.40 0.26 0.40
MEM_REQ_FDIP_BUFFER_HIT 59 59
MEM_REQ_FDIP_CYCLE_DELTA 9049 9049
MEM_REQ_DEMAND_ICACHE_BUFFER_HIT 13 13
MEM_REQ_DEMAND_ICACHE_CYCLE_DELTA 222 222
MEM_REQ_IFETCH 3 0.007% 3 0.007%
MEM_REQ_DFETCH 14533 32.396% 14533 32.396%
MEM_REQ_DSTORE 2 0.004% 2 0.004%
MEM_REQ_IPRF 0 0.000% 0 0.000%
MEM_REQ_DPRF 0 0.000% 0 0.000%
MEM_REQ_WB 100 0.223% 100 0.223%
MEM_REQ_WB_NODIRTY 30223 67.370% 30223 67.370%
 44861 100.000% 44861 100.000%
 4.38 4.29 4.38 4.29
LD_NO_FORWARD 120197 50.002% 120197 50.002%
FORWARDED_LD 120188 49.998% 120188 49.998%
 240385 100.000% 240385 100.000%
 0.50 0.50 0.50 0.50
WRONGPATH_L1Q_REMOVALS 0 -nan% 0 -nan%
WRONGPATH_BUSQ_REMOVALS 0 -nan% 0 -nan%
WRONGPATH_MEMQ_REMOVALS 0 -nan% 0 -nan%
WRONGPATH_L1FILLQ_REMOVALS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
WRONGPATH_L1Q_DEMOTIONS 0 -nan% 0 -nan%
WRONGPATH_BUSQ_DEMOTIONS 0 -nan% 0 -nan%
WRONGPATH_MEMQ_DEMOTIONS 0 -nan% 0 -nan%
WRONGPATH_L1FILLQ_DEMOTIONS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
PROMOTION_QMLC 3 75.000% 3 75.000%
PROMOTION_QL1 1 25.000% 1 25.000%
 4 100.000% 4 100.000%
 0.25 0.46 0.25 0.46
PROMOTION_QBUSOUT 0 0
PROMOTION_QMEM 0 0
PROMOTION_QL1FILL 0 0
PROMOTION_QMLC_FILL 0 0
NOPROMOTION_QMEM 0 0
NOPROMOTION_QL1FILL 0 -nan% 0 -nan%
NOPROMOTION_QMLC_FILL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
PROMOTION_FROM_FDIP_OFF_TO_ON 0 0
ICACHE_FILL_CORRECT_REQ 31 30.097% 31 30.097%
ICACHE_FILL_INCORRECT_REQ 72 69.903% 72 69.903%
 103 100.000% 103 100.000%
 0.70 0.64 0.70 0.64
ICACHE_FILL_CORRECT_REQ_BY_FDIP 28 27.184% 28 27.184%
ICACHE_FILL_INCORRECT_REQ_BY_FDIP 72 69.903% 72 69.903%
ICACHE_FILL_CORRECT_REQ_BY_ICACHE_DEMAND 3 2.913% 3 2.913%
ICACHE_FILL_INCORRECT_REQ_BY_ICACHE_DEMAND 0 0.000% 0 0.000%
 103 100.000% 103 100.000%
 0.76 0.29 0.76 0.29
ICACHE_FILL_CORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 1 1
ICACHE_FILL_CORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0
ICACHE_FILL_INCORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 3 3
ICACHE_FILL_INCORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA 19673 19673
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND 845 845
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_FDIP 8003 8003
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 153 153
ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA 67613 67613
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND 0 0
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_FDIP 27109 27109
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 0 0
ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0
MEM_REQ_INIT 44861 44861
MEM_REQ_COMPLETE 44855 0.9999 44855 0.9999
MEM_REQ_KILLED 0 0.0000 0 0.0000
MEM_REQ_COMPLETE_MLC 14513 0.3235 14513 0.3235
MEM_REQ_COMPLETE_L1 681 0.0152 681 0.0152
MEM_REQ_COMPLETE_MEM 29661 0.6612 29661 0.6612
MEM_REQ_INIT_ONPATH 44764 0.9978 44764 0.9978
MEM_REQ_INIT_OFFPATH 97 0.0022 97 0.0022
MEM_REQ_COMPLETE_ONPATH 44759 0.9979 44759 0.9979
MEM_REQ_COMPLETE_OFFPATH 96 0.0021 96 0.0021
MEM_REQ_INIT_IFETCH 3 0.020% 3 0.020%
MEM_REQ_INIT_DFETCH 14533 99.283% 14533 99.283%
MEM_REQ_INIT_DSTORE 2 0.014% 2 0.014%
MEM_REQ_INIT_IPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_DPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_WB 100 0.683% 100 0.683%
MEM_REQ_INIT_WB_NODIRTY 0 0.000% 0 0.000%
 14638 100.000% 14638 100.000%
 1.03 0.33 1.03 0.33
MEM_REQ_COMPLETE_IFETCH 15033 33.147% 15033 33.147%
MEM_REQ_COMPLETE_DFETCH 30220 66.634% 30220 66.634%
MEM_REQ_COMPLETE_DSTORE 2 0.004% 2 0.004%
MEM_REQ_COMPLETE_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_WB 97 0.214% 97 0.214%
MEM_REQ_COMPLETE_WB_NODIRTY 0 0.000% 0 0.000%
 45352 100.000% 45352 100.000%
 0.68 0.33 0.68 0.33
MEM_REQ_KILLED_IFETCH 29726 100.000% 29726 100.000%
MEM_REQ_KILLED_DFETCH 0 0.000% 0 0.000%
MEM_REQ_KILLED_DSTORE 0 0.000% 0 0.000%
MEM_REQ_KILLED_IPRF 0 0.000% 0 0.000%
MEM_REQ_KILLED_DPRF 0 0.000% 0 0.000%
MEM_REQ_KILLED_WB 0 0.000% 0 0.000%
MEM_REQ_KILLED_WB_NODIRTY 0 0.000% 0 0.000%
 29726 100.000% 29726 100.000%
 0.00 0.00 0.00 0.00
MEM_REQ_INIT_OFFPATH_IFETCH 1 1.031% 1 1.031%
MEM_REQ_INIT_OFFPATH_DFETCH 0 0.000% 0 0.000%
MEM_REQ_INIT_OFFPATH_DSTORE 0 0.000% 0 0.000%
MEM_REQ_INIT_OFFPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_OFFPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_OFFPATH_WB 96 98.969% 96 98.969%
MEM_REQ_INIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 97 100.000% 97 100.000%
 4.95 0.05 4.95 0.05
MEM_REQ_INIT_ONPATH_IFETCH 2 0.014% 2 0.014%
MEM_REQ_INIT_ONPATH_DFETCH 14533 99.945% 14533 99.945%
MEM_REQ_INIT_ONPATH_DSTORE 2 0.014% 2 0.014%
MEM_REQ_INIT_ONPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_ONPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_INIT_ONPATH_WB 4 0.028% 4 0.028%
MEM_REQ_INIT_ONPATH_WB_NODIRTY 0 0.000% 0 0.000%
 14541 100.000% 14541 100.000%
 1.00 0.07 1.00 0.07
MEM_REQ_MATCH_IFETCH 15071 33.613% 15071 33.613%
MEM_REQ_MATCH_DFETCH 29728 66.302% 29728 66.302%
MEM_REQ_MATCH_DSTORE 5 0.011% 5 0.011%
MEM_REQ_MATCH_IPRF 0 0.000% 0 0.000%
MEM_REQ_MATCH_DPRF 0 0.000% 0 0.000%
MEM_REQ_MATCH_WB 32 0.071% 32 0.071%
MEM_REQ_MATCH_WB_NODIRTY 1 0.002% 1 0.002%
 44837 100.000% 44837 100.000%
 0.67 0.30 0.67 0.30
MEM_REQ_COMPLETE_OFFPATH_IFETCH 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_DFETCH 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_DSTORE 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_OFFPATH_WB 96 100.000% 96 100.000%
MEM_REQ_COMPLETE_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000%
 96 100.000% 96 100.000%
 5.00 0.00 5.00 0.00
MEM_REQ_COMPLETE_ONPATH_IFETCH 6 0.040% 6 0.040%
MEM_REQ_COMPLETE_ONPATH_DFETCH 15024 99.940% 15024 99.940%
MEM_REQ_COMPLETE_ONPATH_DSTORE 2 0.013% 2 0.013%
MEM_REQ_COMPLETE_ONPATH_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_ONPATH_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_ONPATH_WB 1 0.007% 1 0.007%
MEM_REQ_COMPLETE_ONPATH_WB_NODIRTY 0 0.000% 0 0.000%
 15033 100.000% 15033 100.000%
 1.00 0.03 1.00 0.03
MEM_REQ_COMPLETE_MEM_IFETCH 29732 66.285% 29732 66.285%
MEM_REQ_COMPLETE_MEM_DFETCH 15024 33.495% 15024 33.495%
MEM_REQ_COMPLETE_MEM_DSTORE 2 0.004% 2 0.004%
MEM_REQ_COMPLETE_MEM_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MEM_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MEM_WB 97 0.216% 97 0.216%
MEM_REQ_COMPLETE_MEM_WB_NODIRTY 0 0.000% 0 0.000%
 44855 100.000% 44855 100.000%
 0.35 0.44 0.35 0.44
MEM_REQ_COMPLETE_MEM_BW_PREFETCHABLE 29053 29053
MEM_REQ_COMPLETE_MEM_MATCHED_BW_PREF 479 479
MEM_REQ_COMPLETE_L1_IFETCH 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_DFETCH 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_DSTORE 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_IPRF 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_DPRF 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_WB 0 -nan% 0 -nan%
MEM_REQ_COMPLETE_L1_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_COMPLETE_MLC_IFETCH 681 100.000% 681 100.000%
MEM_REQ_COMPLETE_MLC_DFETCH 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_DSTORE 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_IPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_DPRF 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_WB 0 0.000% 0 0.000%
MEM_REQ_COMPLETE_MLC_WB_NODIRTY 0 0.000% 0 0.000%
 681 100.000% 681 100.000%
 0.00 0.00 0.00 0.00
CORE_MLP_CLUSTERS 14513 14513
CORE_MLP 1365238 1365238
CORE_MLP_IFETCH 0 0
CORE_MLP_DFETCH 0 0
CORE_MLP_DSTORE 0 0
CORE_MLP_IPRF 0 0
CORE_MLP_DPRF 0 0
CORE_MLP_WB 0 0
CORE_MLP_WB_NODIRTY 0 0
CORE_MLP_0 403 0.120% 403 0.120%
CORE_MLP_1 1014 0.302% 1014 0.302%
CORE_MLP_2 85622 25.463% 85622 25.463%
CORE_MLP_3 161715 48.093% 161715 48.093%
CORE_MLP_4 42408 12.612% 42408 12.612%
CORE_MLP_5 10317 3.068% 10317 3.068%
CORE_MLP_6 7324 2.178% 7324 2.178%
CORE_MLP_7 2659 0.791% 2659 0.791%
CORE_MLP_8 906 0.269% 906 0.269%
CORE_MLP_9 643 0.191% 643 0.191%
CORE_MLP_10 592 0.176% 592 0.176%
CORE_MLP_11 725 0.216% 725 0.216%
CORE_MLP_12 710 0.211% 710 0.211%
CORE_MLP_13 1052 0.313% 1052 0.313%
CORE_MLP_14 2598 0.773% 2598 0.773%
CORE_MLP_15 2345 0.697% 2345 0.697%
CORE_MLP_16 801 0.238% 801 0.238%
CORE_MLP_17 212 0.063% 212 0.063%
CORE_MLP_18 502 0.149% 502 0.149%
CORE_MLP_19 436 0.130% 436 0.130%
CORE_MLP_20 12143 3.611% 12143 3.611%
CORE_MLP_21 17 0.005% 17 0.005%
CORE_MLP_22 161 0.048% 161 0.048%
CORE_MLP_23 370 0.110% 370 0.110%
CORE_MLP_24 380 0.113% 380 0.113%
CORE_MLP_25 111 0.033% 111 0.033%
CORE_MLP_26 12 0.004% 12 0.004%
CORE_MLP_27 12 0.004% 12 0.004%
CORE_MLP_28 66 0.020% 66 0.020%
CORE_MLP_29 0 0.000% 0 0.000%
CORE_MLP_30 0 0.000% 0 0.000%
CORE_MLP_31 0 0.000% 0 0.000%
CORE_MLP_32 0 0.000% 0 0.000%
 336256 100.000% 336256 100.000%
 4.06 3.95 4.06 3.95
MEM_QUEUE_OCC_0 0 -nan% 0 -nan%
MEM_QUEUE_OCC_4 0 -nan% 0 -nan%
MEM_QUEUE_OCC_8 0 -nan% 0 -nan%
MEM_QUEUE_OCC_12 0 -nan% 0 -nan%
MEM_QUEUE_OCC_16 0 -nan% 0 -nan%
MEM_QUEUE_OCC_20 0 -nan% 0 -nan%
MEM_QUEUE_OCC_24 0 -nan% 0 -nan%
MEM_QUEUE_OCC_28 0 -nan% 0 -nan%
MEM_QUEUE_OCC_32 0 -nan% 0 -nan%
MEM_QUEUE_OCC_36 0 -nan% 0 -nan%
MEM_QUEUE_OCC_40 0 -nan% 0 -nan%
MEM_QUEUE_OCC_44 0 -nan% 0 -nan%
MEM_QUEUE_OCC_48 0 -nan% 0 -nan%
MEM_QUEUE_OCC_52 0 -nan% 0 -nan%
MEM_QUEUE_OCC_56 0 -nan% 0 -nan%
MEM_QUEUE_OCC_60 0 -nan% 0 -nan%
MEM_QUEUE_OCC_64 0 -nan% 0 -nan%
MEM_QUEUE_OCC_68 0 -nan% 0 -nan%
MEM_QUEUE_OCC_72 0 -nan% 0 -nan%
MEM_QUEUE_OCC_76 0 -nan% 0 -nan%
MEM_QUEUE_OCC_80 0 -nan% 0 -nan%
MEM_QUEUE_OCC_84 0 -nan% 0 -nan%
MEM_QUEUE_OCC_88 0 -nan% 0 -nan%
MEM_QUEUE_OCC_92 0 -nan% 0 -nan%
MEM_QUEUE_OCC_96 0 -nan% 0 -nan%
MEM_QUEUE_OCC_100 0 -nan% 0 -nan%
MEM_QUEUE_OCC_104 0 -nan% 0 -nan%
MEM_QUEUE_OCC_108 0 -nan% 0 -nan%
MEM_QUEUE_OCC_112 0 -nan% 0 -nan%
MEM_QUEUE_OCC_116 0 -nan% 0 -nan%
MEM_QUEUE_OCC_120 0 -nan% 0 -nan%
MEM_QUEUE_OCC_124 0 -nan% 0 -nan%
MEM_QUEUE_OCC_128 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
OPEN_PAGE_HIT 0 -nan% 0 -nan%
CLOSED_PAGE_MISS 0 -nan% 0 -nan%
WRONG_PAGE_MISS 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_LD_BANK_BLOCK 0 -nan% 0 -nan%
L0_LD_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_ST_BANK_BLOCK 0 -nan% 0 -nan%
L0_ST_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_LD_CACHE_BLOCK 0 -nan% 0 -nan%
L0_LD_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_LD_BANK_BLOCK 0 0.000% 0 0.000%
MLC_LD_BANK_AVAIL 14638 100.000% 14638 100.000%
 14638 100.000% 14638 100.000%
 1.00 1.00 1.00 1.00
MLC_ST_BANK_BLOCK 0 0.000% 0 0.000%
MLC_ST_BANK_AVAIL 14514 100.000% 14514 100.000%
 14514 100.000% 14514 100.000%
 1.00 1.00 1.00 1.00
MLC_LD_CACHE_BLOCK 0 -nan% 0 -nan%
MLC_LD_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MLC_ST_CACHE_BLOCK 0 -nan% 0 -nan%
MLC_ST_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_LD_BANK_BLOCK 0 0.000% 0 0.000%
L1_LD_BANK_AVAIL 29665 100.000% 29665 100.000%
 29665 100.000% 29665 100.000%
 1.00 1.00 1.00 1.00
L1_ST_BANK_BLOCK 0 0.000% 0 0.000%
L1_ST_BANK_AVAIL 682 100.000% 682 100.000%
 682 100.000% 682 100.000%
 1.00 1.00 1.00 1.00
L1_LD_CACHE_BLOCK 0 -nan% 0 -nan%
L1_LD_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_ST_CACHE_BLOCK 0 -nan% 0 -nan%
L1_ST_CACHE_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_LD_BANK_BLOCK 0 -nan% 0 -nan%
MEM_LD_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_ST_BANK_BLOCK 0 -nan% 0 -nan%
MEM_ST_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_PF_BANK_BLOCK 0 -nan% 0 -nan%
MEM_PF_BANK_AVAIL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L0_FILL 0 0
L1_FILL 15140 100.000% 15140 100.000%
L1_WB_FILL 0 0.000% 0 0.000%
 15140 100.000% 15140 100.000%
 0.00 0.00 0.00 0.00
L1_DEMAND_FILL 117 0.773% 117 0.773%
L1_PREF_FILL 15023 99.227% 15023 99.227%
 15140 100.000% 15140 100.000%
 0.99 0.99 0.99 0.99
MLC_FILL 15129 100.000% 15129 100.000%
MLC_WB_FILL 0 0.000% 0 0.000%
 15129 100.000% 15129 100.000%
 0.00 0.00 0.00 0.00
MLC_DEMAND_FILL 14638 96.755% 14638 96.755%
MLC_PREF_FILL 491 3.245% 491 3.245%
 15129 100.000% 15129 100.000%
 0.03 0.17 0.03 0.17
NORESET_L1_FILL 15140 15140
NORESET_L1_FILL_NONPREF 20 20
NORESET_L1_FILL_PREF 15120 15120
NORESET_L1_EVICT 0 0
NORESET_L1_EVICT_NONPREF 0 0
NORESET_L1_EVICT_PREF_USED 0 0
NORESET_L1_EVICT_PREF_UNUSED 0 0
NORESET_L1_PREF_USED 14521 14521
ORACLE_OFFPATH_DC_FILL 0 0
ORACLE_OFFPATH_IC_FILL 0 0
ORACLE_OFFPATH_L1_FILL 0 0
UPDATE_EVENT_QUEUE_PROCESS 0 0
INSERT_EVENT_QUEUE_PROCESS 0 0
ICFILL_AFTER_REDIRECT 0 0
EVENT_QUEUE_MATCH_ADD_REQ 0 0
DC_PREF_CACHE_INSERT_REQ 0 0
DC_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan%
DC_PREF_REQ_PREF_CACHE_HIT 0 -nan% 0 -nan%
DC_PREF_REQ_L1_MISS 0 -nan% 0 -nan%
DC_PREF_REQ_CORR 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DC_PREF_CACHE_INSERT 0 0
DC_PREF_CACHE_HIT_PER 0 0.000% 0 0.000%
DC_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000%
DC_PREF_CACHE_HIT 0 0
DC_PREF_CACHE_HIT_OFFPATH 0 0
DC_PREF_HIT_L1_MISS 0 0
IC_PREF_CACHE_HIT_PER 0 0.000% 0 0.000%
IC_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000%
IC_PREF_CACHE_HIT 0 0
IC_PREF_CACHE_HIT_OFFPATH 0 0
L1_PREF_CACHE_HIT_PER 0 0.000% 0 0.000%
L1_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000%
L1_PREF_CACHE_HIT 0 0
L1_PREF_CACHE_HIT_OFFPATH 0 0
DC_PREF_CACHE_FILL 0 0
DC_PREF_MOVE_DC 0 -nan% 0 -nan%
DC_PREF_MOVE_L1 0 -nan% 0 -nan%
IC_PREF_CACHE_FILL 0 0
IC_PREF_MOVE_IC 0 -nan% 0 -nan%
IC_PREF_MOVE_L1 0 -nan% 0 -nan%
L1_PREF_CACHE_FILL 0 0
L1_PREF_MOVE_L1 0 -nan% 0 -nan%
OFF_PATH_CONFIRMED 136 136
OFF_PATH_NO_FILL_L1 0 0
WB_L1_MISS_FILL_L1 0 0
WB_MLC_MISS_FILL_MLC 0 0
ICACHE_EVICT_REQ_WB_L1 0 0
DCACHE_EVICT_REQ_WB_L1 0 0
DCACHE_EVICT_REQ_WB_L1_NOREAD 0 0
L1_FILL_SKIPPED 0 0
MLC_FILL_SKIPPED 0 0
DCACHE_FILL 15026 15026
DCACHE_WB_REQ 14514 0.9659 14514 0.9659
DCACHE_WB_REQ_DIRTY 14514 100.000% 14514 100.000%
DCACHE_WB_REQ_NODIRTY 0 0.000% 0 0.000%
 14514 100.000% 14514 100.000%
 0.00 0.00 0.00 0.00
ICACHE_FILL 103 103
ICACHE_WB_REQ 0 0.0000 0 0.0000
L1_FILL_DIRTY 0 0.0000 0 0.0000
MLC_FILL_DIRTY 682 0.0451 682 0.0451
ICACHE_UNUSEFUL_CL_CYC 0 0
ICACHE_UNUSEFUL_CL 0 0
ICACHE_EVICT_MISS_ONPATH_BY_FDIP 0 -nan% 0 -nan%
ICACHE_EVICT_MISS_OFFPATH_BY_FDIP 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_EVICT_MISS_BY_FDIP_ONPATH 0 -nan% 0 -nan%
ICACHE_EVICT_MISS_BY_FDIP_OFFPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_EVICT_HIT_ONPATH_BY_FDIP 0 -nan% 0 -nan%
ICACHE_EVICT_HIT_OFFPATH_BY_FDIP 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ICACHE_EVICT_HIT_BY_FDIP_ONPATH 0 -nan% 0 -nan%
ICACHE_EVICT_HIT_BY_FDIP_OFFPATH 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_DENIED_NULL 0 -nan% 0 -nan%
MEM_REQ_DENIED_INST_OUTOF_CS 0 -nan% 0 -nan%
MEM_REQ_DENIED_DATA_IN_CS 0 -nan% 0 -nan%
MEM_REQ_DENIED_DATA_OUTOF_RANGE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_DENIED 0 -nan% 0 -nan%
MEM_REQ_NOT_DENIED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_HIT_WB_STALL 0 0
EXCLUSION_VIOLATED_OSR 0 -nan% 0 -nan%
EXCLUSION_VIOLATED_NOTOSR 0 -nan% 0 -nan%
EXCLUSION_NOT_VIOLATED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DIRTY_WRITE_TO_ICACHE 0 0
STREAM_DC_HIT_NOSEND 0 -nan% 0 -nan%
STREAM_WBQDC_HIT_NOSEND 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
STREAM_DCACHE_PREF_HIT 0 0
PREF_DC_HIT_ON_INSERT 0 -nan% 0 -nan%
PREF_L1_HIT_ON_INSERT 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_NEWREQ_MATCHED_MLC_REQ 0 0
MLC_NEWREQ_MATCHED_L2_PREF 491 491
MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT 0 0.0000 0 0.0000
NEWREQ_WB_MATCH_IGNORED 0 0
DEMAND_MATCH_WB_NEW_DONE_FUNC 0 -nan% 0 -nan%
DEMAND_MATCH_WB_NEW_DONE_FUNC_NULL 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DONE_FUNC_NOT_SAME 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DONE_FUNC_SAME 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WBALL_IFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_DFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_DSTORE 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_IPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_DPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WBALL_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WB_IFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DSTORE 0 -nan% 0 -nan%
DEMAND_MATCH_WB_IPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_DPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WB_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DEMAND_MATCH_WB_ND_IFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_DFETCH 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_DSTORE 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_IPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_DPRF 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_WB 0 -nan% 0 -nan%
DEMAND_MATCH_WB_ND_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
WB_MATCH_DEMAND 0 0.000% 0 0.000%
WB_MATCH_PREF 0 0.000% 0 0.000%
WB_MATCH_WB 0 0.000% 0 0.000%
WB_MATCH_WB_FILTERED 14567 100.000% 14567 100.000%
 14567 100.000% 14567 100.000%
 3.00 3.00 3.00 3.00
WB_COMING_BACK_FROM_MEM 0 0
WB_COMING_BACK_FROM_L1 0 0
WB_COMING_BACK_FROM_MLC 0 0
MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH 0 0.000% 0 0.000%
MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_ETC 15526 100.000% 15526 100.000%
 15526 100.000% 15526 100.000%
 1.00 1.00 1.00 1.00
TOTAL_ONPATH_ICACHE_FILLS 0 0
TOTAL_ONPATH_DCACHE_FILLS 0 0
TOTAL_ONPATH_L1_FILLS 0 0
PER1K_ONPATH_ICACHE_FILLS 0 0.0000 0 0.0000
PER1K_ONPATH_DCACHE_FILLS 0 0.0000 0 0.0000
PER1K_ONPATH_L1_FILLS 0 0.0000 0 0.0000
PER1K_L1_DEMAND_MISS_ONPATH 21 0.0218 21 0.0218
PER1K_L1_DEMAND_MISS_OFFPATH 0 0.0000 0 0.0000
L2_IDEAL_FILL_L1 0 -nan% 0 -nan%
L2_IDEAL_MISS_L2 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L2_IDEAL_FILL_ICACHE 0 -nan% 0 -nan%
L2_IDEAL_MISS_ICACHE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
HPS_MISS_DELTA__0 0 -nan% 0 -nan%
HPS_MISS_DELTA__1 0 -nan% 0 -nan%
HPS_MISS_DELTA__2 0 -nan% 0 -nan%
HPS_MISS_DELTA__3 0 -nan% 0 -nan%
HPS_MISS_DELTA__4 0 -nan% 0 -nan%
HPS_MISS_DELTA__5 0 -nan% 0 -nan%
HPS_MISS_DELTA__6 0 -nan% 0 -nan%
HPS_MISS_DELTA__7 0 -nan% 0 -nan%
HPS_MISS_DELTA__8 0 -nan% 0 -nan%
HPS_MISS_DELTA__9 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
HPS_HIT_DELTA__0 0 -nan% 0 -nan%
HPS_HIT_DELTA__1 0 -nan% 0 -nan%
HPS_HIT_DELTA__2 0 -nan% 0 -nan%
HPS_HIT_DELTA__3 0 -nan% 0 -nan%
HPS_HIT_DELTA__4 0 -nan% 0 -nan%
HPS_HIT_DELTA__5 0 -nan% 0 -nan%
HPS_HIT_DELTA__6 0 -nan% 0 -nan%
HPS_HIT_DELTA__7 0 -nan% 0 -nan%
HPS_HIT_DELTA__8 0 -nan% 0 -nan%
HPS_HIT_DELTA__9 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DC_MISS_DELTA__0 0 -nan% 0 -nan%
DC_MISS_DELTA__1 0 -nan% 0 -nan%
DC_MISS_DELTA__2 0 -nan% 0 -nan%
DC_MISS_DELTA__3 0 -nan% 0 -nan%
DC_MISS_DELTA__4 0 -nan% 0 -nan%
DC_MISS_DELTA__5 0 -nan% 0 -nan%
DC_MISS_DELTA__6 0 -nan% 0 -nan%
DC_MISS_DELTA__7 0 -nan% 0 -nan%
DC_MISS_DELTA__8 0 -nan% 0 -nan%
DC_MISS_DELTA__9 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ONE_MORE_SUCESS 0 -nan% 0 -nan%
ONE_MORE_DISCARDED_L0CACHE 0 -nan% 0 -nan%
ONE_MORE_DISCARDED_MEM_REQ_FULL 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
PREF_L1_TOTAL_SENT 15026 15026
PREF_L1_TOTAL_USED 14521 96.658% 14521 96.658%
PREF_L1_TOTAL_PARTIAL_USED 491 3.268% 491 3.268%
PREF_L1_TOTAL_NOT_USED 11 0.073% 11 0.073%
PREF_L1_TOTAL_DROPPED 0 0.000% 0 0.000%
 15023 100.000% 15023 100.000%
 0.03 0.18 0.03 0.18
PREF_MLC_TOTAL_SENT 0 0
PREF_MLC_TOTAL_USED 0 0.000% 0 0.000%
PREF_MLC_TOTAL_PARTIAL_USED 491 100.000% 491 100.000%
PREF_MLC_TOTAL_NOT_USED 0 0.000% 0 0.000%
PREF_MLC_TOTAL_DROPPED 0 0.000% 0 0.000%
 491 100.000% 491 100.000%
 1.00 0.00 1.00 0.00
CORE_MLC_PREF_REQ_MISS 0 0.000% 0 0.000%
CORE_MLC_DEMAND_MISS 14541 99.337% 14541 99.337%
CORE_MLC_WB_MISS 97 0.663% 97 0.663%
 14638 100.000% 14638 100.000%
 1.01 0.12 1.01 0.12
CORE_MLC_PREF_REQ_HIT 0 0.000% 0 0.000%
CORE_MLC_DEMAND_HIT 0 0.000% 0 0.000%
CORE_MLC_WB_HIT 14513 100.000% 14513 100.000%
 14513 100.000% 14513 100.000%
 2.00 2.00 2.00 2.00
CORE_MLC_HIT 0 0.000% 0 0.000%
CORE_MLC_MISS 14541 100.000% 14541 100.000%
 14541 100.000% 14541 100.000%
 1.00 1.00 1.00 1.00
CORE_MLC_FILL 15129 100.000% 15129 100.000%
CORE_MLC_WB_FILL 0 0.000% 0 0.000%
 15129 100.000% 15129 100.000%
 0.00 0.00 0.00 0.00
CORE_MLC_DEMAND_FILL 14638 96.755% 14638 96.755%
CORE_MLC_PREF_FILL 491 3.245% 491 3.245%
 15129 100.000% 15129 100.000%
 0.03 0.17 0.03 0.17
CORE_MLC_PREF_FILL_USED 0 0.000% 0 0.000%
CORE_MLC_PREF_FILL_PARTIAL_USED 491 100.000% 491 100.000%
CORE_MLC_PREF_FILL_NOT_USED 0 0.000% 0 0.000%
 491 100.000% 491 100.000%
 1.00 0.00 1.00 0.00
CORE_L1_PREF_REQ_MISS 15026 99.227% 15026 99.227%
CORE_L1_DEMAND_MISS 20 0.132% 20 0.132%
CORE_L1_WB_MISS 97 0.641% 97 0.641%
 15143 100.000% 15143 100.000%
 0.01 0.16 0.01 0.16
CORE_L1_PREF_REQ_HIT 0 0.000% 0 0.000%
CORE_L1_DEMAND_HIT 14521 95.520% 14521 95.520%
CORE_L1_WB_HIT 681 4.480% 681 4.480%
 15202 100.000% 15202 100.000%
 1.04 0.30 1.04 0.30
CORE_L1_HIT 14521 99.856% 14521 99.856%
CORE_L1_MISS 21 0.144% 21 0.144%
 14542 100.000% 14542 100.000%
 0.00 0.04 0.00 0.04
CORE_L1_FILL 15140 100.000% 15140 100.000%
CORE_L1_WB_FILL 0 0.000% 0 0.000%
 15140 100.000% 15140 100.000%
 0.00 0.00 0.00 0.00
CORE_L1_DEMAND_FILL 117 0.773% 117 0.773%
CORE_L1_PREF_FILL 15023 99.227% 15023 99.227%
 15140 100.000% 15140 100.000%
 0.99 0.99 0.99 0.99
CORE_L1_PREF_FILL_USED 14521 96.658% 14521 96.658%
CORE_L1_PREF_FILL_PARTIAL_USED 491 3.268% 491 3.268%
CORE_L1_PREF_FILL_NOT_USED 11 0.073% 11 0.073%
 15023 100.000% 15023 100.000%
 0.03 0.18 0.03 0.18
CORE_L1_DEMAND_USED_POS0 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS1 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS2 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS3 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS4 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS5 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS6 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS7 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS8 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS9 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS10 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS11 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS12 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS13 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS14 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS15 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS16 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS17 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS18 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS19 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS20 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS21 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS22 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS23 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS24 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS25 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS26 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS27 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS28 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS29 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS30 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS31 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS32 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS33 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS34 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS35 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS36 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS37 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS38 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS39 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS40 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS41 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS42 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS43 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS44 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS45 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS46 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS47 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS48 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS49 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS50 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS51 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS52 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS53 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS54 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS55 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS56 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS57 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS58 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS59 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS60 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS61 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS62 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS63 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS64 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS65 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS66 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS67 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS68 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS69 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS70 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS71 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS72 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS73 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS74 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS75 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS76 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS77 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS78 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS79 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS80 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS81 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS82 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS83 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS84 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS85 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS86 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS87 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS88 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS89 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS90 0 -nan% 0 -nan%
CORE_L1_DEMAND_USED_POS91 0 -nan% 0 -nan%
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L1_SHADOW_STALLING_HIT_POS52 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS53 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS54 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS55 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS56 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS57 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS58 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS59 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS60 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS61 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS62 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS63 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS64 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS65 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS66 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS67 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS68 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS69 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS70 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS71 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS72 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS73 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS74 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS75 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS76 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS77 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS78 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS79 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS80 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS81 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS82 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS83 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS84 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS85 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS86 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS87 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS88 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS89 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS90 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS91 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS92 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS93 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS94 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS95 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS96 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS97 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS98 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS99 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS100 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS101 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS102 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS103 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS104 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS105 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS106 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS107 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS108 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS109 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS110 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS111 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS112 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS113 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS114 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS115 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS116 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS117 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS118 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS119 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS120 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS121 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS122 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS123 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS124 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS125 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS126 0 -nan% 0 -nan%
L1_SHADOW_STALLING_HIT_POS127 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
L1_SHADOW_DEMAND_HIT_POS0 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS1 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS2 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS3 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS4 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS5 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS6 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS7 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS8 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS9 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS10 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS11 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS12 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS13 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS14 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS15 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS16 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS17 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS18 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS19 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS20 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS21 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS22 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS23 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS24 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS25 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS26 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS27 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS28 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS29 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS30 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS31 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS32 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS33 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS34 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS35 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS36 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS37 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS38 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS39 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS40 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS41 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS42 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS43 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS44 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS45 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS46 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS47 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS48 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS49 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS50 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS51 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS52 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS53 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS54 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS55 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS56 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS57 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS58 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS59 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS60 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS61 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS62 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS63 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS64 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS65 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS66 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS67 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS68 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS69 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS70 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS71 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS72 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS73 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS74 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS75 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS76 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS77 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS78 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS79 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS80 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS81 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS82 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS83 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS84 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS85 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS86 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS87 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS88 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS89 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS90 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS91 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS92 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS93 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS94 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS95 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS96 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS97 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS98 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS99 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS100 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS101 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS102 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS103 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS104 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS105 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS106 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS107 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS108 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS109 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS110 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS111 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS112 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS113 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS114 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS115 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS116 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS117 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS118 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS119 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS120 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS121 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS122 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS123 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS124 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS125 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS126 0 -nan% 0 -nan%
L1_SHADOW_DEMAND_HIT_POS127 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_MLC_SENT 0 0
CORE_PREF_MLC_USED 0 0.000% 0 0.000%
CORE_PREF_MLC_PARTIAL_USED 491 100.000% 491 100.000%
CORE_PREF_MLC_NOT_USED 0 0.000% 0 0.000%
CORE_PREF_MLC_DROPPED 0 0.000% 0 0.000%
 491 100.000% 491 100.000%
 1.00 0.00 1.00 0.00
CORE_PREF_L1_SENT 15026 15026
CORE_PREF_L1_USED 14521 96.658% 14521 96.658%
CORE_PREF_L1_PARTIAL_USED 491 3.268% 491 3.268%
CORE_PREF_L1_NOT_USED 11 0.073% 11 0.073%
CORE_PREF_L1_DROPPED 0 0.000% 0 0.000%
 15023 100.000% 15023 100.000%
 0.03 0.18 0.03 0.18
TOTAL_MEM_LATENCY 2039840 134.7318 2039840 134.7318
TOTAL_MEM_LATENCY_DEMAND 591024 5051.4872 591024 5051.4872
TOTAL_MEM_LATENCY_PREF 1448816 96.4399 1448816 96.4399
CORE_MEM_LATENCY 2039840 134.7318 2039840 134.7318
CORE_MEM_LATENCY_DEMAND 591024 5051.4872 591024 5051.4872
CORE_MEM_LATENCY_PREF 1448816 96.4399 1448816 96.4399
CORE_MEM_LATENCY_IFETCH 967 0.070% 967 0.070%
CORE_MEM_LATENCY_DFETCH 351273 25.449% 351273 25.449%
CORE_MEM_LATENCY_DSTORE 162 0.012% 162 0.012%
CORE_MEM_LATENCY_IPRF 0 0.000% 0 0.000%
CORE_MEM_LATENCY_UOCPRF 0 0.000% 0 0.000%
CORE_MEM_LATENCY_FDIPPRF 29119 2.110% 29119 2.110%
CORE_MEM_LATENCY_DPRF 0 0.000% 0 0.000%
CORE_MEM_LATENCY_WB 998782 72.360% 998782 72.360%
CORE_MEM_LATENCY_WB_NODIRTY 0 0.000% 0 0.000%
 1380303 100.000% 1380303 100.000%
 5.43 2.60 5.43 2.60
CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan%
CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
TOTAL_L1_MISS_LATENCY 1380303 91.1693 1380303 91.1693
TOTAL_L1_MISS_LATENCY_DEMAND 31891 272.5726 31891 272.5726
TOTAL_L1_MISS_LATENCY_PREF 1348412 89.7565 1348412 89.7565
CORE_L1_MISS_LATENCY 1380303 91.1693 1380303 91.1693
CORE_L1_MISS_LATENCY_DEMAND 31891 272.5726 31891 272.5726
CORE_L1_MISS_LATENCY_PREF 1348412 89.7565 1348412 89.7565
CORE_EVICTED_L1_DEMAND 0 -nan% 0 -nan%
CORE_EVICTED_L1_PREF_USED 0 -nan% 0 -nan%
CORE_EVICTED_L1_PREF_NOT_USED 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_EVICTED_MLC_DEMAND 793 100.000% 793 100.000%
CORE_EVICTED_MLC_PREF_USED 0 0.000% 0 0.000%
CORE_EVICTED_MLC_PREF_NOT_USED 0 0.000% 0 0.000%
 793 100.000% 793 100.000%
 0.00 0.00 0.00 0.00
CORE_MEM_LATENCY_AVE_DEMAND 1183 inf 1183 inf
CORE_MEM_LATENCY_AVE_PREF_USED 0 -nan 0 -nan
CORE_MEM_LATENCY_AVE_PREF_NOT_USED 0 -nan 0 -nan
DRAM_LATENCY 0 0
TOTAL_DRAM_LATENCY 0 0
DRAM_CLOSED_PAGE_POLICY_CMD 0 0
DRAM_ACTIVATE_STALLING 0 0
DRAM_PRECHARGE_STALLING 0 0
DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0
L1_STAY_DEMAND 0 -nan 0 -nan
L1_STAY_PREF_USED 0 -nan 0 -nan
L1_STAY_PREF_NOT_USED 0 -nan 0 -nan
TOTAL_DATA_MISS_LATENCY 976629 976629
TOTAL_DATA_MISS_COUNT 15529 15529
CORE_PREF_L1_NOT_USED_LATENCY200 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY400 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY600 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY800 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY1000 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY1200 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY1400 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY1600 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_L1_NOT_USED_DISTANCE_1 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_2 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_4 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_8 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_16 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_32 0 -nan% 0 -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_L1_USED_LATENCY200 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY400 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY600 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY800 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY1000 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY1200 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY1400 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY1600 0 -nan% 0 -nan%
CORE_PREF_L1_USED_LATENCY1600MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_L1_USED_DISTANCE_1 0 -nan% 0 -nan%
CORE_PREF_L1_USED_DISTANCE_2 0 -nan% 0 -nan%
CORE_PREF_L1_USED_DISTANCE_4 0 -nan% 0 -nan%
CORE_PREF_L1_USED_DISTANCE_8 0 -nan% 0 -nan%
CORE_PREF_L1_USED_DISTANCE_16 0 -nan% 0 -nan%
CORE_PREF_L1_USED_DISTANCE_32 0 -nan% 0 -nan%
CORE_PREF_L1_USED_DISTANCE_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_L1_DEMAND_LATENCY300 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY400 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY500 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY600 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY700 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY800 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY900 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY1000 0 -nan% 0 -nan%
CORE_PREF_L1_DEMAND_LATENCY1000MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_MLC_NOT_USED_LATENCY200 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY400 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY600 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY800 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1000 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1200 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1400 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1600 0 -nan% 0 -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_MLC_USED_LATENCY200 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY400 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY600 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY800 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY1000 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY1200 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY1400 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY1600 0 -nan% 0 -nan%
CORE_PREF_MLC_USED_LATENCY1600MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_PREF_MLC_DEMAND_LATENCY300 792 99.874% 792 99.874%
CORE_PREF_MLC_DEMAND_LATENCY400 1 0.126% 1 0.126%
CORE_PREF_MLC_DEMAND_LATENCY500 0 0.000% 0 0.000%
CORE_PREF_MLC_DEMAND_LATENCY600 0 0.000% 0 0.000%
CORE_PREF_MLC_DEMAND_LATENCY700 0 0.000% 0 0.000%
CORE_PREF_MLC_DEMAND_LATENCY800 0 0.000% 0 0.000%
CORE_PREF_MLC_DEMAND_LATENCY900 0 0.000% 0 0.000%
CORE_PREF_MLC_DEMAND_LATENCY1000 0 0.000% 0 0.000%
CORE_PREF_MLC_DEMAND_LATENCY1000MORE 0 0.000% 0 0.000%
 793 100.000% 793 100.000%
 0.00 0.04 0.00 0.04
TOTAL_BATCH_FORMED 0 0
TOTAL_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan
CORE_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan
CORE_BATCH_MEM_REQ_MARKED_DEMAND 0 -nan 0 -nan
CORE_BATCH_MEM_REQ_MARKED_PREF 0 -nan 0 -nan
DRAM_ROW_BATCHES 0 0
REJECTED_QUEUE_MLC 0 0
REJECTED_QUEUE_L1 0 0
REJECTED_QUEUE_BUS_OUT 0 0
LEADING_LOAD_LATENCY 0 0.0000 0 0.0000
LEADING_LOADS 0 0.0000 0 0.0000
MEM_REQ_CRITICAL_PATH_LENGTH 0 0.0000 0 0.0000
TOTAL_MEM_REQ_LATENCY 0 0
TOTAL_CRITICAL_MEM_REQ_LATENCY 0 -nan 0 -nan
TOTAL_CRITICAL_BANK_LATENCY 0 -nan 0 -nan
TOTAL_MEMORY_SLACK 0 0.0000 0 0.0000
TOTAL_CHIP_UTILIZATION 0 0.0000 0 0.0000
CHIP_BUSY_UNDER_CRITICAL_REQS 0 0.0000 0 0.0000
PERF_PRED_NUM_STAT_RESETS 0 0
PERF_PRED_RESET_STATS_CYCLE 0 0
PERF_PRED_CYCLE 336256 336256
ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000
NUM_WINDOWS_WITH_DCACHE_MISS 2163 2163
LONGEST_DCACHE_MISS_CHAIN 4230 4230
NUM_DCACHE_MISSES_IN_WINDOW_1 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_2 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_3 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_4 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_5 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_6 131 6.056% 131 6.056%
NUM_DCACHE_MISSES_IN_WINDOW_7 2029 93.805% 2029 93.805%
NUM_DCACHE_MISSES_IN_WINDOW_8 2 0.092% 2 0.092%
NUM_DCACHE_MISSES_IN_WINDOW_9 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_10 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_11 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_12 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_13 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_14 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_15 0 0.000% 0 0.000%
NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 1 0.046% 1 0.046%
 2163 100.000% 2163 100.000%
 5.94 0.34 5.94 0.34
DCACHE_MLP_IN_WINDOW_1_0 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_1_5 1 0.046% 1 0.046%
DCACHE_MLP_IN_WINDOW_2_0 2 0.092% 2 0.092%
DCACHE_MLP_IN_WINDOW_2_5 1 0.046% 1 0.046%
DCACHE_MLP_IN_WINDOW_3_0 21 0.971% 21 0.971%
DCACHE_MLP_IN_WINDOW_3_5 2026 93.666% 2026 93.666%
DCACHE_MLP_IN_WINDOW_4_0 1 0.046% 1 0.046%
DCACHE_MLP_IN_WINDOW_4_5 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_5_0 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_5_5 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_6_0 109 5.039% 109 5.039%
DCACHE_MLP_IN_WINDOW_6_5 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_7_0 2 0.092% 2 0.092%
DCACHE_MLP_IN_WINDOW_7_5 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_8_0 0 0.000% 0 0.000%
DCACHE_MLP_IN_WINDOW_8_5_OR_MORE 0 0.000% 0 0.000%
 2163 100.000% 2163 100.000%
 5.24 1.13 5.24 1.13
PARAM_CHIP_CYCLE_TIME 0 0
PARAM_CORE_CYCLE_TIME 312500 312500
PARAM_L1_CYCLE_TIME 312500 312500
PARAM_MEMORY_CYCLE_TIME 833333 833333
MEM_REQ_NON_SCHEDULED__0 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED__4 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED__8 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_12 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_16 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_20 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_24 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_28 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_32 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_36 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_40 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_44 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_48 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_52 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_56 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_60 0 -nan% 0 -nan%
MEM_REQ_NON_SCHEDULED_64 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_REQ_DEMANDS__0 321760 95.689% 321760 95.689%
MEM_REQ_DEMANDS__4 14496 4.311% 14496 4.311%
MEM_REQ_DEMANDS__8 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_12 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_16 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_20 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_24 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_28 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_32 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_36 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_40 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_44 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_48 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_52 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_56 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_60 0 0.000% 0 0.000%
MEM_REQ_DEMANDS_64 0 0.000% 0 0.000%
 336256 100.000% 336256 100.000%
 0.04 0.20 0.04 0.20
MEM_REQ_PREFS__0 11910 3.542% 11910 3.542%
MEM_REQ_PREFS__4 291762 86.768% 291762 86.768%
MEM_REQ_PREFS__8 10208 3.036% 10208 3.036%
MEM_REQ_PREFS_12 6725 2.000% 6725 2.000%
MEM_REQ_PREFS_16 14464 4.301% 14464 4.301%
MEM_REQ_PREFS_20 68 0.020% 68 0.020%
MEM_REQ_PREFS_24 1054 0.313% 1054 0.313%
MEM_REQ_PREFS_28 65 0.019% 65 0.019%
MEM_REQ_PREFS_32 0 0.000% 0 0.000%
MEM_REQ_PREFS_36 0 0.000% 0 0.000%
MEM_REQ_PREFS_40 0 0.000% 0 0.000%
MEM_REQ_PREFS_44 0 0.000% 0 0.000%
MEM_REQ_PREFS_48 0 0.000% 0 0.000%
MEM_REQ_PREFS_52 0 0.000% 0 0.000%
MEM_REQ_PREFS_56 0 0.000% 0 0.000%
MEM_REQ_PREFS_60 0 0.000% 0 0.000%
MEM_REQ_PREFS_64 0 0.000% 0 0.000%
 336256 100.000% 336256 100.000%
 1.18 0.73 1.18 0.73
MEM_REQ_WRITEBACKS__0 336080 99.948% 336080 99.948%
MEM_REQ_WRITEBACKS__4 176 0.052% 176 0.052%
MEM_REQ_WRITEBACKS__8 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_12 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_16 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_20 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_24 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_28 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_32 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_36 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_40 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_44 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_48 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_52 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_56 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_60 0 0.000% 0 0.000%
MEM_REQ_WRITEBACKS_64 0 0.000% 0 0.000%
 336256 100.000% 336256 100.000%
 0.00 0.02 0.00 0.02
MEM_REQ_DEMAND_CYCLES 932466 932466
MEM_REQ_PREF_CYCLES 1898375 1898375
MEM_REQ_WB_CYCLES 271949 271949
DRAM_CHANNEL_REQS 0 0
DRAM_CHANNEL_CRIT_REQS 0 0
DRAM_CHANNEL_CRIT_DIR_SWITCHES 0 0
DRAM_BANK_CRIT_REQS 0 0
DRAM_INSTA_MLP_SAMPLES 0 0
DRAM_INSTA_MLP_UNIQUE_REQS 0 -nan 0 -nan
DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000 0 -nan 0 -nan
DRAM_GLOBAL_MLP 0 -nan 0 -nan
DRAM_GLOBAL_MLP_0 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_1 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_2 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_3 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_4 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_5 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_6 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_7 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_8 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_9 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_10 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_11 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_12 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_13 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_14 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_15 0 -nan% 0 -nan%
DRAM_GLOBAL_MLP_16 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_TOTAL_GLOBAL_MLP_0 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_1 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_2 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_3 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_4 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_5 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_6 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_7 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_8 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_9 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_10 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_11 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_12 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_13 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_14 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_15 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_16 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_17 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_18 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_19 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_20 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_21 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_22 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_23 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_24 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_25 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_26 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_27 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_28 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_29 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_30 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_31 0 -nan% 0 -nan%
DRAM_TOTAL_GLOBAL_MLP_32 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
UNIQUE_ROWS_PER_BANK_0 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_1 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_2 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_3 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_4 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_5 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_6 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_7 0 -nan% 0 -nan%
UNIQUE_ROWS_PER_BANK_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORE_UNIQUE_ROWS_PER_BANK_0 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_1 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_2 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_3 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_4 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_5 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_6 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_7 0 -nan% 0 -nan%
CORE_UNIQUE_ROWS_PER_BANK_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
CORES_PER_BANK_0 0 -nan% 0 -nan%
CORES_PER_BANK_1 0 -nan% 0 -nan%
CORES_PER_BANK_2 0 -nan% 0 -nan%
CORES_PER_BANK_3 0 -nan% 0 -nan%
CORES_PER_BANK_4 0 -nan% 0 -nan%
CORES_PER_BANK_5 0 -nan% 0 -nan%
CORES_PER_BANK_6 0 -nan% 0 -nan%
CORES_PER_BANK_7 0 -nan% 0 -nan%
CORES_PER_BANK_MORE 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_BANKS_WITH_REQS_0 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_1 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_2 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_3 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_4 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_5 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_6 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_7 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_8 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_9 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_10 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_11 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_12 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_13 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_14 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_15 0 -nan% 0 -nan%
MEM_BANKS_WITH_REQS_16 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_BANKS_WITH_REQS 0 0
DRAM_CHANNEL_IN_DEMAND 0 0
DRAM_BUS_IN_DEMAND 0 0
DRAM_BANK_IN_DEMAND 0 0
DRAM_BANK_IN_DEMAND_STALLING 0 0
DRAM_ANY_BANK_IN_DEMAND 0 0
DRAM_BANK_IN_DEMAND_BANK_0 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_1 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_2 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_3 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_4 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_5 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_6 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_7 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_8 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_9 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_10 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_11 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_12 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_13 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_14 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_15 0 -nan% 0 -nan%
DRAM_BANK_IN_DEMAND_BANK_16 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_CONTENTION_BUS 0 -nan 0 -nan
DRAM_CONTENTION_BANKS 0 -nan 0 -nan
DRAM_CONTENTION_FAW 0 -nan 0 -nan
DRAM_CONTENTION_BANKS_TIMES_1000 0 -nan 0 -nan
DRAM_STALL_OTHER_CORE 0 0
DRAM_STALLED_BY_OTHER_CORE 0 0
DRAM_MP_CRIT_PATH 0 0
DRAM_MP_CRIT_PATH_BUS 0 -nan 0 -nan
DRAM_MP_CRIT_PATH_BANK 0 -nan 0 -nan
DRAM_MP_CRIT_PATH_BANK_TRAS 0 -nan 0 -nan
DRAM_MP_CRIT_PATH_FAW 0 -nan 0 -nan
DRAM_BLACK_BOX_SERVICE_TIMES_1000 0 0
DRAM_BLACK_BOX_REQS_BUSY_0 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_1 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_2 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_3 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_4 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_5 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_6 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_7 0 -nan% 0 -nan%
DRAM_BLACK_BOX_REQS_BUSY_8 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
NUM_MEM_SCHED_DECISIONS 0 0
MEM_REQ_NON_SCHEDULED_CANDIDATES 0 -nan 0 -nan
NUM_MEM_SCHED_DECISIONS_PER_BANK 0 0
MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK 0 -nan 0 -nan
ROW_BUFFER_HITS_BANK_0 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_1 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_2 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_3 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_4 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_5 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_6 0 -nan% 0 -nan%
ROW_BUFFER_HITS_BANK_7 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
ROW_BUFFER_CONFLICTS_BANK_0 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_1 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_2 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_3 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_4 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_5 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_6 0 -nan% 0 -nan%
ROW_BUFFER_CONFLICTS_BANK_7 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
MEM_BANK_WAITING_CYCLES 0 0
MEM_WAITING_CYCLES_TIMES_840 0 0
MEM_PROB_WAITING_CYCLES 0 0
DRAM_SCHED_QUANTA 0 0
DRAM_SCHED_CORE_PRIORITY_0 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_1 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_2 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_3 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_4 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_5 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_6 0 -nan% 0 -nan%
DRAM_SCHED_CORE_PRIORITY_7 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_SCHED_CMD_SCHEDULED 0 -nan 0 -nan
DRAM_SCHED_DIFF_CORE_AVAILABLE 0 -nan 0 -nan
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_1 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_2 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_3 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_4 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_5 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_6 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_7 0 -nan% 0 -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_8 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_BANK_WAIT_CYCLES_ROW_CONFLICT 0 0
DRAM_BANK_WAIT_CYCLES_ROW_MISS 0 0
DRAM_BANK_WAIT_CYCLES_ROW_HIT 0 0
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DRAM_NUM_REQS_22_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_22_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_22_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_22_WB 0 -nan 0 -nan
DRAM_NUM_REQS_22_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_23_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_23_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_23_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_23_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_23_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_23_WB 0 -nan 0 -nan
DRAM_NUM_REQS_23_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_24_WB 0 -nan 0 -nan
DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_25_WB 0 -nan 0 -nan
DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_26_WB 0 -nan 0 -nan
DRAM_NUM_REQS_26_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_27_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_27_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_27_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_27_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_27_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_27_WB 0 -nan 0 -nan
DRAM_NUM_REQS_27_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_28_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_28_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_28_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_28_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_28_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_28_WB 0 -nan 0 -nan
DRAM_NUM_REQS_28_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_29_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_29_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_29_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_29_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_29_WB 0 -nan 0 -nan
DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_30_WB 0 -nan 0 -nan
DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_31_WB 0 -nan 0 -nan
DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan
DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan
DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan
DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan
DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan
DRAM_NUM_REQS_32_WB 0 -nan 0 -nan
DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan
DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan%
DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan%
DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0
KNOWN_BAD_ADDRESS 0 0.000% 0 0.000%
GOOD_ADDRESS 393319 100.000% 393319 100.000%
 393319 100.000% 393319 100.000%
 1.00 1.00 1.00 1.00
BBL_LENGTH_1 0 -nan% 0 -nan%
BBL_LENGTH_2 0 -nan% 0 -nan%
BBL_LENGTH_3 0 -nan% 0 -nan%
BBL_LENGTH_4 0 -nan% 0 -nan%
BBL_LENGTH_5 0 -nan% 0 -nan%
BBL_LENGTH_6 0 -nan% 0 -nan%
BBL_LENGTH_7 0 -nan% 0 -nan%
BBL_LENGTH_8 0 -nan% 0 -nan%
BBL_LENGTH_9 0 -nan% 0 -nan%
BBL_LENGTH_10 0 -nan% 0 -nan%
BBL_LENGTH_11 0 -nan% 0 -nan%
BBL_LENGTH_12 0 -nan% 0 -nan%
BBL_LENGTH_13 0 -nan% 0 -nan%
BBL_LENGTH_14 0 -nan% 0 -nan%
BBL_LENGTH_15 0 -nan% 0 -nan%
BBL_LENGTH_16 0 -nan% 0 -nan%
BBL_LENGTH_17 0 -nan% 0 -nan%
BBL_LENGTH_18 0 -nan% 0 -nan%
BBL_LENGTH_19 0 -nan% 0 -nan%
BBL_LENGTH_20 0 -nan% 0 -nan%
BBL_LENGTH_21 0 -nan% 0 -nan%
BBL_LENGTH_22 0 -nan% 0 -nan%
BBL_LENGTH_23 0 -nan% 0 -nan%
BBL_LENGTH_24 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
BBL_DONT_END_PRED_NT_LENGTH_1 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_2 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_3 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_4 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_5 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_6 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_7 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_8 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_9 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_10 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_11 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_12 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_13 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_14 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_15 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_16 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_17 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_18 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_19 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_20 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_21 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_22 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_23 0 -nan% 0 -nan%
BBL_DONT_END_PRED_NT_LENGTH_24 0 -nan% 0 -nan%
 0 -nan% 0 -nan%
 -nan -nan -nan -nan
DATA_LD_CYCLES_ONPATH 1228654 1228654
DATA_LD_CYCLES_OFFPATH 0 0
DATA_LD_MLC_CYCLES_ONPATH 0 0
DATA_LD_MLC_CYCLES_OFFPATH 0 0
DATA_LD_MLC_ACCESSES_ONPATH 0 0
DATA_LD_MLC_ACCESSES_OFFPATH 0 0
DATA_LD_L1_CYCLES_ONPATH 856739 856739
DATA_LD_L1_CYCLES_OFFPATH 0 0
DATA_LD_L1_ACCESSES_ONPATH 14521 14521
DATA_LD_L1_ACCESSES_OFFPATH 0 0
DATA_LD_MEM_CYCLES_ONPATH 371915 371915
DATA_LD_MEM_CYCLES_OFFPATH 0 0
DATA_LD_MEM_ACCESSES_ONPATH 505 505
DATA_LD_MEM_ACCESSES_OFFPATH 0 0
DATA_LD_PREF_CYCLES_ONPATH 0 0
DATA_LD_PREF_CYCLES_OFFPATH 0 0
DATA_LD_PREF_MLC_CYCLES_ONPATH 0 0
DATA_LD_PREF_MLC_CYCLES_OFFPATH 0 0
DATA_LD_PREF_L1_CYCLES_ONPATH 0 0
DATA_LD_PREF_L1_CYCLES_OFFPATH 0 0
DATA_LD_PREF_MEM_CYCLES_ONPATH 0 0
DATA_LD_PREF_MEM_CYCLES_OFFPATH 0 0
UOP_CACHE_LINE_EVICTED_USEFUL 0 0.000% 0 0.000%
UOP_CACHE_LINE_EVICTED_USELESS 7 100.000% 7 100.000%
 7 100.000% 7 100.000%
 1.00 1.08 1.00 1.08