hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /2 /core.stat.0.out
| /* -*- Mode: c -*- */ | |
| #################################################################################################### | |
| Core 0 | |
| #################################################################################################### | |
| Cumulative: Cycles: 3811146 Instructions: 9968027 IPC: 2.61549 | |
| Periodic: Cycles: 3811146 Instructions: 9968027 IPC: 2.61549 | |
| EXECUTION_TIME 1190983125000 1190983125000 | |
| SIM_HOST_WALL_SECONDS 52.364201 52.364201 | |
| NODE_CYCLE 3811146 3811146 | |
| NODE_INST_COUNT 10000002 10000002 | |
| NODE_INST_COUNT_FETCHED 9968027 9968027 | |
| NODE_UOP_COUNT 12824509 12824509 | |
| EXEC_STAGE_NO_ISSUE_STALL_CYCLE 3104731 3104731 | |
| EXEC_STAGE_NO_ISSUE_STALL_CYCLE_ONPATH 2780155 2780155 | |
| FULL_WINDOW_STALL 17482 0.459% 17482 0.459% | |
| FULL_WINDOW_MEM_OP 17027 99.971% 17027 99.971% | |
| FULL_WINDOW_FP_OP 0 0.000% 0 0.000% | |
| FULL_WINDOW_OTHER_OP 5 0.029% 5 0.029% | |
| 17032 100.000% 17032 100.000% | |
| 0.00 0.03 0.00 0.03 | |
| RET_BLOCKED_DC_MISS 830553 21.793% 830553 21.793% | |
| RET_BLOCKED_L1_MISS 277686 7.286% 277686 7.286% | |
| RET_BLOCKED_L1_MISS_BW_PREF 9774 0.256% 9774 0.256% | |
| RET_BLOCKED_L1_ACCESS 554855 14.559% 554855 14.559% | |
| RET_BLOCKED_MEM_STALL 278072 7.296% 278072 7.296% | |
| RET_BLOCKED_OFFCHIP_DEMAND 0 0.000% 0 0.000% | |
| OP_ISSUED 13729737 13729737 | |
| OP_RETIRED 12824509 12824509 | |
| OP_MACRO_FUSION_ONPATH 930742 930742 | |
| OP_MACRO_FUSION_OFFPATH 141944 141944 | |
| REPLAY_SIGNALED 0 0 | |
| REPLAY_COUNTED 0 0 | |
| OFF_CRITICAL_PATH 0 -nan% 0 -nan% | |
| ON_CRITICAL_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| LD_NO_DEPENDENTS 239127 8.960% 239127 8.960% | |
| LD_DEPENDENTS 2429802 91.040% 2429802 91.040% | |
| 2668929 100.000% 2668929 100.000% | |
| 0.91 0.87 0.91 0.87 | |
| LD_EXEC_CYCLES_0 0 0.000% 0 0.000% | |
| LD_EXEC_CYCLES_1 0 0.000% 0 0.000% | |
| LD_EXEC_CYCLES_2 0 0.000% 0 0.000% | |
| LD_EXEC_CYCLES_3 249 33.970% 249 33.970% | |
| LD_EXEC_CYCLES_4 484 66.030% 484 66.030% | |
| 733 100.000% 733 100.000% | |
| 3.66 3.01 3.66 3.01 | |
| ICACHE_STAGE_STARVED 395993 13.328% 395993 13.328% | |
| ICACHE_STAGE_NOT_STARVED 2575078 86.672% 2575078 86.672% | |
| 2971071 100.000% 2971071 100.000% | |
| 0.87 0.82 0.87 0.82 | |
| ICACHE_STAGE_STALLED 434471 11.400% 434471 11.400% | |
| ICACHE_STAGE_NOT_STALLED 2536600 66.557% 2536600 66.557% | |
| ICACHE_STAGE_OFF_PATH 840075 22.043% 840075 22.043% | |
| 3811146 100.000% 3811146 100.000% | |
| 1.11 0.67 1.11 0.67 | |
| DECODE_STAGE_STARVED 2203400 67.477% 2203400 67.477% | |
| DECODE_STAGE_NOT_STARVED 1061991 32.523% 1061991 32.523% | |
| 3265391 100.000% 3265391 100.000% | |
| 0.33 0.43 0.33 0.43 | |
| DECODE_STAGE_STALLED 206303 5.413% 206303 5.413% | |
| DECODE_STAGE_NOT_STALLED 3059088 80.267% 3059088 80.267% | |
| DECODE_STAGE_OFF_PATH 545755 14.320% 545755 14.320% | |
| 3811146 100.000% 3811146 100.000% | |
| 1.09 0.54 1.09 0.54 | |
| UOPQ_STAGE_STARVED 1619656 58.040% 1619656 58.040% | |
| UOPQ_STAGE_NOT_STARVED 1170926 41.960% 1170926 41.960% | |
| 2790582 100.000% 2790582 100.000% | |
| 0.42 0.46 0.42 0.46 | |
| UOPQ_STAGE_STALLED 345255 9.059% 345255 9.059% | |
| UOPQ_STAGE_NOT_STALLED 2790582 73.222% 2790582 73.222% | |
| UOPQ_STAGE_OFF_PATH 675309 17.719% 675309 17.719% | |
| 3811146 100.000% 3811146 100.000% | |
| 1.09 0.60 1.09 0.60 | |
| RS_OP_READY_NOT_ISSUED_TOTAL 4300312 4300312 | |
| RS_0_OP_READY_NOT_ISSUED 3138461 3138461 | |
| RS_1_OP_READY_NOT_ISSUED 371450 371450 | |
| RS_2_OP_READY_NOT_ISSUED 790401 790401 | |
| RS_3_OP_READY_NOT_ISSUED 0 0 | |
| RS_4_OP_READY_NOT_ISSUED 0 0 | |
| RS_5_OP_READY_NOT_ISSUED 0 0 | |
| RS_6_OP_READY_NOT_ISSUED 0 0 | |
| RS_7_OP_READY_NOT_ISSUED 0 0 | |
| RS_7_PLUS_OP_READY_NOT_ISSUED 0 0 | |
| FU_IDLE_NO_READY_OPS_TOTAL 13301414 13301414 | |
| FU_0_IDLE_NO_READY_OPS 735720 735720 | |
| FU_1_IDLE_NO_READY_OPS 847188 847188 | |
| FU_2_IDLE_NO_READY_OPS 1662384 1662384 | |
| FU_3_IDLE_NO_READY_OPS 1662840 1662840 | |
| FU_4_IDLE_NO_READY_OPS 855539 855539 | |
| FU_5_IDLE_NO_READY_OPS 726353 726353 | |
| FU_6_IDLE_NO_READY_OPS 2149620 2149620 | |
| FU_7_IDLE_NO_READY_OPS 2149523 2149523 | |
| FU_8_IDLE_NO_READY_OPS 850032 850032 | |
| FU_9_IDLE_NO_READY_OPS 1662215 1662215 | |
| FU_10_IDLE_NO_READY_OPS 0 0 | |
| FU_11_IDLE_NO_READY_OPS 0 0 | |
| FU_12_IDLE_NO_READY_OPS 0 0 | |
| FU_13_IDLE_NO_READY_OPS 0 0 | |
| FU_14_IDLE_NO_READY_OPS 0 0 | |
| FU_15_IDLE_NO_READY_OPS 0 0 | |
| FU_16_IDLE_NO_READY_OPS 0 0 | |
| FU_17_IDLE_NO_READY_OPS 0 0 | |
| FU_18_IDLE_NO_READY_OPS 0 0 | |
| FU_19_IDLE_NO_READY_OPS 0 0 | |
| FU_20_IDLE_NO_READY_OPS 0 0 | |
| FU_21_IDLE_NO_READY_OPS 0 0 | |
| FU_22_IDLE_NO_READY_OPS 0 0 | |
| FU_23_IDLE_NO_READY_OPS 0 0 | |
| FU_24_IDLE_NO_READY_OPS 0 0 | |
| FU_25_IDLE_NO_READY_OPS 0 0 | |
| FU_26_IDLE_NO_READY_OPS 0 0 | |
| FU_27_IDLE_NO_READY_OPS 0 0 | |
| FU_28_IDLE_NO_READY_OPS 0 0 | |
| FU_29_IDLE_NO_READY_OPS 0 0 | |
| FU_30_IDLE_NO_READY_OPS 0 0 | |
| FU_31_IDLE_NO_READY_OPS 0 0 | |
| FU_31_PLUS_IDLE_NO_READY_OPS 0 0 | |
| MAP_STAGE_STARVED 400173 15.050% 400173 15.050% | |
| MAP_STAGE_NOT_STARVED 2258787 84.950% 2258787 84.950% | |
| 2658960 100.000% 2658960 100.000% | |
| 0.85 0.80 0.85 0.80 | |
| MAP_STAGE_STALLED 2585 0.084% 2585 0.084% | |
| MAP_STAGE_NOT_STALLED 2656375 86.410% 2656375 86.410% | |
| MAP_STAGE_OFF_PATH 415177 13.505% 415177 13.505% | |
| 3074137 100.000% 3074137 100.000% | |
| 1.13 0.54 1.13 0.54 | |
| MAP_STAGE_STALL_ITSELF 737009 19.338% 737009 19.338% | |
| MAP_STAGE_NOT_STALL_ITSELF 3074137 80.662% 3074137 80.662% | |
| 3811146 100.000% 3811146 100.000% | |
| 0.81 0.74 0.81 0.74 | |
| MAP_STAGE_LATE_ALLOCATE_SEND_BACK 0 0 | |
| MAP_STAGE_RENAME_OP_ONPATH 12824767 12824767 | |
| MAP_STAGE_RENAME_OP_OFFPATH 1956865 1956865 | |
| MAP_STAGE_RENAME_INT_REG_ONPATH 10845505 10845505 | |
| MAP_STAGE_RENAME_INT_REG_OFFPATH 1529244 1529244 | |
| MAP_STAGE_RENAME_VEC_REG_ONPATH 51447 51447 | |
| MAP_STAGE_RENAME_VEC_REG_OFFPATH 7870 7870 | |
| MAP_STAGE_RENAME_MOVE_ELIM_ONPATH 0 0 | |
| MAP_STAGE_RENAME_MOVE_ELIM_OFFPATH 0 0 | |
| REG_FILE_UTIL_SAMPLES 3811146 3811146 | |
| REG_FILE_INT_PHYS_REGS_SUM 1067120880 1067120880 | |
| REG_FILE_VEC_PHYS_REGS_SUM 1265300472 1265300472 | |
| REG_FILE_INT_OCCUPIED_SUM 689769340 689769340 | |
| REG_FILE_VEC_OCCUPIED_SUM 125576451 125576451 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_ALLOC 10845271 10845271 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_ALLOC 51438 51438 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_SHORTLIVE 4376176 4376176 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_SHORTLIVE 11456 11456 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_0 2090644 2090644 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_0 290 290 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_1 5303711 5303711 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_1 44930 44930 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_2 2477911 2477911 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_2 5634 5634 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_3 655242 655242 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_3 462 462 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_4 124593 124593 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_4 41 41 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_5 74955 74955 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_5 0 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_6 23336 23336 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_6 0 0 | |
| MAP_STAGE_ONPATH_INT_REG_USE_COUNT_7_PLUS 94879 94879 | |
| MAP_STAGE_ONPATH_VEC_REG_USE_COUNT_7_PLUS 81 81 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_0 0 0.0000 0 0.0000 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_0 0 0.0000 0 0.0000 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_1 0 0.0000 0 0.0000 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_1 0 0.0000 0 0.0000 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_2 7698993 3.1070 7698993 3.1070 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_2 368028 65.3227 368028 65.3227 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_3 3557115 5.4287 3557115 5.4287 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_3 27441 59.3961 27441 59.3961 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_4 1795295 14.4093 1795295 14.4093 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_4 4303 104.9512 4303 104.9512 | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_5 1157792 15.4465 1157792 15.4465 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_5 0 -nan 0 -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_6 545001 23.3545 545001 23.3545 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_6 0 -nan 0 -nan | |
| MAP_STAGE_ONPATH_INT_REG_CONSUME_DIST_7_PLUS 3023240 31.8642 3023240 31.8642 | |
| MAP_STAGE_ONPATH_VEC_REG_CONSUME_DIST_7_PLUS 469 5.7901 469 5.7901 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED 15378571 4.9533 15378571 4.9533 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED 60757 0.0196 60757 0.0196 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED 6184151 1.9918 6184151 1.9918 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED 8147 0.0026 8147 0.0026 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED 3606903 1.1617 3606903 1.1617 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED 2495 0.0008 2495 0.0008 | |
| MAP_STAGE_INT_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH 14554350 5.2351 14554350 5.2351 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_TOTAL_CONSUMED_ONPATH 58405 0.0210 58405 0.0210 | |
| MAP_STAGE_INT_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH 5799667 2.0861 5799667 2.0861 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_MULTI_CONSUMED_ONPATH 7248 0.0026 7248 0.0026 | |
| MAP_STAGE_INT_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH 3392050 1.2201 3392050 1.2201 | |
| MAP_STAGE_VEC_REG_ISSUE_READ_SAME_CYCLE_CONSUMED_ONPATH 2422 0.0009 2422 0.0009 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_EMPTY 257135693 257135693 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_EMPTY 2096741 2096741 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_IN_USE 373101420 373101420 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_IN_USE 3142432 3142432 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_SPEC_RELEASE 630737374 630737374 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_SPEC_RELEASE 35663900 35663900 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_NONSPEC_RELEASE 630737374 630737374 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_NONSPEC_RELEASE 35663900 35663900 | |
| MAP_STAGE_ONPATH_INT_REG_LIFECYCLE_TOTAL 630737374 630737374 | |
| MAP_STAGE_ONPATH_VEC_REG_LIFECYCLE_TOTAL 35663900 35663900 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_NONBRANCH 10845271 10845271 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_NONBRANCH 51438 51438 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_NONEXCEPT 10845271 10845271 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_NONEXCEPT 51438 51438 | |
| MAP_STAGE_ONPATH_INT_REG_NUM_ATOMIC 10845271 10845271 | |
| MAP_STAGE_ONPATH_VEC_REG_NUM_ATOMIC 51438 51438 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_REDEFINED_DIST_TOTAL 630737374 58.1578 630737374 58.1578 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_REDEFINED_DIST_TOTAL 35663900 693.3376 35663900 693.3376 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_CONSUMED_DIST_TOTAL 373101420 34.4022 373101420 34.4022 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_CONSUMED_DIST_TOTAL 3142432 61.0916 3142432 61.0916 | |
| MAP_STAGE_ONPATH_INT_REG_ATOMIC_RELEASE_DIST_TOTAL 630737374 58.1578 630737374 58.1578 | |
| MAP_STAGE_ONPATH_VEC_REG_ATOMIC_RELEASE_DIST_TOTAL 35663900 693.3376 35663900 693.3376 | |
| EXEC_STAGE_STARVED 3126483 82.035% 3126483 82.035% | |
| EXEC_STAGE_NOT_STARVED 277528 7.282% 277528 7.282% | |
| EXEC_STAGE_OFF_PATH 407135 10.683% 407135 10.683% | |
| 3811146 100.000% 3811146 100.000% | |
| 0.29 0.60 0.29 0.60 | |
| FU_BUSY_0 2015920 2015920 | |
| FU_BUSY_1 1671616 1671616 | |
| FU_BUSY_2 1034155 1034155 | |
| FU_BUSY_3 1033533 1033533 | |
| FU_BUSY_4 1559183 1559183 | |
| FU_BUSY_5 2107563 2107563 | |
| FU_BUSY_6 976169 976169 | |
| FU_BUSY_7 975872 975872 | |
| FU_BUSY_8 1653851 1653851 | |
| FU_BUSY_9 1034102 1034102 | |
| FU_BUSY_10 0 0 | |
| FU_BUSY_11 0 0 | |
| FU_BUSY_12 0 0 | |
| FU_BUSY_13 0 0 | |
| FU_BUSY_14 0 0 | |
| FU_BUSY_15 0 0 | |
| FU_BUSY_16 0 0 | |
| FU_BUSY_17 0 0 | |
| FU_BUSY_18 0 0 | |
| FU_BUSY_19 0 0 | |
| FU_BUSY_20 0 0 | |
| FU_BUSY_21 0 0 | |
| FU_BUSY_22 0 0 | |
| FU_BUSY_23 0 0 | |
| FU_BUSY_24 0 0 | |
| FU_BUSY_25 0 0 | |
| FU_BUSY_26 0 0 | |
| FU_BUSY_27 0 0 | |
| FU_BUSY_28 0 0 | |
| FU_BUSY_29 0 0 | |
| FU_BUSY_30 0 0 | |
| FU_BUSY_31 0 0 | |
| FU_REJECTED_OP_INV_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOP_NOT_SIMD 41 0.027% 41 0.027% | |
| FU_REJECTED_OP_CF_NOT_SIMD 4762 3.160% 4762 3.160% | |
| FU_REJECTED_OP_MOV_NOT_SIMD 1359 0.902% 1359 0.902% | |
| FU_REJECTED_OP_CMOV_NOT_SIMD 8 0.005% 8 0.005% | |
| FU_REJECTED_OP_LDA_NOT_SIMD 141 0.094% 141 0.094% | |
| FU_REJECTED_OP_IMEM_NOT_SIMD 88953 59.029% 88953 59.029% | |
| FU_REJECTED_OP_IADD_NOT_SIMD 34998 23.225% 34998 23.225% | |
| FU_REJECTED_OP_IMUL_NOT_SIMD 5717 3.794% 5717 3.794% | |
| FU_REJECTED_OP_IDIV_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_ICMP_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_LOGIC_NOT_SIMD 944 0.626% 944 0.626% | |
| FU_REJECTED_OP_SHIFT_NOT_SIMD 362 0.240% 362 0.240% | |
| FU_REJECTED_OP_FMEM_NOT_SIMD 1424 0.945% 1424 0.945% | |
| FU_REJECTED_OP_FCVT_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FADD_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FMUL_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FMA_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FDIV_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FCMP_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FCMOV_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_GATHER_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_SCATTER_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_PIPELINED_FAST_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_PIPELINED_MEDIUM_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_PIPELINED_SLOW_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOTPIPELINED_MEDIUM_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOTPIPELINED_SLOW_NOT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOTPIPELINED_VERY_SLOW_NOT_SIMD 52 0.035% 52 0.035% | |
| FU_REJECTED_OP_INV_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOP_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_CF_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_MOV_SIMD 1 0.001% 1 0.001% | |
| FU_REJECTED_OP_CMOV_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_LDA_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_IMEM_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_IADD_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_IMUL_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_IDIV_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_ICMP_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_LOGIC_SIMD 5 0.003% 5 0.003% | |
| FU_REJECTED_OP_SHIFT_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FMEM_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FCVT_SIMD 5990 3.975% 5990 3.975% | |
| FU_REJECTED_OP_FADD_SIMD 5918 3.927% 5918 3.927% | |
| FU_REJECTED_OP_FMUL_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FMA_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FDIV_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FCMP_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_FCMOV_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_GATHER_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_SCATTER_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_PIPELINED_FAST_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_PIPELINED_MEDIUM_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_PIPELINED_SLOW_SIMD 18 0.012% 18 0.012% | |
| FU_REJECTED_OP_NOTPIPELINED_MEDIUM_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOTPIPELINED_SLOW_SIMD 0 0.000% 0 0.000% | |
| FU_REJECTED_OP_NOTPIPELINED_VERY_SLOW_SIMD 0 0.000% 0 0.000% | |
| 150693 100.000% 150693 100.000% | |
| 9.24 10.14 9.24 10.14 | |
| LSQ_FULL_TOTAL 7988 7988 | |
| LSQ_FULL_LOAD_QUEUE 0 0 | |
| LSQ_FULL_STORE_QUEUE 7988 7988 | |
| OP_WAIT_0 10102687 10102687 | |
| OP_WAIT_1 1657169 1657169 | |
| OP_WAIT_2 355458 355458 | |
| OP_WAIT_3 189997 189997 | |
| OP_WAIT_4 114702 114702 | |
| OP_WAIT_5 65476 65476 | |
| OP_WAIT_6 43148 43148 | |
| OP_WAIT_7 30181 30181 | |
| OP_WAIT_8 24181 24181 | |
| OP_WAIT_9 23484 23484 | |
| OP_WAIT_10 19831 19831 | |
| OP_WAIT_11 15903 15903 | |
| OP_WAIT_12 13233 13233 | |
| OP_WAIT_13 10983 10983 | |
| OP_WAIT_14 9361 9361 | |
| OP_WAIT_15 9589 9589 | |
| OP_WAIT_16 8473 8473 | |
| OP_WAIT_17 8274 8274 | |
| OP_WAIT_18 8151 8151 | |
| OP_WAIT_19 7211 7211 | |
| OP_WAIT_20 5914 5914 | |
| OP_WAIT_21 6862 6862 | |
| OP_WAIT_22 6902 6902 | |
| OP_WAIT_23 6177 6177 | |
| OP_WAIT_24 5706 5706 | |
| OP_WAIT_25 5423 5423 | |
| OP_WAIT_26 4680 4680 | |
| OP_WAIT_27 4372 4372 | |
| OP_WAIT_28 4410 4410 | |
| OP_WAIT_29 3960 3960 | |
| OP_WAIT_30 3935 3935 | |
| OP_WAIT_31 48676 48676 | |
| ROW_SIZE_0 1434884 1434884 | |
| ROW_SIZE_1 350374 350374 | |
| ROW_SIZE_2 179684 179684 | |
| ROW_SIZE_3 89583 89583 | |
| ROW_SIZE_4 93250 93250 | |
| ROW_SIZE_5 45194 45194 | |
| ROW_SIZE_6 38238 38238 | |
| ROW_SIZE_7 40940 40940 | |
| ROW_SIZE_8 1341380 1341380 | |
| ROW_SIZE_9 0 0 | |
| ROW_SIZE_10 0 0 | |
| ROW_SIZE_11 0 0 | |
| ROW_SIZE_12 0 0 | |
| ROW_SIZE_13 0 0 | |
| ROW_SIZE_14 0 0 | |
| ROW_SIZE_15 0 0 | |
| ROW_SIZE_16 0 0 | |
| ROW_SIZE_17 0 0 | |
| ROW_SIZE_18 0 0 | |
| ROW_SIZE_19 0 0 | |
| ROW_SIZE_20 0 0 | |
| ROW_SIZE_21 0 0 | |
| ROW_SIZE_22 0 0 | |
| ROW_SIZE_23 0 0 | |
| ROW_SIZE_24 0 0 | |
| ROW_SIZE_25 0 0 | |
| ROW_SIZE_26 0 0 | |
| ROW_SIZE_27 0 0 | |
| ROW_SIZE_28 0 0 | |
| ROW_SIZE_29 0 0 | |
| ROW_SIZE_30 0 0 | |
| ROW_SIZE_31 0 0 | |
| RET_OP_EXEC_COUNT_0 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_1 12824509 100.000% 12824509 100.000% | |
| RET_OP_EXEC_COUNT_2 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_3 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_4 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_5 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_6 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_7 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_8 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_9 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_10 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_11 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_12 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_13 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_14 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_15 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_16 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_17 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_18 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_19 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_20 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_21 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_22 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_23 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_24 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_25 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_26 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_27 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_28 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_29 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_30 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_31 0 0.000% 0 0.000% | |
| RET_OP_EXEC_COUNT_32 0 0.000% 0 0.000% | |
| 12824509 100.000% 12824509 100.000% | |
| 1.00 0.00 1.00 0.00 | |
| RET_STALL_LENGTH_0 12822487 99.984% 12822487 99.984% | |
| RET_STALL_LENGTH_100 1740 0.014% 1740 0.014% | |
| RET_STALL_LENGTH_200 225 0.002% 225 0.002% | |
| RET_STALL_LENGTH_300 11 0.000% 11 0.000% | |
| RET_STALL_LENGTH_400 2 0.000% 2 0.000% | |
| RET_STALL_LENGTH_500 6 0.000% 6 0.000% | |
| RET_STALL_LENGTH_600 3 0.000% 3 0.000% | |
| RET_STALL_LENGTH_700 3 0.000% 3 0.000% | |
| RET_STALL_LENGTH_800 3 0.000% 3 0.000% | |
| RET_STALL_LENGTH_900 4 0.000% 4 0.000% | |
| RET_STALL_LENGTH_1000 4 0.000% 4 0.000% | |
| RET_STALL_LENGTH_1100 5 0.000% 5 0.000% | |
| RET_STALL_LENGTH_1200 13 0.000% 13 0.000% | |
| RET_STALL_LENGTH_1300 3 0.000% 3 0.000% | |
| RET_STALL_LENGTH_1400 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_1500 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_1600 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_1700 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_1800 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_1900 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2000 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2100 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2200 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2300 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2400 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2500 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2600 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2700 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2800 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_2900 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3000 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3100 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3200 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3300 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3400 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3500 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3600 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3700 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3800 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_3900 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4000 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4100 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4200 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4300 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4400 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4500 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4600 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4700 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4800 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_4900 0 0.000% 0 0.000% | |
| RET_STALL_LENGTH_5000 0 0.000% 0 0.000% | |
| 12824509 100.000% 12824509 100.000% | |
| 0.00 0.02 0.00 0.02 | |
| MEM_BLOCK_LENGTH_0 80 97.561% 80 97.561% | |
| MEM_BLOCK_LENGTH_100 2 2.439% 2 2.439% | |
| MEM_BLOCK_LENGTH_200 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_300 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_400 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_500 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_600 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_700 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_800 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_900 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1000 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1100 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1200 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1300 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1400 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1500 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1600 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1700 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1800 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_1900 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2000 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2100 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2200 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2300 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2400 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2500 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2600 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2700 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2800 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_2900 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3000 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3100 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3200 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3300 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3400 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3500 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3600 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3700 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3800 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_3900 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4000 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4100 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4200 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4300 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4400 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4500 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4600 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4700 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4800 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_4900 0 0.000% 0 0.000% | |
| MEM_BLOCK_LENGTH_5000 0 0.000% 0 0.000% | |
| 82 100.000% 82 100.000% | |
| 0.02 0.15 0.02 0.15 | |
| FUS_BUSY_ON_PATH 13140167 3.4478 13140167 3.4478 | |
| FUS_BUSY_OFF_PATH 921797 0.2419 921797 0.2419 | |
| FU_BUSY_MEM_STALL 305057 0.0800 305057 0.0800 | |
| FUS_EMPTY 24049496 6.3103 24049496 6.3103 | |
| FU_UNAVAILABLE 15022 0.0039 15022 0.0039 | |
| FU_MEM_UNAVAILABLE 135671 0.0356 135671 0.0356 | |
| FU_OTHER_UNAVAILABLE 0 0.0000 0 0.0000 | |
| FU_REPLAY 0 0.0000 0 0.0000 | |
| FU_STARVED 23995108 6.2960 23995108 6.2960 | |
| CHIP_UTILIZATION 0 0.0000 0 0.0000 | |
| CYCLES_UNDER_MEM_REQ 0 0 | |
| CYCLES_UNDER_NO_MEM_REQ 0 0 | |
| CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 | |
| CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 | |
| CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan | |
| CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan | |
| CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan | |
| CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan | |
| CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 | |
| FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan | |
| CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 | |
| FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan | |
| TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 | |
| WRONG_IO_SCHED 0 0 | |
| DVFS_CONFIG_SWITCH 0 0 | |
| MAP_STAGE_RECEIVED_OPS_0 0 0.000% 0 0.000% | |
| MAP_STAGE_RECEIVED_OPS_1 32514 1.450% 32514 1.450% | |
| MAP_STAGE_RECEIVED_OPS_2 39202 1.748% 39202 1.748% | |
| MAP_STAGE_RECEIVED_OPS_3 55923 2.493% 55923 2.493% | |
| MAP_STAGE_RECEIVED_OPS_4 64258 2.865% 64258 2.865% | |
| MAP_STAGE_RECEIVED_OPS_5 42260 1.884% 42260 1.884% | |
| MAP_STAGE_RECEIVED_OPS_6 2008956 89.561% 2008956 89.561% | |
| MAP_STAGE_RECEIVED_OPS_7 0 0.000% 0 0.000% | |
| MAP_STAGE_RECEIVED_OPS_8 0 0.000% 0 0.000% | |
| MAP_STAGE_RECEIVED_OPS_MAX 0 0.000% 0 0.000% | |
| 2243113 100.000% 2243113 100.000% | |
| 5.71 0.96 5.71 0.96 | |
| MAP_STAGE_WAIT_FOR_DECODE 0 -nan% 0 -nan% | |
| MAP_STAGE_CONSUME_DECODE 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| MAP_STAGE_WAIT_FOR_DECODE2 0 -nan% 0 -nan% | |
| MAP_STAGE_CONSUME_DECODE2 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FTQ_RECOVER_EXEC 13185 13185 | |
| FTQ_RECOVER_DECODE 700 700 | |
| FTQ_OFFPATH_CYCLES 2408145 2408145 | |
| FTQ_CYCLES_OFFPATH 2408145 2408145 | |
| FTQ_CYCLES_ONPATH 1403001 1403001 | |
| FTQ_FETCHED_INS_ONPATH 12825187 12825187 | |
| FTQ_FETCHED_INS_OFFPATH 16792774 16792774 | |
| FTQ_BREAK_FULL_FT_ONPATH 593354 593354 | |
| FTQ_BREAK_FULL_FT_OFFPATH 791540 791540 | |
| FTQ_BREAK_PRED_BR_ONPATH 0 0 | |
| FTQ_BREAK_PRED_BR_OFFPATH 0 0 | |
| FTQ_BREAK_BAR_FETCH_ONPATH 0 0 | |
| FTQ_BREAK_BAR_FETCH_OFFPATH 0 0 | |
| FTQ_BREAK_MAX_CFS_TAKEN_ONPATH 0 0 | |
| FTQ_BREAK_MAX_CFS_TAKEN_OFFPATH 0 0 | |
| FTQ_BREAK_MAX_FT_ONPATH 809647 809647 | |
| FTQ_BREAK_MAX_FT_OFFPATH 1616605 1616605 | |
| DFE_GEN_ON_PATH_FT 1616458 1616458 | |
| DFE_GEN_OFF_PATH_FT 1425715 1425715 | |
| DFE_L0_ENABLED_PREDICTIONS 12825187 12825187 | |
| DFE_L0_WRONG_MAIN_CORRECT 535998 535998 | |
| DFE_L0_WRONG_MAIN_WRONG 11027 11027 | |
| DFE_L0_CORRECT_MAIN_WRONG 2858 2858 | |
| DFE_L0_CORRECT_MAIN_CORRECT 12275304 12275304 | |
| DFE_L0_WRONG_MAIN_CORRECT_RECOVERY_SCHEDULED 0 0 | |
| FTQ_SAW_BAR_FETCH_OFFPATH 132 132 | |
| FTQ_SAW_BAR_FETCH_ONPATH 129 129 | |
| DFE_CONF_0_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| DFE_CONF_1_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| DFE_CONF_2_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| DFE_CONF_3_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| DFE_CONF_0_CORRECT 0 -nan% 0 -nan% | |
| DFE_CONF_1_CORRECT 0 -nan% 0 -nan% | |
| DFE_CONF_2_CORRECT 0 -nan% 0 -nan% | |
| DFE_CONF_3_CORRECT 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_ON_CONF_ON_OPS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_OPS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_OPS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_OFF_REALISTIC_OPS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_OFF_PERFECT_OPS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_ON_CONF_ON_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_OFF_REALISTIC_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_OFF_PERFECT_FETCH_TARGETS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_ON_CONF_ON_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_OFF_REALISTIC_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_OFF_PERFECT_CYCLES 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_OFF_CONF_ON_NUM_EVENTS 0 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_EVENTS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_IBTB_MISS_EVENTS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_EVENTS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_EVENTS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_EVENTS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_EVENTS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_EVENTS 0 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_IBTB_MISS_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_CYCLES 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_CYCLES 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_CYCLES 0 0 | |
| DFE_OFF_CONF_ON_NOT_IDENTIFIED_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_IBTB_MISS_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_RECOVER_AT_EXEC_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_RECOVER_AT_EXEC_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_RECOVER_AT_DECODE_FETCH_TARGETS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_OFF_CONF_ON_LATE_BTB_HIT_FETCH_TARGETS 0 0 | |
| DFE_OFF_CONF_ON_BP_INCORRECT_0_CONF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BP_INCORRECT_1_CONF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BP_INCORRECT_2_CONF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BP_INCORRECT_3_CONF 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_0_CONF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_1_CONF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_2_CONF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CBR_3_CONF 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_OFF_CONF_ON_BTB_MISS_NOT_CF 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_BR 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_CBR 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_CALL 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_IBR 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_ICALL 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_ICO 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_RET 0 -nan% 0 -nan% | |
| DFE_OFF_CONF_ON_BTB_MISS_CF_SYS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_ON_CONF_OFF_NUM_EVENTS 0 0 | |
| CONF_BTB_NUM_CYCLES_OFF_PATH_EVENT 0 0 | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_INV_CONF_INC 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_PERFECT_CONF 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_INV_CONF_INC_CYCLES 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_PERFECT_CONF_CYCLES 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| DFE_ON_CONF_OFF_IBTB_MISS_BP_TAKEN_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_BTB_MISS_RATE_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_IBTB_MISS_RATE_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_RECOVER_AT_DECODE_RATE_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_RECOVER_AT_EXEC_RATE_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_INV_CONF_INC_FETCH_TARGETS 0 -nan% 0 -nan% | |
| DFE_ON_CONF_OFF_PERFECT_CONF_FETCH_TARGETS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CONF_OFF_IBTB_MISS_BP_TAKEN 0 -nan% 0 -nan% | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_0 0 -nan% 0 -nan% | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_1 0 -nan% 0 -nan% | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_2 0 -nan% 0 -nan% | |
| CONF_OFF_BTB_MISS_BP_TAKEN_CONF_3 0 -nan% 0 -nan% | |
| CONF_OFF_BTB_MISS_RATE 0 -nan% 0 -nan% | |
| CONF_OFF_IBTB_MISS_RATE 0 -nan% 0 -nan% | |
| CONF_OFF_RECOVER_AT_DECODE_RATE 0 -nan% 0 -nan% | |
| CONF_OFF_RECOVER_AT_EXEC_RATE 0 -nan% 0 -nan% | |
| CONF_OFF_INV_CONF_INC 0 -nan% 0 -nan% | |
| CONF_OFF_PERFECT_CONF 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| TOPDOWN_TOTAL_SLOTS 22866876 22866876 | |
| TOPDOWN_ISSUED_SLOTS 15155480 15155480 | |
| TOPDOWN_RETIRED_SLOTS 12824797 12824797 | |
| TOPDOWN_FETCH_BUBBLES_SLOTS 1938289 1938289 | |
| TOPDOWN_RECOVERY_BUBBLES_SLOTS 1209135 1209135 | |
| TOPDOWN_MEM_LOAD_STALLS_CYCLES 642281 642281 | |
| TOPDOWN_MEM_STORE_STALLS_CYCLES 36 36 | |
| TOPDOWN_EXEC_STALLS_CYCLES 481218 481218 | |
| TOPDOWN_BACKEND_STALLS_CYCLES 642781 642781 | |
| TOPDOWN_FETCH_BUBBLES_GT_MIW_CYCLES 251132 251132 | |
| TOPDOWN_BR_RECOVER_AT_EXEC_RETIRED_CYCLES 13185 13185 | |
| TOPDOWN_MACHINE_CLEAR_CYCLES 549883 549883 | |
| TOPDOWN_FRONTEND_BOUND 847 847 | |
| TOPDOWN_BACKEND_BOUND 1997 1997 | |
| TOPDOWN_BAD_SPEC_BOUND 1548 1548 | |
| TOPDOWN_RETIRING_BOUND 5608 5608 | |
| TOPDOWN_FETCH_LATENCY_BOUND 658 658 | |
| TOPDOWN_FETCH_BANDWIDTH_BOUND 189 189 | |
| TOPDOWN_MEM_BOUND 1995 1995 | |
| TOPDOWN_CORE_BOUND 2 2 | |
| TOPDOWN_BR_RECOVER_AT_EXEC_BOUND 36 36 | |
| TOPDOWN_MACHINE_CLEARS_BOUND 1512 1512 | |
| H2P_SEEN_MAIN 1327 1327 | |