hpca2027-database-validated-traces-20260711 / validation /postgresql /simpoint-validation /2 /fetch.stat.0.out
| /* -*- Mode: c -*- */ | |
| #################################################################################################### | |
| Core 0 | |
| #################################################################################################### | |
| Cumulative: Cycles: 3811146 Instructions: 9968027 IPC: 2.61549 | |
| Periodic: Cycles: 3811146 Instructions: 9968027 IPC: 2.61549 | |
| MISS_WAIT_TIME 39040731823 39040731823 | |
| ICACHE_STAGE_MISS 18588 18588 | |
| ICACHE_CYCLE 3811146 3811146 | |
| TCACHE_CYCLE 0 0 | |
| ICACHE_SERVING_CYCLE_ON_PATH 1057073 1057073 | |
| ICACHE_SERVING_CYCLE_OFF_PATH 223138 223138 | |
| UCACHE_SERVING_CYCLE_ON_PATH 1548901 1548901 | |
| UCACHE_SERVING_CYCLE_OFF_PATH 560295 560295 | |
| ICACHE_CYCLE_ONPATH 2971071 77.957% 2971071 77.957% | |
| ICACHE_CYCLE_OFFPATH 840075 22.043% 840075 22.043% | |
| 3811146 100.000% 3811146 100.000% | |
| 0.22 0.38 0.22 0.38 | |
| FETCH_ON_PATH 3004927 78.846% 3004927 78.846% | |
| FETCH_OFF_PATH 806219 21.154% 806219 21.154% | |
| 3811146 100.000% 3811146 100.000% | |
| 0.21 0.38 0.21 0.38 | |
| FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% | |
| FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| INST_LOST_FETCH 12824928 48.319% 12824928 48.319% | |
| INST_LOST_OFF_PATH 3787894 14.271% 3787894 14.271% | |
| INST_LOST_FULL_WINDOW 500624 1.886% 500624 1.886% | |
| INST_LOST_ROB_STALL_OTHER 645218 2.431% 645218 2.431% | |
| INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% | |
| INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 148 0.001% 148 0.001% | |
| INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 2122130 7.995% 2122130 7.995% | |
| INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% | |
| INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_DONT 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_FT_UNAVAILABLE 1169000 4.404% 1169000 4.404% | |
| INST_LOST_BREAK_ICACHE_STAGE_RESTEER 19620 0.074% 19620 0.074% | |
| INST_LOST_BREAK_ICACHE_MISS_REQ_SUCCESS 84014 0.317% 84014 0.317% | |
| INST_LOST_BREAK_ICACHE_MISS_REQ_FAILURE 1565 0.006% 1565 0.006% | |
| INST_LOST_BREAK_ICACHE_WAIT_FOR_MISS 1261084 4.751% 1261084 4.751% | |
| INST_LOST_BREAK_ICACHE_STALLED 102128 0.385% 102128 0.385% | |
| INST_LOST_BREAK_ICACHE_TO_UOP_CACHE_SWITCH 309354 1.166% 309354 1.166% | |
| INST_LOST_BREAK_ICACHE_READ_LIMIT 505252 1.904% 505252 1.904% | |
| INST_LOST_BREAK_ICACHE_ISSUE_WIDTH 0 0.000% 0 0.000% | |
| INST_LOST_BREAK_UOP_CACHE_STALLED 767629 2.892% 767629 2.892% | |
| INST_LOST_BREAK_UOP_CACHE_TO_ICACHE_SWITCH 402857 1.518% 402857 1.518% | |
| INST_LOST_BREAK_UOP_CACHE_READ_LIMIT 2038879 7.682% 2038879 7.682% | |
| INST_LOST_BREAK_UOP_CACHE_ISSUE_WIDTH 0 0.000% 0 0.000% | |
| 26542324 100.000% 26542324 100.000% | |
| 5.91 7.51 5.91 7.51 | |
| INST_LOST_TOTAL 27099720 27099720 | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_NOT_PREFETCHED 132540 11.694% 132540 11.694% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH 0 0.000% 0 0.000% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP 0 0.000% 0 0.000% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_MSHR_HIT_PREF_OFFPATH 15138 1.336% 15138 1.336% | |
| INST_LOST_WAIT_FOR_ICACHE_MISS_MSHR_HIT_PREF_ONPATH 985740 86.971% 985740 86.971% | |
| 1133418 100.000% 1133418 100.000% | |
| 3.52 3.31 3.52 3.31 | |
| FETCH_0_OPS 418718 10.987% 418718 10.987% | |
| FETCH_1_OPS 101455 2.662% 101455 2.662% | |
| FETCH_2_OPS 157176 4.124% 157176 4.124% | |
| FETCH_3_OPS 242950 6.375% 242950 6.375% | |
| FETCH_4_OPS 195117 5.120% 195117 5.120% | |
| FETCH_5_OPS 255188 6.696% 255188 6.696% | |
| FETCH_6_OPS 1071228 28.108% 1071228 28.108% | |
| FETCH_7_OPS 144607 3.794% 144607 3.794% | |
| FETCH_8_OPS 1224707 32.135% 1224707 32.135% | |
| FETCH_9_OPS 0 0.000% 0 0.000% | |
| FETCH_10_OPS 0 0.000% 0 0.000% | |
| FETCH_11_OPS 0 0.000% 0 0.000% | |
| FETCH_12_OPS 0 0.000% 0 0.000% | |
| FETCH_13_OPS 0 0.000% 0 0.000% | |
| FETCH_14_OPS 0 0.000% 0 0.000% | |
| FETCH_15_OPS 0 0.000% 0 0.000% | |
| FETCH_16_OPS 0 0.000% 0 0.000% | |
| 3811146 100.000% 3811146 100.000% | |
| 5.36 1.97 5.36 1.97 | |
| ST_BREAK_DONT 0 0.000% 0 0.000% | |
| ST_BREAK_FT_UNAVAILABLE 196676 5.161% 196676 5.161% | |
| ST_BREAK_ICACHE_STAGE_RESTEER 5455 0.143% 5455 0.143% | |
| ST_BREAK_ICACHE_MISS_REQ_SUCCESS 18588 0.488% 18588 0.488% | |
| ST_BREAK_ICACHE_MISS_REQ_FAILURE 264 0.007% 264 0.007% | |
| ST_BREAK_ICACHE_WAIT_FOR_MISS 210226 5.516% 210226 5.516% | |
| ST_BREAK_ICACHE_STALLED 145056 3.806% 145056 3.806% | |
| ST_BREAK_ICACHE_TO_UOP_CACHE_SWITCH 95875 2.516% 95875 2.516% | |
| ST_BREAK_ICACHE_READ_LIMIT 196738 5.162% 196738 5.162% | |
| ST_BREAK_ICACHE_ISSUE_WIDTH 829208 21.757% 829208 21.757% | |
| ST_BREAK_UOP_CACHE_STALLED 476207 12.495% 476207 12.495% | |
| ST_BREAK_UOP_CACHE_TO_ICACHE_SWITCH 92510 2.427% 92510 2.427% | |
| ST_BREAK_UOP_CACHE_READ_LIMIT 565257 14.832% 565257 14.832% | |
| ST_BREAK_UOP_CACHE_ISSUE_WIDTH 979086 25.690% 979086 25.690% | |
| 3811146 100.000% 3811146 100.000% | |
| 9.76 5.87 9.76 5.87 | |
| ORACLE_ON_PATH_INST 12824928 77.199% 12824928 77.199% | |
| ORACLE_OFF_PATH_INST 3787894 22.801% 3787894 22.801% | |
| 16612822 100.000% 16612822 100.000% | |
| 0.23 0.38 0.23 0.38 | |
| ORACLE_ON_PATH_INST_MEM 4453950 26.810% 4453950 26.810% | |
| ORACLE_ON_PATH_INST_NOTMEM 8370978 50.389% 8370978 50.389% | |
| ORACLE_OFF_PATH_INST_MEM 1170464 7.046% 1170464 7.046% | |
| ORACLE_OFF_PATH_INST_NOTMEM 2617430 15.755% 2617430 15.755% | |
| 16612822 100.000% 16612822 100.000% | |
| 1.12 0.90 1.12 0.90 | |
| ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% | |
| ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 | |
| FETCH_ALL_INST 16612822 16612822 | |
| EXEC_ALL_INST 13729737 13729737 | |
| RET_ALL_INST 12824509 12824509 | |
| EXEC_ON_PATH_INST 12824571 93.407% 12824571 93.407% | |
| EXEC_OFF_PATH_INST 905166 6.593% 905166 6.593% | |
| 13729737 100.000% 13729737 100.000% | |
| 0.07 0.24 0.07 0.24 | |
| EXEC_ON_PATH_INST_MEM 4453817 32.439% 4453817 32.439% | |
| EXEC_ON_PATH_INST_NOTMEM 8370754 60.968% 8370754 60.968% | |
| EXEC_OFF_PATH_INST_MEM 294957 2.148% 294957 2.148% | |
| EXEC_OFF_PATH_INST_NOTMEM 610209 4.444% 610209 4.444% | |
| 13729737 100.000% 13729737 100.000% | |
| 0.79 0.55 0.79 0.55 | |
| EXEC_RA_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_INST 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% | |
| EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% | |
| EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% | |
| EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| ICACHE_THROTTLE_CYCLE 0 0 | |
| FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% | |
| FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% | |
| FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_TH_ADJUST__0 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__1 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__2 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__3 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__4 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__5 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__6 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__7 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__8 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__9 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST__MAX 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| FETCH_TH_ADJUST_UP 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% | |
| FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 | |
| LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% | |
| LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_RESTEER_RECOVER_AT_EXEC 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_RESTEER_RECOVER_AT_EXEC_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_EXEC_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_RECOVER_AT_DECODE_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| CYCLES_RESTEER_BTB_MISS_COULD_BE_SAVED_UC_FETCH 0 -nan% 0 -nan% | |
| 0 -nan% 0 -nan% | |
| -nan -nan -nan -nan | |
| CYCLES_UOC_IC_SWITCH 0 0 | |