/* -*- Mode: c -*- */ #################################################################################################### Core 0 #################################################################################################### Cumulative: Cycles: 3811146 Instructions: 9968027 IPC: 2.61549 Periodic: Cycles: 3811146 Instructions: 9968027 IPC: 2.61549 ICACHE_MISS 18590 2.537% 18590 2.537% ICACHE_HIT 714065 97.463% 714065 97.463% 732655 100.000% 732655 100.000% 0.97 0.96 0.97 0.96 ICACHE_MISS_ONPATH 16705 89.860% 16705 89.860% ICACHE_MISS_OFFPATH 1885 10.140% 1885 10.140% 18590 100.000% 18590 100.000% 0.10 0.29 0.10 0.29 ICACHE_MISS_NOT_PREFETCHED 124 0.670% 124 0.670% ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_IFETCH 0 0.000% 0 0.000% ICACHE_MISS_PREFETCHED_AND_EVICTED_BY_FDIP 0 0.000% 0 0.000% ICACHE_MISS_MSHR_HIT_PREFETCHED_OFFPATH 2422 13.077% 2422 13.077% ICACHE_MISS_MSHR_HIT_PREFETCHED_ONPATH 15975 86.253% 15975 86.253% 18521 100.000% 18521 100.000% 3.84 3.58 3.84 3.58 ICACHE_HIT_ONPATH 614895 86.112% 614895 86.112% ICACHE_HIT_OFFPATH 99170 13.888% 99170 13.888% 714065 100.000% 714065 100.000% 0.14 0.33 0.14 0.33 ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan ICACHE_HIT_BY_FDIP_ONPATH 0 -nan% 0 -nan% ICACHE_HIT_BY_FDIP_OFFPATH 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan ICACHE_MISS_MSHR_HIT_BY_FDIP_ONPATH 14003 76.116% 14003 76.116% ICACHE_MISS_MSHR_HIT_BY_FDIP_OFFPATH 4394 23.884% 4394 23.884% 18397 100.000% 18397 100.000% 0.24 0.39 0.24 0.39 ICACHE_HIT_ONPATH_BY_FDIP 0 0.000% 0 0.000% ICACHE_HIT_OFFPATH_BY_FDIP 0 0.000% 0 0.000% ICACHE_MISS_MSHR_HIT_ONPATH_BY_FDIP 16581 89.193% 16581 89.193% ICACHE_MISS_MSHR_HIT_OFFPATH_BY_FDIP 1816 9.769% 1816 9.769% ICACHE_MISS_TOO_EARLY_ONPATH 0 0.000% 0 0.000% ICACHE_MISS_TOO_EARLY_OFFPATH 0 0.000% 0 0.000% ICACHE_MISS_NOT_PREFETCHED_ONPATH 124 0.667% 124 0.667% ICACHE_MISS_NOT_PREFETCHED_OFFPATH 69 0.371% 69 0.371% 18590 100.000% 18590 100.000% 2.14 0.54 2.14 0.54 ICACHE_MISS_MEM_REQ_FAIL_ON_PATH 174 58.389% 174 58.389% ICACHE_MISS_MEM_REQ_SUCCESS_ON_PATH 124 41.611% 124 41.611% 298 100.000% 298 100.000% 0.42 0.46 0.42 0.46 ICACHE_UNIQUE_MISSED_LINES 16581 16581 ICACHE_UNIQUE_HIT_LINES 0 0 ICACHE_OVERTAKE_FDIP 0 0 FT_UOP_CACHE_HIT_ON_PATH 984826 60.926% 984826 60.926% FT_UOP_CACHE_MISS_ICACHE_HIT_ON_PATH 614895 38.040% 614895 38.040% FT_UOP_CACHE_MISS_ICACHE_MISS_ON_PATH 16705 1.033% 16705 1.033% 1616426 100.000% 1616426 100.000% 0.40 0.41 0.40 0.41 FT_UOP_CACHE_HIT_OFF_PATH 339964 77.086% 339964 77.086% FT_UOP_CACHE_MISS_ICACHE_HIT_OFF_PATH 99170 22.487% 99170 22.487% FT_UOP_CACHE_MISS_ICACHE_MISS_OFF_PATH 1885 0.427% 1885 0.427% 441019 100.000% 441019 100.000% 0.23 0.38 0.23 0.38 UOPS_SERVED_BY_ICACHE_ON_PATH 4951552 38.609% 4951552 38.609% UOPS_SERVED_BY_UOP_CACHE_ON_PATH 7873376 61.391% 7873376 61.391% 12824928 100.000% 12824928 100.000% 0.61 0.57 0.61 0.57 UOPS_SERVED_BY_ICACHE_OFF_PATH 1003506 26.492% 1003506 26.492% UOPS_SERVED_BY_UOP_CACHE_OFF_PATH 2784388 73.508% 2784388 73.508% 3787894 100.000% 3787894 100.000% 0.74 0.67 0.74 0.67 UOP_CACHE_FT_INSERTED_ONPATH_USED_ONPATH 176924 176924 UOP_CACHE_FT_INSERTED_OFFPATH_USED_ONPATH 40654 40654 UOP_CACHE_LINE_INSERTED_ONPATH_USED_ONPATH 281685 281685 UOP_CACHE_LINE_INSERTED_OFFPATH_USED_ONPATH 61372 61372 UOP_CACHE_PREFETCH 0 0 UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_ON_PATH 40127 6.359% 40127 6.359% UOP_CACHE_FT_INSERT_SUCCEEDED_ON_PATH 590913 93.641% 590913 93.641% 631040 100.000% 631040 100.000% 2.94 2.85 2.94 2.85 UOP_CACHE_FT_INSERT_FAILED_INST_TOO_BIG_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_INSERT_FAILED_FT_TOO_BIG_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_SHORT_REUSE_CONFLICTED_OFF_PATH 5203 6.476% 5203 6.476% UOP_CACHE_FT_INSERT_SUCCEEDED_OFF_PATH 75143 93.524% 75143 93.524% 80346 100.000% 80346 100.000% 2.94 2.85 2.94 2.85 UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_ON_PATH 60524 6.221% 60524 6.221% UOP_CACHE_LINE_INSERT_SUCCEEDED_ON_PATH 912445 93.779% 912445 93.779% 972969 100.000% 972969 100.000% 2.94 2.86 2.94 2.86 UOP_CACHE_LINE_INSERT_FAILED_INST_TOO_BIG_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_LINE_INSERT_FAILED_FT_TOO_BIG_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_LINE_SHORT_REUSE_CONFLICTED_OFF_PATH 6969 5.151% 6969 5.151% UOP_CACHE_LINE_INSERT_SUCCEEDED_OFF_PATH 128315 94.849% 128315 94.849% 135284 100.000% 135284 100.000% 2.95 2.88 2.95 2.88 UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_RESTEERED 0 -nan% 0 -nan% UOP_CACHE_ICACHE_SWITCH_BR_NOT_TAKEN_CORRECT_PRED 0 -nan% 0 -nan% UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_RESTEERED 0 -nan% 0 -nan% UOP_CACHE_ICACHE_SWITCH_BR_TAKEN_CORRECT_PRED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan UOP_CACHE_FT_LINES_1_ON_PATH 381147 60.400% 381147 60.400% UOP_CACHE_FT_LINES_2_ON_PATH 169764 26.902% 169764 26.902% UOP_CACHE_FT_LINES_3_ON_PATH 68668 10.882% 68668 10.882% UOP_CACHE_FT_LINES_4_ON_PATH 11015 1.746% 11015 1.746% UOP_CACHE_FT_LINES_5_ON_PATH 446 0.071% 446 0.071% UOP_CACHE_FT_LINES_6_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_LINES_7_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_LINES_8_ON_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_LINES_9_AND_MORE_ON_PATH 0 0.000% 0 0.000% 631040 100.000% 631040 100.000% 0.54 0.63 0.54 0.63 UOP_CACHE_FT_LINES_1_OFF_PATH 44260 55.087% 44260 55.087% UOP_CACHE_FT_LINES_2_OFF_PATH 19264 23.976% 19264 23.976% UOP_CACHE_FT_LINES_3_OFF_PATH 14831 18.459% 14831 18.459% UOP_CACHE_FT_LINES_4_OFF_PATH 1952 2.429% 1952 2.429% UOP_CACHE_FT_LINES_5_OFF_PATH 39 0.049% 39 0.049% UOP_CACHE_FT_LINES_6_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_LINES_7_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_LINES_8_OFF_PATH 0 0.000% 0 0.000% UOP_CACHE_FT_LINES_9_AND_MORE_OFF_PATH 0 0.000% 0 0.000% 80346 100.000% 80346 100.000% 0.68 0.69 0.68 0.69 UOP_CACHE_PREFETCH_PW_LENGTH_1 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_2 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_3 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_4 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_5 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_6 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_7 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_8 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_9 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_10 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_11 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_12 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_13 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_14 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_15 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_16 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_17 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_18 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_19 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_20 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_21 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_22 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_23 0 -nan% 0 -nan% UOP_CACHE_PREFETCH_PW_LENGTH_24 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DCACHE_MISS 172029 3.863% 172029 3.863% DCACHE_ST_BUFFER_HIT 7652 0.172% 7652 0.172% DCACHE_HIT 4274135 95.966% 4274135 95.966% 4453816 100.000% 4453816 100.000% 1.92 1.88 1.92 1.88 DCACHE_MISS_ONPATH 172029 97.222% 172029 97.222% DCACHE_MISS_OFFPATH 4915 2.778% 4915 2.778% 176944 100.000% 176944 100.000% 0.03 0.16 0.03 0.16 DCACHE_ST_BUFFER_HIT_ONPATH 7652 97.577% 7652 97.577% DCACHE_ST_BUFFER_HIT_OFFPATH 190 2.423% 190 2.423% 7842 100.000% 7842 100.000% 0.02 0.15 0.02 0.15 DCACHE_HIT_ONPATH 4274135 94.037% 4274135 94.037% DCACHE_HIT_OFFPATH 271044 5.963% 271044 5.963% 4545179 100.000% 4545179 100.000% 0.06 0.23 0.06 0.23 DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 717 0.017% 717 0.017% DCACHE_HIT_ONPATH_SAT_BY_ONPATH 4273418 99.983% 4273418 99.983% 4274135 100.000% 4274135 100.000% 1.00 1.00 1.00 1.00 DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 1220 0.450% 1220 0.450% DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 269824 99.550% 269824 99.550% 271044 100.000% 271044 100.000% 1.00 0.99 1.00 0.99 DCACHE_MISS_LD 123745 71.933% 123745 71.933% DCACHE_MISS_ST 48284 28.067% 48284 28.067% 172029 100.000% 172029 100.000% 0.28 0.41 0.28 0.41 DCACHE_MISS_LD_ONPATH 123745 97.220% 123745 97.220% DCACHE_MISS_LD_OFFPATH 3538 2.780% 3538 2.780% 127283 100.000% 127283 100.000% 0.03 0.16 0.03 0.16 DCACHE_MISS_ST_ONPATH 48284 97.227% 48284 97.227% DCACHE_MISS_ST_OFFPATH 1377 2.773% 1377 2.773% 49661 100.000% 49661 100.000% 0.03 0.16 0.03 0.16 DCACHE_MISS_WAITMEM 2355 2355 MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan SHADOW_ROW_BUFFER_HITS 0 0 SHADOW_ROW_HIT_STALL_TIME 0 0 CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL6_BUS_BUSY_CYCLES 0 -nan% 0 -nan% CHANNEL7_BUS_BUSY_CYCLES 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CHANNEL_IDLE_DESPITE_READY_CMD 0 0 MEM_NUM_TOTAL_BUS_CYCLES 0 0 MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CORE_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan RAMULATOR_QUEUE_ENQUEUED 0 0 RAMULATOR_QUEUE_FULL 0 0 BUS_DEMAND_ACCESS 10345 10345 BUS_PREF_ACCESS 11205 11205 BUS_ACCESS 0 0 L1_DEMAND_ACCESS 31057 31057 L1_PREF_ACCESS 29299 29299 L1_ACCESS 47776 47776 MLC_DEMAND_ACCESS 77820 77820 MLC_PREF_ACCESS 287138 287138 MLC_ACCESS 364958 364958 L1_HIT 7214 57.763% 7214 57.763% L1_MISS 5275 42.237% 5275 42.237% 12489 100.000% 12489 100.000% 0.42 0.47 0.42 0.47 L1_HIT_ALL 8613 28.555% 8613 28.555% L1_MISS_ALL 21550 71.445% 21550 71.445% 30163 100.000% 30163 100.000% 0.71 0.65 0.71 0.65 L1_DEMAND_MISS 5055 23.457% 5055 23.457% L1_PREF_REQ_MISS 11205 51.995% 11205 51.995% L1_WB_MISS 5290 24.548% 5290 24.548% 21550 100.000% 21550 100.000% 1.01 0.70 1.01 0.70 L1_DEMAND_HIT 7213 83.746% 7213 83.746% L1_PREF_REQ_HIT 768 8.917% 768 8.917% L1_WB_HIT 632 7.338% 632 7.338% 8613 100.000% 8613 100.000% 0.24 0.53 0.24 0.53 L1_MISS_ONPATH 5228 99.109% 5228 99.109% L1_MISS_OFFPATH 47 0.891% 47 0.891% 5275 100.000% 5275 100.000% 0.01 0.09 0.01 0.09 L1_MISS_ALL_ONPATH 16265 75.476% 16265 75.476% L1_MISS_ALL_OFFPATH 5285 24.524% 5285 24.524% 21550 100.000% 21550 100.000% 0.25 0.39 0.25 0.39 L1_HIT_ONPATH 7213 99.986% 7213 99.986% L1_HIT_OFFPATH 1 0.014% 1 0.014% 7214 100.000% 7214 100.000% 0.00 0.01 0.00 0.01 L1_HIT_ALL_ONPATH 8588 99.710% 8588 99.710% L1_HIT_ALL_OFFPATH 25 0.290% 25 0.290% 8613 100.000% 8613 100.000% 0.00 0.05 0.00 0.05 L1_HIT_ONPATH_SAT_BY_OFFPATH 3 0.035% 3 0.035% L1_HIT_ONPATH_SAT_BY_ONPATH 8585 99.965% 8585 99.965% 8588 100.000% 8588 100.000% 1.00 1.00 1.00 1.00 L1_HIT_OFFPATH_SAT_BY_OFFPATH 24 96.000% 24 96.000% L1_HIT_OFFPATH_SAT_BY_ONPATH 1 4.000% 1 4.000% 25 100.000% 25 100.000% 0.04 0.20 0.04 0.20 L1_HIT_ONPATH_IFETCH_SAT_BY_OFFPATH 2 66.667% 2 66.667% L1_HIT_ONPATH_IFETCH_SAT_BY_ONPATH 1 33.333% 1 33.333% 3 100.000% 3 100.000% 0.33 0.53 0.33 0.53 L1_HIT_ONPATH_DATA_SAT_BY_OFFPATH 0 0.000% 0 0.000% L1_HIT_ONPATH_DATA_SAT_BY_ONPATH 7210 100.000% 7210 100.000% 7210 100.000% 7210 100.000% 1.00 1.00 1.00 1.00 L1_FILL_OFFPATH_IFETCH 28 28 L1_FILL_OFFPATH_DATA 10 10 L1_FILL_OFFPATH 5276 5276 L1_USE_OFFPATH_IFETCH 2 0.0714 2 0.0714 L1_USE_OFFPATH_DATA 10 1.0000 10 1.0000 L1_USE_OFFPATH 13 0.0025 13 0.0025 JUST_L1_USE_OFFPATH 5 0.0009 5 0.0009 L1_FILL_ONPATH_IFETCH 245 245 L1_FILL_ONPATH_DATA 5814 5814 L1_FILL_ONPATH 6111 6111 L1_USE_ONPATH_IFETCH 1 0.0041 1 0.0041 L1_USE_ONPATH_DATA 7210 1.2401 7210 1.2401 L1_USE_ONPATH 8585 1.4048 8585 1.4048 L1_CYCLE 3811146 3811146 L1_LINES 54538501009 14310.2628 54538501009 14310.2628 MLC_HIT 63767 83.881% 63767 83.881% MLC_MISS 12254 16.119% 12254 16.119% 76021 100.000% 76021 100.000% 0.16 0.34 0.16 0.34 MLC_HIT_ALL 346530 95.171% 346530 95.171% MLC_MISS_ALL 17584 4.829% 17584 4.829% 364114 100.000% 364114 100.000% 0.05 0.21 0.05 0.21 MLC_DEMAND_MISS 12254 69.688% 12254 69.688% MLC_PREF_REQ_MISS 0 0.000% 0 0.000% MLC_WB_MISS 5330 30.312% 5330 30.312% 17584 100.000% 17584 100.000% 0.61 0.84 0.61 0.84 MLC_DEMAND_HIT 63767 18.402% 63767 18.402% MLC_PREF_REQ_HIT 0 0.000% 0 0.000% MLC_WB_HIT 282763 81.598% 282763 81.598% 346530 100.000% 346530 100.000% 1.63 1.51 1.63 1.51 MLC_MISS_ONPATH 12188 99.461% 12188 99.461% MLC_MISS_OFFPATH 66 0.539% 66 0.539% 12254 100.000% 12254 100.000% 0.01 0.07 0.01 0.07 MLC_MISS_ALL_ONPATH 12244 69.631% 12244 69.631% MLC_MISS_ALL_OFFPATH 5340 30.369% 5340 30.369% 17584 100.000% 17584 100.000% 0.30 0.42 0.30 0.42 MLC_HIT_ONPATH 61094 95.808% 61094 95.808% MLC_HIT_OFFPATH 2673 4.192% 2673 4.192% 63767 100.000% 63767 100.000% 0.04 0.20 0.04 0.20 MLC_HIT_ALL_ONPATH 179697 51.856% 179697 51.856% MLC_HIT_ALL_OFFPATH 166833 48.144% 166833 48.144% 346530 100.000% 346530 100.000% 0.48 0.49 0.48 0.49 L1_QUEUE_OCCUPANCY 1128641 0.2961 1128641 0.2961 MLC_QUEUE_OCCUPANCY 1098478 0.2882 1098478 0.2882 DCACHE_FILL_PORT_UNAVAILABLE_ONPATH 1382 1382 DCACHE_FILL_PORT_UNAVAILABLE_OFFPATH 143 143 DCACHE_READ_PORT_UNAVAILABLE_ONPATH 403383 403383 DCACHE_READ_PORT_UNAVAILABLE_OFFPATH 28258 28258 DCACHE_FILL_OFFPATH 1747 1747 DCACHE_USE_OFFPATH 717 0.4104 717 0.4104 DCACHE_FILL_ONPATH 57781 57781 DCACHE_USE_ONPATH 4273418 73.9589 4273418 73.9589 ICACHE_FILL_OFFPATH 170382 170382 ICACHE_USE_OFFPATH 0 0.0000 0 0.0000 ICACHE_FILL_ONPATH 116293 116293 ICACHE_USE_ONPATH 0 0.0000 0 0.0000 REQBUF_CREATE_ONPATH 202756 202756 REQBUF_ONPATH_MATCH_OFFPATH 139 0.0007 139 0.0007 REQBUF_CREATE_ONPATH_DATA 56697 56697 REQBUF_ONPATH_MATCH_OFFPATH_DATA 41 0.0007 41 0.0007 REQBUF_CREATE_ONPATH_IFETCH 124 124 REQBUF_ONPATH_MATCH_OFFPATH_IFETCH 98 0.7903 98 0.7903 REQBUF_CREATE_OFFPATH 173938 173938 ONPATH_KICKED_OUT_OFFPATH 0 0 ONPATH_KICKED_OUT_PREFETCH 0 0 DIST_ICACHE_FILL_OFFPATH_USED 0 0.000% 0 0.000% DIST_ICACHE_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000% DIST_ICACHE_FILL_ONPATH_PARTIAL 98 0.084% 98 0.084% DIST_ICACHE_FILL_ONPATH 116195 99.916% 116195 99.916% 116293 100.000% 116293 100.000% 3.00 3.00 3.00 3.00 DIST_DCACHE_FILL_OFFPATH_USED 717 1.226% 717 1.226% DIST_DCACHE_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000% DIST_DCACHE_FILL_ONPATH_PARTIAL 41 0.070% 41 0.070% DIST_DCACHE_FILL_ONPATH 57740 98.704% 57740 98.704% 58498 100.000% 58498 100.000% 2.96 2.94 2.96 2.94 DIST_L1_FILL_OFFPATH_USED 13 0.212% 13 0.212% DIST_L1_FILL_OFFPATH_NOTUSED 0 0.000% 0 0.000% DIST_L1_FILL_ONPATH_PARTIAL 49 0.800% 49 0.800% DIST_L1_FILL_ONPATH 6062 98.988% 6062 98.988% 6124 100.000% 6124 100.000% 2.99 2.97 2.99 2.97 DIST_JUST_L1_FILL_OFFPATH_USED 0 -nan% 0 -nan% DIST_JUST_L1_FILL_OFFPATH_NOTUSED 0 -nan% 0 -nan% DIST_JUST_L1_FILL_ONPATH_PARTIAL 0 -nan% 0 -nan% DIST_JUST_L1_FILL_ONPATH 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_REQBUF_OFFPATH_USED 859 0.467% 859 0.467% DIST_REQBUF_OFFPATH_NOTUSED 0 0.000% 0 0.000% DIST_REQBUF_ONPATH 183195 99.533% 183195 99.533% 184054 100.000% 184054 100.000% 1.99 1.99 1.99 1.99 DIST2_REQBUF_OFFPATH_USED_PARTIAL 139 0.076% 139 0.076% DIST2_REQBUF_OFFPATH_USED_FULL 720 0.391% 720 0.391% DIST2_REQBUF_OFFPATH_NOTUSED 0 0.000% 0 0.000% DIST2_REQBUF_ONPATH 183195 99.533% 183195 99.533% 184054 100.000% 184054 100.000% 2.99 2.99 2.99 2.99 DIST_ICACHE_FILL 286675 286675 DIST_DCACHE_FILL 59528 59528 DIST_L1_FILL 11387 11387 DIST_USED_OFFPATH_ICACHE 0 -nan% 0 -nan% DIST_NOTUSED_OFFPATH_ICACHE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_USED_OFFPATH_DCACHE 0 -nan% 0 -nan% DIST_NOTUSED_OFFPATH_DCACHE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_USED_OFFPATH_L1 0 -nan% 0 -nan% DIST_NOTUSED_OFFPATH_L1 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_USED_OFFPATH_JUST_L1 0 -nan% 0 -nan% DIST_NOTUSED_OFFPATH_JUST_L1 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_OFFPATH_ICACHE_FULL 0 -nan% 0 -nan% DIST_OFFPATH_ICACHE_PARTIAL 0 -nan% 0 -nan% DIST_OFFPATH_ICACHE_NOTUSED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_OFFPATH_DCACHE_FULL 0 -nan% 0 -nan% DIST_OFFPATH_DCACHE_PARTIAL 0 -nan% 0 -nan% DIST_OFFPATH_DCACHE_NOTUSED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_OFFPATH_L1_FULL 0 -nan% 0 -nan% DIST_OFFPATH_L1_PARTIAL 0 -nan% 0 -nan% DIST_OFFPATH_L1_NOTUSED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIST_OFFPATH_JUST_L1_FULL 0 -nan% 0 -nan% DIST_OFFPATH_JUST_L1_PARTIAL 0 -nan% 0 -nan% DIST_OFFPATH_JUST_L1_NOTUSED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MLC_MISS_ONPATH_IFETCH 234 1.911% 234 1.911% MLC_MISS_ONPATH_DFETCH 5229 42.707% 5229 42.707% MLC_MISS_ONPATH_DSTORE 6725 54.925% 6725 54.925% MLC_MISS_ONPATH_IPRF 0 0.000% 0 0.000% MLC_MISS_ONPATH_DPRF 0 0.000% 0 0.000% MLC_MISS_ONPATH_WB 55 0.449% 55 0.449% MLC_MISS_ONPATH_WB_NODIRTY 1 0.008% 1 0.008% 12244 100.000% 12244 100.000% 1.55 0.54 1.55 0.54 MLC_MISS_OFFPATH_IFETCH 29 0.543% 29 0.543% MLC_MISS_OFFPATH_DFETCH 32 0.599% 32 0.599% MLC_MISS_OFFPATH_DSTORE 5 0.094% 5 0.094% MLC_MISS_OFFPATH_IPRF 0 0.000% 0 0.000% MLC_MISS_OFFPATH_DPRF 0 0.000% 0 0.000% MLC_MISS_OFFPATH_WB 5274 98.764% 5274 98.764% MLC_MISS_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000% 5340 100.000% 5340 100.000% 4.95 0.32 4.95 0.32 MLC_HIT_ONPATH_IFETCH 16337 9.091% 16337 9.091% MLC_HIT_ONPATH_DFETCH 40219 22.382% 40219 22.382% MLC_HIT_ONPATH_DSTORE 4538 2.525% 4538 2.525% MLC_HIT_ONPATH_IPRF 0 0.000% 0 0.000% MLC_HIT_ONPATH_DPRF 0 0.000% 0 0.000% MLC_HIT_ONPATH_WB 99650 55.454% 99650 55.454% MLC_HIT_ONPATH_WB_NODIRTY 18953 10.547% 18953 10.547% 179697 100.000% 179697 100.000% 3.68 2.15 3.68 2.15 MLC_HIT_OFFPATH_IFETCH 936 0.561% 936 0.561% MLC_HIT_OFFPATH_DFETCH 1349 0.809% 1349 0.809% MLC_HIT_OFFPATH_DSTORE 388 0.233% 388 0.233% MLC_HIT_OFFPATH_IPRF 0 0.000% 0 0.000% MLC_HIT_OFFPATH_DPRF 0 0.000% 0 0.000% MLC_HIT_OFFPATH_WB 164160 98.398% 164160 98.398% MLC_HIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000% 166833 100.000% 166833 100.000% 4.93 0.39 4.93 0.39 L1_MISS_ONPATH_IFETCH 241 1.482% 241 1.482% L1_MISS_ONPATH_DFETCH 3200 19.674% 3200 19.674% L1_MISS_ONPATH_DSTORE 1787 10.987% 1787 10.987% L1_MISS_ONPATH_IPRF 0 0.000% 0 0.000% L1_MISS_ONPATH_DPRF 0 0.000% 0 0.000% L1_MISS_ONPATH_WB 52 0.320% 52 0.320% L1_MISS_ONPATH_WB_NODIRTY 10985 67.538% 10985 67.538% 16265 100.000% 16265 100.000% 4.48 4.27 4.48 4.27 L1_MISS_OFFPATH_IFETCH 32 0.605% 32 0.605% L1_MISS_OFFPATH_DFETCH 13 0.246% 13 0.246% L1_MISS_OFFPATH_DSTORE 2 0.038% 2 0.038% L1_MISS_OFFPATH_IPRF 0 0.000% 0 0.000% L1_MISS_OFFPATH_DPRF 0 0.000% 0 0.000% L1_MISS_OFFPATH_WB 5238 99.111% 5238 99.111% L1_MISS_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000% 5285 100.000% 5285 100.000% 4.96 0.21 4.96 0.21 L1_HIT_ONPATH_IFETCH 3 0.035% 3 0.035% L1_HIT_ONPATH_DFETCH 2146 24.988% 2146 24.988% L1_HIT_ONPATH_DSTORE 5064 58.966% 5064 58.966% L1_HIT_ONPATH_IPRF 0 0.000% 0 0.000% L1_HIT_ONPATH_DPRF 0 0.000% 0 0.000% L1_HIT_ONPATH_WB 1 0.012% 1 0.012% L1_HIT_ONPATH_WB_NODIRTY 1374 15.999% 1374 15.999% 8588 100.000% 8588 100.000% 2.39 1.89 2.39 1.89 L1_HIT_OFFPATH_IFETCH 1 4.000% 1 4.000% L1_HIT_OFFPATH_DFETCH 0 0.000% 0 0.000% L1_HIT_OFFPATH_DSTORE 0 0.000% 0 0.000% L1_HIT_OFFPATH_IPRF 0 0.000% 0 0.000% L1_HIT_OFFPATH_DPRF 0 0.000% 0 0.000% L1_HIT_OFFPATH_WB 24 96.000% 24 96.000% L1_HIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000% 25 100.000% 25 100.000% 4.80 0.20 4.80 0.20 DRAM_CYCLES 0 0 DRAM_UNBLOCK_CYCLES 0 -nan 0 -nan DRAM_UNBLOCK_PERIODS 0 0 MEM_REQ_BUFFER_FULL 17207 17207 MEM_REQ_BUFFER_FULL_DENIED_DEMAND 2619 2619 CORE_MEM_BLOCKED 2228 2228 MEM_REQ_BUFFER_FULL_DENIED_IFETCH 264 8.998% 264 8.998% MEM_REQ_BUFFER_FULL_DENIED_DFETCH 926 31.561% 926 31.561% MEM_REQ_BUFFER_FULL_DENIED_DSTORE 1429 48.705% 1429 48.705% MEM_REQ_BUFFER_FULL_DENIED_IPRF 0 0.000% 0 0.000% MEM_REQ_BUFFER_FULL_DENIED_DPRF 0 0.000% 0 0.000% MEM_REQ_BUFFER_FULL_DENIED_WB 315 10.736% 315 10.736% MEM_REQ_BUFFER_FULL_DENIED_WB_NODIRTY 0 0.000% 0 0.000% 2934 100.000% 2934 100.000% 1.83 1.15 1.83 1.15 MEM_QUEUE_FULL 14271 14271 MEM_REQ_BUFFER_MISS 376696 54.261% 376696 54.261% MEM_REQ_BUFFER_HIT 317535 45.739% 317535 45.739% 694231 100.000% 694231 100.000% 0.46 0.48 0.46 0.48 MEM_REQ_FDIP_BUFFER_HIT 198194 198194 MEM_REQ_FDIP_CYCLE_DELTA 2112996 2112996 MEM_REQ_DEMAND_ICACHE_BUFFER_HIT 131 131 MEM_REQ_DEMAND_ICACHE_CYCLE_DELTA 6925 6925 MEM_REQ_IFETCH 191 0.051% 191 0.051% MEM_REQ_DFETCH 46829 12.432% 46829 12.432% MEM_REQ_DSTORE 11656 3.094% 11656 3.094% MEM_REQ_IPRF 0 0.000% 0 0.000% MEM_REQ_DPRF 0 0.000% 0 0.000% MEM_REQ_WB 286484 76.052% 286484 76.052% MEM_REQ_WB_NODIRTY 31534 8.371% 31534 8.371% 376694 100.000% 376694 100.000% 4.49 1.95 4.49 1.95 LD_NO_FORWARD 1966461 63.729% 1966461 63.729% FORWARDED_LD 1119179 36.271% 1119179 36.271% 3085640 100.000% 3085640 100.000% 0.36 0.44 0.36 0.44 WRONGPATH_L1Q_REMOVALS 0 -nan% 0 -nan% WRONGPATH_BUSQ_REMOVALS 0 -nan% 0 -nan% WRONGPATH_MEMQ_REMOVALS 0 -nan% 0 -nan% WRONGPATH_L1FILLQ_REMOVALS 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan WRONGPATH_L1Q_DEMOTIONS 0 -nan% 0 -nan% WRONGPATH_BUSQ_DEMOTIONS 0 -nan% 0 -nan% WRONGPATH_MEMQ_DEMOTIONS 0 -nan% 0 -nan% WRONGPATH_L1FILLQ_DEMOTIONS 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan PROMOTION_QMLC 17345 98.663% 17345 98.663% PROMOTION_QL1 235 1.337% 235 1.337% 17580 100.000% 17580 100.000% 0.01 0.11 0.01 0.11 PROMOTION_QBUSOUT 0 0 PROMOTION_QMEM 0 0 PROMOTION_QL1FILL 35 35 PROMOTION_QMLC_FILL 18 18 NOPROMOTION_QMEM 0 0 NOPROMOTION_QL1FILL 0 -nan% 0 -nan% NOPROMOTION_QMLC_FILL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan PROMOTION_FROM_FDIP_OFF_TO_ON 0 0 ICACHE_FILL_CORRECT_REQ 18104 6.315% 18104 6.315% ICACHE_FILL_INCORRECT_REQ 268571 93.685% 268571 93.685% 286675 100.000% 286675 100.000% 0.94 0.91 0.94 0.91 ICACHE_FILL_CORRECT_REQ_BY_FDIP 17945 6.260% 17945 6.260% ICACHE_FILL_INCORRECT_REQ_BY_FDIP 268539 93.674% 268539 93.674% ICACHE_FILL_CORRECT_REQ_BY_ICACHE_DEMAND 159 0.055% 159 0.055% ICACHE_FILL_INCORRECT_REQ_BY_ICACHE_DEMAND 32 0.011% 32 0.011% 286675 100.000% 286675 100.000% 0.94 0.07 0.94 0.07 ICACHE_FILL_CORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 13128 13128 ICACHE_FILL_CORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 4 4 ICACHE_FILL_INCORRECT_REQ_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 3437 3437 ICACHE_FILL_INCORRECT_REQ_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0 ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA 38930533668 38930533668 ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND 26028 26028 ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_FDIP 554569 554569 ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 130997 130997 ICACHE_FILL_CORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 246 246 ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA 605816113827 605816113827 ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ICACHE_DEMAND 7972 7972 ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_FDIP 6334935 6334935 ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_ON_FDIP_HIT_BY_DEMAND_LOAD 0 0 ICACHE_FILL_INCORRECT_REQ_CYCLE_DELTA_BY_OFF_FDIP_HIT_BY_DEMAND_LOAD 0 0 MEM_REQ_INIT 376694 376694 MEM_REQ_COMPLETE 376694 1.0000 376694 1.0000 MEM_REQ_KILLED 0 0.0000 0 0.0000 MEM_REQ_COMPLETE_MLC 346531 0.9199 346531 0.9199 MEM_REQ_COMPLETE_L1 1374 0.0036 1374 0.0036 MEM_REQ_COMPLETE_MEM 28789 0.0764 28789 0.0764 MEM_REQ_INIT_ONPATH 202756 0.5383 202756 0.5383 MEM_REQ_INIT_OFFPATH 173938 0.4617 173938 0.4617 MEM_REQ_COMPLETE_ONPATH 204565 0.5431 204565 0.5431 MEM_REQ_COMPLETE_OFFPATH 172129 0.4569 172129 0.4569 MEM_REQ_INIT_IFETCH 191 0.055% 191 0.055% MEM_REQ_INIT_DFETCH 46829 13.567% 46829 13.567% MEM_REQ_INIT_DSTORE 11656 3.377% 11656 3.377% MEM_REQ_INIT_IPRF 0 0.000% 0 0.000% MEM_REQ_INIT_DPRF 0 0.000% 0 0.000% MEM_REQ_INIT_WB 286484 83.000% 286484 83.000% MEM_REQ_INIT_WB_NODIRTY 0 0.000% 0 0.000% 345160 100.000% 345160 100.000% 4.35 1.44 4.35 1.44 MEM_REQ_COMPLETE_IFETCH 29548 7.822% 29548 7.822% MEM_REQ_COMPLETE_DFETCH 66978 17.731% 66978 17.731% MEM_REQ_COMPLETE_DSTORE 12111 3.206% 12111 3.206% MEM_REQ_COMPLETE_IPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_DPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_WB 269100 71.240% 269100 71.240% MEM_REQ_COMPLETE_WB_NODIRTY 0 0.000% 0 0.000% 377737 100.000% 377737 100.000% 3.80 1.59 3.80 1.59 MEM_REQ_KILLED_IFETCH 30491 100.000% 30491 100.000% MEM_REQ_KILLED_DFETCH 0 0.000% 0 0.000% MEM_REQ_KILLED_DSTORE 0 0.000% 0 0.000% MEM_REQ_KILLED_IPRF 0 0.000% 0 0.000% MEM_REQ_KILLED_DPRF 0 0.000% 0 0.000% MEM_REQ_KILLED_WB 0 0.000% 0 0.000% MEM_REQ_KILLED_WB_NODIRTY 0 0.000% 0 0.000% 30491 100.000% 30491 100.000% 0.00 0.00 0.00 0.00 MEM_REQ_INIT_OFFPATH_IFETCH 67 0.039% 67 0.039% MEM_REQ_INIT_OFFPATH_DFETCH 1392 0.800% 1392 0.800% MEM_REQ_INIT_OFFPATH_DSTORE 396 0.228% 396 0.228% MEM_REQ_INIT_OFFPATH_IPRF 0 0.000% 0 0.000% MEM_REQ_INIT_OFFPATH_DPRF 0 0.000% 0 0.000% MEM_REQ_INIT_OFFPATH_WB 172083 98.934% 172083 98.934% MEM_REQ_INIT_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000% 173938 100.000% 173938 100.000% 4.96 0.38 4.96 0.38 MEM_REQ_INIT_ONPATH_IFETCH 124 0.072% 124 0.072% MEM_REQ_INIT_ONPATH_DFETCH 45437 26.537% 45437 26.537% MEM_REQ_INIT_ONPATH_DSTORE 11260 6.576% 11260 6.576% MEM_REQ_INIT_ONPATH_IPRF 0 0.000% 0 0.000% MEM_REQ_INIT_ONPATH_DPRF 0 0.000% 0 0.000% MEM_REQ_INIT_ONPATH_WB 114401 66.814% 114401 66.814% MEM_REQ_INIT_ONPATH_WB_NODIRTY 0 0.000% 0 0.000% 171222 100.000% 171222 100.000% 3.74 1.80 3.74 1.80 MEM_REQ_MATCH_IFETCH 20581 3.841% 20581 3.841% MEM_REQ_MATCH_DFETCH 99536 18.576% 99536 18.576% MEM_REQ_MATCH_DSTORE 33395 6.232% 33395 6.232% MEM_REQ_MATCH_IPRF 0 0.000% 0 0.000% MEM_REQ_MATCH_DPRF 0 0.000% 0 0.000% MEM_REQ_MATCH_WB 382088 71.309% 382088 71.309% MEM_REQ_MATCH_WB_NODIRTY 221 0.041% 221 0.041% 535821 100.000% 535821 100.000% 3.88 1.63 3.88 1.63 MEM_REQ_COMPLETE_OFFPATH_IFETCH 985 0.572% 985 0.572% MEM_REQ_COMPLETE_OFFPATH_DFETCH 1357 0.788% 1357 0.788% MEM_REQ_COMPLETE_OFFPATH_DSTORE 390 0.227% 390 0.227% MEM_REQ_COMPLETE_OFFPATH_IPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_OFFPATH_DPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_OFFPATH_WB 169397 98.413% 169397 98.413% MEM_REQ_COMPLETE_OFFPATH_WB_NODIRTY 0 0.000% 0 0.000% 172129 100.000% 172129 100.000% 4.93 0.38 4.93 0.38 MEM_REQ_COMPLETE_ONPATH_IFETCH 16590 9.530% 16590 9.530% MEM_REQ_COMPLETE_ONPATH_DFETCH 46060 26.460% 46060 26.460% MEM_REQ_COMPLETE_ONPATH_DSTORE 11721 6.733% 11721 6.733% MEM_REQ_COMPLETE_ONPATH_IPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_ONPATH_DPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_ONPATH_WB 99703 57.276% 99703 57.276% MEM_REQ_COMPLETE_ONPATH_WB_NODIRTY 0 0.000% 0 0.000% 174074 100.000% 174074 100.000% 3.26 1.79 3.26 1.79 MEM_REQ_COMPLETE_MEM_IFETCH 30793 62.693% 30793 62.693% MEM_REQ_COMPLETE_MEM_DFETCH 5849 11.908% 5849 11.908% MEM_REQ_COMPLETE_MEM_DSTORE 7185 14.628% 7185 14.628% MEM_REQ_COMPLETE_MEM_IPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_MEM_DPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_MEM_WB 5290 10.770% 5290 10.770% MEM_REQ_COMPLETE_MEM_WB_NODIRTY 0 0.000% 0 0.000% 49117 100.000% 49117 100.000% 0.95 1.39 0.95 1.39 MEM_REQ_COMPLETE_MEM_BW_PREFETCHABLE 16672 16672 MEM_REQ_COMPLETE_MEM_MATCHED_BW_PREF 825 825 MEM_REQ_COMPLETE_L1_IFETCH 0 -nan% 0 -nan% MEM_REQ_COMPLETE_L1_DFETCH 0 -nan% 0 -nan% MEM_REQ_COMPLETE_L1_DSTORE 0 -nan% 0 -nan% MEM_REQ_COMPLETE_L1_IPRF 0 -nan% 0 -nan% MEM_REQ_COMPLETE_L1_DPRF 0 -nan% 0 -nan% MEM_REQ_COMPLETE_L1_WB 0 -nan% 0 -nan% MEM_REQ_COMPLETE_L1_WB_NODIRTY 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_REQ_COMPLETE_MLC_IFETCH 18647 5.669% 18647 5.669% MEM_REQ_COMPLETE_MLC_DFETCH 41568 12.637% 41568 12.637% MEM_REQ_COMPLETE_MLC_DSTORE 4926 1.497% 4926 1.497% MEM_REQ_COMPLETE_MLC_IPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_MLC_DPRF 0 0.000% 0 0.000% MEM_REQ_COMPLETE_MLC_WB 263810 80.197% 263810 80.197% MEM_REQ_COMPLETE_MLC_WB_NODIRTY 0 0.000% 0 0.000% 328951 100.000% 328951 100.000% 4.17 1.38 4.17 1.38 CORE_MLP_CLUSTERS 18954 18954 CORE_MLP 3929097 3929097 CORE_MLP_IFETCH 0 0 CORE_MLP_DFETCH 0 0 CORE_MLP_DSTORE 0 0 CORE_MLP_IPRF 0 0 CORE_MLP_DPRF 0 0 CORE_MLP_WB 0 0 CORE_MLP_WB_NODIRTY 0 0 CORE_MLP_0 3129281 82.109% 3129281 82.109% CORE_MLP_1 216477 5.680% 216477 5.680% CORE_MLP_2 148022 3.884% 148022 3.884% CORE_MLP_3 53860 1.413% 53860 1.413% CORE_MLP_4 50910 1.336% 50910 1.336% CORE_MLP_5 24410 0.640% 24410 0.640% CORE_MLP_6 19281 0.506% 19281 0.506% CORE_MLP_7 17683 0.464% 17683 0.464% CORE_MLP_8 13196 0.346% 13196 0.346% CORE_MLP_9 9469 0.248% 9469 0.248% CORE_MLP_10 10072 0.264% 10072 0.264% CORE_MLP_11 5858 0.154% 5858 0.154% CORE_MLP_12 5456 0.143% 5456 0.143% CORE_MLP_13 7299 0.192% 7299 0.192% CORE_MLP_14 4956 0.130% 4956 0.130% CORE_MLP_15 4453 0.117% 4453 0.117% CORE_MLP_16 5231 0.137% 5231 0.137% CORE_MLP_17 4320 0.113% 4320 0.113% CORE_MLP_18 4194 0.110% 4194 0.110% CORE_MLP_19 5612 0.147% 5612 0.147% CORE_MLP_20 5649 0.148% 5649 0.148% CORE_MLP_21 4053 0.106% 4053 0.106% CORE_MLP_22 7803 0.205% 7803 0.205% CORE_MLP_23 12922 0.339% 12922 0.339% CORE_MLP_24 17203 0.451% 17203 0.451% CORE_MLP_25 10902 0.286% 10902 0.286% CORE_MLP_26 2920 0.077% 2920 0.077% CORE_MLP_27 1903 0.050% 1903 0.050% CORE_MLP_28 6387 0.168% 6387 0.168% CORE_MLP_29 1346 0.035% 1346 0.035% CORE_MLP_30 18 0.000% 18 0.000% CORE_MLP_31 0 0.000% 0 0.000% CORE_MLP_32 0 0.000% 0 0.000% 3811146 100.000% 3811146 100.000% 1.03 3.66 1.03 3.66 MEM_QUEUE_OCC_0 0 -nan% 0 -nan% MEM_QUEUE_OCC_4 0 -nan% 0 -nan% MEM_QUEUE_OCC_8 0 -nan% 0 -nan% MEM_QUEUE_OCC_12 0 -nan% 0 -nan% MEM_QUEUE_OCC_16 0 -nan% 0 -nan% MEM_QUEUE_OCC_20 0 -nan% 0 -nan% MEM_QUEUE_OCC_24 0 -nan% 0 -nan% MEM_QUEUE_OCC_28 0 -nan% 0 -nan% MEM_QUEUE_OCC_32 0 -nan% 0 -nan% MEM_QUEUE_OCC_36 0 -nan% 0 -nan% MEM_QUEUE_OCC_40 0 -nan% 0 -nan% MEM_QUEUE_OCC_44 0 -nan% 0 -nan% MEM_QUEUE_OCC_48 0 -nan% 0 -nan% MEM_QUEUE_OCC_52 0 -nan% 0 -nan% MEM_QUEUE_OCC_56 0 -nan% 0 -nan% MEM_QUEUE_OCC_60 0 -nan% 0 -nan% MEM_QUEUE_OCC_64 0 -nan% 0 -nan% MEM_QUEUE_OCC_68 0 -nan% 0 -nan% MEM_QUEUE_OCC_72 0 -nan% 0 -nan% MEM_QUEUE_OCC_76 0 -nan% 0 -nan% MEM_QUEUE_OCC_80 0 -nan% 0 -nan% MEM_QUEUE_OCC_84 0 -nan% 0 -nan% MEM_QUEUE_OCC_88 0 -nan% 0 -nan% MEM_QUEUE_OCC_92 0 -nan% 0 -nan% MEM_QUEUE_OCC_96 0 -nan% 0 -nan% MEM_QUEUE_OCC_100 0 -nan% 0 -nan% MEM_QUEUE_OCC_104 0 -nan% 0 -nan% MEM_QUEUE_OCC_108 0 -nan% 0 -nan% MEM_QUEUE_OCC_112 0 -nan% 0 -nan% MEM_QUEUE_OCC_116 0 -nan% 0 -nan% MEM_QUEUE_OCC_120 0 -nan% 0 -nan% MEM_QUEUE_OCC_124 0 -nan% 0 -nan% MEM_QUEUE_OCC_128 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan OPEN_PAGE_HIT 0 -nan% 0 -nan% CLOSED_PAGE_MISS 0 -nan% 0 -nan% WRONG_PAGE_MISS 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L0_LD_BANK_BLOCK 0 -nan% 0 -nan% L0_LD_BANK_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L0_ST_BANK_BLOCK 0 -nan% 0 -nan% L0_ST_BANK_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L0_LD_CACHE_BLOCK 0 -nan% 0 -nan% L0_LD_CACHE_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MLC_LD_BANK_BLOCK 844 0.244% 844 0.244% MLC_LD_BANK_AVAIL 345160 99.756% 345160 99.756% 346004 100.000% 346004 100.000% 1.00 1.00 1.00 1.00 MLC_ST_BANK_BLOCK 0 0.000% 0 0.000% MLC_ST_BANK_AVAIL 18954 100.000% 18954 100.000% 18954 100.000% 18954 100.000% 1.00 1.00 1.00 1.00 MLC_LD_CACHE_BLOCK 0 -nan% 0 -nan% MLC_LD_CACHE_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MLC_ST_CACHE_BLOCK 0 -nan% 0 -nan% MLC_ST_CACHE_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L1_LD_BANK_BLOCK 30 0.101% 30 0.101% L1_LD_BANK_AVAIL 29556 99.899% 29556 99.899% 29586 100.000% 29586 100.000% 1.00 1.00 1.00 1.00 L1_ST_BANK_BLOCK 0 0.000% 0 0.000% L1_ST_BANK_AVAIL 607 100.000% 607 100.000% 607 100.000% 607 100.000% 1.00 1.00 1.00 1.00 L1_LD_CACHE_BLOCK 0 -nan% 0 -nan% L1_LD_CACHE_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L1_ST_CACHE_BLOCK 0 -nan% 0 -nan% L1_ST_CACHE_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_LD_BANK_BLOCK 0 -nan% 0 -nan% MEM_LD_BANK_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_ST_BANK_BLOCK 0 -nan% 0 -nan% MEM_ST_BANK_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_PF_BANK_BLOCK 0 -nan% 0 -nan% MEM_PF_BANK_AVAIL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L0_FILL 0 0 L1_FILL 21550 100.000% 21550 100.000% L1_WB_FILL 0 0.000% 0 0.000% 21550 100.000% 21550 100.000% 0.00 0.00 0.00 0.00 L1_DEMAND_FILL 10345 48.005% 10345 48.005% L1_PREF_FILL 11205 51.995% 11205 51.995% 21550 100.000% 21550 100.000% 0.52 0.51 0.52 0.51 MLC_FILL 18626 99.995% 18626 99.995% MLC_WB_FILL 1 0.005% 1 0.005% 18627 100.000% 18627 100.000% 0.00 0.01 0.00 0.01 MLC_DEMAND_FILL 17583 94.400% 17583 94.400% MLC_PREF_FILL 1043 5.600% 1043 5.600% 18626 100.000% 18626 100.000% 0.06 0.22 0.06 0.22 NORESET_L1_FILL 21550 21550 NORESET_L1_FILL_NONPREF 5055 5055 NORESET_L1_FILL_PREF 16495 16495 NORESET_L1_EVICT 0 0 NORESET_L1_EVICT_NONPREF 0 0 NORESET_L1_EVICT_PREF_USED 0 0 NORESET_L1_EVICT_PREF_UNUSED 0 0 NORESET_L1_PREF_USED 7114 7114 ORACLE_OFFPATH_DC_FILL 0 0 ORACLE_OFFPATH_IC_FILL 0 0 ORACLE_OFFPATH_L1_FILL 0 0 UPDATE_EVENT_QUEUE_PROCESS 0 0 INSERT_EVENT_QUEUE_PROCESS 0 0 ICFILL_AFTER_REDIRECT 0 0 EVENT_QUEUE_MATCH_ADD_REQ 0 0 DC_PREF_CACHE_INSERT_REQ 0 0 DC_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% DC_PREF_REQ_PREF_CACHE_HIT 0 -nan% 0 -nan% DC_PREF_REQ_L1_MISS 0 -nan% 0 -nan% DC_PREF_REQ_CORR 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DC_PREF_CACHE_INSERT 0 0 DC_PREF_CACHE_HIT_PER 0 0.000% 0 0.000% DC_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000% DC_PREF_CACHE_HIT 0 0 DC_PREF_CACHE_HIT_OFFPATH 0 0 DC_PREF_HIT_L1_MISS 0 0 IC_PREF_CACHE_HIT_PER 0 0.000% 0 0.000% IC_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000% IC_PREF_CACHE_HIT 0 0 IC_PREF_CACHE_HIT_OFFPATH 0 0 L1_PREF_CACHE_HIT_PER 0 0.000% 0 0.000% L1_PREF_CACHE_HIT_PER_OFFPATH 0 0.000% 0 0.000% L1_PREF_CACHE_HIT 0 0 L1_PREF_CACHE_HIT_OFFPATH 0 0 DC_PREF_CACHE_FILL 0 0 DC_PREF_MOVE_DC 0 -nan% 0 -nan% DC_PREF_MOVE_L1 0 -nan% 0 -nan% IC_PREF_CACHE_FILL 0 0 IC_PREF_MOVE_IC 0 -nan% 0 -nan% IC_PREF_MOVE_L1 0 -nan% 0 -nan% L1_PREF_CACHE_FILL 0 0 L1_PREF_MOVE_L1 0 -nan% 0 -nan% OFF_PATH_CONFIRMED 1893846 1893846 OFF_PATH_NO_FILL_L1 0 0 WB_L1_MISS_FILL_L1 0 0 WB_MLC_MISS_FILL_MLC 1 1 ICACHE_EVICT_REQ_WB_L1 0 0 DCACHE_EVICT_REQ_WB_L1 0 0 DCACHE_EVICT_REQ_WB_L1_NOREAD 0 0 L1_FILL_SKIPPED 0 0 MLC_FILL_SKIPPED 0 0 DCACHE_FILL 59528 59528 DCACHE_WB_REQ 18954 0.3184 18954 0.3184 DCACHE_WB_REQ_DIRTY 18954 100.000% 18954 100.000% DCACHE_WB_REQ_NODIRTY 0 0.000% 0 0.000% 18954 100.000% 18954 100.000% 0.00 0.00 0.00 0.00 ICACHE_FILL 286675 286675 ICACHE_WB_REQ 0 0.0000 0 0.0000 L1_FILL_DIRTY 0 0.0000 0 0.0000 MLC_FILL_DIRTY 607 0.0326 607 0.0326 ICACHE_UNUSEFUL_CL_CYC 1740373757 1740373757 ICACHE_UNUSEFUL_CL 269608 269608 ICACHE_EVICT_MISS_ONPATH_BY_FDIP 240683 89.319% 240683 89.319% ICACHE_EVICT_MISS_OFFPATH_BY_FDIP 28783 10.681% 28783 10.681% 269466 100.000% 269466 100.000% 0.11 0.29 0.11 0.29 ICACHE_EVICT_MISS_BY_FDIP_ONPATH 152044 56.424% 152044 56.424% ICACHE_EVICT_MISS_BY_FDIP_OFFPATH 117422 43.576% 117422 43.576% 269466 100.000% 269466 100.000% 0.44 0.47 0.44 0.47 ICACHE_EVICT_HIT_ONPATH_BY_FDIP 14911 90.069% 14911 90.069% ICACHE_EVICT_HIT_OFFPATH_BY_FDIP 1644 9.931% 1644 9.931% 16555 100.000% 16555 100.000% 0.10 0.29 0.10 0.29 ICACHE_EVICT_HIT_BY_FDIP_ONPATH 16551 99.976% 16551 99.976% ICACHE_EVICT_HIT_BY_FDIP_OFFPATH 4 0.024% 4 0.024% 16555 100.000% 16555 100.000% 0.00 0.02 0.00 0.02 MEM_REQ_DENIED_NULL 0 -nan% 0 -nan% MEM_REQ_DENIED_INST_OUTOF_CS 0 -nan% 0 -nan% MEM_REQ_DENIED_DATA_IN_CS 0 -nan% 0 -nan% MEM_REQ_DENIED_DATA_OUTOF_RANGE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_REQ_DENIED 0 -nan% 0 -nan% MEM_REQ_NOT_DENIED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DEMAND_HIT_WB_STALL 0 0 EXCLUSION_VIOLATED_OSR 0 -nan% 0 -nan% EXCLUSION_VIOLATED_NOTOSR 0 -nan% 0 -nan% EXCLUSION_NOT_VIOLATED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DIRTY_WRITE_TO_ICACHE 0 0 STREAM_DC_HIT_NOSEND 0 -nan% 0 -nan% STREAM_WBQDC_HIT_NOSEND 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan STREAM_DCACHE_PREF_HIT 0 0 PREF_DC_HIT_ON_INSERT 0 -nan% 0 -nan% PREF_L1_HIT_ON_INSERT 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L1_NEWREQ_MATCHED_MLC_REQ 216 216 MLC_NEWREQ_MATCHED_L2_PREF 1043 1043 MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT 1 0.0010 1 0.0010 NEWREQ_WB_MATCH_IGNORED 0 0 DEMAND_MATCH_WB_NEW_DONE_FUNC 0 -nan% 0 -nan% DEMAND_MATCH_WB_NEW_DONE_FUNC_NULL 0 -nan% 0 -nan% DEMAND_MATCH_WB_DONE_FUNC_NOT_SAME 0 -nan% 0 -nan% DEMAND_MATCH_WB_DONE_FUNC_SAME 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DEMAND_MATCH_WB 0 -nan% 0 -nan% DEMAND_MATCH_WB_NODIRTY 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DEMAND_MATCH_WBALL_IFETCH 0 -nan% 0 -nan% DEMAND_MATCH_WBALL_DFETCH 0 -nan% 0 -nan% DEMAND_MATCH_WBALL_DSTORE 0 -nan% 0 -nan% DEMAND_MATCH_WBALL_IPRF 0 -nan% 0 -nan% DEMAND_MATCH_WBALL_DPRF 0 -nan% 0 -nan% DEMAND_MATCH_WBALL_WB 0 -nan% 0 -nan% DEMAND_MATCH_WBALL_WB_NODIRTY 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DEMAND_MATCH_WB_IFETCH 0 -nan% 0 -nan% DEMAND_MATCH_WB_DFETCH 0 -nan% 0 -nan% DEMAND_MATCH_WB_DSTORE 0 -nan% 0 -nan% DEMAND_MATCH_WB_IPRF 0 -nan% 0 -nan% DEMAND_MATCH_WB_DPRF 0 -nan% 0 -nan% DEMAND_MATCH_WB_WB 0 -nan% 0 -nan% DEMAND_MATCH_WB_WB_NODIRTY 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DEMAND_MATCH_WB_ND_IFETCH 0 -nan% 0 -nan% DEMAND_MATCH_WB_ND_DFETCH 0 -nan% 0 -nan% DEMAND_MATCH_WB_ND_DSTORE 0 -nan% 0 -nan% DEMAND_MATCH_WB_ND_IPRF 0 -nan% 0 -nan% DEMAND_MATCH_WB_ND_DPRF 0 -nan% 0 -nan% DEMAND_MATCH_WB_ND_WB 0 -nan% 0 -nan% DEMAND_MATCH_WB_ND_WB_NODIRTY 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan WB_MATCH_DEMAND 0 0.000% 0 0.000% WB_MATCH_PREF 0 0.000% 0 0.000% WB_MATCH_WB 0 0.000% 0 0.000% WB_MATCH_WB_FILTERED 475651 100.000% 475651 100.000% 475651 100.000% 475651 100.000% 3.00 3.00 3.00 3.00 WB_COMING_BACK_FROM_MEM 0 0 WB_COMING_BACK_FROM_L1 0 0 WB_COMING_BACK_FROM_MLC 0 0 MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH 41 0.035% 41 0.035% MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_ETC 118418 99.965% 118418 99.965% 118459 100.000% 118459 100.000% 1.00 1.00 1.00 1.00 TOTAL_ONPATH_ICACHE_FILLS 0 0 TOTAL_ONPATH_DCACHE_FILLS 0 0 TOTAL_ONPATH_L1_FILLS 0 0 PER1K_ONPATH_ICACHE_FILLS 0 0.0000 0 0.0000 PER1K_ONPATH_DCACHE_FILLS 0 0.0000 0 0.0000 PER1K_ONPATH_L1_FILLS 0 0.0000 0 0.0000 PER1K_L1_DEMAND_MISS_ONPATH 5228 0.5228 5228 0.5228 PER1K_L1_DEMAND_MISS_OFFPATH 47 0.0047 47 0.0047 L2_IDEAL_FILL_L1 0 -nan% 0 -nan% L2_IDEAL_MISS_L2 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan L2_IDEAL_FILL_ICACHE 0 -nan% 0 -nan% L2_IDEAL_MISS_ICACHE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan HPS_MISS_DELTA__0 0 -nan% 0 -nan% HPS_MISS_DELTA__1 0 -nan% 0 -nan% HPS_MISS_DELTA__2 0 -nan% 0 -nan% HPS_MISS_DELTA__3 0 -nan% 0 -nan% HPS_MISS_DELTA__4 0 -nan% 0 -nan% HPS_MISS_DELTA__5 0 -nan% 0 -nan% HPS_MISS_DELTA__6 0 -nan% 0 -nan% HPS_MISS_DELTA__7 0 -nan% 0 -nan% HPS_MISS_DELTA__8 0 -nan% 0 -nan% HPS_MISS_DELTA__9 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan HPS_HIT_DELTA__0 0 -nan% 0 -nan% HPS_HIT_DELTA__1 0 -nan% 0 -nan% HPS_HIT_DELTA__2 0 -nan% 0 -nan% HPS_HIT_DELTA__3 0 -nan% 0 -nan% HPS_HIT_DELTA__4 0 -nan% 0 -nan% HPS_HIT_DELTA__5 0 -nan% 0 -nan% HPS_HIT_DELTA__6 0 -nan% 0 -nan% HPS_HIT_DELTA__7 0 -nan% 0 -nan% HPS_HIT_DELTA__8 0 -nan% 0 -nan% HPS_HIT_DELTA__9 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DC_MISS_DELTA__0 0 -nan% 0 -nan% DC_MISS_DELTA__1 0 -nan% 0 -nan% DC_MISS_DELTA__2 0 -nan% 0 -nan% DC_MISS_DELTA__3 0 -nan% 0 -nan% DC_MISS_DELTA__4 0 -nan% 0 -nan% DC_MISS_DELTA__5 0 -nan% 0 -nan% DC_MISS_DELTA__6 0 -nan% 0 -nan% DC_MISS_DELTA__7 0 -nan% 0 -nan% DC_MISS_DELTA__8 0 -nan% 0 -nan% DC_MISS_DELTA__9 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan ONE_MORE_SUCESS 0 -nan% 0 -nan% ONE_MORE_DISCARDED_L0CACHE 0 -nan% 0 -nan% ONE_MORE_DISCARDED_MEM_REQ_FULL 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan PREF_L1_TOTAL_SENT 11205 11205 PREF_L1_TOTAL_USED 7114 63.490% 7114 63.490% PREF_L1_TOTAL_PARTIAL_USED 1042 9.299% 1042 9.299% PREF_L1_TOTAL_NOT_USED 3049 27.211% 3049 27.211% PREF_L1_TOTAL_DROPPED 0 0.000% 0 0.000% 11205 100.000% 11205 100.000% 0.64 0.72 0.64 0.72 PREF_MLC_TOTAL_SENT 0 0 PREF_MLC_TOTAL_USED 2077 66.571% 2077 66.571% PREF_MLC_TOTAL_PARTIAL_USED 1043 33.429% 1043 33.429% PREF_MLC_TOTAL_NOT_USED 0 0.000% 0 0.000% PREF_MLC_TOTAL_DROPPED 0 0.000% 0 0.000% 3120 100.000% 3120 100.000% 0.33 0.38 0.33 0.38 CORE_MLC_PREF_REQ_MISS 0 0.000% 0 0.000% CORE_MLC_DEMAND_MISS 12254 69.688% 12254 69.688% CORE_MLC_WB_MISS 5330 30.312% 5330 30.312% 17584 100.000% 17584 100.000% 1.30 0.85 1.30 0.85 CORE_MLC_PREF_REQ_HIT 0 0.000% 0 0.000% CORE_MLC_DEMAND_HIT 63767 18.402% 63767 18.402% CORE_MLC_WB_HIT 282763 81.598% 282763 81.598% 346530 100.000% 346530 100.000% 1.82 1.69 1.82 1.69 CORE_MLC_HIT 63767 83.881% 63767 83.881% CORE_MLC_MISS 12254 16.119% 12254 16.119% 76021 100.000% 76021 100.000% 0.16 0.34 0.16 0.34 CORE_MLC_FILL 18626 99.995% 18626 99.995% CORE_MLC_WB_FILL 1 0.005% 1 0.005% 18627 100.000% 18627 100.000% 0.00 0.01 0.00 0.01 CORE_MLC_DEMAND_FILL 17583 94.400% 17583 94.400% CORE_MLC_PREF_FILL 1043 5.600% 1043 5.600% 18626 100.000% 18626 100.000% 0.06 0.22 0.06 0.22 CORE_MLC_PREF_FILL_USED 2077 66.571% 2077 66.571% CORE_MLC_PREF_FILL_PARTIAL_USED 1043 33.429% 1043 33.429% CORE_MLC_PREF_FILL_NOT_USED 0 0.000% 0 0.000% 3120 100.000% 3120 100.000% 0.33 0.38 0.33 0.38 CORE_L1_PREF_REQ_MISS 11205 51.995% 11205 51.995% CORE_L1_DEMAND_MISS 5055 23.457% 5055 23.457% CORE_L1_WB_MISS 5290 24.548% 5290 24.548% 21550 100.000% 21550 100.000% 0.73 0.74 0.73 0.74 CORE_L1_PREF_REQ_HIT 768 8.917% 768 8.917% CORE_L1_DEMAND_HIT 7213 83.746% 7213 83.746% CORE_L1_WB_HIT 632 7.338% 632 7.338% 8613 100.000% 8613 100.000% 0.98 0.38 0.98 0.38 CORE_L1_HIT 7214 57.763% 7214 57.763% CORE_L1_MISS 5275 42.237% 5275 42.237% 12489 100.000% 12489 100.000% 0.42 0.47 0.42 0.47 CORE_L1_FILL 21550 100.000% 21550 100.000% CORE_L1_WB_FILL 0 0.000% 0 0.000% 21550 100.000% 21550 100.000% 0.00 0.00 0.00 0.00 CORE_L1_DEMAND_FILL 10345 48.005% 10345 48.005% CORE_L1_PREF_FILL 11205 51.995% 11205 51.995% 21550 100.000% 21550 100.000% 0.52 0.51 0.52 0.51 CORE_L1_PREF_FILL_USED 7114 63.490% 7114 63.490% CORE_L1_PREF_FILL_PARTIAL_USED 1042 9.299% 1042 9.299% CORE_L1_PREF_FILL_NOT_USED 3049 27.211% 3049 27.211% 11205 100.000% 11205 100.000% 0.64 0.79 0.64 0.79 CORE_L1_DEMAND_USED_POS0 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS1 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS2 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS3 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS4 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS5 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS6 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS7 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS8 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS9 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS10 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS11 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS12 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS13 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS14 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS15 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS16 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS17 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS18 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS19 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS20 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS21 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS22 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS23 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS24 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS25 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS26 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS27 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS28 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS29 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS30 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS31 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS32 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS33 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS34 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS35 0 -nan% 0 -nan% CORE_L1_DEMAND_USED_POS36 0 -nan% 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L1_SHADOW_DEMAND_HIT_POS92 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS93 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS94 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS95 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS96 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS97 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS98 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS99 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS100 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS101 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS102 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS103 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS104 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS105 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS106 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS107 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS108 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS109 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS110 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS111 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS112 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS113 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS114 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS115 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS116 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS117 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS118 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS119 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS120 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS121 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS122 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS123 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS124 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS125 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS126 0 -nan% 0 -nan% L1_SHADOW_DEMAND_HIT_POS127 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_PREF_MLC_SENT 0 0 CORE_PREF_MLC_USED 2077 66.571% 2077 66.571% CORE_PREF_MLC_PARTIAL_USED 1043 33.429% 1043 33.429% CORE_PREF_MLC_NOT_USED 0 0.000% 0 0.000% CORE_PREF_MLC_DROPPED 0 0.000% 0 0.000% 3120 100.000% 3120 100.000% 0.33 0.38 0.33 0.38 CORE_PREF_L1_SENT 11205 11205 CORE_PREF_L1_USED 7114 63.490% 7114 63.490% CORE_PREF_L1_PARTIAL_USED 1042 9.299% 1042 9.299% CORE_PREF_L1_NOT_USED 3049 27.211% 3049 27.211% CORE_PREF_L1_DROPPED 0 0.000% 0 0.000% 11205 100.000% 11205 100.000% 0.64 0.72 0.64 0.72 TOTAL_MEM_LATENCY 7239676 335.9478 7239676 335.9478 TOTAL_MEM_LATENCY_DEMAND 3864073 373.5208 3864073 373.5208 TOTAL_MEM_LATENCY_PREF 3375603 301.2586 3375603 301.2586 CORE_MEM_LATENCY 7239676 335.9478 7239676 335.9478 CORE_MEM_LATENCY_DEMAND 3864073 373.5208 3864073 373.5208 CORE_MEM_LATENCY_PREF 3375603 301.2586 3375603 301.2586 CORE_MEM_LATENCY_IFETCH 55110 1.395% 55110 1.395% CORE_MEM_LATENCY_DFETCH 437856 11.083% 437856 11.083% CORE_MEM_LATENCY_DSTORE 384444 9.731% 384444 9.731% CORE_MEM_LATENCY_IPRF 0 0.000% 0 0.000% CORE_MEM_LATENCY_UOCPRF 0 0.000% 0 0.000% CORE_MEM_LATENCY_FDIPPRF 1770611 44.818% 1770611 44.818% CORE_MEM_LATENCY_DPRF 0 0.000% 0 0.000% CORE_MEM_LATENCY_WB 1302626 32.972% 1302626 32.972% CORE_MEM_LATENCY_WB_NODIRTY 0 0.000% 0 0.000% 3950647 100.000% 3950647 100.000% 4.85 1.99 4.85 1.99 CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan% CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan% CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan% CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan% CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan% CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan% CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan TOTAL_L1_MISS_LATENCY 3950647 183.3247 3950647 183.3247 TOTAL_L1_MISS_LATENCY_DEMAND 2478092 239.5449 2478092 239.5449 TOTAL_L1_MISS_LATENCY_PREF 1472555 131.4195 1472555 131.4195 CORE_L1_MISS_LATENCY 3950647 183.3247 3950647 183.3247 CORE_L1_MISS_LATENCY_DEMAND 2478092 239.5449 2478092 239.5449 CORE_L1_MISS_LATENCY_PREF 1472555 131.4195 1472555 131.4195 CORE_EVICTED_L1_DEMAND 0 -nan% 0 -nan% CORE_EVICTED_L1_PREF_USED 0 -nan% 0 -nan% CORE_EVICTED_L1_PREF_NOT_USED 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_EVICTED_MLC_DEMAND 2484 53.639% 2484 53.639% CORE_EVICTED_MLC_PREF_USED 701 15.137% 701 15.137% CORE_EVICTED_MLC_PREF_NOT_USED 1446 31.224% 1446 31.224% 4631 100.000% 4631 100.000% 0.78 0.81 0.78 0.81 CORE_MEM_LATENCY_AVE_DEMAND 191168 inf 191168 inf CORE_MEM_LATENCY_AVE_PREF_USED 184173 inf 184173 inf CORE_MEM_LATENCY_AVE_PREF_NOT_USED 537233 inf 537233 inf DRAM_LATENCY 0 0 TOTAL_DRAM_LATENCY 0 0 DRAM_CLOSED_PAGE_POLICY_CMD 0 0 DRAM_ACTIVATE_STALLING 0 0 DRAM_PRECHARGE_STALLING 0 0 DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 L1_STAY_DEMAND 0 -nan 0 -nan L1_STAY_PREF_USED 0 -nan 0 -nan L1_STAY_PREF_NOT_USED 0 -nan 0 -nan TOTAL_DATA_MISS_LATENCY 1438608 1438608 TOTAL_DATA_MISS_COUNT 11673 11673 CORE_PREF_L1_NOT_USED_LATENCY200 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY400 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY600 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY800 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY1000 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY1200 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY1400 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY1600 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_PREF_L1_NOT_USED_DISTANCE_1 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_DISTANCE_2 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_DISTANCE_4 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_DISTANCE_8 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_DISTANCE_16 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_DISTANCE_32 0 -nan% 0 -nan% CORE_PREF_L1_NOT_USED_DISTANCE_MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_PREF_L1_USED_LATENCY200 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY400 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY600 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY800 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY1000 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY1200 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY1400 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY1600 0 -nan% 0 -nan% CORE_PREF_L1_USED_LATENCY1600MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_PREF_L1_USED_DISTANCE_1 0 -nan% 0 -nan% CORE_PREF_L1_USED_DISTANCE_2 0 -nan% 0 -nan% CORE_PREF_L1_USED_DISTANCE_4 0 -nan% 0 -nan% CORE_PREF_L1_USED_DISTANCE_8 0 -nan% 0 -nan% CORE_PREF_L1_USED_DISTANCE_16 0 -nan% 0 -nan% CORE_PREF_L1_USED_DISTANCE_32 0 -nan% 0 -nan% CORE_PREF_L1_USED_DISTANCE_MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_PREF_L1_DEMAND_LATENCY300 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY400 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY500 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY600 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY700 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY800 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY900 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY1000 0 -nan% 0 -nan% CORE_PREF_L1_DEMAND_LATENCY1000MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_PREF_MLC_NOT_USED_LATENCY200 214 14.799% 214 14.799% CORE_PREF_MLC_NOT_USED_LATENCY400 711 49.170% 711 49.170% CORE_PREF_MLC_NOT_USED_LATENCY600 429 29.668% 429 29.668% CORE_PREF_MLC_NOT_USED_LATENCY800 51 3.527% 51 3.527% CORE_PREF_MLC_NOT_USED_LATENCY1000 2 0.138% 2 0.138% CORE_PREF_MLC_NOT_USED_LATENCY1200 0 0.000% 0 0.000% CORE_PREF_MLC_NOT_USED_LATENCY1400 9 0.622% 9 0.622% CORE_PREF_MLC_NOT_USED_LATENCY1600 8 0.553% 8 0.553% CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 22 1.521% 22 1.521% 1446 100.000% 1446 100.000% 1.39 1.13 1.39 1.13 CORE_PREF_MLC_USED_LATENCY200 267 38.088% 267 38.088% CORE_PREF_MLC_USED_LATENCY400 290 41.369% 290 41.369% CORE_PREF_MLC_USED_LATENCY600 126 17.974% 126 17.974% CORE_PREF_MLC_USED_LATENCY800 10 1.427% 10 1.427% CORE_PREF_MLC_USED_LATENCY1000 1 0.143% 1 0.143% CORE_PREF_MLC_USED_LATENCY1200 0 0.000% 0 0.000% CORE_PREF_MLC_USED_LATENCY1400 2 0.285% 2 0.285% CORE_PREF_MLC_USED_LATENCY1600 3 0.428% 3 0.428% CORE_PREF_MLC_USED_LATENCY1600MORE 2 0.285% 2 0.285% 701 100.000% 701 100.000% 0.89 0.83 0.89 0.83 CORE_PREF_MLC_DEMAND_LATENCY300 2424 97.585% 2424 97.585% CORE_PREF_MLC_DEMAND_LATENCY400 20 0.805% 20 0.805% CORE_PREF_MLC_DEMAND_LATENCY500 9 0.362% 9 0.362% CORE_PREF_MLC_DEMAND_LATENCY600 7 0.282% 7 0.282% CORE_PREF_MLC_DEMAND_LATENCY700 6 0.242% 6 0.242% CORE_PREF_MLC_DEMAND_LATENCY800 0 0.000% 0 0.000% CORE_PREF_MLC_DEMAND_LATENCY900 3 0.121% 3 0.121% CORE_PREF_MLC_DEMAND_LATENCY1000 1 0.040% 1 0.040% CORE_PREF_MLC_DEMAND_LATENCY1000MORE 14 0.564% 14 0.564% 2484 100.000% 2484 100.000% 0.09 0.70 0.09 0.70 TOTAL_BATCH_FORMED 0 0 TOTAL_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan CORE_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan CORE_BATCH_MEM_REQ_MARKED_DEMAND 0 -nan 0 -nan CORE_BATCH_MEM_REQ_MARKED_PREF 0 -nan 0 -nan DRAM_ROW_BATCHES 0 0 REJECTED_QUEUE_MLC 0 0 REJECTED_QUEUE_L1 0 0 REJECTED_QUEUE_BUS_OUT 0 0 LEADING_LOAD_LATENCY 0 0.0000 0 0.0000 LEADING_LOADS 0 0.0000 0 0.0000 MEM_REQ_CRITICAL_PATH_LENGTH 0 0.0000 0 0.0000 TOTAL_MEM_REQ_LATENCY 0 0 TOTAL_CRITICAL_MEM_REQ_LATENCY 0 -nan 0 -nan TOTAL_CRITICAL_BANK_LATENCY 0 -nan 0 -nan TOTAL_MEMORY_SLACK 0 0.0000 0 0.0000 TOTAL_CHIP_UTILIZATION 0 0.0000 0 0.0000 CHIP_BUSY_UNDER_CRITICAL_REQS 0 0.0000 0 0.0000 PERF_PRED_NUM_STAT_RESETS 0 0 PERF_PRED_RESET_STATS_CYCLE 0 0 PERF_PRED_CYCLE 3811146 3811146 ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000 NUM_WINDOWS_WITH_DCACHE_MISS 14942 14942 LONGEST_DCACHE_MISS_CHAIN 50200 50200 NUM_DCACHE_MISSES_IN_WINDOW_1 2674 17.896% 2674 17.896% NUM_DCACHE_MISSES_IN_WINDOW_2 2264 15.152% 2264 15.152% NUM_DCACHE_MISSES_IN_WINDOW_3 2172 14.536% 2172 14.536% NUM_DCACHE_MISSES_IN_WINDOW_4 1520 10.173% 1520 10.173% NUM_DCACHE_MISSES_IN_WINDOW_5 2951 19.750% 2951 19.750% NUM_DCACHE_MISSES_IN_WINDOW_6 825 5.521% 825 5.521% NUM_DCACHE_MISSES_IN_WINDOW_7 716 4.792% 716 4.792% NUM_DCACHE_MISSES_IN_WINDOW_8 465 3.112% 465 3.112% NUM_DCACHE_MISSES_IN_WINDOW_9 364 2.436% 364 2.436% NUM_DCACHE_MISSES_IN_WINDOW_10 296 1.981% 296 1.981% NUM_DCACHE_MISSES_IN_WINDOW_11 188 1.258% 188 1.258% NUM_DCACHE_MISSES_IN_WINDOW_12 109 0.729% 109 0.729% NUM_DCACHE_MISSES_IN_WINDOW_13 75 0.502% 75 0.502% NUM_DCACHE_MISSES_IN_WINDOW_14 54 0.361% 54 0.361% NUM_DCACHE_MISSES_IN_WINDOW_15 40 0.268% 40 0.268% NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 229 1.533% 229 1.533% 14942 100.000% 14942 100.000% 3.27 2.75 3.27 2.75 DCACHE_MLP_IN_WINDOW_1_0 9149 61.230% 9149 61.230% DCACHE_MLP_IN_WINDOW_1_5 4257 28.490% 4257 28.490% DCACHE_MLP_IN_WINDOW_2_0 1033 6.913% 1033 6.913% DCACHE_MLP_IN_WINDOW_2_5 249 1.666% 249 1.666% DCACHE_MLP_IN_WINDOW_3_0 114 0.763% 114 0.763% DCACHE_MLP_IN_WINDOW_3_5 43 0.288% 43 0.288% DCACHE_MLP_IN_WINDOW_4_0 46 0.308% 46 0.308% DCACHE_MLP_IN_WINDOW_4_5 9 0.060% 9 0.060% DCACHE_MLP_IN_WINDOW_5_0 22 0.147% 22 0.147% DCACHE_MLP_IN_WINDOW_5_5 5 0.033% 5 0.033% DCACHE_MLP_IN_WINDOW_6_0 4 0.027% 4 0.027% DCACHE_MLP_IN_WINDOW_6_5 6 0.040% 6 0.040% DCACHE_MLP_IN_WINDOW_7_0 2 0.013% 2 0.013% DCACHE_MLP_IN_WINDOW_7_5 0 0.000% 0 0.000% DCACHE_MLP_IN_WINDOW_8_0 1 0.007% 1 0.007% DCACHE_MLP_IN_WINDOW_8_5_OR_MORE 2 0.013% 2 0.013% 14942 100.000% 14942 100.000% 0.57 0.89 0.57 0.89 PARAM_CHIP_CYCLE_TIME 0 0 PARAM_CORE_CYCLE_TIME 312500 312500 PARAM_L1_CYCLE_TIME 312500 312500 PARAM_MEMORY_CYCLE_TIME 833333 833333 MEM_REQ_NON_SCHEDULED__0 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED__4 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED__8 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_12 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_16 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_20 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_24 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_28 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_32 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_36 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_40 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_44 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_48 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_52 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_56 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_60 0 -nan% 0 -nan% MEM_REQ_NON_SCHEDULED_64 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_REQ_DEMANDS__0 3702301 97.144% 3702301 97.144% MEM_REQ_DEMANDS__4 79843 2.095% 79843 2.095% MEM_REQ_DEMANDS__8 13100 0.344% 13100 0.344% MEM_REQ_DEMANDS_12 8045 0.211% 8045 0.211% MEM_REQ_DEMANDS_16 3263 0.086% 3263 0.086% MEM_REQ_DEMANDS_20 1565 0.041% 1565 0.041% MEM_REQ_DEMANDS_24 1075 0.028% 1075 0.028% MEM_REQ_DEMANDS_28 1954 0.051% 1954 0.051% MEM_REQ_DEMANDS_32 0 0.000% 0 0.000% MEM_REQ_DEMANDS_36 0 0.000% 0 0.000% MEM_REQ_DEMANDS_40 0 0.000% 0 0.000% MEM_REQ_DEMANDS_44 0 0.000% 0 0.000% MEM_REQ_DEMANDS_48 0 0.000% 0 0.000% MEM_REQ_DEMANDS_52 0 0.000% 0 0.000% MEM_REQ_DEMANDS_56 0 0.000% 0 0.000% MEM_REQ_DEMANDS_60 0 0.000% 0 0.000% MEM_REQ_DEMANDS_64 0 0.000% 0 0.000% 3811146 100.000% 3811146 100.000% 0.04 0.33 0.04 0.33 MEM_REQ_PREFS__0 2984638 78.313% 2984638 78.313% MEM_REQ_PREFS__4 490034 12.858% 490034 12.858% MEM_REQ_PREFS__8 186032 4.881% 186032 4.881% MEM_REQ_PREFS_12 60284 1.582% 60284 1.582% MEM_REQ_PREFS_16 23972 0.629% 23972 0.629% MEM_REQ_PREFS_20 14243 0.374% 14243 0.374% MEM_REQ_PREFS_24 46516 1.221% 46516 1.221% MEM_REQ_PREFS_28 5427 0.142% 5427 0.142% MEM_REQ_PREFS_32 0 0.000% 0 0.000% MEM_REQ_PREFS_36 0 0.000% 0 0.000% MEM_REQ_PREFS_40 0 0.000% 0 0.000% MEM_REQ_PREFS_44 0 0.000% 0 0.000% MEM_REQ_PREFS_48 0 0.000% 0 0.000% MEM_REQ_PREFS_52 0 0.000% 0 0.000% MEM_REQ_PREFS_56 0 0.000% 0 0.000% MEM_REQ_PREFS_60 0 0.000% 0 0.000% MEM_REQ_PREFS_64 0 0.000% 0 0.000% 3811146 100.000% 3811146 100.000% 0.40 0.94 0.40 0.94 MEM_REQ_WRITEBACKS__0 3808083 99.920% 3808083 99.920% MEM_REQ_WRITEBACKS__4 2949 0.077% 2949 0.077% MEM_REQ_WRITEBACKS__8 114 0.003% 114 0.003% MEM_REQ_WRITEBACKS_12 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_16 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_20 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_24 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_28 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_32 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_36 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_40 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_44 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_48 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_52 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_56 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_60 0 0.000% 0 0.000% MEM_REQ_WRITEBACKS_64 0 0.000% 0 0.000% 3811146 100.000% 3811146 100.000% 0.00 0.03 0.00 0.03 MEM_REQ_DEMAND_CYCLES 2633677 2633677 MEM_REQ_PREF_CYCLES 8526893 8526893 MEM_REQ_WB_CYCLES 344677 344677 DRAM_CHANNEL_REQS 0 0 DRAM_CHANNEL_CRIT_REQS 0 0 DRAM_CHANNEL_CRIT_DIR_SWITCHES 0 0 DRAM_BANK_CRIT_REQS 0 0 DRAM_INSTA_MLP_SAMPLES 0 0 DRAM_INSTA_MLP_UNIQUE_REQS 0 -nan 0 -nan DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000 0 -nan 0 -nan DRAM_GLOBAL_MLP 0 -nan 0 -nan DRAM_GLOBAL_MLP_0 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_1 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_2 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_3 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_4 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_5 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_6 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_7 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_8 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_9 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_10 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_11 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_12 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_13 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_14 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_15 0 -nan% 0 -nan% DRAM_GLOBAL_MLP_16 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_TOTAL_GLOBAL_MLP_0 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_1 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_2 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_3 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_4 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_5 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_6 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_7 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_8 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_9 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_10 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_11 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_12 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_13 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_14 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_15 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_16 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_17 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_18 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_19 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_20 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_21 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_22 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_23 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_24 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_25 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_26 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_27 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_28 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_29 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_30 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_31 0 -nan% 0 -nan% DRAM_TOTAL_GLOBAL_MLP_32 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan UNIQUE_ROWS_PER_BANK_0 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_1 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_2 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_3 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_4 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_5 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_6 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_7 0 -nan% 0 -nan% UNIQUE_ROWS_PER_BANK_MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORE_UNIQUE_ROWS_PER_BANK_0 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_1 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_2 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_3 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_4 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_5 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_6 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_7 0 -nan% 0 -nan% CORE_UNIQUE_ROWS_PER_BANK_MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan CORES_PER_BANK_0 0 -nan% 0 -nan% CORES_PER_BANK_1 0 -nan% 0 -nan% CORES_PER_BANK_2 0 -nan% 0 -nan% CORES_PER_BANK_3 0 -nan% 0 -nan% CORES_PER_BANK_4 0 -nan% 0 -nan% CORES_PER_BANK_5 0 -nan% 0 -nan% CORES_PER_BANK_6 0 -nan% 0 -nan% CORES_PER_BANK_7 0 -nan% 0 -nan% CORES_PER_BANK_MORE 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_BANKS_WITH_REQS_0 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_1 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_2 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_3 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_4 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_5 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_6 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_7 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_8 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_9 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_10 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_11 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_12 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_13 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_14 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_15 0 -nan% 0 -nan% MEM_BANKS_WITH_REQS_16 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_BANKS_WITH_REQS 0 0 DRAM_CHANNEL_IN_DEMAND 0 0 DRAM_BUS_IN_DEMAND 0 0 DRAM_BANK_IN_DEMAND 0 0 DRAM_BANK_IN_DEMAND_STALLING 0 0 DRAM_ANY_BANK_IN_DEMAND 0 0 DRAM_BANK_IN_DEMAND_BANK_0 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_1 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_2 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_3 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_4 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_5 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_6 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_7 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_8 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_9 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_10 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_11 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_12 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_13 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_14 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_15 0 -nan% 0 -nan% DRAM_BANK_IN_DEMAND_BANK_16 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_CONTENTION_BUS 0 -nan 0 -nan DRAM_CONTENTION_BANKS 0 -nan 0 -nan DRAM_CONTENTION_FAW 0 -nan 0 -nan DRAM_CONTENTION_BANKS_TIMES_1000 0 -nan 0 -nan DRAM_STALL_OTHER_CORE 0 0 DRAM_STALLED_BY_OTHER_CORE 0 0 DRAM_MP_CRIT_PATH 0 0 DRAM_MP_CRIT_PATH_BUS 0 -nan 0 -nan DRAM_MP_CRIT_PATH_BANK 0 -nan 0 -nan DRAM_MP_CRIT_PATH_BANK_TRAS 0 -nan 0 -nan DRAM_MP_CRIT_PATH_FAW 0 -nan 0 -nan DRAM_BLACK_BOX_SERVICE_TIMES_1000 0 0 DRAM_BLACK_BOX_REQS_BUSY_0 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_1 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_2 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_3 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_4 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_5 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_6 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_7 0 -nan% 0 -nan% DRAM_BLACK_BOX_REQS_BUSY_8 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan NUM_MEM_SCHED_DECISIONS 0 0 MEM_REQ_NON_SCHEDULED_CANDIDATES 0 -nan 0 -nan NUM_MEM_SCHED_DECISIONS_PER_BANK 0 0 MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK 0 -nan 0 -nan ROW_BUFFER_HITS_BANK_0 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_1 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_2 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_3 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_4 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_5 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_6 0 -nan% 0 -nan% ROW_BUFFER_HITS_BANK_7 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan ROW_BUFFER_CONFLICTS_BANK_0 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_1 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_2 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_3 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_4 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_5 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_6 0 -nan% 0 -nan% ROW_BUFFER_CONFLICTS_BANK_7 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan MEM_BANK_WAITING_CYCLES 0 0 MEM_WAITING_CYCLES_TIMES_840 0 0 MEM_PROB_WAITING_CYCLES 0 0 DRAM_SCHED_QUANTA 0 0 DRAM_SCHED_CORE_PRIORITY_0 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_1 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_2 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_3 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_4 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_5 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_6 0 -nan% 0 -nan% DRAM_SCHED_CORE_PRIORITY_7 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_SCHED_CMD_SCHEDULED 0 -nan 0 -nan DRAM_SCHED_DIFF_CORE_AVAILABLE 0 -nan 0 -nan DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_1 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_2 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_3 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_4 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_5 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_6 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_7 0 -nan% 0 -nan% DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_8 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_BANK_WAIT_CYCLES_ROW_CONFLICT 0 0 DRAM_BANK_WAIT_CYCLES_ROW_MISS 0 0 DRAM_BANK_WAIT_CYCLES_ROW_HIT 0 0 DRAM_ROW_OPEN_WAIT 0 0 MEM_QUEUE_ARRIVAL_DISTANCE_0 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_10 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_20 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_30 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_40 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_50 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_60 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_70 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_80 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_90 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_100 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_110 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_120 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_130 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_140 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_150 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_160 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_170 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_180 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_190 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_200 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_210 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_220 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_230 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_240 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_250 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_260 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_270 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_280 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_290 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_300 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_310 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_320 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_330 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_340 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_350 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_360 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_370 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_380 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_390 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_400 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_410 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_420 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_430 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_440 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_450 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_460 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_470 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_480 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_490 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_500 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_510 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_520 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_530 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_540 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_550 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_560 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_570 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_580 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_590 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_600 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_610 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_620 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_630 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_640 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_650 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_660 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_670 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_680 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_690 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_700 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_710 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_720 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_730 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_740 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_750 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_760 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_770 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_780 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_790 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_800 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_810 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_820 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_830 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_840 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_850 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_860 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_870 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_880 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_890 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_900 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_910 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_920 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_930 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_940 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_950 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_960 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_970 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_980 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_990 0 -nan% 0 -nan% MEM_QUEUE_ARRIVAL_DISTANCE_1000 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan EQUAL_USE_QUANTUMS 0 0 EQUAL_USE_BW_MEASURE_PERIODS 0 0 EQUAL_USE_BW 0 0 EQUAL_USE_BOTTLENECK_BUS 0 -nan% 0 -nan% EQUAL_USE_BOTTLENECK_BANK 0 -nan% 0 -nan% EQUAL_USE_BOTTLENECK_FAW 0 -nan% 0 -nan% EQUAL_USE_BOTTLENECK_BUS_PLUS_FAW 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan EQUAL_USE_BW_BUS 0 0 EQUAL_USE_BW_BANK 0 0 EQUAL_USE_BW_FAW 0 0 EQUAL_USE_BW_BUS_PLUS_FAW 0 0 EQUAL_USE_BW_BUS_PLUS_FAW2 0 0 EQUAL_USE_BW_BUS_PLUS_FAW3 0 0 EQUAL_USE_BW_CRIT_PATH 0 0 EQUAL_USE_BW_BLACK_BOX 0 0 DRAM_BANK_SERVICE 0 0 DRAM_CONTENDED_BANK_SERVICE 0 0 DRAM_BUS_DIR_SWITCHES 0 0 DRAM_ACTIVATE_TO_COLUMN_LATENCY 0 0 DRAM_ACTIVATE_TO_READ 0 0 DRAM_ACTIVATE_TO_READ_LATENCY 0 -nan 0 -nan DRAM_ACTIVATE_TO_WRITE 0 0 DRAM_ACTIVATE_TO_WRITE_LATENCY 0 -nan 0 -nan EQUAL_USE_PRIORITY_0 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_1 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_2 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_3 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_4 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_5 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_6 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_7 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_8 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_9 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_10 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_11 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_12 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_13 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_14 0 -nan% 0 -nan% EQUAL_USE_PRIORITY_15 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_ROW_ACCESSES_0 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_1 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_2 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_3 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_4 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_5 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_6 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_7 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_8 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_9 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_10 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_11 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_12 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_13 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_14 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_15 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_16 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_17 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_18 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_19 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_20 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_21 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_22 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_23 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_24 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_25 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_26 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_27 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_28 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_29 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_30 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_31 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_32 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_33 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_34 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_35 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_36 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_37 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_38 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_39 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_40 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_41 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_42 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_43 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_44 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_45 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_46 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_47 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_48 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_49 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_50 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_51 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_52 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_53 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_54 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_55 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_56 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_57 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_58 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_59 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_60 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_61 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_62 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_63 0 -nan% 0 -nan% DRAM_ROW_ACCESSES_64 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_NUM_REQS_0_TOTAL 0 0 DRAM_NUM_REQS_1_TOTAL 0 0 DRAM_NUM_REQS_2_TOTAL 0 0 DRAM_NUM_REQS_3_TOTAL 0 0 DRAM_NUM_REQS_4_TOTAL 0 0 DRAM_NUM_REQS_5_TOTAL 0 0 DRAM_NUM_REQS_6_TOTAL 0 0 DRAM_NUM_REQS_7_TOTAL 0 0 DRAM_NUM_REQS_8_TOTAL 0 0 DRAM_NUM_REQS_9_TOTAL 0 0 DRAM_NUM_REQS_10_TOTAL 0 0 DRAM_NUM_REQS_11_TOTAL 0 0 DRAM_NUM_REQS_12_TOTAL 0 0 DRAM_NUM_REQS_13_TOTAL 0 0 DRAM_NUM_REQS_14_TOTAL 0 0 DRAM_NUM_REQS_15_TOTAL 0 0 DRAM_NUM_REQS_16_TOTAL 0 0 DRAM_NUM_REQS_17_TOTAL 0 0 DRAM_NUM_REQS_18_TOTAL 0 0 DRAM_NUM_REQS_19_TOTAL 0 0 DRAM_NUM_REQS_20_TOTAL 0 0 DRAM_NUM_REQS_21_TOTAL 0 0 DRAM_NUM_REQS_22_TOTAL 0 0 DRAM_NUM_REQS_23_TOTAL 0 0 DRAM_NUM_REQS_24_TOTAL 0 0 DRAM_NUM_REQS_25_TOTAL 0 0 DRAM_NUM_REQS_26_TOTAL 0 0 DRAM_NUM_REQS_27_TOTAL 0 0 DRAM_NUM_REQS_28_TOTAL 0 0 DRAM_NUM_REQS_29_TOTAL 0 0 DRAM_NUM_REQS_30_TOTAL 0 0 DRAM_NUM_REQS_31_TOTAL 0 0 DRAM_NUM_REQS_32_TOTAL 0 0 DRAM_NUM_REQS_0_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_0_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_0_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_0_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_0_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_0_WB 0 -nan 0 -nan DRAM_NUM_REQS_0_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_1_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_1_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_1_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_1_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_1_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_1_WB 0 -nan 0 -nan DRAM_NUM_REQS_1_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_2_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_2_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_2_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_2_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_2_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_2_WB 0 -nan 0 -nan DRAM_NUM_REQS_2_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_3_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_3_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_3_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_3_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_3_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_3_WB 0 -nan 0 -nan DRAM_NUM_REQS_3_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_4_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_4_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_4_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_4_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_4_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_4_WB 0 -nan 0 -nan DRAM_NUM_REQS_4_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_5_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_5_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_5_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_5_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_5_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_5_WB 0 -nan 0 -nan DRAM_NUM_REQS_5_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_6_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_6_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_6_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_6_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_6_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_6_WB 0 -nan 0 -nan DRAM_NUM_REQS_6_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_7_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_7_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_7_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_7_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_7_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_7_WB 0 -nan 0 -nan DRAM_NUM_REQS_7_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_8_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_8_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_8_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_8_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_8_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_8_WB 0 -nan 0 -nan DRAM_NUM_REQS_8_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_9_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_9_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_9_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_9_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_9_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_9_WB 0 -nan 0 -nan DRAM_NUM_REQS_9_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_10_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_10_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_10_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_10_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_10_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_10_WB 0 -nan 0 -nan DRAM_NUM_REQS_10_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_11_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_11_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_11_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_11_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_11_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_11_WB 0 -nan 0 -nan DRAM_NUM_REQS_11_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_12_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_12_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_12_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_12_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_12_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_12_WB 0 -nan 0 -nan DRAM_NUM_REQS_12_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_13_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_13_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_13_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_13_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_13_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_13_WB 0 -nan 0 -nan DRAM_NUM_REQS_13_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_14_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_14_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_14_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_14_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_14_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_14_WB 0 -nan 0 -nan DRAM_NUM_REQS_14_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_15_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_15_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_15_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_15_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_15_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_15_WB 0 -nan 0 -nan DRAM_NUM_REQS_15_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_16_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_16_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_16_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_16_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_16_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_16_WB 0 -nan 0 -nan DRAM_NUM_REQS_16_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_17_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_17_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_17_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_17_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_17_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_17_WB 0 -nan 0 -nan DRAM_NUM_REQS_17_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_18_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_18_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_18_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_18_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_18_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_18_WB 0 -nan 0 -nan DRAM_NUM_REQS_18_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_19_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_19_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_19_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_19_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_19_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_19_WB 0 -nan 0 -nan DRAM_NUM_REQS_19_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_20_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_20_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_20_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_20_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_20_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_20_WB 0 -nan 0 -nan DRAM_NUM_REQS_20_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_21_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_21_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_21_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_21_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_21_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_21_WB 0 -nan 0 -nan DRAM_NUM_REQS_21_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_22_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_22_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_22_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_22_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_22_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_22_WB 0 -nan 0 -nan DRAM_NUM_REQS_22_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_23_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_23_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_23_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_23_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_23_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_23_WB 0 -nan 0 -nan DRAM_NUM_REQS_23_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_24_WB 0 -nan 0 -nan DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_25_WB 0 -nan 0 -nan DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_26_WB 0 -nan 0 -nan DRAM_NUM_REQS_26_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_27_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_27_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_27_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_27_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_27_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_27_WB 0 -nan 0 -nan DRAM_NUM_REQS_27_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_28_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_28_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_28_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_28_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_28_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_28_WB 0 -nan 0 -nan DRAM_NUM_REQS_28_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_29_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_29_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_29_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_29_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_29_WB 0 -nan 0 -nan DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_30_WB 0 -nan 0 -nan DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_31_WB 0 -nan 0 -nan DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan DRAM_NUM_REQS_32_WB 0 -nan 0 -nan DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% GOOD_ADDRESS 6461684 100.000% 6461684 100.000% 6461684 100.000% 6461684 100.000% 1.00 1.00 1.00 1.00 BBL_LENGTH_1 0 -nan% 0 -nan% BBL_LENGTH_2 0 -nan% 0 -nan% BBL_LENGTH_3 0 -nan% 0 -nan% BBL_LENGTH_4 0 -nan% 0 -nan% BBL_LENGTH_5 0 -nan% 0 -nan% BBL_LENGTH_6 0 -nan% 0 -nan% BBL_LENGTH_7 0 -nan% 0 -nan% BBL_LENGTH_8 0 -nan% 0 -nan% BBL_LENGTH_9 0 -nan% 0 -nan% BBL_LENGTH_10 0 -nan% 0 -nan% BBL_LENGTH_11 0 -nan% 0 -nan% BBL_LENGTH_12 0 -nan% 0 -nan% BBL_LENGTH_13 0 -nan% 0 -nan% BBL_LENGTH_14 0 -nan% 0 -nan% BBL_LENGTH_15 0 -nan% 0 -nan% BBL_LENGTH_16 0 -nan% 0 -nan% BBL_LENGTH_17 0 -nan% 0 -nan% BBL_LENGTH_18 0 -nan% 0 -nan% BBL_LENGTH_19 0 -nan% 0 -nan% BBL_LENGTH_20 0 -nan% 0 -nan% BBL_LENGTH_21 0 -nan% 0 -nan% BBL_LENGTH_22 0 -nan% 0 -nan% BBL_LENGTH_23 0 -nan% 0 -nan% BBL_LENGTH_24 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan BBL_DONT_END_PRED_NT_LENGTH_1 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_2 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_3 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_4 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_5 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_6 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_7 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_8 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_9 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_10 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_11 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_12 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_13 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_14 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_15 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_16 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_17 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_18 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_19 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_20 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_21 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_22 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_23 0 -nan% 0 -nan% BBL_DONT_END_PRED_NT_LENGTH_24 0 -nan% 0 -nan% 0 -nan% 0 -nan% -nan -nan -nan -nan DATA_LD_CYCLES_ONPATH 2470697 2470697 DATA_LD_CYCLES_OFFPATH 37171 37171 DATA_LD_MLC_CYCLES_ONPATH 896527 896527 DATA_LD_MLC_CYCLES_OFFPATH 34892 34892 DATA_LD_MLC_ACCESSES_ONPATH 44757 44757 DATA_LD_MLC_ACCESSES_OFFPATH 1737 1737 DATA_LD_L1_CYCLES_ONPATH 425539 425539 DATA_LD_L1_CYCLES_OFFPATH 0 0 DATA_LD_L1_ACCESSES_ONPATH 7210 7210 DATA_LD_L1_ACCESSES_OFFPATH 0 0 DATA_LD_MEM_CYCLES_ONPATH 1148631 1148631 DATA_LD_MEM_CYCLES_OFFPATH 2279 2279 DATA_LD_MEM_ACCESSES_ONPATH 5814 5814 DATA_LD_MEM_ACCESSES_OFFPATH 10 10 DATA_LD_PREF_CYCLES_ONPATH 0 0 DATA_LD_PREF_CYCLES_OFFPATH 0 0 DATA_LD_PREF_MLC_CYCLES_ONPATH 0 0 DATA_LD_PREF_MLC_CYCLES_OFFPATH 0 0 DATA_LD_PREF_L1_CYCLES_ONPATH 0 0 DATA_LD_PREF_L1_CYCLES_OFFPATH 0 0 DATA_LD_PREF_MEM_CYCLES_ONPATH 0 0 DATA_LD_PREF_MEM_CYCLES_OFFPATH 0 0 UOP_CACHE_LINE_EVICTED_USEFUL 342859 32.958% 342859 32.958% UOP_CACHE_LINE_EVICTED_USELESS 697417 67.042% 697417 67.042% 1040276 100.000% 1040276 100.000% 0.67 0.61 0.67 0.61