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| "text": "Lectures: 45 hours. Evaluation: Midterm Exam (20%), Final Exam (40%),\nTutorial: Weight: 10%.\nLabs/Practices: 20 hours. Weight: 10%.\nProjects: 15 hours. Weight: 30%.\nSelf-study: 125 hours.\nOthers:", |
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| "text": "HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY BK TP.HCM TRUONG DAI HQC BACH KHOA - DHQG-HCM Dai Hoc Qu6c Gia TP.HCM Vietnam National University - HCMC Truo'ng Dai Hoc Bach Khoa Ho Chi Minh City University of Technology Khoa Khoa hoc va Ky thuat Mäy tinh Faculty of Computer Science and Engineering DE CUONG HOC PHAN Course Syllabus 1. Thong tin vé hoc phan (Course information) 1.1. Thong tin tong quan (General information) - Tén hoc phan: Kién trüc may tinh Course title: Computer Architecture Ma hoc phan (Course ID): CO2007 - S6 tin chi (Credits): 4 (ETCS: 8 ) - Hoc ky äp dung (Applied from semester): 20221 To chúc hoc phan (Course format) : Hinh thüc hoc tap Só tiét/gi S6 tin chi Ghi chü (Teaching/study type) (Hours) (Credits) (Notes) Ly thuyét (LT) 45 (Lectures) Thao luan (ThL/Thuc hanh tai l6p (TH) O (Tutorial) Thi nghiem (TNg)/Thuc tap xuöng (TT) 20 Labs/Practices Bai tap l6n (BTL)/D6 án (DA) 15 (Projects) Tu hoc (Self-study) 125 Khäc (Others) O Tong cöng (Total) 172.5 4 Ty lé dänh giä va hinh thúc kiém tra/thi (Evaluation form & ratio) Hinh thúc danh gia Ty le Hinh thüc Thoi gian (Evaluation type) (Ratio) (Format) (Duration) Thäo luan (ThL)/Thuc hanh tai lóp (TH) (Tutorial) Thi nghiém 10% Labs/Practices) Bai tap l6n (BTL)/D6 än (DA) 30% (Projects) Kiém tra 20% Trac nghiém 60 phút (minutes) (Midterm Exam) (Multiple choice (MCQ) Thi 40% Trac nghiém 90 phút (minutes)", |
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| "text": "Projects) Kiém tra 20% Trac nghiém 60 phút (minutes) (Midterm Exam) (Multiple choice (MCQ) Thi 40% Trac nghiém 90 phút (minutes) (Final Exam) (Multiple choice (MCQ)) Tong cong 100% (Total)", |
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| "text": "Course: Computer_Architecture (ID: )", |
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| "text": "Stu: Nghe giang va lam bai tap (Listen to lectures and do exercises 7. Yeu cau khäc vé hoc phan (Other course requirements and expectations) 8. Bién soan va cap nhat dé cuong (Editing information) - Dé cuong dugc bién soan vao nam hoc hoc ky (Syllabus edited in year-semester): 20221 - Dé cuong duoc chinh sura lan thú (Editing version) : DCMH.CO2007.8.1 - Nöi dung duoc chinh sua, cap nhat, thay dói ö lan gan nhat (The latest editing content): -- -- Tp.H6 Chi Minh, ngay 3 thang 9 nam 2022 HCM City, September 3 2022 TRUONG KHOA CHU NHIEM BO MON CB PHU TRACH LAP DE CUONG (Dean) Head of Department) (Lecturer in-charge) 268 Ly Thuong Ki&t, Phuong 14,Quan 10,TP.HCM 268 Ly Thuong Kiet St., Ward 14, Dist. 10, Ho Chi Minh City, Vietnam Dien thoai: 028 3864 7256 Phone: 028 3864 7256 www.hcmut.edu.vn www.hcmut.edu.vn", |
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| "text": "chüc nang cap khäi niém Lec: Thuyét giang va giao bai tap 4.2. Lo trinh cac cong doan thuc hién lénh (Lectures and assignments) 4.3. Tin hiéu diéu khién Stu: Nghe giang va lam bai tap 4.4. L trinh dü lieu theo co ché don chu ky Listen to lectures and do exercises) 4.5. L trinh d liéu theo co ché óng (da chu ky). L.0.3.2 [ A.0.1 , A.0.2 , A.0.3 ] 4.6. Nhung yan dé xäy ra va cäch giai quyét khi thuc hién Lec: Thuyét giang va giao bai tap theo co ché ng (Lectures and assignments) 4.7. Ngoai lé va cac van dé can giai quyét Stu: Nghe giang va lam bai tap Listen to lectures and do exercises) (Chapter 4. Processor: Data Path - Control L.0.3.3 [ A.0.1 , A.0.2 , A.0.3 ] 4.1. Concept-level functional execution block Lec: Thuyét giang va giao bai tap 4.2. The route of the order execution stages (Lectures and assignments) 4.3. Control signal Stu: Nghe giäng va lam bai tap 4.4. Single-cycle data route (Listen to lectures and do exercises) 4.5. Pipeline (multi-cycle) data route 4.6. Problems and solutions when implementing the pipe mechanism 4.7. Exceptions and issues to be resolved) 13-14 Chuong 5. Bo nh6 L.0.4.2 [A.0.1 A.0.3 ] 5.1. Cäu trúc phan tang va su cän thiét phan tang Lec: Thuyét giang va giao bai tap 5.2. Nguyén tac cuc bo (Lectures and assignments) 5.3. Tó chúc va co ché hoat dong cache o Stu: Ng", |
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| "text": "ét giang va giao bai tap 5.2. Nguyén tac cuc bo (Lectures and assignments) 5.3. Tó chúc va co ché hoat dong cache o Stu: Nghe giang va lam bai tap 5.4. Cai thién hiéu suat cache Listen to lectures and do exercises 5.5. Bo nh6 ao: cac thuat ngu L.0.4.1 [A.0.1 , A.0.3 ] 5.6. Tó chúc va quan ly b nhó ao o Lec: Thuyét giang va giao bai tap 5.7. Tói uu b nh6 ao (Lectures and assignments) Stu: Nghe giang va lam bai tap (Listen to lectures and do exercises) (Chapter 5. Memory L.0.4.3 [A.0.1 , A.0.3 ] 5.1. Hierarchical structure and the need for stratification o Lec: Thuyét giang va giao bai tap 5.2. Local principles (Lectures and assignments) 5.3. Cache organization and mechanism Stu: Nghe giäng va lam bai tap 5.4. Improved cache performance Listen to lectures and do exercises) 5.5. Virtual memory: terms 5.6. Organize and manage virtual memory 5.7. Optimize virtual memory) 15 Chuong 6. Xü ly song song L.0.3.3 [A.0.1 , A.0.3 ] 4.1. Gi6i thiéu Lec: Thuyét giang va giao bai tap 4.2. Cac kién trúc tinh toanh song song (Lectures and assignments) o Stu: Nghe giang va lam bai tap Listen to lectures and do exercises (Chapter 6. Parallel Processing L.0.3.2 [A.0.1 , A.0.3 ] 4.1. Introduce o Lec: Thuyét giang va giao bai tap 4.2. Parallel computing architectures (Lectures and assignments) Stu: Nghe giäng va lam bai tap (Listen to lectures and do exercises)", |
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| "text": "Lec: Thuyét giang va giao bai tap 4.2. Parallel computing architectures (Lectures and assignments) Stu: Nghe giäng va lam bai tap (Listen to lectures and do exercises) L.0.3.1 [A.0.1 , A.0.3 ] Lec: Thuyét giang va giao bai tap (Lectures and assignments)", |
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| "id": "CO2007-chapter-0-slide-000-0000", |
| "text": "COMPUTER R ARCHITECTURE Introduction BK Computer Engineering - CSE - HCMUT 1 TP.HCM", |
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| "text": "Administrative issues Instructor: - Assoc. Prof. Dr. Cuong Pham-Quoc (in Vietnamese Pham Quöc Cung) Computer Engineering Department, Faculty of Computer Science and Engineering, HCMUT Email: cuongpham@hcmut.edu.vn Homepage: www.cse.hcmut.edu.vn/cuongpham BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2", |
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| "CO2007-chapter-0-slide-002-0000": { |
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| "text": "Computer Q: What is a Computer? - A: \"an electronic machine that is used for storing, organizing, and finding words, numbers, and pictures, for doing calculations, and for controlling other machines\" - Cambridge dictionary A: \"a general-purpose device that can be programmed to carry out a set of arithmetic or logical operations automatically\" - Wikipedia Abacus BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3", |
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| "CO2007-chapter-0-slide-003-0000": { |
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| "text": "Computer architecture Q: What is Computer Architecture? A: \"the science and art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals\" - WWW Computer Architecture Page jump target branch target result bus fetch decode execute writeback branch PC logic op2 alu regfile op1 fw2 w_m decode logic fw1 w_e pmem dmem bop addr addr din dout dout ext addrWext dout ext din BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4", |
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| "text": "The course Elementary course for both Computer Engineering and Computer Science programs Contents: - Performance evaluation Instruction set architecture Computer arithmetic Data-path and control signals Memory & l/O system Multicores, Multiprocessors, and Clusters BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5", |
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| "text": "Outcomes Outcomes: Understand the structure, organization of a computer system: the main components and the basic principles of its operations Write and optimize small programs and fragments of codes to demonstrate an understanding of machine leve operation BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6", |
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| "text": "Learning materials Slides/handouts BKEL DAIHOC QUOCGIA TP HO CHI MINH TRUONGDAIHOCBACHKHOA www.cse.hcmut.edu.vn/cuongpham Textbooks Cepyighted Materia KIENTRUC COMPUTER ORGANIZATION MAY TiNH swap: multi $2, $5,4 AND DESIGN add$2,$4,$2 lw $15, 0$2) lw $16, 4$2) SW $16, 0$2) SW $15, 4($2) THE HARDWARE/SOFTWARE INTERFACE jr $31 5 bit 32bit acv ngun 1 Lenh Du lieu 1 Toar FIFTHEDTIO DAVIDA PATTERSON 5 bit hang 1 zero Ghbonho # nguon 2 JOHN LHENNESSY 32 bit 5 bit ALU 32. Dir 32 bi # dich Ke Dia chi lieu 32 bit De lieu2 qua 32bit Da DE li@u ghi ang B nhó Tap thanhghi vao dulieu Ghi thanh gh Doc ba nho PHAM Quóc Cuöng M< NHA XUAT BAN DAI HOC QUOC GIA TP HO CHi MINH Copyright BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7", |
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| "text": "Assessment Assignment: 30% Labs: 10% (mandatory) Mid-term: 20% - multiple choices/writing, with 1 A4 piece of paper note Final exam: 40% - multiple choices/writing, with 2 A4 piece of paper note BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8", |
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| "text": "In-class regulations C 1o handout #202334458 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9", |
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| "text": "COMPUTER ARCHITECTURE Chapter 1: Technology & Performance evaluation BK Computer Engineering - CSE - HCMUT TP.HCM", |
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| "CO2007-chapter-1-slide-010-0000": { |
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| "text": "TECHNOLOGY REVIEW BK TP.HCM 2", |
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| "text": "The computer revolution The third revolution along with agriculture and industry Progress in computer technology Underpinned by Moore's Law Makes novel applications feasible Computers in automobiles - Cell phones - Human genome project - World Wide Web Search Engines ABACUS Computers are pervasive BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3", |
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| "text": "The Moore's Law 50,000,000,000 72-core Xeon Phi Centriq 2400 GC2IPU SPARC M7 32-core AMD Epyc IBM z13 Storage Controller. Apple A12X Bionic 10,000,000,000 18-core Xeon Haswell-E5 + Tegra Xavier SoC Qualcomm Snapdragon 8cx/SCX8180 Xbox One main SoC 5,000,000,000 HiSilicon Kirin 980+Apple A12 Bionic 12-core POWER8 HiSilicon Kirin 710 8-coreXeon Nehalem-EX 10-core Core i7 BroadwellE Six-coreXeon 7400 QualcommSnapdragon 835 Dual-core Itanium 2 Dual-core+GPU Iris Core i7 Broadwell-U Quad-core + GPU GT2 Core i7 Skylake K 1,000,000,000 Pentium D Presler POWER6 Quad-core+ GPU Core i7 Haswell Itanium 2with Apple A7 (dual-core ARM64\"mobile SoC\" 500,000,000 9MB cache Core i7 (Quad) Itanium2Madison 6M AMD K10 quad-core 2M L3 Core 2 Duo'Wolfdale Pentium D Smithfield Itanium 2McKiniey Core 2.Duo Conroe Core 2 Duo Wolfdale 3M Pentium 4Prescott-2M Core 2 Duo Allendale 100,000,000 Pentium 4Cedar Mill 50.000.000 Pentium 4Willamette Atom ARM Cortex-A9 AMD K6-IiI 10,000,000 Pentiym IlIl Katma Pentium Pro PentiumII Deschutes 5,000,000 Pentiumg oKlamath AMD K5 + Intel 80486 1,000,000 + R4000 500,000 ARM700 Intel 80386 Intel ARM3 Motorola 68020 i960 100,000 MultiTitan Motorola Intel80286 68000 50,000 Intel 80186 Intel8086 ntel 8088 ARM2 ARM6 Motorola WDC 65C816 6809 Novix Gordon Moore 10,000 TMS.1000 Zilog Z80. & WD NC4016 A RCA.1802 65C02 5,000 Intel8085 Intel8008 Intel 8080 MQ", |
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| "id": "CO2007-chapter-1-slide-012-0001", |
| "text": "6809 Novix Gordon Moore 10,000 TMS.1000 Zilog Z80. & WD NC4016 A RCA.1802 65C02 5,000 Intel8085 Intel8008 Intel 8080 MQS Technology Intel co-founder Motorola 6502 Intel 4004 6800 Our World 1,000 in Data 4829849869889908298499g98202002 4080 t 1 2018 The number of transistors integrated in a chip has doubled every 18-24 months (1975) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4", |
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| "CO2007-chapter-1-slide-013-0000": { |
| "id": "CO2007-chapter-1-slide-013-0000", |
| "text": "Intel processors As of Q1/2023 intel. intel intel. Raptor Lake: 13th CORe CORe generation CORC 10 nm technology i5 i3 i7 Intel\" Core i9 Intel\" Core i7 Intel\" Core i5 Intel Core i3 Processors Processors Processors Processors Max Turbo Frequency Up to 5.8 Up to 5.4 Up to 5.1 Up to 4.5 [GHz] Intel Turbo Boost Max Up to 5.7 Up to 5.4 n/a n/a Technology 3.0 Frequency [GHz] Performance-core Max Up to 5.4 Up to 5.3 Up to 5.1 Up to 4.5 Turbo Frequency [GHz] BK TP.HCM 5", |
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| "CO2007-chapter-1-slide-014-0000": { |
| "id": "CO2007-chapter-1-slide-014-0000", |
| "text": "History... The first computer in the world II BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6", |
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| "CO2007-chapter-1-slide-015-0000": { |
| "id": "CO2007-chapter-1-slide-015-0000", |
| "text": "History... Facts of ENIAC: 30+ tons -: 1,500+ square feet (140 square meter) 18,000+ vacuum tubes 140+ KW power 5,000+ additions per second ENIAC: Electronic Numerical Integrator and Computer BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7", |
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| "id": "CO2007-chapter-1-slide-016-0000", |
| "text": "A Brief History of Computers The first generation - Vacuum tubes - 1946- 1955 The second generation Transistors EZ80 AFEINHOULA 1955 - 1965 The third generation 1965- 1980 Integrated circuits The current generation 1980 - ... - Personal computers What's the next? - Quantum computers? Areplica of the first transistor microeiectronicsgroup O December 23.1947 Lucent Technologies 50 Years and Counting. - Memristor? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8", |
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| "id": "CO2007-chapter-1-slide-017-0000", |
| "text": "Classes of Computers Personal computers General purpose, variety of software Subject to cost/performance tradeoff Server computers - Network based - High capacity, performance, reliability Range from small servers to building sized Supercomputers High-end scientific and engineering calculations Highest capability but represent a small fraction of the overall computer market Embedded computers Hidden as components of systems - Stringent power/performance/cost constraints 18 16 15 2 3 12 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9", |
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| "id": "CO2007-chapter-1-slide-018-0000", |
| "text": "Post PC era 3000 Tablets 2500 Smartphones 272.6 249.2 2000 276.7 256 PCs 229.7 1500 227.3 145 11942 1000 76 725.3 494.5 500 304.7 358 364 349 315.3 308.1 276.7 256.1 272.6 249.1 0 2010 2011 2012 2013 2014 2015 2016* 2019* 2020* The number of devices (millions) shipped - source: statista.com BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10", |
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| "CO2007-chapter-1-slide-019-0000": { |
| "id": "CO2007-chapter-1-slide-019-0000", |
| "text": "Modern computer components Same components for all kinds Compiler Components - Processor Interface Datapath Computer controller Memory Input Main memory Cache Control Input/Output Datapath Evaluating performance User-interface Output Network Processor Memory Storage BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 11", |
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| "CO2007-chapter-1-slide-020-0000": { |
| "id": "CO2007-chapter-1-slide-020-0000", |
| "text": "Below your program Application software - Written in high-level language System software Compiler: translates HLL code to machine code Operating System: service code Handling input/output Hardware Managing memory and storage Scheduling tasks & sharing resources Hardware - Processor, memory, I/o controllers BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12", |
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| "CO2007-chapter-1-slide-021-0000": { |
| "id": "CO2007-chapter-1-slide-021-0000", |
| "text": "Levels of Program Code High-level swap(int v[l, int k language tint temp; High-level language program temp = v[k]; (in C) v[k] = v[k+1]; v[k+1] = temp; Level of abstraction closer to problem domain Compiler Provides for productivity and portability Assembly swap: language muli $2, $5,4 Assembly language program add $2, $4,$2 (for MIPS) 1w $15, 0($2) 1w $16, 4($2) SW $16, 0($2) Textual representation of SW $15, 4($2) jr $31 instructions Hardware representation Assembler Binary digits (bits) Binary machine 00000000101000010000000000011000 Encoded instructions and language 00000000000110000001100000100001 program 10001100011000 0000000000000 data (for MIPS) 10001100111100 00000000000100 10101100111100 00000000000000 10101100011000 10000000000100 BK 0000001111100 00000000001000 TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13", |
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| "id": "CO2007-chapter-1-slide-022-0000", |
| "text": "Technology trends 10,000,000 4G 1,000,000 2G 1G Thanks to electronics and 100,000 512M 16M 64M 10,000 4M material technologies 1M 1000 256K 64K - Increased capacity and 100 16K 10 19761978 1980 19821984 19861988 1990 1992 1994 19961998 2000 2002 2004 2006 2008 2010 2012 performance Year of introduction DRAM capacity Reduced cost Year Technology Relative performance/cost 1951 Vacuum tube 1 1965 Transistor 35 1975 Integrated circuit (IC) 900 1995 Very large scale lC (VLSI) 2,400,000 2013 Ultra large scale IC 250,000,000,000 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14", |
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| "CO2007-chapter-1-slide-023-0000": { |
| "id": "CO2007-chapter-1-slide-023-0000", |
| "text": "PERFORMANCE EVALUATION BK TP.HCM 15", |
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| "CO2007-chapter-1-slide-024-0000": { |
| "id": "CO2007-chapter-1-slide-024-0000", |
| "text": "Defining performance Which airplane has the best performance? Boeing 777 Boeing 777 Boeing 747 Boeing 747 BAC/Sud BAC/Sud Concorde Concorde Douglas Dc- Douglas DC- 8-50 8-50 0 100 200 300 400 500 0 2000 4000 6000 8000 10000 l Passenger Capacity Cruising Range (miles) Boeing 777 Boeing 777 Boeing 747 Boeing 747 BAC/Sud BAC/Sud Concorde Concorde Douglas DC- Douglas DC- 8-50 8-50 0 500 1000 1500 0 100000 200000 300000 400000 Cruising Speed (mph) Passengers x mph BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16", |
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| "CO2007-chapter-1-slide-025-0000": { |
| "id": "CO2007-chapter-1-slide-025-0000", |
| "text": "Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/... per hour How are response time and throughput affected by Replacing the processor with a faster version? - Adding more processors? We'll focus on response time for now... BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 17", |
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| "CO2007-chapter-1-slide-026-0000": { |
| "id": "CO2007-chapter-1-slide-026-0000", |
| "text": "Relative performance 1 Performance = Execution time Computer X is n times faster than Computer Y Performancex Execution timey : n Performancey Execution timex Example: time take to run a program 10s on A and 15s on B ExecutionB 15s A is 1.5 x faster than B because = 1.5 x ExecutionA 10s BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18", |
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| "CO2007-chapter-1-slide-027-0000": { |
| "id": "CO2007-chapter-1-slide-027-0000", |
| "text": "Measuring time Elapsed time - Total response time, including all aspects Processing, I/O, Os overhead, idle time Determines system performance CPU time - Time spent processing a given job Discounts I/O time, other jobs' shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19", |
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| "CO2007-chapter-1-slide-028-0000": { |
| "id": "CO2007-chapter-1-slide-028-0000", |
| "text": "Measuring CPU time Operations of digital hardware (including CPU/processor) governed by a constant-rate clock Clock period Clock (cycles) Data transfer and computation Update state - Clock period (T): duration of a clock cycle s, ms, us, ns Clock rate/frequency (F = - the number of cycles per second 1 Hz,KHz,MHz,GHz BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20", |
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| "CO2007-chapter-1-slide-029-0000": { |
| "id": "CO2007-chapter-1-slide-029-0000", |
| "text": "CPU time Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count CPU Time = CPU Clock Cycles X Clock Cycle Time CPU Clock Cycles Clock Rate BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21", |
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| "CO2007-chapter-1-slide-030-0000": { |
| "id": "CO2007-chapter-1-slide-030-0000", |
| "text": "CPU time example Computer A: 2GHz clock, 10s CPU time Designing Computer B - Aim for 6s CPU time - Can do faster clock, but causes 1.2 x clock cycles How fast must Computer B clock be? CPU TimeA = Clock RateA 2.0GHz CPU Clock CyclesB CpU TimeB = Clock RateB Clock RateB => Clock RateB = 4.0GHz BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22", |
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| "CO2007-chapter-1-slide-031-0000": { |
| "id": "CO2007-chapter-1-slide-031-0000", |
| "text": "Instruction count & CPl Instruction Count for a program Determined by program, IsA and compiler Average cycles per instruction Determined by CPU hardware - If different instructions have different CPI Average CPI affected by instruction mix Clock Cycles = Instruction count X Cycles per Instruction CPU Time = Instruction count X Cycles per Instruction X Clock Cycle Time Instruction count X Cycles per Instruction IC X CPI Clock Rate Clock Rate BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23", |
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| "CO2007-chapter-1-slide-032-0000": { |
| "id": "CO2007-chapter-1-slide-032-0000", |
| "text": "Example Which is faster, and by how much? - Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same IsA, compiler CPU TimeA = ICa X CPlA X Cycle TimeA = IC x 2.0 x 250ps CPU TimeB = ICB X CPlB X Cycle TimeB = IC x 1.2 x 500ps CPU TimeB IC x 600ps = 1.2 X CPU TimeA IC X 500ps BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24", |
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| "CO2007-chapter-1-slide-033-0000": { |
| "id": "CO2007-chapter-1-slide-033-0000", |
| "text": "Mixed instructions CPI CPl for instructions/operations may vary - e.g.,: multiplication takes more cycles than addition More precise CPU clock cycles should take instruction types into account n Clock cycles = (CPI; X Instruction counti) i=1 Weighted average CPI n Clock cycles Instruction count (CPI; X CPl = Instruction count Instruction count i=1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25", |
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| "CO2007-chapter-1-slide-034-0000": { |
| "id": "CO2007-chapter-1-slide-034-0000", |
| "text": "Example Question: two implementations of an application that use instructions in classes A, B, and C as follows. Which one is better? Implementation 1 uses 2 A, 1 B, and 2 C Implementation 2 uses 4 A, 1 B, and 1 C CPls for A, B, and C are 1, 2, and 3, respectively Answer: lmplementation 1: clock cycles1 = 2 x 1 + 1 x 2 + 2 x 3 = 10 lC = 5,wCPI = 2.0 - lmplementation 2: clock cycles, = 4 x 1 + 1 x 2 + 1 x 3 = 9 lC = 6,wCPl =1.5 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26", |
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| "CO2007-chapter-1-slide-035-0000": { |
| "id": "CO2007-chapter-1-slide-035-0000", |
| "text": "Exercise A program is executed on a 2 GHz CPU. The program consists of 1000 instructions in which: 30% load/store instructions, CPl = 2.5 10% jump instructions, CPI = 1 20% branch instructions, CPl = 1.5 The rest are arithmetic instructions, CPI = 2.0 a) What is execution time (cPU time) of the program? b) What is the weighted average CPI of the program? c) If load/store instructions are improved so that their execution time is reduced by a factor of 2, what is the speed-up of the system? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27", |
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| "CO2007-chapter-1-slide-036-0000": { |
| "id": "CO2007-chapter-1-slide-036-0000", |
| "text": "Performance summary The BIG picture (take home message) Instructions Clock cycles Seconds CPU time = X X Program Instruction Clock cycle Performance depends on Algorithm: IC, possibly CPI Programming language: IC, CPI Compiler: IC, CPI - Instruction set architecture: IC, CPl, 7 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28", |
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| "CO2007-chapter-1-slide-037-0000": { |
| "id": "CO2007-chapter-1-slide-037-0000", |
| "text": "Power trends In CMOS technology Power(P) = Capacitive load x Voltage2 x Clock rate 10000 120 3600 3900 2667 3300 3400 2000 100 frequency 103 1000 (zHWI) Xouanbau 95 87 80 200 (M) uaM0d 66 77 75.3 100 60 65 25 power 12.5 16 40 29.1 10 10.1 20 4.1 4.9 3.3 1 0 prd p an!suad syekye - (t002) (0022) aip!ie (STOZ) 98Z08 (286T) 98808 (586T) 98t08 (686T) (2661) (266T) (T022) Ccor2 (2222) (1222) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29", |
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| "CO2007-chapter-1-slide-038-0000": { |
| "id": "CO2007-chapter-1-slide-038-0000", |
| "text": "Reducing power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction Cold X 0.85 x (Vold X 0.85)2 x Fold X 0.85 = 0.854 = 0.52 P od Cold x V2 x Fod old The power wall We can't reduce voltage further We can't remove more heat How else can we improve performance? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30", |
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| "CO2007-chapter-1-slide-039-0000": { |
| "id": "CO2007-chapter-1-slide-039-0000", |
| "text": "Multiprocessors 100,000 Intel Xeon 4 cores3.6 GHzBoost to 4.0 Intel Core i7 4 cores 3.4 GHzboost to 3.8 GHz) Intel Xeon 6 cores.3.3 GHzboost to 3.6 GHz 34,967 Intel Xeon 4 cores,3.3 GHzboost to 3.6 GHz) 31.999 Intel Core i7 Extreme 4 cores 3.2 GHzboost to 3.5 GHz 24.129 Intel Core Duo Extreme 2 cores.3.0 GHz 21.871 Intel Core2Extreme 2 cores,2.9 GHz 19.484 AMDAthlon64.2.8GHz 14.387 10,000 AMD Athlon,2.6 GHz 11.865 Intel Xeon EE 3.2 GHz 7.108 Intel D850EMVR motherboard3.06GHz.Pentium 4 processor with Hyper-threading Technology 6.0436,681 IBM Power4.1.3 GHz 4,195 3,016 Intel VC820motherboard,1.0 GHz Pentium Ill processor 1,779 ProfessionalWorkstationXP1000,667MHz 21264A DigitalAlphaServer.8400.6/575..57.5.MHz.21264 1.267 1000 993 AlphaServer 40005/600.600MHz 21164 -649 Digital Alphastation 5/500,500 MHz 481 Digital Alphastation 5/300.300 MHz 280 22%/year Digital Alphastation 4/266,266MHz .183 BM POWERstation100.150 MHz 100 117 Digital3000AXP/500,150MHz 80 HP9000/750,66MHz 51 IBMRS6000/540.30MHz 52%/year 24 MIPSM2000.25MHz 18 MIPSM/120.16.7MHz 10 Sun-4/260,16.7MHz VAX8700.22MHz 5 AX-11/780.5MHz 25%/year 1.5.VAX-11/785 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010", |
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| "CO2007-chapter-1-slide-039-0001": { |
| "id": "CO2007-chapter-1-slide-039-0001", |
| "text": "1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 31", |
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| "id": "CO2007-chapter-1-slide-040-0000", |
| "text": "Benchmark Programs used to measure performance - Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC - Develops benchmarks for CPU, I/O, Web, ... SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 32", |
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| "CO2007-chapter-1-slide-041-0000": { |
| "id": "CO2007-chapter-1-slide-041-0000", |
| "text": "Example Intel core i7 920 results with CINT 2006 Executlon Reference Instruction Clock cycle tlme TIme TIme Descrlptlon Name Count x 109 CPI (seconds x 1o-9) (seconds) (seconds) SPECratlo Interpreted string processing perl 2252 0.60 0.376 508 9770 19.2 Block-sorting bzip2 2390 0.70 0.376 629 9650 15.4 compression GNU C compiler gcc 794 1.20 0.376 358 8050 22.5 Combinatorial optimization mcf 221 2.66 0.376 221 9120 41.2 Go game (Al) go 1274 1.10 0.376 527 10490 19.9 Search gene sequence hmmer 2616 0.60 0.376 590 9330 15.8 Chess game (Al) sjeng 1948 0.80 0.376 586 12100 20.7 Quantum computer libquantum 659 0.44 0.376 109 20720 190.0 simulation Video compression h264avc 3793 0.50 0.376 713 22130 31.0 Discrete event omnetpp 367 2.10 0.376 290 6250 21.5 simulation library Games/path finding astar 1250 1.00 0.376 470 7020 14.9 XML parsing xalancbmk 1045 0.70 0.376 275 6900 25.1 Geometric mean - - - - - - 25.7 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 33", |
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| "CO2007-chapter-1-slide-042-0000": { |
| "id": "CO2007-chapter-1-slide-042-0000", |
| "text": "Concluding remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture - The hardware/software interface Execution time: the best performance measure Power is a limiting factor - Use parallelism to improve performance BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 34", |
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| "CO2007-chapter-2-slide-043-0000": { |
| "id": "CO2007-chapter-2-slide-043-0000", |
| "text": "COMPUTER ARCHITECTURE Chapter 2: Instruction set architecture - ISA Pham Quöc Cuö'ng BK Computer Engineering - CSE - HCMUT TP.HCM", |
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| "timestamp": "2025-10-30T22:28:33+07:00" |
| } |
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| "CO2007-chapter-2-slide-044-0000": { |
| "id": "CO2007-chapter-2-slide-044-0000", |
| "text": "Languages of Computer? Why? Q: Why do we need to learn the language of computers? A: To command a computer's hardware: speak its language BevansiaTTeRy 0110010110 CaLS for CompUTER 0111000110110 C0De toBe a Key 100110101010001 LanguaGeTavgHl 00101000100101 at SCHoOLu 010111001000101 1011001010110 100110010101 010010101 Source: http://media.apnarm.net.au/img/media/images/2013/08/14/computer_language_t620.jpg BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_002.png", |
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| "CO2007-chapter-2-slide-045-0000": { |
| "id": "CO2007-chapter-2-slide-045-0000", |
| "text": "Abstraction We teach students how to use abstraction so that we can build really complex software systems. John Hennessy ACM A.M.Turing Laureate acm BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3", |
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| } |
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| "CO2007-chapter-2-slide-046-0000": { |
| "id": "CO2007-chapter-2-slide-046-0000", |
| "text": "Instruction set architecture software instruction set architecture hardware MIPS32 Add Immediate Instruction 001000 0000100010 0000000101011110 OP CodeAddr 1Addr 2 Immediate value Equivalent mnemonic: addi Sr1,Sr2,350 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4", |
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| "CO2007-chapter-2-slide-047-0000": { |
| "id": "CO2007-chapter-2-slide-047-0000", |
| "text": "Von Neumann architecture Stored-program concept Central Processing Unit (CPU) Instruction category: Arithmetic Arithmetic- logic Data transfer 1 unit (CA) Logical 1/0 Main Equip- memory Conditional branch ment (M) (I, 0) Unconditional jump Program control unit (CC) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_005.png", |
| "page_index": 47, |
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| "CO2007-chapter-2-slide-048-0000": { |
| "id": "CO2007-chapter-2-slide-048-0000", |
| "text": "Computer components CPU Main memory 0 System 1 bus 2 PC MAR . Instruction . Instruction Instruction IR MBR . I/O AR . Data Execution Data unit I/O BR Data Data I/O Module n - 2 n - 1 . PC = Program counter . IR = Instruction register Buffers MAR = Memory address register MBR = Memory buffer register I/O AR = Input/output address register I/O BR = Input/output buffer register BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6", |
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| "CO2007-chapter-2-slide-049-0000": { |
| "id": "CO2007-chapter-2-slide-049-0000", |
| "text": "Instruction execution model Fetch cycle Execute cycle Fetch next Execute START HALT instruction instruction Instruction fetch: from the memory - PC increased PC stores address of the next instruction Execution: decode and execute BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7", |
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| "CO2007-chapter-2-slide-050-0000": { |
| "id": "CO2007-chapter-2-slide-050-0000", |
| "text": "STANDARDI MIPS INSTRUCTIONS BK TP.HCM 8", |
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| "CO2007-chapter-2-slide-051-0000": { |
| "id": "CO2007-chapter-2-slide-051-0000", |
| "text": "MlPS instruction set MIpS architecture MIPS Assembly Instruction > MIPS Machine Instruction Assembly: - add $tO,$s2,$t0 Machine: - 000000 10010 01000 01000 00000 100000 Only one operation is performed per MiPs instruction - e.g., a + b + c needs at least two instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9", |
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| "CO2007-chapter-2-slide-052-0000": { |
| "id": "CO2007-chapter-2-slide-052-0000", |
| "text": "Instruction set design principle Simplicity favors regularity Smaller is faster Make the common case fast Good design demands good compromises BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10", |
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| "CO2007-chapter-2-slide-053-0000": { |
| "id": "CO2007-chapter-2-slide-053-0000", |
| "text": "MIPS operands 1. Register: 32 32-bit registers (start with the $ sign) - $sO-$s7: corresponding to variables (save) - $t0-$t9: storing temporary value - $a0-$a3 - $vO-$v1 - $gp,$fp,$sp,$ra,$at,$zero,$kO-$k1 only by data transfer instructions 3. Short integer immediate: -10, 20, 2020,... Only three operand types! Nothing else! BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 11", |
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| "CO2007-chapter-2-slide-054-0000": { |
| "id": "CO2007-chapter-2-slide-054-0000", |
| "text": "group: arithmetic instructions Assembly instruction format: Destination Source Source Opcode register register 1 register 2(*) Opcode: - add:DR=SR1+ SR2 - sub:DR =SR1-SR2 - addi: (*) SR2 is an immediate (e.g. 2O), DR = SR1 + SR2 Three register operands BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12", |
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| "CO2007-chapter-2-slide-055-0000": { |
| "id": "CO2007-chapter-2-slide-055-0000", |
| "text": "Example Question: what is MIPS code for the following C code f = (g + h) - (i + j): If the variables g, h, i, j, and f are assigned to the register $sO,$s1, $s2,$s3, and $s4, respectively. Answer: add$tO,$sO,$s1# g + h add $sO,$sO,$s1 add $t1,$s2,$s3 # i+ j add $s1,$s2,$s3 sub $s4,$tO,$t1 # tO-t1 sub $s4,$s0,$s1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13", |
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| "id": "CO2007-chapter-2-slide-056-0000", |
| "text": "2nd group: data transfer instructions Copy data b/w memory Memory and registers in CPU Register read addr/ write addr Address: a value used to Processor read data delineate the location of a write data specific data element 10 8 within a memory array 101 4 1 0 Load (l): copy data from Data 32 bits memory to a register Store (s): copy data from a Address register to memory BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14", |
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| "id": "CO2007-chapter-2-slide-057-0000", |
| "text": "Data transfer instructions Assembly instruction format: Memory Opcode Register operand Opcode: Size of data: 1 byte, 2 bytes (half of word), or 4 bytes (word) Behaviors: load or store Register: Load: destination - Store: source Memory operand: offset(base register) - offset: short integer number Byte address: each address identifies an 8-bit byte \"words\" are aligned in memory (address must be multiple of 4) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 15", |
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| "CO2007-chapter-2-slide-058-0000": { |
| "id": "CO2007-chapter-2-slide-058-0000", |
| "text": "Memory address = < offset > + value( < base register > ) Question: given the following memory map, assume that $sO stores value of 8. Which is the memory operand used to access the byte storing value of Ox9A? address: 8 9 10 11 0x12 0x34 0x56 0x78 0x9A 0xBC 0xDE 0xF0 Answer: address:l 12 13 14 15 Address of the byte storing value of 0x9A is 12 - If we use $sO as the base register, offset = 12 - 8 = 4 - Memory operand: 4($s0) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16", |
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| "CO2007-chapter-2-slide-059-0000": { |
| "id": "CO2007-chapter-2-slide-059-0000", |
| "text": "Load instructions Remind: \"load\" means copying data from memory to a 32-bit register Instructions: Iw: load word eg.: Iw $s0,100($s1) #copy 4 bytes from memory to $s0 lh: load half - sign extended eg.: Ih $sO,10O($s1) #copy 2 bytes to $s0 and extend signed bit Ihu: load half unsigned - zero extended - Ib: load byte - sign extended - Ibu: load byte unsigned - zero extended - Special case: lui - load upper immediate eg.:lui $s0,0x1234 #$s0 = 0x12340000 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 17", |
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| "CO2007-chapter-2-slide-060-0000": { |
| "id": "CO2007-chapter-2-slide-060-0000", |
| "text": "Store instructions Remind: \"store\" means copying data from a register to memory Instructions: - sw: store word $s0,100($s1) #copy 4 bytes in $s0 to memory eg.: sw sh: store half - two least significant bytes eg.:sh $s0,100($s1) #copy 2 bytes in $s0 to memory sb: store byte - the least significant byte eg.: sb $s0,100($s1) #copy 1 bytes in $s0 to memory BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_018.png", |
| "page_index": 60, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:23+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-061-0000": { |
| "id": "CO2007-chapter-2-slide-061-0000", |
| "text": "Main memory used for composite data - Arrays, structures, dynamic data To apply arithmetic operations - Load value(s) from memory into register(s) Apply arithmetic operations to the register(s) Store result from a register to memory (if required) MIPS is Big Endian - Most-significant byte at least address of a word Little Endian: least-significant byte at least address BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_019.png", |
| "page_index": 61, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:26+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-062-0000": { |
| "id": "CO2007-chapter-2-slide-062-0000", |
| "text": "Example-1 C code: g = h + A[8]; - g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw $tO,32($s3 # load word add $s1,$s2,$t0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_020.png", |
| "page_index": 62, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:29+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-063-0000": { |
| "id": "CO2007-chapter-2-slide-063-0000", |
| "text": "Example-2 C code: A[12] = h + A[8] - h in $s2,base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 Iw $tO,32($s3) # load word add $tO,$s2,$tO $t0,48($s3) # store word SW BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_021.png", |
| "page_index": 63, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:31+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-064-0000": { |
| "id": "CO2007-chapter-2-slide-064-0000", |
| "text": "Exercises 1. Given the following memory map, assume that the register $tO stores value 8 while $sO contains 0xCAFEFACE. Show the effects on memory and registers of following instructions: a) Iw $t1,O($tO) address: 8 9 10 11 b) Iw $t2,4($tO) 0x12 0x34 0x56 0x78 c) Ih $t6,4($tO) 0x9A 0xBC 0xDE 0xF0 d) Ib $t5,3($tO) address: 12 13 14 15 e) sw $sO,O($tO) f) sb $sO,4($tO) g) Ih $sO,7($tO) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_022.png", |
| "page_index": 64, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:35+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-065-0000": { |
| "id": "CO2007-chapter-2-slide-065-0000", |
| "text": "Exercises 2. Convert the following C statements to equivalent MIPs assembly language if the variables f, g, and h are assigned to registers $sO, $s1, and $s2 respectively. Assume that the base address of the array A and B are in registers $s6 and $s7, respectively. a) f=g+h+ B[4] b) f = g- A[B[4]] BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_023.png", |
| "page_index": 65, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:37+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-066-0000": { |
| "id": "CO2007-chapter-2-slide-066-0000", |
| "text": "3rd group: logical instructions Instruction format: the same with arithmetic instructions Bitwise manipulation - Process operands bit by bit Operation C operator MIPS opcode Shift left << sll Shift right >> srl Bitwise AND & and, andi Bitwise OR or, ori Bitwise NOT nor BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_024.png", |
| "page_index": 66, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:40+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-067-0000": { |
| "id": "CO2007-chapter-2-slide-067-0000", |
| "text": "Shift operations Shift left (sll) Shift value in the first source to left and fill least significant positions With 0 bits - e.g.,s11 $sO,$s1,4 #$s0 = $s1<< 4 - Special case: sll by i bits multiplies by 2 Shift right (srl) Shift value in the first source to right and fill most significant positions With 0 bits - e.g.,sr1 $s0,$s1,4 # $s0= $s1>>4 - Special case: srl by i bits divides by 2' (unsigned number only) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_025.png", |
| "page_index": 67, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:43+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-068-0000": { |
| "id": "CO2007-chapter-2-slide-068-0000", |
| "text": "AND operation $s1(32 bit Bitwise AND two source operands 0 (16b) 100 (16b) - and: two source registers e.g.,and $sO,$s1,$s2 #$s0=$s1 & $s2 - andi: the second source is a short integer number (16 bit) 16 high-significant bits of the result are 0s e.g.,andi $s0,$s1,100 #$s0 ={16'b0,$s1[15:0]&100} Useful to mask bits in a register Select some bits and clear others to 0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_026.png", |
| "page_index": 68, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:46+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-069-0000": { |
| "id": "CO2007-chapter-2-slide-069-0000", |
| "text": "OR operation Bitwise OR two source operands - or: two registers e.g.,or $s0,$s1,$s2 #$s0=$s1$s2 - ori: the second source is a short integer number (16 bit Copy 16 high-significant bit from the first source to destination e.g.,ori $s0,$s1,100 #$s0 ={$s1[31:16]$s1[15:0]100} Useful to include bits in a word Set some bits to 1, leave others unchanged BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_027.png", |
| "page_index": 69, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:49+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-070-0000": { |
| "id": "CO2007-chapter-2-slide-070-0000", |
| "text": "NOT operation Don't have a not instruction in MIPS ISA - 2-operand instruction Useful to invert all bits in a register Can be done by the nor operator, 3-operand instruction - a NOR b= NOT (a OR b) NOT a = NOT(a OR 0) = a NOR 0 - e.g.,nor $sO,$sO,$zero - What else? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_028.png", |
| "page_index": 70, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:51+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-071-0000": { |
| "id": "CO2007-chapter-2-slide-071-0000", |
| "text": "Example Question: assume that $s0 and $s1 are storing values 0x12345678 and OxCAFEFACE, respectively. What is value of $S2 after each following instructions 1.s1l $s2,$s0,4 2.and $s2,$s0,$s1 3.or $s2,$s0,$s1 4.andi $s2,$s0,2020 Answer: 1.0x23456780 2.0x02345248 3.0xDAFEFEFE 4. 0x00000660 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_029.png", |
| "page_index": 71, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:54+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-072-0000": { |
| "id": "CO2007-chapter-2-slide-072-0000", |
| "text": "Exercise Find the value for $t2 after each following sequence of instructions if the values for register $tO and $t1 are a) $tO = OxAAAAAAAA,$t1 = Ox12345678 b) $tO = OxFOODDOOD,$t1 = Ox11111111 Sequence 1: Sequence 2: Sequence 3: sll $t2,$tO,44 s1I $t2,$tO,4 srl $t2,$t0,3 or $t2,$t2,$t1 andi $t2,$t2,-2 andi$t2,$t2,OxFFEF BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_030.png", |
| "page_index": 72, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:29:56+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-073-0000": { |
| "id": "CO2007-chapter-2-slide-073-0000", |
| "text": "4th group: conditional branch instructions Branch to a label if a condition is True true; otherwise, continue Condition? sequentially Only two standard conditional False branch instructions Instruction with next instruction beq $rs,$rt, L1 #branch if a label equal . If (rs == rt), go to L1 addi $tO, $zero,0 - bne $rs, $rt, L1 addi $t1, $zero, 5 If(rs != rt),go to L1 L1: addi $tO,$tO,1 Label: a given name bne $tO,$t1,L1 #branch to L1 add $tO,$t1,$t0 - format: <label>: <instruction> BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 31", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_031.png", |
| "page_index": 73, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:00+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-074-0000": { |
| "id": "CO2007-chapter-2-slide-074-0000", |
| "text": "Sth group: unconditional jump instructions Immediately jump to a label Without any condition checked Three standard unconditional jumps - j<label> . Jump to the label, e.g., L1 - jal<label> Jump to the label L1 and store address of the next instruction to the $ra register Used for function/procedure call jr $register Jump to an instruction whose address is stored in the register Used for returning to the caller function/procedure from a sub-function/- procedure BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 32", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_032.png", |
| "page_index": 74, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:03+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-075-0000": { |
| "id": "CO2007-chapter-2-slide-075-0000", |
| "text": "Example Question: Compile the following C code into MIPS code (assume that f, g, h, i and j are stored in registers from $sO to $s4, respectively) if (i == j) f = g + h; else f = g - h; Answer: bne $s3,$s4,Else beq $s3,$s4,If add $sO,$s1,$s2 sub $s0,$s1,$s2 j Exit j Exit Else: sub $s0,$s1,$s2 If: c add $sO,$s1,$s2 Exit: Exit: How can we compare less than or greater than? - e.g., if (a< b) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 33", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_033.png", |
| "page_index": 75, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:06+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-076-0000": { |
| "id": "CO2007-chapter-2-slide-076-0000", |
| "text": "Exercise Convert the following C code to MIPS. Assume that the base address of the save array is stored in $sO while i and k are stored in the registers $s1 and $s2, respectively int save[]j int i, kj i = 0: while (save[i]== k i += 1: BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 34", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_034.png", |
| "page_index": 76, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:09+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-077-0000": { |
| "id": "CO2007-chapter-2-slide-077-0000", |
| "text": "Set-on-less-than instruction Used for comparing less than or greater than Results (destination registers) are always 0 (false) or 1 (true) slt $rd,$rs, $rt - if (rs< rt) rd = 1; else rd = 0; slti $rt, $rs, immediate - if (rs < immediate) rt = 1; else rt = 0; sltu $rd, $rs, $rt Values are unsigned numbers sltui $rt, $rs, immediate Values in registers & immediate are unsigned numbers BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 35", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_035.png", |
| "page_index": 77, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:12+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-078-0000": { |
| "id": "CO2007-chapter-2-slide-078-0000", |
| "text": "Example-1 Question: Assume that values storing in $s1 and $s2 are 0xFFFFFFFF and Ox00000001,respectively. What are the results in $tO and $t1 after the following instructions slt $tO,$s1,$s2 sltu $t1,$s1,$s2 Answer: - $t1 = 0 due to unsigned numbers comparison ($s1 = 4.294.967.295) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 36", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_036.png", |
| "page_index": 78, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:14+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-079-0000": { |
| "id": "CO2007-chapter-2-slide-079-0000", |
| "text": "Example-2 Question: Compile the following C code into MIPS code (assume that f, g, h, i, and j are stored in registers from $sO to $s4, respectively) if (i<j) f=g+ h; else f = g - h; Answer: slt $tO,$s3,$s4 s1t $tO,$s3,$s4 beq $tO,$zero, Else bne $tO, $zero,If add $sO,$s1,$s2 sub $s0,$s1,$s2 j Exit j Exit Else: sub $sO,$s1,$s2 If: c add $s0,$s1,$s2 Exit: Exit: BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 37", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_037.png", |
| "page_index": 79, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:17+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-080-0000": { |
| "id": "CO2007-chapter-2-slide-080-0000", |
| "text": "Exercise Convert the following C code to MIPS instructions a) Sequence 1: int a, b: if (a>= 5) a = a + b; else a = a - b: b) Sequence 2: int a, i: for (i = 0, a = 0: i < 10: i++) a++: BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 38", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_038.png", |
| "page_index": 80, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:19+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-081-0000": { |
| "id": "CO2007-chapter-2-slide-081-0000", |
| "text": "Branch instruction design Why not blt, bge, etc? Hardware for <, -, ... slower than =, - Combining with branch involves more work per instruction requiring a slower clock - All instructions penalized! beq and bne are the common case This is a good design compromise BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 39", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_039.png", |
| "page_index": 81, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:22+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-082-0000": { |
| "id": "CO2007-chapter-2-slide-082-0000", |
| "text": "Pseudo instructions Most assembler instructions represent machine instructions one-to-one Pseudo instructions (instructions in blue): figments of the assembler's imagination Help programmer - Need to be converted into standard instructions For example - move $tO,$t1 -> add $tO,$zero,$t1 - blt $tO,$t1,L -> s1t $at,$tO,$t1 bne $at, $zero, L BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 40", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_040.png", |
| "page_index": 82, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:25+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-083-0000": { |
| "id": "CO2007-chapter-2-slide-083-0000", |
| "text": "PROCEDURE CALL BK TP.HCM 41", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_041.png", |
| "page_index": 83, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:26+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-084-0000": { |
| "id": "CO2007-chapter-2-slide-084-0000", |
| "text": "Procedure calling Caller vs. Callee int mainO{ /7 caller ..(1) Steps required to call a procedure fact(4): - Place parameters in registers ..(.2) fact(1000) Transfer control to procedure Acquire storage for procedure Perform procedure's operations int fact(int a){ //callee Place result in register for caller Return to place of call BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 42", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_042.png", |
| "page_index": 84, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:29+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-085-0000": { |
| "id": "CO2007-chapter-2-slide-085-0000", |
| "text": "Register usage $a0 - $a3: arguments $gp: global pointer for static data $vO,$v1: result values $sp: stack pointer $t0 - $t9: temporaries $fp: frame pointer Can be overwritten by callee $ra: return address $s0 - $s7: saved Must be saved/restored by callee BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 43", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_043.png", |
| "page_index": 85, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:32+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-086-0000": { |
| "id": "CO2007-chapter-2-slide-086-0000", |
| "text": "Stack addressing model High address $sp $sp - $sp - Low address Empty stack Three elements stack Empty stack BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 44", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_044.png", |
| "page_index": 86, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:34+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-087-0000": { |
| "id": "CO2007-chapter-2-slide-087-0000", |
| "text": "Procedure call instructions Procedure call: jump and link jal ProcedureLabel - Address of following instruction put in $ra - Jumps to target address Procedure return: jump register jr $ra - Copies $ra to program counter Can also be used for computed jumps e.g., for case/switch statements BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 45", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_045.png", |
| "page_index": 87, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:37+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-088-0000": { |
| "id": "CO2007-chapter-2-slide-088-0000", |
| "text": "Leaf procedure Leaf-procedure: will not call any sub-procedure or itself - No need to care any else, except saved registers C code: int leaf_example (int g, h, i, j)} int f: f = (g + h) - (i + j) return f: - Arguments g, ..., in $aO, .., $a3 - f in $sO (hence, need to save $sO on stack) - Result in $vO BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 46", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_046.png", |
| "page_index": 88, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:39+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-089-0000": { |
| "id": "CO2007-chapter-2-slide-089-0000", |
| "text": "Main: add Leaf procedure - MIPS code sub jal leaf_example bne # addr =>$ra leaf_example: Label procedure name (used to call) addi $sp,$sp,-4 Save $sO to the stack $s0,0($sp) SW add $tO,$aO,$a1 add $t1,$a2,$a3 Procedure body sub $sO,$tO,$t1 add $vO,$sO,$zero Result Iw $sO,O($sp) Restore $s0 addi $sp,$sp,4 jr $ra Return to caller BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 47", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_047.png", |
| "page_index": 89, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:43+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-090-0000": { |
| "id": "CO2007-chapter-2-slide-090-0000", |
| "text": "Non-leaf procedure Non-leaf procedure: will call at least an other procedure or itself - Need to care: Return address ($ra) (always!!!) Caller call A ($ra = caller: address of the instruction after jal A) A call B ($ra = A: address of the instruction after jal B) Overwrite the value of $ra B return to A ($ra = A) Cannot return to Caller Arguments transferred from Caller if needed (sometimes!!! Use the stack to backup BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 48", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_048.png", |
| "page_index": 90, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:45+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-091-0000": { |
| "id": "CO2007-chapter-2-slide-091-0000", |
| "text": "Non-leaf procedure - example Factorial calculation C code int fact (int n){ if (n< 1) return 1: else return n * fact(n - 1): - Argument n in $a0 Result in $vO BK TP.HCM 49 Computer Architecture (c) Cuong Pham-Quoc/HCMUT", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_049.png", |
| "page_index": 91, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:48+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-092-0000": { |
| "id": "CO2007-chapter-2-slide-092-0000", |
| "text": "Non-leaf procedure - MIPS code fact: addi $sp, $sp, -8 # adjust stack for 2 items $ra,4($sp) sW # save return address No recursive call $a0,0($sp) sW # save argument - No change in $aO & slti $tO,$aO,1 # test for n< 1 $ra beq $tO,$zero,L1 No need to restore addi $vO,$zero,1 # if so, result is 1 from stack addi $sp,$sp,8 # t pop 2 items from stack jr $ra # c and return L1: addi $aO, $aO, -1 # else decrement n jal fact # recursive call Iw $aO,O($sp) # restore original n Recursive call Iw $ra,4($sp) # and return address addi $sp,$sp,8 # pop 2 items from stack muI $vO,$aO,$vO # multiply to get result jr $ra # and return BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 50", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_050.png", |
| "page_index": 92, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:53+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-093-0000": { |
| "id": "CO2007-chapter-2-slide-093-0000", |
| "text": "Exercise Write corresponding MIPS code for the following function void strcpy (char x[],char y[]){ int i: i = 0: while ((x[i]=y[i])!='0' i += 1: - Addresses of x, y in $aO,$a1 - i in$sO Ascii code ofO' is 0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 51", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_051.png", |
| "page_index": 93, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:56+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-094-0000": { |
| "id": "CO2007-chapter-2-slide-094-0000", |
| "text": "MACHINE INSTRUCTIONS BK TP.HCM 52", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_052.png", |
| "page_index": 94, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:30:57+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-095-0000": { |
| "id": "CO2007-chapter-2-slide-095-0000", |
| "text": "Machine instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words - Small number of formats encoding operation code (opcode), register numbers, .. - Regularity! Representing instructions: Instruction format: R, I, and J Opcode: predefined (check the reference card) Operands: Register numbers: predefined (check the reference card) Immediate: integer to binary Memory operands: offset + base register BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 53", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_053.png", |
| "page_index": 95, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:00+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-096-0000": { |
| "id": "CO2007-chapter-2-slide-096-0000", |
| "text": "Instruction formats MIPS machine instructions use one of three formats R-format: encoding all-register-operands instructions and two shift instructions add $s0,$s1, $s2 # all operand are registers sll $sO,$s1,4 # shift instruction I-format: encoding instructions with one operand different from registers except: sll, srl, j, and jal addi $s0, $s1,100 #immediate lw $s1,100($s0) #memory operand - J-format: encoding j and jal j Label1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 54", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_054.png", |
| "page_index": 96, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:04+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-097-0000": { |
| "id": "CO2007-chapter-2-slide-097-0000", |
| "text": "R-format instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op: always 0 for R-format instructions - 6 bits for all formats rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (0 for non-shift instructions) funct: identify operators BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 55", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_055.png", |
| "page_index": 97, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:07+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-098-0000": { |
| "id": "CO2007-chapter-2-slide-098-0000", |
| "text": "Register numbers & some function fields Register Number Register Number Register Number $zero 0 $t0-$t7 8-15 $gp 28 $at 1 $s0-$s7 16-23 $sp 29 $v0-$v1 $+8-$+9 $fp 2-3 24-25 30 $a0-$a3 $k0-$k1 $ra 3 4-7 26-27 31 Instruction Function field Instruction Function field add 0x20 (32) sub 0x22 (34) and 0x24 (36) 0x25 (37) or 0x28 (39) jr 0x08 (8) nor sll 0x00 (0) srl Ox02 (2) slt 0x2A(42) sltu 0x2B (43) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 56", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_056.png", |
| "page_index": 98, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:12+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-099-0000": { |
| "id": "CO2007-chapter-2-slide-099-0000", |
| "text": "Example-1 Question: what is machine code of following instruction add $tO,$s1,$s2 T T Answer: rd rs rt - R-format is used to encode the above instruction 0 17 18 8 0 32 000000 10001 10010 01000 00000 100000 Machine code: 0x02324020 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 57", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_057.png", |
| "page_index": 99, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:15+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-100-0000": { |
| "id": "CO2007-chapter-2-slide-100-0000", |
| "text": "Example-2 Question: what is the assembly instruction of the following MIPS machine code 0000_0000_0001_0000_0101_0001_0000_0000 Answer: - Opcode (the 6 high-significant bits) is 0 => an R-format instruction 000000 00000 10000 01010 00100 000000 - Function field is 0 = a sll instruction - The assembly instruction: sll $t2, $sO, 4 Note: shift instructions don't use the rs field BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 58", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_058.png", |
| "page_index": 100, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:18+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-101-0000": { |
| "id": "CO2007-chapter-2-slide-101-0000", |
| "text": "MlPS I-format Instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits op: specific values for instructions beq $s0,$s1,L1 rs: source or base address register (no destination) - First source register in 2 source register instructions rt: source or destination register Second source register in 2 source register instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 59", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_059.png", |
| "page_index": 101, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:20+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-102-0000": { |
| "id": "CO2007-chapter-2-slide-102-0000", |
| "text": "Some opcode fields Instruction Opcode field Instruction Opcode field addi 0x08 (8) addiu 0x09 (9) Ibu 0x24 (36) lhu 0x25 (37) Ib 0x20 (32) Ih 0x21 (33) Iw 0x23 (35) 0x2B (43) sW sb 0x28 (40) sh 0x29 (41) slti 0x0A (10) sltiu Ox0B (11) andi OxOC (12) ori 0x0D (13) beq 0x04 (4) bne 0x05 (5) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 60", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_060.png", |
| "page_index": 102, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:25+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-103-0000": { |
| "id": "CO2007-chapter-2-slide-103-0000", |
| "text": "Example-1 Question: what is machine code of following instruction lw$tO,32($s3) T T Answer: rt (destination) rs (base register) I-format is used to encode the above instruction 35 19 8 32 100011 10011 01000 0000 0000 0010 0000 Machine code: 0x8E680020 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 61", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_061.png", |
| "page_index": 103, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:28+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-104-0000": { |
| "id": "CO2007-chapter-2-slide-104-0000", |
| "text": "Example-2 Question: what is the assembly instruction of the following MIPS machine code 1010 1101 0010 1000 0000 0000 0110 0100 Answer: - Opcode 0 (not j and jal) => an I-format 101011 01001 01000 0000 0000 0110 0100 Opcode = 101011 => sw instruction - The assembly instruction: sw $t0, 100($t1) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 62", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_062.png", |
| "page_index": 104, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:30+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-105-0000": { |
| "id": "CO2007-chapter-2-slide-105-0000", |
| "text": "Exercise Write MIPS code for the following C code, then translate the MIPS code to machine code. Assume that $t1 stores the base of array A (array of integers) and $s2 stores h int A[301] int h: A[300] = h + A[300]- 2: BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 63", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_063.png", |
| "page_index": 105, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:32+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-106-0000": { |
| "id": "CO2007-chapter-2-slide-106-0000", |
| "text": "Branch & jump addressing Question: how can we represent labels in conditional branch and unconditional jump instructions? Answer: use addressing methods Cannot representing label names Calculate distance between the current instruction to the label PC-relative addressing (Pseudo) direct addressing BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 64", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_064.png", |
| "page_index": 106, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:35+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-107-0000": { |
| "id": "CO2007-chapter-2-slide-107-0000", |
| "text": "PC-relative addressing Use for encoding bne and beg instructions Target address (the instruction associated with the label) calculated based on Pc - program counter register PC is already increased by 4 target address = PC + address field x 4 When encoding branch conditional instructions, address field should be calculated by target address - PC address field = 4 The number of instructions from PC to the label BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 65", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_065.png", |
| "page_index": 107, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:37+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-108-0000": { |
| "id": "CO2007-chapter-2-slide-108-0000", |
| "text": "Example-1 Question: given the following MIPS code, what is the machine code for the conditional branch instruction? bne $s3,$s4,Else <- X add $sO,$s1,$s2 j Exit Else: sub $sO,$s1,$s2 <- X + 12 Answer: Exit: I-format is used - Assume that the bne instruction is stored at address x PC = x + 4 when processing the bne instruction (x +12) -(x +4) = 2 target address = x + 12 => address field = 4 5 19 20 2 Machine code: 0x16740002 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 66", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_066.png", |
| "page_index": 108, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:42+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-109-0000": { |
| "id": "CO2007-chapter-2-slide-109-0000", |
| "text": "Example-2 Question: given the following MIPS code, what is the machine code for the conditional branch instruction? Label: addi $tO, $tO,-1 bne $tO,$t1,Label <- X add $tO,$tO,$s1 Answer: I-format is used Assume that the bne instruction is stored at address x PC = x + 4 when processing the bne instruction (x - 4) -(x +4) target address = x - 4 => address field = - 2 4 5 8 9 -2 16-bit 2's complement Machine code: Ox1611FFFE BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 67", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_067.png", |
| "page_index": 109, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:45+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-110-0000": { |
| "id": "CO2007-chapter-2-slide-110-0000", |
| "text": "J-format instructions PC-relative and I-format not good enough op address 6 bits 26 bits J-format is used for j and jal instructions only - opcode: 2 for j; 3 for jal address: used for calculate target address of jump instructions target address = {Pc[31 : 28],address[25 : 0],002} Need full address of instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 68", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_068.png", |
| "page_index": 110, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:31:48+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-111-0000": { |
| "id": "CO2007-chapter-2-slide-111-0000", |
| "text": "Example Question: given the following MIPS code, what is the machine code for the unconditional jump instruction if the first instruction is stored at memory location 80000? Label: addi $tO,$tO,-1 bne$tO,$t1,Exit j Label Exit: Answer: J-format is used PC = 80012 when processing the j instruction => PC[31 : 28] = 0000 target address = 80000 = {00002,address field,002} 80000 - address field = = 20000 4 2 20000 - Machine code: 0x08004E20 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 69", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_069.png", |
| "page_index": 111, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:31:52+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-112-0000": { |
| "id": "CO2007-chapter-2-slide-112-0000", |
| "text": "Exercise Decide the machine code of the following sequence. Assume that the first instruction (start label) is stored at memory address OxFC00O00C 0xFC00000C start: add $sO,$s1,$s2 0xFC000010 loop: addi$tO,$tO,-1 sw $tO,4($t2) 0xFC000014 bne $tO,$t3,loop 0xFC000018 j start 0xFC00001C BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 70", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_070.png", |
| "page_index": 112, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:31:54+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-113-0000": { |
| "id": "CO2007-chapter-2-slide-113-0000", |
| "text": "Branching far-away If branch target is too far to encode with 16-bit offset, assembler rewrites the code Example beq $s0,$s1,L1 bne$sO,$s1,L2 j L1 L2: BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 71", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_071.png", |
| "page_index": 113, |
| "language": "en", |
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| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:31:56+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-114-0000": { |
| "id": "CO2007-chapter-2-slide-114-0000", |
| "text": "Summary MIPS ISA - 3 types of operands - 5 groups of instructions Procedure call Machine code - 3 formats Addressing methods BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 72", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_072.png", |
| "page_index": 114, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:31:58+07:00" |
| } |
| }, |
| "CO2007-chapter-2-slide-115-0000": { |
| "id": "CO2007-chapter-2-slide-115-0000", |
| "text": "The end Computer Engineering - CSE - HCMUT BK 73 TP.HCM", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_073.png", |
| "page_index": 115, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:01+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-116-0000": { |
| "id": "CO2007-chapter-3-slide-116-0000", |
| "text": "COMPUTER ARCHITECTURE Chapter 3: Computer arithmetic BK Computer Engineering - CSE - HCMUT 1 TP.HCM", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_001.png", |
| "page_index": 116, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:04+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-117-0000": { |
| "id": "CO2007-chapter-3-slide-117-0000", |
| "text": "Outline Integer operations - Addition and subtraction Multiplication and division Floating-point numbers Representation Operations and instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_002.png", |
| "page_index": 117, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:06+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-118-0000": { |
| "id": "CO2007-chapter-3-slide-118-0000", |
| "text": "INTEGER OPERATIONS BK TP.HCM 3", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_003.png", |
| "page_index": 118, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:07+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-119-0000": { |
| "id": "CO2007-chapter-3-slide-119-0000", |
| "text": "Integer addition (0) (0) (1) (1) (0) (Carries 0 0 0 1 1 1 0 0 0 1 1 0 (0) 0 (0) 0 (0) (1 1) (1) 0 (0) 1 Example: 710 + 610 = 01112 + 01102 Overflow: result out of range - Adding +ve and -ve operands, no overflow Adding two +ve operands . Overflow if result sign is 1 Adding two -ve operands Overflow if result sign is 0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_004.png", |
| "page_index": 119, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:12+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-120-0000": { |
| "id": "CO2007-chapter-3-slide-120-0000", |
| "text": "Integer subtraction Add negation (2's complement) of the second operand Example: 7 - 6 = 7 + (-6) = 01112 + 10102 = 00012 Overflow if result out of range Subtracting two +ve or two -ve operands, no overflow - Subtracting +ve from -ve operand: -7 - 6 Overflow if result sign is 0 Subtracting -ve from +ve operand: 7 - (-6) Overflow if result sign is 1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_005.png", |
| "page_index": 120, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:15+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-121-0000": { |
| "id": "CO2007-chapter-3-slide-121-0000", |
| "text": "Deal with Overflow Some languages (e.g., C) ignore overflow - Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPs add, addi, sub instructions - On overflow, invoke exception handler (hardware) Save PC in exception program counter (EPC) register Jump to predefined handler address mfcO (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_006.png", |
| "page_index": 121, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:18+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-122-0000": { |
| "id": "CO2007-chapter-3-slide-122-0000", |
| "text": "Hardware for multiplication Multiplicand multiplicand Shift left 1000 64 bits multiplier x 1001 1000 Multiplier 0000 64-bit ALU Shift right 0000 32 bits 1000 Product Control test product 1001000 Write 64 bits Length of product is the sum of operand lengths BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_007.png", |
| "page_index": 122, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:21+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-123-0000": { |
| "id": "CO2007-chapter-3-slide-123-0000", |
| "text": "Hardware operation Start m0 = 1 m0 = 0 1. m0? Multiplicand Shift left 64 bits 1a. Accumulate multiplicand to product Multiplier 64-bit ALU Shift right 32 bits 2. Shift multiplicand to the left 1 bit Product Shift multiplier to the right 1 bit Control test Write 64 bits 32 steps? no yes Initially 0 End m0: LSB bit of the multiplier BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_008.png", |
| "page_index": 123, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:25+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-124-0000": { |
| "id": "CO2007-chapter-3-slide-124-0000", |
| "text": "Example Using 4-bit numbers, calculate e 210 x 310 = 00102 x 00112 Iteration Step Multiplier Multiplicand Product 0 Initial values 0011 00000010 00000000 1 1a: 1 = Prod= Prod + Mcand 0011 0000 0010 00000010 2: Shift left Multiplicand 0011 0000 0100 0000 0010 3: Shift right Multiplier 0000 0000 0100 0000 0010 2 1a: 1 = Prod = Prod + Mcand 0001 0000 0100 00000110 2: Shift left Multiplicand 0001 00001000 0000 0110 3: Shift right Multiplier 0000 0000 1000 0000 0110 3 1: 0 => No operation 0000 00001000 0000 0110 2: Shift left Multiplicand 0000 0001 0000 0000 0110 3: Shift right Multiplier 0000 0001 0000 0000 0110 4 1: 0 = No operation 0000 0001 0000 0000 0110 2: Shift left Multiplicand 0000 00100000 0000 0110 3: Shift right Multiplier 0000 0010 0000 0000 0110 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_009.png", |
| "page_index": 124, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:30+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-125-0000": { |
| "id": "CO2007-chapter-3-slide-125-0000", |
| "text": "Optimized hardware Start Multiplicand (32 bit) m0 = 1 m0 = 0 1. m0? 1a. Accumulate Multiplicand to ALU 32 bit 32 MSB bits of product write Product 2. Shift the product 1 bit to the right Control (64 bit) shift right Multiplier 32 step? no yes Optimized in hardware usage; not in performance End BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_010.png", |
| "page_index": 125, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:34+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-126-0000": { |
| "id": "CO2007-chapter-3-slide-126-0000", |
| "text": "MiPS multiplication instructions Two 32-bit registers for product HI: most-significant 32 bits LO: least-significant 32-bits Instructions - mult rs, rt / multu rs, rt 64-bit product in Hl/LO - mfhi rd / mfIo rd Move from Hl/LO to rd Can test HI value to see if product overflows 32 bits - mul rd, rs, rt ONLY least-significant 32 bits of product -> rd BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 11", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_011.png", |
| "page_index": 126, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:36+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-127-0000": { |
| "id": "CO2007-chapter-3-slide-127-0000", |
| "text": "Division Dividend 1000 Divisor 1001010 1001010 1000 10 10 2 2 -1000 -1000 1001 Quotient 1001 10 10 10 101 101 1010 n-bit operands yield n-bit 1010 -1000 -1000 quotient and remainder Reminder 10 10 10 2 Long division approach Restoring divisor if divisor dividend bits Do the subtract, and if remainder goes < 0, add divisor back 1 bit in quotient, subtract Signed division Otherwise Divide using absolute values 0 bit in quotient, bring down Adjust sign of quotient and remainder as next dividend bit required BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_012.png", |
| "page_index": 127, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:42+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-128-0000": { |
| "id": "CO2007-chapter-3-slide-128-0000", |
| "text": "Hardware for division Start K Initially divisor 1. Deduct the value of divisoi in left half from the value of reminder reminder 0 reminder < 0 Divisor 2. Test reminder Shift right 64 bits 4. Accumulate divisor 3. Shift quotient to reminder & to the left 1 bit & shift quotient Quotient adjust LSB to 1 to the left 1 bit 64-bit ALU Shift left 32 bits Remainder Control 5. Shift divisor to the right 1 bit Write test 64 bits 1 33 step? no yes Initially dividend End BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_013.png", |
| "page_index": 128, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:32:46+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-129-0000": { |
| "id": "CO2007-chapter-3-slide-129-0000", |
| "text": "Example Using 4-bit numbers, calculate e 710 * 210 = 01112 : 00102 Iteration Step Quotient Divisor Remainder 0 Initial values 0000 0010 0000 0000 0111 1: Rem = Rem - Div 0000 0010 0000 @110 0111 1 2b: Rem < 0 => +Div,sIl Q,QO= 0 0000 0010 0000 0000 0111 3: Shift Div right 0000 0001 0000 0000 0111 1: Rem = Rem - Div 0000 0001 0000 111 0111 2 2b: Rem < 0 => +Div,sll Q,QO = 0 0000 0001 0000 0000 0111 3: Shift Div right 0000 0000 1000 0000 0111 1: Rem = Rem - Div 0000 0000 1000 0111 1111 3 2b: Rem < 0 => +Div,slI Q,Q0 = 0 0000 0000 1000 0000 0111 3: Shift Div right 0000 0000 0100 0000 0111 1: Rem = Rem - Div 0000 0000 0100 0000 0011 4 2a: Rem Z 0 => sll Q,Q0 = 1 0001 0000 0100 0000 0011 3: Shift Div right 0001 0000 0010 0000 0011 1: Rem = Rem - Div 0001 0000 0010 0000 0001 5 2a: Rem 0 => sll Q,Q0 = 1 0011 0000 0010 0000 0001 3: Shift Div right 0011 0000 0001 0000 0001 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_014.png", |
| "page_index": 129, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-30T22:32:54+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-130-0000": { |
| "id": "CO2007-chapter-3-slide-130-0000", |
| "text": "Optimized hardware Start 1. Shift reminder to the left 1 bit divisor Deduct divisor from 32 MSB bits of reminder (32 bit) reminder 0 reminder < 0 2. Test reminder ALU 32 bit 3.Adjust the LSB bit 4.Restore 32 MSB bits dividend of reminder to 1 of reminder shift left reminder control (64 bit) reminder quotient 32 step? no yes End BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 15", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_015.png", |
| "page_index": 130, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:32:58+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-131-0000": { |
| "id": "CO2007-chapter-3-slide-131-0000", |
| "text": "MipS division instructions Use HI/LO registers for result - Hl: 32-bit remainder L0: 32-bit quotient Instructions - div rs, rt / divu rs, rt No overflow or divide-by-0 checking What are values in HI/LO if divisor is 0? Software must perform checks if required - Use mfhi, mflo to access result BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_016.png", |
| "page_index": 131, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:00+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-132-0000": { |
| "id": "CO2007-chapter-3-slide-132-0000", |
| "text": "FLOATING POINT NUMBERS BK TP.HCM 17", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_017.png", |
| "page_index": 132, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:02+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-133-0000": { |
| "id": "CO2007-chapter-3-slide-133-0000", |
| "text": "Floating point Representation for non-integral numbers - Including very small and very large numbers Like scientific notation - Not normalized: 0.002 x 10-4; 987.6 x 103 In binary In ANSI C: float or double BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_018.png", |
| "page_index": 133, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:04+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-134-0000": { |
| "id": "CO2007-chapter-3-slide-134-0000", |
| "text": "Floating point standard Defined by lEEE Std 754-1985 (IEEE-754) Developed in response to divergence of representations Portability issues for scientific code Now almost universally adopted Two representations - Single precision (32-bit): float (C) - Double precision (64-bit): double (C) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_019.png", |
| "page_index": 134, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-30T22:33:06+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-135-0000": { |
| "id": "CO2007-chapter-3-slide-135-0000", |
| "text": "lEEE-754 format single: 8 bits single: 23 bits double: 11 bits double: 52 bits S Exponent Fraction S: sign bit (0 = non-negative, 1 = negative) Normalize significand: 1.0 significand < 2.0 - Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) Significand is Fraction with the \"1.\" restored: 0 Fraction < 1.0 Exponent = actual exponent + Bias Ensures exponent is unsigned Single: Bias = 127; Double: Bias = 1023 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_020.png", |
| "page_index": 135, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:33:09+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-136-0000": { |
| "id": "CO2007-chapter-3-slide-136-0000", |
| "text": "Example Question: What is the decimal value of the floating point number 0x414C0000? Answer: 0x414C0000 => single precision S = 0; Exponent = 1000_0010, = 130; BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_021.png", |
| "page_index": 136, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:12+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-137-0000": { |
| "id": "CO2007-chapter-3-slide-137-0000", |
| "text": "Single precision range Exponents 00000000 and 11111111 reserved Smallest value Exponent: 00000001 = actual exponent = 1 - 127 = -126 Fraction: 000...00 => significand = 1.0 1.0 x 2-126 Largest value exponent: 11111110 => actual exponent = 254 - 127 = +127 Fraction: 111...11 = significand 2.0 2.0 x 2127 3.4 x 1038 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_022.png", |
| "page_index": 137, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:15+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-138-0000": { |
| "id": "CO2007-chapter-3-slide-138-0000", |
| "text": "Double precision range Exponents 0000...00 and 1111...11 reserved Smallest value Exponent: 00000000001 = actual exponent = 1 - 1023 = -1022 Fraction: 000...00 = significand = 1.0 1.0 x 2-1022 Largest value Exponent: 11111111110 => actual exponent = 2046 - 1023 = +1023 Fraction: 111...11 => significand 2.0 2.0 X 21023 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_023.png", |
| "page_index": 138, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:17+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-139-0000": { |
| "id": "CO2007-chapter-3-slide-139-0000", |
| "text": "Convert to lEEE-754 Step 1: Decide S (1: negative; 0: positive) Step 2: Decide Fraction - Convert the integer part to Binary Convert the fractional part to Binary Adjust the integer and fractional parts according the Significand format (1.xxx) Step 3: Decide exponent BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_024.png", |
| "page_index": 139, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:20+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-140-0000": { |
| "id": "CO2007-chapter-3-slide-140-0000", |
| "text": "Example Question: what is the lEEE-754 representation of 12.75? Answer: - S=0; Exponent = 3 + 127 = 130 Fraction: 100_1100_0000_0000_0000_0000, 12.75 = 0x414C0000 IEEE-754 6.3 = ? lEEE-754 single precision BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_025.png", |
| "page_index": 140, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:23+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-141-0000": { |
| "id": "CO2007-chapter-3-slide-141-0000", |
| "text": "Floating point addition Question: how to add two 4-digit decimal floating point numbers 9.999 x 101 + 1.610 x 10-1 Answer: do the following step 1. Align decimal points Shift number with smaller exponent - 9.999 x 101 + 0.016 x 10l 2. Add significands - 9.999 x 101 + 0.016 x 101 = 10.015 x 10l 3. Normalize result & check for over/underflow - 1.0015 x 102 4. Round and renormalize if necessary 1.002 x 102 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_026.png", |
| "page_index": 141, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:25+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-142-0000": { |
| "id": "CO2007-chapter-3-slide-142-0000", |
| "text": "Floating point addition Now consider a 4-digit binary example 1.000, x 2-1 + -1.110, x 2-2(0.5 + -0.4375) 1. Align binary points Shift number with smaller exponent - 1.0002 x 2-1 + -0.1112 x 2-1 2. Add significands - 1.0002 x 2-1 + -0.1112 x 2-1 = 0.0012 x 2-1 3. Normalize result & check for over/underflow - 1.000, x 2-4, with no over/underflow 4. Round and renormalize if necessary - 1.000 x 2-4 (no change) = 0.0625 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_027.png", |
| "page_index": 142, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:28+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-143-0000": { |
| "id": "CO2007-chapter-3-slide-143-0000", |
| "text": "Floating pointer adder hardware Sign Exponent Fraction Sign Exponent Fraction Compare Small ALU exponents Exponent difference Step 1 0 Shift smaller Control Shift right number righi Add Step 2 Big ALU Step 3 Increment or Shift left or right decrement Normalize Step 4 Rounding hardware Round Sign Exponent Fraction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_028.png", |
| "page_index": 143, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:32+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-144-0000": { |
| "id": "CO2007-chapter-3-slide-144-0000", |
| "text": "Floating point multiplication Question: how to multiply two 4-digit decimal numbers 1.110 x 1010 x 9.200 x 10-5 Answer: do the following steps 1. Add exponents For biased exponents, subtract bias from sum - New exponent =10 + -5 = 5 2. Multiply significands 1.110 x 9.200 = 10.212 => 10.212 x 10 3. Normalize result & check for over/underflow 1.0212 x 106 4. Round and renormalize if necessary 1.021 x 106 5. Determine sign of result from signs of operands - +1.021 x 106 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_029.png", |
| "page_index": 144, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:35+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-145-0000": { |
| "id": "CO2007-chapter-3-slide-145-0000", |
| "text": "Floating point multiplication Now consider a 4-digit binary example 1.000, x 2-1 x -1.110, x 2-2 = (0.5 x -0.4375) Add exponents - Unbiased: -1 + -2 = - 3 - Biased: (-1 + 127) + (-2 + 127) = - 3 + 254 - 127 = - 3 + 127 Multiply significands 1.0002 x 1.1102 = 1.1102 => 1.1102 x 2-3 Normalize result & check for over/underflow 1.110, x 2-3 (no change) with no over/underflow Round and renormalize if necessary 1.110, x 2-3 (no change Determine sign: +ve X -ve => - ve - -1.1102 x 2-3 = - 0.21875 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_030.png", |
| "page_index": 145, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:33:38+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-146-0000": { |
| "id": "CO2007-chapter-3-slide-146-0000", |
| "text": "FP instructions in MIPS Fp hardware is coprocessor 1 0x40F00000 => 7.5 Adjunct processor that extends the ISA => 1.089.470.464 Separate FP registers - 32 single-precision: $fO, $f1, ... $f31 - Paired for double-precision: $fO/$f1,$f2/$f3,... Odd-number registers: right half of 64-bit floating-point numbers FP instructions operate only on FP registers - Programs generally don't do integer ops on FP data, or vice versa - More registers with minimal code-size impact Fp load and store instructions - Iwc1,Idc1,swc1,sdc1 e.g.,Idc1$f8,32($sp) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 31", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_031.png", |
| "page_index": 146, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:33:41+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-147-0000": { |
| "id": "CO2007-chapter-3-slide-147-0000", |
| "text": "FP instructions in MIPS Single-precision arithmetic Write MIPS Code for following C code float a, b;//$f0 = a; $f1 = b add.s, sub.s, mul.s, div.s if (a< b) a = a+b; e.g.,add.s $fO,$f1,$f6 else a = a - b; Double-precision arithmetic add.d, sub.d, mul.d, div.d e.g.,mul.d $f4,$f4,$f6 Single- and double-precision comparison - c.xx.s, c.xx.d (xx is eq, It, le,...) Sets or clears FP condition-code bit e.g.c.It.s $f3,$f4 Branch on FP condition code true or false bc1t,bc1f e.g., bc1t TargetLabel BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 32", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_032.png", |
| "page_index": 147, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:44+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-148-0000": { |
| "id": "CO2007-chapter-3-slide-148-0000", |
| "text": "Example: *F to *C C code: float f2c (float fahr{ return ((5.0/9.0)*(fahr - 32.0)): - fahr in $f12, result in $fO, literals in global memory space Compiled MIPS code: f2c:lwc1 $f16,const5($gp) Iwc1 $f18,const9($gp) div.s $f16,$f16,$f18 lwc1 $f18,const32($gp) sub.s $f18,$f12,$f18 mul.s $f0, $f16,$f18 jr $ra BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 33", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_033.png", |
| "page_index": 148, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:47+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-149-0000": { |
| "id": "CO2007-chapter-3-slide-149-0000", |
| "text": "FP machine instructions Name Format Example Comments add.s R 17 16 6 4 2 O add.s $f2,$f4,$f6 sub.s R 17 16 6 4 2 1 sub.s $f2,$f4,$f6 mul.s R 17 16 6 4 2 2 mul.s $f2,$f4,$f6 div.s R 17 16 6 4 2 3 div.s $f2,$f4,$f6 add.d R 17 17 6 4 2 0 add.d $f2.$f4.$f6 sub.d R 17 17 6 4 2 1 sub.d $f2,$f4,$f6 mul.d R 17 17 6 4 2 2 mul.d $f2.$f4.$f6 div.d R 17 17 6 4 2 3 div.d $f2,$f4,$f6 1wc1 I 49 20 2 100 1wc1 $f2,100($s4 swc1 I 57 20 2 100 swc1 $f2,100($s4) bc1t 1 17 8 1 25 bc1t 25 bc1f - 17 8 0 25 bc1f 25 c.lt.s R 17 16 4 2 0 60 c.lt.s $f2,$f4 c.lt.d R 17 17 4 2 0 60 c.lt.d $f2.$f4 Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 34", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_034.png", |
| "page_index": 149, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:33:57+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-150-0000": { |
| "id": "CO2007-chapter-3-slide-150-0000", |
| "text": "Accurate arithmetid IEEE Std 754 specifies additional rounding control Extra bits of precision (guard, round, sticky) Choice of rounding modes - Allows programmer to fine-tune numerical behavior of a computation Not all FP units implement all options - Most programming languages and FP libraries just use defaults Trade-off between hardware complexity, performance, and market requirements Who Cares About FP Accuracy? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 35", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_035.png", |
| "page_index": 150, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:00+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-151-0000": { |
| "id": "CO2007-chapter-3-slide-151-0000", |
| "text": "Concluding remarks Bits have no inherent meaning - Interpretation depends on the instructions applied Computer representations of numbers Finite range and precision Need to account for this in programs BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 36", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_036.png", |
| "page_index": 151, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:02+07:00" |
| } |
| }, |
| "CO2007-chapter-3-slide-152-0000": { |
| "id": "CO2007-chapter-3-slide-152-0000", |
| "text": "The end Computer Engineering - CSE - HCMUT BK 37 TP.HCM", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_3/slide_037.png", |
| "page_index": 152, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:05+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-153-0000": { |
| "id": "CO2007-chapter-4-slide-153-0000", |
| "text": "COMPUTER ARCHITECTURE Chapter 4: Microarchitecture BK Computer Engineering - CSE - HCMUT 1 TP.HCM", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_001.png", |
| "page_index": 153, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:07+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-154-0000": { |
| "id": "CO2007-chapter-4-slide-154-0000", |
| "text": "Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPu hardware We will examine two MiPs implementations A simplified version: CPI = 1 A more realistic pipelined version: CPl 1 Simple subset, shows most aspects - Memory reference: Iw, sw - Arithmetic/logical: add, sub, and, or, slt - Control transfer: beq, j BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_002.png", |
| "page_index": 154, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:10+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-155-0000": { |
| "id": "CO2007-chapter-4-slide-155-0000", |
| "text": "Instruction execution 1. PC -> instruction memory (cache), fetch instruction 2. Register numbers -> registers file, read registers 3. Depending on instruction class 3,1, Use ALU to calculate Arithmetic result -> done Memory address for load/store -> 3.2 Branch target address -> 3.3 3.2. Access data memory for load/store 3.3. PC < target address or PC + 4 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_003.png", |
| "page_index": 155, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:13+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-156-0000": { |
| "id": "CO2007-chapter-4-slide-156-0000", |
| "text": "Execution stages 1. Instruction fetch (iF): PC -> instruction address 2. Instruction decode (iD): register operands -> register file 3. Execute (EXE) Load/store: compute a memory address Arithmetic/logical: compute an arithmetic/logical result 4. Memory access (MEM) : - Load: read data memory - Store: write data memory 5. Write back (WB) : - Store a result of register file BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_004.png", |
| "page_index": 156, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:16+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-157-0000": { |
| "id": "CO2007-chapter-4-slide-157-0000", |
| "text": "Datapath - controller Datapath: contains information that is operated on by a functional unit - Instruction memory: contain instructions (iF) Registers file: 32 32-bit registers (ID & WB) - ALU: calculate arithmetic and logical operations (ExE) Data memory: contain data (MEM) Control signals: used for multiplexer selection or for directing the operation of a functional unit Control unit Multiplexer BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_005.png", |
| "page_index": 157, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:19+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-158-0000": { |
| "id": "CO2007-chapter-4-slide-158-0000", |
| "text": "Datapath overview Add Add Data Register # PC Registers ALU Address Address Instruction Register # Data Instruction memory memory Register # Data BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_006.png", |
| "page_index": 158, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:22+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-159-0000": { |
| "id": "CO2007-chapter-4-slide-159-0000", |
| "text": "Multiplexer - MUX A A- 0 M C u C x B B S S S=0-> C=A S=1-C=B BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_007.png", |
| "page_index": 159, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:34:25+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-160-0000": { |
| "id": "CO2007-chapter-4-slide-160-0000", |
| "text": "Controller overview Branch M u x Add M Add u x ALU operation Data MemWrite Register # PC Address Instruction Registers ALU Address Register # M Zero Data Instruction u memory memory Register # X RegWrite Data MemRead Control BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
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| } |
| }, |
| "CO2007-chapter-4-slide-161-0000": { |
| "id": "CO2007-chapter-4-slide-161-0000", |
| "text": "Building datapath Hardware components: 5 Read register 1 Read Instruction Register data 1 address Read numbers register 2 Data Instruction PC Add Sum Registers Write register Read Instruction Write data 2 memory Data Data RegWrite IF lD & WB ALU operation MemWrite Read Address data Zero 16 32 Sign- ALU ALU Data extend result Write memory data MemRead EXE MEM BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_009.png", |
| "page_index": 161, |
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| } |
| }, |
| "CO2007-chapter-4-slide-162-0000": { |
| "id": "CO2007-chapter-4-slide-162-0000", |
| "text": "Instruction fetch Main operations: fetching the next instruction from Instruction memory Pc - instruction address Instruction memory -> Add instruction (32 bits) 4 PC <- PC + 4 (using the Add component) Instruction PC 32 bit address Results: 32 bit Instruction 32 bits machine instruction Instruction (Instruction) memory Address of the next instruction in PC BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_010.png", |
| "page_index": 162, |
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| "timestamp": "2025-10-30T22:34:38+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-163-0000": { |
| "id": "CO2007-chapter-4-slide-163-0000", |
| "text": "Instruction decode Main operations: Extract machine instructions Results: - Values (32-bit) for the next stage R-format, branch, and store: rs, rt - Registers -> values I-format: rs -> Registers -> values & immediate -> sign-extend Add 5 bit Read register 1 32 bit Instruction PC 32 bit address Read data 1 5 bit Instruction Read register 2 32 bit 5 bit Instruction Write register 32 bit memory Read data 2 32 bit Write data Registers RegWrite Sign-extend 16 bit 32 bit BK TP.HCM 11", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_011.png", |
| "page_index": 163, |
| "language": "en", |
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| } |
| }, |
| "CO2007-chapter-4-slide-164-0000": { |
| "id": "CO2007-chapter-4-slide-164-0000", |
| "text": "Instruction execution Main operation Results: Arithmetic result/memory address (ALU - Calculate the arithmetic operations/ result) address of memory/register comparison Comparison result (zero-output) R-format and bne&beq: both PC+4 operands collected from Registers 2 I-format (except bne&beq): one Add Target address operands collected from Registers and one from sign-extend 4 bit ALU Operation 5 bit 32 bit Read register 1 Read data 1 oprd 1 Instruction 5 bit zero Read register 2 32 bit ALU 32 bit 5 bit ALU-result Write register Read data 2 XnW 32 bit 32 bit oprd2 Write data Register RegWrite Sign-extend 16 bit 32 bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_012.png", |
| "page_index": 164, |
| "language": "en", |
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| } |
| }, |
| "CO2007-chapter-4-slide-165-0000": { |
| "id": "CO2007-chapter-4-slide-165-0000", |
| "text": "Memory access Main operations Results: Load: get data from Data Load: values of Data memory memory (Read data) Store: write data from Store: N/A Registers to Data memory 4 bit ALU Operation 5 bit 32 bit Read register 1 Read data 1 oprd 1 Instruction MemWrite 5 bit Read register 2 zero 32 bit ALU 32 bit 32 bit 5 bit Read Address ALU result data Write register Read data 2 32 bit 32 bit 32 bit xnW Write oprd 2 Write data data Data Register memory RegWrite MemRead BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_013.png", |
| "page_index": 165, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:34:52+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-166-0000": { |
| "id": "CO2007-chapter-4-slide-166-0000", |
| "text": "Write back Main operations: - Write values back to Registers (arithmetic/load) Result: - N/A 4 bit ALU Operation 5 bit 32 bit Read register 1 Read data 1 oprd 1 Instruction 5 bit MemWrite Read register 2 zero 32 bit ALU 32 bit 32 bit Read 5 bit ALU result Address data Write register xnW Read data 2 32 bit 32 bit 32 bit xnW Write oprd 2 Write data data Data Register memory MemRead RegWrite BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_014.png", |
| "page_index": 166, |
| "language": "en", |
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| } |
| }, |
| "CO2007-chapter-4-slide-167-0000": { |
| "id": "CO2007-chapter-4-slide-167-0000", |
| "text": "Full datapath xnW 2 Add PCSrc Add 4 bit 5 bit ALU Operation 32 bit Read register 1 Instruction Read data 1 oprd 1 PC Address 32 bit 5 bit MemtoReg 32 bit zero MemWrite Instruction Read register 2 ALUSrc ALU 32 bit 5 bit 32 bit Read Instruction ALU result Address Write register data xnw memory Read data 2 xnW 32 bit 32 bit 32 bit Write oprd 2 Write data data Data memory Register MemRead RegWrite Sign-extend 16 bit 32 bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 15", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_015.png", |
| "page_index": 167, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:01+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-168-0000": { |
| "id": "CO2007-chapter-4-slide-168-0000", |
| "text": "Example Question: Assume that the processor is executing add $s0,$s1,$s2 Identify values of functional units' inputs/outputs Answer: - The machine code is: 000000_10001_10010_10000_00000_100000 Instruction memory: Instruction address = PC (word address where we store the above instruction) Instruction = machine code Registers: Read register 1 = 10001, => Read data 1 = content ($s1) Read register 2 = 10010, => Read data 2 = content ($s2) Write register = 10000, & Write data = content ($s1) + content ($s2) ...sign-extend: input = 10000 00000 100000 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_016.png", |
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| } |
| }, |
| "CO2007-chapter-4-slide-169-0000": { |
| "id": "CO2007-chapter-4-slide-169-0000", |
| "text": "Building controller Extracting bits from 32-bit instructions Read register 1, Read register 2, and Write registers - Sign-extend Control block Building a Control block: Handling multiplexers Handling control signals of functional units RegWrite MemRead MemWrite BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 17", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_017.png", |
| "page_index": 169, |
| "language": "en", |
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| } |
| }, |
| "CO2007-chapter-4-slide-170-0000": { |
| "id": "CO2007-chapter-4-slide-170-0000", |
| "text": "Extracting bits Registers: Read register 1 rs (instruction[25:21] - Read register 2 rt (instruction[20:16]) - Write register rt/rd -> need a multiplexer Sign-extend address (instruction[15:0] 0 rt rd rs shamt funct R-type 31:26 25:21 20:16 15:11 10:6 5:0 Load/ 35 or 43 rs rt address Store 31:26 25:21 20:16 15:0 4 rs rt address Branch 31:26 25:21 20:16 15:0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_018.png", |
| "page_index": 170, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:11+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-171-0000": { |
| "id": "CO2007-chapter-4-slide-171-0000", |
| "text": "Datapath with bit-selection 32 bit 32 bit 1 Add PCSrc Add [25:21] 32 bit Read register 1 Read data oprd 1 Instruction PC 32 bit address 32 bit [20:16] MemWrite zero Instruction Read register 2 ALUSrc MemtoReg ALU 0 32bit 32 bit Read 1 Instruction XNW H ALU result Address data xnw [15:11] Write register memory Read data 2 0 32 bit 32 bit xnw Write oprd 2 0 Write data data RegDst Data 1 Registers 4 bit memory RegWrite ALUoperatiol MemRead [15:0] ALUop ALU control Sign-extend 16 bit 32 bit 32 bit [5:0] 6 bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_019.png", |
| "page_index": 171, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:17+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-172-0000": { |
| "id": "CO2007-chapter-4-slide-172-0000", |
| "text": "Control block Main function: handling Predefined ALU operation values multiplexers and functional Operator ALU Opeation and 0000 units' control signals or 0001 add - ALU: two levels of decoding 0010 sub 0110 slt 0111 Level 1: 6 bit opcode -> 2 bit ALUop ALUop: Level 2: 2 bit ALUop (+ 6 - opcode -> add operator - bit function field) -> 4 bit ALUop = 00 ALU operation - opcode -> sub operator -> Muxes and control signals ALUop = 01 of functional units (except - opcode -> unknown -> ALUop = 10 ALU): 6 bit opcode BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_020.png", |
| "page_index": 172, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:20+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-173-0000": { |
| "id": "CO2007-chapter-4-slide-173-0000", |
| "text": "Full microarchitecture 32 bit xnW 1 32 bit Add PCSrc Add Branch [31:26] Control unit RegWrite [25:21] 32 bit Read register 1 Instruction Read oprd 1 PC address [20:16] data 1 32 bit 32 ASSSSE bit zerc MemWrite Instruction Read register 2 oxnw ALU Read 32 32 bit HXNW o Instruction ALU Address Write register data memory [15:11] Read oXnW result data 2 32 bit 32bit oprd 2 Write Write data data Data RegD Register 4 bit memory ALU Opleration MemRead [15:0] ALU Sign Control 16 bit extend ALUOp 32 bit 32 bit [5:0] 6`bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_021.png", |
| "page_index": 173, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:28+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-174-0000": { |
| "id": "CO2007-chapter-4-slide-174-0000", |
| "text": "Exercise Question: assume that registers store values of two times their numbers, for instance $s1 stores values of 17 x 2 = 34, please identify: 1. Which functional units contribute to the processing of following instructions 2. Values of inputs/outputs of functional units when processing following instructions 3. Values of control signals when processing following instructions - add $t0,$t1,$t2 addi $s0,$s1,100 - lw $s0,100($s2) # memory word at address 136 stores values of 2021 - sw $s0,100($s2 beq $s1,$sO,L1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22", |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_022.png", |
| "page_index": 174, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:31+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-175-0000": { |
| "id": "CO2007-chapter-4-slide-175-0000", |
| "text": "Unconditional jump instructions Chapter 2: update Pc with concatenation of Top 4 bits of old PC 26-bit jump address PC ={PC31:28Laddress,00} - 00 One more way to update Pc => Need a multiplexer & an extra control signal decoded from opcode 2 address Jump 31:26 25:0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_023.png", |
| "page_index": 175, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:34+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-176-0000": { |
| "id": "CO2007-chapter-4-slide-176-0000", |
| "text": "Datapath with Jumps added 32 bit xnw [8Z:T€](v+Od) 2 Add 1 H!ys Jump Add [25:0] Shift Pstse left 2 ...... 4 32 bit ...... Branch [31:26] Control unit .. . RegWrite [25:21] 32 bit Read register1 Instruction Read data 1 oprd 1 PC 32 bit address 32 Hit [20:16] MemWrite ASLSTC zero Instruction :Readregister 2 0 ALU 32 bit 32 bit Read Instruction xnW ALU result Address data xnw o [15:11] Write register memory 0 Read data 2 1 xnW 32 bit 32 bit Write Write data oprd data Data RegDst Registers 4 bit Memory ALU Operation .......... MemRead [15:0] ALU Control :Sign-extend ALUOP 16 bit 32 bit 32 bit [5:0] 6 bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_024.png", |
| "page_index": 176, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:41+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-177-0000": { |
| "id": "CO2007-chapter-4-slide-177-0000", |
| "text": "Performance issue Simplified version (CPl = 1): every instruction executed in only one cycle - Longest delay determines clock period What is the longest instruction? Instruction memory -> register file > AlU -> data memory > register file Not feasible to vary period for different instructions We will improve performance by pipelining BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_025.png", |
| "page_index": 177, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:44+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-178-0000": { |
| "id": "CO2007-chapter-4-slide-178-0000", |
| "text": "Pipelining analogy Pipeline laundry: 6PM 7 8 9 10 11 12 1 2AM Overlapping execution Time Task order Improving performance A (time for entire group) B C Four loads D 6PM 7 8 9 10 11 12 1 2AM Speed-up = 2.3X Time Not impressive Task order OM A Non-stop (#loads -> co) B C - Speed-up? D Number of stages BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_026.png", |
| "page_index": 178, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:48+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-179-0000": { |
| "id": "CO2007-chapter-4-slide-179-0000", |
| "text": "MIPS pipeline Five stages, one step per stage 1. Instruction fetch (iF): PC -> instruction address 2. Instruction decode (iD): register operands -> register file 3. Execute (EXE): Load/store: compute a memory address Arithmetic/logical: compute an arithmetic/logical result 4. Memory access (MEM): Load: read data memory Store: write data memory 5. Write back (WB): Store a result of register file BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_027.png", |
| "page_index": 179, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:51+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-180-0000": { |
| "id": "CO2007-chapter-4-slide-180-0000", |
| "text": "Pipeline performance Assume time for stages is 100ps for register read or write (ID & WB) 200ps for other stages (IF, EXE,& MEM) Compare pipelined datapath with single-cycle datapath nstruction Instr Register ALU op Memory Register Total fetch read access write time 200ps 100 ps 200ps Iw 200ps 100 ps 800ps 200ps 100 ps 200ps 200ps 700ps sW 200ps 100 ps 200ps 100 ps 600ps R-format beq 200ps 100 ps 200ps 500ps BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_028.png", |
| "page_index": 180, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:35:56+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-181-0000": { |
| "id": "CO2007-chapter-4-slide-181-0000", |
| "text": "Pipeline performance Program execution 200 400 600 800 1000 1200 1400 1600 1800 Time order (in instructions) Single-cycle(Tc = 800ps) lw $1,100($0) Instruction Data Reg ALU Reg fetch access lw $2,200($0) Instruction Data 800 ps Reg ALU Reg fetch access lw $3,300($0) Instruction 800 ps fetch 800 ps Program execution 200 400 600 800 1000 1200 1400 Time order (in instructions) Pipeline(Tp = 200ps) Instruction Data lw $1,100($0) Reg ALU Reg fetch access Instruction Data lw $2,200($0) 200 ps Reg ALU Reg fetch access Instruction Data lw $3,300($0) 200 ps Reg ALU Reg fetch access 200 ps 200 ps 200 ps 200 ps 200 ps BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29", |
| "metadata": { |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_029.png", |
| "page_index": 181, |
| "language": "en", |
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| } |
| }, |
| "CO2007-chapter-4-slide-182-0000": { |
| "id": "CO2007-chapter-4-slide-182-0000", |
| "text": "Pipeline speed-up time bw instructionsingle-cycle time of single-cycle speed-up = time of pipelined If all stages are balanced: - speed_up = number of pipe stages If not balanced, speedup is less Source of speedup Throughput increased Latency (time for each instruction) does not decrease Sometimes increased BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30", |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_030.png", |
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| "timestamp": "2025-10-30T22:36:07+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-183-0000": { |
| "id": "CO2007-chapter-4-slide-183-0000", |
| "text": "Pipeline datapath IF: Fetch an instruction D: Decode the instruction EX: Compute a result or MEM: Access WB: Write the & access registers an address of memory memory 1 result back 1 32 bit 32 bit Add Add [25:21] 32 bit oXNWH Instruction Read register 1 Read data 1 1 oprd 1 MemtoReg address PC 32 bit [20:16] MemWrite 32 bit Instruction Read register 2 AL USrc zero - 0 ALU 32bit 32 bit Read 1 Instruction xnw ALU result Address [15:11] Write register data xnW PCSrc memory 0 Read data 2 xnW 32 bit 32 bit 1 Write oprd 2 0 Write data data Data Reg isters 1 RegDst 4 bit Memory Reg Write ALU Operatior MemRead - - [15:0] - ALUOp ALU Control Sign-extend 16 bit 32 bit 1 1 1 32 bit 1 1 1 1 1 [5:0] 6`bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 31", |
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| "timestamp": "2025-10-30T22:36:16+07:00" |
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| "CO2007-chapter-4-slide-184-0000": { |
| "id": "CO2007-chapter-4-slide-184-0000", |
| "text": "Instructions execution Time (in clock cycles) CC1 CC2 CC3 CC4 CC5 CC6 CC7 I - lw $s1,10($s0) IM REG DM REG 1w $s2,20($s0) REG IM DM REG 1 - - - - - lw $s2,30($s0) IM REG DM REG Multi-Cycle Pipeline Diagram How can we keep data when stages are not balanced? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 32", |
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| "CO2007-chapter-4-slide-185-0000": { |
| "id": "CO2007-chapter-4-slide-185-0000", |
| "text": "Wholesale market example - 10 10 10 weight = 100kg weight = 1ton weight = 1ton weight = 100kg time = 15minutes time = 1hour time = 1hour time = 15minutes Trucks move forward when completed Accident at the Apple store - Barriers can help: open every hour (cycle BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 33", |
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| "CO2007-chapter-4-slide-186-0000": { |
| "id": "CO2007-chapter-4-slide-186-0000", |
| "text": "Pipeline registers Barriers in wholesale markets > Registers in digital circuits IF/ID ID/EX EX/MEM MEM/WB 2 Add Add [25:21] oXnW Read register 1 Instruction Read oprd1 data : MemtoReg PC 32 bit address [20:16] MemWrite Read register 2 zero Instruction ALUSrc oXnWH ALU Read -xnw o Instruction Result Address 15:11] Write register data PCSrc Memory Read oXNW H data 2 Write Write data oprd2 data Data RegDstl Registers 4 bit Memory ALU Operation RegWrite MemRead [15:0] ALU Sign Control extend 32 bit ALUOp 16 bit [5:0] 32 bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 34", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_034.png", |
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| } |
| }, |
| "CO2007-chapter-4-slide-187-0000": { |
| "id": "CO2007-chapter-4-slide-187-0000", |
| "text": "Example Question: Given the following MIPS sequence: 1.lw $s0,20($s1) 2.sub $t2,$s2,$s3 3.add $t3,$s3,$s4 4.lw $t4,24($s1) 5.add $t5,$s5,$s6 Assume that the sequence is executed by a 5-stage pipelined MIPS processor a) [ Draw a multi-cycle pipeline diagram for the sequence previous slide BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 35", |
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| } |
| }, |
| "CO2007-chapter-4-slide-188-0000": { |
| "id": "CO2007-chapter-4-slide-188-0000", |
| "text": "Multi-cycle pipeline diagram - - - - - CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 - - - - 1 1 - - lw $s0, 20($s1) IM REG DM REG - - - - - - - - - - - . . - - - - - - - -- - sub $t2, $s2, $s3 : IM - REG - DM REG - - - - 1 - 1 - - - - - - -- - add St3, Ss3, Ss4 IM REG DM REG 1 - - - - - - - - 1 I - - = - - - lw $t4, 24($s1) IM - REG DM REG - - - 1 - 1 1 I - 1 - add $t5, $s5, $s6 - IM - REG DM - REG - - - - - - - - BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 36", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_036.png", |
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| "timestamp": "2025-10-30T22:36:54+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-189-0000": { |
| "id": "CO2007-chapter-4-slide-189-0000", |
| "text": "Single-cycle pipeline diagram add $t5, $s5, $s6 lw $t4, 24($s1) add $t3, $s3, $s4 sub s $t2, $s2, $s3 lw $s0, 20($sl) IF/ID ID/EX EX/MEM MEM/WB Add Add A [25:21] oXnW Instruction Read register 1 Read oprd1 MemtoReg PC 32 bit address data 1 [20:16] MemWrite Instruction Read register 2 zero ALUSrc oxnw ALU Read Instruction Resulth Address data Xnw o Write register PCSrc Memory Read oXNW data 2 Write Write data oprd2 data Data RegDstl Registers Memory 4 bit ALU Operation RegWrite MemRead [15:0] ALU Sign ALUOp Control Anything wrong? extend 16 bit 32 bit [5:0] 32 bit BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 37", |
| "metadata": { |
| "doc_type": "slide", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_037.png", |
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| } |
| }, |
| "CO2007-chapter-4-slide-190-0000": { |
| "id": "CO2007-chapter-4-slide-190-0000", |
| "text": "Corrected pipeline datapath IF/ID ID/EX EX/MEM MEM/WB 2 Add Add [25:21] oXnW Read register 1 Read Address oprd 1 MemtoReg PC data 1 32 bit [20:16] MemWrite Read register 2 zero Instruction ALUSrc ALU Read Instruction Write register Result Address data XNWo PCSrc Memory Read oXnW data 2 Write Write data oprd 2 data Data Registers 1 4 bit Memory ALU Operation RegWrite MemRead [15:0] Sign ALU Control extend 16 bit 32 bit ALUOp [5:0] [20:16] [15:11] RegDst BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 38", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_038.png", |
| "page_index": 190, |
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| "timestamp": "2025-10-30T22:37:05+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-191-0000": { |
| "id": "CO2007-chapter-4-slide-191-0000", |
| "text": "Example of lw -lF lw IF/ID ID/EX EX/MEM MEM/WB 2 Add Add [25:21] oXnW Read register 1 Read oprd1 Address data 1 MemtoReg PC 32 bit [20:16] MemWrite Read register 2 zero Instruction ALUSrc ALU Read HXNW g Instruction Write register Result Address data PCSrc Memory Read oXNW data 2 Write oprd2 0 Write data data Data Registers 4 bit Memory ALU Operation RegWrite MemRead [15:0] Sign ALU ALUOp Control extend 16 bit 32 bit [5:0] 0 XNWH [20:16] [15:11] RegDst BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 39", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_039.png", |
| "page_index": 191, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:11+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-192-0000": { |
| "id": "CO2007-chapter-4-slide-192-0000", |
| "text": "Example of lw -ID lw IF/ID ID/EX EX/MEM MEM/WB 2 Add Add [25:21] oXNWH Read register 1 Read oprd1 Address data 1 MemtoReg PC MemWrite 32 bit [20:16] zero Instruction Read register 2 ALUSrc ALU Read HXNW o Instruction Write register Result Address data PCSrc Memory Read oXnW data 2 Write oprd2 Write data data Data Registers 4 bit Memory ALU Operation RegWrite MemRead [15:0] Sign ALU ALUOp Control extend 16 bit 32 bit [5:0] oXnW [20:16] ] [15:11] 1 RegDst BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 40", |
| "metadata": { |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_040.png", |
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| "timestamp": "2025-10-30T22:37:17+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-193-0000": { |
| "id": "CO2007-chapter-4-slide-193-0000", |
| "text": "Example of lw - EXE lw IF/ID ID/EX EX/MEM MEM/WB 2 Add Add [25:21] oXNWH Read register 1 Read oprd1 Address data 1 MemtoReg PC 32 bit [20:16] Meml rite Instruction Read register 2 zero ALUSrc ALU Read HXNW o Instruction Write register Result Address data PCSrc Memory Read oXnW data 2 Write oprd2 Write data data Data Registers 4 bit Memory ALU Operation RegWrite MemRead [15:0] ALU Sign ALUOp Control extend 16 bit 32 bit [5:0] XnW [20:16] [15:11] 1 RegDst BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 41", |
| "metadata": { |
| "doc_type": "slide", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_041.png", |
| "page_index": 193, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:22+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-194-0000": { |
| "id": "CO2007-chapter-4-slide-194-0000", |
| "text": "Example of lw - MEM lw IF/ID ID/EX EX/MEM MEM/WB 2 Add Add 4 [25:21] Read register 1 Read XNWH Address oprd1 data 1 MemtoReg PC 32 bit [20:16] MemWrite zero Instruction Read register 2 ALUSrc ALU Read Instruction Write register Result Address data XnW PCSrc Memory Read oXnW data 2 Write oprd2 0 Write data data Data Registers 1 Memory 4 bit ALU Operation RegWrite MemRead [15:0] Sign ALU ALUOp Control extend 16 bit 32 bit [5:0] 4 0 xnW [20:16] [15:11] RegDst BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 42", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_042.png", |
| "page_index": 194, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:28+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-195-0000": { |
| "id": "CO2007-chapter-4-slide-195-0000", |
| "text": "Example of lw - WB lw IF/ID ID/EX EX/MEM MEM/WB 2 Add Add [25:21] oXnWH Read register 1 Read Address oprd1 PC data 1 32 bit [20:16] Instruction zero Read register 2 ALUSrc ALU Read HXNW o Instruction Write register Result Address data PCSrc Memory Read oXNW r data 2 Write oprd2 HWrite data data Data Registers 4 bit Memory ALU Operation RegWrite MemRead [15:0] Sign ALU ALUOp Control extend 16 bit 32 bit [5:0] 1 [20:16] ] [15:11] RegDst BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 43", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_043.png", |
| "page_index": 195, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:33+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-196-0000": { |
| "id": "CO2007-chapter-4-slide-196-0000", |
| "text": "Control signals Control signals travel across pipeline registers WB Control M WB EX M WB 2 bit Mitetne doN7D IF/ID ID/EX EX/MEM MEM/WB BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 44", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_044.png", |
| "page_index": 196, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:36+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-197-0000": { |
| "id": "CO2007-chapter-4-slide-197-0000", |
| "text": "Exercise Question: Given the following MIPS sequence: lw $s0,20($s1) sub $t2,$s2,$s3 add $t3,$s3,$s4 lw $t4,24($s1) add $t5,$s5,$s6 Assume that the sequence is executed by a 5-stage pipelined MIPS processor a) Identify values of control signals in cycle 5 at the functional units b) Identify values of control signals in cycle 5 at the Control block BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 45", |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_045.png", |
| "page_index": 197, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:39+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-198-0000": { |
| "id": "CO2007-chapter-4-slide-198-0000", |
| "text": "Full pipeline micro-architecture ID/EX EX/MEN WB MEM/WB Control M WB IF/ID NB M 31:26] 2 Add RegWrite [25:21] oXnW Read register 1 Read Instruction oprd1 PC data 32 bit address [20:16] MemWrite Instruction Read register 2 zero ALU Read HXNW Instruction Write register Result Address data PCSrc Memory Read oXnW data 2l Write Write data oprd2 data Data Registers 4 bit Memory MemRead [15:0] Sign ALU Control extend 16 bit 32 bit [5:0] [20:16] [15:11] BK TP.HCM Computer Architecture (c Cuong Pham-Quoc/HCvUt", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_046.png", |
| "page_index": 198, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:46+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-199-0000": { |
| "id": "CO2007-chapter-4-slide-199-0000", |
| "text": "Hazards Situations that prevent starting the next instruction in the next cycle Structure hazard - A required resource is busy Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instruction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 47", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_047.png", |
| "page_index": 199, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:48+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-200-0000": { |
| "id": "CO2007-chapter-4-slide-200-0000", |
| "text": "Structure hazards Conflict for use of a resource - e.g.,: the laundry process, B forgot to bring clothes from the washing machine to dryer Should be eliminated entirely Stall the pipe for that cycle May repeat many times MiPs processors already solved all structure hazards Separated instructions and data memory (caches) Read and write registers use different ports BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 48", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_048.png", |
| "page_index": 200, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:51+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-201-0000": { |
| "id": "CO2007-chapter-4-slide-201-0000", |
| "text": "Data hazards An instruction depends on completion of data access by a previous instruction sub$tO,$t2,$t3 add $t3,$tO,$t1 No any issues with the simplified version Problem with pipeline CC1 CC2 CC3 CC4 Updated CC5 CC6 value sub $t0,$t2,$t3 $t0 IM REG DM REG Old value $t0 add $t3,$t0,$t1 IM REG DM REG ALL BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 49", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_049.png", |
| "page_index": 201, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:55+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-202-0000": { |
| "id": "CO2007-chapter-4-slide-202-0000", |
| "text": "Control hazards Branch determines flow of control - Fetching next instruction depends on branch outcome Pipeline updates PC in the MEM stage - Still working on ID stage of branch CC1 CC2 CC3 CC4 Updated CC5 CC6 CC7 CC8 CC9 PC beq $t1,$t2,L1 IM REG DM REG ALU Fetch correct instrction IM REG DM REG ubble oubble oubble BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 50", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_050.png", |
| "page_index": 202, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:37:59+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-203-0000": { |
| "id": "CO2007-chapter-4-slide-203-0000", |
| "text": "Data hazards solutions 1. Code rescheduling Done by compiler (software level) Sometimes cannot find solutions 2. Delay or stalls insertion Done by hardware Always can find solutions Increase execution time & need extra hardware resources 3. Forwarding Done by hardware Cannot find solutions in a special case Requires extra hardware resources BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 51", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_051.png", |
| "page_index": 203, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:38:01+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-204-0000": { |
| "id": "CO2007-chapter-4-slide-204-0000", |
| "text": "Code re-scheduling When haven't data hazards happened? - Read after or in the same cycle with Write (RAW) CC1 CC2 CC3 CC4 Updated CC5 CC6 value sub $t0,$t2,$t3 $t0 clk IM REG DM REG input oubble bubbl bubble bubble bubble output bubble bubble oubble bubble oubble New value $t0 add $t3,$t0,$t1 IM REG DM REG Find and swap data-independent instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 52", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_052.png", |
| "page_index": 204, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:38:06+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-205-0000": { |
| "id": "CO2007-chapter-4-slide-205-0000", |
| "text": "Example Question: given the following sequence of MIPS instructions 1:lw $t1,0($t0) 1: lw $t1,0($t0) 2:lw $t2,4($t0) 2:lw $t2,4($t0) 3: add $+3,$+1,$+2 5:lw $t4,8($t0) 4: sw $+5,12($t0) 7: addi $t6,$t0,4 5:lw $t4,8($t0) 3: add $t3,$t1,$t2 6:add $t5,$t1,$t4 4: sw $+5,12($t0) 7: addi $t6,$t0,4 6: add $t5,$t1,$t4 Identify data hazards and solve by code re-scheduling Answer: - The third and the sixth instructions (add $t3, $t1, $t2 and add $t5, $t1, $t4) have data hazards Move two data-independent instructions 5 and 7 to right after the second instruction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 53", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_053.png", |
| "page_index": 205, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:38:10+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-206-0000": { |
| "id": "CO2007-chapter-4-slide-206-0000", |
| "text": "Stalls insertion When haven't data hazards happened? Read after or in the same cycle with Write (RAW) CC1 CC2 CC3 CC4 Updated CC5 CC6 CC7 CC8 value sub $t0,$t2,$t3 $t0 IM REG DM REG New value $t0 add $t3,$t0,$t1 IM REG DM REG stall stall ALU Delay instructions that use data: - ID stage of the instruction using data = WB stage of the instruction producing data BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 54", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_054.png", |
| "page_index": 206, |
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| "timestamp": "2025-10-30T22:38:14+07:00" |
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| "CO2007-chapter-4-slide-207-0000": { |
| "id": "CO2007-chapter-4-slide-207-0000", |
| "text": "Example Questions: given the following MIPS sequence of instructions 1:Iw $t1,O($tO) 2:lw $t2,4($tO) 3: add$t3,$t1,$t2 4:sw $t3,12($tO) - Identify data hazards and solve them by the stalls insertion method; how many cycles needed for the sequence? Answer: Data hazards (2) - (3) & (3) - (4) instruction 12 cycles needed BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 55", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_055.png", |
| "page_index": 207, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:38:17+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-208-0000": { |
| "id": "CO2007-chapter-4-slide-208-0000", |
| "text": "Example (cont.) i 1 - - - - - CK1 CK2 CK3 CK4 CK5 1 CK6 CK7 CK8 CK9 CK10 - CK11 - CK12 1 - - - - - 1 1 1 IM REG DM REG 1 1 1 1 1 1 - - (07$) 1 1 1 1 1 - 1 1 1 1 1 1 1 1 0 1 1 1 IM - REG 1 DM - REG - 1 - - 1 - 1 1 1 1 1 - 1 - 1 - - S 1 - 1 - (07: 1 1 1 1 - 1 1 - S 1 1 1 1 1 - 1 - - i 1 - 1 1 $t3 St1, $t2 IM 1 REG DM REG add s 1 - - 1 : 1 1 1 1 - 2 - 1 1 1 - 1 ? 1 S 1 1 1 1 Stall 1 Stall 1 3 1 1 1 - 1 1 1 0 1 1 IM - REG DM - REG Sw $t3 12($t0) - - - 1 1 1 1 1 1 1 - - 1 1 1 1 - 1 Stall - Stall - - - 1 1 1 - 1 - 1 - - 1 i - - BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 56", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_056.png", |
| "page_index": 208, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:38:58+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-209-0000": { |
| "id": "CO2007-chapter-4-slide-209-0000", |
| "text": "Forwarding When can an instruction use data at soonest? Right after data is produced (EXE stage & MEM stage) When is data processed? Apply operators: EXE state CC1 CC2 CC3 CC4 CC5 CC6 new value $t0 sub $t0,$t2,$t3 IM REG DM REG Replace old value $t0 add St3,St0,St1 IM REG DM REG Use data right after created BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 57", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_057.png", |
| "page_index": 209, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:02+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-210-0000": { |
| "id": "CO2007-chapter-4-slide-210-0000", |
| "text": "Example Question: given the following MiPS sequence 1:sub$s2,$s1,$s3 2:and$s7,$s2,$s5 3:or $s8,$s6,$s2 4:add$sO,$s2,$s2 5: sw $s5,100($s2) Analyze data dependencies & identify data hazards Answer: $s2 produced by the 1st instruction used by all other instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 58", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_058.png", |
| "page_index": 210, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:05+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-211-0000": { |
| "id": "CO2007-chapter-4-slide-211-0000", |
| "text": "Example (cont.) Answer (cont.) CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 - 1 - sub $s2,$s1,$s3 IM REG DM DM - . - - I .. 1 I and $s7,$s2,$s5 IM - REG D:M REG ALU 1 - .1 - - I :. or $s8,$s6,$s2 REG DM REG IM I 1 : 4 - add $s0,$s2,$s2 IM REG 1 DM REG - 4 1 -- sw $s5,100($s2 IM - REG - DM REG - - - - - BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 59", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_059.png", |
| "page_index": 211, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:25+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-212-0000": { |
| "id": "CO2007-chapter-4-slide-212-0000", |
| "text": "Forwarding Consider the previous sequence of MiPs instructions Data can be forwarded CC1 CC2 CC3 CC4 1 CC5 CC6 CC7 CC8 CC9 sub $s2,$s1,$s3 IM REG DM REG -1 and $s7,$s2,$s5 IM REG DM REG 0r $s8,$s6,$s2 IM REG DM REG add $s0,$s2,$s2 IM REG DM REG sw $s5,100($s2) IM REG DM REG BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 60", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_060.png", |
| "page_index": 212, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:30+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-213-0000": { |
| "id": "CO2007-chapter-4-slide-213-0000", |
| "text": "Load used data hazards When instruction producing data is a load, can data be forwarded? Cannot forward to the next instruction since data is produced later CC1 CC2 CC3 CC4 CC5 CC6 lw $s0,100($s1) IM REG DM REG Not value of $s0 add $s2,$s0,$s2 IM REG DM REG - Delay: 1 stall with forwarding or 2 stalls without forwarding BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 61", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_061.png", |
| "page_index": 213, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:34+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-214-0000": { |
| "id": "CO2007-chapter-4-slide-214-0000", |
| "text": "Detecting data hazards EXE hazard versus MEM hazard EXE hazard: forward from the Ex/MEM register Destination register in the MEM stage = one of the source registers of the instruction in EXE MEM hazard: forward from the MEM/wB register Destination register in the WB stage = one of the source registers of the instruction in EXE Passing register numbers along the pipe ID/EX.rs & ID/EX.rt: first & second sources EX/MEM.rd; MEM/WB.rd: destinations BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 62", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_062.png", |
| "page_index": 214, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:37+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-215-0000": { |
| "id": "CO2007-chapter-4-slide-215-0000", |
| "text": "Ex hazard conditions IF/ID ID/EX EX/MEM MEM/WB Control [31;26] unit Instruction address Instruction Instruction [0:1€]sUI Memory [25:21] ID/EX.rs [20:16] ID/EX.rt oXnWH EXMEM.rd MEM/WB.rd [15:11] RegDst 1a.ID/EX.rs = EX/MEM.rd 1b. ID/EX.rt = EX/MEM.rd (not happened when an I-format instruction is in the EXE stage BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 63", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_063.png", |
| "page_index": 215, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:40+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-216-0000": { |
| "id": "CO2007-chapter-4-slide-216-0000", |
| "text": "MEM hazard conditions Consider the following MIPS sequence of instructions 1: add $s0,$s0,$s1 2:add$s0,$sO,$s2 3: add $s0,$s0,$s3 Both EX and MEM hazards seem occur - EX hazard is correct MEM hazard conditions 2a.(ID/EX.rs = MEM/WB.rd) & (ID/EX.rs!= EX/MEM.rd) 2b.(ID/EX.rt = MEM/WB.rd) & (ID/EX.rt!= EX/MEM.rd) (not happened when an I-format instruction is in the ExE stage) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 64", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_064.png", |
| "page_index": 216, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:44+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-217-0000": { |
| "id": "CO2007-chapter-4-slide-217-0000", |
| "text": "Datapath with forwarding ID/EX EX/MEM MEM/WB WB WB Control M IF/ID Unit NE (1) ALUSrc EX (2) RegDst M (3) ALUop [31:26] 2 Add Add RegWrite Mmetme [25:21] xnW Instruction Read register 1 oprd 1 xnW PC 32 bit address Read data 1H [20:16] Instruction zero Read register 2 (1) ALU Read HXnW Instruction Write register Resultl Address data PcSrc Memory xnW Write oprd 2 0 Write data Read data 2 data Data Registers 1 ALU4 bit Memory Operatior F1 MemReaa F2 (3) [15:0] Sign ALU Control extend 16 bit 32 bit [5:0] (2) 4 oxnw EX/MEM.rd [15:11] D/EX.rt Forwarding ID/EX.rs unit EX/MEM.RegWrite Mem/WB.RegWrite BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 65", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_065.png", |
| "page_index": 217, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:51+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-218-0000": { |
| "id": "CO2007-chapter-4-slide-218-0000", |
| "text": "Forwarding control values Mux values Source Explanatior (binary) F1 = 00 ID/EX The first ALU operand comes from the registers file The first ALU operand is forwarded from the prior ALU F1 = 10 EX/MEM result The first AlU operand is forwarded from data memory F1 = 01 MEM/WB of an earlier ALU result F2 = 00 ID/EX The second ALU operand comes from the registers file The second ALU operand is forwarded from the prior F2 = 10 EX/MEM ALU result The second ALU operand is forwarded from data F2 = 01 MEM/WB memory of an earlier ALU result BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 66", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_066.png", |
| "page_index": 218, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:55+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-219-0000": { |
| "id": "CO2007-chapter-4-slide-219-0000", |
| "text": "Forwarding conditions EX hazard 1a: if (EX/MEM.ReqWrite and (EX/MEM.rd 7 O) and (EX/MEM.rd = ID/EX.rs))F1 = 10 1b: if (EX/MEM.RegWrite and (EX/MEM.rd Z 0) and (EX/MEM.rd = ID/EX.rt)) F2 = 10 MEM hazarc - 2a: if (MEM/WB.RegWrite and (MEM/WB.rd 0) and not_(EX/ MEM.ReqWrite and (EX/MEM.rd Z 0) and (EX/MEM.rd = ID/EX.rs) and (MEM/WB.rd = ID/EX.rs)) F1 = 01 2b: if (MEM/WB.RegWrite and (MEM/WB.rd 0) and not_(EX/ MEM.ReqWrite and (EX/MEM.rd Z 0) and (EX/MEM.rd = ID/EX.rt)) and (MEM/WB.rd = ID/EX.rt)) F2 = 01 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 67", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_067.png", |
| "page_index": 219, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:39:59+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-220-0000": { |
| "id": "CO2007-chapter-4-slide-220-0000", |
| "text": "Detecting Load-use data hazards Check when using data instruction is decoded in ID stage - Producing data instruction (load) is in the ExE stage The sooner the better due to a stall inserted Load-use hazard when ID/EX.MemRead and ((ID/EX.rt = IF/ID.rs) or (ID/EX.rt = IF/ID.rt)) How to stall the pipeline? Force control signals in ID/EX register to 0 => EXE, MEM and WB do nothing Prevent updating PC and ID/EX register BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 68", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_068.png", |
| "page_index": 220, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:01+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-221-0000": { |
| "id": "CO2007-chapter-4-slide-221-0000", |
| "text": "ID/EX EX/MEM MEM/WB WB 1 Write xnWo ID/EX.MemRead WB Hazard LU-hazarg M NB detection (1) ALUSrc xsJ Ol/3l EX (2) RegDst M ID/EX.rt (3) ALUop IF/ID Control unit [31:26] 2 Add Add 4 Mtretne RegWrite [2521] xnW 0 Instruction Read register 1 oprd1 XnW PC address Read data 1H 32 bit [2q:16] zero Instruction Read register 2 (1) ALU Read xnw o) Instruction Write register ResultH Address data PCSrc Memory xn 0 X Write Read data 2H nw oprd2 Write data data Data Registers 1 Memory 4 bit F1 Operatior MemRead F2 (3) [15:0] ALU Sign control extend 16 bit 32 bit [5:0] (2) 1 XnW H EX/MEM.rd [15:11] ID/EX.rt Forwarding ID/EX.rs unit EX/MEM.ReqWrite Mem/WB.RegWrite BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 69", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_069.png", |
| "page_index": 221, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:10+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-222-0000": { |
| "id": "CO2007-chapter-4-slide-222-0000", |
| "text": "Branch hazards solutions Predict outcome of branch Only stall if prediction is wrong CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 1 beq $s1,$s2, L1 IM REG DM REG and $s1, $s2, $s3 IM REG DM REG add $t3, $s3, $s4 IM REG DM REG sub $s3, $s3, $s4 IM REG DM REG L1: lw $t4, 24($s1) IM REG DM REG 1 BK 1 TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 70", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_070.png", |
| "page_index": 222, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:15+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-223-0000": { |
| "id": "CO2007-chapter-4-slide-223-0000", |
| "text": "Branch prediction Static branch prediction Based on typical branch behavior Example: loop and if-statement branches Predict backward branches taken Predict forward branches not taken Dynamic branch prediction Hardware measures actual branch behavior e.g., record recent history of each branch - Assume future behavior will continue the trend When wrong, stall while re-fetching, and update history BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 71", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_071.png", |
| "page_index": 223, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:17+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-224-0000": { |
| "id": "CO2007-chapter-4-slide-224-0000", |
| "text": "Concluding remarks ISA influences design of datapath and control Datapath and control influence design of ISA Pipelining improves instruction throughput using parallelism More instructions completed per second Latency for each instruction not reduced Hazards: structural, data, control BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 72", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_072.png", |
| "page_index": 224, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:20+07:00" |
| } |
| }, |
| "CO2007-chapter-4-slide-225-0000": { |
| "id": "CO2007-chapter-4-slide-225-0000", |
| "text": "The end Computer Engineering - CSE - HCMUT BK 73 TP.HCM", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_4/slide_073.png", |
| "page_index": 225, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:22+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-226-0000": { |
| "id": "CO2007-chapter-5-slide-226-0000", |
| "text": "Computer Architecture Chapter 5: Memory Hierarchy BK Computer Engineering - CSE - HCMUT 1 TP.HCM", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_001.png", |
| "page_index": 226, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:25+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-227-0000": { |
| "id": "CO2007-chapter-5-slide-227-0000", |
| "text": "Contents Memory hierarchy Cache organization Direct mapped - Fully associative - n-way associative Virtual memory (self-learning) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_002.png", |
| "page_index": 227, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:27+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-228-0000": { |
| "id": "CO2007-chapter-5-slide-228-0000", |
| "text": "Motivation example amazoh Publishers/Secondary I memory Table/Cache Bookshelf/Memory BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_003.png", |
| "page_index": 228, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:30+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-229-0000": { |
| "id": "CO2007-chapter-5-slide-229-0000", |
| "text": "Principle of Locality Programs access a small proportion of their address space at any time Temporal locality Items accessed recently are likely to be accessed again soon - e.g., instructions in a loop, induction variables Spatial locality - Items near those accessed recently are likely to be accessed soon E.g., sequential instruction access, array data BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_004.png", |
| "page_index": 229, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-30T22:40:34+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-230-0000": { |
| "id": "CO2007-chapter-5-slide-230-0000", |
| "text": "Taking Advantage of Locality Memory hierarchy Store everything on disk Copy recently accessed (and nearby) items from disk to smaller DRAM memory Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory Cache memory attached to CPU BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_005.png", |
| "page_index": 230, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-30T22:40:36+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-231-0000": { |
| "id": "CO2007-chapter-5-slide-231-0000", |
| "text": "Memory Hierarchy Levels Block (aka line): unit of copying Processor - May be multiple words If accessed data is present in upper level - Hit: access satisfied by upper level Hit ratio: hits/accesses Data is transferreo If accessed data is absent Miss: block copied from lower level Time taken: miss penalty Miss ratio: misses/accesses = 1 - hit ratio Then accessed data supplied from upper level BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6", |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_006.png", |
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| "CO2007-chapter-5-slide-232-0000": { |
| "id": "CO2007-chapter-5-slide-232-0000", |
| "text": "Technology Memory Static RAM (SRAM) 0.5ns - 2.5ns, $500 - $1000 per GiB Dynamic RAM (DRAM) 50ns - 70ns,$3 -$6 per GB Flash Memory - 5us - 50us,$0.06 -$0.12 per GiB Magnetic disk 5ms - 20ms, $0.01 -$0.02 per GiB Ideal memory - Access time of SRAM Capacity and cost/GB of disk BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7", |
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| "CO2007-chapter-5-slide-233-0000": { |
| "id": "CO2007-chapter-5-slide-233-0000", |
| "text": "Cache Memory Cache memory - The level of the memory hierarchy closest to the CPU X4 X4 X1 X1 Xn-2 Xn-2 How do we know if the data is present? Xn-1 Xn-1 Where do we look? X2 X2 Xn X3 X3 a. Before the reference to X. b. After the reference to X, BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_008.png", |
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| }, |
| "CO2007-chapter-5-slide-234-0000": { |
| "id": "CO2007-chapter-5-slide-234-0000", |
| "text": "Direct Mapped Cache Location determined by address Direct mapped: only one choice (Block address) modulo (#Blocks in cache) Cache 80058500 #Blocks is a power of 2 Use low-order address bits 00001 00101 01001 01101 10001 10101 11001 11101 BK Memory TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9", |
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| } |
| }, |
| "CO2007-chapter-5-slide-235-0000": { |
| "id": "CO2007-chapter-5-slide-235-0000", |
| "text": "Tags and Valid Bits How do we know which particular block is stored in a cache location? Store block address as well as the data Actually, only need the high-order bits Called the tag What if there is no data in a location? Valid bit: 1 = present, 0 = not present - Initially 0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_010.png", |
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| }, |
| "CO2007-chapter-5-slide-236-0000": { |
| "id": "CO2007-chapter-5-slide-236-0000", |
| "text": "Cache Example 8-blocks, 1 word/block, direct mapped Initial state Index Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 N 111 N BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 11", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_011.png", |
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| } |
| }, |
| "CO2007-chapter-5-slide-237-0000": { |
| "id": "CO2007-chapter-5-slide-237-0000", |
| "text": "Cache Example Word addr Binary addr Hit/miss Cache block 22 10 110 Miss 110 Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 10 Mem[10110] 111 N BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_012.png", |
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| "CO2007-chapter-5-slide-238-0000": { |
| "id": "CO2007-chapter-5-slide-238-0000", |
| "text": "Cache Example Word addr Binary addr Hit/miss Cache block 26 11 010 Miss 010 Index V Tag Data 000 N 001 N 010 11 Mem[11010] 011 N 100 N 101 N 110 10 Mem[10110] 111 N BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_013.png", |
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| } |
| }, |
| "CO2007-chapter-5-slide-239-0000": { |
| "id": "CO2007-chapter-5-slide-239-0000", |
| "text": "Cache Example Word addr Binary addr Hit/miss Cache block 22 10 110 Hit 110 26 11 010 Hit 010 Index V Tag Data 000 z 001 N 010 11 Mem[11010] 011 N 100 N 101 N 110 10 Mem[10110 111 N BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14", |
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| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_014.png", |
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| "timestamp": "2025-10-30T22:41:06+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-240-0000": { |
| "id": "CO2007-chapter-5-slide-240-0000", |
| "text": "Cache Example Word addr Binary addr Hit/miss Cache block 16 10 000 Miss 000 3 00 011 Miss 011 16 10 000 Hit 000 Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 11 Mem[11010] 011 00 Mem[00011] 100 N 101 N 110 10 Mem[10110] 111 N BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 15", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_015.png", |
| "page_index": 240, |
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| "timestamp": "2025-10-30T22:41:10+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-241-0000": { |
| "id": "CO2007-chapter-5-slide-241-0000", |
| "text": "Cache Example Word addr Binary addr Hit/miss Cache block 18 10 010 Miss 010 Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 10 Mem[10010] 011 00 Mem[00011] 100 N 101 N 110 10 Mem[10110] 111 N BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_016.png", |
| "page_index": 241, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:14+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-242-0000": { |
| "id": "CO2007-chapter-5-slide-242-0000", |
| "text": "Address s Subdivision Address (showing bit positions) 31 30 ... 131211...2 10 Byte offset 20 10 Hit Tag Data Index Index Valid Tag Data 0 1 2 1021 1022 1023 20 32 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 17", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_017.png", |
| "page_index": 242, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:17+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-243-0000": { |
| "id": "CO2007-chapter-5-slide-243-0000", |
| "text": "Example: Larger Block Size 64 blocks, 16 bytes/block To what bytenumber does address 1200 map? 1200 Block address l= 75 16 Block number = 75 modulo 64 = 11 31 10 9 4 3 0 Tag Index Offset 22 bits 6 bits 4 bits BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_018.png", |
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| "timestamp": "2025-10-30T22:41:20+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-244-0000": { |
| "id": "CO2007-chapter-5-slide-244-0000", |
| "text": "Block Size Considerations Larger blocks should reduce miss rate Due to spatial locality But in a fixed-sized cache Larger blocks => fewer of them More competition = increased miss rate - Larger blocks = pollution Larger miss penalty Can override benefit of reduced miss rate Early restart and critical-word-first can help BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_019.png", |
| "page_index": 244, |
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| "timestamp": "2025-10-30T22:41:23+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-245-0000": { |
| "id": "CO2007-chapter-5-slide-245-0000", |
| "text": "Cache Misses On cache hit, CPU proceeds normally On cache miss Stall the CPU pipeline Fetch block from next level of hierarchy Instruction cache miss Restart instruction fetch Data cache miss Complete data access BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_020.png", |
| "page_index": 245, |
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| "timestamp": "2025-10-30T22:41:26+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-246-0000": { |
| "id": "CO2007-chapter-5-slide-246-0000", |
| "text": "Write-Through On data-write hit, could just update the block in cache But then cache and memory would be inconsistent Write through: also update memory But makes writes take longer - e.g., if base CPI = 1, 10% of instructions are stores, write to memory takes 100 cycles Effective CPl = 1 + 0.1x100 = 11 Solution: write buffer Holds data waiting to be written to memory CPU continues immediately Only stalls on write if write buffer is already full BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_021.png", |
| "page_index": 246, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:28+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-247-0000": { |
| "id": "CO2007-chapter-5-slide-247-0000", |
| "text": "Write-Back Alternative: On data-write hit, just update the block in cache Keep track of whether each block is dirty When a dirty block is replaced - Write it back to memory Can use a write buffer to allow replacing block to be read first BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_022.png", |
| "page_index": 247, |
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| "timestamp": "2025-10-30T22:41:30+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-248-0000": { |
| "id": "CO2007-chapter-5-slide-248-0000", |
| "text": "Write Allocation What should happen on a write miss? Alternatives for write-through - Allocate on miss: fetch the block Write around: don't fetch the block Since programs often write a whole block before reading it (e.g., initialization) For write-back Usually fetch the block BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_023.png", |
| "page_index": 248, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:33+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-249-0000": { |
| "id": "CO2007-chapter-5-slide-249-0000", |
| "text": "Example: Intrinsity FastMATH Embedded MIPS processor - 12-stage pipeline Instruction and data access on each cycle Split cache: separate I-cache and D-cache Each 16KB: 256 blocks x 16 words/block D-cache: write-through or write-back SPEC2000 miss rates I-cache: 0.4% - D-cache: 11.4% Weighted average: 3.2% BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24", |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_024.png", |
| "page_index": 249, |
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| "timestamp": "2025-10-30T22:41:36+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-250-0000": { |
| "id": "CO2007-chapter-5-slide-250-0000", |
| "text": "Example: Intrinsity FastMATH Address (showing bit positions) 31 1413...65...210 18 8 4 Byte Data Hit Tag offset Index Block offset 18 bits 512 bits V Tag Data 256 entries 18 32 32 32 Mux 32 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_025.png", |
| "page_index": 250, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:39+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-251-0000": { |
| "id": "CO2007-chapter-5-slide-251-0000", |
| "text": "Main Memory Supporting Caches Use DRAMs for main memory Fixed width (e.g., 1 word) Connected by fixed-width clocked bus Bus clock is typically slower than CPU clock Example cache block read 1 bus cycle for address transfer 15 bus cycles per DRAM access 1 bus cycle per data transfer For 4-word block, 1-word-wide DRAM Miss penalty = 1 + 4x15 + 4x1 = 65 bus cycles Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_026.png", |
| "page_index": 251, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:42+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-252-0000": { |
| "id": "CO2007-chapter-5-slide-252-0000", |
| "text": "Increasing Memory Bandwidth Processor Processor Processor Multiplexor Cache Cache Cache Bus Bus Bus Memory Memory Memory Memory Memory bank 0 bank 1 bank 2 bank 3 b. Wider memory organization c. Interleaved memory organization 4-word wide memory Memory Miss penalty = 1 + 15 + 1 = 17 bus cycles Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle 4-bank interleaved memory Miss penalty = 1 + 15 + 4x1 = 20 bus cycles a. One-word-wide Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle memory organization BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_027.png", |
| "page_index": 252, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:46+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-253-0000": { |
| "id": "CO2007-chapter-5-slide-253-0000", |
| "text": "Measuring Cache Performance Components of CPU time Program execution cycles Includes cache hit time Memory stall cycles Mainly from cache misses With simplifying assumptions: Memory accesses Memory stall cycles = x Miss rate X Miss penalty Program Instructions Misses x Miss penalty X Program Instruction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_028.png", |
| "page_index": 253, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:49+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-254-0000": { |
| "id": "CO2007-chapter-5-slide-254-0000", |
| "text": "Cache Performance e Example Given I-cache miss rate = 2% D-cache miss rate = 4% Miss penalty = 100 cycles Base CPI (ideal cache) = 2 Load & stores are 36% of instructions Miss cycles per instruction I-cache: 0.02 x 100 = 2 - D-cache: 0.36 x 0.04 x 100 = 1.44 ActuaI CPI = 2 + 2 + 1.44 = 5.44 ldeal CPU is 5.44/2 =2.72 times faster BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_029.png", |
| "page_index": 254, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:41:52+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-255-0000": { |
| "id": "CO2007-chapter-5-slide-255-0000", |
| "text": "Average Access Time Hit time is also important for performance Average memory access time (AMAT) AMAT = Hit time + Miss rate x Miss penalty Example CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles, I-cache miss rate = 5% - AMAT = 1 + 0.05 x 20 = 2ns 2 cycles per instruction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_030.png", |
| "page_index": 255, |
| "language": "en", |
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| "CO2007-chapter-5-slide-256-0000": { |
| "id": "CO2007-chapter-5-slide-256-0000", |
| "text": "Performance Summary When CPU performance increased Miss penalty becomes more significant Decreasing base CPI - Greater proportion of time spent on memory stalls Increasing clock rate - Memory stalls account for more CPU cycles Can't neglect cache behavior when evaluating system performance BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 31", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_031.png", |
| "page_index": 256, |
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| "timestamp": "2025-10-30T22:41:57+07:00" |
| } |
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| "CO2007-chapter-5-slide-257-0000": { |
| "id": "CO2007-chapter-5-slide-257-0000", |
| "text": "Associative Caches Fully associative - Allow a given block to go in any cache entry Requires all entries to be searched at once 1 Comparator per entry (expensive) n-way set associative Each set contains n entries Block number determines which set (Block address) modulo (#Sets in cache) Search all entries in a given set at once n comparators (less expensive) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 32", |
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| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_032.png", |
| "page_index": 257, |
| "language": "en", |
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| "timestamp": "2025-10-30T22:42:00+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-258-0000": { |
| "id": "CO2007-chapter-5-slide-258-0000", |
| "text": "Associative Cache Example Direct mapped Set associative Fully associative Block # O 1 2 3 4 5 6 7 Set # 0 2 3 Data Data Data 1 1 1 Tag Tag Tag 2 2 2 Search Search Search BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 33", |
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| "text": "Spectrum of Associativity For a cache with 8 entries One-way set associative (direct mapped) Block Tag Data 0 Two-way set associative 1 Set Tag Data Tag Data 2 0 3 1 4 2 5 3 6 7 Four-way set associative Set Tag Data Tag Data Tag Data Tag Data 0 1 Eight-way set associative (fully associative) Tag Data Tag q Data Tag Data Tag Data Tag Data Tag Data Tag Data Tag Data BK TP.HCM 34 Computer Architecture (c) Cuong Pham-Quoc/HCMU", |
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| "text": "Associativity Example Compare 4-block caches Direct mapped, 2-way set associative, fully associative Block access sequence: 0, 8, 0, 6, 8 Direct mapped Block Cache Cache content after access Hit/miss address index 0 1 2 3 0 0 miss Mem[0] 8 0 miss Mem[8] 0 miss Mem[0] 6 2 miss Mem[0] Mem[6] 8 0 miss Mem[8] Mem[6] BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 35", |
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| "CO2007-chapter-5-slide-261-0000": { |
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| "text": "Associativity Example 2-way set associative Block Cache Cache content after access Hit/miss address index Set 0 Set 1 0 0 miss Mem[0] 8 0 miss Mem[0] Mem[8] 0 hit Mem[0] Mem[8] 6 0 miss Mem[0] Mem[6] 8 0 miss Mem[8] Mem[6] Fully associative Block Hit/miss Cache content after access address 0 miss Mem[0] 8 miss Mem[0] Mem[8] 0 hit Mem[0] Mem[8] 6 miss Mem[0] Mem[8] Mem[6] 8 hit Mem[0] Mem[8] Mem[6] BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 36", |
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| "CO2007-chapter-5-slide-262-0000": { |
| "id": "CO2007-chapter-5-slide-262-0000", |
| "text": "Much Associativity How Increased associativity decreases miss rate But with diminishing returns Simulation of a system with 64KB D-cache, 16-word blocks,SPEC2000 1-way: 10.3% 2-way: 8.6% 4-way: 8.3% 8-way: 8.1% BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 37", |
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| "CO2007-chapter-5-slide-263-0000": { |
| "id": "CO2007-chapter-5-slide-263-0000", |
| "text": "Set Associative Cache Organization Address 3130...12111098...3210 22 8 Tag Index Index V Tag Data V Tag Data V Tag Data V Tag Data 0 1 2 253 254 255 22 32 4-to-1 multiplexor Hit Data BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 38", |
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| "CO2007-chapter-5-slide-264-0000": { |
| "id": "CO2007-chapter-5-slide-264-0000", |
| "text": "Replacement Policy Direct mapped: no choice Set associative Prefer non-valid entry, if there is one - Otherwise, choose among entries in the set Least-recently used (LRU) Choose the one unused for the longest time Simple for 2-way, manageable for 4-way, too hard beyond that Random Gives approximately the same performance as LRU for high - ( associativity BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 39", |
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| "CO2007-chapter-5-slide-265-0000": { |
| "id": "CO2007-chapter-5-slide-265-0000", |
| "text": "Least Recently Used Algorithm Need to keep track of what was used when Keep \"age bits\" for each cache line Update all the \"age bits\" of all cache lines when a cache ine is used -> Pseudo-LRU: use one bit per cache line/block BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 40", |
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| "CO2007-chapter-5-slide-266-0000": { |
| "id": "CO2007-chapter-5-slide-266-0000", |
| "text": "Multilevel Caches Primary cache attached to CPU Small, but fast Level-2 cache services misses from primary cache - Larger, slower, but still faster than main memory Main memory services L-2 cache misses Some high-end systems include L-3 cache BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 41", |
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| "CO2007-chapter-5-slide-267-0000": { |
| "id": "CO2007-chapter-5-slide-267-0000", |
| "text": "Multilevel Cache Example Given - CPU base CPl = 1,clock rate = 4GHz Miss rate/instruction = 2% Main memory access time = 100ns With just primary cache Miss penalty = 100ns/0.25ns = 400 cycles Effective CPl = 1 + 0.02 x 400 = 9 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 42", |
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| "id": "CO2007-chapter-5-slide-268-0000", |
| "text": "Example (cont.) Now add L-2 cache - Access time = 5ns Global miss rate to main memory = 0.5% Primary miss with L-2 hit Penalty = 5ns/0.25ns = 20 cycles Primary miss with L-2 miss Extra penalty = 400 cycles CPl = 1 + 0.02 x 20 + 0.005 x 400 = 3.4 Performance ratio = 9/3.4 = 2.6 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 43", |
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| "CO2007-chapter-5-slide-269-0000": { |
| "id": "CO2007-chapter-5-slide-269-0000", |
| "text": "Multilevel Cache Considerations Primary cache - Focus on minimal hit time L-2 cache - Focus on low miss rate to avoid main memory access Hit time has less overall impact Results - L-1 cache usually smaller than a single cache - L-1 block size smaller than L-2 block size BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 44", |
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| "CO2007-chapter-5-slide-270-0000": { |
| "id": "CO2007-chapter-5-slide-270-0000", |
| "text": "Interactions with Advanced CPUs Out-of-order CPUs can execute instructions during cache miss Pending store stays in load/store unit Dependent instructions wait in reservation stations Independent instructions continue Effect of miss depends on program data flow Much harder to analyse Use system simulation BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 45", |
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| "id": "CO2007-chapter-5-slide-271-0000", |
| "text": "Interactions with Software 1200 Radix Sort 1000 Misses depend on 800 600 memory access patterns 400 Quicksort 200 0 Algorithm behavior 4 8 16 32 64 128 256 512102420484096 a. Size K items to sort) 2000 Compiler optimization Radix Sort 1600 for memory access 1200 800 400 Quicksort 0 4 8 16 32 64 128 256512102420484096 b. Size (K items to sort) Radix Sort 3 2 Quicksort 0 4 8 16 32 64 128 256 512 102420484096 SizeK items to sort) C. BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 46", |
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| "CO2007-chapter-5-slide-272-0000": { |
| "id": "CO2007-chapter-5-slide-272-0000", |
| "text": "Software Optimization via Blocking Goal: maximize accesses to data before it is replaced Consider inner loops of DGEMM: 1. for (int i = O; i< n;++i) 2. for (int j = O: j < n; ++j)t 3. double cij = C[i+j*n] 4. for( int k= O;k< n; k++) 5. cij += A[i+k*n]* B[k+j*n] 6. C[i+j*n] = cij 7. } BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 47", |
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| "CO2007-chapter-5-slide-273-0000": { |
| "id": "CO2007-chapter-5-slide-273-0000", |
| "text": "DGEMM Access Pattern C,A, and B arrays older accesses new accesses j k j x y z 0 1 2 3 4 5 O 1 2 3 4 5 0 1 2 3 4 5 0 0 1 1 1 2 2 2 k 3 3 3 4 4 4 5 5 5 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 48", |
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| "CO2007-chapter-5-slide-274-0000": { |
| "id": "CO2007-chapter-5-slide-274-0000", |
| "text": "Cache Accessed in DGEMM Cache miss depends on N For example: - N = 32, each element 8 bytes Three matrix 24KB (32x32x8x3 Core i7 Sandy Bridge: 32KB What would happen when N is increased? What would happen if matrices is divided into N-by-N Bocks BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 49", |
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| "CO2007-chapter-5-slide-275-0000": { |
| "id": "CO2007-chapter-5-slide-275-0000", |
| "text": "Cache Bocked DGEMM 1.#define BLOCKSIZE 32 2.void do_block (int n, int si, int sj, int sk, double *A, double *B, double *C{ 3. for (int i = si; i < si+BLOCKSIZE: ++i) 4. for (int j = sj; j< sj+BLOCKSIZE; ++j 5. double cij = C[i+j*n];/* cij = C[i][j]*7 6. for( int k= sk; k< sk+BLOCKSIZE;k++) 7. cij += A[i+k*n]* B[k+j*n];/* cij+=A[i][k]*B[k][j]*/ 8. C[i+j*n] = cij;/* C[i][j] = cij *7 10.} 12.void dgemm (int n,double* A,double* B, double* C{ 13.for ( int sj = O;sj< n; sj +=BLOCKSIZE) 14. for ( int si = O;si< n; si += BLOCKSIZE ) 15. for(int sk= O;sk< n; sk+= BLOCKSIZE) 16. do_block(n,si,sj,sk, A, B, C) 17.} BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 50", |
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| "CO2007-chapter-5-slide-276-0000": { |
| "id": "CO2007-chapter-5-slide-276-0000", |
| "text": "Bocked DGEMM Access Pattern j k j x y z 0 1 2 3 4 5 O 1 2 3 4 5 0 1 2 3 4 5 O O 1 1 1 2 2 2 k 3 3 3 4 4 4 5 5 5 0 32x32 160x160 480x480 960x960 1.8 1.7 1.7 1.6 1.6 1.5 1.5 1.5 1.3 CCEOOS 1.2 0.8. 0.9 0.6 0.3 Unoptimized Blocked BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 51", |
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| "CO2007-chapter-5-slide-277-0000": { |
| "id": "CO2007-chapter-5-slide-277-0000", |
| "text": "Virtual Memory Use main memory as a \"cache\" for secondary (disk) storage Managed jointly by CPu hardware and the operating system (OS) Each gets a private virtual address space holding its frequently used code and data Protected from other programs CPU and OS translate virtual addresses to physical addresses - VM \"block\" is called a page - VM translation \"miss\" is called a page fault BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 52", |
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| "CO2007-chapter-5-slide-278-0000": { |
| "id": "CO2007-chapter-5-slide-278-0000", |
| "text": "Address Translation Fixed-size pages (e.g.,4K) Virtual address Virtual addresses Physical addresses 31 30 29 28 27 15 14 131211 109.8 3 21 0 Address translation Virtual page number Page offset Translation Disk addresses 29 28 27 15 14.1312 11 10.9.8 3 2 1 0 Physical page number Page offset Physical address BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 53", |
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| "CO2007-chapter-5-slide-279-0000": { |
| "id": "CO2007-chapter-5-slide-279-0000", |
| "text": "Page Fault Penalty On page fault, the page must be fetched from disk Takes millions of clock cycles - Handled by OS code Try to minimize page fault rate Fully associative placement Smart replacement algorithms BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 54", |
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| "CO2007-chapter-5-slide-280-0000": { |
| "id": "CO2007-chapter-5-slide-280-0000", |
| "text": "Page Tables Stores placement information - Array of page table entries, indexed by virtual page number - Page table register in CPU points to page table in physical memory If page is present in memory - PTE stores the physical page number Plus other status bits (referenced, dirty, ...) If page is not present - PTE can refer to location in swap space on disk BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 55", |
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| "CO2007-chapter-5-slide-281-0000": { |
| "id": "CO2007-chapter-5-slide-281-0000", |
| "text": "Translation Using a Page Table Page table register Virtual address 31 30 29 28 15 14 13 12 1 1 1.0 3 2 1 0 Virtual page number Page offset 20 12 Valid Physical page number Page table 18 If o then page is not present in memory 29 28 27 13 12 0 8. .3 Physical page number Page offset Physical address BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 56", |
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| "CO2007-chapter-5-slide-282-0000": { |
| "id": "CO2007-chapter-5-slide-282-0000", |
| "text": "Mapping Pages to Storage Virtual page number Page table Physical page or Physical memory Valid disk address 1 1 1 1 0 1 1 0 1 Disk storage 1 0 1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 57", |
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| "CO2007-chapter-5-slide-283-0000": { |
| "id": "CO2007-chapter-5-slide-283-0000", |
| "text": "Replacement and Writes To reduce page fault rate, prefer least-recently used (LRU) replacement Reference bit (aka use bit) in PTE set to 1 on access to page F Periodically cleared to 0 by Os - A page with reference bit = 0 has not been used recently Disk writes take millions of cycles Block at once, not individual locations - Write through is impractical Use write-back Dirty bit in PTE set when page is written BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 58", |
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| "CO2007-chapter-5-slide-284-0000": { |
| "id": "CO2007-chapter-5-slide-284-0000", |
| "text": "Fast Translation Using a TLB Address translation would appear to require extra memory references One to access the PTE Then the actual memory access But access to page tables has good locality - So use a fast cache of PTEs within the CPU Called a Translation Look-aside Buffer (TLB) Typical: 16-512 PTEs, 0.5-1 cycle for hit, 10-100 cycles for miss, 0.01%-1% miss rate Misses could be handled by hardware or software BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 59", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_059.png", |
| "page_index": 284, |
| "language": "en", |
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| } |
| }, |
| "CO2007-chapter-5-slide-285-0000": { |
| "id": "CO2007-chapter-5-slide-285-0000", |
| "text": "Fast Translation Using a TLB TLB Virtual page Physical page number Valid Dirty Ref Tag address 1 0 1 1 1 1 Physical memory 1 1 1 1 0 1 0 0 0 1 0 1 Page table Physical page Valid Dirty Ref or disk address 1 0 1 1 0 0 Disk storage 1 0 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 60", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_060.png", |
| "page_index": 285, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-31T05:22:43+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-286-0000": { |
| "id": "CO2007-chapter-5-slide-286-0000", |
| "text": "TLB and Cache Interaction Virtual address 313029 14131211109 3210 Virtual page number Page offset If cache tag uses physical 20 112 Valid Dirty Tag Physical page numbe address TLB 00000 TLB hit - Need to translate before 20 cache lookup Physical page number Page offset Alternative: use virtual Physical address Block Physical address tag Byte Cache index offset offset 18 18 14 2 address tag 8 Complications due to Data - 0 Valid Tag aliasing Cache Different yirtual addresses for shared. Cache hit physical address 32 BK Data TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 61", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_061.png", |
| "page_index": 286, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-31T05:22:53+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-287-0000": { |
| "id": "CO2007-chapter-5-slide-287-0000", |
| "text": "TLB Misses If page is in memory Load the PTE from memory and retry Could be handled in hardware Can get complex for more complicated page table structures Or in software Raise a special exception, with optimized handler If page is not in memory (page fault) - Os handles fetching the page and updating the page table - Then restart the faulting instruction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 62", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_062.png", |
| "page_index": 287, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-31T05:22:57+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-288-0000": { |
| "id": "CO2007-chapter-5-slide-288-0000", |
| "text": "TLB Miss Handler TLB miss indicates Page present, but PTE not in TLB Page not preset Must recognize TLB miss before destination register overwritten - Raise exception Handler copies PTE from memory to TLB Then restarts instruction If page not present, page fault will occur BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 63", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_063.png", |
| "page_index": 288, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:00+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-289-0000": { |
| "id": "CO2007-chapter-5-slide-289-0000", |
| "text": "Page Fault Handler Use faulting virtual address to find PTE Locate page on disk Choose page to replace - If dirty, write to disk first Read page into memory and update page table Make process runnable again Restart from faulting instruction BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 64", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_064.png", |
| "page_index": 289, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:03+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-290-0000": { |
| "id": "CO2007-chapter-5-slide-290-0000", |
| "text": "Memory Protection Different tasks can share parts of their virtual address spaces But need to protect against errant access Requires OS assistance Hardware support for Os protection - Privileged supervisor mode (aka kernel mode) Privileged instructions Page tables and other state information only accessible in supervisor mode - System call exception (e.g., syscall in MIPs) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 65", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_065.png", |
| "page_index": 290, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:09+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-291-0000": { |
| "id": "CO2007-chapter-5-slide-291-0000", |
| "text": "The Memory Hierarchy The BlG Picture Common principles apply at all levels of the memory hierarchy Based on notions of caching At each level in the hierarchy Block placement Finding a block Replacement on a miss - Write policy BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 66", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_066.png", |
| "page_index": 291, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:12+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-292-0000": { |
| "id": "CO2007-chapter-5-slide-292-0000", |
| "text": "Exercise Given the TLB (fully associative) and the V Physical or V Tag Physical Page table (4KB pages) with LRU Disk 1 11 12 replacement 1 5 1 7 4 0 Disk If pages must be brought from disk, 1 3 6 increment the next largest page 0 Disk 0 4 9 number 1 6 1 9 Show the final state of the TLB and Page 1 11 table if virtual address requests are as 0 Disk follow: 1 4 - 4669,2227,13916,34587,48870 0 Disk 12608,49225 0 Disk 12948,49419,46814,13975,40004 1 3 12707,52236 1 12 The same question but 16KB pages instead of 4KB Hint: Analyse the virtual address to extract virtual page number BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 67", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_067.png", |
| "page_index": 292, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:18+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-293-0000": { |
| "id": "CO2007-chapter-5-slide-293-0000", |
| "text": "Solution Virtual address (decimal): 4669, 2227, 13916, 34587, 48870, 12608,49225 Binary address: 4KB pages => 12-bit page offset 4669 = 1 0010 0011 1101,VPN = 1 2227 = 0 1000 1011 0011,VPN = 0 13916 = 11 0110 0101 1100, VPN = 3 34587 = 1000 0111 0001 1011,VPN = 8 48870 = 1011 1110 1110 0110, VPN = 11 12608 = 11 0001 0100 0000,VPN = 3 49225 = 1100 0000 0100 1001,VPN = 12 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 68", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_068.png", |
| "page_index": 293, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:21+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-294-0000": { |
| "id": "CO2007-chapter-5-slide-294-0000", |
| "text": "TLB Address Virtual Page TLB H/M Valid Tag Physical Page 1 11 12 TLB miss 4669 1 1 7 4 PT hit 1 3 6 PF 1 (last access 0) 1 13 1 (last access 1) 0 5 1 7 4 TLB miss 2227 0 PT hit 1 3 6 1 (last access 0) 1 13 1 (last access 1) 0 5 1 7 4 13916 3 TLB hit 1 (last access 2) 3 6 1 (last access 0) 1 13 1 (last access 1) 0 5 TLB miss 1 (last access 3) 8 14 34587 8 PT hit 1 (last access 2) 3 6 PF 1(last access 0) 1 13 1 (last access 1) 0 5 1 (last access 3) 8 14 TLBmiss 48870 11 PT hit 1 (last access 2) 3 6 1 (last access 4) 11 12 1 (last access 1) 0 5 1 (last access 3) 8 14 12608 3 TLB hit 1 (last access 5 3 6 1 (last access 4) 11 12 1 (last access 6) 12 15 1 (last access 3) 8 14 TLB miss 49225 12 BK PT miss 1 (last access 5 3 6 TP.HCM 69 1 (last access 4) 11 12", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_069.png", |
| "page_index": 294, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:32+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-295-0000": { |
| "id": "CO2007-chapter-5-slide-295-0000", |
| "text": "TLB Address Virtual Page TLB H/M Valid Tag Physical Page 1 11 12 1 7 4 TLB miss 4669 0 PT hit 1 3 6 1 (last access 0) 0 5 1 11 12 1 7 4 2227 0 TLB hit 1 3 6 1 (last access 1) 0 5 1 11 12 1 7 4 13916 0 TLB hit 1 3 6 1 (last access 2) 0 5 1 (last access 3) 2 13 TLB miss 1 7 4 34587 2 PT hit 1 3 6 PF 1 (last access 2) 0 5 1 (last access 4) 2 13 1 7 4 48870 2 TLB hit 1 3 6 1 (last access 2) 0 5 1 (last access 4) 2 13 1 7 4 12608 0 TLB hit 1 3 6 1 (last access 5) 0 5 1 (last access 4) 2 13 1 7 4 49225 3 TLB hit BK 1 (last axxess 6) 3 6 TP.HCM 70 1 (last access 5) 0 5", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_070.png", |
| "page_index": 295, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-31T05:23:41+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-296-0000": { |
| "id": "CO2007-chapter-5-slide-296-0000", |
| "text": "Block Placement Determined by associativity Direct mapped (1-way associative) One choice for placement n-way set associative n choices within a set Fully associative Any location Higher associativity reduces miss rate - Increases complexity, cost, and access time BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 71", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_071.png", |
| "page_index": 296, |
| "language": "en", |
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| "timestamp": "2025-10-31T05:23:43+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-297-0000": { |
| "id": "CO2007-chapter-5-slide-297-0000", |
| "text": "Finding a Block Hardware caches - Reduce comparisons to reduce cost Virtual memory - Full table lookup makes full associativity feasible Benefit in reduced miss rate Associativity Location method Tag comparisons Direct mapped Index 1 n-way set associative Set index, then search entries n within the set Fully associative Search all entries #entries Full lookup table BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 72", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_072.png", |
| "page_index": 297, |
| "language": "en", |
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| "timestamp": "2025-10-31T05:23:48+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-298-0000": { |
| "id": "CO2007-chapter-5-slide-298-0000", |
| "text": "Replacement Choice of entry to replace on a miss - Least recently used (LRU) Complex and costly hardware for high associativity - Pseudo-LRU Close to LRU, less costly hardware - Random Close to LRU, easier to implement Virtual memory - LRU approximation with hardware support BK TP.HCM 73 Computer Architecture (c) Cuong Pham-Quoc/HCMUT", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_073.png", |
| "page_index": 298, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-31T05:23:50+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-299-0000": { |
| "id": "CO2007-chapter-5-slide-299-0000", |
| "text": "Write Policy Write-through - Update both upper and lower levels - Simplifies replacement, but may require write buffer Write-back - Update upper level only Update lower level when block is replaced Need to keep more state Virtual memory - Only write-back is feasible, given disk write latency BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 74", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_074.png", |
| "page_index": 299, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
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| "timestamp": "2025-10-31T05:23:53+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-300-0000": { |
| "id": "CO2007-chapter-5-slide-300-0000", |
| "text": "Sources of Misses Compulsory misses (aka cold start misses) First access to a block Capacity misses Due to finite cache size A replaced block is later accessed again Conflict misses (aka collision misses) - In a non-fully associative cache Due to competition for entries in a set - Would not occur in a fully associative cache of the same total size BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 75", |
| "metadata": { |
| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_075.png", |
| "page_index": 300, |
| "language": "en", |
| "ocr_engine": "PaddleOCR 3.2", |
| "extractor_version": "1.0.0", |
| "timestamp": "2025-10-31T05:23:57+07:00" |
| } |
| }, |
| "CO2007-chapter-5-slide-301-0000": { |
| "id": "CO2007-chapter-5-slide-301-0000", |
| "text": "Concluding Remarks Fast memories are small, large memories are slow - We really want fast, large memories - Caching gives this illusion Principle of locality - Programs use a small part of their memory space frequently Memory hierarchy - L1 cache < > L2 cache < > ... < > DRAM memory < > disk Memory system design is critical for multiprocessors BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 76", |
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| "doc_type": "slide", |
| "course_id": "CO2007", |
| "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_5/slide_076.png", |
| "page_index": 301, |
| "language": "en", |
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| "timestamp": "2025-10-31T05:23:59+07:00" |
| } |
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| } |
