{ "course": "Computer_Architecture", "course_id": "CO2007", "schema_version": "material.v1", "slides": [ { "page_index": 0, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_001.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_001.png", "page_index": 0, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:25:53+07:00" }, "raw_text": "COMPUTER R ARCHITECTURE Introduction BK Computer Engineering - CSE - HCMUT 1 TP.HCM" }, { "page_index": 1, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_002.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_002.png", "page_index": 1, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:25:56+07:00" }, "raw_text": "Administrative issues Instructor: - Assoc. Prof. Dr. Cuong Pham-Quoc (in Vietnamese Pham Quöc Cung) Computer Engineering Department, Faculty of Computer Science and Engineering, HCMUT Email: cuongpham@hcmut.edu.vn Homepage: www.cse.hcmut.edu.vn/cuongpham BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2" }, { "page_index": 2, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_003.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_003.png", "page_index": 2, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:25:58+07:00" }, "raw_text": "Computer Q: What is a Computer? - A: \"an electronic machine that is used for storing, organizing, and finding words, numbers, and pictures, for doing calculations, and for controlling other machines\" - Cambridge dictionary A: \"a general-purpose device that can be programmed to carry out a set of arithmetic or logical operations automatically\" - Wikipedia Abacus BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3" }, { "page_index": 3, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_004.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_004.png", "page_index": 3, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:03+07:00" }, "raw_text": "Computer architecture Q: What is Computer Architecture? A: \"the science and art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals\" - WWW Computer Architecture Page jump target branch target result bus fetch decode execute writeback branch PC logic op2 alu regfile op1 fw2 w_m decode logic fw1 w_e pmem dmem bop addr addr din dout dout ext addrWext dout ext din BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4" }, { "page_index": 4, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_005.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_005.png", "page_index": 4, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:05+07:00" }, "raw_text": "The course Elementary course for both Computer Engineering and Computer Science programs Contents: - Performance evaluation Instruction set architecture Computer arithmetic Data-path and control signals Memory & l/O system Multicores, Multiprocessors, and Clusters BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5" }, { "page_index": 5, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_006.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_006.png", "page_index": 5, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:07+07:00" }, "raw_text": "Outcomes Outcomes: Understand the structure, organization of a computer system: the main components and the basic principles of its operations Write and optimize small programs and fragments of codes to demonstrate an understanding of machine leve operation BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6" }, { "page_index": 6, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_007.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_007.png", "page_index": 6, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:14+07:00" }, "raw_text": "Learning materials Slides/handouts BKEL DAIHOC QUOCGIA TP HO CHI MINH TRUONGDAIHOCBACHKHOA www.cse.hcmut.edu.vn/cuongpham Textbooks Cepyighted Materia KIENTRUC COMPUTER ORGANIZATION MAY TiNH swap: multi $2, $5,4 AND DESIGN add$2,$4,$2 lw $15, 0$2) lw $16, 4$2) SW $16, 0$2) SW $15, 4($2) THE HARDWARE/SOFTWARE INTERFACE jr $31 5 bit 32bit acv ngun 1 Lenh Du lieu 1 Toar FIFTHEDTIO DAVIDA PATTERSON 5 bit hang 1 zero Ghbonho # nguon 2 JOHN LHENNESSY 32 bit 5 bit ALU 32. Dir 32 bi # dich Ke Dia chi lieu 32 bit De lieu2 qua 32bit Da DE li@u ghi ang B nhó Tap thanhghi vao dulieu Ghi thanh gh Doc ba nho PHAM Quóc Cuöng M< NHA XUAT BAN DAI HOC QUOC GIA TP HO CHi MINH Copyright BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7" }, { "page_index": 7, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_008.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_008.png", "page_index": 7, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:16+07:00" }, "raw_text": "Assessment Assignment: 30% Labs: 10% (mandatory) Mid-term: 20% - multiple choices/writing, with 1 A4 piece of paper note Final exam: 40% - multiple choices/writing, with 2 A4 piece of paper note BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8" }, { "page_index": 8, "chapter_num": 0, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_009.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_0/slide_009.png", "page_index": 8, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:18+07:00" }, "raw_text": "In-class regulations C 1o handout #202334458 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9" }, { "page_index": 9, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_001.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_001.png", "page_index": 9, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:21+07:00" }, "raw_text": "COMPUTER ARCHITECTURE Chapter 1: Technology & Performance evaluation BK Computer Engineering - CSE - HCMUT TP.HCM" }, { "page_index": 10, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_002.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_002.png", "page_index": 10, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:22+07:00" }, "raw_text": "TECHNOLOGY REVIEW BK TP.HCM 2" }, { "page_index": 11, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_003.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_003.png", "page_index": 11, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:25+07:00" }, "raw_text": "The computer revolution The third revolution along with agriculture and industry Progress in computer technology Underpinned by Moore's Law Makes novel applications feasible Computers in automobiles - Cell phones - Human genome project - World Wide Web Search Engines ABACUS Computers are pervasive BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3" }, { "page_index": 12, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_004.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_004.png", "page_index": 12, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:36+07:00" }, "raw_text": "The Moore's Law 50,000,000,000 72-core Xeon Phi Centriq 2400 GC2IPU SPARC M7 32-core AMD Epyc IBM z13 Storage Controller. Apple A12X Bionic 10,000,000,000 18-core Xeon Haswell-E5 + Tegra Xavier SoC Qualcomm Snapdragon 8cx/SCX8180 Xbox One main SoC 5,000,000,000 HiSilicon Kirin 980+Apple A12 Bionic 12-core POWER8 HiSilicon Kirin 710 8-coreXeon Nehalem-EX 10-core Core i7 BroadwellE Six-coreXeon 7400 QualcommSnapdragon 835 Dual-core Itanium 2 Dual-core+GPU Iris Core i7 Broadwell-U Quad-core + GPU GT2 Core i7 Skylake K 1,000,000,000 Pentium D Presler POWER6 Quad-core+ GPU Core i7 Haswell Itanium 2with Apple A7 (dual-core ARM64\"mobile SoC\" 500,000,000 9MB cache Core i7 (Quad) Itanium2Madison 6M AMD K10 quad-core 2M L3 Core 2 Duo'Wolfdale Pentium D Smithfield Itanium 2McKiniey Core 2.Duo Conroe Core 2 Duo Wolfdale 3M Pentium 4Prescott-2M Core 2 Duo Allendale 100,000,000 Pentium 4Cedar Mill 50.000.000 Pentium 4Willamette Atom ARM Cortex-A9 AMD K6-IiI 10,000,000 Pentiym IlIl Katma Pentium Pro PentiumII Deschutes 5,000,000 Pentiumg oKlamath AMD K5 + Intel 80486 1,000,000 + R4000 500,000 ARM700 Intel 80386 Intel ARM3 Motorola 68020 i960 100,000 MultiTitan Motorola Intel80286 68000 50,000 Intel 80186 Intel8086 ntel 8088 ARM2 ARM6 Motorola WDC 65C816 6809 Novix Gordon Moore 10,000 TMS.1000 Zilog Z80. & WD NC4016 A RCA.1802 65C02 5,000 Intel8085 Intel8008 Intel 8080 MQS Technology Intel co-founder Motorola 6502 Intel 4004 6800 Our World 1,000 in Data 4829849869889908298499g98202002 4080 t 1 2018 The number of transistors integrated in a chip has doubled every 18-24 months (1975) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4" }, { "page_index": 13, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_005.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_005.png", "page_index": 13, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:41+07:00" }, "raw_text": "Intel processors As of Q1/2023 intel. intel intel. Raptor Lake: 13th CORe CORe generation CORC 10 nm technology i5 i3 i7 Intel\" Core i9 Intel\" Core i7 Intel\" Core i5 Intel Core i3 Processors Processors Processors Processors Max Turbo Frequency Up to 5.8 Up to 5.4 Up to 5.1 Up to 4.5 [GHz] Intel Turbo Boost Max Up to 5.7 Up to 5.4 n/a n/a Technology 3.0 Frequency [GHz] Performance-core Max Up to 5.4 Up to 5.3 Up to 5.1 Up to 4.5 Turbo Frequency [GHz] BK TP.HCM 5" }, { "page_index": 14, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_006.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_006.png", "page_index": 14, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:45+07:00" }, "raw_text": "History... The first computer in the world II BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6" }, { "page_index": 15, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_007.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_007.png", "page_index": 15, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:48+07:00" }, "raw_text": "History... Facts of ENIAC: 30+ tons -: 1,500+ square feet (140 square meter) 18,000+ vacuum tubes 140+ KW power 5,000+ additions per second ENIAC: Electronic Numerical Integrator and Computer BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7" }, { "page_index": 16, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_008.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_008.png", "page_index": 16, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:51+07:00" }, "raw_text": "A Brief History of Computers The first generation - Vacuum tubes - 1946- 1955 The second generation Transistors EZ80 AFEINHOULA 1955 - 1965 The third generation 1965- 1980 Integrated circuits The current generation 1980 - ... - Personal computers What's the next? - Quantum computers? Areplica of the first transistor microeiectronicsgroup O December 23.1947 Lucent Technologies 50 Years and Counting. - Memristor? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 8" }, { "page_index": 17, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_009.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_009.png", "page_index": 17, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:26:55+07:00" }, "raw_text": "Classes of Computers Personal computers General purpose, variety of software Subject to cost/performance tradeoff Server computers - Network based - High capacity, performance, reliability Range from small servers to building sized Supercomputers High-end scientific and engineering calculations Highest capability but represent a small fraction of the overall computer market Embedded computers Hidden as components of systems - Stringent power/performance/cost constraints 18 16 15 2 3 12 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9" }, { "page_index": 18, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_010.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_010.png", "page_index": 18, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:00+07:00" }, "raw_text": "Post PC era 3000 Tablets 2500 Smartphones 272.6 249.2 2000 276.7 256 PCs 229.7 1500 227.3 145 11942 1000 76 725.3 494.5 500 304.7 358 364 349 315.3 308.1 276.7 256.1 272.6 249.1 0 2010 2011 2012 2013 2014 2015 2016* 2019* 2020* The number of devices (millions) shipped - source: statista.com BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10" }, { "page_index": 19, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_011.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_011.png", "page_index": 19, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:04+07:00" }, "raw_text": "Modern computer components Same components for all kinds Compiler Components - Processor Interface Datapath Computer controller Memory Input Main memory Cache Control Input/Output Datapath Evaluating performance User-interface Output Network Processor Memory Storage BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 11" }, { "page_index": 20, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_012.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_012.png", "page_index": 20, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:06+07:00" }, "raw_text": "Below your program Application software - Written in high-level language System software Compiler: translates HLL code to machine code Operating System: service code Handling input/output Hardware Managing memory and storage Scheduling tasks & sharing resources Hardware - Processor, memory, I/o controllers BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12" }, { "page_index": 21, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_013.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_013.png", "page_index": 21, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:12+07:00" }, "raw_text": "Levels of Program Code High-level swap(int v[l, int k language tint temp; High-level language program temp = v[k]; (in C) v[k] = v[k+1]; v[k+1] = temp; Level of abstraction closer to problem domain Compiler Provides for productivity and portability Assembly swap: language muli $2, $5,4 Assembly language program add $2, $4,$2 (for MIPS) 1w $15, 0($2) 1w $16, 4($2) SW $16, 0($2) Textual representation of SW $15, 4($2) jr $31 instructions Hardware representation Assembler Binary digits (bits) Binary machine 00000000101000010000000000011000 Encoded instructions and language 00000000000110000001100000100001 program 10001100011000 0000000000000 data (for MIPS) 10001100111100 00000000000100 10101100111100 00000000000000 10101100011000 10000000000100 BK 0000001111100 00000000001000 TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13" }, { "page_index": 22, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_014.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_014.png", "page_index": 22, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:17+07:00" }, "raw_text": "Technology trends 10,000,000 4G 1,000,000 2G 1G Thanks to electronics and 100,000 512M 16M 64M 10,000 4M material technologies 1M 1000 256K 64K - Increased capacity and 100 16K 10 19761978 1980 19821984 19861988 1990 1992 1994 19961998 2000 2002 2004 2006 2008 2010 2012 performance Year of introduction DRAM capacity Reduced cost Year Technology Relative performance/cost 1951 Vacuum tube 1 1965 Transistor 35 1975 Integrated circuit (IC) 900 1995 Very large scale lC (VLSI) 2,400,000 2013 Ultra large scale IC 250,000,000,000 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14" }, { "page_index": 23, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_015.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_015.png", "page_index": 23, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:18+07:00" }, "raw_text": "PERFORMANCE EVALUATION BK TP.HCM 15" }, { "page_index": 24, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_016.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_016.png", "page_index": 24, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:23+07:00" }, "raw_text": "Defining performance Which airplane has the best performance? Boeing 777 Boeing 777 Boeing 747 Boeing 747 BAC/Sud BAC/Sud Concorde Concorde Douglas Dc- Douglas DC- 8-50 8-50 0 100 200 300 400 500 0 2000 4000 6000 8000 10000 l Passenger Capacity Cruising Range (miles) Boeing 777 Boeing 777 Boeing 747 Boeing 747 BAC/Sud BAC/Sud Concorde Concorde Douglas DC- Douglas DC- 8-50 8-50 0 500 1000 1500 0 100000 200000 300000 400000 Cruising Speed (mph) Passengers x mph BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16" }, { "page_index": 25, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_017.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_017.png", "page_index": 25, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:26+07:00" }, "raw_text": "Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/... per hour How are response time and throughput affected by Replacing the processor with a faster version? - Adding more processors? We'll focus on response time for now... BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 17" }, { "page_index": 26, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_018.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_018.png", "page_index": 26, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:29+07:00" }, "raw_text": "Relative performance 1 Performance = Execution time Computer X is n times faster than Computer Y Performancex Execution timey : n Performancey Execution timex Example: time take to run a program 10s on A and 15s on B ExecutionB 15s A is 1.5 x faster than B because = 1.5 x ExecutionA 10s BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18" }, { "page_index": 27, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_019.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_019.png", "page_index": 27, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:32+07:00" }, "raw_text": "Measuring time Elapsed time - Total response time, including all aspects Processing, I/O, Os overhead, idle time Determines system performance CPU time - Time spent processing a given job Discounts I/O time, other jobs' shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19" }, { "page_index": 28, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_020.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_020.png", "page_index": 28, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:34+07:00" }, "raw_text": "Measuring CPU time Operations of digital hardware (including CPU/processor) governed by a constant-rate clock Clock period Clock (cycles) Data transfer and computation Update state - Clock period (T): duration of a clock cycle s, ms, us, ns Clock rate/frequency (F = - the number of cycles per second 1 Hz,KHz,MHz,GHz BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20" }, { "page_index": 29, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_021.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_021.png", "page_index": 29, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:37+07:00" }, "raw_text": "CPU time Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count CPU Time = CPU Clock Cycles X Clock Cycle Time CPU Clock Cycles Clock Rate BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21" }, { "page_index": 30, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_022.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_022.png", "page_index": 30, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:39+07:00" }, "raw_text": "CPU time example Computer A: 2GHz clock, 10s CPU time Designing Computer B - Aim for 6s CPU time - Can do faster clock, but causes 1.2 x clock cycles How fast must Computer B clock be? CPU TimeA = Clock RateA 2.0GHz CPU Clock CyclesB CpU TimeB = Clock RateB Clock RateB => Clock RateB = 4.0GHz BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22" }, { "page_index": 31, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_023.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_023.png", "page_index": 31, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:43+07:00" }, "raw_text": "Instruction count & CPl Instruction Count for a program Determined by program, IsA and compiler Average cycles per instruction Determined by CPU hardware - If different instructions have different CPI Average CPI affected by instruction mix Clock Cycles = Instruction count X Cycles per Instruction CPU Time = Instruction count X Cycles per Instruction X Clock Cycle Time Instruction count X Cycles per Instruction IC X CPI Clock Rate Clock Rate BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23" }, { "page_index": 32, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_024.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_024.png", "page_index": 32, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:46+07:00" }, "raw_text": "Example Which is faster, and by how much? - Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same IsA, compiler CPU TimeA = ICa X CPlA X Cycle TimeA = IC x 2.0 x 250ps CPU TimeB = ICB X CPlB X Cycle TimeB = IC x 1.2 x 500ps CPU TimeB IC x 600ps = 1.2 X CPU TimeA IC X 500ps BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24" }, { "page_index": 33, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_025.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_025.png", "page_index": 33, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:49+07:00" }, "raw_text": "Mixed instructions CPI CPl for instructions/operations may vary - e.g.,: multiplication takes more cycles than addition More precise CPU clock cycles should take instruction types into account n Clock cycles = (CPI; X Instruction counti) i=1 Weighted average CPI n Clock cycles Instruction count (CPI; X CPl = Instruction count Instruction count i=1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25" }, { "page_index": 34, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_026.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_026.png", "page_index": 34, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:52+07:00" }, "raw_text": "Example Question: two implementations of an application that use instructions in classes A, B, and C as follows. Which one is better? Implementation 1 uses 2 A, 1 B, and 2 C Implementation 2 uses 4 A, 1 B, and 1 C CPls for A, B, and C are 1, 2, and 3, respectively Answer: lmplementation 1: clock cycles1 = 2 x 1 + 1 x 2 + 2 x 3 = 10 lC = 5,wCPI = 2.0 - lmplementation 2: clock cycles, = 4 x 1 + 1 x 2 + 1 x 3 = 9 lC = 6,wCPl =1.5 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26" }, { "page_index": 35, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_027.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_027.png", "page_index": 35, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:55+07:00" }, "raw_text": "Exercise A program is executed on a 2 GHz CPU. The program consists of 1000 instructions in which: 30% load/store instructions, CPl = 2.5 10% jump instructions, CPI = 1 20% branch instructions, CPl = 1.5 The rest are arithmetic instructions, CPI = 2.0 a) What is execution time (cPU time) of the program? b) What is the weighted average CPI of the program? c) If load/store instructions are improved so that their execution time is reduced by a factor of 2, what is the speed-up of the system? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27" }, { "page_index": 36, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_028.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_028.png", "page_index": 36, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:27:57+07:00" }, "raw_text": "Performance summary The BIG picture (take home message) Instructions Clock cycles Seconds CPU time = X X Program Instruction Clock cycle Performance depends on Algorithm: IC, possibly CPI Programming language: IC, CPI Compiler: IC, CPI - Instruction set architecture: IC, CPl, 7 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28" }, { "page_index": 37, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_029.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_029.png", "page_index": 37, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:04+07:00" }, "raw_text": "Power trends In CMOS technology Power(P) = Capacitive load x Voltage2 x Clock rate 10000 120 3600 3900 2667 3300 3400 2000 100 frequency 103 1000 (zHWI) Xouanbau 95 87 80 200 (M) uaM0d 66 77 75.3 100 60 65 25 power 12.5 16 40 29.1 10 10.1 20 4.1 4.9 3.3 1 0 prd p an!suad syekye - (t002) (0022) aip!ie (STOZ) 98Z08 (286T) 98808 (586T) 98t08 (686T) (2661) (266T) (T022) Ccor2 (2222) (1222) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29" }, { "page_index": 38, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_030.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_030.png", "page_index": 38, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:07+07:00" }, "raw_text": "Reducing power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction Cold X 0.85 x (Vold X 0.85)2 x Fold X 0.85 = 0.854 = 0.52 P od Cold x V2 x Fod old The power wall We can't reduce voltage further We can't remove more heat How else can we improve performance? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30" }, { "page_index": 39, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_031.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_031.png", "page_index": 39, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:15+07:00" }, "raw_text": "Multiprocessors 100,000 Intel Xeon 4 cores3.6 GHzBoost to 4.0 Intel Core i7 4 cores 3.4 GHzboost to 3.8 GHz) Intel Xeon 6 cores.3.3 GHzboost to 3.6 GHz 34,967 Intel Xeon 4 cores,3.3 GHzboost to 3.6 GHz) 31.999 Intel Core i7 Extreme 4 cores 3.2 GHzboost to 3.5 GHz 24.129 Intel Core Duo Extreme 2 cores.3.0 GHz 21.871 Intel Core2Extreme 2 cores,2.9 GHz 19.484 AMDAthlon64.2.8GHz 14.387 10,000 AMD Athlon,2.6 GHz 11.865 Intel Xeon EE 3.2 GHz 7.108 Intel D850EMVR motherboard3.06GHz.Pentium 4 processor with Hyper-threading Technology 6.0436,681 IBM Power4.1.3 GHz 4,195 3,016 Intel VC820motherboard,1.0 GHz Pentium Ill processor 1,779 ProfessionalWorkstationXP1000,667MHz 21264A DigitalAlphaServer.8400.6/575..57.5.MHz.21264 1.267 1000 993 AlphaServer 40005/600.600MHz 21164 -649 Digital Alphastation 5/500,500 MHz 481 Digital Alphastation 5/300.300 MHz 280 22%/year Digital Alphastation 4/266,266MHz .183 BM POWERstation100.150 MHz 100 117 Digital3000AXP/500,150MHz 80 HP9000/750,66MHz 51 IBMRS6000/540.30MHz 52%/year 24 MIPSM2000.25MHz 18 MIPSM/120.16.7MHz 10 Sun-4/260,16.7MHz VAX8700.22MHz 5 AX-11/780.5MHz 25%/year 1.5.VAX-11/785 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 31" }, { "page_index": 40, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_032.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_032.png", "page_index": 40, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:17+07:00" }, "raw_text": "Benchmark Programs used to measure performance - Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC - Develops benchmarks for CPU, I/O, Web, ... SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 32" }, { "page_index": 41, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_033.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_033.png", "page_index": 41, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:27+07:00" }, "raw_text": "Example Intel core i7 920 results with CINT 2006 Executlon Reference Instruction Clock cycle tlme TIme TIme Descrlptlon Name Count x 109 CPI (seconds x 1o-9) (seconds) (seconds) SPECratlo Interpreted string processing perl 2252 0.60 0.376 508 9770 19.2 Block-sorting bzip2 2390 0.70 0.376 629 9650 15.4 compression GNU C compiler gcc 794 1.20 0.376 358 8050 22.5 Combinatorial optimization mcf 221 2.66 0.376 221 9120 41.2 Go game (Al) go 1274 1.10 0.376 527 10490 19.9 Search gene sequence hmmer 2616 0.60 0.376 590 9330 15.8 Chess game (Al) sjeng 1948 0.80 0.376 586 12100 20.7 Quantum computer libquantum 659 0.44 0.376 109 20720 190.0 simulation Video compression h264avc 3793 0.50 0.376 713 22130 31.0 Discrete event omnetpp 367 2.10 0.376 290 6250 21.5 simulation library Games/path finding astar 1250 1.00 0.376 470 7020 14.9 XML parsing xalancbmk 1045 0.70 0.376 275 6900 25.1 Geometric mean - - - - - - 25.7 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 33" }, { "page_index": 42, "chapter_num": 1, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_034.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_1/slide_034.png", "page_index": 42, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:30+07:00" }, "raw_text": "Concluding remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture - The hardware/software interface Execution time: the best performance measure Power is a limiting factor - Use parallelism to improve performance BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 34" }, { "page_index": 43, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_001.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_001.png", "page_index": 43, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:33+07:00" }, "raw_text": "COMPUTER ARCHITECTURE Chapter 2: Instruction set architecture - ISA Pham Quöc Cuö'ng BK Computer Engineering - CSE - HCMUT TP.HCM" }, { "page_index": 44, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_002.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_002.png", "page_index": 44, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:36+07:00" }, "raw_text": "Languages of Computer? Why? Q: Why do we need to learn the language of computers? A: To command a computer's hardware: speak its language BevansiaTTeRy 0110010110 CaLS for CompUTER 0111000110110 C0De toBe a Key 100110101010001 LanguaGeTavgHl 00101000100101 at SCHoOLu 010111001000101 1011001010110 100110010101 010010101 Source: http://media.apnarm.net.au/img/media/images/2013/08/14/computer_language_t620.jpg BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 2" }, { "page_index": 45, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_003.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_003.png", "page_index": 45, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:39+07:00" }, "raw_text": "Abstraction We teach students how to use abstraction so that we can build really complex software systems. John Hennessy ACM A.M.Turing Laureate acm BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 3" }, { "page_index": 46, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_004.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_004.png", "page_index": 46, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:42+07:00" }, "raw_text": "Instruction set architecture software instruction set architecture hardware MIPS32 Add Immediate Instruction 001000 0000100010 0000000101011110 OP CodeAddr 1Addr 2 Immediate value Equivalent mnemonic: addi Sr1,Sr2,350 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 4" }, { "page_index": 47, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_005.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_005.png", "page_index": 47, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:45+07:00" }, "raw_text": "Von Neumann architecture Stored-program concept Central Processing Unit (CPU) Instruction category: Arithmetic Arithmetic- logic Data transfer 1 unit (CA) Logical 1/0 Main Equip- memory Conditional branch ment (M) (I, 0) Unconditional jump Program control unit (CC) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 5" }, { "page_index": 48, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_006.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_006.png", "page_index": 48, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:51+07:00" }, "raw_text": "Computer components CPU Main memory 0 System 1 bus 2 PC MAR . Instruction . Instruction Instruction IR MBR . I/O AR . Data Execution Data unit I/O BR Data Data I/O Module n - 2 n - 1 . PC = Program counter . IR = Instruction register Buffers MAR = Memory address register MBR = Memory buffer register I/O AR = Input/output address register I/O BR = Input/output buffer register BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 6" }, { "page_index": 49, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_007.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_007.png", "page_index": 49, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:53+07:00" }, "raw_text": "Instruction execution model Fetch cycle Execute cycle Fetch next Execute START HALT instruction instruction Instruction fetch: from the memory - PC increased PC stores address of the next instruction Execution: decode and execute BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 7" }, { "page_index": 50, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_008.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_008.png", "page_index": 50, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:55+07:00" }, "raw_text": "STANDARDI MIPS INSTRUCTIONS BK TP.HCM 8" }, { "page_index": 51, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_009.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_009.png", "page_index": 51, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:57+07:00" }, "raw_text": "MlPS instruction set MIpS architecture MIPS Assembly Instruction > MIPS Machine Instruction Assembly: - add $tO,$s2,$t0 Machine: - 000000 10010 01000 01000 00000 100000 Only one operation is performed per MiPs instruction - e.g., a + b + c needs at least two instructions BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 9" }, { "page_index": 52, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_010.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_010.png", "page_index": 52, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:28:59+07:00" }, "raw_text": "Instruction set design principle Simplicity favors regularity Smaller is faster Make the common case fast Good design demands good compromises BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 10" }, { "page_index": 53, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_011.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_011.png", "page_index": 53, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:02+07:00" }, "raw_text": "MIPS operands 1. Register: 32 32-bit registers (start with the $ sign) - $sO-$s7: corresponding to variables (save) - $t0-$t9: storing temporary value - $a0-$a3 - $vO-$v1 - $gp,$fp,$sp,$ra,$at,$zero,$kO-$k1 only by data transfer instructions 3. Short integer immediate: -10, 20, 2020,... Only three operand types! Nothing else! BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 11" }, { "page_index": 54, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_012.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_012.png", "page_index": 54, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:05+07:00" }, "raw_text": "group: arithmetic instructions Assembly instruction format: Destination Source Source Opcode register register 1 register 2(*) Opcode: - add:DR=SR1+ SR2 - sub:DR =SR1-SR2 - addi: (*) SR2 is an immediate (e.g. 2O), DR = SR1 + SR2 Three register operands BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 12" }, { "page_index": 55, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_013.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_013.png", "page_index": 55, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:08+07:00" }, "raw_text": "Example Question: what is MIPS code for the following C code f = (g + h) - (i + j): If the variables g, h, i, j, and f are assigned to the register $sO,$s1, $s2,$s3, and $s4, respectively. Answer: add$tO,$sO,$s1# g + h add $sO,$sO,$s1 add $t1,$s2,$s3 # i+ j add $s1,$s2,$s3 sub $s4,$tO,$t1 # tO-t1 sub $s4,$s0,$s1 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 13" }, { "page_index": 56, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_014.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_014.png", "page_index": 56, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:12+07:00" }, "raw_text": "2nd group: data transfer instructions Copy data b/w memory Memory and registers in CPU Register read addr/ write addr Address: a value used to Processor read data delineate the location of a write data specific data element 10 8 within a memory array 101 4 1 0 Load (l): copy data from Data 32 bits memory to a register Store (s): copy data from a Address register to memory BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 14" }, { "page_index": 57, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_015.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_015.png", "page_index": 57, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:14+07:00" }, "raw_text": "Data transfer instructions Assembly instruction format: Memory Opcode Register operand Opcode: Size of data: 1 byte, 2 bytes (half of word), or 4 bytes (word) Behaviors: load or store Register: Load: destination - Store: source Memory operand: offset(base register) - offset: short integer number Byte address: each address identifies an 8-bit byte \"words\" are aligned in memory (address must be multiple of 4) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 15" }, { "page_index": 58, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_016.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_016.png", "page_index": 58, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:18+07:00" }, "raw_text": "Memory address = < offset > + value( < base register > ) Question: given the following memory map, assume that $sO stores value of 8. Which is the memory operand used to access the byte storing value of Ox9A? address: 8 9 10 11 0x12 0x34 0x56 0x78 0x9A 0xBC 0xDE 0xF0 Answer: address:l 12 13 14 15 Address of the byte storing value of 0x9A is 12 - If we use $sO as the base register, offset = 12 - 8 = 4 - Memory operand: 4($s0) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 16" }, { "page_index": 59, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_017.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_017.png", "page_index": 59, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:21+07:00" }, "raw_text": "Load instructions Remind: \"load\" means copying data from memory to a 32-bit register Instructions: Iw: load word eg.: Iw $s0,100($s1) #copy 4 bytes from memory to $s0 lh: load half - sign extended eg.: Ih $sO,10O($s1) #copy 2 bytes to $s0 and extend signed bit Ihu: load half unsigned - zero extended - Ib: load byte - sign extended - Ibu: load byte unsigned - zero extended - Special case: lui - load upper immediate eg.:lui $s0,0x1234 #$s0 = 0x12340000 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 17" }, { "page_index": 60, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_018.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_018.png", "page_index": 60, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:23+07:00" }, "raw_text": "Store instructions Remind: \"store\" means copying data from a register to memory Instructions: - sw: store word $s0,100($s1) #copy 4 bytes in $s0 to memory eg.: sw sh: store half - two least significant bytes eg.:sh $s0,100($s1) #copy 2 bytes in $s0 to memory sb: store byte - the least significant byte eg.: sb $s0,100($s1) #copy 1 bytes in $s0 to memory BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 18" }, { "page_index": 61, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_019.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_019.png", "page_index": 61, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:26+07:00" }, "raw_text": "Main memory used for composite data - Arrays, structures, dynamic data To apply arithmetic operations - Load value(s) from memory into register(s) Apply arithmetic operations to the register(s) Store result from a register to memory (if required) MIPS is Big Endian - Most-significant byte at least address of a word Little Endian: least-significant byte at least address BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 19" }, { "page_index": 62, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_020.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_020.png", "page_index": 62, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:29+07:00" }, "raw_text": "Example-1 C code: g = h + A[8]; - g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw $tO,32($s3 # load word add $s1,$s2,$t0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 20" }, { "page_index": 63, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_021.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_021.png", "page_index": 63, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:31+07:00" }, "raw_text": "Example-2 C code: A[12] = h + A[8] - h in $s2,base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 Iw $tO,32($s3) # load word add $tO,$s2,$tO $t0,48($s3) # store word SW BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 21" }, { "page_index": 64, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_022.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_022.png", "page_index": 64, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:35+07:00" }, "raw_text": "Exercises 1. Given the following memory map, assume that the register $tO stores value 8 while $sO contains 0xCAFEFACE. Show the effects on memory and registers of following instructions: a) Iw $t1,O($tO) address: 8 9 10 11 b) Iw $t2,4($tO) 0x12 0x34 0x56 0x78 c) Ih $t6,4($tO) 0x9A 0xBC 0xDE 0xF0 d) Ib $t5,3($tO) address: 12 13 14 15 e) sw $sO,O($tO) f) sb $sO,4($tO) g) Ih $sO,7($tO) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 22" }, { "page_index": 65, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_023.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_023.png", "page_index": 65, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:37+07:00" }, "raw_text": "Exercises 2. Convert the following C statements to equivalent MIPs assembly language if the variables f, g, and h are assigned to registers $sO, $s1, and $s2 respectively. Assume that the base address of the array A and B are in registers $s6 and $s7, respectively. a) f=g+h+ B[4] b) f = g- A[B[4]] BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 23" }, { "page_index": 66, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_024.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_024.png", "page_index": 66, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:40+07:00" }, "raw_text": "3rd group: logical instructions Instruction format: the same with arithmetic instructions Bitwise manipulation - Process operands bit by bit Operation C operator MIPS opcode Shift left << sll Shift right >> srl Bitwise AND & and, andi Bitwise OR or, ori Bitwise NOT nor BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 24" }, { "page_index": 67, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_025.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_025.png", "page_index": 67, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:43+07:00" }, "raw_text": "Shift operations Shift left (sll) Shift value in the first source to left and fill least significant positions With 0 bits - e.g.,s11 $sO,$s1,4 #$s0 = $s1<< 4 - Special case: sll by i bits multiplies by 2 Shift right (srl) Shift value in the first source to right and fill most significant positions With 0 bits - e.g.,sr1 $s0,$s1,4 # $s0= $s1>>4 - Special case: srl by i bits divides by 2' (unsigned number only) BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 25" }, { "page_index": 68, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_026.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_026.png", "page_index": 68, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:46+07:00" }, "raw_text": "AND operation $s1(32 bit Bitwise AND two source operands 0 (16b) 100 (16b) - and: two source registers e.g.,and $sO,$s1,$s2 #$s0=$s1 & $s2 - andi: the second source is a short integer number (16 bit) 16 high-significant bits of the result are 0s e.g.,andi $s0,$s1,100 #$s0 ={16'b0,$s1[15:0]&100} Useful to mask bits in a register Select some bits and clear others to 0 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 26" }, { "page_index": 69, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_027.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_027.png", "page_index": 69, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:49+07:00" }, "raw_text": "OR operation Bitwise OR two source operands - or: two registers e.g.,or $s0,$s1,$s2 #$s0=$s1$s2 - ori: the second source is a short integer number (16 bit Copy 16 high-significant bit from the first source to destination e.g.,ori $s0,$s1,100 #$s0 ={$s1[31:16]$s1[15:0]100} Useful to include bits in a word Set some bits to 1, leave others unchanged BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 27" }, { "page_index": 70, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_028.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_028.png", "page_index": 70, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:51+07:00" }, "raw_text": "NOT operation Don't have a not instruction in MIPS ISA - 2-operand instruction Useful to invert all bits in a register Can be done by the nor operator, 3-operand instruction - a NOR b= NOT (a OR b) NOT a = NOT(a OR 0) = a NOR 0 - e.g.,nor $sO,$sO,$zero - What else? BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 28" }, { "page_index": 71, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_029.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_029.png", "page_index": 71, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:54+07:00" }, "raw_text": "Example Question: assume that $s0 and $s1 are storing values 0x12345678 and OxCAFEFACE, respectively. What is value of $S2 after each following instructions 1.s1l $s2,$s0,4 2.and $s2,$s0,$s1 3.or $s2,$s0,$s1 4.andi $s2,$s0,2020 Answer: 1.0x23456780 2.0x02345248 3.0xDAFEFEFE 4. 0x00000660 BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 29" }, { "page_index": 72, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_030.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_030.png", "page_index": 72, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:29:56+07:00" }, "raw_text": "Exercise Find the value for $t2 after each following sequence of instructions if the values for register $tO and $t1 are a) $tO = OxAAAAAAAA,$t1 = Ox12345678 b) $tO = OxFOODDOOD,$t1 = Ox11111111 Sequence 1: Sequence 2: Sequence 3: sll $t2,$tO,44 s1I $t2,$tO,4 srl $t2,$t0,3 or $t2,$t2,$t1 andi $t2,$t2,-2 andi$t2,$t2,OxFFEF BK TP.HCM Computer Architecture (c) Cuong Pham-Quoc/HCMUT 30" }, { "page_index": 73, "chapter_num": 2, "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_031.png", "metadata": { "doc_type": "slide", "course_id": "CO2007", "source_file": "/workspace/data/converted/CO2007_Computer_Architecture/Chapter_2/slide_031.png", "page_index": 73, "language": "en", "ocr_engine": "PaddleOCR 3.2", "extractor_version": "1.0.0", "timestamp": "2025-10-30T22:30:00+07:00" }, "raw_text": "4th group: conditional branch instructions Branch to a label if a condition is True true; otherwise, continue Condition? sequentially Only two standard conditional False branch instructions Instruction with next instruction beq $rs,$rt, L1 #branch if a label equal . If (rs == rt), go to L1 addi $tO, $zero,0 - bne $rs, $rt, L1 addi $t1, $zero, 5 If(rs != rt),go to L1 L1: addi $tO,$tO,1 Label: a given name bne $tO,$t1,L1 #branch to L1 add $tO,$t1,$t0 - format: