{
  "course": "Digital_Systems",
  "course_id": "CO1023",
  "schema_version": "material.v1",
  "slides": [
    {
      "page_index": 0,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_001.png",
        "page_index": 0,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:48:43+07:00"
      },
      "raw_text": "C01023 Digital Systems - GE BK TP.HCM 1"
    },
    {
      "page_index": 1,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_002.png",
        "page_index": 1,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:48:48+07:00"
      },
      "raw_text": "CO1023 - Course lntroduction 2 Course e Introduction Instructor Pham Hoang Anh, Ph.D Faculty of Computer Science and Engineering HCMC University of Technology Email: anhpham@hcmut.edu.vn Phone: (84)(8) 38647256 (Ext. 5843) Course materials: BKel 6E anhpham@hcmut.edu.vr"
    },
    {
      "page_index": 2,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_003.png",
        "page_index": 2,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:48:53+07:00"
      },
      "raw_text": "CO1023 - Course lntroduction 3 What will you learn in this class? This course provides fundamentals of logic design, such as number presentation and codes, Boolean algebra and logic gates, analysis and design of combinational and sequential circuits. Why do you study this class?  It is fundamental for students in computer science and course engineering major. 6E anhpham@hcmut.edu.vn"
    },
    {
      "page_index": 3,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_004.png",
        "page_index": 3,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:48:58+07:00"
      },
      "raw_text": "CO1023- Course lntroduction Learning  Outcome  L.O.1 Describe digital systems, codes systems, Boolean algebra and logic gates L.O.1.1 - Describe digital systems, codes systems, main memory, secondary storage, I/O devices L.O.1.2 - Describe Boolean algebra and logic gates 0  L.O.2 Analyze and demonstrate the operation of basic combinational and seguential circuits L.O.2.1 - Analyze and demonstrate the operation of basic combinational circuits L.O.2.2 - Analyze and demonstrate the operation of basic sequential circuits  L.O.3 Design and simulate basic combinational and seguential circuits L.0.3.1 - Design basic combinational circuits L.O.3.2 - Design basic sequential circuits L.O.4 Assemble combinational and sequential circuits L.O.4.1 - Assemble combinational circuits L.O.4.2 - Assemble sequential circuits 0 GE anhpham@hcmut.edu.vr"
    },
    {
      "page_index": 4,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_005.png",
        "page_index": 4,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:02+07:00"
      },
      "raw_text": "CO1023 - Course lntroduction 5 Tentative Contents  Number presentation and codes Boolean algebra and logic gates  Combinational circuits  Sequential circuits 6E anhpnam@hcmut.edu.vr"
    },
    {
      "page_index": 5,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_006.png",
        "page_index": 5,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:06+07:00"
      },
      "raw_text": "CO1023 - Course lntroduction 6 Grading  Policy Grading Lab: 30% Mini Project Midterm: 20% Final Exam: 50% 2?? https://www.hackster.io/projects?ref=topnav http://www.electronicshub.org/iot-project-ideas GE anhpnam@hcmut.edu.vr"
    },
    {
      "page_index": 6,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_007.png",
        "page_index": 6,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:11+07:00"
      },
      "raw_text": "CO1023 - Course lntroduction Textbooks  Digital Systems: Principles and Applications (12th Edition) - Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss. Internet  Fundamentals  of Digital Logic - Stephen Brown,  Zvonko Vranesic McGraw Hill.  Digital Design: Principles and Practices- John F. Wakerly, Prentice-Hall 6E anhpham@hcmut.edu.vr"
    },
    {
      "page_index": 7,
      "chapter_num": 1,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_1/slide_008.png",
        "page_index": 7,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:14+07:00"
      },
      "raw_text": "CO1023 - Course lntroduction 8 QnA  https://www.youtube.com/watch?v=j6R  Wmsl79E https://www.youtube.com/watch?v=fi5GJBKb3Ww 6E anhpham@hcmut.edu.vn"
    },
    {
      "page_index": 8,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_001.png",
        "page_index": 8,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:17+07:00"
      },
      "raw_text": "C01023 Numerical Representation and Codes - BK TP.HCM"
    },
    {
      "page_index": 9,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_002.png",
        "page_index": 9,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:23+07:00"
      },
      "raw_text": "CO1023 - Number Presentation and Codes 2 Introduction  Digital technology is widely used. Examples Computers Manufacturing systems MERITBADGESERIES Medical Science Transportation DIGITAL TECHNOLOGY Entertainment Telecommunications SCTSDAM Basic digital concepts and terminology are introduced https://study.com/articles/What is Digital Logic.html Samsung SMARTTV GE"
    },
    {
      "page_index": 10,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_003.png",
        "page_index": 10,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:29+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 3 Numerical Representations Analog Representation A continuously variable, proportional indicator. Examples of analog representation:  Sound through a microphone causes voltage changes.  Mercury thermometer varies over a range of values with temperature. Digital Representation  Varies in discrete (separate) steps. Examples of digital representation: . Passing time is shown as a change in the display on a digital clock at one minute intervals. 6E"
    },
    {
      "page_index": 11,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_004.png",
        "page_index": 11,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:38+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes Digital and Analog Systems  Digital system A combination of devices that manipulate values represented in digital form. Analog system A combination of devices  that manipulate yalues represented in analog form 45 45 42 40 41 40 37 35 35 30 30 29 25 25 23 20 18 15 15 10 10 5 5 0 3 4 5 6 7 8 9 10 11 12 131415 2 3 4 5 6 1 8 9 10 11 12 13 14 15 time samples GE"
    },
    {
      "page_index": 12,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_005.png",
        "page_index": 12,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:42+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 5 Digital and Analog Systems  Advantages of digital systems Ease of design Well suited for storing information. Accuracy and precision are easier to maintain Programmable operation Less affected by noise Ease of fabrication on IC chips 6E"
    },
    {
      "page_index": 13,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_006.png",
        "page_index": 13,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:47+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 6 Digital and Analog Systems There are limits to digital technigues: The world is analog 0 The analog nature of the word requires a time consuming 0 conversion process: 1. Convert the physical variable to an electrical signal (analog) 2. Convert the analog signal to digital form. 3. Process (operate on) the digital information 4. Convert the digital output back to real-world analog form. 6E"
    },
    {
      "page_index": 14,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_007.png",
        "page_index": 14,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:53+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes Digital and Analog Systems  Analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) complicate circuitry. (Analog) Analog-to- (Digital) Temperature Measuring Digital digital (Analog) device processing converter (Digital) (Analog) Digital-to- Adjusts analog Controller temperature converter GE"
    },
    {
      "page_index": 15,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_008.png",
        "page_index": 15,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:49:57+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 8 Digital and Analog Systems  The audio CD is a typical hybrid (combination) system Analog sound is converted into analog voltage. Analog voltage is changed into digital through an ADC in the recorder Digital information is stored on the CD . At playback the digital information is changed into analog by a DAC in 0 the CD player. The analog voltage is amplified and used to drive a speaker that produces the original analog sound. 6E"
    },
    {
      "page_index": 16,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_009.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_009.png",
        "page_index": 16,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:02+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes Digital Number Systems  Number systems differ in the number of symbols they use Decimal - 10 symbols (base 10) 0 Hexadecimal - 16 symbols (base 16) Octal - 8 symbols (base 8) 0 Binary - 2 symbols (base 2) Generalized form of number system base b an-1an-2 ...a2a1a0.a.1a-2a-3...a-m+1a-m SE"
    },
    {
      "page_index": 17,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_010.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_010.png",
        "page_index": 17,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:06+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 10 Digital Number Systems  Example (7,239)1o = 7x 103 + 2x 102 +3x 101 + 9 x 100 (4103.2)5 = 4x 53 +1 x 52 + 0 x 51 + 3 x 50 + 2 x 5-1 =4x 125 +1 x 25 + 0x 5 + 3x 1 +2x 5-1 = (528.4)10 110112 = 1x 24 + 1 x 23 + 0 x 22 + 1X 21 + 1 X 20 = (27)10 (B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160 6E"
    },
    {
      "page_index": 18,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_011.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_011.png",
        "page_index": 18,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:11+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 11 Digital Number Systems  The Decimal (base 10) System 10 symbols: 0,1,2,3,4,5,6,7,8,9 Each number is a digit (from Latin for finger) Most significant digit (MSD) and least significant digit (LSD) Positional value may be stated as a digit multiplied by a power of 10 Positional values (weights) 103  102 101 100 10-110-210-3 2 7 4 5 2 1 4 Decimal MSD LSD point 6E"
    },
    {
      "page_index": 19,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_012.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_012.png",
        "page_index": 19,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:19+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 12 Digital Number  Systems  Decimal counting 0 20 103 1 421 - - 2 22 3 23 4 24 5 25 6 26 7 27 8 28 9 29 10 30 11 1 1 12 199 13 200 14 1 15 16 99 17 100 18 101 999 19 102 1000 6E"
    },
    {
      "page_index": 20,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_013.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_013.png",
        "page_index": 20,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:25+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 13 Digital Number Systems  The Binary (base 2) System 2 symbols: 0,1 Lends itself to electronic circuit design since only two different voltage levels are required. Other number systems are used to represent binary quantities. Positional value may be stated as a digit multiplied by a power of 2. 21 -2 2 2 2 V V V 1 1 0 1 1 1 0 1 LSB MSB (11011101), =1* 2° +1*21 +0*22 +1*23 +1*24 +1*2-1 +0*2-2 +1*2-3 SE"
    },
    {
      "page_index": 21,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_014.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_014.png",
        "page_index": 21,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:36+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 14 Digital Number  Systems Binary Counting 23 = 8 22= 4 l21 = 2 20 = 1 Decimal equivalent Weights 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 2 1 0 0 1 1 1 3 1 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 1 0 1 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 1 0 1 0 10 1 1 0 1 1 11 1 1 0 0 1 12 / 1 1 0 1 13 1 1 1 1 0 14 1 1 1 1 15 LSB 6E"
    },
    {
      "page_index": 22,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_015.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_015.png",
        "page_index": 22,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:44+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 15 Representing Binary  Quantities  Open and closed switches  Paper Tape Hole No hole 0 1 0 0 O 1 0 0 0 O 0 O 1 0 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1 (a) (b) 6E"
    },
    {
      "page_index": 23,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_016.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_016.png",
        "page_index": 23,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:48+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 16 Representing Binary  Quantities  Other two state devices: Light bulb (off or on) Diode (conducting or not conducting) Relay (energized or not energized) Transistor (cutoff or saturation) Photocell (illuminated or dark) GE"
    },
    {
      "page_index": 24,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_017.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_017.png",
        "page_index": 24,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:53+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 17 Representing Binary  Quantities  Exact voltage level is not important in digital systems.  A voltage of 3.6 V will mean the same (binary 1) as a voltage of 4.3 V. 5 V Binary 1 2 V Invalid Not voltages used 0.8 V Binary 0 0 V SE"
    },
    {
      "page_index": 25,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_018.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_018.png",
        "page_index": 25,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:50:57+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 18 Representing Binary  Quantities  Digital Signals and Timing Diagrams Timing diagrams show voltage versus time. Horizontal scale represents regular intervals of time beginning at time zero. Timing diagrams are used to show how digital signals change with time Timing diagrams are used to compare two or more digital signals 0 The oscilloscope and logic analyzer are used to produce timing diagrams. 6E"
    },
    {
      "page_index": 26,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_019.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_019.png",
        "page_index": 26,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:01+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 19 Digital Circuits/Logic Circuits  Digital circuits Produce and respond to predefined voltage ranges. Logic circuits Is used interchangeably with the term, digital circuits.  Digital integrated circuits (ICs) provide logic operations in a small reliable package 6E"
    },
    {
      "page_index": 27,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_020.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_020.png",
        "page_index": 27,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:06+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 20 Parallel and Serial Transmission  Parallel transmission MSB A3 B3 All bits in a binary number are transmitted A2 B2 A A1 B1 B simultaneously. A separate line is required LSB  Ao Bo for each bit.  Serial transmission Each bit in a binary number is transmitted per some time interval. Aout Bin A B SE"
    },
    {
      "page_index": 28,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_021.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_021.png",
        "page_index": 28,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:11+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 21 Parallel and Serial Transmission  Parallel transmission is faster but requires more paths.  Serial is slower but requires a single path. Both methods have useful applications which will be seen in later chapters. MSB A3 B3 A2 B2 Bin A B1 B A B A1 LSB Ao Bo SE"
    },
    {
      "page_index": 29,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_022.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_022.png",
        "page_index": 29,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:15+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 22 Memory  A circuit which retains a response to a momentary input is displaying memory  Memory is important because it provides a way to store binary numbers temporarily or permanently  Memory elements include: Magnetic Optical 0 Electronic latching circuits 0 GE"
    },
    {
      "page_index": 30,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_023.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_023.png",
        "page_index": 30,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:19+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 23 Digital Computers  Computer A system of hardware that performs arithmetic operations, manipulates  data 0 (usually in binary form), and makes decisions.  Computers perform operations based on instructions in the form of a program at high speed and with a high degree of accuracy. 6E"
    },
    {
      "page_index": 31,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_024.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_024.png",
        "page_index": 31,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:24+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 24 Block diagram of digital computer Von Neumann-architecture computers Central Processing Unit(CPU) Arithmetic/ logic Data, Data, Input Control Output information information Control signals Memory Dataor information GE"
    },
    {
      "page_index": 32,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_025.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_025.png",
        "page_index": 32,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:30+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 25 Central Processing Digital Computers Unit(CPU) Arithmetic logic  Major parts of a computer Input unit Data, Data, Input Control Output information information  Processes instructions and data into the memory. Memory unit -Control signals Memory Data or information Stores data and instructions. Control unit  Interprets instructions and sends appropriate signals to other units as instructed. Arithmetic/logic unit . Performs arithmetic calculations and logical decisions are performed. Output unit presents information from the memory to the operator or process.  The control and arithmetic/logic units are often treated as one and called the central processing unit (CPU) SE"
    },
    {
      "page_index": 33,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_026.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_026.png",
        "page_index": 33,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:34+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 26  Microcomputer Most common (desktop PCs, notebook computers Has become very powerful  Minicomputer (workstation) Mainframe Microcontroller Designed for a specific application Dedicated or embedded controllers Used in appliances, manufacturing processes, auto ignition systems, ABS systems, and many other applications. 6E"
    },
    {
      "page_index": 34,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_027.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_027.png",
        "page_index": 34,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:41+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 27 Numerical Conversion The hexadecimal number system is introduced. Since different number systems may be used in a system, it is important for a technician to understand how to convert between them. Binary codes that are used to represent different information are also described. N10 =(anan-1an-2...a2aqao) b N ao a + a. 6n-2 +....+a =Q a b Q + +a b +....+a =Q +a ai a b Q *63 +....+a=Q a ta D ta b SE"
    },
    {
      "page_index": 35,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_028.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_028.png",
        "page_index": 35,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:45+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 28 Binary to Decimal Conversion  Convert binary to decimal by summing the positions that contain a 1. 1 0 0 1 0 25+24 +23 +22 +21 +2o 1011.1012= ? SE"
    },
    {
      "page_index": 36,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_029.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_029.png",
        "page_index": 36,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:48+07:00"
      },
      "raw_text": "CO1023 - Number Presentation and Codes 29 Decimal to Binary Conversion Two methods to convert decimal to binary: Reverse process described above 0 Use repeated division 0 6E"
    },
    {
      "page_index": 37,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_030.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_030.png",
        "page_index": 37,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:52+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 30 Decimal to Binary Conversion Reverse process described above Note that all positions must be accounted for 0  +22+0  +0 ) +2o 1 0 0 1 0 6E"
    },
    {
      "page_index": 38,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_031.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_031.png",
        "page_index": 38,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:51:58+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 31 Decimal to Binary Conversion  Repeated division steps: Divide the decimal number by 2 Write the remainder after each division until a quotient of zero is obtained The first remainder is the LSB and the last is the MSB 41 5 20 2 az =1 ao =1 2 2 20 2 a4 = 0 10 aq = 0 2 2 1 10 as =1 az =0 2 2 (41)10 = (a5a4a3a2aao)2 = (101001)2 SE"
    },
    {
      "page_index": 39,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_032.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_032.png",
        "page_index": 39,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:03+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 32 Decimal to Binary Conversion START  Repeated division Divide by This flowchart describes the process and can be 2 used to convert from decimal to any other number system. Record quotient(Q) and remainder(R NO Is Q=0? YES Collect R's into desired binary numberwith first R as LSB and last R as MSB END SE"
    },
    {
      "page_index": 40,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_033.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_033.png",
        "page_index": 40,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:06+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 33 Hexadecimal Number System  Most digital systems deal with groups of bits in even powers of 2 such as 8,16, 32, and 64 bits.  Hexadecimal uses groups of 4 bits. Base 16 16 possible symbols 0-9 and A-F  Allows for convenient handling of long binary strings 6E"
    },
    {
      "page_index": 41,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_034.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_034.png",
        "page_index": 41,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:10+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 34 Hexadecimal Number System t from hex to decimal by multiplying  Convert each hex digit by its positional weight. Example: 16316 1631=1(162)+6(16')+3(16°) =1x 256 + 6x16 +3x1 = 35510 SE"
    },
    {
      "page_index": 42,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_035.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_035.png",
        "page_index": 42,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:13+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 35 Hexadecimal Number System  Convert from decimal to hex by using the repeated division method used for decimal to binary and decimal to octal conversion.  Divide the decimal number by 16  The first remainder is the LSB and the last is the MSB Note, when done on a calculator a decimal remainder can be multiplied by 16 to get the result. If the remainder is greater than 9, the letters A through F are used. 6E"
    },
    {
      "page_index": 43,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_036.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_036.png",
        "page_index": 43,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:23+07:00"
      },
      "raw_text": "C01023-Number Presentation and Codes 36 Hexadecimal Number System Example of hex to binary conversion: Decimal Binary Octal Hexa 0 0000 00 9F216 = 9 F 2 1 0001 01 1 2 0010 02 2 1001 1111 0010= 3 0011 03 3 4 0100 04 4 5 0101 05 5 1001111100102 6 0110 06 6 7 0111 07 7 8 1000 10 8 9 1001 11 9 10 1010 12 A 11 1011 13 B 12 1100 14 c 13 1101 15 D 14 1110 16 E 15 1111 17 F GE"
    },
    {
      "page_index": 44,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_037.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_037.png",
        "page_index": 44,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:34+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 37 Binary to Hex Conversion  Convert from binary to hex by grouping bits in four starting with the LSB.  Each group is then converted to the hex equivalent  Leading zeros can be added to the left of the MSB to fill out the last group. Decimal Binary Octal Hexa Example: 0 0000 00 0 1 0001 01 (Note the addition of leading zeroes) 1 2 0010 02 2 3 0011 03 3 4 0100 04 4 5 0101 05 5 11101001102= 0011 1010 0110 6 0110 06 6 7 0111 07 7 3 A = 8 1000 10 8 9 1001 11 9 3A616 10 1010 12 A 11 1011 13 B 12 1100 14 c 13 1101 15 D 14 1110 16 E 15 17 F GE 1111"
    },
    {
      "page_index": 45,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_038.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_038.png",
        "page_index": 45,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:38+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 38 Hexadecimal Number System  Hexadecimal is useful for representing long strings of bits. Understanding the conversion and memorizing the  4 bit 1 process patterns for each hexadecimal digit will prove valuable later. SE"
    },
    {
      "page_index": 46,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_039.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_039.png",
        "page_index": 46,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:44+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 39 Binary Coded Decimal (BCD) Binary Coded Decimal is another way to present decimal numbers in binary form BCD is widely used and combines features of both decimal and binary systems.  Each digit is converted to a binary equivalent. Decimal BCD 0 0000 01100101 1000 1 0001 2 0010 3 0011 4 0100 58 5 0101 6 6 0110 7 0111 8 1000 9 1001 SE"
    },
    {
      "page_index": 47,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_040.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_040.png",
        "page_index": 47,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:48+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 40 BCD  To convert the number 8741o to BCD 8 7 4 1000 0111 0100 =100001110100 BCD  Each decimal digit is represented using 4 bits. Each 4-bit group can never be greater than 9. Reverse the process to convert BCD to decimal. 6E"
    },
    {
      "page_index": 48,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_041.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_041.png",
        "page_index": 48,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:53+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 41 BCD BCD is not a number system. BCD is a decimal number with each digit encoded to its binary equivalent.  A BCD number is not the same as a straight binary number. The advantage BCD is s the primary  of relative of ease converting to and from decimal. GE"
    },
    {
      "page_index": 49,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_042.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_042.png",
        "page_index": 49,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:52:58+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 42 Gray Code - The gray code is used in applications where numbers change rapidly. - In the gray code, only one bit changes from each value to the next. Binary Gray Code 000 000 001 001 010 011 011 010 100 110 101 111 110 101 111 100 6E"
    },
    {
      "page_index": 50,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_043.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_043.png",
        "page_index": 50,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:04+07:00"
      },
      "raw_text": "C01023- Number Presentation and Codes 43 Gray Code 1 bit 2 bit 3 bit 4 bit 00 000 0000 1 01 001 0001 11 011 0011 10 010 0010 110 0110 111 0111 101 0101 100 0100 1100 1101 1111 1110 1010 1011 1001 1000 GE"
    },
    {
      "page_index": 51,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_044.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_044.png",
        "page_index": 51,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:13+07:00"
      },
      "raw_text": "CO1023 - Number Presentation and Codes 44 Putting  It All Together Decimal Binary Hexadecimal BCD Gray 0 0 0 0 0 1 1 1 0001 0001 2 10 2 0010 0011 3 11 3 0011 0010 4 100 4 0100 0110 5 101 5 0101 0111 6 110 6 0110 0101 7 111 7 0111 0100 8 1000 8 1000 1100 9 1001 9 1001 1101 10 1010 A 0001 0000 * 1111 11 1011 B 0001 0001 F 1110 12 1100 C 0001 0010F 1010 13 1101 D 0001 0011F 1011 14 1110 E 0001.0100F 1001 15 1111 F 0001 0101F 1000 6E"
    },
    {
      "page_index": 52,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_045.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_045.png",
        "page_index": 52,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:17+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 45 The Byte, Nibble, and Word 1 byte = 8 bits  1 nibble = 4 bits 1 word = size depends on data pathway size.  Word size in a simple system may be one byte (8 bits) Word size in a PC is eight bytes (64 bits) 6E"
    },
    {
      "page_index": 53,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_046.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_046.png",
        "page_index": 53,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:21+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 46 Alphanumeric Codes  Represents characters and functions found on a computer keyboard  ASCll - American Standard Code for Information Interchange. Seven-bit code: 27 = 128 possible code groups Examples of use are: to transfer information between computers, between computers and printers, and for internal storage. 6E"
    },
    {
      "page_index": 54,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_047.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_047.png",
        "page_index": 54,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:26+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 47 Parity Method for Error Detection Binary data and codes s are frequently moved between locations. For example: Digitized voice over a microwave link. Storage and retrieval of data from magnetic and optical disks. Communication between computer systems over telephone lines using a modem. 0  Electrical noise can cause errors during transmission  Many digital employ for systems methods detection (and error sometimes correction) SE"
    },
    {
      "page_index": 55,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_048.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_048.png",
        "page_index": 55,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:30+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 48 Parity Method for Error Detection  The parity method of error detection requires the addition of an extra bit to a code group.  This extra bit is called the parity bit.  The bit can be either a 0 or 1, depending on the number of 1s in the code group. There are two methods, even and odd 6E"
    },
    {
      "page_index": 56,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_049.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_049.png",
        "page_index": 56,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:34+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 49 Parity Method for Error Detection - Even parity method - the total number of bits in a group including the parity bit must add up to an even number. The binary group 1 0 1 1 would require the addition of a parity bit 1 1 0 1 1  Odd parity method - the total number of bits in a group including the parity bit must add up to an odd number. The binary group 1 1 1 1 would require the addition of a parity bit 1 1 1 1 1 6E"
    },
    {
      "page_index": 57,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_050.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_050.png",
        "page_index": 57,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:37+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 50 Parity Method for Error Detection  The transmitter and receiver must \"agree\" on the type of parity checking used.  Two bit errors would not indicate a parity error.  Both odd and even parity methods are used, but even seems to be used more often. 6E"
    },
    {
      "page_index": 58,
      "chapter_num": 2,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_051.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_2/slide_051.png",
        "page_index": 58,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:40+07:00"
      },
      "raw_text": "CO1023- Number Presentation and Codes 51 Odd Parity Error Detection  Original data 10011010  With Odd Parity 110011010 1-bit error 110111010  Number of 1s even indicates 1-bit error  2-bit error 110110010  Number of 1s odd no error indicated  3-bit error 100110010  Number of 1s even indicates error 6E"
    },
    {
      "page_index": 59,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_001.png",
        "page_index": 59,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:43+07:00"
      },
      "raw_text": "C01023 Describing Logic Circuits - SE BK TP.HCM"
    },
    {
      "page_index": 60,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_002.png",
        "page_index": 60,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:47+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 2 Boolean Constants and Variables  Boolean algebra is an important tool in describing, analyzing, designing and implementing digital circuits.  Boolean algebra allows only two values: 0 and 1. Logic 0 can be: false, off, low, no, open switch. Logic 1 can be: true, on, high, yes, closed switch. Three basic logic operations: OR, AND, and NOT. 6E"
    },
    {
      "page_index": 61,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_003.png",
        "page_index": 61,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:53:51+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits Truth Tables - A truth table describes the relationship between the input and output of a logic circuit. The  number of entries  to the number of inputs. For corresponds example, a 2-input table would have 22 = 4 entries. A 3-input table 1 would have 23 = 8 entries. GE"
    },
    {
      "page_index": 62,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_004.png",
        "page_index": 62,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:05+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 4 Truth Tables - Examples of truth tables with 2, 3, and 4 inputs. Output A B C A B C D x x 0 0 0 0 0 0 0 0 0 Inputs 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 A B x 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 (b) 1 0 0 1 0 1 0 1 0 0 A 1 0 1 1 1 2. x 1 1 0 0 0 B 1 1 0 1 0 (a) 1 1 1 0 0 1 1 1 1 1 https://www.youtube.com/watch?v=Xi18hl1LqAA (c) 6E"
    },
    {
      "page_index": 63,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_005.png",
        "page_index": 63,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:10+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 5 OR Operation With OR Gates  The Boolean expression for the OR operation is x = A + B This is read as \"X equals A or B.\" X = 1 when A= 1 or B = 1.  Truth table, circuit symbol and timing diagram for a two input OR gate: OR A B x = A + B 0 0 0 A x = A + B A 0 1 1 1 0 1 B B 1 1 1 OR Gate x GE"
    },
    {
      "page_index": 64,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_006.png",
        "page_index": 64,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:20+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits OR Operation With OR Gates  The OR operation is similar to addition but when A = 1 and B = 1. the OR operation produces 1 + 1 = 1.  In the Boolean expression x=1+1+1+1=1 We could say that x is true (1) when A is true (1) OR B is true (1) OR C is A B c D X true (1) OR D is true (1 0 0 0 0 0 In general, the output of an OR gate is HIGH whenever one or 0 0 0 1 1 0 0 1 0 1 more inputs are HIGH 0 0 1 1 0 1 0 0 1 0 0 1 1 A 0 1 0 0 1 1 B 1 0 0 0 1 0 0 1 B 1 X c 1 0 1 0 7 0 1 1 D 1 1 0 0 D x 1 1 0 1 7 1 1 1 0 1 1 1 1 1 1 6E"
    },
    {
      "page_index": 65,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_007.png",
        "page_index": 65,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:24+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits OR Operation With OR Gates  an output function is desired when one of multiple inputs is activated. VT Temperature transducer Comparator Alarm VP Pressure PH transducer Comparator Chemical process VPR GE"
    },
    {
      "page_index": 66,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_008.png",
        "page_index": 66,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:30+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 8 AND Operations with AND gates - The Boolean expression for the AND operation is x = A . B This is read as \"x equals A and B.\" x = 1 when A = 1 and B = 1  Truth table and circuit symbol for a two input AND gate are shown. Notice the difference between OR and AND gates AND A B x=A.B 0 0 0 A A 0 1 0 x= AB 1 0 0 1 B B 1 1 1 1 AND gate 1 x GE"
    },
    {
      "page_index": 67,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_009.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_009.png",
        "page_index": 67,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:36+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits AND Operation With AND Gates  The AND operation is similar to multiplication. - In the Boolean expression X = A: B : C X = 1 only when A=1,B =1,and C =1.  The output of an AND gate is HIGH only when all inputs are HIGH. A B C X 0 0 0 0 A 0 0 1 0 0 0 0 B B 0 0 C C 1 0 0 0 1 0 1 0 x - 1 0 1 0 1 1 1 6E"
    },
    {
      "page_index": 68,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_010.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_010.png",
        "page_index": 68,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:42+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 10 NOT Operation - The Boolean expression for the NOT operation is X = A X = A'  This is read as: x equals NOT A,or x equals the inverse of A, or 0 0 x equals the complement of A  Truth table, symbol, and sample waveform for the NOT circuit. NOT 1 NOT A A x = A 0 0 1 A X = A 1 0 x (a) Presence of small 0 circle always denotes inversion (c) (b) GE"
    },
    {
      "page_index": 69,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_011.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_011.png",
        "page_index": 69,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:46+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits Describing Logic Circuits Algebraically  The three basic Boolean operations (OR, AND, NOT) can describe any logic circuit. Examples of Boolean expressions for logic circuits: A A.B x = A:B + C B A A + B B x=(A +B).O GE"
    },
    {
      "page_index": 70,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_012.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_012.png",
        "page_index": 70,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:50+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 12 Describing Logic Circuits Algebraically  The output of an inverter is equivalent to the input with a bar over it. Input A through an inverter equals A'. Examples using inverters. A A X=A+B A A+B B B X=A+B (a) (b) GE"
    },
    {
      "page_index": 71,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_013.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_013.png",
        "page_index": 71,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:54+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 13 More Examples A ABC B C x=ABCA+D A A+D A+D D (a) A+B (A+BC A+BC B C D+A+B)C D E x=[D+A+BC]·E (b) GE"
    },
    {
      "page_index": 72,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_014.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_014.png",
        "page_index": 72,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:54:58+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 14 Evaluating Logic Circuit Outputs  Rules for evaluating a Boolean expression: Perform all inversions of single terms. Perform all operations within parenthesis. Perform AND  operation before an OR  operation unless parenthesis indicate otherwise If an expression has a bar over it, perform the operations inside the expression and then invert the result. 6E"
    },
    {
      "page_index": 73,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_015.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_015.png",
        "page_index": 73,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:02+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 15 Evaluating Logic Circuit Outputs - Evaluate Boolean expressions by substituting values and performing the indicated operations: A=0,B=1,C=1,and D=1 x = ABC(A+D) =0.1.1.(0+1) =1.1.1.(0+1) =1.1.1.(1) 1:1:1:0 = 0 GE"
    },
    {
      "page_index": 74,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_016.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_016.png",
        "page_index": 74,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:06+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 16 Evaluating Logic Circuit Outputs  Output logic levels can be determined directly from a circuit diagram  Technicians frequently use this method. - The output of each gate is noted until a final output is found. 1 C C+D 0 0 D x=ABC+D B 1 A 6E"
    },
    {
      "page_index": 75,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_017.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_017.png",
        "page_index": 75,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:12+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 17 Implementing Circuits From Boolean  Expressions  It is important to be able to draw a logic circuit from a Boolean expression.  The expression x=A:B.O B X could be drawn as a three input AND gate  A more complex example such as AC C y = AC+BC+ ABC could be drawn as two 2-input AND gates and B 00 BC one 3-input AND gate feeding into a 3-input OR gate. Two of the AND gates have inverted inputs. B ABC C GE"
    },
    {
      "page_index": 76,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_018.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_018.png",
        "page_index": 76,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:15+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 18 Example  Draw the circuit diagram to implement the expression x =(A+B)(B+C) A A+B x=A+BB+C B B - B+C GE"
    },
    {
      "page_index": 77,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_019.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_019.png",
        "page_index": 77,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:21+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 19 NOR Gates and NAND Gates  Combine basic AND, OR, and NOT operations. The NOR gate is an inverted OR gate. An inversion \"bubble\" is placed at the output of the OR gate.  The Boolean expression is x = A +B A A+B NOR A B A X B 0 C 1 0 0 1 x 0 0 1 GE"
    },
    {
      "page_index": 78,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_020.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_020.png",
        "page_index": 78,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:26+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 20 NOR Gates and NAND Gates  The  NAND gate is an inverted AND An inversion \"bubble\" is gate. placed at the output of the AND gate.  The Boolean expression is x =AB A AB NAND B A A B X 0 0 B 1 0 1 1 1 0 1 x 1 1 0 GE"
    },
    {
      "page_index": 79,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_021.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_021.png",
        "page_index": 79,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:29+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 21 Laws of Boolean Algebra  Commutative Laws  Associative Laws  Distributive Laws GE"
    },
    {
      "page_index": 80,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_022.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_022.png",
        "page_index": 80,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:34+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 22 Commutative Laws of Boolean Algebra A + B = B + A A B A+B= B+A B A A o B =B oA A B AB BA B A GE"
    },
    {
      "page_index": 81,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_023.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_023.png",
        "page_index": 81,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:40+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 23 Associative Laws of Boolean Algebra A + (B + C) = (A + B) + C A A +B A +(B + C) B B B + C C A+B)+C C A(B.C)=(A.B).C A A AB B A(BC) B BC C C (ABC GE"
    },
    {
      "page_index": 82,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_024.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_024.png",
        "page_index": 82,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:45+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 24 Distributive Laws of Boolean Algebra A.(B+ C) =A o B +A o C A (B + C) =A B + A C A B AB B B+C C x x A A AC C X =A(B + C X =AB +AC GE"
    },
    {
      "page_index": 83,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_025.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_025.png",
        "page_index": 83,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:51+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 25 Rules of Boolean Algebra 1.A+0=A 7.AA-A 2.A+1=1 8.AA0 3.A·0=0 9.A=A 4.A1=A 10.A+AB=A 5.A+A=A 11.A+AB=A+B 6.A+A=1 12.A+BA+C=A+BC 6E"
    },
    {
      "page_index": 84,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_026.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_026.png",
        "page_index": 84,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:55:59+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 26 Rules of Boolean Algebra A=1 A=0 A B X X=1 X=0 0 0 0 0 Rule 1 X=A+O=A 0 1 1 1 0 1 4=0 x=1 1 1 1 X=1 OR Truth Table Rule 2 X=A+1=1 A B X A=1 A=0 X=0 X=0 0 0 0 0 0 Rule 3 0 1 0 X=A0=0 1 0 0 A=0 A=1 1 1 1 X=0 X=1 1 AND Truth Table Rule 4 X=A1=A GE"
    },
    {
      "page_index": 85,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_027.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_027.png",
        "page_index": 85,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:08+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 27 Rules of Boolean Algebra A=0 A=1 A B X X=0 X=1 A=1 A=0 0 0 Rule 5 X=A+A=A D 1 1 1 0 1 A=0 A=1 X=1 X=1 1 1 A=0 A=1 OR Truth Table Rule 6 X=A+A=1 A=1 A=0 A B X X=0 X=1 A=1 A=0 0 0 Rule 7 X=A·A=A 0 1 0 0 0 A=1 A=0 X=0 X=0 1 1 1 A=0 A=1 AND Truth Table Rule 8 X=A·A=0 GE"
    },
    {
      "page_index": 86,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_028.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_028.png",
        "page_index": 86,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:16+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 28 Rules of Boolean Algebra A B X 0 0 A= A=0 A= A=1 0 1 1  Rule 9 1 0 1 A=A 1 1 1 Rule 10:A + AB =A OR Truth Table A B X A B AB A+AB A C 0 0 0 0 0 B D 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 1 A 1 straight connection 1 1 equal AND Truth Table GE"
    },
    {
      "page_index": 87,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_029.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_029.png",
        "page_index": 87,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:27+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 29 Rules of Boolean  Algebra  Rule 11:A +A'B =A +B A B AB A+AB A+B A 0 0 0 0 0 B 0 1 1 1 1 0 0 1 1 A 1 1 0 1 1 B equal  Rule 12: (A + B)(A + C) = A + BC A B c A+B A+C A+BA+C BC A+BC B 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 1 A 0 1 1 0 1 B 1 1 1 1 1 1 1 equal 6E"
    },
    {
      "page_index": 88,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_030.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_030.png",
        "page_index": 88,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:31+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 30 Examples  Simplify the expression y = ABD+ABD y=AB z =(A+B)(A+B) z =B x = ACD+ ABCD x = ACD+ BCD y = AC + ABC y =AC GE"
    },
    {
      "page_index": 89,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_031.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_031.png",
        "page_index": 89,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:35+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 31 DeMorgan's Theorems  Theorem l 1: When the OR sum of two variables is inverted, it is equivalent to inverting each variable individually and ANDing them. A+B=A.B  Theorem 2: When the AND product of two variables is inverted, it is eguivalent to inverting each variable individually and ORing them. A.B =A+B GE"
    },
    {
      "page_index": 90,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_032.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_032.png",
        "page_index": 90,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:40+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 32 DeMorgan's Theorems - A NOR gate is equivalent to an AND gate with inverted inputs. - A NAND gate is equivalent to an OR gate with inverted inputs.  For N variables, DeMorgan's theorem is expressed as: ABC...N = A+ B+C+...+N and A+ B+C+...+N = ABC. N Applying Demorgan's theorem to the expression ABC + D we get: ABC +DEF =(ABC)(DEF) =(A+B+C)(D+E+F 6E"
    },
    {
      "page_index": 91,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_033.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_033.png",
        "page_index": 91,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:44+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 33 Implications of DeMorgan's Theorems X X X x + y xy=x+y V (a) x:y= x + y (b) x x+y=xy (a) X x+y=xy (b) GE"
    },
    {
      "page_index": 92,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_034.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_034.png",
        "page_index": 92,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:49+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 34 Implications of DeMorgan's Theorems  Determine the output expression for the below circuit and simplify it using DeMorgan's Theorem A z=A-BC=A+B+=A+B+C B C C  Use DeMorgan's . theorems to below convert expression  to an expression containing only single-variable inversions y=AB(C+D) y = A+B+CD GE"
    },
    {
      "page_index": 93,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_035.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_035.png",
        "page_index": 93,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:52+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 35 Example of DeMorgan's Theorems Simplify the expression to one having only single variables inverted F=X+Y+P+Q F =XY+P.Q z=(A+C)(B+D) z=AC+BD 6E"
    },
    {
      "page_index": 94,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_036.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_036.png",
        "page_index": 94,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:55+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 36 Examples  Simplify the expressions z =(A' + B)(A+B)  De Morgan's z = ((a'+c) . (b+d')) GE"
    },
    {
      "page_index": 95,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_037.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_037.png",
        "page_index": 95,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:56:58+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 37 Examples  Simplify the expressions z = (A' + B)(A+B) = A'A + A'B + AB + BB = 0 + (A'+A)B + B = B  De Morgan's z = ((a'+c) . (b+d')) =(a'+c)' + (b+d')'=ac' + b'd 6E"
    },
    {
      "page_index": 96,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_038.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_038.png",
        "page_index": 96,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:03+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 38 Universality of NAND and NOR Gates NAND  or NOR be to  the three  basic logic gates  can used create expressions (OR, AND, and INVERT) X=AA=A (a) INVERTER A AB X=AB 4 2 B B AND (b) A x=A B=A+ B 3 B B B 2 (c) OR GE"
    },
    {
      "page_index": 97,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_039.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_039.png",
        "page_index": 97,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:08+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 39 Universality of NAND and NOR Gates x= A + A =A A (a) INVERTER A A+B A+B A 2 B B OR (b) A A A X=A+B=AB B B AND B 2 (c) GE"
    },
    {
      "page_index": 98,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_040.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_040.png",
        "page_index": 98,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:12+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 40 Alternate Logic-Gate Representations  To convert a standard symbol to an alternate: Invert each input and output (add an inversion bubble where there are none on the standard symbol, and remove bubbles where they exist on the standard symbol. Change a standard OR gate to and AND gate, or an AND gate to an OR gate. 6E"
    },
    {
      "page_index": 99,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_041.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_041.png",
        "page_index": 99,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:17+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 41 Alternate Logic-Gate Representations Standard and alternate symbols for various logic gates and inverter A A·B AND A+B=AB B A+B OR A·B=A+B B B A AB NAND A+B=AB B A+B NOR AB=A+B B B A INV A GE"
    },
    {
      "page_index": 100,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_042.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_042.png",
        "page_index": 100,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:22+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 42 Alternate Logic-Gate Representations  The equivalence can be applied to gates with any number of inputs.  No standard symbols have bubbles on their inputs. All of the alternate symbols do.  The standard and alternate symbols  the represent physical same circuitry GE"
    },
    {
      "page_index": 101,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_043.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_043.png",
        "page_index": 101,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:26+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 43 Alternate Logic-Gate Representations  Active high - an input or output has no inversion bubble.  Active low - an input or output has an inversion bubble. - An AND gate will produce an active output when all inputs are in their active states  An OR gate will produce an active output when any input is in an active state. 6E"
    },
    {
      "page_index": 102,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_044.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_044.png",
        "page_index": 102,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:30+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 44 Alternate Logic-Gate Representations  Interpretation of the two NAND gate symbols. A AB Output goes LOW only when a// inputs are HIGH B LOW state is Active-HIGH the active state (a) A A+ B=AB Output is HIGH when any input is LOW. B HIGH state is the active state. Active-LOW (b) GE"
    },
    {
      "page_index": 103,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_045.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_045.png",
        "page_index": 103,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:35+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 45 Alternate Logic-Gate Representations - Interpretation of the two OR gate symbols A A + B Output goes HIGH when B any input is HIGH HlGH state is active state. Active-HlGH (a) A AB=A+B Output goes LOW only when all inputs are LOW. B LOW state is active state. Active-LOW (b) GE"
    },
    {
      "page_index": 104,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_046.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_046.png",
        "page_index": 104,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:38+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 46 Which Gate Representation to Use  Using g alternate and standard Iogic gate symbols together can make circuit operation clearer.  When possible choose symbols that gate SO bubbe outputs are connected to bubble input and nonbubble  outputs are connected to nonbubble inputs. GE"
    },
    {
      "page_index": 105,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_047.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_047.png",
        "page_index": 105,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:42+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 47 Which Gate Representation to Use  When a logic signal is in the active state (high or low) it is said to be asserted.  When a logic signal is in the inactive state  (high or low) it is said to be unasserted.  A bar over a signal means asserted (active) low.  The absence of a bar over a signal means asserted (active) high 6E"
    },
    {
      "page_index": 106,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_048.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_048.png",
        "page_index": 106,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:53+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 48 (a) Original circuit using B standard NAND symbols; C A B C D z (b) equivalent representation 0 0 0 0 0 (a) 0 0 0 1 0 0 0 1 0 0 where output Z is active-HIGH; 0 0 1 1 1 X 0 1 0 0 0 0 1 0 1 0 B 0 1 0 0 0 1 1 1 (c) equivalent representation 0 0 0 0 C 1 0 0 1 0 Active-HIGH where output Z is active-LOW: 0 1 0 0 D 1 0 1 1 1 (b) 1 1 0 0 1 1 0 1 1 1 1 1 0 1 (d) truth table. 1 1 1 1 1 X (d) Active-LOW D (c) GE"
    },
    {
      "page_index": 107,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_049.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_049.png",
        "page_index": 107,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:57:57+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 49 Example  Alarm is activated when Z goes high. Modify the circuit so that it represents the circuit operation more effectively. A Z z B 2 ALARM B 2 ALARM C D D (b) (a) GE"
    },
    {
      "page_index": 108,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_050.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_050.png",
        "page_index": 108,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:07+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 50 Methods of describing logic circuits Boolean expression  (a) Boolean expression; warning_light = driver_present- buckled_up* ignition_on (a)  (b) schematic diagram; Schematic diagram driver_present  (c) truth table; buckled_up warning_light  (d) timing diagram. ignition_on (b) Truth table driver_present buckled_up ignition_on warning_light 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 (c) Timing diagram Name Val 1.0 ms 2.0ms 3.0 ms 4.0ms 5.0ms 6.0 ms 7.0 ms 8.0 ms 9.0 ms 10 ms  ignition_on 0 buckled_up O driver_present  warning_light 0 6E (d)"
    },
    {
      "page_index": 109,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_051.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_051.png",
        "page_index": 109,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:10+07:00"
      },
      "raw_text": "CO1023-Describing Logic Circuits 51 Summary of Methods to Describe Logic Circuits  The three basic logic functions are AND, OR, and NOT.  Logic functions allow us to represent a decision process. If it is raining OR it looks like rain I will take an umbrella. If I get paid AND I go to the bank I will have money to spend 6E"
    },
    {
      "page_index": 110,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_052.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_052.png",
        "page_index": 110,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:15+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 52 Summary  Boolean Algebra:  A mathematical tool used in the analysis and design of digital circuits  Basic Boolean operations OR: HIGH output when any input is HIGH AND: HIGH output only when all inputs are HIGH NOT: output is the opposite logic level as the input  NOR: OR with its output connected to an INVERTER  NAND: AND with its output connected to an INVERTER  Boolean theorems and rules To simplify the expression of a logic circuit and can lead to a simpler way of implementing the circuit NAND. NOR: can be used to implement any of the basic Boolean operations GE"
    },
    {
      "page_index": 111,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_053.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_053.png",
        "page_index": 111,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:18+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 53 A B C A D GE"
    },
    {
      "page_index": 112,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_054.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_054.png",
        "page_index": 112,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:25+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 54 .......................... ........... C A 0 ........ 11111111111111111 .............. 1 .............................................. B ....... 0 .............................................. ............ ................................. 1 ................................... C 0 11 ..............    .... 1 x Xo XX2 X3 X4 X5 X6 X7 X8X,X10 X1Xi2X13X14 X 0 0 0 0 0 GE"
    },
    {
      "page_index": 113,
      "chapter_num": 3,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_055.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_3/slide_055.png",
        "page_index": 113,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:31+07:00"
      },
      "raw_text": "C01023-Describing Logic Circuits 55 .................. A A .. .........  0 B x ............. ...... .......................................... ... ........... c 1 ...................... .............................. B 0 ... .............................................    1 .................... C ................... ... 0 1 x Xo X X2 X3 X4 X5 X6 X7 X:X9X10 X11X12X13X4 Xi5 0 GE"
    },
    {
      "page_index": 114,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_001.png",
        "page_index": 114,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:34+07:00"
      },
      "raw_text": "C01023 Combinational Circuits - SE BK TP.HCM"
    },
    {
      "page_index": 115,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_002.png",
        "page_index": 115,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:40+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 2 Introduction  Basic logic gate functions s will be combined in combinational logic circuits. Simplification of logic circuits will be done using Boolean algebra and a Mapping technique. Basic Rules of Boolean Algebra 1. A+0=A 7. A.A=A 2. A+1=1 8. A.A=0 3. A.0=0 9. A=A 4. A:1=A 10.A+AB=A 5. A+A=A ll.A+AB=A+B 6. A+A=1 12.(A+B(A+C)=A+BC DeMorgan's Theorem (AB=(A+B (A+B)=(AB GE"
    },
    {
      "page_index": 116,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_003.png",
        "page_index": 116,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:43+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits Sum-of-Products & Product-of-Sums Forms A Sum-of-products (SOP) expression will appear as two or more AND terms ORed together. ABC + ABC AB+ ABC+CD+ D A Product-of-sums(POS) expression is sometimes used in logic design (A+B+C)(A+ B+C) 6E"
    },
    {
      "page_index": 117,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_004.png",
        "page_index": 117,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:48+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits Simplifying Logic Circuits The circuits below both provide the same output, but the lower one is clearly less complex A + BC B x = A B(A + BC) BC C (a) A B x = A B C C (b) We will study simplifying logic circuits using Boolean algebra and s Karnaugh mapping GE"
    },
    {
      "page_index": 118,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_005.png",
        "page_index": 118,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:52+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 5 Algebraic Simplification Place the  expression in SOP form by applying DeMorgan's theorems and multiplying terms. Check the SOP form for factors and perform common factoring where possible. Note that this s process may involve  some  trial and error to obtain the simplest result. GE"
    },
    {
      "page_index": 119,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_006.png",
        "page_index": 119,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:58:56+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits Designing Combinational Logic Circuits To solve any logic design problem: Interpret the problem and set up its truth table. 0 Write the AND (product) term for each case where the output equals 1 0 Combine the terms in SOP form. 0 Simplify the output expression if possible. 0 Implement the circuit for the final, simplified expression. 0 GE"
    },
    {
      "page_index": 120,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_007.png",
        "page_index": 120,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:02+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits Example of Logic Design A B C x 0 0 0 0  Design a logic circuit that has three inputs, A, B, and C 0 0 0 whose output will be HIGH only when a majority of the 0 0 0 inputs are HIGH. 0 0 0 0 X = A'BC + AB'C + ABC' + ABC 0 X =A'BC + ABC + AB'C + ABC + ABC' + ABC 0 X = BC (A'+ A) + AC(B'+ B) + AB(C' + C) X = BC + AC + AB BC X=BC+AC+AB AB GE"
    },
    {
      "page_index": 121,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_008.png",
        "page_index": 121,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:06+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 8 Karnaugh Map Method A method of simplifying logic graphical equations s or truth tables. Also called a K map. Theoretically can be used for any number of input variables, but practically limited to 5 or 6 variables. GE"
    },
    {
      "page_index": 122,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_009.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_009.png",
        "page_index": 122,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:11+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits Karnaugh Map Method The truth table values are placed in the K map. Adjacent  K  map differ in only variable both square one horizontally and vertically. The pattern from top to bottom and left to right must be in the form A SOP expression can be obtained by ORing all squares that contain a 1. AB,AB,AB,AB GE"
    },
    {
      "page_index": 123,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_010.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_010.png",
        "page_index": 123,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:15+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 10 Karnaugh Map Method Looping adjacent  groups of 2, 4, or 8 1s will result in further simplification. When the largest possible groups have been looped, only the common terms are placed in the final expression. Looping may also be wrapped between top, bottom, and sides. GE"
    },
    {
      "page_index": 124,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_011.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_011.png",
        "page_index": 124,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:24+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 11 Karnaugh Map for 2, 3 Variables  Looping adjacent groups of 2, 4, or 8 1s will result in further simplification B B A B x 0 AB A 0 1 1 0 0 1 0 x=AB+AB 1 0 0 1 1 ->AB A 0 1 1 c C A B C X AB 1 1 0 0 0 1 >ABC 0 0 1 1 ->ABC AB 1 0 0 1 0 1 ABC 0 1 1 0 X = ABC + ABC 0 0 0 + ABC + ABC 1 AB 1 0 1 0 1 0 1 1 0 1 -> ABC AB 0 0 1 1 1 0 GE"
    },
    {
      "page_index": 125,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_012.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_012.png",
        "page_index": 125,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:36+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 12 Karnaugh Map for 4 Variables  Looping adjacent groups of 2, 4, or 8 1s will result in further simplification. A B C D X X = ABCD + ABCD 0 0 0 0 0 +ABCD + ABCD 0 0 0 1 1 - ABCD 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 - ABCD CD CD CD CD 0 1 1 0 0 0 1 1 1 0 AB 0 1 0 0 1 0 0 0 0 1 0 0 1 0 AB 0 1 0 0 1 0 1 0 0 1 0 1 1 0 AB 0 1 1 0 1 1 0 0 0 1 1 0 1 1 ->ABCD AB 0 0 0 0 0 0 1 1 1 1 1 1 1 1 -ABCD GE"
    },
    {
      "page_index": 126,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_013.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_013.png",
        "page_index": 126,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:41+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 13 Minimization Technique - Minimization is done by spotting patterns of 1's and 0's  Simple theorems are then used to simplify the Boolean description of the patterns  Pairs of adjacent 1's remember that adjacent sguares differ by only one variable hence the combination of 2 adjacent squares has the form P(A+A) this can be simplified (from before) to just P ABC 00 01 11 10 0 0 0 1 0 1 0 1 1 7 GE"
    },
    {
      "page_index": 127,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_014.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_014.png",
        "page_index": 127,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T16:59:49+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 14 Example of pairs of adjacent of 1s c C c C AB 0 0 AB 0 0 AB 0 AB X = ABC + ABC X =ABC + ABO = BC =AB AB 0 AB 0 0 AB 0 0 AB 0 0 CD CD CD CD c C ABC AB AB 0 0 0 AB 0 0 0 0 X=ABCD+ ABCD AB 0 0 + ABCD+ ABCD X =ABC + ABC = BC AB =ABC +ABD 0 0 0 0 AB 0 0 AB AB 1 0 0 0 (d) ABD GE"
    },
    {
      "page_index": 128,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_015.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_015.png",
        "page_index": 128,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:00+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 15 Example of 1s (quads) grouping of fours c C CD CD CD CD CD CD CD CD AB 0 AB 0 0 AB 0 0 0 0 0 0 AB 0 AB 0 0 0 0 AB 0 0 AB 0 AB 1 1 AB 1 0 0 AB 0 AB 0 0 0 0 AB 0 0 0 0 X = C X=AB X = BD CD CD CD CD CD CD CD CD AB 0 0 0 0 AB 1 0 0 1 AB 0 0 0 0 AB 0 0 0 0 X = BD AB 1 0 0 AB 0 0 0 0 AB 1 0 0 1 AB 1 0 0 1 GE X =AD"
    },
    {
      "page_index": 129,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_016.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_016.png",
        "page_index": 129,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:10+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 16 Example of grouping of eight 1s (octals) CD CD CD CD CD CD CD CD AB 0 0 0 0 AB 0 0 AB 1 1 AB 7 0 0 AB 1 1 1 AB 1 1 0 0 AB 0 0 0 0 AB 0 0 CD CD CD CD CD CD CD CD AB 1 1 AB X = B X = C 1 0 0 1 AB 0 0 0 0 AB 1 0 0 1 AB 0 0 0 0 AB 1 0 0 1 AB AB 1 1 1 0 0 1 X =B X = D GE"
    },
    {
      "page_index": 130,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_017.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_017.png",
        "page_index": 130,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:15+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 17 Complete Simplification Process Complete K map simplification process: Construct the K map, place 1s as indicated in the truth table. 0 Loop 1s that are not adjacent to any other 1s. 0 Loop 1s that are in pairs 0 Loop 1s in octets even if they have already been looped 0 Loop quads that have one or more 1s not already looped 0 Loop any pairs necessary to include 1st not already looped. 0 Form the OR sum of terms generated by each loop. 0 6E"
    },
    {
      "page_index": 131,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_018.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_018.png",
        "page_index": 131,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:30+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 18 Example CD CD CD CD AB 0 0 0 2 AB 0 0 X = ABCD + ACD + BD 5 6 8 AB 0 1 0 loop 4 loop loop 6, 10 11 12 11,15 7,10,11 AB 0 0 1 0 13 14 15 16 (a) CD CD CD CD AB 0 0 0 2 3 4 AB 1 1 1 X = AB BC + + ACD 5 6 8 AB 1 1 0 0 lo0p 5, loop 5, loop 9 10 11 12 6,7,8 6,9,10 3,7 AB 0 0 0 0 13 14 15 16 (b) CD CD CD CD AB 0 1 0 0 2 3 4 AB 0 7 1 X = ABC + ACD ABC + ACD 5 6 8 AB 0 9,10 2,6 7,8 11,15 9 10 11 12 AB 0 0 0 13 14 15 16 GE (c)"
    },
    {
      "page_index": 132,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_019.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_019.png",
        "page_index": 132,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:36+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 19 Example CD CD CD CD CD I c CD I CD CD AB 0 0 0 AB 0 0 0 AB 0 AB 0 AB 0 0 0 AB 0 0 0 AB 0 AB 0 X = ACD + ABC + ABC + ACD X =ABD + BCD + BCD + ABD (a) (b) GE"
    },
    {
      "page_index": 133,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_020.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_020.png",
        "page_index": 133,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:44+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 20 P Q R s CD CD CD CD O O 0 1 PQR AB 1 1 0 1 O 0 1 1 P QR O 1 0 1 PQR AB 1 1 0 1 O 1 1 1 PQR 1 O O 0 AB 1 1 0 1 1 0 1 0 1 1 0 0 AB 1 1 1 1 1 1 1 1 PQR GE"
    },
    {
      "page_index": 134,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_021.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_021.png",
        "page_index": 134,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:00:54+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 21 Don't Care Conditions  In certain cases some of the minterms may never occur or it may not matter what happens if they do In such cases we fill in the Karnaugh map with X meaning don't care When minimizing an X is like a \"ioker\" X can be 0 or 1 - whatever helps best with the minimization  \"Don't care\" conditions should be changed to either 0 or 1 to produce K-map looping that yields the simplest expression. c C c C A B C z AB 0 0 AB 0 0 0 0 0 0 0 0 1 0 0 AB 0 0 AB 0 1 X 0 0 0 1 1 x \"don't 1 0 0 care\" AB 1 AB = A 1 1 0 1 1 1 1 0 1 AB x 1 AB 1 1 1 1 (a) (b) (c) GE"
    },
    {
      "page_index": 135,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_022.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_022.png",
        "page_index": 135,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:01+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 22 Terminology: Minterm - A minterm is a special product of literals, in which each input variable exactly appears once. - A function with n variables has 2\" minterms Minterm Is true when... Shorthand (since each variable can appear x'y'z' x=0,y=0,z=0 mo complemented or not) x'y'z x=0,y=0,z=1 m1  A three-variable function, such as f(x,y,z), has x'yz' x=0,y=1,z=0 m2 x'yz x=0,y=1,z=1 m3 23 = 8 minterms: xy'z' x=1,y=0,z=0 m4 xy'z x'y'z' x=1,y=0,z=1 m5 x'v'z x`yz xyz' x=1,y=1,z=0 m6 xy'z' xy`z xyz' xyz xyz x=1,y=1,z=1 m7  Each minterm is true for exactly one combination of inputs: GE"
    },
    {
      "page_index": 136,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_023.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_023.png",
        "page_index": 136,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:09+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 23 Terminology: Sum of Minterms  Every function can be written as a sum of minterms, which is a special kind of sum of products form  The sum of minterms form for any function is unique  If you have a truth table for a function, you can write a sum of minterms expression just by picking out the rows of the table where the function output is 1. f(x,y,z f'(x,y,z) f = x'y'z'+ x'y'z + x'yz'+ x'yz + xyz x y z = mo + m1 + m2 + m3 + m6 0 0 0 1 0 = m(0,1,2,3,6) 0 0 1 1 0 0 1 0 1 0 0 1 0 f'= xy'z'+ xy'z+ xyz 1 1 1 0 0 0 1 = m4 + m5 + m7 0 0 1 = m(4,5,7) 1 1 1 1 0 1 0 1 1 1 0 1 f' contains all the minterms not in f 6E"
    },
    {
      "page_index": 137,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_024.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_024.png",
        "page_index": 137,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:13+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 24 Terminology: Maxterm  A maxterm is a sum (OR) of all the variables in the function, in direct or complemented form.  A maxterm has the property that it is equal to 0 on exactly one row of the truth table 6E"
    },
    {
      "page_index": 138,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_025.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_025.png",
        "page_index": 138,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:19+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 25 Minterm and Maxterm & Binary I Representations A B C Minterm Maxterm 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 GE"
    },
    {
      "page_index": 139,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_026.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_026.png",
        "page_index": 139,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:25+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 26 Minterms and Maxterms & Binary Representations A B C Min-terms Max-terms 0 0 0 A.B.C A+B +C 0 0 1 A.B.C A+B+C 0 1 0 A.B.C A+B+C 0 1 1 A.B.C A+B+C 1 0 0 A.B.C A+B+C 1 0 1 A.B.C A+B+C 1 1 0 A.B.C A+B+C 1 1 1 A.B.C A+B+C GE"
    },
    {
      "page_index": 140,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_027.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_027.png",
        "page_index": 140,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:30+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 27 SOP-POS Conversion  Minterm values present in SOP expression not present in corresponding POS expression Maxterm values in POS present expression not present in corresponding SOP expression  Relationship between minterm m; and maxterm M; For f(A,B,C),(m1)'=(A'B'C)'=A + B + C' =M1 In general, (mi)' = M Mi'=((mi)')'=m GE"
    },
    {
      "page_index": 141,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_028.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_028.png",
        "page_index": 141,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:34+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 28 SOP-POS Conversion  Canonical Sum ABC+ ABC+ ABC+ ABC+ ABC 11A.B,c (1,4,6)  Canonical Product (A + B + C)(A + B+ C)(A + B + C) 11A.B.c (1,4,6) = 6E"
    },
    {
      "page_index": 142,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_029.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_029.png",
        "page_index": 142,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:37+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 29 Boolean Expressions and Truth Tables  Standard SOP & POS expressions converted to truth table form  Standard SOP & POS expressions determined from truth table 6E"
    },
    {
      "page_index": 143,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_030.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_030.png",
        "page_index": 143,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:44+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 30 SOP-Truth Table Conversion Input Output AB +BC A B C F 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 GE"
    },
    {
      "page_index": 144,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_031.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_031.png",
        "page_index": 144,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:50+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 31 POs-Truth Table Conversion (A + B)(B + C) Input Output A B C F 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 GE"
    },
    {
      "page_index": 145,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_032.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_032.png",
        "page_index": 145,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:54+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 32 Simplification of POS expressions using K-map  Mapping of expression  Forming of Groups of 0s Each group represents sum term 6E"
    },
    {
      "page_index": 146,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_033.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_033.png",
        "page_index": 146,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:01:59+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 33 Simplification of POS expressions using K-map (A+B).(B+ C) 0 ABC 00 01 11 10 00 0 ABC 0 O 0 0 1 1 01 1 1 1 1 1 1 11 1 1 (A +B).(A +B+ C 10 1 GE"
    },
    {
      "page_index": 147,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_034.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_034.png",
        "page_index": 147,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:04+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 34 Simplification of POS expressions using K-map (A + C).(C + D).(B + C + D) ABCD 00 01 11 10 00 0 0 1 01 0 0 1 1 11 1 0 1 1 10 1 0 1 GE"
    },
    {
      "page_index": 148,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_035.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_035.png",
        "page_index": 148,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:10+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 35 Example  Let's design a logic circuit that controls an elevator door in a three-story building. The circuit has four inputs. M is a logic signal that indicates when the elevator is moving (M= 1) or stopped (M = 0). F1,F2, and F3 are floor indicator signals that are normally LOW, and they go HIGH only when the elevator is positioned at the level of that particular floor.  For example, when the elevator is lined up level with the second floor, F2 = 1 and F1 = F3 = 0. The circuit output is the OPEN signal, which is y LOW and will go normally  HIGH when the elevator  door is to be opened. GE"
    },
    {
      "page_index": 149,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_036.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_036.png",
        "page_index": 149,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:25+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 36 Example M F1 F2 F3 OPEN O O 0 0 0 MF1F2F3 0 0 0 1 1 0 0 1 0 1 0 0 1 1 x Elevator circuit 0 1 0 0 1 0 1 0 1 x 0 1 1 0 x OPEN 0 1 1 1 x F2F3 F2F3 F2F3 F2F3 1 0 0 0 0 M F1 F2F3 F2F3 F2F3F2F3 0 0 1 0 0 1 1 7 1 1 0 1 0 0 M F1 0 1 x 1 0 x M F1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 x M F1 M F1 x x x 0 0 0 0 1 1 1 1 0 x 1 1 1 1 x M F1 0 0 0 0 M F1 0 x x x OPEN = M (F1 + F2 + F3) M F1 0 0 x 0 GE"
    },
    {
      "page_index": 150,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_037.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_037.png",
        "page_index": 150,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:29+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 37  Compared to the algebraic method, the K-map process  is a more orderly process reguiring fewer steps and always producing a minimum expression.  The minimum expression in generally is NOT unique. - For the circuits with large numbers of inputs (larger than four), other more complex technigues are used. 6E"
    },
    {
      "page_index": 151,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_038.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_038.png",
        "page_index": 151,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:34+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 38 Summary SOP and POS -useful forms of Boolean equations  Design of a comb. Logic circuit (1) construct its truth table, (2) ) convert it to a SOP, (3) simplify using Boolean algebra or K mapping, (4) implement s truth table and generating a simplified expression \"Don't cares\" e entries in K map can take on values of 1 or 0. Therefore can be exploited to help simplification 6E"
    },
    {
      "page_index": 152,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_039.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_039.png",
        "page_index": 152,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:38+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 39 Example: 2-input NAND gates  Implement The following function using only two-input NAND gates B = x'y'b + x'yb'+ x'yb + xyb = x'(y'b + yb') + yb(x'+x) by distributivity = x'(y'b + yb') + yb by complement =x'((y'b)' (yb')')' + yb by De Morgan's law =(x'((y'b)'(yb')')')'(yb)' by De Morgan's law 6E"
    },
    {
      "page_index": 153,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_040.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_040.png",
        "page_index": 153,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:45+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 40 Exclusive-OR The exclusive OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels. A A B x A 0 0 0 B B O 1 1 1 0 1 AB 1 1 0 x =AB+ AB AB A A B (a) B XOR gate symbols X x=AB to t1 t2 A = AB + AB A x=AB B B (c) (b) GE"
    },
    {
      "page_index": 154,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_041.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_041.png",
        "page_index": 154,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:52+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 41 Exclusive-NOR The exclusive NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level. XOR and XNOR outputs are opposite A A A B AB 0 0 B 1 B 0 1 0 1 O 0 1 1 1 X=AB +AB B AB A (a) XNOR gate symbols A x=AB=AB+AB A x=AB =1 B B (b) (c) GE"
    },
    {
      "page_index": 155,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_042.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_042.png",
        "page_index": 155,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:02:58+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 42 Parity Generator and Checker Even-parity generator XOR and XNOR gates  for Original D are useful in circuits data Parity (P) D1 parity and generation D Transmitted checking. data with parity bit (a) Even-parity checker D Error (E) From D. {1=error transmitter 0= no error} D1 D (b) GE"
    },
    {
      "page_index": 156,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_043.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_043.png",
        "page_index": 156,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:02+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 43 Enable/Disable Circuits A circuit is enabled when it allows the passage of an input signal to the output. A circuit is disabled when it prevents the passage of an input signal to the output. Situations requiring enable/disable circuits occur frequently in digital circuit design. 6E"
    },
    {
      "page_index": 157,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_044.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_044.png",
        "page_index": 157,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:06+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 44 Enable/Disable Circuits  AND gate function act as enable/disable circuits ENABLE DISABLE x=A  NAND gate function act as enable/disable circuits X=A X B=0 GE"
    },
    {
      "page_index": 158,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_045.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_045.png",
        "page_index": 158,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:12+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 45 Enable/Disable Circuits  Design a logic circuit that will allow a signal to pass to the output only when control inputs B and C are both HIGH; otherwise, the output will stay LOW X B  Design a logic circuit that will allow a signal to pass to the output only when one, but not both, of the control inputs are HiGH; otherwise, the output will stay HIGH. A + GE"
    },
    {
      "page_index": 159,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_046.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_046.png",
        "page_index": 159,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:16+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 46 Merging & Inversion Circuits  OR gate performs signal merging function A B x  XOR gate performs selectable inversion function A B X 6E"
    },
    {
      "page_index": 160,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_047.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_047.png",
        "page_index": 160,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:22+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 47 Basic Characteristics of Digital ICs IC \"chipsj consist of resistors, diodes, and transistors fabricated on a piece of semiconductor material called l a substrate. Digital ICs may be categorized according to the number of logic gates on the substrate: SSI - less than 12 0 MSl - 12 to 99 0 LSl - 100 to 9999 0 VLSl - 10,000 to 99,999 0 ULSI - 100,000 to 999,999 0 GSl - 1,000,000 or more 0 GE"
    },
    {
      "page_index": 161,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_048.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_048.png",
        "page_index": 161,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:28+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 48 Basic Characteristics of Digital ICs  The first package we will examine is the dual in line package (DiP) 141312 11 10 8 Notch Chip may have smalldot near pin 7 2 3 4 5 6 7 14 3 2 (a) (b) Actual silicon chip Pin 8 Pin 1 Pin 14 GE"
    },
    {
      "page_index": 162,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_049.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_049.png",
        "page_index": 162,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:36+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 49 Basic Characteristics of Digital ICs ICs are also categorized by the type of components used in their circuits. Bipolar ICs use NPN and PNP transistors 0 Unipolar ICs use FET transistors. 0 The transistor-transistor logic (TTL) and the complementary metal-oxide semiconductor (CMOS) families will both be examined. +V DD +Vcc (14) (14) 3.6 k 1.6 k 115 R1 R2 R4 Input A (1) Output (2) D2 Output Y Input A O (2) GND (1) (7) (b) D k0 R3 Pin number GND(7) GE (a)"
    },
    {
      "page_index": 163,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_050.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_050.png",
        "page_index": 163,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:42+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 50 Basic Characteristics of Digital ICs  The TTL family consists of subfamilies as listed in the table TTL Series Prefix Example IC Standard TTI 74 7404 (hex INVERTER Schottky TTL 74S 74S04 (hex INVERTER) Low-power Schottky TTL 74LS 74LS04 (hex INVERTER) Advanced Schottky TTL 74AS 74AS04 (hex INVERTER) Advanced low-power 74ALS 74ALS04 (hex INVERTER) Schottky TTL GE"
    },
    {
      "page_index": 164,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_051.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_051.png",
        "page_index": 164,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:48+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 51 Basic Characteristics of Digital ICs  The CMOS family consists of several series, some of which are shown in the table. CMOS Series Prefix Examplc IC Metal-gate CMOS 40 4001 (quad NOR gates) Metal-gate, pin-compatible with TTL 74C 74C02 (quad NOR gates) Silicon-gate, pin-compatible with TTL, 74HC 74HC02 (quad NOR gates) high-speed Silicon-gate, high-speed, pin-compatible and 74HCT  74HCT02 (quad NOR gates) electrically compatible with TTL Advanced-performance CMOs, not pin- 74AC 74AC02 (quad NOR) compatible or electrically compatible with TTL Advanced-performance CMOS, not pin- 74ACT 74ACT02 (quad NOR) compatible with TTL, but electrically compatible with TTL GE"
    },
    {
      "page_index": 165,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_052.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_052.png",
        "page_index": 165,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:53+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 52 Basic Characteristics of Digital ICs Power (referred to as Vcc) and ground connections are required for chip operation. Vcc for TTL devices is normally +5 V. TTL CMOS* 5.0 V 5.0 V . LOGlC 1 LOGlC 1 3.5 V . 2.0 V . Indeterminate Indeterminate 1.5 V . 0.8 V . . LOGIC 0 LOGlC 0 0 V 0 V *VDD=+ 5 V GE (a) (b)"
    },
    {
      "page_index": 166,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_053.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_053.png",
        "page_index": 166,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:03:58+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 53 Basic Characteristics of Digital ICs Inputs  that said to be floating. The t are not connected are consequences of floating inputs differ for TTL and CMOS. Floating TTL input acts like a logic 1. The voltage measurement may appear in the indeterminate range, but the device will behave as if there is a 1 on the floating input. Floating CMOS inputs can cause overheating and damage to the 0 device.  Some ICs have protection circuits built in, but the best practice is to tie all unused inputs either high or low. GE"
    },
    {
      "page_index": 167,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_054.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_054.png",
        "page_index": 167,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:03+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 54 Troubleshooting Digital Systems 3 basic steps Fault detection, determine operation to expected operation 0 Fault isolation, test and measure to isolate the fault. 0 Fault correction, repair the fault 0 Good troubleshooting skills come through experience in actual hands- on troubleshooting. The basic troubleshooting tools s used here  will be: the logic probe oscilloscope, and logic pulser. The most important tool is the technician's brain. 6E"
    },
    {
      "page_index": 168,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_055.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_055.png",
        "page_index": 168,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:10+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 55 Troubleshooting Digital Systems  The logic probe will indicate the presence or absence of a signal when touched to a pin as indicated below. LEDs Red Green Yellow Logic Condition Logic probe OFF ON OFF LOW To GND ON OFF OFF HIGH OFF OFF OFF INDETERMINATE' x X FLASHING PULSING Indicator LEDs lncludes open or floating condition IC +5 V PC Board GND GE"
    },
    {
      "page_index": 169,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_056.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_056.png",
        "page_index": 169,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:13+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 56 Internal Digital IC Faults Most common internal failures: Malfunction in the internal circuitry 0 Inputs or outputs shorted to ground or Vcc 0 Inputs or outputs open-circuited 0 Short between two pins (other than ground or Vcc) 0 GE"
    },
    {
      "page_index": 170,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_057.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_057.png",
        "page_index": 170,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:19+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 57 Internal Digital IC Faults Malfunction in internal circuitry Outputs do not respond properly to inputs. Outputs are unpredictable. 0 Input internally shorted to ground or supply The input will be stuck in LOW or HIGH state. 0 Output internally shorted to ground or supply Output will be stuck in LOW or HIGH state. 0 Open-circuited input or output Floating input in a TTL device will result in a HIGH output. Floating input in a CMOS device will result in erratic or possibly destructive output. An open output will result in a floating indication. Short between two pins The signal at those pins will always be identical. 6E"
    },
    {
      "page_index": 171,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_058.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_058.png",
        "page_index": 171,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:23+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 58 External Faults Open signal lines - signal is prevented from moving between points. Some causes: Broken wire 0 Poor connections (solder or wire-wrap 0 Cut or crack on PC board trace Bent or broken IC pins 0 Faulty lC socket 0 Detect visually and verify with an ohmmeter. GE"
    },
    {
      "page_index": 172,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_059.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_059.png",
        "page_index": 172,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:27+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 59 External Faults Shorted signal lines - the same signal will appear on two or more pins. Vcc or ground may also be shorted. Some causes: Sloppy wiring 0 Solder bridges 0 Incomplete etching Detect visually and verify with an ohmmeter. GE"
    },
    {
      "page_index": 173,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_060.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_060.png",
        "page_index": 173,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:32+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 60 External Faults Faulty power supply - ICs will not operate  or will operate erratically May lose regulation due to an internal fault or because circuits are drawing too much current. Always verify that power supplies are providing the specified range 0 of voltages and are properly grounded. Use an oscilloscope to verify that AC signals are not present. 0 GE"
    },
    {
      "page_index": 174,
      "chapter_num": 4,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_061.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_4/slide_061.png",
        "page_index": 174,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:36+07:00"
      },
      "raw_text": "CO1023- Combinational Circuits 61 External Faults Output loading - caused by connecting too many inputs to the output of an lC. Causes output voltage to fall into the indeterminate range. 0 This is called /oading the output. 0 Usually a result of poor design or bad connection. 0 6E"
    },
    {
      "page_index": 175,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_001.png",
        "page_index": 175,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:40+07:00"
      },
      "raw_text": "C01023 Flip Flop - BK TP.HCM"
    },
    {
      "page_index": 176,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_002.png",
        "page_index": 176,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:45+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 2 Introduction  So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables  Here we will look at Sequential Logic circuits The output(s) can depend on present and also past values of the input and the output variables. Sequential circuits exist in one of a defined number of states at any one time They move  \"sequentially\" through a defined sequence of transitions from one state to the next. The output variables are used to describe the state of a sequential circuit either directly or by deriving state variables from them. 6E"
    },
    {
      "page_index": 177,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_003.png",
        "page_index": 177,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:49+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 3 General Digital System Combinational Memory outputs outputs Combinational 1 Memory logic elements gates 1 External inputs GE"
    },
    {
      "page_index": 178,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_004.png",
        "page_index": 178,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:04:55+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits Synchronous and Asynchronous Sequential Logic Synchronous The timing of all state transitions is controlled by a common clock Changes in all variables occur simultaneously Asynchronous State transitions occur independently of any clock and normally dependent on the timing of transitions in the input variables Changes in more than one output do not necessarily occur simultaneously Clock A clock signal is a square wave of fixed frequency Often, transitions will occur on one of the edges of clock pulses i.e. the rising edge or the falling edge SE"
    },
    {
      "page_index": 179,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_005.png",
        "page_index": 179,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:00+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 5 General Flip-Flop General flip-flop symbol and definition of its two possible output states Output states Q Normal Q = 1,Q= 0: called HIGH or 1 output state; also called SET state FF Inputs Q Inverted Q = 0,Q=1: called LOW or 0 state; output also called CLEAR or (a) RESET state (b) - We now introduce the concept of memory. The flip-flop, abbreviated FF is a key memory element.  The outputs of a flip flop are Q and Q  Q is understood to be the normal output, Q' is always the opposite 6E"
    },
    {
      "page_index": 180,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_006.png",
        "page_index": 180,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:05+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits NAND Gate Latch The NAND gate latch or simply latch is a basic FF The inputs are set and clear (reset) The inputs are active low, that is the output will change when the input is pulsed low. When the latch is set Q =1 and Q = 0 0 When the latch is clear or reset Q= 0 and Q = 1 0 SE"
    },
    {
      "page_index": 181,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_007.png",
        "page_index": 181,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:10+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits Example  A NAND latch is an example of a bistable device SET SET NAND 0 0 1 0 11 1 0 1 Q 1 10 2 2 RESET RESET GE"
    },
    {
      "page_index": 182,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_008.png",
        "page_index": 182,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:14+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 8 Setting the NAND Flip-Flop SET SET 0 0 t0 t1 2 2 RESET RESET NAND 0 0 1 0 11 1 01 1 1'0 SE"
    },
    {
      "page_index": 183,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_009.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_009.png",
        "page_index": 183,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:20+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits Resetting the NAND Flip-Flop SET SET 0 0 t1 RESET 2 to t1 RESET 2 0 0 NAND to t1 0 01 0 11 1 0 1 1 10 SE"
    },
    {
      "page_index": 184,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_010.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_010.png",
        "page_index": 184,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:25+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 10 Function Table of a NAND latch SET Q Set Reset Output 1 1 No change 0 1 Q= 1 1 0 Q = 0 0 0 Invalid* Q *Produces Q = Q = 1 RESET (b) (a) SE"
    },
    {
      "page_index": 185,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_011.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_011.png",
        "page_index": 185,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:30+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 11 NAND Gate Latch - Summary SET = RESET = 1 Normal resting state, outputs remain in state prior to input. SET = 0RESET =1 Q will go high and remain high even if the SET input goes high SET = 1.RESET = 0 Q will go low and remain low even if the RESET input goes high SET = RESET = 0 Output is unpredictable because the latch is being set and reset at the same time. SE"
    },
    {
      "page_index": 186,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_012.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_012.png",
        "page_index": 186,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:34+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 12 Other Representations of a NAND latch  Symbols indicate Q is set (high) when S is low. SET S Q LATCH Q R Q RESET (a) (b) SE"
    },
    {
      "page_index": 187,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_013.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_013.png",
        "page_index": 187,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:39+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 13 Determine Q SET RESET Q 0 1 1 T1 Tz T3 T 4 T5 T6 SE"
    },
    {
      "page_index": 188,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_014.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_014.png",
        "page_index": 188,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:43+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 14 Determine Q SET RESET Q 0 - / 1 T1 T 4 T5 T6 SE"
    },
    {
      "page_index": 189,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_015.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_015.png",
        "page_index": 189,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:48+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 15 An Example of NAND latch Application +5 V Random \"bouncing 5 V 2 OUT 0 V Switch comes to rest Switch to in position 2 position 2 NAND latch used to debounce a mechanical switch +5 V 2 VOUT 0 R Switch to Switch back to position 2 position 1 SE +5 V"
    },
    {
      "page_index": 190,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_016.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_016.png",
        "page_index": 190,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:05:52+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 16 NOR Gate Latch The NOR latch is similar to the NAND Iatch except that the Q and Q outputs are reversed. The SET and RESET inputs are active high, that is, the output will change when the input is pulsed high In order to ensure that a FF begins operation at a known level, a pulse may be applied to the SET or RESET inputs when a device is powered up. SE"
    },
    {
      "page_index": 191,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_017.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_017.png",
        "page_index": 191,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:00+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 17 NOR Gate Latch  (a) NOR gate latch; SET Q Set Reset Output (b) function table; S Q 0 O No change 1 O Q=1 (c) simplified block symbol LATCH 0 1 Q=0 1 1 Invalid* R Q 2 *Produces Q = Q= 0 RESET (b) (c) (a) SET RESET Determine Q for a l NOR 0 latch given the inputs Q 0 T2 T3 T4 T6 T1 SE"
    },
    {
      "page_index": 192,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_018.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_018.png",
        "page_index": 192,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:07+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 18 SR latch useful when temporary setting is used to activate switch +5 V  The NAND FF is used to provide a bounce free switch so that the 1 KHz pulse can propagate to the output without distortion. S Q Alarm + +5 V +5 V 1 kHz R SW1 SET 3 Z2 3 2 Y Q Z1 6 Q Z2 6 5 Z1 5 B Switch CLEAR XA XB position A Pulses LOW B LOW Pulses SE"
    },
    {
      "page_index": 193,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_019.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_019.png",
        "page_index": 193,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:11+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 19 Digital Pulses The transition from low to high on a positive pulse is called rise time (tr). Rise time is measured between the 10% and 90% points on the leading edge of 0 the voltage waveform. The transition from high to low on a positive pulse is called fall time (ti) Fall time is measured between the 9o% and 10% points on the trailing edge of 0 the voltage waveform. 6E"
    },
    {
      "page_index": 194,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_020.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_020.png",
        "page_index": 194,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:15+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 20 Rise and Fall times 90% Positive pulse 50% 10% Time (a) 90% Negative pulse 10% Time Leading edge Trailing edge (b) SE"
    },
    {
      "page_index": 195,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_021.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_021.png",
        "page_index": 195,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:20+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 21 Rise and Fall times Signal that activates an active-low output with: tw = 50ns, tr =15ns, and tf = 10 ns. 5.0 V 4.5 V  50 ns 0.5V  0 10 50 100 Time (ns) SE"
    },
    {
      "page_index": 196,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_022.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_022.png",
        "page_index": 196,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:25+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 22 Clock Signals and Clocked Flip-Flops Asynchronous system - outputs change state at any time the  can c input(s) change Synchronous system - output can change state only at a specific time in the clock cycle. The clock signal is a rectangular pulse train or square wave. 0 Positive going transition (PGT) - when clock pulse goes from 0 to 1. 0 Negative going transition (NGT) - when clock pulse goes from 1 to 0. 0 Transitions are also called edges 0 GE"
    },
    {
      "page_index": 197,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_023.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_023.png",
        "page_index": 197,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:30+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 23 Ideal Clock Signals Positive-going Negative-going transition (PGT) transition (NGT) 1 0 Time (a) 1 0 (b) GE"
    },
    {
      "page_index": 198,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_024.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_024.png",
        "page_index": 198,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:35+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 24 Clock Signals and Clocked Flip-Flops Clocked FFs change state on one or the other clock transitions. Some common characteristics Clock inputs are labeled CLK, CK, or CP 0 A small triangle at the CLK input indicates that the input is activated with a PGT 0 A bubble and a triangle indicates that the CLK input is activated with a NGT. 0 Control inputs have an effect on the output only at the active clock transition 0 (NGT or PGT). These are also called synchronous control inputs. The control inputs get the FF outputs ready to change, but the change is not 0 triggered until the CLK edge. 6E"
    },
    {
      "page_index": 199,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_025.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_025.png",
        "page_index": 199,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:38+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 25 Clocked Flip-Flops Control Control inputs inputs CLK CLK Q Q CLK is activateo CLK is activated by a PGT by an NGT (a) (b) GE"
    },
    {
      "page_index": 200,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_026.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_026.png",
        "page_index": 200,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:43+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 26 Clock Signals and Clocked Flip-Flops Setup time (ts) is the minimum time interval before the active CLK transition that the control input must be kept at the proper level. Hold time (t) is the time after the active CLK transition during which the control input must kept at the proper level. Synchronous control input Clock input ts tH Setup time Hold time (a) (b) 6E"
    },
    {
      "page_index": 201,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_027.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_027.png",
        "page_index": 201,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:06:53+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 27 Clocked S-R Flip-Flop The SET-RESET (or SET-CLEAR) ) FF will change states at the positive going or negative going clock edge. S Q S CLK 0 1 1 R Q FF triggers R onpositive transition (a) 0 1 Inputs Output OLK S R CLK Q 0 0 0 1 Qo(no change) a b C d e f g h 1 0 - 1 1 1 0 1 1 0 Q 1 1 1 Ambiguous 0 Qois output level prior toTof CLK Time No Set Reset Set Set  of CLK produces no change in Q change GE"
    },
    {
      "page_index": 202,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_028.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_028.png",
        "page_index": 202,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:01+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 28 Clocked SR Flip-Flop  Clocked S-R flip-flop that triggers only on negative-going transitions. Inputs Output S Q S R CLK Q 0 0 Qo (no change) CLK 1 0 1 0 1 0 R Q 1 Ambiguous 1 1 Triggers on negative edge SET Simplified version of the internal Edge circuitry for an edge-triggered S-R CLK detector CLK * flip-flop. Q 2 R RESET Pulse-steering NAND latch SE circuit"
    },
    {
      "page_index": 203,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_029.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_029.png",
        "page_index": 203,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:05+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 29 Clocked SR Flip-Flop  Implementation of edge-detector circuits used in edge-triggered flip-flops: (a PGT; (b) NGT. The duration of the CLK* pulses is typically 2-5 ns. CLK CLK CLK- CLK - CLK* CLK* CLK CLK CLK CLK CLK* CLK * (a) (b) SE"
    },
    {
      "page_index": 204,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_030.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_030.png",
        "page_index": 204,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:10+07:00"
      },
      "raw_text": "CO1023-Combinational Circuits 30 Clocked J-K Flip-Flop Operates like the S-R FF J is set 0 K is clear. 0 When J and K are both high the output is toggled from whatever state it is in to the opposite state. May be positive going or negative going clock trigger. Has the ability to do everything the S-C FF does, plus operate in toggle mode. SE"
    },
    {
      "page_index": 205,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_031.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_031.png",
        "page_index": 205,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:21+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 31 Clocked J-K Flip-Flop J Q J K CLK Q 0 0 T Qo (no change) CLK 1 0 T 1 0 1 T 0 K Q 1 1 T Q o (toggles) (a) 1 J 0 / 1 1 K 1 1 0 1 CLK 0 a b c d e f g h i i k Time 1 1 1 1 Q 1 0 Reset Toggle No Set Toggle Toggle change (b) GEI"
    },
    {
      "page_index": 206,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_032.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_032.png",
        "page_index": 206,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:25+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 32 Edge-triggered J-K Flip-Flop  CLK* must be high for FF to change states. This condition only occurs at the edge of a CLK transition. SET 3 CLK CLK * Edge detector 4 Q K 2 RESET Pulse-steering NAND latch circuit SE"
    },
    {
      "page_index": 207,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_033.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_033.png",
        "page_index": 207,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:33+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 33 Clocked D Flip-Flop  One data input. D Q  The output changes to the D CLK Q O T 0 value of the input at either the 1 T 1 CLK Q positive going or negative (a) going clock trigger. D 0 1 CLK 0 a b C d e g 1 Q / 0 (b) GEI"
    },
    {
      "page_index": 208,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_034.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_034.png",
        "page_index": 208,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:37+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 34 Edge-triggered D Flip-Flop implementation from a J-K Flip-Flop D Q D Q CLK CLK CLK K Q Q (a) (b) SE"
    },
    {
      "page_index": 209,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_035.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_035.png",
        "page_index": 209,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:41+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 35 Parallel transfer of binary data using D Flip-Flops X Combinational logic D circuit z TRANSFER After occurrence of NGT"
    },
    {
      "page_index": 210,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_036.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_036.png",
        "page_index": 210,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:44+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 36 D Latch  (Transparent Latch) One data input. The clock has been replaced by an enable line. The device is NOT edge triggered The output follows the input only when EN is high 6E"
    },
    {
      "page_index": 211,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_037.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_037.png",
        "page_index": 211,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:51+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 37 D Latch  D latch: (a) structure; (b) function table; (c) logic symbol. NAND LATCH SET Inputs Output 1 EN D Q 0 x Qo (no change) ENABLE 1 0 0 (EN) 1 1 1 \"X\" indicates \"don't care.' Q o is state Q just Q RESET prior to EN going LOW 2 (b) (a) D Q EN Q (c) SE"
    },
    {
      "page_index": 212,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_038.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_038.png",
        "page_index": 212,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:07:55+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 38 D Latch  Waveforms showing the two modes of operation of the transparent D latch. EN D Q T2 T 3 1 'Latched' \"Transparent\" \"Latched' \"Transparent' \"Latched' at Q = 0 Q = D at Q = 1 Q = D at Q = 0 GEI"
    },
    {
      "page_index": 213,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_039.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_039.png",
        "page_index": 213,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:00+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 39 Asynchronous Inputs Inputs that depend on the clock are synchronous  Most clocked FFs have asynchronous s inputs that do not depend on the clock. The labels PRE and CLR are used for asynchronous inputs.  Active low asynchronous inputs will have a bar over the labels and inversion bubbles  If the asynchronous s inputs are not used they will be tied to their inactive state. SE"
    },
    {
      "page_index": 214,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_040.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_040.png",
        "page_index": 214,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:09+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 40 Clocked J-K flip-flop with Asynchronous  Inputs PRESET J K Clk PRE CLR Q 0 0 1 1 Q (no change) Q 0 1 1 1 0 (Synch reset) 1 0 1 (Synch set) 1 CLK 1 1 1 Q (Synch toggle) 1 X X X 1 1 Q (no change) K Q X X X 1 0 0 (asynch clear) X X X 0 1 1 (asynch preset) x x x 0 0 (Invalid) CLEAR SE"
    },
    {
      "page_index": 215,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_041.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_041.png",
        "page_index": 215,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:15+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 41 Clocked J-K Flip-Flop with Asynchronous Inputs J,K 1 CLK +5 V PRE 0 PRE PRE 0 CLK CLK CLR K Q CLR 0 Q 0 CLR a b C d e f g (a) Point Operation a Synchronous toggle on NGT of CLK b Asynchronous set on PRE = 0 c Synchronous toggle d Synchronous toggle e Asynchronous clear on CLR = 0 f CLR overrides the NGT of CLK g Synchronous toggle (b) SE"
    },
    {
      "page_index": 216,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_042.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_042.png",
        "page_index": 216,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:21+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 42 Flip-Flop Timing Considerations Important timing parameters: Setup and hold times Propagation delay: the time for a signal at the input to be shown at the output. 0 Maximum clocking frequency: highest clock frequency that will give a reliable 0 output. Clock pulse high and low times: minimum time that the clock must be high 0 before going low, and low before going high. Asynchronous active pulse width: the minimum time PRESET or CLEAR must 0 be held for the FF to set or clear reliably. Clock transition times: maximum time for the clock transitions, generally less 0 than 50 ns for TTL, or 200 ns for CMOS devices. 6E"
    },
    {
      "page_index": 217,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_043.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_043.png",
        "page_index": 217,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:26+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 43 Flip-Flop  Propagation Delays CLK 50% CLK  50% Q 50% Q 50% t pLH t pHL Delay going from Delay going from LOW to HlGH HIGH to LOW (a) (b) SE"
    },
    {
      "page_index": 218,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_044.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_044.png",
        "page_index": 218,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:31+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 44 Clock LOW and HIGH time Similarly for asynchronous signals - but may have a different value than the CLK signal. 1 PRE CLOCK or CLR 0 0 Ktw(L) -H KF tw(H) -H Ktw(L) -I (a) (b) synchronous asynchronous SE"
    },
    {
      "page_index": 219,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_045.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_045.png",
        "page_index": 219,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:35+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 45 Potential Timing Problems in FF Circuits When the output of one FF is connected to the input of another FF and both devices are triggered by the same clock, there is a potential timing problem. Propagation delay may cause unpredictable outputs The low hold time parameter of most FFs mean this won't normally be a problem. SE"
    },
    {
      "page_index": 220,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_046.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_046.png",
        "page_index": 220,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:40+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 46 Propagation Delay in Synchronous Circuits The input (Jz) to Qz must be CLOCK held for t. after the clock  CLK > CLK edge. K1 Q1 K2 Q2 This will occur only if tpH > tH CLOCK pulse 0  Usually, this is the case. Q1 (J2) O t pHL 0f Q1 1 0 t pLH 0f Q2 SE"
    },
    {
      "page_index": 221,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_047.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_047.png",
        "page_index": 221,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:44+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 47 Flip-Flop Synchronization  Most systems are primarily synchronous in operation, in that changes depend on the clock. Asynchronous and synchronous operations are often combined.  The random nature of asynchronous inputs can result in unpredictable results. 6E"
    },
    {
      "page_index": 222,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_048.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_048.png",
        "page_index": 222,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:49+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 48 Asynchronous Signals may have Undesirable Side Effects  Asynchronous signal A can produce partial pulses at X CLOCK Debounced A switch X A x CLOCK Partial pulses (a) (b) SE"
    },
    {
      "page_index": 223,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_049.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_049.png",
        "page_index": 223,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:55+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 49 Edge-triggered flip-flop can synchronize circuit The signal A has no effect A Debounced until negative edge of clock. D Q switch X CLK CLOCK (a) CLOCK A Q T1 Complete pulses (b) SE"
    },
    {
      "page_index": 224,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_050.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_050.png",
        "page_index": 224,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:08:59+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 50 Data Storage  and Transfer  Asynchronous transfers are controlled by PRE and CLR inputs Transferring the bits of a register simultaneously is a parallel transfer. Transferring the bits of a register a bit at a time is a serial transfer SE"
    },
    {
      "page_index": 225,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_051.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_051.png",
        "page_index": 225,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:05+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 51 Asynchronous Data Transfer Operation  Uses PRE and CLR inputs to load data into FF PRE and CLR won't be both low at the same time A =1,EN =1,PRE = 0,sets B =1 A =0,EN =1,CLR = 0,sets B = 0 PRE A B CLK CLK K A K B CLR Transfer enable SE"
    },
    {
      "page_index": 226,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_052.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_052.png",
        "page_index": 226,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:10+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 52 Synchronous transfer of contents of register X into register Y SOURCE DESTINATION Register X Register Y Data (Dz DDo) D2 D 2 clk X2 D1 X1 D clk X1 Y1 Do Xo D Yo clk Xo Yo TRANSFER SE"
    },
    {
      "page_index": 227,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_053.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_053.png",
        "page_index": 227,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:15+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 53 Serial Data Transfer: Shift Registers When FFs are arranged as a shift register, bits will shift with each clock pulse. FFs used as shift registers must have very low hold time parameters to perform predictably. Modern FFs have th values well within what is required. The direction of data shifts will depend on the circuit reguirements and the design. SE"
    },
    {
      "page_index": 228,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_054.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_054.png",
        "page_index": 228,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:19+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 54 Serial Data Transfer: Shift Registers Parallel transfers - register contents are transferred simultaneously with a single clock cycle. Serial transfers - register contents are transferred one bit at a time, with a clock pulse for each bit. Serial transfers are slower, but the circuitry is simpler. Parallel transfers are faster, but circuitry is more complex. Serial and parallel are often combined to exploit the benefits of each. SE"
    },
    {
      "page_index": 229,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_055.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_055.png",
        "page_index": 229,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:26+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 55 Four-bit Shift Register DATA IN X3 X2 J J X1 J Xo CLK CLK CLK CLK K X3 K X2 K x1 K Xo JUL Shift (a) pulses 1 Shift pulses 0 T1 T2 T3 T4 1 DATA IN O 1 X3 0 1 X2 0 1 X1 0 1 Xo 0 SE (b)"
    },
    {
      "page_index": 230,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_056.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_056.png",
        "page_index": 230,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:35+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 56 Serial Transfer from X Register into Y Register X register Y register D + D X1 D Xo D D Y D CLK CLK CLK CLK CLK CLK A Shift pulses (a) X2 X1 Xo Y2 Y1 Yo 0 0 O 0 Before pulses applied 0 0 0 0 After first pulse 0 0 0 1 0 After second pulse 0 0 0 O After third pulse (b) SE"
    },
    {
      "page_index": 231,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_057.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_057.png",
        "page_index": 231,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:40+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 57 FFs are often used to divide a frequency as illustrated in next slide. Here the output frequency is 1/8th the input (clock) frequency. The same circuit is also acting as a binary counter. The outputs will count from 0002 to 1112 The number of states possible in a counter is the modulus or MOD number. Next slide is a MOD-8 (23) counter. If another FF is added it would become a MOD-16 (24) counter. 6E"
    },
    {
      "page_index": 232,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_058.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_058.png",
        "page_index": 232,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:49+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 58 MOD-8 Asynchronous Counter 1 J Q Qo Q CLK CLK CLK K Q2 K Q K Qo All PRE and CLR are HIGH JUUL Input clock (a) pulses 2 3 4 5 6 7 8 9 10 11 Clock pulses 0 KHTQ->I 1 Qo 0 1 Q1 1 0 - 1 0 1 1 - 1 1 / 1 1 1 1 1 1 - Count 1 000001010011100101 110 111000001010100 . Q2Q1Q0 GEI"
    },
    {
      "page_index": 233,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_059.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_059.png",
        "page_index": 233,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:09:59+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 59 State Table & Diagram of MOD-8 Asynchronous Counter 22 21 20 Q2 Q1 Qo 000 O 0 0 Before applying clock pulses 111 001 0 0 1 After pulse #1 0 1 0 After pulse #2 0 1 1 After pulse #3 110 010 1 0 0 After pulse #4 1 0 1 After pulse #5 1 1 0 After pulse #6 1 1 1 After pulse #7 101 011 O 0 O After pulse #8 recycles to 000 0 0 100 1 After pulse #9 O 1 0 After pulse #10 0 1 1 After pulse #11 GEI"
    },
    {
      "page_index": 234,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_060.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_060.png",
        "page_index": 234,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:05+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 60 Microcomputer Application  Microprocessor units (MPUs) which will be studied later, perform many functions that involve the use of registers for data transfer and storage. MPUs may send data  to external registers for many purposes including Solenoid or relay control Motor starting Device positioning Motor speed controls I SE"
    },
    {
      "page_index": 235,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_061.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_061.png",
        "page_index": 235,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:11+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 61 Register A15 D X3 A14 Detect address A13 CLK A12 A11 A10 D Ag 2 A8 CLK MPU n WR Timing & control D X signal D3 CLK D2 D1 Do D Data CLK SE"
    },
    {
      "page_index": 236,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_062.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_062.png",
        "page_index": 236,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:16+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 62 Schmitt-Trigger Devices  Not a FF but shows a memory characteristic Accepts slow changing signals and produces a signal that transitions quicky  A Schmitt trigger device will not respond to an input until it exceeds the positive or negative going threshold.  There is a separation between the two threshold levels. This means that the device will \"remember\" the last threshold  exceeded until the input goes to the opposite threshold. SE"
    },
    {
      "page_index": 237,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_063.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_063.png",
        "page_index": 237,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:21+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 63 One-shot (Monostable Multivibrator) Changes from stable state to quasi-stable state for a period of time determined by external components (usually resistors and capacitors). Nonretriggerable devices will trigger and return to stable state. Retriggerable devices can be triggered while in the quasi-stable state to begin another pulse. One shots are called monostable multivibrators because they have only one stable state. They are prone to triggering by noise so, tend to be used in simple timing applications. EE"
    },
    {
      "page_index": 238,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_064.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_064.png",
        "page_index": 238,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:27+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 64 Stable state Normally low Q output Q=0,Q=1 Trigger OS input Quasi-stable state Normally high Q output Q=1,Q=0 RT CT Transitions at d and f have tp x RTCT a b C e no effect on Q 1 since it is already T HIGH 0 / 1 / 1 1 1 Q 0 Q 0 SE"
    },
    {
      "page_index": 239,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_065.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_065.png",
        "page_index": 239,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:32+07:00"
      },
      "raw_text": "C01023-Combinational Circuits 65 REXT/CEXT 74121 A1 1 & Q A2 74121 B RINT A1 R1 A2 Q CX REXT/CEXT RX/CX B (X indicates nonlogic connection) EXT (a) (b) SE"
    },
    {
      "page_index": 240,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_066.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_066.png",
        "page_index": 240,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:38+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 66 Clock Generator Circuits FFs have two stable states, so are considered bistable multivibrators One shots have  stable state one  and are considered monostable multivibrators Astable or free-running multivibrators switch back and forth between two unstable states. This makes it useful for generating clock signals for synchronous circuits. Crystal control may be used if a very stable clock is needed. ( Crystal control is used in microprocessor based systems and microcomputers where accurate timing intervals are essential. SE"
    },
    {
      "page_index": 241,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_067.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_067.png",
        "page_index": 241,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:44+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 67 Schmitt-trigger oscillator using a 7414 INVERTER. A 7413 Schmitt-trigger NAND may also be used. +5 V R 14 4 V 2 OUT 7414 7 0 V  100 pF 7T C or equivalent IC Frequency 7414 0.8/RC (R  500 O) 74LS14  0.8/RC (R  2 kN) 74HC14  1.2/RC (R  10 MO) Circuit will not oscillate if R is not kept within these limits. SE"
    },
    {
      "page_index": 242,
      "chapter_num": 5,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_068.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_5/slide_068.png",
        "page_index": 242,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:50+07:00"
      },
      "raw_text": "CO1023 - Combinational Circuits 68 Clock Generator Circuit: 555 Timer +5 V 5 V RA 4 8 OUTPUT 1 3 OV RB 555 6 timer l= 0.693 RpC 2 tz= 0.693 (Ra + Rp)C T= lq + l2 5 frequency = 1/T duty cycle = 1/T x 100% .01 uF Ra  1 kS Ra + Rg S 6.6 MS C z 500 pF GE"
    },
    {
      "page_index": 243,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_001.png",
        "page_index": 243,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:54+07:00"
      },
      "raw_text": "C01023  Arithmetic- BK 5E TP.HCM"
    },
    {
      "page_index": 244,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_002.png",
        "page_index": 244,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:10:58+07:00"
      },
      "raw_text": "CO1023 - Arithmetic Introduction Digital circuits are frequently used for arithmetic operations. Fundamental arithmetic operations binary on numbers and digital circuits which perform arithmetic operations will be examined. SE"
    },
    {
      "page_index": 245,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_003.png",
        "page_index": 245,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:02+07:00"
      },
      "raw_text": "C01023 - Arithmetic 3 Binary Addition Binary numbers are added like decimal numbers.  In decimal, when numbers sum more than 9 a carry results.  In binary when numbers sum more than 1 a carry takes place. Addition is the basic arithmetic operation used by digital devices to perform subtraction, multiplication, and division. 6E"
    },
    {
      "page_index": 246,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_004.png",
        "page_index": 246,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:07+07:00"
      },
      "raw_text": "C01023 - Arithmetic Binary Addition  0 + 0 =0 1 + O = 1  1 + 1 = 0 + carry 1  1 + 1 + 1 =1 + carry 1 Example 1010 (10) 001 (1) +1100 (12) +101 C (5) 10110 (22) +111 (7) 1101 (13) GE"
    },
    {
      "page_index": 247,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_005.png",
        "page_index": 247,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:12+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 5 Representing Signed Numbers Since it is only possible to show magnitude with a binary number, the sign (+ or -) is shown by adding an extra \"sign\" bit. A sign bit of 0 indicates a positive number. A sign bit of 1 indicates a negative number. The 2's complement system is the  most commonly  used way to represent signed numbers. SE"
    },
    {
      "page_index": 248,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_006.png",
        "page_index": 248,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:18+07:00"
      },
      "raw_text": "C01023- Arithmetic Representing Signed Numbers So far, numbers are assumed to be unsigned (i.e. positive) How to represent signed numbers? Solution 1: Sign-magnitude - Use one bit to represent the sign, the remain bits to represent magnitude 7 6 0 +27 = 0001 1011 b 0 = +ve -27 = 1001 1011 b magnitude S 1 = -ve Problem: need to handle sign and magnitude separately Solution 2: One's complement - If the number is negative, invert each bits in the magnitude t27 = 0001 1011 b -27 = 1110 0100 b Not convenient for arithmetic - add 27 to -27 results in 1111 1111b Two zero values 6E"
    },
    {
      "page_index": 249,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_007.png",
        "page_index": 249,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:24+07:00"
      },
      "raw_text": "C01023 - Arithmetic Representing Signed Numbers Solution 3: Two's complement - represent negative numbers by taking its magnitude, invert all bits and add one: Positive number +27 = 0001 1011b 0 Invert all bits 1110 0100b 0 Add 1 -27 = 1110 0101b 0 27 26 20 Unsigned number 26 20 -27 S Signed 2's complement +...+b2+bo20 x=-bn-12 SE"
    },
    {
      "page_index": 250,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_008.png",
        "page_index": 250,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:30+07:00"
      },
      "raw_text": "C01023 - Arithmetic 8 Examples of 2's Complement A common method to represent -ve numbers: use half the possibilities for positive numbers and half for negative numbers to achieve this, let the MSB have a negative weighting Construction of 2's Complement Numbers 4-bit example Decimal 2's Complement (Signed Binary -8 +4 +2 +1 5 0 1 0 1 -5 1 0 1 1 7 0 1 1 1 -3 1 1 0 1 GE"
    },
    {
      "page_index": 251,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_009.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_009.png",
        "page_index": 251,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:37+07:00"
      },
      "raw_text": "CO1023-Arithmetic Why 2's complement representation? If we represent signed numbers in 2's complement form, subtraction is the same as addition to negative (2's complemented) number. -1 +0 27 C 0001 1011 b -2 1111 0000 +1 1110 0001 - 17 0001 0001 b .3 +2 1101 0010 + 10 0000 1010 b 4 +3 1100 0011 .5 1011 0100 +4 27 0001 1011 b + 1010 -6 0101 +5 + - 17 1110 1111 b 1001 0110 +6 -7 1000 0111 + 10 0000 1010 b -8 +7 Note that the range for 8-bit unsigned and signed numbers are different 8-bit unsigned: 0 ...... +255 8-bit 2's complement signed number: -128 ...... +127 EE"
    },
    {
      "page_index": 252,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_010.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_010.png",
        "page_index": 252,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:46+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 10 Comparison Table Unsigned Binary 2' comp Note e the effect of 7 0111 7 wrap-around\" 6 0110 6 the binary representation 5 0101 5  i.e. The top of the table wraps around to 4 0100 4 3 0011 3 the bottom of the table 2 0010 2 1 0001 1 0 0000 0 15 1111 -1 14 1110 -2 13 1101 -3 12 1100 -4 11 1011 -5 10 1010 -6 9 1001 -7 8 1000 -8 6E"
    },
    {
      "page_index": 253,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_011.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_011.png",
        "page_index": 253,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:50+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 11 Sign Extension How to translate an 8-bit 2's C complement number to a 16-bit 2's complement number? -27 26 20 S -215 duplicate sign bit 26 20 S s This operation is known as sign extension SE"
    },
    {
      "page_index": 254,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_012.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_012.png",
        "page_index": 254,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:11:56+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 12 Sign Extension Sometimes we need to extend a number into more bits Decimal converting 12 into a 4 digit number gives 0012 we add 0's to the left-hand side Unsigned binary converting 0011 into an 8 bit number gives 00000011 we add 0's to the left-hand side For signed numbers we duplicate the sign bit (MSB Signed binary converting 0011 into 8 bits gives 00000011 (duplicate the 0 MSB converting 1011 into 8 bits gives 11111011 (duplicate the 1 MSB Called \"Sign Extension\" GE"
    },
    {
      "page_index": 255,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_013.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_013.png",
        "page_index": 255,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:01+07:00"
      },
      "raw_text": "CO1023- Arithmetic 13 Representing Signed Numbers  In order to change a binary number to 2's complement it must first be changed to 1's complement. To convert to 1's complement, simply change each bit to its complement. To convert 1's complement to 2's complement add 1 to the 1's complement.  A positive number is true binary with 0 in the sign bit. A negative number is in 2's complement form with 1 in the sign bit.  A number is negated when converted to the opposite sign. - A binary number can be negated by taking the 2's complement of it. 6E"
    },
    {
      "page_index": 256,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_014.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_014.png",
        "page_index": 256,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:06+07:00"
      },
      "raw_text": "CO1023- Arithmetic 14 Signed Addition The same hardware can be used for 2's complement signed numbers as for unsigned numbers This is the main advantage of 2's complement form Consider 4 bit numbers: the Adder circuitry will \"think\" the negative numbers are 16 greater than they are in fact but if we take only the 4 LSBs of the result (i.e. ignore the carry out of the MSB) then the answer will be correct providing it is with the range: -8 to +7. To add 2 n-bit signed numbers without possibility of overflow we need to: sign extend to n+1 bits use an n+1 bit adder 6E"
    },
    {
      "page_index": 257,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_015.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_015.png",
        "page_index": 257,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:11+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 15 Addition in the 2's Complement System  Perform normal binary addition of magnitudes.  The sign bits are added with the magnitude bits  If addition results in a carry of the sign bit, the carry bit is ignored  If the result is positive it is in pure binary form.  If the result is negative it is in 2's complement form. 6E"
    },
    {
      "page_index": 258,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_016.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_016.png",
        "page_index": 258,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:19+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 16 Addition in the 2's Complement System +9 0 0.0 +9 0 0.0 -4 l l 0 O +4 0 0 1 0 0 0 O l O l (+5) 0 (+13) O Don't care cari Sign bit A [Sign bit 1 0111 -9 4 l l 0 O 1 0111 -9 0 O l l (-13) +4 0 0 1 0 O Don't care car  Sign bit l 0 l l (-5) 4 Sign bit +9 0 0.0 -9 O l l l 0 0.0.0 Don't care carr 4 Bit dau C SE"
    },
    {
      "page_index": 259,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_017.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_017.png",
        "page_index": 259,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:24+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 17 Subtraction in the 2's Complement System  The number subtracted (subtrahend) is negated The result is added to the minuend  The answer represents the difference.  If the answer exceeds the number of magnitude bits an overflow results +9 0 l 0 0 l +8 10 0 0 0001 Sign bit SE"
    },
    {
      "page_index": 260,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_018.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_018.png",
        "page_index": 260,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:28+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 18 In decimal, multiplying by 10 can be achieved by shifting the number left by one digit adding a zero at the LS digit In binary, this operation multiplies by 2 In general, left shifting by N bits multiplies by 2N zeros are always brought in from the right-hand end E.g. Binary Decim al 1101 13 11010 26 110100 52 EE"
    },
    {
      "page_index": 261,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_019.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_019.png",
        "page_index": 261,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:33+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 19 Multiplication of Binary Numbers This is similar to multiplication of decimal numbers. Each bit in the multiplier is multiplied by the multiplicand  The results are shifted as we move from LSB to MSB in the multiplier  All of the results are added to obtain the final product. 1001 (9) 1011 (11) x 1 001 1 001 0000 1 001 1100011 (99) SE"
    },
    {
      "page_index": 262,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_020.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_020.png",
        "page_index": 262,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:37+07:00"
      },
      "raw_text": "CO1023 - Arithmetio 20 Binary Division This is similar to decimal long division. It is simpler because only 1 or 0 are possible. The subtraction part of the operation is done using 2's complement subtraction. If the signs of the dividend and divisor are the same the answer will be positive. If the signs of the dividend and divisor are different the answer will be negative EE"
    },
    {
      "page_index": 263,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_021.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_021.png",
        "page_index": 263,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:42+07:00"
      },
      "raw_text": "CO1023- Arithmetic 21 Summary of Signed and Unsigned Numbers Unsigned Signed MSB has a positive value (e.g. +8 for a 4-bit MSB has a negative value (e.g. -8 for a 4-bit system) system) The carry-out from the MSB of an adder can be To avoid overflow in an adder, need to sign used as an extra bit of the answer to avoid extend and use an adder with one more bit than overflow the numbers to be added To increase the number of bits, add zeros to the To increase the number of bits, sign extend by left-hand side duplicating the MSB Complementing and adding 1 converts X to (2N-X) Complementing and adding 1 converts X to -X GE"
    },
    {
      "page_index": 264,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_022.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_022.png",
        "page_index": 264,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:47+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 22 BCD Addition  When the sum of each decimal digit is less than 9, the operation is the same as normal binary addition.  When the sum of each decimal digit is greater than 9, a binary 6 is added. This will always cause a carry. 47 0100 0111 47 BCD +35 0011 0101 35 BCD 82 0111 1100 invalid 1 0110 + 6 1000 0010 valid 6E"
    },
    {
      "page_index": 265,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_023.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_023.png",
        "page_index": 265,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:51+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 23 Hexadecimal Arithmetic Hex addition: Add the hex digits in decimal If the sum is 15 or less express it directly in hex digits. If the sum is greater than 15, subtract 16 and carry 1 to the next position. Hex subtraction - use the same method as for binary numbers. - When the MSD in a hex number is 8 or greater, the number is negative. When the MSD is 7 or less, the number is positive. 6E"
    },
    {
      "page_index": 266,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_024.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_024.png",
        "page_index": 266,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:12:56+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 24 Arithmetic Circuits  An arithmetic/logic unit (ALU) accepts data stored in memory and executes logic Accumulator arithmetic and instructed by operations as Memory Logic the control unit. Control unit circuits unit B register Arithmetic/ogic unit SE"
    },
    {
      "page_index": 267,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_025.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_025.png",
        "page_index": 267,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:00+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 25 Arithmetic Circuits  Typical sequence of operations: Control unit is instructed to add a specific number from a memory Iocation to a number stored in the accumulator register. The number is transferred from memory to the B register. Number in B register and accumulator register are added in the logic circuit, with sum sent to accumulator for storage. The new number remains in the accumulator for further operations or can be transferred to memory for storage. 6E"
    },
    {
      "page_index": 268,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_026.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_026.png",
        "page_index": 268,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:06+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 26 Parallel Binary Adder  The A and B variables represent 2 binary numbers to be added. The C variables are the carries. The S variables are the sum bits. B. B B. Bo Addend bits from B register Full FA FA FA FA adder #4 #3 #2 #1 #0 S. Augend bits A4 A A1 from A register Sum appears at S4, S3, S2, S1, So outputs 6E"
    },
    {
      "page_index": 269,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_027.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_027.png",
        "page_index": 269,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:13+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 27 Half Adder A B S C  Truth Table 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Boolean Equations S = AB+ AB =AO B C = AB Implementation A A Half Adder s B (HA) B C SE"
    },
    {
      "page_index": 270,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_028.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_028.png",
        "page_index": 270,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:22+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 28 Full Adder Augend Addend Carry Sum Carry B bit bit bit bit bit  Truth Table input input input output output A B CIN S COUT S 0 0 0 0 0 0 FA 0 1 1 0 1 0 1 0 0 1 1 0 1 COUT 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 A 1 1 1 1 1 Boolean Equations S = A.B.C; + A.B.C; + A.B.C; + A.B.C. =AO B O Cj C, = ABC; + ABC; + ABC; + ABCj = AB+ AC; + BCj = AB+C;(A+ B) 6E"
    },
    {
      "page_index": 271,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_029.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_029.png",
        "page_index": 271,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:34+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 29 K maps for the full-adder outputs Augend Addend Carry Sum Carry CIN CIN CIN CIN bit bit bit bit bit input input input output output A B CIN S COUT AB 0 AB 0 0 0 0 0 0 0 0 0 1 1 0 0 1 O 1 0 0 1 1 0 1 AB 0 AB 0 1 O 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 AB 0 AB AB 0 AB 0 K map for S K map for CouT S = ABCIN + ABCIN + ABCIN + ABCIN CoUT = BCIN + ACIn + AB (a) (b) 6E"
    },
    {
      "page_index": 272,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_030.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_030.png",
        "page_index": 272,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:38+07:00"
      },
      "raw_text": "C01023 - Arithmetic 30 S = ABCIN + ABCIN + ABCIN + ABCIN CoUT = BCIN + ACIN + AB B S CIN 1 COUT FA 1 GE"
    },
    {
      "page_index": 273,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_031.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_031.png",
        "page_index": 273,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:48+07:00"
      },
      "raw_text": "C01023 - Arithmetic 31 Full Adder from  Half Adders A B HAs HAc Ci S Co  Truth Table 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 1 1 Boolean Equations Half-adder Half-adder 2 2 Sum AB 2 A 2 A ABCn A B B Cout B Cout Input ABCin carry, Cin AB Output carry, Cout 6E AB+ABCn"
    },
    {
      "page_index": 274,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_032.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_032.png",
        "page_index": 274,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:53+07:00"
      },
      "raw_text": "C01023 - Arithmetic 32 Adder Example A C A. Cout HALF B- ADDER B S A C HALF Cin* ADDER S .s B U1A sum U2A Cout 6E"
    },
    {
      "page_index": 275,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_033.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_033.png",
        "page_index": 275,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:13:58+07:00"
      },
      "raw_text": "C01023 - Arithmetic 33 Parallel Adder  Uses 1 full adder per bit of the numbers  The carry is propagated from one stage to the next most significant stage takes some time to work because of the carry propagation delay which is n times the propagation delay of one stage B. B A 0 A B A B in A2A1 +BB1 Cout 2 Cout 2 2222 (MSB) 2 1(LSB) SE"
    },
    {
      "page_index": 276,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_034.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_034.png",
        "page_index": 276,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:04+07:00"
      },
      "raw_text": "C01023- Arithmetic 34 Complete Parallel Adder With Registers Register notation - to indicate the contents s of a register we  use brackets: [A]=1011 is the same as As=1, Az=0, A1=1, Ao=1 A transfer of data to or from a register is indicated with an arrow [B]->[A] means  the contents of register B have been transferred to register A. Eg.: 1001 + 0101 using the parallel adder: t1 : A CLR pulse is applied 0 t2 : 1001 from mem-> B t3 : 1001 + 0000 -> A 0 t4 : 0101 from mem-> B 0 t5 : The sum outputs -> A 0 The sum of the two numbers is now present in the accumulator. 0 6E"
    },
    {
      "page_index": 277,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_035.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_035.png",
        "page_index": 277,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:11+07:00"
      },
      "raw_text": "C01023 - Arithmetic 35 Frommemory LOAD) CLK CLK CLK Bregister B3 B2 B1 Bo C3 C2 C1 FA FA FA FA 4-bit adder A3 D A2 A D Ao CLK >CLK >CLK >CLK Aregister CLR CLR CLR CLR CLEAR TRANSFER> CLEAR Accumulator outputs LOAD TRANSFER - 1 1 6E t1 t2 t3 t4 ts"
    },
    {
      "page_index": 278,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_036.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_036.png",
        "page_index": 278,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:16+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 36 Carry Propagation l by  Parallel adder is limited carry propagation (also s speed called carry ripple).  Carry propagation results from having to wait for the carry bits to \"ripple\" through the device.  Additional bits will introduce more delay. s have been developed to reduce the delay.  Various technigues The look-ahead is commonly used in high carry scheme speed devices. EE"
    },
    {
      "page_index": 279,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_037.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_037.png",
        "page_index": 279,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:23+07:00"
      },
      "raw_text": "CO1023 - Arithmetio 37 Integrated Circuit Parallel Adder  The most common parallel adder is a 4 bit device with 4 interconnected FAs and look-ahead Carry circuits.  Parallel adders may be cascaded together as shown to add larger numbers 8-bit augend AA6A5A A A2A1Ao AA1A 74HC283 C 74HC283 4-bit Co (high-order adder low-order adder parallel adder Co 74HC283 tt t t ttt BBB5B4 BBBBo BBBBo ZYYY 8-bit addend E3Ez E1 2o 72625242322212o 6E"
    },
    {
      "page_index": 280,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_038.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_038.png",
        "page_index": 280,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:28+07:00"
      },
      "raw_text": "C01023 - Arithmetic 38 From A register 2's-complement representation of -3 (augend) 4-bit 1 0 parallel adder Co C4 74LS283 +6 22 21 20 O (addend) +3 0 0 1 1 B3 Bz B1 Bo (resultant sum) From B register SE"
    },
    {
      "page_index": 281,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_039.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_039.png",
        "page_index": 281,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:34+07:00"
      },
      "raw_text": "CO1023- Arithmetio 39 Parallel adder used to perform subtraction (A - B) using the 2's-complement system. The bits of the subtrahend (B) are inverted (1's complement), and C, = 1 to produce the 2's complement A3 A2 A1 Ao  From A register l 1  4-bit C4 parallel adder Co = 1 (disregard) 74LS283 Inverted B3 BzB1 Bo outputs of B register Represents DIFFERENCE E3 Ez E1 Eo output GE"
    },
    {
      "page_index": 282,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_040.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_040.png",
        "page_index": 282,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:41+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 40 Parallel adder/subtractor using the 2's-complement system B register B3 B3 B2 B2 B1 B1 Bo Bo ADD ADD = 1. SUB = 0: B register passes to adder and Carry in = 0 SUB 8 ADD = 0.SUB = 1: 12 11 10 Complement of B register passes to adder and Carry B3 B2 B1 Bo Co 74LS283 in = 1 A3 A2 A1 Ao T A3 A2 A1 Ao CLK CLK CLK CLK D D D A 2 22 Transfer pulse 6E"
    },
    {
      "page_index": 283,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_041.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_041.png",
        "page_index": 283,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:51+07:00"
      },
      "raw_text": "CO1023 - Arithmetic 41 ALU Integrated Circuits Inputs Function Table A2 S2 S1 So Operation Comments A A1 Outputs 0 0 0 CLEAR FzFzFFo= 0000 Ao F3 0 0 1 B minus A >Needs Cn =1 0 1 0 A minus B F B3 0 1 1 A plus B Needs Cn = 0 F B2 74LS382/ 1 0 0 AB Exclusive-OR B F B1 74HC382 1 0 1 A+B OR Bo 1 1 0 AB AND 1 1 1 PRESET F3FFFo=1111 CN N+4 Notes: S inputs select operation OvR=1 for signed-number overflow S2 (b) OVR S S1 So ALU A =4-bit input number F= 4-bit output number B= 4-bit input number Cn+4 = carry out of MSB position Cn = carry into LSB position OVR= overflow indicator S= 3-bit operation select inputs EE"
    },
    {
      "page_index": 284,
      "chapter_num": 6,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_042.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_6/slide_042.png",
        "page_index": 284,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:56+07:00"
      },
      "raw_text": "C01023 - Arithmetic 42 Two 74HC382 ALU chips connected as an eight-bit adder Bz B6 B5 B4 Ba 0 S2 S1 So CN B3 Bz B1 BoA3 Az A1 7 Sz S1 So Cn B3 Bz B1 Bo A3 A2 A1 A 74HC382 74HC382 Cn 4 OVR Z2 Cn 4 OVR Z1 3 2 0 3 2 0 Notes: Z1 adds lower-order bits Z2 adds higher-order bits z-o = 8-bit sum. OVR of Z2 is 8-bit overflow indicator. 6E"
    },
    {
      "page_index": 285,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_001.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_001.png",
        "page_index": 285,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:14:59+07:00"
      },
      "raw_text": "C01023 Counter and Register - 1 BK 5E TP.HCM"
    },
    {
      "page_index": 286,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_002.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_002.png",
        "page_index": 286,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:04+07:00"
      },
      "raw_text": "CO1023- Counter and Register Introduction  FFs and logic  gates  combined to form various  are counters and registers.  Part 1 covers counter principles, various counter circuits, and IC counters  Part 2 covers several types of IC registers and shift register counter troubleshooting. 6E"
    },
    {
      "page_index": 287,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_003.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_003.png",
        "page_index": 287,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:09+07:00"
      },
      "raw_text": "CO1023- Counter and Register 3 Asynchronous (Ripple) Counters Review of four bit counter operation (refer to next slide) Clock is applied only to FF A. J and K are high in all FFs to toggle on every D clock pulse. Output of FF A is CLK of FF B and so forth. 0 FF outputs D, C, B, and A are a 4 bit binary number with D as the MSB. 0 After the negative transition of the 15th clock pulse the counter recycles to 0000 0 This s is an asynchronous counter because state is not changed in exact synchronism with the clock. GE"
    },
    {
      "page_index": 288,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_004.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_004.png",
        "page_index": 288,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:17+07:00"
      },
      "raw_text": "CO1023-Counter and Register 4 Four-bit Asynchronous (ripple) Counter D C B A CLKAO CLKA CLKA cLk<b o JLL D K C K B K A K *All J and K inputs assumed to be 1. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLOCK A B C D DCBA 0000:0001:0010:0011:01000101:0110:01111000:1001:1010:1011:1100:1101:1110:1111:0000:00010010 (count) -- Recycle to 0000 MOD = the number of states SE"
    },
    {
      "page_index": 289,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_005.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_005.png",
        "page_index": 289,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:21+07:00"
      },
      "raw_text": "CO1023- Counter and Register 5 Frequency Division The output frequency of each FF = the clock frequency of input / 2. The output frequency of the last FF = the clock frequency / MOD. C CLKFF K Q CLKFF K Q CLKFF K Q 6E"
    },
    {
      "page_index": 290,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_006.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_006.png",
        "page_index": 290,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:25+07:00"
      },
      "raw_text": "CO1023- Counter and Register Propagation Delay in Ripple Counters Ripple simple, but the cumulative counters are 1 propagation delay can cause problems at high frequencies.  For proper operation the following apply: F = 1/(N x tpd) max SE"
    },
    {
      "page_index": 291,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_007.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_007.png",
        "page_index": 291,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:32+07:00"
      },
      "raw_text": "C01023- Counter and Register 7 #1 #2 #3 #4 #5 Input 1000 ns 1MHz A 50 ns B 100 ns C (a) 150 ns #1 #2 #3 #4 #5 Input 10MHz 100 ns A 50 ns B 50 ns C 150 ns The 100 condition does not occur. (b) GE"
    },
    {
      "page_index": 292,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_008.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_008.png",
        "page_index": 292,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:37+07:00"
      },
      "raw_text": "C01023- Counter and Register 8 Find the smallest MOD required so that 2 is less than or equal to the requirement. Connect a NAND gate to the asynchronous CLEAR inputs of all FFs. Determine which FFs are HIGH at the desired count and connect the outputs of these FFs to the NAND gate inputs. C B A 111 000 001 State transition diagram for the MOD-6 counter Temporary 110 state 010 101 011 100 (a) GE"
    },
    {
      "page_index": 293,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_009.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_009.png",
        "page_index": 293,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:43+07:00"
      },
      "raw_text": "CO1023- Counter and Register MOD-6 Counter MOD-6 counter produced by clearing a MOD-8 3 counter when a count of six (110) occurs. All J, K C B inputs are 1. CLK CLK CLK< CLR K B CLR K CLR K Input 2 3 4 5 6 7 8 9 10 11 12 pulses A B C NAND output 0 6E"
    },
    {
      "page_index": 294,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_010.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_010.png",
        "page_index": 294,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:47+07:00"
      },
      "raw_text": "C01023- Counter and Register 10  General Procedures Counter Design Find the smallest number of FF Connect a NAND gate to the Asynchronous CLEAR inputs of all the FFs Determine which FFs will be in the HlGH state at a count = X: then connect the normal outputs of these FFs to the NAND gate inputs 6E"
    },
    {
      "page_index": 295,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_011.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_011.png",
        "page_index": 295,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:51+07:00"
      },
      "raw_text": "CO1023- Counter and Register 11 Decade counters/BcD counters Decade counters/BCD counters  states, regardless of the sequence. Any MOD-10 counter is a decade counter. A BCD counter is a decade counter that counts from binary 0000 to 1001. Decade counters are widely used for counting events and displaying results in decimal form. 6E"
    },
    {
      "page_index": 296,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_012.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_012.png",
        "page_index": 296,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:15:56+07:00"
      },
      "raw_text": "CO1023- Counter and Register 12 Asynchronous Down  Counter  All of the counters we have looked CBA were up counters. (7) 111< Down counter counts number (6) 110 downward. (5) 101 e.g., 111 -> 000 (4) 100 Recycles (3) 011 (2) 010 (1) 001 (0) 000 - 6E"
    },
    {
      "page_index": 297,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_013.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_013.png",
        "page_index": 297,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:01+07:00"
      },
      "raw_text": "CO1023- Counter and Register 13 Asynchronous Down  Counter Each FF, except the first must toggle when the preceding FF goes from LOW to HIGH If the FFs have CLK inputs that respond to negative transition (HIGH to LOW), then an inverter can be placed in front of each CLK input; however the same effect can accomplished by driving each FF CLK input from the inverted output of the preceding FF.  Input pulses are applied to A. The A' output serves as the CLK input for B ; the B' output serves as the CLK input for the C. The waveforms at A, B and C show that B toggles whenever A goes LOW to HIGH and C toggles whenever B goes LOW to HIGH. 6E"
    },
    {
      "page_index": 298,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_014.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_014.png",
        "page_index": 298,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:09+07:00"
      },
      "raw_text": "CO1023- Counter and Register 14 All J.K inputs are HIGH CLK CL CLK C K K K Input Input A ... .. ..... B .... .... .... ... ........... C ... ... ... .. ....... .. ....... Count 000 .... 111 110 ..... 101 100 ..... (CBA) 011 010 .... 001 000 111 Recycles 000 001 010 10 011 101 100 SE"
    },
    {
      "page_index": 299,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_015.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_015.png",
        "page_index": 299,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:18+07:00"
      },
      "raw_text": "C01023- Counter and Register 15 IC Asynchronous counter +Vcc 74LS293 (14) 11 CP Q Q 74LS293 (10) CPo-O>CP D>CP >CP DCP K K K a K Co CD Co Co (7) (8) (4) (5) (9) (12) (13) O O O O Q3 Q2 Q1 Qo MR1 MR2 (MSB) (LSB) CP1 MR1 MR2 LS293 MODE SELECTION Q1 Q2 Qo Q3 (LSB) (MSB) RESET INPUTS OUTPUTS \"AllJ,Kinputs are internally MR1 MR2 Q0 Q1 Q2 Q3 connected HIGH. (a) H H L L L L L H Count H L Count L L Count 6E"
    },
    {
      "page_index": 300,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_016.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_016.png",
        "page_index": 300,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:25+07:00"
      },
      "raw_text": "C01023- Counter and Register 16 Example CP Show  to wire  the  how 74LS293 74LS293 as a MOD-16 10 kHz CP MOD-10 counter with a MR1 MR2 10-kHz cock input. Determine the frequency at Q3. f =10 kHz/16= 625 Hz 0000 1001 0001 CP 74LS293 10 kHz 1000 0010 CP MR2 MR 0111 0011 f=10 kHz/10=1 kHz 0110 0100 0101 6E"
    },
    {
      "page_index": 301,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_017.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_017.png",
        "page_index": 301,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:28+07:00"
      },
      "raw_text": "CO1023-Counter and Register 17 Exercise Show how to wire the 74LS293 as a MOD-14, MOD-60, counter with a 10-kHz clock input. 6E"
    },
    {
      "page_index": 302,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_018.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_018.png",
        "page_index": 302,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:43+07:00"
      },
      "raw_text": "CO1023-Counter and Register 18 Synchronous (Parallel) Counters Count D C B A 0 O 0 0 0 1 0 0 0 1 All FFs are triggered by CLK simultaneously 2 0 0 0 3 0 0 1 1 Mod-16 counter. 4 0 1 0 0 5 0 0 1 Each FF has J and K inputs connected so they are HIGH only when 0 6 0 1 0 the outputs of all lower-order FFs are HIGH. 7 0 7 1 1 8 1 0 0 0 The total propagation delay will be the same for any number of FFs. 0 9 0 0 1 10 0 1 0 Synchronous counters operate at much higher can 11 0 1 1 frequencies than asynchronous counters. 12 1 0 0 13 1 0 1 14 1 1 0 A 15 AB 7 1 1 A 0 0 0 0 0 ABC B D C B A etc CLKA CLK< CLK< CLK< D K c K B K A K (b) CLR CLR CLR CLR Input GE (a)"
    },
    {
      "page_index": 303,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_019.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_019.png",
        "page_index": 303,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:51+07:00"
      },
      "raw_text": "CO1023- Counter and Register 19 Synchronous (Parallel) Counters  Circuit Operation On a given NGT of the clock, only those FFs that are supposed to toggle on that NGT should have J=K=1 when that NGT occurs. FF A must change states at each NGT. Its J and K inputs are permanently HIGH so that it will toggle on each NGT of the CLK input. FF B must change states on each NGT that occurs while A=1. FF C must change states on each NGT that occurs while A=B=1 FF D must change states on each NGT that occurs while A=B=C=1 0 AB ABC B D C B A CLK< CLK< CLK< CLK< D K c K B K A K CLR CLR CLR CLR Input 6E (a)"
    },
    {
      "page_index": 304,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_020.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_020.png",
        "page_index": 304,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:16:55+07:00"
      },
      "raw_text": "CO1023- Counter and Register 20 Synchronous (Parallel) Counters  Each FF should have its J&K inputs connected such that they are HIGH only when the outputs of all lower-order FFs are in the HIGH state.  Advantages over asynchronous: 1. FFs will change states simultaneously; synchronized to the NGTs of the input clock pulses. 2. Propagation delays of the FFs do not add together to produce the overall delay. 3. The total response time is the time it takes one FF to toggle plus the time for the new logic levels to propagate through a single AND gate to reach the J, K inputs. Total delay = FF tpd +AND gate tpd 6E"
    },
    {
      "page_index": 305,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_021.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_021.png",
        "page_index": 305,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:03+07:00"
      },
      "raw_text": "CO1023- Counter and Register 21 D C B CLK< CLK< CLKA CLK< MOD-14 counter resets when K C K 8 K A K CLR CLR CLR CLR count 14 is reached. O 30 kHz B C D D C B A CLKA CLK< CLK< CLK< D K C K B K A K CLR CLR CLR CLR MOD-10 (decade) counter. Resets O O when count 10 is reached. 1 MHz B D SE"
    },
    {
      "page_index": 306,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_022.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_022.png",
        "page_index": 306,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:07+07:00"
      },
      "raw_text": "CO1023- Counter and Register 22 Example: M0D-60 Counter Resets when count 60 is reached Q CLK CLK CLK CLK CLK CLK K K K K K K CLR CLR CLR CLR CLR CLR 60 Hz SE"
    },
    {
      "page_index": 307,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_023.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_023.png",
        "page_index": 307,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:13+07:00"
      },
      "raw_text": "CO1023- Counter and Register 23 Synchronous, MOD-16, Down Counter A AB A ABC B D C B A CLK< CLK D K C K B K A K CLR CLR CLR CLR Input Input A B C D SE"
    },
    {
      "page_index": 308,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_024.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_024.png",
        "page_index": 308,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:22+07:00"
      },
      "raw_text": "CO1023- Counter and Register 24 Synchronous Down and Up/Down Counters  The synchronous counter can be converted to a down counter by using the inverted FF outputs to drive the JK inputs. Up/Down CLOCK A MOD-8 synchronous up/down counter B C Count 000001 010 011 100 I 101 100011 010 (CBA) 001 000 Down (b) The counter counts when the control input Up/Down up 1 it counts down when the control input Up/Down = 0. EE"
    },
    {
      "page_index": 309,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_025.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_025.png",
        "page_index": 309,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:27+07:00"
      },
      "raw_text": "CO1023- Counter and Register 25 MOD-8 Synchronous Up/Down Counter  The counter counts up when the control input Up/Down = 1;  A and B signals are passed it counts down when the control input Up/Down = 0; inverted A and B signals are passed Up/Down B A B A A C B J A CLK CLK CL C K B K A K CLR CLR CLR CLOCK (a) 6E"
    },
    {
      "page_index": 310,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_026.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_026.png",
        "page_index": 310,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:31+07:00"
      },
      "raw_text": "CO1023-Counter and Register 26 Presettable Counters  A presettable counter can be set to any desired starting point either asynchronously or synchronously  The preset operation is also called parallel loading the counter. 6E"
    },
    {
      "page_index": 311,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_027.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_027.png",
        "page_index": 311,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:35+07:00"
      },
      "raw_text": "CO1023- Counter and Register 27 Synchronous Counter with Asynchronous s Parallel Load P Po Parallel da a PRE PRE PRE Q Qo J J CLK CLK CLK K K K CLR CLR CLR CLK Parallelload PL 6E"
    },
    {
      "page_index": 312,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_028.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_028.png",
        "page_index": 312,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:46+07:00"
      },
      "raw_text": "C01023- Counter and Register 28 IC Synchronous Counters 74ALS160- 74ALS163 CLK ENT RCO  4 FFs ENP Part Modulus Number CLR 74ALS160 10 LOAD 74ALS161 16 . PGT at the CLK input 74ALS162 10 D QD 74ALS163 16 C QC (b) B QB A QA . The counter can be preset to any (a) value (applied to the A, B, C, and D inputs) by applying 74ALS160-74ALS163FunctionTable an active-low CLR LOAD ENP ENT CLK Function Part Numbers LOAD input. L x X X X Asynch.Clear 74ALS160&74ALS161 L X X T Synchr. Clear 74ALS162 & 74ALS163 H L x x T Synchr. Load All H H H H T Count up All H H L x x No change All H H L x No change All (c) 6E"
    },
    {
      "page_index": 313,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_029.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_029.png",
        "page_index": 313,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:17:55+07:00"
      },
      "raw_text": "CO1023- Counter and Register 29 Synchronous Counter Example 74HC163 start counting at t1 CLK ENT ENT RCO RCO synchronous clear at t2 ENP ENP CLR CLR synchronous load at t3 LOAD LOAD 7 D QD QD C QC QC stop counting at t4 (ENP low) 0 B QB QB 0 A QA QA no counting at t5 (ENT low) (a) t2 13 t5 t6 t resume counting at t6 CLK CLR terminal state s sets RCO (ripple LOAD carry out) high automatic reset at t7 ENT ENP QD QC QB QA RCO (b) GE"
    },
    {
      "page_index": 314,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_030.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_030.png",
        "page_index": 314,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:03+07:00"
      },
      "raw_text": "C01023- Counter and Register 30 Synchronous Counter Example 74HC160 start counting at t1 CLK ENT ENT RCO RCO asynchronous clear at t2 ENP ENP CLR CLR asynchronous clear at t3 LOAD LOAD 0 D QD QD C QC QC stop counting at t4 (ENP Iow) B QB QB A QA QA synchronous load at t5 (a) to t2t3 L ts t6 t7 t8 tgt10 stop counting at t6 (ENT low) CLK CLR continue counting at t7 LOAD terminal state of 1001 sets RC0 ENT stop counting at t8 (ENP) ENP RCO goes low at t9 due to QD  low ENT (ENP does not affect RCO) QC QB QA RCO GE (b)"
    },
    {
      "page_index": 315,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_031.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_031.png",
        "page_index": 315,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:09+07:00"
      },
      "raw_text": "CO1023- Counter and Register 31 74ALS190-75ALS191 Series synchronous counters (up/down) 74ALS190- Part Modulus 74ALS191 Number 74ALS190 10 CLK 74ALS191 16 CTEN RCO (b) D/U 74ALS190-74ALS191 Function Table Max /Min LOAD LOAD CTEN D/U CLK Function D QD L x x x Asynch. Load C QC H L L T Count up B QB H L H T Count down A QA H H x x No change (a) (c) 6E"
    },
    {
      "page_index": 316,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_032.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_032.png",
        "page_index": 316,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:26+07:00"
      },
      "raw_text": "CO1023-Counter and Register 32 MOD-10 Counter Maximum state is 1001 t2t3 t4 t5 t6 17 t8 tg CLK Max/min is high when state is / 1001 and up-counting; or 1 1 1 1 - D/U 0000 and down-counting LOAD - 1 - 1 / - 1 1 - 1 1 1 1 1 1 1 1 1 Max/min low at other times 1 1 - - / - - 1 1 1 - 1 CTEN - - - 1 - 1 1 I 1 - - 1 1 - QD 74ALS190-74ALS191Function Table 1 1 1 1 1 - 1 1 1 - LOAD CTEN D/U CLK Function QC 1 L x x x Asynch. Load QB H L L Count up H L H T Count down QA 1 H H x X No change 1 1 1 1 1 I 1 - - MAX/MIN RCO 1 - 1 I I 1 I 1 - I 1 I I 1 1 1 I 1 6E"
    },
    {
      "page_index": 317,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_033.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_033.png",
        "page_index": 317,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:35+07:00"
      },
      "raw_text": "CO1023- Counter and Register 33 Synchronous Example : Counter JUU Using q 74ALS163  (syn load) and 74ALS163 74ALS11 CLK CLK 74ALS191(async load) MOD-16 ENT RCO ENP 0 CTEN RCO 0 D counters for other MODs. CLR Ma S-LD T-LD M LOAD LOAD QD S3 QD T3 D 0 D S2 QC T2 0 C QC C S1 0 B QB B QB T1 So TO A QA 4 QA (a) CLK Synchronous load S3 0001-1100 S2 mod-12 counter S1 SO S-LD T3 Asynchronous load T2 0001-1011 T 1 mod-11 counter ( in 1100 state for a short period of time TO T-LD 6E (b)"
    },
    {
      "page_index": 318,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_034.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_034.png",
        "page_index": 318,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:43+07:00"
      },
      "raw_text": "CO1023- Counter and Register 34 Extending Maximum  Counting Range 74ALS163 74ALS163 CLK CLK TC1 TC2 To higher-order EN ENT RCO ENT RCO counter stages ENP ENP CLR CLR least- CLR significant LD LOAD nibble LOAD D3 D QD Q3 D7 D QD Q7 D2 C QC Q2 D6 C QC Q6 D1 B QB Q1 D5 B QB Q5 DO A QA Q0 (LSB) D4 A QA Q4 stage 1 stage 2 To higher-order counter stages 6E"
    },
    {
      "page_index": 319,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_035.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_035.png",
        "page_index": 319,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:47+07:00"
      },
      "raw_text": "CO1023-Counter and Register 35 Decoding a Counter Decoding is the conversion of a binary output to a decimal value. The active high decoder could be used to light an LED representing each decimal number 0 to 7  Active low decoding is obtained by replacing the AND gates with NAND gates. SE"
    },
    {
      "page_index": 320,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_036.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_036.png",
        "page_index": 320,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:53+07:00"
      },
      "raw_text": "C01023- Counter and Register 36 Decoding a Counter C B CLK CLK CLK C K B K A K CLK > CLK Using AND Gates to Decode a C B A 000 001 010 011 100 101 110 1 1 1 MOD-8 Counter CBA (produce pulse at specific count C BA CBA 2 CBA 3 CBA 4 CBA 5 CBA 6 C B A 6E"
    },
    {
      "page_index": 321,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_037.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_037.png",
        "page_index": 321,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:18:59+07:00"
      },
      "raw_text": "CO1023- Counter and Register 37 Decoding a Counter D C D K C K B K A K CLK 2 D I0 B Circuit to Make X High Between A 0 PRE x Counts of 8 and 14 decodes 0 1000 CLK (sets FF at count 8, then clears at count 14) K x CLR state state D 1000 1110 C B A decodes 1110 6E"
    },
    {
      "page_index": 322,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_038.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_038.png",
        "page_index": 322,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:19:03+07:00"
      },
      "raw_text": "CO1023- Counter and Register 38 Analyzing Synchronous Counters Example of a synchronous up counter. The control inputs are as follows: Jc = AB, Kc = C,JB = KB = A,Ja = Ka = C 0 C B A CLK CLK CLK C K B K A K CLK 6E"
    },
    {
      "page_index": 323,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_039.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_039.png",
        "page_index": 323,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:19:09+07:00"
      },
      "raw_text": "C01023- Counter and Register 39 Analyzing Synchronous Counters 111 000 C B CLK CLK CLK 100 001 C K B K A K C B A CLK > 011 010 State transition diagram timing 101 and 110 diagram for synchronous counter CLK C Unused states not in timing diagram B A 6E"
    },
    {
      "page_index": 324,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_040.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_040.png",
        "page_index": 324,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:19:13+07:00"
      },
      "raw_text": "CO1023- Counter and Register 40 Counter Design Synchronous Determine desired number of bits and desired counting seguence Draw the state transition diagram showing all possible states  Use the diagram to create a table listing all PRESENT states and their NEXT states  Add a column for each JK input (or other inputs). Indicate the level required at each J and K in order to produce transition to the NEXT state.  Design the logic circuits to generate levels required at each JK input  Implement the final expressions. 6E"
    },
    {
      "page_index": 325,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_041.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_041.png",
        "page_index": 325,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:19:23+07:00"
      },
      "raw_text": "CO1023- Counter and Register 41 State transition diagram for the synchronous counter design 110 unused states 101 111 PRESENT State NEXT State C B A C B A 000 Line 1 0 0 0 0 0 1 2 0 0 1 0 1 O 3 0 1 0 0 1 1 001 100 4 0 1 1 1 0 0 5 1 0 0 0 0 O 6 1 0 1 0 0 0 7 1 1 O 0 0 0 8 1 1 1 0 0 O 010 011 6E"
    },
    {
      "page_index": 326,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_042.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_042.png",
        "page_index": 326,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:19:37+07:00"
      },
      "raw_text": "CO1023- Counter and Register 42 State table of counter example J K CLK Q 0 0 T Qo (no change) 1 0 T 1 0 1 T 0 1 1 T Q o (toggles) PRESENT State NEXT State 110 101 111 C B A C B A JA KA Line 1 0 0 0 0 0 1 0 x 0 x 1 x 000 2 0 0 1 0 1 0 0 x 1 x x 1 3 0 1 0 0 1 1 0 x x 0 1 x 001 100 4 0 1 1 1 0 0 1 x x 1 x 1 5 1 0 0 0 0 0 x 1 0 x 0 x 6 1 0 1 0 0 0 x 1 0 x x 1 7 1 1 0 0 O 0 x 1 x 1 0 010 x 011 8 1 1 1 0 0 0 x 1 x 1 x 1 6E"
    },
    {
      "page_index": 327,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_043.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_043.png",
        "page_index": 327,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:19:53+07:00"
      },
      "raw_text": "CO1023- Counter and Register 43 K l maps for the J and K logic circuits  K map used to obtain the simplified expression for JA ; from the state table A A PRESENT State NEXT State C B 1 X C B A C Jc Kc JB KB JA KA Line 1 0 O O 0 0 1 0 x 0 x 1 x C B 1 x 2 0 0 1 0 1 0 0 x 1 x x 1 3 0 1 0 0 1 1 0 x x 0 1 x C B 0 x 4 0 1 1 1 0 0 1 x x 1 x 1 5 1 0 0 0 0 0 x 1 0 x O x 6 1 0 1 0 0 0 x 1 0 x x 1 C B 0 x 7 1 1 0 0 O 0 x 1 x 1 O x 8 1 1 1 0 0 0 x 1 x 1 x 1 JA = C 6E"
    },
    {
      "page_index": 328,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_044.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_044.png",
        "page_index": 328,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:20:08+07:00"
      },
      "raw_text": "CO1023- Counter and Register 44 K  maps for the J and K logic circuits PRESENT State NEXT State A A A A C B A C Jc Kc JB KB JA KA C B C B O x x Line 1 O O 0 0 O 1 O x 0 x 1 x 2 0 0 1 0 1 0 0 x 1 x x 1 C B x X C B 0 1 3 O 1 0 0 1 1 O x x 0 1 x C B x x C B 4 0 1 1 0 0 1 1 1 1 1 x x x 5 1 0 0 0 0 0 x 1 0 x 0 x C B 0 0 C B x x 6 1 0 1 0 0 0 x 1 0 x x 1 JB=C A Kg= C + A 7 1 1 0 O 0 0 x 1 x 1 0 x 8 1 1 1 0 0 0 x 1 x 1 x 1 6E"
    },
    {
      "page_index": 329,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_045.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_045.png",
        "page_index": 329,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:20:24+07:00"
      },
      "raw_text": "CO1023- Counter and Register 45 K  maps for the J and K logic circuits PRESENT State NEXT State C B A C Jc Kc JB  KB JA KA A A A A Line 1 O O 0 O O 1 O x 0 x 1 x C B 0 C B 0 X X 2 0 0 1 0 1 0 0 x 1 x x 1 C B C B O x x 3 O 1 0 0 1 1 O x x 0 1 x 4 0 1 1 1 0 0 1 x x 1 x 1 C B x x C B 1 1 5 1 0 0 O 0 O x 1 0 x 0 x C B x x C B 6 1 0 1 0 0 0 x 1 0 x x 1 7 1 1 0 O 0 0 x 1 x 1 0 x Jc = B A Kc = 1 8 1 1 1 0 0 0 x 1 x 1 x 1 6E"
    },
    {
      "page_index": 330,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_046.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_046.png",
        "page_index": 330,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:20:29+07:00"
      },
      "raw_text": "CO1023- Counter and Register 46 Final Implementation Ka =1 JA = Cj JB = C'A Kp = C + A Jc = BA Kc = 1 AB Jc JB B A CLOCK CLK CLK CLK Kc C KB B KA A SE"
    },
    {
      "page_index": 331,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_047.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_047.png",
        "page_index": 331,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:20:39+07:00"
      },
      "raw_text": "C01023- Counter and Register 47 Design Example (a) A synchronous supplies Coil Coil1 A Synch 2 D  A Current the 4 appropriate sequential counter 3 amplifiers B (Direction 4 input) 8 outputs to drive  a stepper motor; Stepper Step motor (clock) (b)  state transition diagrams (a) for both states of Direction CW rotation CCW rotation D=0 D =1 input, D. BA BA 01 10 01 10 00 00 (b) 6E"
    },
    {
      "page_index": 332,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_048.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_048.png",
        "page_index": 332,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:20:53+07:00"
      },
      "raw_text": "C01023 - Counter and Register 48 State table for Design  Example Coil Coil1 A Synch 2 D A Current 4 counter 3 8 amplifiers Direction 4 PRESENT State NEXT State Control Inputs input) D B A B A JB KB JA KA Stepper Step motor (clock) 0 0 0 0 1 0 x 1 x (a) 0 0 1 1 1 1 x x 0 0 1 0 0 0 x 1 0 x CW rotation CCW rotation 0 1 1 1 0 x 0 D=0 D=1 x 1 BA BA 1 0 0 1 0 1 x 0 x 11 1 0 1 0 0 0 x x 1 1 1 O 10 1 1 x 0 1 x 01 10 1 1 1 0 1 x 1 x 0 00 00 (b) SE"
    },
    {
      "page_index": 333,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_049.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_049.png",
        "page_index": 333,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:21:06+07:00"
      },
      "raw_text": "CO1023- Counter and Register 49 K-maps for four outputs D D D D - BA 0 BA X x BA 0 BA x X BA x x BA 0 PRESENT State NEXT State Control Inputs BA x BA X 1 0 D B A B A JB KB JA KA - - 0 0 0 0 1 0 x 1 x JB = DA + DA KB = DA + DA 0 O 1 1 1 1 x x O =DA =DA 0 1 0 0 0 x 1 0 x 0 1 1 1 0 x 0 x 1 D D D D 1 0 0 1 0 1 x 0 x BA 0 BA x X 1 0 1 0 0 0 x x 1 1 1 O 1 1 x 0 1 x BA BA x x 0 1 1 1 0 1 x 1 x O BA x X BA 0 BA 0 BA x x Ja=DB + DB Ka= DB + DB =DB =DB 6E"
    },
    {
      "page_index": 334,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_050.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_050.png",
        "page_index": 334,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:21:15+07:00"
      },
      "raw_text": "C01023-Counter and Register 50 State Table for Example MOD-5 Counter Using D-type Flip-Flops PRESENT State NEXT State Control Inputs C B A C B A Dc DB DA 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 O 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 O 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 SE"
    },
    {
      "page_index": 335,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_051.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_051.png",
        "page_index": 335,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:21:29+07:00"
      },
      "raw_text": "CO1023- Counter and Register 51 K maps for Outputs - MOD-5 D-flip-flop counter PRESENT State NEXT State Control Inputs A A A A A A C B A C B A Dc DB DA C B 0 0 C B C B 0 O 0 O O O 1 0 0 1 O 0 1 0 1 0 0 0 C B 1 0 C B 0 C B 0 O 1 0 0 1 1 0 1 1 C B 0 0 C B O 0 C B 0 0 O 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 C B 0 0 C B 0 0 C B 0 0 1 0 1 0 0 0 0 0 0 1 1 0 O O 0 0 O 0 Dc = C B A Dp=CBA+CBA Da = C A 1 1 1 0 0 0 0 0 0 SE"
    },
    {
      "page_index": 336,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_052.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_052.png",
        "page_index": 336,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:21:34+07:00"
      },
      "raw_text": "CO1023- Counter and Register 52 Implementation of MOD-5, D flip-flop design Dc = C B A Dp =C B A + C B A Da = C A B A D C D D D B D A 8 CLK CLK CLK c B A CLOCKS 6E"
    },
    {
      "page_index": 337,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_053.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_053.png",
        "page_index": 337,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:21:37+07:00"
      },
      "raw_text": "CO1023-Counter and Register 53 Integrated-Circuit Registers Registers can be classified by the way data is entered for storage, and by the way data is outputted from the register. Parallel in/parallel out (PIPO) Serial in/serial out (SISO) Parallel in/serial out (PISO) Serial in/parallel out (SIPO) SE"
    },
    {
      "page_index": 338,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_054.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_054.png",
        "page_index": 338,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:21:44+07:00"
      },
      "raw_text": "CO1023- Counter and Register 54 PIS0 - The 74ALS165/74HC165 P P P 8-bit register Serial data entry via Ds 0 CP 74HC165 Asynchronous parallel data entry P, through P- CP INH 0 SH/LD Only the outputs of Qz are accessible 0 CP is clock input for shifting Q Clock inhibit input (a) Shift load input Function Table Inputs SH/LD CP CP INH Operation H = high leve L =lowlevel L x x Parallel load X = immaterial H H x No change =PGT H X H No change H L Shifting H L Shifting (b) SE"
    },
    {
      "page_index": 339,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_055.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_055.png",
        "page_index": 339,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:22:05+07:00"
      },
      "raw_text": "CO1023- Counter and Register 55 74HC165 PISO Waveforms Ds = 0, CP INH = 0, Output values for given inputs s (P0=P7) CP SH/LD - - - - 1 - - - - - - - - - 1 - - - I - - - 1 - - 0101 0011 1001 1010 / 1 - / 1 / - - 1 Q - - 1 - - / - - - - - - - (Q1) - I - - - - - 1 - - - - - - - - - - - - - - - - - - - (Q2) - - - - - - - - - - - - - - - - - - Q - - / - - - (Q4) - - - - - - - - - Q5 - - - - - - - - - - - - - - EE 1"
    },
    {
      "page_index": 340,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_056.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_056.png",
        "page_index": 340,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:22:15+07:00"
      },
      "raw_text": "CO1023- Counter and Register 56 SIP0 - The 74ALS164/74HC164 A 8 bit shift register B- 74ALS164 Each FF output is externally accessible CP- A and B inputs are combined in an AND gate for serial input. Shift occurs on NGT of the clock input. MR Q3Q4Q5Q6Q A B CD CD MR Qo Q1 Q2 Q4 Q5 Q6 Q7 Input pulse Qo Q1 Q2 number Q3 Q4 Q5 Q6 Q7 A 0 0 0 0 0 0 0 0 0 B X 0 0 0 0 74ALS164 0 O 0 2 0 0 0 0 O GP 3 0 0 0 0 0 4 0 0 0 Recycles MR 5 0 0 0 6 1 O 0 1 1 1 1 1 1 0 8 1 - 1 1 SE (a) Temporary state"
    },
    {
      "page_index": 341,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_057.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_057.png",
        "page_index": 341,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:22:18+07:00"
      },
      "raw_text": "CO1023- Counter and Register 57 Other Similar Devices 74194/ASL194/HC194 4 bit bi-directional universal shift register Performs shift left, shift right, parallel in and parallel out. 74373/ALS373/HC373/HCT373 8 bit PIPO with 8 D latches Tristate outputs 74374/ALS374/HC374 8 bit PIPO with 8 edge triggered D FFs, Tristate outputs 6E"
    },
    {
      "page_index": 342,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_058.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_058.png",
        "page_index": 342,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:22:21+07:00"
      },
      "raw_text": "CO1023- Counter and Register 58 Shift Register Counters Ring Counter Last FF shifts its value to first FF Uses D-type FFs (JK FFs can also be used) Must start with only one FF in the 1 state and all others in the 0 state 6E"
    },
    {
      "page_index": 343,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_059.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_059.png",
        "page_index": 343,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:22:29+07:00"
      },
      "raw_text": "CO1023- Counter and Register 59 Four-bit Ring Counter D Q3 D Q2 D Q1 D Q CLK CLK CLK >CLK CLOCK Q3 Q Q1 Qo JU (a) 2 3 4 5 6 8 CLOCK Q3 Q2 Q1 Qo (b) CLOCK Q3 Q2 Q1 Qo pulse 1000 O O 0 0 1 O 1 0 O O 2 O 0 3 1 0 4 0001 0100 1 O 0 5 O 0 1 0 6 0 1 7 0010 (c) (d) SE"
    },
    {
      "page_index": 344,
      "chapter_num": 7,
      "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_060.png",
      "metadata": {
        "doc_type": "slide",
        "course_id": "CO1023",
        "source_file": "/workspace/data/converted/CO1023_Digital_Systems/Chapter_7/slide_060.png",
        "page_index": 344,
        "language": "en",
        "ocr_engine": "PaddleOCR 3.2",
        "extractor_version": "1.0.0",
        "timestamp": "2025-10-30T17:22:37+07:00"
      },
      "raw_text": "C01023-Counter and Register 60 MOD-6 Johnson Counter D Q2 D Q D  Johnson counter CLK CLK CLK Q2 Q Qo CLOCK Also called a twisted ring counter (a) Same as ring counter but the inverted 2 3 4 5 6 7 output of the last FF  is connected to CLOCK input of the first FF Q2 Q1 Qo (b) CLOCK Q2 Q1 Qo pulse 000 0 0 0 0 1 1 0 2 001 3 100 1 0 4 0 0 5 0 O O 6 1 0 O 7 1 1 0 8 011 110 111 (c) (d) 6E"
    }
  ]
}