This index lists the information that forms a part of. or supplements this specification, and indicates the
authorized issues thereof.

Bell System Repair Specifications which have been covered in
BSRS Lists320 through328 prepared by the Indiana Publication Center.
It is the intent that BSRS Lists issued subsequent to List 328 are to
be considered as supplementary to this checking list until it is
reissued. It is the plan to reissue this checking list semiannually.

1.02 The "Issue" column of this checking list indicates the authorized
issue of BSRS Page 1 Indexes. Since BSRS's do not have an issue
number for the entire document due to the method of revision whereby
individual pages and drawings are reissued, the issue of the BSRS
Page 1 Index is used for reference and record purposes.

1.03 Changes and additions are indicated by asterisks (*) in the left-
hand margin.

SCCPE ANC PLAN FOR ISSUANCE CF BELL SYSTEM REPAIR SPECIFICATIONS
ALPHABETICAL INDEX - ALL DIVISIONS
CHECKIN!-, LIST

STATICN AND OUTSIDE PLANT APPARATUS AND EQUIPMENT - GENERAL REQUIREMENTS
CIRCUIT PACKS AND PRINTED WIRING BOARD ASSEMBLIES - GENERAL REQUIREMENTS
TELEPHONE SETS - GENERAL REQUIREMENTS

COIN COLLECTORS AND CCIN TELEPHONE SETS - GENERAL REQUIREMENTS
APPEARANCE STANDARDS - STATICN APPARATUS - GENERAL REQUIREMENTS
STATICN APPARATUS - APPLICATION CF CORROSION INHIBITOR
STATICN PLLSS -274 AND 233 TYPE - CORDING
TELEPHONE SETS - 592 TYPE - CONNECTIONS ANC CCRCING
MULTISLDT COIN COLLECTCRS - CONNECTIONS

HAND TELEPHONE SETS ANC TELEPHONE SETS - MODIFIED AND RAFIC RECOVERY
TELEPHONE SETS - 59? TYPE - RECOVERY REQUIREMENTS

MUL TI BUT TON K r Y TELEPHONE SETS - 500, i5C0, 25C0, ANC 35C0 SERIES - RECOVERY REQUIREMENTS
TELEPHONE SETS - 532, 533, 535, AND 536 TY PES
T EL C PHONE SETS, 5 54,555 , r 56,557 5 5B,ANC 559 TYPES

TELEPHONE SETS 6C0,1fcOC,260C AND 3600 SERIES (CALL CIKECTCRSl- RECOVERY REQUIREMENTS
TELc-PHCNE SETS - PRINCESS (R) TY FES - RECOVERY REQUIREMENTS

TELEPHONE CONSOLES, SELECTOR CONSOLES, 12-14 TYP.E APPARATUS UNITS ANC 600 SERIES TEL'PHUNE SETS ATTENDA
NT CONSOLES - RECOVERY REQUIREMENTS

5 BlA TELEPHONE S r T EASE G F-56659 G E-56660 TELEPHONE SET- RECOVERY REQUIREMENTS
TELEPHONE SETS-A NT I CUE-MCDIFICATICN ANC RECOVERY REQUIREMENTS
TELEPHONE C1NSCLES-14 AND 15 TYPFS-RECOVERY REQUIREMENTS
Tf'L = PHONE SETS-2671 TYFE- RECOVERY REQUIREMENTS

DIALS - 21 TYPE - RECOVERY RECUIREMENTS
CIALS 22-, 25-, 35ILCI-, AND 66-TYPE
DIALS-26.36.AND 67 TYPFS RFCCVERY REQUIREMENTS
EILTFRS - RADIO FREQUENCY SUPPRESSION TYPE
DIALS to, 7, 3, 9, 10, AND 11 TYPES
DIALS-10C8,1025,1035,1036 AND 1066 TYPE
DIALS - 51 TYPE
DIALS - 3 J AND 82 TYPE

AND C16Cli3 (SPECIAL NUMBER 228A) CCNNECTING BLOCKS - 18 TYPE
l RELAYS - 114, 124, 126, 174, AND 198 TYPES - RELAY COVERS IA ANC 2A

RELAYS - 2 9 0 TYPE
R rlAYS - ?99, 2 5 C» AND 293 TYPES
RFLAYS - 156 TYPE
RELAYS - GENERAL RECUIRFMFNTS
N1. 49 JACKS AND ASSOCIATFC JACK MOUNTING
NOS. 92 AND 292 JACKS AND ASSGCIATEC JACK MOUNTINGS

STEP-BY-STEP SYSTEMS WIRFD ASSEMBLIES WITH 197 ANC 198 TYPE SWITCHES
STEP-BY-STEP SYSTEMS - SWITCH BANK MULTIPLE ASSEMBLES
PANEL SELECTOR COMMUTATORS
BRUSHES - 11, 12, 13 ANC 15 TYPES
TO 11 TYPE CLUTCHES
PANEL RACKS

C). AND JU CARRIER TELEPHONE - GFCUF RECEIVING AND R E PE A T t R-AMPL I F I ER UNITS
11 CARRIER TcLFPHONE-GPPUP CSCILLATCR UNIT

Cl AND C\ll CARRIER TELEPHONE - REPEATER CSCILLATCR ANC MISCELLANEOUS - OSCILLATOR UNITS
LX CARRIER AMPLIFIERS

CN CARRIER ( J 9 F 7 06) - RECFIVING AMPLIFIER AND CEMCCULATOR ANC TRANSMITTING AMPLIFIER ANC MODULATOR UNIT
S

ON /K CARRIER (J987C9) - RECEIVING AND TRANSMITTING AMPLIFIER UMTS
CN/K CA.RRI = R (J987C9) - ADJUSTABLE DEVIATION FCUALIZER UMTS
A 6 CHANNEL RANK EQUIP W FNT-J68853A MCCEM UNIT

SECONDARY GROUP AMPLIFIER AM) DISTRIBUTICN MOGUL F EC-50105-31 - CONSISTING OF 230A AMPLIFIER AND CISTRI

'•.-TYPE COUNTERS - 4A, 4B, 4C
2 c 4A SWITCH
H) CIRCUIT PACK
H 2 CIRCUIT PACK
25 3 A SWITCH
2 5 SWITCH

J 6 a 64 7 VOICE-FREQUENCY AMPLIFIERS
El, r2• AND E 3 TELEPHONE REPEATERS
TELEPHONE REPEATER ( J9 9 2 5 ? )

M’»350 3 TYPE N 2 CARRIER (J99272) - N 2 WM 1 WIDE-eAND MODEMS - TRANSMITTING AND RECEIVING UNITS

411.301 1 Hi DATA CARRIER TERMINAL UNIT (J7C.52AB AND J7C152BBI (PLUG INBOARDS ONLY! ANC POWER SUPPLY

41 1.302 1. 81 DATA CARRIER TERMINAL - CARRIER SUPPLY UNIT - (J7C152AA AND J7C1528A1 - (PLUG IN eCARCS CNLY1

411.443 , c JfcPR c 6AP-i,LIST 1,3,4 6 J6RB58AP-2 C-2C RECEIVING SUPERGROUP REGULATED AMPLIFIER -L-MULTIPLEX

411.445 1 F 452=4 THROUGH F 55257 SUPERGROUP DEMODULATOR NETWORKS ANC F 55256 THROUGH F 55?Hi SUPFRGROUP MCOLLATC

J6885EAC SUPERGROUP MODULATOR CR DEMODULATOR, CARRIER FILTER £ BANCPASS FILTER MODLLPS

J68818 - TONE IDENTIFICATION AND BALANCING UNIT - L2 CARRIER SYSTEM (PEARL) - INCLUDING 62 TYPE CSCILLA

ED-5C657-30 MAJOR CARRIER ALARM - MASTERGROUP MULTIPLEX
MASTERGROUP MULTIPLEX - ED-506C5-31 128 TO 512 KHZ MULTIPLIER ASSEMBLY
MASTERGROUP MULTIPLEX - EC-50605-32 1024 TO 4C56 KHZ MULTIPLIER ASSEMBLY
L4 C Afifi I £8-1 8 A MEMORY LMT
L4 CARRIER - ISA MEMORY LMT

L4 CARRIER - J68877AF-), LIST 1 THRU LIST 6 - TEST OSCILLATOR ANC LOGIC UNIT
L4 CARP. IER-J66877AG COMMAND RECEIVER

MASTERGROUP MULTIPLEX - FC-506C5-33 8152 TC 16384KHZ MULTIPLIER ANC ALARM ASSEMBLY
EC-5 C615-30 TRANSFER CONTROL CIRCUT - MASTERGROUP MULTIPLEX
EC-50622-31 OSCILLATOR ALARM CIRCUIT - MASTERGROUP MULTIPLEX

L~4 CARRIER-J66877AS-1.LIST l.LIST 2A G LIST 3 TEST CSCILATOR AND LOGIC UNIT
MASTERGROUP MULTIPLEX - EC-50621-30 PILOT GENERATOR ALARM AMPLIFIER
ED-5C62 2-30 PILOT ALARM SY STEM-MASTERGROUP MULTIPLEX
4A ECHO SUPPRESSOR - CIRCUIT BCARCS - (J68514!

L4 CAPRIcR-J6E877AB-2 LIST 7 REGULATING REPEATER
CATV EUUIPMENT-JERROLO ELECTRONICS CORP.-•STARL INF•

DATA SYSTEMS CENTRAL OFFICE - WLR4 AND WLR5 WICEeANC LOOP REPEATERS J70171AC, J70171RA AMPLIFIERS

DATA SYSTEMS CENTRAL OFFICE - WLR4 AND WLR5 WIDEBAND LOOP REPEATERS J70171AC GROUP PRFAMPLIFIEKS AND J7

DATA SYSTEMS CENTRAL OFFICE - WLR4 6 WLR5 W ICEPAND LCOP REPEATERS J7C171AG, LI GROUP CONTROL TESTS G J7
Ji 7 iAT, LI SUPER GRUUP CCNTRCL TESTS

DATA SYSTEMS CENTRAL OFFICE - WLR4 6 WLR5 WIDEBAND LCCP REPEATERS J7C171AR GROUP PILOT OSCILLATORS G J7
C171AL SUPER GRCLP PILOT CSCILLATCRS

DATA SYSTEMS CENTRAL OFFICE - WLR4 G WLR5 WICEeAND LCOP REPEATERS J7C171AJ-L1, L2 LOCAL POWER SELECTCRS

J7C171AK-LL. L2 RFMCTE PCWER SELECTORS J7C171AW- LCCAL FCWEP SELECTCRS ANC J7jl 7 ]AY- o EMCTC POWER «ELE

CATA SYSTEMS CENTRAL CFFICE - WLP4 6 WLR 5 WICEEANC LCCP REPEATERS J7C171AL ALARM
FWA.FWH, G FUA SIGNALING UNTTS-(J59335WA,J59335WB,G J9R335UA1

RYA ?6CC H7 TCNE SUPPLY AND TRANSFER CIRCUIT (J55335YA-1) - FYG CARRIER GROUP ALARM CONTROL CIRCUIT (J-

L4 CARR IER-J68E77AC-LIST 2 REGULATING REPEATER
L4 CARR IFR-J6EE77AN-LIST 2 REGULATING REPEATEP

L4 CARRIER - J6PF77AE, LIST 1, LIST 2 ANC LIST 2A MEMORY UNITS
L4 CARRIER - J6F 877AR, LIST 1 G LIST 2 MEMORY UMTS

14 CARRIER J6S877AB-2 LIST 0 REGULATING REPEATER
L4 CARRIER J60677AC-1 LIST 3 REGULATING REPEATER
L4 CAPRI£R-J6E€77AM-1»LI$T2-PEGULATING REPEATER
L4 CARRIER J66E77AN-1 LIST 3 REGILATING REPEATER
L4 CARRIER - 28A GATE
L4 CARRIER - 6 0 A CONTROL LMT

LAMP SOCKET MOUNTINGS - 136 TYPE, NO. 137B, 236 TYPE, 275 TYPE AND NCS. 278B, 281A, 283A, 290A AND 251A
LAMP SOCKETS - NOS. 12, 12B, 13, 41A, 43A, 47B, 45A, 50A, 51B, AND 53A
ELFCTRIC CLOCKS - NOS. 1A, le ANC 1C
CALCULAGRAPHS - MODEL 6
CALCULAGRAPHS - MODEL 3C
CALCLLAGRAPHS - KS-7765 - MCCEL 33

ALTOMATIC MESSAGE ACCOUNTING - REAOERS KS-13S35, LISTS L, 2, 3, 4, 5, 6 , AND 7
AMA TAPE REELS, BINS ANC RECEPTACLE

CONVERSION OF AMA PERFORATOR CABINET EQUIPPED - WITH OUTPUT TAPE BINS (ED-40028-011 TO CABINET EQUIPPED
WITH OUTPUT TAPE REELS (EC-40025-01 ANO EC-26301-11)

AC/OC DUPLEX MOTORS - KS-5C2C, KS-5021, ANC KS-5407 REPAIRED AC/OCDUPUEX MOTORS - KS-5440
FREOLENCY GENERAT0RS-1C7 TYPE
J072C2A, LIST 1 RECTIFIERS
J86738A, LIST 1 POWER SLPPLY UNITS

ENCLOSED LEAD-ACID TYPE STORAGE eATTERIES- KS5361, KS15577, KS15754 AND KS15886
8C7D TONE POWER PLANT - FLUG-IN UNITS - IJ86825C, 0, E, AND C-)

404A-G TONE GENERATORS - 1CA ANC 8 TONE MONITORS, ANC 174A INTERRUPTER
J86815C. C, E, F, G, AND H FLUG-IN UMTS
24-TYPF POWER UNIT
23A POWER UNIT

J67266F 2C-HZ INVERTER - FLUG-IN UMTS - (J87266F, G, ANC HI
158 TYPE REGULATOR
• 2 TYFE POWER LMT
39A POWER UNIT

J 8 729 7 A,3, ANC C - OC TC DC CONVERTER
JF72FPA-CC TO DC CONVERTER REGULATOR
RECT IF IER-J872 C5A.8
POWFR PLANTS-(J8t485)

POWER SUP’LY ANC RINGING AND TONE FOR PCCA FriX - J <E f: 3 5 A ANC B
1 C1 A ANC ICIB-FRfcOLENCY GENERATOR

I12A frequency gfneratcf
P 8 X SWITCHED ARCS - 5C5 ANF 5C6 TYPES
CORDLESS POX SWITCHBOARDS - 507 TYPE
PRX SYSTEMS - NO 5 5 8A PBX

PBX SWITCHBOARDS - COR r TYFE (INCLUCING PLATE FORMS I-GENERAL REQUI REPENTS
PBX SWITCHBOARDS - NO. 6G5A ANC 6C7 TYPFS
R 8 > 5YSTFYS - 6 C 8 A PBX
RwITCH FRAMES - 74C TYPF FPX
P IX SYSTEMS NC. 7 * 5 A P?X

S * ITCHING ,r CUlPRHNT - NC. 7C1A ANC 713A F8XS
PBX SYSTEMS NC, 7 5 8 A PCX
S*ITCHING EQUIPMENT, 7C1B ANC 711H PRXS
PBX SYSTEM NJ.757A PPX

?A AUTOMATIC CALL DISTRIBUTING SYSTEM - (EQUIPMENT CABINETS, CABLING AND CONSOLES
7 11 A PRX - Hv)TEL-MCTE L SERVICE

TFIEPK'Nf ANSWERING SYSTEM NC. 1A - (ECUIFMENT CABINETS, CABLING, ANC CONSOLES!

ATTENDANT CABINETS ISED WITH NC. 740A, 7406, AND 740C PBXS
SCLOERING COPPERS - KS-P74C ANC KS-14440

TEST OSCILLATCR-HEWLETT-PACKARD CCMPANY-MCCEL 65CA
RELAY TIMING TFST SET JS4713A

CONNECTOR, SELECTOR, ANC TRUNK TEST SET J34722B
PORTABLE AC RELAY AND SIGNALING TEST SET-J68602AJ Ll
PORTABLE TRUNK TEST SET-J54729A

MAGNFTIC LATCHING RELAY TIMING TEST SET - J54735A
ICOA.e C COMMUNICATION SET
RESISTORS - 18 AND 19 TYPES
KEY SPACES

OPERATOR CHAIRS IMETAL TYFE) - AND PURSE HOLDERS
SUPERVISOR CHAIRS (METAL TYPE) - ANC SUPPLY CABINETS
DIODES AND VARISTORS

COMMON SYSTEMS-LINE CONCENTRATOR N0.1A-REMCTE UMTS
TOUCH-TONE CALLING-RECEIVER CIRCUIT-J99266(TYFE A2)

J9512CB MF RECEIVING UNIT - H295-119, H295-12C ANC H295-121
PBX TOUCH-TONE CALLING-RECEI VtNG CIRCUIT-J58844A ANC J58844B
PB X SYSTEMS - SCLIC STATE CCNVERTER J58847AC
2A ANC 28 - LINE CCNCENTRATCR - CIRCUIT PACKS
ELECTRONIC DRAWER ASSEMBLIES - E0-71291-10, G1 THROUGH G13
AE1, AE2, AE3 ANC AE4 CIRCUIT PACKS - (3A CCMMUNICATICN SYSTEM)

* 421.001 11 AGP TYPE CIRCUIT PACKS G NC.l ESS LINES G TRUNKS-CENERAL REQUIREMENTS G INDEX

421.C 66 1 NC.l ESS HIGH CURRENT PLLSER 6 PATH CHECK CIRCUIT - ELECTRONIC FERREfcC PULSER

4 2 1 .00* 4 \T). 101 ELECTRONIC SWITCHING SYSTEMS - HETERCCFNCUS FULSt-TESTEC CIRCUIT PACKAGES

h 2 , .OOA 7 NO. 10! ELECTRONIC SWITCHING SYSTEM - OSCILLATOR ANC TONE CENERATQR CIRCUIT PACKAGES

4 2 3 • C C G 2 N). 1C! ELECTRON 1C SWITCHING SYSTEM - MCNCFULSEP AND TIMFR C IF. CU ITPACK AGE S

iil.J'J l RL-CTRONIC SWITCHING SYSTFMS - NC. 101 - LCGIC Tf.STCr S-TYPE CIRCUIT PACKS

h 2 7 • Ill 1 ELECTRONIC SWITCHING SYSTEM - NC. 101 - S-TYPE CIRCUIT PACKS - OSCILLATORS AND TON" GE N>" R A TCP S

4?j.on 1 ELECTRONIC SWITCHING SYSTFMS - NC. 101 - S-TYPE CIRCUIT PACKS - AMPLIFIERS AND SWITCHES

423.104 1 SCOA PBX-CIRCLIT PACKS AC1C.AC13 C AC51.REC-ISTER CIRCUIT FOR DIAL PULSING 6 TOUCH-TONE CALLING

423.105 2 SCOA PBX - CIRCUIT PACKS AC23 AND AC59 - CNE-WAY OUTGOING CENTRAL OFFICE TRUNK CIRCUIT

423.106 ? SCOA PBX CIRCUIT PACKS AC20 AC22. AC52 AC58, AC63 AC66 CNE WAY INCOMING OR TWO WAY CENTRAL OFFICE

423.111 1 SOOA PBX - CIRCUIT PACK ADI - FUSE, ALARM, EMERGENCY TRANSFER AND TEST CIRCUIT

423.112 1 SCOA PBX - CIRCUIT PACKS AC31, AC32 AND AC33 - ATTENDANT CONTROLLED CONFERENCE CIRCUIT

4 3 2.012 1 ELECTRON 1C SWITCHING SYSTEMS - NC. 101 - S - TYPE CIRCUIT PACKS -NONCPULSERS AND TIMERS

KS-16378 TELEPHCNE ANSWERING SET ANC ACCESSORIES
ANNOUNCEMENT SETS KS-16765 ,LIST 1 AND LIST 2
KS-16523 TELEPHCNE ANSWFRING SETS AND ACCESSORIES
KS-19245 TELEPHCNE ANSWERING SETS ANC ACCESSORIES
1A TELEPHCNE REPORTING SET
CONTROL LMT 62A

K$-6846»KS-81C8»KS-81C9 ANC KS-8110 eUZZERS, 4 AND 7 TYPES EXCEPT 7G AND KS-1378? ANC 7 TYPE BELLS
EU7/FRS -0 TYPE

TRANSFORMER RELAY SFTS KS-7338, ANC KS-8233 AND RELAY SETS KS-16626 AND KS-16763
CODE SFN0IN3 STATIONS AND TRANSFORMER UNIT - KS-14468
SIGNAL 5 - KS-16 3C1

K S-19120 SCHCCL-IC-HCME SETS
LOUDSPEAKER SETS -ICO TYPE
AMPLIFIER - KS-16754 LISTS 1,2,3 AND 4
LOUDSPEAKER SEIS-lC6A , B ,C , 0 , E , F
LOUDSPEAKER SET-137 TYPE

TRANSFORMERS - KS-15675, KS-16184, KS-16368, KS-16886, 2C12 ANC 2075 TYPES
TRAN«FGRMERS-3S3 TYPE
LCUOSPFAKERS-759A ANC 759P TYPES
LOUDSPEAKERS - 76CA TYPE

CONNECTING BLOCKS - 66 TYPE - 72ei-50 TYPE & 1A1 MATRIX BLOCK
AMPLIFIER - KS-15220 TYPE
AMPLIFIER - KS' 15 2211 LIST 1

STAPLERS - HELLER CCNVEPTEC MODEL T ANC MODEL T2
B AUTOMATIC DRILL
STAPLER-HELLER MODEL TM

FLASHLIGHTS, HEAD LAMPS, SPOTLIGHTS, ELECTRIC HAND LANTERNS, AND DUAL BATTERY LIGHTS

TELETYPEWRITER COMPONENTS-GENEPAL REQUIREMENTS
TELETYPEWRITER MOTORS, MOTOR UNITS, AND GOVERNORS
TELETYPEWRITER RECTIFIERS

714 TYPE REPERFORATOR TRANSMITTER UNITS 114 TYPE REPERFORATOR TRANSMITTER UNITS 114 TYPE REPERFGRA

NCN-TYPING S TYPING PERFORATOR £ REPERFORAT OR,RECEIVING SELECTOR fiTAPE TYPING UNITS - 28 TYPE

TYPING UNIT, SUB-BASE 6 DISTRIBUTOR 6 ANSWER-PACK MECHANISMS - ASSOCIATED WITH 33 TYPE TELETYPEWRITER-S
ETS

NCN-TYPING AND TYPING REPERFCRATCR, RECEIVING SELECTOR AND TAPE TYPING UNITS - 35 TYPE

SELECTCR MAGNET DRIVERS - TF182630 AND TP1S3440
LOUDSPEAKER AMPLIFIER - TP18275C
CALL CCNTRCL LMTS - 33 £ 35 TYPES

CATASPEEC - 1A, 2A AND 5C SENDER CABINETS - IB ANC 5B RECEIVER CABINETS AND 5A-APPAHATUS BOX ASSEMBLY (
TP196C22 )

HIGH SPEED WlRF SPRING PEACERS CXI ,CX2 ,CX3 ,CX4,0X800,CX8C1 £ DX802
EDGE PUNCHED CARC REACEP UMTS 35 TYPE
TYPING UNIT - 37 TYPE

37 TYPF TELETYPEWRITER - KEYBOARC ANC BASE NOT E9 EARLY UNIT YK80C WAS DROPPED AND NEW UNITS ADDED
NCN TYPING ANC TYPING REPERFCRATCR UNITS - 37 TYPE
ELFCTRICAU SERVICE UMTS - 37 TYPE

456.7C7 2 TPl529C3 AND TP15478C MODIFICATION KITS TC FRCVIOE HORIZONTAL TABULATION AND TRANSMITTER OISTRIBL

456.7CB 3 TP154760 THROUGH TP15477C MODIFICATION KITS TC PPCVICE VERTICAL TABULATION ANO TRANSMITTER-DISTRIBUTOR

456.7C9 1 TP17e3l6, TP178344, TP178345 ANC TP178346 MCCIFICATICN KITS TC PROVICE ANSWER BACK ANC MCTCR CONTRCL

456.710 1 1P 152324 ANC TP154147 MCDIFICATICN KITS TC FPCVICE LCCAL PAPER FEEC CUT MCTOR START CN 26 TELETYPE

456.713 1 TP161815 MODIFICATION KIT LSED FOR MOUNTING CN AUXILIARY TYPING REPERFORATOR

456.716 1 MODIFICATION KITS LSED TO CONVERT 28 TYPING UMTS FROM FPIcflON FEED TO SPROCKET FEED ANC FROM SPROCKET

456.718 1 TP173443 MODIFICATION KIT - TO PROVIDE REMOTE CONTROL - NON-INTERFERRING LETTERS FEED-OUT - 28 TYPING R

456.719 1 TP16241 ANO TP163359 VARIABLE SPEEC GEAR SHIFT MCCIFICATION KIT 28 TELETYPEWRITER BASE (KSR ANC RC)

456.721 1 TP-164564 MODIFICATION KIT - TC CONVERT FROM CHADLESS - TC FLLLY PERFORATED TAPE - 28 REPERFORATOR

456.722 1 TP16249Q MULTIPLE WIRE CLTPUT - MCCIFICATICN KIT - TRANSMITTER DISTRIBUTOR UNIT - 28 TYPE

456.725 l TP1736ei FIVE-LEVEL PARALLEL - CCCE READING CONTACTS - MODIFICATION KIT - MODEL 28 TYPING UNIT

TP174216 MOO IFICATICN KIT - TO ECUIP MARK 11 KEYBOARD - WITH ANSWER-EACK - MODEL 28 KEY80ARD
TP175724 MODIFICATION KIT - TC PROVIDE TWO-CCLCR PRINTING CN MOOEl 28 TYPING UNIT

TP174235 AND TP178834 MCOIFICATICN KIT - TC CONVERT CHADLESS TO FULLY PERFORATED TAPE - MCOEL 28 TYPING
REPCRATOR

TP 333672 MOUNTING FRAMF ANC • STLNTRCNIC• (SA120AG1 CATA TERMINAL- ACCESSORY ASSEMBLY
STUN TRONIC S A113 CATA TERMINAL ACCESSCRY PARITY ERKCP CETECTCR

STUNTRONIC SA120 DATA TERMINAL ACCESSOR IES,PAR ITY ERROR OETECTORS ANC PARITY ERROR INSERTORS
J70112 A CHANNEL TERMINALS-43A1 (CARRIED TELEGRAPH ECU IPMENT)

NETWORK-453 6 454 TYPES-(LSED WITH 43A1 CARRIER TELEGRAPH TERMINAL EGUIPMENT1
144 TYPE COUPLING UNITS AND 56A1 LCCP REPEATERS
43B1 VOICE FRECLENCY - CARRIER CATA SYSTEM

ASSEMBLED TELETYPEWRITER STATIONS M28 ECUIPPEC WITH/WITHCUT SUB SET OF DATA SET FOR PRIVATE LINE SERVI
CE

15-ANC 15-TYPE ASSFMBLEC STATIONS - 60-WCRC-PER-MINUTE TWX
ASSEMBLED TTY STATIONS - 33-TYPE

TELEGRAPH SYSTEMS - 83B3 SELECTIVE CALLING SYSTEM - ASSEMBLEC 28TYPE OUTLYING STATIONS

TELEGRAPH SYSTEMS - P3B3 SELECTIVE CALLING SYSTEM - ASSEMBLEC 28ASR CONTRCL STATIONS

3A1, ANC FBI CATA SELECTIVE CALLING RC ST AT I CN (35EE, 35BF1
CATASPEEC-COMPLETE STATION TYPE 4

ASSEMBLED TTY STATICNS M35 TTY SETS ECUIPPEC WITH/WITHCUT SUBSETS CR CATA SETS FOR PRIVATE LINE
SERVICE

CATASPEEC(R)MAGNETIC TAPE TERMINALS STANC ALCNE CR USED WITH A LOW SPEED ADJUNCT

CATA LINE CONCENTRATOR SYSTEM - CATA-PHCNE - PRIVATE LINF - El A ANC CIRECT NEUTRAL INTERFACE TERMINAL S
T ATICNS - M 3 3 £ M35 SElF-CCNTA INEC LCGIC SETS
CCMMLNICATIONS DISPLAY - TERMINAL
CLUSTER CCNTRCLLER - TERMINAL

TELEPHONE WIRING, BCCTHS AND SIMILAR MOUNTING ARRANGEMENTS
SHELF - 20 TYPE
MOUNTING - KS-167C5

KS-19425 ANO KS-19580 - TELEPHONE BOOTHS ANC ACCESSORIES
COIN RECEPTACLES AND CCIN RECEPTACLE COVERS

457.220 2 COIN COLLECTORS -MULTISLOT TYPES - CONVERSIONS TO PULL BUCKET RETURN CHUTE

457.223 9 MULTISLOT COIN COLLECTORS - HANOSET TYPES - CCNVERSICNS FOR USE INNETWORK CIRCUIT

457. 220 4 CCIN CCLLECTORS,MULT ISLCT TYPES, CONVERSION TO SLOW RELEASE CCIN RELAYS

472.012 3 55A RADIO RECEIVER AND ACCESSORIES (8 TYPE BATTERY CASE, 32 TYPE RECTIFIER AND 215 TYPE SELECTORS)

473.014 2 PORTABLE RAOIC - LCW PCWER TRANSMITTER-RECEIVER - HALL I CRAFT ER LITTLEFONE HT-22 TYPE

473.015 1 PORTABLE RADIO-LCW-POWER TRANSM ITTER-RECEIVER-INCUSTRIAL RADIO COMPANY(PAK-FONE)

1 M J MOBILE RADIC TELEPt-CNE SYSTEM - RACIO TRANSM ITTER-RECEIVER - KS-1S6J9 (MOTOROLA)

2 OSCILLATORS - HEWLETT-PACKARD COMPANY-MODELS 200C, 23JCD, ANC 200H
4 2iA TRANSMISSION MEASURING SET - (J94021A)

4 VIDEO MONITORS KS-5799,LI S7S 1, 2, AND 3 (7-INCH) - KS-15654, LISTS 1 ANC 2 (12-INCH)
4 2M REPEATER SWITCHING SET (J940J2M)

MOTOFCl A P-81CC 1EST SET
PULSING TEST SET - J34717A
MERCURY RELAY TEST SET - J54725A
CCNTRCL SET - J64717

FREQUENCY AND MODULATION METERS - GENERAL ELECTRIC 4ST-13A ANO 4ST13A-WE
1 AH TUEE TEST SET - (J640C1AH)

3 7B TRANSMISSION MEASURING S ET-(J64037BI
COLD CATHODE TUBE TEST SETS - J24754A ANC J94731A
AUXILIARY TEST PANEL ANC TELEPHONE SET - J68649C
SELECTOR TEST SET - JS47C6A

VACUUM TLBE VOLTMETER - MEASUREMENTS CORPORATION - MODEL 62
VACUUM TUBE VOLTMETERS - HEWLETT-PACKARD COMPANY - MODELS 4iOA,ANC41CB
REPEATFR ACTIVITY TEST SET - J68825A
TEST SET FOR TIMING TESTS - J24753A

53A MOBILE OSCILLATOR, J64C53A, LISTS 1, 2 ANC 3 (CCNSISTING OF THERMOCOUPLE PANEL) J86221A RECTIFIER,

VOLTMETERS - WESTON TYFE 531
PER CENT BREAK METER - KS-7361
THFRMISTER CCNTRCL SETS - J6E839A ANC J68839e
ANALYZER - WESTON MODEL 779

1U AMPLIFIER - RECTIFIER - IJ640Q1U) - (MODIFIED FOR USE IN 406 MOBILE TRANSMISSION MEASLRING CIRCUIT)
32A TRANSMISSION MEASURING SET (X66C65A ANC J64032A)

SIGNAL GENERATORS - FERRIS INSTRUMENT COMPANY - MCCELS 220 ANC 22CS
FM MODULATION MONITORS - DOOLITTLE RADIO FC-9 ANC FC-9B ANC JAMES KNIGHTS FD-12

1 OSCILLOSCOPE - HEWLETT-PACKARD - MODEL 130A
1 5L SERVICING CENTER TEST SET - (JSe7C5U)
l ECHO SUPPRESSOR TEST SET - J68605M

1 TRANSMISSION MEASURING SYSTEM - J64047A - (J64047BI SENDING UNIT AND J64047C RECEIVING UNIT

3 MODELS 4 ANC 4A TRANSMISSION TEST SETS (NORTHEAST ELECTRONIC CORPORATION!

1C 5C2-SERIES CATA TEST SET (J79902A ANC 81 - X-67945MB DISTORTION MEASURING AND ERRCR CETECTCR SET

3 36A VICEO VISUAL GAIN AND DELAY CISTCRTICN MEASURING SET- (J64C36AA TRAN EMITTER!-!J64C36AB

3 36R VIDEO VISUAL GAIN AND DELAY DISTORTION MEASURING SET - (J64036eA TRANSMITTER ) - (J64C368B RECEIVER)

J-693920-1-ATTENUATCR,JACK,AND MARKER OSCILLATOR PANEL
J-633S2E-1-SWEEP CCNTRCL PANEL
J-68392F-1-IF DETECTOR UNIT
SIGNAL GEN6RATCR-KS-2C146
DISTORTION CETECTOR-KS-20147

SLA,8, 6 E AUTOMATIC TRANSMISSION MEASURING SYSTEM - J94051A,8,C,E - CIRCUIT PACKS
26A MICE3AN0 GAIN AND DELAY SET (J94026A!

23 SIGNALING TEST SET-!J64730B> 6 PULSE REPEAING ADAPTER(J64730CI
KS-19763 TV hAVEFCRM CSCILLCSCCPE
KS-1963 3-TV PICTURE MCMTCR
KS-205C1 RETURN LOSS MEASURING SET

CATA SETS 601A, 601A1, 6C1A2 AND CATA SETS 6018, 60 iei, ANO 601B2
CATA SET 202 7YPE-TRANSMITTER-RECEIVER-!J1C202A ANC J1C2C2B)

CATA SET 201 TYPE-TRANSMITTER-RECEIVER
J70148 - PLUG-1N ELECTRONIC UMTS
CATA SETS - 1C1 TYPE - 1J1C1C1I
CATA SET 4C2A TYPE TRANSMITTERS

DATA SET 3318 - TRANSMITTER - RECEIVER - (J1C301BI
CATA SET 1038 - (J1D103B) ANC J87239A, 8 RECTIFIER
CATA AUXILIARY SETS 801C1, EC1C2-At TCM AT I C CALLING UMTS
CATA SETS 6 32A (ALL LISTI AND 602Al-TRANSMITTER-RECE IVER

CATA AimiARY S ET S-804 A1,80 4A 2,804 A3,804 A4,804 A 5,8 04 A6,804 A 7 C 804AE
DATA SETS 105A TYPE, CIRCUIT PACKS ANC RECTIFIER (JE7240B, LIST 1>

CATA SET 1C3F TYPE ANC JE7239A ANC e RECTIFIERS
CATA SET 202C/202D TRANSMITTER RECEIVER
CATA SET-TYPE 4020

DIGITAL CATA TRANSMITTER JIGCGCBG ANC DIGITAL CATA RECEIVER JIGOOOeG

Bell System Repair Specifications - Checking List


1.01 This section is reissued to define the circuit
pack systems now included in the circuit pack

pool in the Washington-Idaho Area (1.03a) and to
make a minor revision in the wording of paragraph
4.05. Changes are indicated by arrows.

1.02 The SPCS circuit pack pools replace defective
circuit packs for the No. 101 Electronic

Switching System (ESS), No. 1 ESS, No. 2 ESS,
Traffic Service Position System (TSPS), Electronic
Translator System (ETS), and solid state Traffic
measuring devices, eg, Alston and PMC.

1.03 Defective packs are replaced with spares from
the SPCS circuit pack pools.

1.04 Twenty-four hour service is provided. The
method of shipment to the field is determined
by the urgency of the requirement.

2.01 Replacement packs are ordered from the pool
by calling the above numbers at any time.

2.03 The central office, after receiving the
replacement pack, does the following:

(a) Completes the P-7991, provides the
teletypewriter diagnostic printout if
available. Places the completed form and
printout in the shipping container with
the defective circuit pack.

(b) Attaches the address label to the carton
and ships the items to the pool, reusing
the carton and packing materials.

BCb q This material is prepared for Pacific Northwest Bell Tel. Co. purposes and is in no sense a publication. Neither the material nor any
•J" portion thereof is to be reproduced in any form by others without the written permission of the Pacific Northwest Bell Tel. Co.

2.04 The pool receives and forwards the defective
pack to Western Electric (WE) with Form

2.05 Repaired packs and no-trouble-found packs
returned from Western Electric may be

(b) Packs are returned to the original office
and tested in the same equipment
location in which they originally failed. If
the packs do not fail, they are left in place
and the replacement packs are returned
to shelf stock in the pool.

3.01 Obtain replacement packs as soon as possible
to prevent accumulation of defective units.

3.02 Make sure the completed Form P-7991 and
teletypewriter diagnostic are returned with the

3.03 Make sure the pack is actually defective before
requesting a replacement.

3.04 Make sure defective packs are returned to the
pool as soon as replacements arrive.

4.01 Ship packs (same pack issue, if appropriate) to
the field as soon as they are requested.

4.02 Verify accuracy of paper work accompanying
shipments to and from the field.

4.05 Have defective units repaired, or dispose of
them as obsolete or unrepairable items (eg,

4.07 Maintain an adequate spare circuit pack stock
to provide the field with any pack that may be

4.08 Be responsible for preparation of all paper
forms involving pooled items:

4.09 Supply Plant field forces with enough packing
and shipping materials to insure adequate

Stored Program Control Systems (SPCS) / Circuit Pack Pool


1. WHEN CHANGES ARE MADE IN THIS DRAWING.
ONLY THOSE SHUTS AFFECTED WILL BE
REISSUED.

2. THIS SHEET INDEX WILL BE REISSUED AND
BROUGHT UP TO DATE EACH TIME ANY SHEET
OF THE DRAWING IS REISSUED. OR A NEW
SHEET IS ADDED.

3. THE ISSUE NUMBER ASSIGNED TO A
CHANGED OR NEW SHEET WILL BE THE
SAME ISSUE NUMBER AS THAT OF THE

CIRCUIT PACK SCHEMATIC
EQUIPMENT DRAWING
KS-21447 MINIRECORDER CKT
DC-DC CBNVERTER (J87421A)

* - SCHEMATICS OF ALL FA,FB,FC AND JK-COOED
CIRCUIT PACKS USED IN THIS CIRCUIT ARE
SHOW ON DRMINGS NUMBERED WITH A CPS
PREFIX FOLLOWED BY THE CODE OF THE PACK,
e.«, CPS-JK10

NOTICE- NOT FOR USE OR DISCLOSURE OUTSIDE THE BELL
SYSTEM EXCEPT UNDER WRITTEN AGREEMENT.

REQUEST TO THE SP! TO TRANSMIT AN ERROR
START CODE IN THE CURRENT STATUS REPLY
TO THE CC. LOW ACTIVE

REOUEST TO BT TO GENERATE PARITY OVER
THE STATUS REPLY CURRENTLY RESIDING ON
THE COMMON PARALLEL BUS

COMMON PARALLEL BUS PARITY BIT (ODD)
OVER THE 8 HIGH-ORDER DATA BITS. LOW =
LOGICAL ONE

COMMON PARALLEL BUS PARITY BIT (ODD)
OVER THE S LOW-ORDER OATA BITS. LOW =
LOGICAL ONE

ADDRESS DEVICE TO RECEIVE THE DATA ON
THE COMMON PARALLEL BUS, ACTIVE LOW

ADDRESSED DEVICE TO SEND OATA TO THE SPI
ON THE COMMON PARALLEL BUS. ACTIVE LOW

ADDRESSED DEVICE REOUESTED TO GATE A
STATUS REPLY ON THC COMMON PARALLEL BUS.
ACTIVE LOW

A SYNCHRONIZING SIGNAL TO THE SPI WHICH
INDICATES ThAT A DEVICE HAS SENSED A
COMMAND ON THE PARALLEL BUS. ACTIVE LOW

A REGUEST TO THE SPI TO WAIT UNTIL THE
DEVICE HAS HAD TIME TO ACT UPON A
COMMAND BEFORE REMOVING THAT COMMAND
FROM THE COMMON PARALLEL BUS. ACTIVE LOW

INDICATES T"AT A DEVlCt HAS SENSED A
ACKNOWLEDGE INTERRUPT COMMAW. ACTIVE COMMAND ON THE P < RALLEL BUS. ACTIVE LOW
LOW

WAITO A REQUEST TO THE SPI TO WAIT UNTIL THE
SERIAL BUFFER BUS CARRY PULSE INDICATING DEVICE KAS HAD TIME TO ACT UPON A
THAT THE ON-LINE (ACTIVE) DATA BUFFER CCHHAKu BEFCf . REMOVING THAT COMMAND
HAS BEEN EITHER FILLED OR CIFT.cD. FROM THE COMMON PARALLEL BUS. ACTIVE LOW
ACTIVE LOW

SERIAL BUFFER BUS 16 BIT CARRY PULSE
INDICATING THAT A 16-BIT WORD HaS BEEN
TRANSFERRED BETWEEN THE ON LINE DATA
BUFFER AND THE DEVICE CONNtCTED TO IT,
ACTIVE LOW

REOUEST TO THE SPI TO TRANSMIT AN ERROR
START CODE IN THE CURRENT STATUS REPLY
TO THE CC. ACTIVE LOW

COMMON PARALLEL BUS PARITY BIT (ODD)
OVER THE 8 HIGH-ORDER DATA BITS. LOW =
LOGICAL ONE

COMMON PARALLEL BUS PARITY BIT (ODD)
OVER THE 8 LOW-ORDER DATA BITS. LOW =
LOGICAL ONE

ADDRESS DEVICE TO RECEIVE THE DATA ON
THE COMMON PARALLEL BUS AND INTERPRET
THEM AS A COMMAND. LOW ACTIVE

ADDRESSED DEVICE TO RECEIVE THE DATA ON
THE COMMON PARALLEL BUS. ACTIVE LOW

ADORESSED DEVICE TO SEND DATA TO THE SPI
ON COMMON PARALLEL BUS. ACTIVE LOW

ADDRESSED DEVICE REOUESTED TO GATE A
STATUS REPLY ON THE COMMON PARALLEL BUS,
ACTIVE LOW

SERIAL BUFFER BUS CARRY PULSE INDICATING
THAT THE ON-LINE (ACTIVE) DATA BUFFER
HAS BEEN EITHER FILLED OR EMPTIED,
ACTIVE LOW

SERIAL BUFFER 8US 16 BIT CARRY PULSE
INDICATING THAT A 16-BIT WORD HAS BEEN
TRANSFERRED BETWEEN THE ON-LINE DATA
BUFFER AND THE DEVICE CONNECTED TO IT,
ACTIVE LOW

SERIAILY SHIFT THE INTERMEDIATE TRANSFER
REGISTER ON THE TRAILING EDGE OF A
LOW-GOING PULSE

ENABLE DATA TRANSFER - GATE THE
INTERMEDIATE TRANSFER REGISTER ONTO THE
COMMON PARALLEL BUS. ACTIVE LOW

REQUEST TO THE SPI TO TRANSMIT AN ERROR
START CODE IN THE CURRENT STATUS REPLY
TO THE CC, LOW ACTIVE

COMMON PARALLEL BUS PARITY BIT (ODD)
OVER THE * LOW-ORDER DA A BITS. LOW =
LOGICAL ONE

16 BIT LARRY Pl'LSE INDICATING THAT A
16-BIT WORD HAS BEEN TRANSFERRED BETWEEN
THE OFF-LINE BUFFER AND THE INTERMEDIATE
TRANSFER REGISTER. ACTIVE HIGH

SERIAL DATA INPUT TO THE OFF-LINE BUFFER
FROM THE INTERhEDlATE TRANS-ER REGISTER,
LOW = LOGICAL 1

LOAD THE INTERMEDIATE TRANSFER REGISTER
fRDM THE COMMON PARALLEL Btfr ON A HIGH
TO LOW TRANSITION

LOAD OPERATION PARITY CHECK DELAY.
ACTIVE LO«. GUARANTEES THAT .. PARALLEL
PARITY ERROR IS REPORTED IN THE
FOLLOWING STATES REPLY

ENABLES THE LOADING OF THE PARALLEL
PARITY BITS INTO THE INTERMEDIATE
TRANSFER REGISTER FROM THE COMMON
PARALLEL BUS

CLOCK THE OFF-LINE SUFFER AND ITS
ASSOCIATED COUNTER ON A HIGH TO LOW
TRANSITION

CLOCK THE ON-LINE BUFFER AND ITS
ASSOCIATED COUNTER ON A LOW TO HIGH
TRANSITION

PARALLEL PARITY ERROR IN THE HIGH ORDER
BITS DUPING !TR REGISTRATION. ACTIVE LOW

PARALLEL PARITY ERROR IN THE LOW ORDER
BITS DURING 1TR REGISTRATION. ACTIVE LOW

ADDRESS DEVICE TO RECEIVE THE OATA ON
THE CGMMON PARALLEL BUS AND INTERPRET
THEM AS A COMMAND, LOW ACTIVE

ADDRESSED DEVICE TO RECEIVE THE DATA ON
THE COMMON PARALLEL BUS. .CT1VE LOW

SERIAL DATA INPUT TO INTERMEDIATE
TRANSFER REGISTER FROM THE OFF-LINE
BUFFER. LOU « LOGICAL 1

ADDRESSED DEVICE TO SEND DATA TO THE SPI
ON THE COMMOX PARALLEL BUS. ACTIVE LOW

ADDRESSED DEVICE REQUESTED TO GATE A
STATUS REPLY ON THE COMMON PARALLEL BUS.
ACTIVE LOW

A SYNCHRONIZING SIGNAL TO THE SPI WHICH
INDICATES THAT A DEVICE HAS SENSED A
COMMAND ON THE PARALLEL BUS. ACTIVE LOW

TOGGLE THE FIRST ELEMENT OF THE OFF-LINE
BUFFER SEQUENCER CHAIN ON A HIGH TO LOW
TRANSITION

INHIBIT PARALLEL PARITY CHECKING WHILE
UNLOADING THE INTERMEDIATE TRANSFER
REGISTER ONTO THE COMMON PARALLEL BUS.
ACTIVE LOW

A REOUEST TO THE SPI TO WAIT UNTIL THE
DEVICE HAS HAD TIME TO ACT UPON A
COMMAND BEFORE REMOVING THAT COMMAND
FROM THE COMMON PARALLEL BUS, ACTIVE LOW

TIMING DIAGRAMS F0R C0MM0I, PARALLEL BUS
CISHMUNICA T I0N AND 0FF - LINE SEQUENCING

START OF OFF-LINE SEQUENCE
(DASHED LINES INDICATE SEQUENCER
ACTION DURING LOAD OPERATION WITH PARALLEL PARITY ERROR)

ON-LINE SHIFTING
(DASHED LINES INDICATE ACTION LEAOING TO OR RESULTING FROM OVERFLOW)

THE BUFFER UNIT (BUF) IS A TEMPORARY SERIAL MEMORY DEVICE
FOR BUFFERING DATA TRANSFERS BEIVJEEN THE 3ACC AND SERIAL
DEVICES ON THE TUC COMMON PARALLEL BUS. MX IS ESSENTIALLY
BUILT AROUND TWO 1024-BIT SHIFT REGISTERS (B'JFO,BUF1 ) ,
WHICH ARE MAINTAINED IN OPPOSITE BUT SWITCHABLE ON-LINE/
OFF-LI N£~STATES. AN ON-LINE BUFFER IS THST SHIFT REGISTER
WHICH IS CONNECTED TO THE SERIAL 3"FFER BUS PRESENTLY SERV-
INfi THE CARTRIDGF TAPE TRANSPORT CONTROLLEP 'CTTC). AN OFF-
LrtJE BUFFER IS THAT SHIFT REGISTER WHICH IS CONNECTED IN-
DIRECTLY (THROUGH A SERIAL/PARALLEL CON«ERTER) TO THE COM-
MON PARALLEL BUS AND MAY BE SERVICED BY THE 5AC,:. THE DUAL

THE 0FF - LINE BUFFER AT ITS CONVENIENCE WHILE A CTTC/
ON-LINE BUFFER SERIAL CONVERSATION PtfOGPESSES AT THE CTTC
DATA RATE THE ON-LI NE /OFF-LINE BUFFEK STATUS SWITCHES AT
THE COMPLETION OF EACH 1024-BIT DATA TRANSFER ON THE SERIAL
BUS TRANSPARENTLY PROVIDING THE CTTC WITH A FRESH BUFFER
WHILE FLAGGING AN OFF-LINE BUFFER SERVICE REQUEST. BUF IN-
CLUDES FEATURES FOR TRANSFERRING VARIABLE LENGTh DATA BLOCKS
IN 16-BIT WORD INCREMENTS.

THE B'JF F'lNCTIONA! PARTITION DIRECTLY CORRESPONDS TO THE
PHYSICAL PARTITION OF THE CIRCUIT ONTO FOUR BOARDS, AS
SHOWN IN COMPOSITE DIAGRAM 1. BUF-A (J* 1 "} I NTERFACES Wl l"H
THE COMMON PARALLEL BUS AND PERFORMS B'JF ADCPfSS AND COM-
MAND DECODING. B'IF-C (JM2) PROVIDES THE SERIAL /PARALLEL
CONVERSION CAPABILITY NECESSARr TO TRANSFER DATA BETWEEN THE
COMMON PARALLEL BUS AND THE 1024-RIT SHIFT REGISTERS LO-
CATED ON BUF-C (JK13). BUF-C ALSO INCLUDES PARITY CHECKING
AND GENERATION CIRCUITS. BUF-B (JK1 1 ) PERFORMS THE SE-
QUENCING INVOLVED IN STEERING DATA THROUGH THE BUFFER.

BUF RESlOES AS A PERIPHERAL DEVICE ON 'HE COW.1N KARALLEl
BUS TOR WHICH THE COMMUNICATIONS PROTOCOL HAS Bt"-'N DESCRlUfcO
IN FS 1 AND FS 2. BUF IS ASSIGNED DEVICE CODE 15. THF AP-
PEARANCE OF THIS DEVICE CODE ON THE SIX LOW-ORDER BUS IK-
FORMATION LEADS, ACCOMPANYING AN ACTIVE X BUS CONTROL LEAD.
AODRESSES LIF AND ENABlFS T!€ DECODING CI COMMAND INFORK-
TION ON TKF TEN HIGH-ORDER BUS INFORMATION LEADS. ONCE
SELECTED Bl'F LATCHES INTO AN ADDRESSED S'"ATE, TURN INC 1 1-
SELF ON fo FATHER PARRLEL b'JS COMMUNICATION. BUT IS DE-
SELECTED UPON THE RECrPTION OF AN RC SIGNAL ACCOMPANIED BY
OTHtR THAN A tj DEVICE CODE.

CODED COMMAND INFORMATION IS BROUGHT INTO THE COMMAND DE-
CODER ON THE THREE HIGitST ORDER BUS INFORMATION LEADS.
THE DECODER RESPONDS BY DRIVING CONTROL CIRCUITS WHICH Pl?-
- FORM OR INITIATE THE ACTION SPECIFIED BY THE CO^E. THE
FIGHT *-BIT CODES FOLLOW:

CLEARS THE BR (BUFFER READY) FLAG, INDICATING
THt 3ACC HAS COMPLETED SERVICING THE OFF-LINE
BUFFER. (THE BR IS RAISED TO REQUEST 5ACC SER-
VICING OF THE OFF-LINE BUFFER.)

INITIATES AN ON-LINE BUFFER FILL OPERATION. A
FILL OPERATION CAUSES THE DATA QUEUE IN THE ON-
LINE BUFFER TO BE STEPPED TO THAT BUFFER'S OUT-
PUT IF NOT ALREADY THERE.

THE STATE REGISTER B1I KStGmtlCSS FOLLOW. THE FIRST
THREE A^E "JSFI TC S£l£" CUFFcREM OFF-LINE BUFFER OPERA-

STIFF . A ST»JFF OPERATION CAUSES TtC DATA QUEUE
SN THt 5F-L'« B.FFER TO BE STEPPED TO THAT
BUTTER'S OUTPUT IF !£,T ALREADY THERE.

THE IOTEWCMITE TWUBTES REGISTER (ITR) PERFORMS
SERIAL '='-RALLEL CONFUSION IN AL t DATA TRANSFERS BETWEEN
THt OFF-LINE KFFE8 MB TIC JACC. IN A LOAD OPERATION,
THE TT R ACCEPTS VA'S. A?«AR!»C ON THE 16-PARALLEL BUS
INFORMATION LEADS. BE BUS PARITY BITS ARC LOADED INTO
AN AUXILIA*' 2-B' I AGISTER. THE PARALLEL LOADING OF

TKX*LEi" RTM (NOTE TVT BUF WJST BE ADDRESSED). PARITY
rPE£S WJiGlfiG Ot. THE ITR CCTRTS patch THE PARALLEL DATA
PARITY Wt» Tt£ S£3ISTETS) PARITY STS TO CHECK FCR BUS
PARITY BCORS. BHCMKS THE OCCURENCE OF A PARALLEL
PARITY ERSCw THE ITR ENTERS A SERIAL SHIFT MODE AND THE
16 O-'TA 3!T3'fc'>; 3UXX2 ll.TO T€ OFF-LINE BUFFER UNDER
CONTROL" OF THE S£2.3£ER ON SLF-e. A COUNTER
ASSOCIAT'D WITH T>€ C-F-Li'.E BUFFER SIGNALS THE SEOUENCER
WHEN "!'. = ITS HME F3* T5AKSFFRRE0. A DETECTED PARALLEL
PARITY ERROR WILL ISSHSSiT SERIAL SHIFTING OF THE ITR.

TH r err- i;.e buffer hjtc t>£ its (khich is in a serial
shift •*:-:?;. the M&m trees se&erate odd parity over

Th" utC-~*'iD LOW ^TtS OF WE IATA WORD. "HE DATA _ ANO
PARITY *-£ GATED KTt I»€ RHtALLEi BL5 BY BUS CONTROL
SIGNAL 5Kv

sEOuENCiv;, cal-sfs rE=-:ES tc E£ shifted into the off-
line Et'TEF TO ?*? OCT A BUFFER CONTAINING LESS THAN
1C24 DATA SITS.

THE ON-LINE BL'FFEs; fW?i Vi OAT* PORT OF A SERIAL BUF-
FT! BL- WICM PRESEVTLY iERVES OBLT THE CTTC. THE SERI-
AL BUFFER BUS l«XUDES SEVERAL CONTROL AND STATUS LEADS
VWICH A 'CW THF CTTC TC tOiVC. THE MOVEMENT OF DATA INTO
AMD OUT CF THE 0V-U3L" a=-FES W1THCLT INTERFERING
BUF PF'-LINE CPE?JtT10 , i <L OFt EVE*. PECLHRING BUF TO BE AD-
DRESSED IN PARTIS-'LAF. THE CTTC-DRIVBJ BUFFER SHIFT
PULSE CCKTRO" LFJC (5SW1 DIRECTLY CLOCKS THE ON-LINE
BUFFER. » DATA BIT APPEARING C*i THE SERIAL DATA INPUT
LEAD 1« CLOCKED 8' "" TME tWFFER BY BSHPC WHILE A DATA
HIT AT Tr£ BLIFFT T».:T IS PRESENTED ON THE SERIAL DATA
OUTPUT „U2. A CCL^TS ASSSCiRTEC WITH THE ON-LINE BUF-
FER PRC-VIDFS A HASIH? PLLSE (EA16CR0) ON THE SERIAL BUS
WHICH WO! GATES V* CCPRETIW. OF EACH 16-BIT ON-LINE
DATA TRANSFER. A t-^4_F.iT RARKS? R'LSE (BACRO) IS ALSO
AVAILABLE TO DEVICES C*. THE SERIAL BUFFER BUS.

A FILL OPERATION &X S£ IMTIAJE3 BY THE CTTC (VIA
SERIAL SuTEJr tfci iEJ£ tlllO) R) PAD CUT A BUFFER TO
WHICH ir€ CTTC MAS WMffTDHICT) LESS THAN 1024 BITS.
FIL^ CAN AL& 5E ISIT1ATETJ SY A 5ACC COWAND FOR HAIN-
TEKAN" PLBPCSES. !>■: EITTCS CASE, THE OM.INE BUFFER IS
ADVANC— ?/ THE ft- S€3jE>iCER L9.TIL BACRO IS DETECTED.
THE C*i-LINE bLIFFES «Y 55 RECIRCULATEC OF gNES PADOED
OUR INC A FILL 0?E«-Ti3i, 0EFB3IIIG ON THE STATE OF THE
SERIAL CiTA 1MR-T i&C

DATA AND CLOCK INFORMATION IS STEERED TO OR FROM THE
PRCPER BUFFER BY MULTiaEXER SWITCHING DIRECTLY CONTROLLED
BY THE STATE OF THE ACT F/F. BUFFER INITIALIZATION
FORCES ACT INTO STATE SHOWN IN FIGURE 1 (SHT B3GB) WITH BUF0 OFF
LINE AND BUF1 ON-LINE. COUNTER CNTO (ASSOCIATED WITH
BUFO) IS CONFIGURED TO THE OFF-LINE CLOCK ALONG WITH
BUFO WHILE CNT1 AND BUF1 ARE CONFIGURED TO THE ON-LINE
CLOCK SOURCE. TOGGLING ACT RESULTS IN A REVERSAL OF
THE ON-LINE/OFF-LINE STATUS OF BUFO.BUFI, AND THEIR
ASSOCIATED COUNTERS. SUBSEQUENT CHANGES IN THE STATE OF
THE ACT F/F YIELD SIMILAR BUrFER REVERSALS. THE BR aAG
IS SET BY THE ON-LUE BUFFER COUNTER BACRO SIGNAL AND
INDICATES THAT THE ON-LINE BUFFER HAS BEEN CLOCKED 1024
TIMES AND NOW REQUIRES SERVICING BY THE 5ACC. RAISING
THE BR FLAG NORMALL" ASSERTS THE PARALLEL BUS INTERRUPT
LEAD (INTPO) UNLESS STATE REGISTER BIT INTOFF IS SET.
RAISING THE BR FUG ALSO TOGGLES THE ACT F/F, SWITCHING
. THE BUFFERS. THE 3ACC MAY THEN SERVICE THE NEW OFF-LINE
BUFFER AND RETIRE THE BR FLAG UPON COMPLETION. IF THE
3ACC DOES NOT MANAGE TO RETIRE THE BR FLAG BEFORE CURRENT
ON-LINE BUFFER OPERATIONS ARE COMPLETE (INDICATED BY
BACRO), A BUFFER SWITCH WILL MOT OCCUR, THE BBFL F/F
(BUFFER OVERFLOW) IS SET, AND ALL SUBSEQUENT CLOCK SIG-
NALS TO THE ON-LINE BJFFER ARE CUT OFF. THE STRANDED
ON-LINE BUFFER MAY BE BROUGHT OFF-LINE BY A 3ACC COMMAND
TO SWITCH BUFFERS, TOGGLING ACT THROUGH THE COMMAND DE-
CODER. DATA IN THIS BUFFER MAY THEN BE RETRIEVED BY SUC-
CESSIVE UNLOAD OPERATIONS.

BUF STATUS, ACCOMPANIED BY A 13 DEVICE CODE, IS REPORTED
ON THE PARALLEL BUS IN RESPONSE TO A SST CONTROL SIGNAL.
THE STATUS BIT DESIGNATIONS FOLLOW:

THIS EXAMPLE. A SERIES OF LOAD OPERATIONS TRIGGERED BY
RD cgw-:a;;ds BEGINS, EACH RD MOVING A 1 6-BIT DATA WORD
TFROUGH THE ITR AND INTO BUFO. WHEN THE 64-WORD CAPACITY
OF BUFO IS REACHED (ASSUMING A DATA BLOCK GREATER THAN
64 WORDS FOR SIMPLICITY), BUFO IS SWITCHED ON-LINE AND
THE CTTC IS ALERTED THAT IT IS TO RECEIVE A DATA BLOCK-
LOAD OPERATIONS CONTINUE ON BUF1. WHEN &UF1 HAS BEEN
LOADED TC ITS 64-WORD CAPACITY, OFF-LINE BUFFER OPERA-
TlCiS ARE SUSPENDED AND BUF STATUS REQUESTS MUST BE
PERIODICALLY HADE TO CHECK THE STATE OF THE BR FLAG
SINCE THE INTERRUPT FACILITY IS INHIBITED.

THE CTTC BEGINS TO DEPLETE THE ON-LINF BUFFER. A STATUS
REPLY INDICATING THAT THE BR RAG HAS BEEN RAISED IMPLIES
A BUFFER SWITCH HAS OCCURRED AND OFF-LINE LOADING OPERA-
TIONS CAN CONTINUE. AS BUF COMPLETES THE LOADING OF AN
OFF-LINE BUFFER, THE BR RAG IS CLEARED. IT IS IMPORTANT
THAT THE OFF-LINE LOADING OF THE SECOND BUFFER BE CON-
RETE3 BEFORE THE FIRST BR FLAG IS RAISED; OTHERWISE. AN
OVERROU SITUATION OCCURS (A PREMATURE BUFFER SWITCH)
BUT MR DOESN'T GET SET.

FOR DATA BLOCKS WHICH ARE NOT MULTIRES 01 64 WORDS, THE
FINAL BUFFER IS PARTIALLY LOADED, THE COUNTER ASSOCIATED
WITH THAT OFF-LINE BUFFER IS CLEARED TO MARK THE Nll'^ER
OF DATA WORDS IN THE BUFFER, A STUFF OPERATION IS i
IT1ATED. AiiD THE BR FLAG IS CLEARED AT THE COMPLETIu: OF
THE STUFF.

AN EXA.MRE BUF COMMAND SEQUENCE FOR MOVING A BLOCK OF
DATA FROM THE CTTC TO THE 3ACC IS FLOWCHARTER IN
FIGURE 5. BUF SHOULD BE INITIALIZED AT THE START. AN
ACKNOWLEDGED BUF INTERRUPT INDICATES THAT THE BR HAS
BEEN RAISED AND BUF1 HAS JUST BEEN SWITCHED OFF-LINE
FOR SERVICING. THE UNLOAD BIT IS SET IN THE STATE
REGISTER WHICH ADVANCES THE FIRST DATA WORD INTO THE
ITR AN SO COMMAND WILL GATE THE ITR ONTO THE PARALlEL
BUS" AliO ADVANCE THE NEXT WORD INTO THE ITR. 64 SDCOM-
HANOS ARE REQUIRED TO MOVE A FULL BUFFER OF DATA TO THE
5AC- AFTER WHICH THE OFF-LINE COUNTER IS CLEARED. THE
BR RAG IS RETIRED AND THE 3ACC WAITS FOR THE NEXT IN-
TFPCTiPT NOTE THAT THE UNLOAD STATE MUST BE SET EACH
TIME" A BUFFER IS TO BE DUMPED TO THE 3ACC IN ORDER TO
GET THE FIRST WORD OF EACH BUFFER INTO THE ITR.

rur r-n- ""ST REQUEST A FILL OPERATION ON THE LAST ON-
i'l'NE'ajFFER IF THt BLOCK LENGTH IS NOT A MULTIPLE OF 64
WORDS.

COMPOSITE DIAGRAM 8 PR6VIDES A FUNCTIONAL REFERENCE,
ORAUIH& FOR TIMING DIAGRA-SS THAT FOLLOW, AND AS SUCH
IS NOT MEANT TO OFFER AN ACCURATE GATE LEVEL DESCRIP-
TION. THE BUF CPS DRAWINGS SHOULD BE REFERENCED FOR
GATE LEVEL RESOLUTION. A TIMING DIAGRAM MNEMONI- ENDING
IN OR 1 DIRECTLY CORRESPONDS TO A "WS'^AL CIRCUIT
LEAD WHOSE LOGIC POLARITY WILL BE CORRECTLY INDICATED ON
THE DIAGRAM-

BITS 5-0 CONTAIN THE 13 DEVICE CODE. BUF BUS TIMING
LOGIC USES PARALLEL BUS LEAD GPO TO REQUEST PARITY
GENERATION OVER THE STATUS WORD BY THE BUS TERMINATOR.

BUF SHOULD BE INITIALIZED INTO A KNOWN STATE VIA A TDC
SYSTEM INITIALIZATION SIGNAL ON PARALLEL BUS LEAD INITO
OR BY A BUF RESET COMMANO. THE LOAD BIT MUST THEN BE
SET IN THE STATE REGISTER TO ENABLE THE REGISTRATION OF
PARALLEL PARITY BITS. THE INTeFF BIT IS ALSO SET IK

, glF RECEIVES A COMMAND FRO-; THE 3ACC VIA THE RC SEQUENCE
&OM IN FIGURE 4 (SHT B5GC). THE 3UF DEVICE CODE AND
COMMAND INFORMATION APPEARS ON TH-: BUS BEFORE THE LEAD-
ING EOCE OF RCO, ALLOWING ATDRESS WO COMMAND DECODER
SET UP TIME. THE LEADING CDGE OF RCO WILL LATCH THE
UOR F/F AUO ENAffE Or;' CF THE EIG'-T CurfMAND DECODER
OUTPUTS, BUF RETURiiS SYNCO AND ErO ON THE BUS AT THIS
TIME TO VERIFY THAT A CONTROL SIGNAL HAS BEEN RECEIVED
AND TO CHECK FOR PROPER OPERATION OF THE ERO LEAD, RE-
SPECTIVELY. THE TRAIL IMG EDGE OF RCO ALLOWS SYIJCO TO
DROP OFF. EF.0 WILL ALSO DROP OFF AT THIS TIME UNLESS
yuc PTTR F/F (PARITY ERROR) HAS BE r N SET IN A PREVIOUS
RUF OPERATION. IN THIS CASE, ERO WILL REMAIN ACTIVE
UNTIL BUF IS RESET OR DESELECTED.

THE BUS INFORMATION WILL REMAIN STEADY FOR A PERIOD
BEYOND THE TRAILING EDGE OF RCO. THIS EDGE IS INDIRECT-
LY USED TO CLOCK LEADS INF09-12 INTO THE STATE REGISTER
IF SUCH AN OPERATION HAS BEEN SPECIFIED BY THE COMMAND
OFCODER. IF THE UNLOAD OR STUFF BIT IS TO BE SET IN THE
STATE REGISTER, THE COMMAND DECODER LOAD STATE REGISTER
OUTPUT PRODUCES WISE TG. SEO WHOSE TRAILING EDGE IS USED
TC TOGGLE THE FIRST ELEHB,T \U AN OFF-LINE SEQUENCE TIM-
ING CHAIN. A BUSY STATE IS ENTERED FOR THE DURATION CF
THE OFF-LINE SEQUENCE INITIATED.

BUF RECEIVES DATA FROM THE 3ACC VIA RD SEQUENCES, BUF
MIST BE ADDRESSED WITH THE STATE REGISTER LOAD BIT SET
PRIOR TO A VALID DATA TRANSFER FRO!-' 3ACC TO BUF. IF BUF
IS NOT ADDRESSED, CONTROL SIGNALS RO, SO, OR SST ARE IG-
NORED. IF BUF IS ADDRESSED BUT NOT IN THE LOAD STAU,
A 1-BIT BUFFERING REGISTER AT THE IfR SERIAL OUTPUT
(LDO) IS HELD CLEAR PREVENTING DATA SHIFTED OUT OF THE
ITR FROM REACHING THE OFF-LINE BUFFER. IN ADDITION TO
THE LOCK UP OF LDO, THE AJXILIARY 2-BIT PARITY REGISTER
ISALSOHLLD CLEAR, RESULTING IN A PARITY ERROR AS SOON
AS AN EVEN PARITY BYTE IS REGISTERED IN THE ITR.

THE LEADING EDGE OF RED CAUSES SYNCO TO BE RETURNED AND
TG.SEQ TO BE ASSERTED. THE TRAILING EDGE OF RDO REG-
ISTERS DATA ON THE PARALLEL BUS INTO THE ITR AMD ITS
ASSOCIATED PARITY REGISTER. SYNCO AND TG. SEQ DROP OFF
AND THE BUSY STA^ IS ENTERED FOR THE DURATION OF THE
LOAD SEQUENCE.

THE 3ACC RECEIVES DATA FROM BUF VIA SO SEQUENCES, BUF
MUST BE ADDRESSED WITH THE STATE REGISTER UNLOAD BIT SET
PRIOR TO A VnLID DATA TRANSFER. SETTING THE UNLOAO BIT
PRIMES THE ITR FOR THE FIRST SO.

THE LEAUlNG EDGE OF THE SDC CAUSES BUF TO ASSERT SYNCC
AND TG. SEQ. THE ITR IS GATED ONTO THF PARALLFL BUS FOR
THE DURATION OF SOO. THE TRAILING EDGE OT SDO REMOVES
THF ITR FROM THE BUS AND NEGATES SYNCO. THE BUSY STATE
IS ENTERED FOR the DURATION OF THE UNLOAD SEQUENCE.

THE 5ACC REQUESTS BUF STATUS VIA THE SST SEQUENCE ON
FIGURE 5. AN AWRESSED BUF RESPONDS TO THE ASSERTION
OF SSTO BY ACTIVATING SYNCC, WAITO, AND GPO AND BY GATIKG
STATUS INFORMATION ONTO THE BUS. LDPCKD DELAYS FURTHER
ACTION IN A SST WHICH FOLLOWS A RO UNTIL THE RESULTS OF
THE LOAD OPERATION PARITY CHECK CAN BE REPORTED. LDPCKD
IS ONLY ACTIVE IN LOAD OPERATIONS. WHEN RELEASED FRCf.
THE DELAY, A 2-STAGE TIMING CHAIN IN THE BUF SST CIRCUIT
LOOKS FOR THE NEXT NEGATIVE TRANSITION ON PARALLEL BUS
CLOCK LEAD CLK AND RELEASES GPO ON THE FOLLOWING POS-
ITIVE TRANSITION INSURING THAT GPO IS OF SUFFICIENT
WIDTH TO OPERATE THE PARITY GENERATION CIRCUITS IN THE
BUS TERMINATOR (BT). BT RESPONDS WITH GPRO, INSTRUCTING
BUF TC REMOVE ITS STATUS AND ITS WAITO FROM THE BUS.
BUF LATER REMOVES SYNCO AFTER SSTO HAS BEEN NEGATED.

PROGRESS TO CONTINUE. AN EXCEPTION TO THE ABOVE IS AN
-- | jr ,p COMMAND IN WHICH A CQH1AH0 Dl CODER OUTPUT IS USED
TC INHIBIT WAITO. RC MOT CAM BE USED TC ADDRESS BUF
WITHOUT HANGING UP THE BUS IF BUT IS BUSY. THE ABSENCE
C-F THE BUSY CONDITION IS REFLECTED BY THE STATE OF THE
TOY STATUS BIT.

BUF REPORTS AN .NTERNUPT TO THE- 3ACC WHEN THE BR 'LAG IS
SET AND Tr'f STATE REGISTER BIT INTC-F IS NOT SET. AS-
SERTION OF BUS CONTROL LEAD ACKIC GATES BU C 'S INTERRUPT
IDENTIFICATION RESPONSE ONTO INF010. THIS LEAD IS RE-
LEASED UPON RECEPTION OF GPRO.

COMPOSITE DIAGRAM B SHOWS BUF SEQUENCING TO BE DIVIDED
BETWEEN TWO DISTINCT SEQUENCERS. THE OFF-LINE SEQUENCER
EaSEQ HANDLE! LOAD, UNLOAD, AND STUFF OPERATIONS. 0FLSE3
IS BASICALLY A FOUR ELEMENT TIMING CHAIN (BFLSEQA-D)
05110 BY A FREE-RUNNING BUF CLOCK (BCLK). BCLK PROVIDES
A SQUARE UAVE PULSE TRAIN WITh A NOMINAL 600 MS PERIOD.

BPSEG ACTION BEGINS WITH A Y6.SFQ PULSE. TG. SEO IS
DERIVED FROM SO OR RO PULSES OR RC PULSES WHICH SET THE
STAT r AGISTER STUFF OR UNLOAC BITS. THF iHAILING EDGE
OF TG,'.n TOGGLES BFLSEOA WHICH THEt; FNABLE3 THl CONSECU-
TIVE ACTUATION CF TIMING CHAIN ELEMENTS BFLSEQ6-D ON
SUCCESSIVE NFGAT'VF TRANSITIONS OF BCLK, FIGURE 6 (SHT B5GC).
A BUSY CONDITIO* EXISTS WHENEVER 0R.SEQA OR C ARE ACTIVATED.
THF ACTIVATION OF BFLSEQB FORCES THF ITS INTO TIC SERIAL
SHIFTING MODE. BFLSEQO ENABLES AN OFF-LINE CLOCK SIGNAL
(CLKITRO 0FLCIK1) DERIVED FRCM BCLK. A NEGATIVE TRAN-
SITION OF THE OFF-LINE CLOCK SIGNAL CLOCKS THE STATE OF
THE 'TR SERIAL OUTPUT INTO LDD. THE FCLIOWING POSITIVE
TRANSITION HCVES THE OFF-LINE BUFFER OUTPUT INTO THE ITR,
CLOCKS THE STATE OF LCD INTO THE BUFFER iNPUT, AND IN-
CREMENTS THE BUFFER COUNTER.

THF SEQUENCE OF FIGURE 6 IS PERFORMED AT THE START OF ALL
OFF-LINE OPERATIONS WITH THE EXCEPTION OF THE LOAD OPERA-
TION WHICH REQUIRES THE ADDITIONAL PARITY CHECKING FUNC-
TION LDPCKD (DFLAYS A SST OPERATION) IS ACTIVE FRC.-I
T iic POSITIVE 0FLSEQA TRANSITION TO POSITIVE BFLSEQC TRAN-
SITION AT WHICH TIME PARALLEL PARITY IS CHECKED. A PAR-
ITY EUROS AT THIS TIME SETS FTER F/F CAUSING THE TIMING
CHAIN ELEMENTS TO SEQUENTIALLY DROP OFF AND INHIBITING
ANY OFF-LINE CLOCK PULSES. BFLSEO IS LOCKED OFF UNTIL
THE PTER F/F IS CLEARED VIA BUT RESET OR WIT. THF. AB-
SENCE OF A PARITY ERROR AT THE BFLSEQC TRANSITION ALLOWS
eaSEQ TO CONTINUE THE LOAD OPERATION.

3ELSEQD ENABLES THESHIFTING PHASE OF AN OTF-LINE OPERA-
TION. FIGURE 7 (SHT B3GD) SHOWS THE SHIFTING ASSOCIATED
WITH A LOAD OR UNLOAD OPERATION. SIXTEEN DATA BITS ARE
SERIALLY TRANSFERRED BETWEEN THE ITR ANO THE OFF-LINE
BUFFER BY THE OFF-LINE CLOCK. THE OFF-LINE BUFFER COUN-
TER GENERATES A 16-BIT CARRY PULSE, H6BC, WHOSE TRAILING
EDGE TERMINATES SHIFTING AND INCREMENTS STUFF COUNTER
SCNT' SCNT TALLIES THE NUMBER CF IT6BC PULSES (16-BIT
TRANFERS) DETECTED SINCE THE LOAD STATE WAS LAST SET.
BaSEQ DROPS OFF AS SHOWN AT THE COMPLETION OF SHIFTING.
SCNT RECYCLES TC ZERO ON THE RECEPTION OF THE 64TH H6BC
PULSE.

SHINING IN A ST FF OPERATION (FIGURE 8 - SHT 63CE) PR0CEEDS CON-
TINUOUSLY OVER 1 TIT WORD BOUNDARIES UNTIL DATA IN THE
OFF-LINE BUFFER I'.hS BEEN PIGHT-ACJUSTED TO THE BUFFER
OUTPUT, AS INDICATED BY 5CI!T. LDD IS HELD CLEAR DURING
STUFF SHIFTING, PADDING THE OFF-LINE BUFFER WITH ALL
ZEROES.

FOLLOWING IS A DESCRIPTION OF THE LEADS WHICH COMPRISE
THE SERIAL SUFFER BUS. THESE LEADS ARE ALL TERMINATED
AT THE BT.

RSHPO IS THE PRIMARY CLOCK SOURCE FOR THE ON-LINE
BUFFER. CLOCK PULSES SUPPLIED BY THE CTTC ON THIS
LEAD SHUT DATA INTO AND OUT OF THE ON-LINE BUFFER.

DATA SHIFTED OUT OF THE ON-LINE BUFFER APPEARS ON
SOCTO FOLLOWING A NEGATIVE TRANSITION ON BSHPC,
FIGURE 9 (SHT B5GF). DATA IS NOT VALID PRIOR TO THE
LEADING EDGE OF THE FIRST CLOCK PULSE.

DATA IS SHIFTED INTO THE ON-LINE BUFFER FROM THIS
LFAO ON THE TRAILING EDGE OF BSHPO. INPUT DATA
MUST BE STEADY FOR A PERIOD BRACKETING THIS

BA16CR0 IS A MARKER PULSE GENERATED BY THE ON-LINE
BUFFER COUNTER WHICH COINCIDES WITH EVERY 16TH
ON-LINE CLOCK PULSE.

BACRC IS A HARKER PULSE GENERATED BY THE ON-LINE
BUFFER COUNTER INDICATING THE ON-LINE BUFFER HAS
BEE!. CLOCKED 1024 TIMES.

BR FLAG CAN BE RETIRED. AN OVERFLOW CONDITION
LOCKS OUT ON-LINE CLOCK SIGNALS.

THE CTTC ACTIVATES FILLO TO INITIATE A FILL OPERA-
TION, RIGHT ADJUSTING DATA IN THE ON-LINE SUFFER.

BCLK IS A FREE-RUNNING CLOCK WHICH DRIVES 9UF
SEQUENCERS AND WHICH IS BROUGHT OUT ON THE SERIAL
BUFFER BUS FOR OPTIONAL USE BY DEVICES ON WIS
BUS, BCLK IS A SQUARE WAVE PULSE TRAIN WITH A
NOMINAL 600 NS PERIOD.

CTTC SHIFTING OF THE ON-LINE BUFFER IS SHOW; IN FIGURE
9 (SHT B3GF). THE TRAILING EDGE OF BACRO FIRES IW
Ot'-LINE BUFFER COMPLETE MOHOPULSER 0NLCMP, HHICH RAISES
THE SR F..AG AND SWITCHES THE BUFFERS WITHOUT INTERFERING
CTTC/BUF DATA TRANSFER. NOTE THAT IF THE BR PJ.Z IS
STILL RAISED AT THE TRAILING EDGE OF 0NLCMP, AN OVER-
FLY conditio;: exists, the buffers do not switch and on-
line BUFFER CLOCKING IS INHIBITED.

THE ON-LINE SEQUENCER BNLSEQ HANDLES CTTC OR 5ACC RE-
QUESTED FILL OPERATIONS. BNLSEQ IS A THREE ELEMENT
TIMING CHAIN (BNLSEQA-C) DRIVEN BY BCLK. ACTION SEGINS
WITH CTTC ASSERTION OF FILLO OR THE ACTIVATION OF THE
COMMAND DECODER FILL OUTPUT, EITHER OF WHICH SET BNLSEQA,
FIGURE 10 (SHT B3GG). SUBSEQUENT NEGATIVE TRANSITIONS
OF BCLK SET ELEMENTS BNLSEQB AND C CONSECUTIVELY 0NLSFQC
ENABLES ON-LINE BUFFER SHIFTING BY A SERIES OF CLOCK
PULSES DERIVED FROM BCLK INFORMATION AT THE BuF^ER OUT-
PUT WILL BE RECIRCULATED INTO THE BUFFER INa'TOURINC'
FIU OPERATION (NORMALLY PADDING THE BUFFER WI"H ZEROES/
UN'LESS THE CTTC H0LDS SDWO L0W. IN WHICH CASE
THE BUFFER IS PADDED WITH ALL 0NES. THE TRAILING
EDGE BF BACRO INDICATES THE RIGHT ADJUSTMENT BE
THE BN - ' INE BUFFER IS CBMPLETE EY FIRING flNLCHF.
WHICH IN TURN RAISES THE BR FLAG AND SWITCHES
BUFFERS. BNLSEQ SUBSEQUENTLY DR0PS 0FF, TEkkINATI >-
FURTHER SHIFTING.

WTA10 f WTA00,WREtiAB0,TTSR0 f TTSf0,TTSEL0,TTINUC,
TTREHCO^TT^aO.TTFFQ^RTAIO.RTAOO (12 LEADS)

THAT THE ON-LiNE (ACTIVE) DATA BUFFER
HAS BEEN EITHER FILLED OR EMflED.
ACTIVE LOW

CTTC'S CLEAR THE CYLIC REDUNDANCY CHECK
CIRCUIT COMMAND BEING DECODED. LOW
ACTIVE

ERROR INDICATION OUTPUT OF THE CYCLIC
REDUNDANCY CHECK CIRCUIT. ACTIVE LOW

INHIBITS THE DATA DETECT STATUS SIGNAL
FROM THE CTT UNTIL THE TAPE HAS
ACCELERATED TO FULL SPEED DURING
BACKSPACE. READ-A-BLOCK. ASD
READ-AFTER-WR'TE OPERATIONS. ACTIVE LOW

ENABLE THE RIAC CIRCUITS OF THE CTTC TO
ACCEPT READ DATA FROM THE CTT. ACTIVE
HIGH

REQUEST TO THE SPI TO TRANSMIT AN ERROR
START CODE IN THE CURRENT STATUS REPLY
TO THE CC. LOW ACTIVE

CTTC'S TAPE MOTION REOUEST PEG1STER IS
SET TO FAST OR SLOW FORWARD. ACTIVE LOW

REQUEST TO BT TO GENERATE PARITY OVER
THE STATUS REPLY CURRENTLY RESIDING ON
THE COMMON PARALLEL BUS

TDC INITIALIZE COMMAND EXECUTE
(LOGICALLY EQUIVALENT TO INITO). ACTIVE
LOW

STATUS PULSE FROM CTT TO INDICATE THAT
THE CTT HAS SENSED THE LOAD POINT OR
EARLY WARntNG HCi MARK ON THE TAPE.
ACTIVE LOW

CTTC IS IN THE MAINTENANCE MODE OF
OPERATION. (COMPLEMENT OF MAINTO) ACTIVE
HIGH

REOUEST TO THE CTT TO ENABLE THE
OPERATORS REWIND AND UNLOAD MANUAL PUSH
BUTTONS

GATE THE CTTC'S PRIMARY STVTUS REPLY TO
TK. PARALLEL INFORMATION BUS, HIGH
ACTIVE

RECEIVE THE DATA ON THE COMMON PARALLEL
BUS AND INTERPRET IT AS A COMMAND, LOW
ACTIVE

READ DATA ADJUST FOR PROPER 16-BIT WORD
FRAMING (COMPLEMENT OF RDADJ1). ACTIVE
LOW

READ DATA ADJUJT FOR PROPER 16-BIT WORD
FRAMING (COMPLEMENT OF RDADJO), ACTIVE
HIGH

CLEAR THE CRC CHECK CIRCUIT FOR A READ
OR READ-AFTER-WRITE OPERATION, ACTIVE
LOW

CTTC'S TAPE MOTION REOUEST REGISTER 'S
SET TO FAST OR SLOW REVERSE. ACTIVE LOW

READ SHIFT PULSE USED TO GENERATE DATA
SHIFT PULSES TO THE BUFFER. ACTIVE HIGH

CTT IS PERFORMING A TAPE REWIND SEQUENCE
(LOGICALLY EQUIVALENT TO RWDINGBO). LOW
ACTIVE

CTT IS PERFORMING A TAPE REWIND SEQUENCE
(LOGICALLY EQUIVALENT TO RWDINGAO). LOW
ACTIVE

CTTC'S SHIFT CYCLIC REDUNDANCY CHECK
CIRCUIT COMMAND BEING DECODED. LOW
ACTIVE

A SYNCHRONIZING SIGNAL TO THE SPI WHICH
INDICATES THAT A DEVICE HAS SENSED A
COMMAND ON THE PARALLEL BUS. ACTIVE LOW

TAPE IS MOVING STATUS BIT =RCM CTT
(LOGICALLY EQUIVALENT TO TIM30). ACTIVE
LOW

TAPE IS MOVING STATUS BIT FROM CTT
(LOGICALLY EQUIVALENT TO TIMAO). ACTIVE
LOW

PHYSICAL END-OF-TAPE STATUS BIT FROM CTT
(LOGICALLY EQUIVALENT TC TTEOTBO).
ACTIVE LOW

CTTC'S 3-0UT-0F-6 DEVICE SELECTIONS CODE
IS PRESENT ON THE PARALLEL INFORMATION
BUS LINES INFOOO THROUGH INF350 DURING
SCO. ACTIVE LOW

SPl'S. RECEIVE COMMAND SIGNAL. BUFFERED
FOR USE BY THE CTTC (LOGICALLY THE
COMPLEMENT OF RCO). ACTIVE HIGH

A REOUEST TO THE SPI TO WAIT UNTIL TW
DEVICE HAS HAD TIME TO ACT UPON A
COMMAND BEFORE REMOVING TH*' COMMAND
FROM THE PARALLEL BUS. ACTIVE LOW

WRITE DATA BEING PRESENTED TO THE CTTC'S
PHASE ENCODING CIRCUITRY, HIGH =
LOGICAL ONE

OUTPUT CF THE CTTC'S WRITE CIRCUITRY
ENABLE FLIP-FLOP (LOGICALLY EQUIVALENT
TO WRENABO). ACTIVE LOW

WRITE CIRCUITRY ENABLE REQUEST LINE TO
THE CTT (LOGICALLY EQUIVALENT TO
WENAAO). ACTIVE LOW

WRITE DATA DELAY PULSE USED TO DELAY THE
STARTING OF THE WRITE DATA OPERATION
UNTIL THE TAPE IS MOVING AT FULL SPEED
AND THE PROPER LENGTH 1BG HAS BEEN —
WRITTEN, ACTIVE LOW

CTTC'S WR1TE-A-BL0CK COMMAND IS BEING
DECODED AND A NONWRITE FROTECTED TRACK
IS SELECTED. ACTIVE LOW

1 DATA P0STAMBLE IS STRIPPED BY BEING LEFT IN THE DELAY
REGISTER AT THE TERS1INATI8N 0F A READ ADJUST BPERATI0N.

1. LEADS INDICATED SHALi BE PAIRED AND TWISTED WITH A
SIMILARLY NAMED GROUND LEAD ittMHMG FP*4 THE
CARTRIDGE TAPE TRANSPBRT T0 AN INTERMEDIATE
CTF STAGING AREA.

STATUS PULSE FROM CTT TO INDICATE THAT
THE CTT HAS SENSED THE LOAD POINT OR

REQUEST TO THE CTT TO ENABLE THE
OPERATORS REWIND AND UNLOAD MANUAL PUSH

SWITCH SI IS AN ALTERNATE ACTI3N SWITCH
SUCH THAT IT IS DEPRESSEO SINCE T3 CL0SE
ALL C0NTACTS ANO DEPRESSED AGAIN T0
0PEN ALL C0NTACTS.

NPA »5V CONVERTER POWER ALARM OUTPUT AND
POWER ALARM RESET INPUT. ACTIVE LOW

20u'2400 bps, switched networt or private line
20ea 1900 bps. 4 wire private line
20sb 4800 bps, switched network
209a 9600 bps. 4 wire private line

THAT THE ON-LINE (ACTIVE) DATA BUFFER
HAS BEEN EITHER FILLED OR EMPTltD.
ACTIVE LOW

request to the spi to transmit an error
start code in 'he current status reply
to the cc. low active

reouest to bt to generate parity over
the status reply currently residing on
the common parallel bus

ADDRESS DEVICE TO RECEIVE THE DATA ON
T«E COMMON PARALLEL BUS AND INTERPRET
THEM AS A COMMAND. LOW, ACTIVE

AWRESSED DEVICE TO RECEIVE THE DATA ON
THE COMMON PARALLEL BUS. ACTIVE LOW

ADDRESSED DEVICE REQUESTED TO GATE A
STATUS REPLY ON THE COMMON PARALLEL BUS.
ACTIVE LOW

A S'iNCHRONIZlNG SIGNAL TO THF. SPI WHICH
INDICATES THAT A DEVICE HAS SENSED A
COMMAND ON THE PARALLEL BUS. ACTIVE LOW

A REQUEST TO THE SPI TO WAIT UNTIL THE
DEVICE HAS HAD TIME TO ACT UPON A
COMMAND BEFORE REMOVING THAT COMMAND
FROM THE COMMON PARALLEL BUS. ACTIVE LOW

1.1 THE SDSC CIRCUIT PACKS ARE A USER SPECIFIED OPTION TO THE
TDC CIRCUIT ANO MAY BE PURCHASED SEPARATELY. TDC'S BUILT
AFTER HID 1977 WILL HAVE BACKPLANE WIRING FACTORY INSTALLED.
WIRING LISTS ARE AVAILABLE FOR USERS WISHING TO RETROFIT
EXISTING TDCS. THE SDSC IS REQUIRED FOR 2B ESS OFFICES
USING THE EF2 GENERIC.

BY A USER SUPPLIED DATA SET WHICH HAY BE LOCATED UP TO 50 "IRE
FEET AWAY FROM THE TDC. THE TDC BACKPLANE CONTAINS A
KS-19088,L14 CONNECTOR TO HATE WITH ALL E1A BINARY
SYNCHRONOUS HALF DUPLEX DATA SETS WITH A USER SUPPLIED CABLF.

1.5 THE SDSC HAS THE CAPABILITY TO OPERATE AT 2K.2.4K.4.8K AND
9.6K BITS PER SECOND. HO ALTERATION OF THE SOSC IS REQUIRED
TO OPERATE AT THE VARIOUS DATA RATES. IT IS NECCESSARY THAT
SPEED AND FUNCTION COMPATIBLE DATA SETS BE USED AT OPPOSITE
ENDS OF THE DATA LINK.

1.4 PRIOR TO ATTACHING A DATA SET TO THE SDSC THE FOLLOWING
OPTIONS INTERNAL TO THE DATA SET SHOULD BE CHECKED PER THE
APPROPRIATE BSP. ALL OTHER OPTIONS AS SUPPLIED BY THE
FACTORY.

1.4.1. GROUNDING - FOR ESS USE FRAME GROUND MUST BE SEPARATED
FROM SIGNAL GROUND.

1.5 THE SDSC WILL ONLY OPERATE III HALF-DUPLEX MODE. E.G. IT
MAY NOT BE USED TO SIMULTANEOUSLY TRANSMIT ANO RECEIVE.

1.6 THE SDSC IS TRANSPARENT TO THE PROTOCOL USED. IT IS ALSO
TRANSPARENT TO THE DATA TRAWSHITTED WITH THE EXCEPTION OF

THE FIRST CHARACTERS IHICH MET BE EIA STANDARD SYN CHARACTERS.
THESE ARE USED FOR MESSAGE DETECTION AND DISCARDED. ALL
OTHER DATA MANIPULATIONS MUST BE DONE BY THE PROGRAM.

2.1 ©LINE INACTIVE, TRANSHIT CLOCK IS ALWAYS PRESENT FROM THF
DATA SETS TO THE CUSTOMER EQUIPMENT (SDSC) AT BOTH ENDS OF
THE LINE.

2.2 THE CALLING END HAS DIALED AMD THE CALLED PHONE IS RINGING
©THE LINE LIGHT ON THE CALLED PHONE IS FLASHING.

2.5 THE LINE KEY IS DEPRESSED® (PLACING THE PHONE IN THE VOICE
MODE), THE HANDSET IS PICKED IIP, AND VOICE CONTACT IS
ESTABLISHED.

2.4 THE FIRST PROGRAM ACTIOS TWHI IS TO SET DATA TERMINAL READY
© THE "TR" LAMP ON A 201-C DATA SET WILL BE LIT WHEN DTR
IS ACTIVE.

2.5 THE DATA (RaEASE) KEY OB THE TEL. SET IS THEN DEPRESSED©
THE LINE LIGHT SHOULD THEM ILLUMINATE AND THE HANDSET HAY BE
HUNG UP WITHOUT DROPPING THE LINE.

2.6 APPROXIMATELY 55ms LATER THE DATA SET WILL ACTIVATE ITS
READY BIT© INDICATING DATA MODE AND ILLUMINATE THE "MR"
LAMP (201-C).

2.7 THE OH STATE OF THE "MR" LAW SHOULD NOT BE INTERPRETED TO
MEAN THAT A DATA COMMtHI CAT IONS PATH EXISTS. THE CALLING
STATION MUST ALSO BE III THE DATA MODE.

THE PROTOCOL) BUT FOR THE SAKE OF THIS EXAMPLE WE WILL ASSUME
THE CALLING END DOES SO.

2.9 THE CALLED (RECEIVING} END MET SET ITS' RECEIVE BIT©
ENABLING THE RECEIVE MESSAGE REGISTER AND THE CALLING
(TRANSMITTING) END TMEB SETS ITS TRANSMIT BIT WHICH ASSERTS
REQUEST TO SEND TO THE DATA SET © .

2.14 AS THE FIRST NON-SYN CHARACTER IS DETECTED THE SDSC WILL
ASSERT "NEW MESSAGE" © OHF070) .

MAY DISABLE REQUEST TO SEND EITHER MANUALLY OR AUTOMATICALLY
VIA THE ABE BIT. THIS IS IMMEDIATELY REFLECTED BY THE DATA
SET REMOVING CLEAR TO SEND.

2.17 THE RECEIVING OATA SET SIMILARLY CONTINUES TO RUN FOR SEVERAL
CYCLES © FOR THE SAKE REASON AND THEN DISABLES CARRIER
DETECT TO THE CALLED SDSC.

2.18 THE SDSC SEES DCD GO AWAY AND REMOVES THE RECEIVE CLOCK
(IF STILL PRESENT) CAUSING NEW MESSAGE AND SYNC TO GO
INACTIVE. THIS TRIGGERS AN END OF MESSAGE PULSE AND FORCES
A FILL OF THE TDC BUFFER CIRCUIT IF THE BUFFER READY FLAG
IS NOT SET.

2.20 COMMUNICATIONS TYPICALLY CONTINUE LIKE THIS WITH REPETITIVE
LINE REVERSALS UNTIL ALL DATA IS TRANSMITTED © .

2.21 DATA TRANSFER MAY BE INTERRUPTED AT ANY TIME TO RE-ESTABLISH
VOICE CONTACT (SEE F"G. 2) OR TERHINATE THE CALL. TRANSFER
TO VOICE MODE OR CALL TERMINATION MUST OCCUR AT BOTH ENDS

2.22 THE CALL IS TERMINATE^ BY EITHER © TRANSFERING TO VOICE
MODE AND HANGING UP Or , IF THE DATf SET IS OPTIONED FOR DTR
CONTROL, BY REMOVING DATA TERMINAL READY Q .

2.23 THE LINE IS ACTUALLY TERMINATED 15ms LATER © WHEN DATA
SET READY GOES INACTIVE.

2.11 APPROXIMATELY 5ms LATER © THE CARRIER SENT BY THE
CALLING END IS RECEIVED AND SYNCHRON I ZED BY THE CALLED
DATA SET WHICH BEGINS TO SEND CLOCK INFORMATION ANO
CARRIER DETECT TO THE CALLED SDSC.

2.12 ANY TIME AFTER CTS GOES ACTIVE THE CALLING SDSC IS FREE
TO SEND DATA TO ITS* DATA SET © USING THE TRANSHIT
CLOCK TO SHIFT DATA FROM THE TDC BUFFER CIRCUIT.

2.13 AFTER DETECTING TWO SW CHARACTERS (026 OR 226) ©
CALLED SOSC INDICATES SYNCHRONIZATION (INF 060).

THESE SIGNALS OCCUR IDENTICALLY AT THE
OPPOSITE END OF THE LINE DURING THE
REVERSE DATA TRANSFER. ALL SHOULD BE
INACTIVE DURII.G NORMAL CALL TERMINATION.

1. the point at which dtr is set is mot critical as long
as it is active prior to putting the tel set into data

3. RINGO IS ONLY ACTIVE AT THE TIME THE CALLED TEL SET IS
ACTUALLY RINGING (THE SAME TIME AS THE TEL SET LINE
LAMP IS LIT).

5. UNLESS OTHERWISE STATED, SIGNALS SHOWN ARE THE CALLED
END OF THE LINE (THE END WHICH RECEIVES THE FIRST
MESSAGE).

6. RECB1 MUST BE SET PRIOR TO RDATA1 GOING ACTIVE AND
SHOULD BE SET PRIOR TO DCDO GOING ACTIVE.

8. ALTHOUGH CTS GOES INACTIVE SIMULTANEOUSLY WITH RTS
THERE IS AN EFFECTIVE INTERVAL OF 1-2ms WHEN RTS Mtfi
eS REASSERTED WITHOUT INVOKING THE NORMAL 150-»s DELAY.

9. LINE DISCONNECT IS ACHIEVED IN DATA MODE BY REHOVING
DTR, OR IN VOICE MODE BY HANGING UP THE HANDSET.

10. DELAY INDICATED AT THESE POINTS IS VARIABLE ID A
FUNCTION OF PROGRAM TIMING.

3 1 A CALL HAY BE ORIGINATED EITHER MANUALLY AS SHOWN IN
FIGURE 1, OR AUTOMATICALLY WITH AT! AUTOMATIC CALLING
UNIT (ACU). THE ACU MUST BE INTERFACED SEPARATELY
FROM THF DATA SET.

1. the actual point at which dtr is set is not critical
as long as it is set prior to transferring into data

201. UNLESS OTHERWISE SPECIFIED. ALL HIRING SHALL BE 30 GAUGE.
AUTOMATICALLY INSTALLED, 0-4 TTPE HIRING.

207 THE DATA SET MAY BE LOCATED lil ANY SPACE AVAILABLE AS LONG AS
THE CONNECTING CIRCUIT CABLE DOES fiOT EXCEED 50 FEET IN L£t«TH.

302. IN SDSC APPLlCAIIONS OF THE TDC REFER TO
APPROPRIATE SD FOR INFORMATION ON USER SUPPLIED
DATA SET. SEE NOTE 1 ON FS 7 FOR SOSC COMPATIBLE
RECOMMENDED DATA SETS.

10 THIS TERHINA1 IS A STAJSARD COAXIAL TERMINATION FIELP(CTF) GROUND PIN. IT'S GROUND IS COMMON WITH ALL GROUND
TERMINALS VIA ThE WitTliAYER PRINTFE HIRING BGARC(MLPWB), E04C017-30, GROUND PLANE.

11. THE FOLLOWING SHOWS Tt£ SYJSCLIC EQUIVALENT OF THE TABULAR REPRESENTATION".

13. THE FOLLOWING SHOWS THE SYMBOLIC EQUIVALEHT CF THE TABULAR REPRESENTATION;

14. THE FOLLOWING SHOWS THE SYMBOLIC EQUIVALENT CF THE TABULAR REPRESENTATION;

15. THE FOLLOHING SHOWS THE SYMBOLIC EQUIVALENT OF THE TABULAR REPRESENTATION:

16. THE FOLLOWING SHOWS THE SYMBOLIC EQUIVALENT OF THE TABULAR REPRESENTATION:

OPT NOTE DESTINATION DESIG METHOD SYM TERMINAL DESIG TERMINATION TERMINAL

HTAOOO CA3
RTAOOG CA3
kTA'OG CA3
RTA10G CA3
URENABOG CA3
HROATAG CA3
RDDATAOG CA3
ROCLKOG CA3
DATDETOG CA3
OATDETO CA3
HTAOO
RTAOO
HTA10
RTA10
HFCNABO
URDATA
RDDATAO
RDCLKO

Common Systems, Tape Data Controller circuit


APPENDIX 3D

DWG ISSUE 14D

DISTN CODE 1T99

FEB 2

S 1977

^

CHANGES

D. Description of Changes . ■

D.l Changed the rating of option W from A&M Only to AT&TCo

Standard for No. 3 ESS only. Option W remains A&M Only .
for all other systems.

D.2 Added Circuit Note 111 which details the limited use of

option w. i ■ '

D.3 Changed Circuit Note 104 and FS 1 to reflect the changes
in D . 1 . .'

D.4 Corrected a drawing error in Circuit Note 102.

BELL TELEPHONE LABORATORIES, INCORPORATED

DEPT 5317-GJS-GH

\^F

^i!P

Printed in U.S.A.

Page 1
1 Page

fi

Ji.

<^

CIRCUIT DESCRIPTION

CD-1A210-01

ISSUE 7D

APPENDIX 2D

DWG ISSUE 13D

vy

ELECTRONIC SWITCHING SYSTEMS

NO. 1, lA, 2, OR NO. 3
ARRANGED WITH 2 -WIRE FEATURES

REMOTE MASTER SCANNER
APPLIQUE CIRCUIT-

FEB 1 8 1975

1^1

CHANGES

D. Description of Changes

D.l Revised FS I to show the necessary connecting Information
for the application of this circuit into ESS No. 3-

D.2 Corrected the lead Index and Circuit Notes 102 and 104 on
FS 1 and CAD 1 to reflect the changes in D.l.

BELL TELEPHONE LABORATORIES, INCORPORATED'

DEPT 5317-GJS-GH

'kJ

Printed in U. S. A,

Page 1
1 Page

CIRCUIT DESCRIPTION

CD- 1A2 10-01

ISSUE 7D

APPENDIX -IB

DWG ISSUE 12B

ELECTRONIC SWITCHING SYSTEMS

FEB 2 4 1975

NO. 1 OR NO. 2
ARRANGED WITH 2-WIRE FEATURES

P EMOTE MASTER SCANNER
APPLIQUE CIRCUIT

^

^^f'

. CHANGES

B . Changes in Apparatus
B. 1 Added

CR10 through CR15

App Fig. 1
CR20 through CR25

App Fig. 1

(6) Diodes 4 46K -
(6) Diodes 446K -

D . D escription of Changes

D. 1 Revised FS 1 to show the addition of
battery isolating diodes, option R. The
diodes will eliminate circulating currents
between paralleled battery plants caused by
potential di f f erences .

D.2 The option index. Circuit Notes 102
and 104, and App Fig. 1 have been corrected
to reflect the addition of the battery
isolating diodes.

D.3 Added Circuit Note 110 and Equipment

Note 204-

F. Changes in Description of Oger a tign

F.I In Section II, under 4-. BATTERY_AND

GROUND FOR OUTSIDE ESS OFFICE, add:

(d) Option R when the circuit is part of
a multiple monitoring a single signal
source in conjunction with other
collocated No. 1 ESS offices.

F.2 In Section II, unde^ 6-_ PURPOSE_OF

COMPONENTS, add:

6.03 Diodes CRI and CR2 (option R) are
provided to eliminate circulating currents
between multipled No. 1 ESS offices
resulting from battery potential
differences.

w

\i

!\

1
i

( I i

BELL TELEPHONE LABORATORIES, INCORPORATED

DEPT 5317-GJS-GH

Printed in U.S.A.

Page 1 , 1 Page

f
L

-=»i«ivrTr- --^1

CIRCUIT DESCRIPTION

CD-1A210-01

ISSaE 7D

DH3 ISSUE 11D

ELECTRONIC SWITCHING SYSTEMS

FEB 2 ^ 1975

NO. 1 OR NO. 2
ARRANGED WITH 2 -WIRE FEATURES

REMOTE MASTER SCANNER
APPLIQUE CIRCUIT

SECTION I

GENERAL DESCRIPTION

^:z7

Sw^

#

"<!■

1. PURPOSE OF CIRCUIT

1.01 The purpose of this circuit is to
provide means to connect miscellaneous
circuits outside the central office to the
master scanner or universal trunk scanner
circuit.

2. GENERAL METHOD OF OPERATION

2.01 Connecting circuits requiring the
use of this circuit must connect on a loop
basis and be capable of opening or closing
the loop.

2.02 Battery and ground can be supplied
by either the No. 1 ESS or by the
transmission facility, but not both.

2.03 When battery and ground is
supplied by No. 1 ESS, it can be supplied
either by the master scanner circuit or by
this circuit, but not both.

2.04 The remote master scanner applique
circuit can be used for connecting circuits
within the office.

SECTION I I - DETAILED DESCRIPTION

1 . LOOP SIGNAL S

1.01 Connecting circuits requiring the
use of this circuit must supply an open or
closed loop signal. An open loop provides
no current; a closed loop produces current
in the associated ferrod sensor control
winding.

2. FERRO D SENSOR

2.01 One ferrod sensor is associated
with one applique circuit. The, applique
circuits are designated through 7. There
are eight circuits per unit.

3i MASTER SCANNER OR. UNIVERSAL

TiyNK_SCANNER ~ '

3.01 The scanner circuit is under
program control and reports the loop
condition to the system.

ii BATTERY, AND .GROUND, FACILITIES FOR

gUTSIDE_ESS_2FFICE

4.01 Transmission facilities outside
the central office should be compatible
with one of trie follo#fing options:

(a) Option Y when battery and ground is
provided at the scanner circuit

(b) Option W when battery and ground is
not provided at the scanner circuit
or fro.Ti the distant office

(c) Option Z when battery and ground is
provided by the distant office.

5i. BATTERY. AND„GROUNp„FACILITIES_FOR

INSIDE THE ESS OFFICE"

5.0 1 Connecting circuits within the
office should be compatible with one of the
following options:

(a) Option W when battery and ground is
not provided by the scanner circuit

(b) Option Y when battery and ground is
provided Dy the scanner circuit.

6i. PURPOSE. OF_COM PONE NTS

6.01 Resistors R1 and R2 limit the
current and provide lightning protection
and a balanced loop for each circuit.

6.0 2 Contact protection network CP
reduces the peak voltage across the ferrod
sensor for each circuit.

Printed in U.S.A.

Page 1

CD-1A21C-01

ISSUE 7D

SECTION III - REFERE NCE DATA
Is WORK ING LIMI TS

1.01 Maximum external circuit
resistance is 6.8 kilohms. Minimum

psulation resistance is 30 kilohms.

1.02 Voltage limits:
Voltage Minimum Maximum

-48 42.75 52.5

2. FUNCTIONAL DESIG NATIONS

2.01 Associated Scanner Ferrod Sensors

Isiqnat ion
through 7

FUNCTION

Me ani ng

Ferrod sensors associated
with this circuit are
numerically designated
for program reference.

3.01 The basic function of this circuit
is to provide the facilities for connecting
miscellaneous circuits outside the central
office to the master scanner or universal
trunk scanner circuit.

t. CONNECTI NG_CIRrnTTS

4.01 When this circuit is listed on a
keysheet, the information thereon is to be
followed.

(a) Master Scanner Circuit -
SD-1A1 18-01.

(b) Miscellaneous circuits for all
Frames

- SD-1A129-01.

(c) Master Scanner circuit -
SD-1A209-01.

(d) Universal Trunk Scanner -
SD-2H161-01.

(e) Route Transfer and Make Busy
circuits - SD-56048-01.

(f) Auxiliary Signal Circuit -
SD-63842-01.

(g) Toll Switchboard No. 1, 3, or 3C
Emergency Ringback Circuit -
SD-64244-01.

(h) Alarm Circuit - SD-81223-01.

(i) Power Systems - SD-8 1626-01-

(j) N2 Carrier Group Alarm Circuit -
SD-97118-01.

(k) N2 Carrier Group Alarm Circuit -
SD-97166-01.

ii MANUFACTURING TESTING REQUIREMgNTS

Intermediate R equire ments

5.01 None.
End Req uirem ents

5.02 This circuit should be tested to
verify that it is wired in accordance with
the schematic and wiring drawings, and that
the circuit is capable of performing all
functions stated in this circuit
discription,

6^ ALA RM SYSTEMS

6.01 This circuit has a single fuse to
the -1*8 volt supply in the bay fuse panel.
There is one fuse for every eight circuits
in a unit.

6.02 A blown fuse causes the FA relay
to operate an alarm. In No. 1 ESS the FA
relay is part of the miscellaneous circuit.
In No. 2 ESS the FA relay is part of the
trunk peripheral decoder circuit.

2i rAKING_E2yiPMENT_0UT_0F_SERVICE

7.01 Instructions for taking this
circuit out of service can be found in
BSP-231-130-301.

SECTION_IV_::_REAS0NS_FOR_REISSUE
Pi. De script ion of_Changgs

D.I Changed the CADs to provide means
by which this circuit and non-ESS frames,
in the same building, can be connected
directly.

r>

^

^

D.2 Corrected CAD 1
lead designations.

to show the A, B

^kL TELEPHONE LABORATORIES, INCORPORATED
DEPT 5723-GJS-GH

r>

Page 2, 2 Pages

■-WUI^^^BII.a^ VIM^,,

•JiVBf-i

*• >. r

r-

Electronic Switching Systems, Common, Remote Master Scanner, Applique Circuit


"THE 'INFORMATION "CONTAINED KERCtbJ iSHDULD
>fc)T -BEOISCLOSED TO UNAUTHOfcim*^RSDNS.
>fT <iS '-MEANT SOLELY FOR USE BY AUTW©ft+2£D
•W^&I'F-JC-' NORTHWEST BELL EMPLOYEES.

CD-3H205-01

ISSUE 1

DWG ISSUE 1

DISTN CODE 7T11

ELECTRONIC SWITCHING SYSTEMS
NO. 3

j Ul 8 1976

DIAL-TONE-FIRST COIN LINE
CIRCUIT

m.

i ;

SECTION I

GENERAL DESCRIPTION

1.

PURPOSE OF CIRCUIT

1.01 The
specify the
J3H00EE uni
wiring and
circuit pac
potential f
Also provide
-48 volt dc
dc talk bat
♦48 volt
dial-tone- fi
the miscella

purpose of this circuit is to
wiring information for the
t, which provides the means of
physically mounting eight
ks to provide +48 volts dc
or coin lines in No. 3 ESS.
d are the fuses needed for

signal battery, the + 48 volts
tery, and the filters for the

dc talk battery. All
rst units will be mounted on
neous frames.

2^ GENERAL DESCRIPTION OF OPERA TION

2.01 The operation of this circuit
involves placing +4 8 volts dc potential
toward the coin line on the ring lead and
keepinq the tip lead at ground. Also, the
circuit repeats the supervision of tha coin
line back to the junctor circuit, where it
is maintained.

SrcTigN_II_-_pF^AILED_DESCRIP2:iON
1_. DIAL TONE FIRST (DTF) CIRCUIT

1.01 This circuit is used to connect a
coin telephone to a +48 volt dc source to
disable the TOUCH-TONE* pad and to release
a single nickel dropped into the coin
telephone. There are two DTF circuits on
one circuit pack. Distribution fuses for
both -48 and +48 Vdc and the filters of the
♦48 Vdc are provided on this unit.

POWER DISTRIBUTION

1.02 The +48 volt talk battery, via an
A and B bus, comes to the DTF unit from the
miscellaneous power frame, and is filtered
at the unit by C1, R1 for the A bus and C2,

R2 for the B bus. After the filter, power
is distributed to the circuit packs by
fuses DFAO through DFA3 for the A bus and
fuses DFBO through DFB3 for the B bus.

1.03 The -48 volt signal battery, via
an A and B bus, comes to the DFT unit from
the miscellaneous frame circuit.
Distribution of the -48 volt battery to the
DTF circuit packs is done through fuses
DCA0 through DCA3 for the A bus and DCBO
through DCB3 for the E bus.

DTF CIRCUIT •

1.04
circuit,
telephone
operation
DTF cin
indeoende
circuit
telephone
junctor
obtained
the coin

The DTF circuit,

is connected dir

that is set for

The circuit pa

uits that are oper

ntly of each ot

in the bypass s

is connected d

circuit from wh

and supervision i

telephone.

being a line
ectly to a coin
dial- tone- fir st
ck contains two
ated completely
her. With the
tate, the coin
irectly to the
ich battery is
s maintained for

* Registered U.S. Patent Office.

1.05 With the circuit in the reverse
battery state, +48 volt talk battery is
placed on the ring lead to the coin
telephone and ground is maintained on the
tip lead. Capacitors C1 and C2 are placed
into the circuit to pass ac signals and to
provide dc isolation between +48 volt
battery and the -U8 volt battery coming
from the junctor circuit. Loop current to
the coin telephone causes relay K2 to
operate, thus closinq a dc current path
through L2 back to the junctor circuit. L2
provides a low impedance for dc continuity
while maintaining a high impedance to voice
siqnals. Supervision is maintained at the
junc+or circuit with dc current.

1.06 One relay, designated A and
operated by the distributor circuit under
program control, is used to provide the
necessary states for the various functions
of the circuit. F.Ach state is defined by a
particular relay operating or releasing.

Printed in U.S.A.

Page 1

?D-3H205-01

ISSUE 1

SECTIOW III - REFEREM Cff D ATA

1. WO RKING LIM TfS

1.01 The maximum external loop

resistance is 1000 ohms . The minimum

insulation resistance is 10,000 ohms.

_FUNCTIONAL_DESI3NATIONS

2.01 Pel ay s

D esigna tion Meaning

A This relay is alpha-

betically designated
for prograrr reference.

3. FUNCTIONS

3.0 1 Provides a direct connection
itween the coin telephone and the junctor
circuit.

3.0 2 Provides the *HS volts to the ring
lead and repeats suDervision to the junctor
circuit from the coin telephone.

fij CQNNECTING_CIRCUITS

U.01 When these circuits are listed on
the keysheets, the connecting information
thereon is to be followed.

(a) Distribute
SD-3H150-01 .

Point

(b) Network Frame Circuit
Appearance) - SD-3H901-01.

Circuit -
(Network

f~\

5.= MANyFACTJJRING_TJSTING_PE2yiREMFNTS

l2^rmediate_geauirements

5.01 None.
End_Be_guirements

5.02 This circuit should be tested to
verify that it is wired in accordance with
the schematic and wiring drawing, that the
requirements of the circuit requirements
table are met, and that the circuit is
capable of performing all functions stated
in this circuit description.

L: TAKING .EQUIPM ENT OUT OF SERVICE

6.01 Information for taking this
circuit out of service is found in IM-3H000
and OM-3H000. Also, the associated fuses
must be removed before removing the PTF
circuit from this unit.

BELL TELEPHONE LABORATORIES, INCORPORATED

DEPT 5341-WLH-LFG

^\

^

Page 2, 2 Pages

Electronic Switching Systems, No. 3, Dial-Tone-First Coin Line circuit


points. These signals are the directory
number of a customer to which a distant
office is calling. In addition, this
circuit checks the continuity of loop
trunks and transmits a battery- reversal
start-pulsing signal (wink) to the MF
transmitter of the distance office. This
circuit also provides a high degree of
protection against false operation by
voice-frequency components contained in
speech or noise picked up by an operator
transmitter and/or coupled into the
transmission facility as crosstalk.

2.01 When a call is from a distant
office, the local office must be sent the
called number so that it can complete the
call. An MF receiver is the circuit that
receives the called number in the form of
tone signals from the distant office.
After the calling customer has dialed the
called number and the distant office has
determined that the call is to another
office, an idle MF transmitter will be
seized and connected to the appropriate
trunk circuit. The trunk circuit will then
send a seizure (start) signal to the local
office. The local office will connect an
idle MF receiver to the trunk circuit via a
network path through a bypassed junctor.
To verify the connection, the processor
will scan the continuity scan point of the
MF receiver. Whan the MF receiver is ready
to receive digits, the MF receiver sends a
wink (reverse battery) signal to the
distant MF transmitter. The MF transmitter
will detect the wink signal and the distant
office will cause the MF transmitter to
start sending the digits in the form of
tone signals conforming to the 2-out-of-6
code. The MF receiver will detect and
decode the signals into the frequency
components.

2.02 Several timers are used to verify
that the signals detected are true digits.
When the signal input exceeds a minimum
value, a timer is started. Once the MF

receiver decodes the signal into at least
two freauency components, a second timer is
started. When both timers time out, the
signal-present scan point is operated. The
processor will then scan the frequency scan
points to determine the digit sent and
check that only two of the six frequencies
are present. If the signal input does not
exceed the minimum valve or goes away
before the timer times out, the timer will
be reset and no signal-present indication
is given. If only one frequency is
present, the second timer will not be
started and no signal-present indication
will be given when the first timer times
out. To prevent double registration of a
digit, a third timer is started when the
signal input is removed. The third timer
will hold the signal-present scan point
operated for a period of time to prevent
noise from causing a second signal-present
indication to be given on the same digit.
After all digits have been received, the
processor idles the MF receiver and
releases it.

1.01 MF signaling uses one group of six
frequencies in the speech band (700, 900,
1100, 1300, 1500, and 1700 Hz). A valid MF
signal consists of exactly two of these six
frequencies. This signaling code is known
as the 2-out-of-6 code. There are only 1 5
valid combinations, which can be used as
digits or other signals.

1.02 When a call is from a distant
office, the distant office will locate and
connect an idle MF transmitter to the
appropriate trunk circuit. This connection
will then cause the trunk circuit to send a
seizure (start) signal to the local office.

1.03 The local
connect an idle MF-re
trunk circuit via a
bypassed junctor,
send a start-pulsing
MF transmitter when i
trunk. When the MF t
wink signal, the
operate the MF-tra
relays and begin send

office will locate and
ceiver circuit to the
network path through a
The MF receiver will
signal (wink) to the
t is connected to the
ransmitter detects the
distant office will
nsmitter tone^select
ing the digits.

1.0i» The MF receiver will receive the
signals from the distant office and decode
the individual frequencies. The receiver
will time the input signal and the
frequency combinations to verify that a
digit has been received (not noise or
speech). When the input signal persists
for a minimum time, with at least two
frequency components, the signal-present
scan point is operated. The operation of
the signal-present scan point will cause
the processor to scan the frequency scan
points. The processor then determines that
two out of the six frequencies (2-out-of-6

code) are present and that the frequency
combination is a valid combination. If
either test fails, the processor aborts the
call. To prevent double registration of a
digit (noise interference) , another timer
is started when the input signal is
removed. This timer will hold the
signal-present scan point operated for a
period of time to prevent causing the
processor to res can the frequency scan
points for the same digit. The processor
will monitor the signal-present scan point
for each successive operate and release (to
initiate a frequency scan) until all digits
are received.

2.01 The relationship between digits
and other signals and the MF-signaling
frequencies in the 2-out-of-6 signaling
code is shown in Table A.

MF receiver has one state
relay (A), which is controlled by the
distributor circuit. The processor
determines the state required and, via the
peripheral decoder circuit, operates the
relay.

3.02 Relay A, driven by -48 V, has a
1000-ohm resistor, with one of the break
contacts in parallel with it, in series
with the coil to initially provide rapid
operate. This arrangement also limits the
maximum current through the distribute
point when the relay is operated. ro limit
the transient voltage spike when the relay
is released and to dissipate the relay-coil
energy when released, a diode is connected
from the distribute point to -48- V with the
anode of the diode to -48 V.

lamo. The remainder of the circui<
components will be discussed in the order
in which the signal passes through them.

4.02 The input transmission components
are L, T, C5, C6, C7, and C8. Inductor L
connects the continuity scan point (SCO)
which suDplies battery and ground, to the
network via the tip-ring reversing contacts
of relay A. Transformer T has a very lowe-
capacitance between the primary and
secondary windings, which provides a high
degree of protection from longitudinal
lightning surges to the circuit.
Capacitors C5, C6, C7, and C8 provide
protection against metallic surges. C5 and
C6 also provide dc blocking in the
transformer primary. The input
transmission circuitry, when terminated
into the variolosser circuit (P/o circuit
pack A260) , presents a very high return
loss to the network.

3.04 When the MF receiver is in the
idle or wink state, the A relay is released
and -4 8 V and ground are connected to the
tip and ring respectively (reverse
battery) . Operating the A relay connects
-48 V and ground to the ring and
respectively.

3.05 This is a tvpical state sequence
of this circuit. See BSP 233-151-105 for
more details.

4.01 An MF-receiver circuit is
comprised of 11 circuit packs, input
transmission circuitry, and a
volt age- divider power supply (R1
through R5) . Because all operating
potentials are proportional to the battery
voltage, all potential changes are as well
Thus, overall battery variations have
little effect on receiver performance.
Filter capactors (C1 through C6 on circuit
pack A1024) smooth the output voltage of
the voltage divider. The power-off (PWR
OFF) key removes battery from the circuit
to permit circuit pack removal and testing.
A resistor (R3 on circuit pack A1024)
limits the current in the PWR OFF indicator

4.03 The variolosser circuit (P/o
circuit oack A26 0) provides a controlled
loss to the input signal and passes the
signal to the AGC amplifier (P/o circuit
pack A261). A dc control current from the
AGC will change the shunt impedance (and
thus the gain) of the variolosser circuit.
This feedback control assures an almost
constant steady-sta*-e ac signal at the
variolosser output.

. 4.04 Any feedback
finite time to respond
changes in the input
called the attack time
The attack time of
approximately 5 ms. If
is received, the vario
excessively-high input
amplifier until the
reduce the variolosser

4.05 After the receiver sends the wink
signal (reverse battery) , relay A is
operated to place the circuit in the
receive-digits state. Operating relay A
connects ground and battery to tip and ring
respectively, and also creates high-level
voice- frequency transients, which appear as
an input to the receiver. These transients
could cause the variolosser circuit to be
placed in a high- loss condition until the
AGC system responds. This high-loss
condition could persist long enough to
prevent detection of the low-level keypulse
(KP) signal from the distant office. To
prevent this problem an inhibit amplifier
(P/O circuit pack A26 2) stops the feedback
control from operating for approximately
20 ms after relay A operates. The 20-ms
delay is sufficient to allow for the
battery-reversal transients to die out and
no longer affect the operation of the
receiver.

it. 06 The AGC amplifier amplifies the
signal from the variolosser and supplies
the amplified signal to the signal driver
(P/O circuit pack A261) , the guard driver
(P/O circuit pack A260) , and the control
rectifier of the variolosser, which
generates the direct current to control the
variolosser gain.

4.07 The guard driver provides a
f reguency-dependant dc bias to the
MF-channel detectors (A152s) to prevent
digit simulation (see 5.01 through 5 .01) .
The guard filters (P/O circuit packs A26 2
and A263) short signaling frequencies out
of the guard-driver input. All other voice
freguencies are amplified and rectified to
provide the dc guard bias.

4.08 The signal driver provides power
gain to the signal so that the channel
filters (circuit packs A2 64 and A26 5) can
respond. These six filters are a parallel
combination of series- re sonant circuits.
This configuration offers low impedance at
signaling frequencies and requires that the
signal driver provide high (ac) current.

4.09 The channel filters separate the
signal into the frequency components,
corresponding to the MF-signaling code, and
apply the individual frequencies to the
MF-channel detectors. The channel
detectors (dc) will convert, the frequencies
applied to a direct current only if the
guard bias does not exist. A direct
current would operate the frequency scan
points (SC2 through SC7) . When two channel
detectors operate, a valid signal is
present.

4.10 The signal-present timer (circuit
pack A266) is two separate timers ANDed
together. The first timer is activated by
the ac signal from the signal driver. If
the input persists continuously for 20 ms,
the timer will time out and activate one
side of the AND gate. The second timer
will be activated when at least two
channel-detector outputs are operated. If
the channel- detector outDUts are operated
continuously for 10 ms, the timer will time
out and activate the other side of the AND
gate. If the input to either timer is
removed before the timer times out, the
timer will be reset. When both inputs to
the AND gate are activated, the AND gate
will operate the scanner driver (P/O
circuit pack A1024), which will operate the
signal-present scan point (SC1). The
operating of the signal-present scan point
(SC1) will cause the processor to scan the
freguency scan points (SC2 through SC7) and
interpret the digit received. To prevent
double registration of the same digit,
bridge timing is used. When the input to
the timers is removed after time-out, the
timers will time for 20 ms before releasing
the AND gate. The 20-ms delay will prevent
noise from causing the signal-present scan

5.01 The MF receiver uses guard action
to reduce digit simulation or the response
of the receiver to signals that are not
genuine MF pulses. The guard driver
applies a dc bias to the channel detectors
that varies in magnitude according to the
frequency and amplitude of the received
signal. With guard action, genuine MF
pulses excite the guard driver only weakly
and strongly excite the proper channel
detectors. Thus, the receiver is able to
respond. In contrast, most speech signals
contain many frequency components that
excite the guard driver more strongly than
the channel detectors. Guard bias is
generated to inhibit the response of the
channel detectors and the receiver tends
not to respond to signaling frequencies in
the presence of other signals.

5.02 The AGC amplifier applies a signal
to the guard driver. The MF guard filter
effectively shorts the signaling
frequencies out of the guard driver. Any
voice-frequency signal not shorted out will
be amplified and rectified to produce a
dc-bias voltage. Since the MF-signaling
frequencies are shorted out, the dc bias
will only appear as a result of the
presence of nonsignaling frequencies. This
bias raises the threshold of the channel
detectors and inhibits the recognition of
signaling frequencies. Consequently, if a
siqnal is to be recognized, frequencies in
the 2-out-of-6 code must be present and
other signals must be either absent or at a
much lower level.

5.04 Another
for ac-signal lev
or greater than
signals. Lower 1
timer at all. Th
ac signal be pre
digit can be
action and two
prevent digi
voice-frequency e

longer timing is provided
els approximately equal to
the minimum expected MF
evels cannot activate the
is timer requires that an
sent for 20 ms before a
recognized. Thus, guard
separate timing operations
t simulations by
nergy.

3.01 Provides for reception of
multifrequency signals from operator
keysets or automatic sending equipment and
converts the received signals into outputs
suitable for detection by the scanner.

3.02 Provides proper response to MF
pulses of 30-ms duration with 30-ms
intervals between pulses.

3. .03 Provides response to MF pulses
with received level within the limits of
-22 dBm and -2 dBm per tone. The receiver
is able to respond properly in the presence
of 6. C-dB twist (difference) between any
two MF tones.

^.0 4 Provides 6c output signals of at
least 11 ms for each of the signaling
frequencies, regardless of input-signal
duration, when a valid signal is received.

3.05 Provides a signal-present output
signal, which starts about 2 ms after a
valid input signal is received and remains
operated until about 20-ms after the input
signal is terminated.

3.06 Provides tolerance for variation
in the received signaling frequencies of
♦1.5 percent +10 Hz about the nominal
MF-signalinq frequencies.

(c) A signal-validity check reguiring
the operation of two (or more)
detectors for a timed interval
before the signal-present output is
delivered.

(d) A fast-cycling timer, which forces
an input signal above a threshold
level to persist uninterrupted for a
required time interval before the
signal-present output is delivered.

(e) Signal-present output holding to
prevent recycling when noise causes
short breakups in the input signals.

3.08 Provides means to prevent a
reverse-battery start-pu] sing transient
from affecting the AGC feedback loop; the
feedback loop is inhibit ed for a timed
interval after operation oi the A relay.

4.01 when this circuit is listed on a
keysheet, the connecting information
thereon is to be followed.

5.01 Before circuit packs are inserted
in the unit, it should be verified that the
unit is wired in accordance with the
schematic and wiring drawings to prevent
damage to the circuit packr.

5.02 This circuit should be tested to
verify that it is wired in accordance with
the schematic and wiring drawings, that
requirements of the circuit requirements
table are met, and that the circuit is
capable of performing all functions stated
in this circuit description.

6.01 This circuit is fused individually
with one fuse to the -«J8 V talk supply. if
the fuse blows, it will cause an FA relay,
in the frame that it is mounted on, to
operate as alarm.

7.01 Information on taking this circuit
out of service can be found in BSP IM-3H0
and OM-3H000.

Electronic Switching Systems, No. 3, Multifrequency Receiver Circuit


order to break the ground loop between battery boost
circuits. This is reflected in Equipment Note 202.

D.l Diodes were added to cable assembly CA02 to break up the input
node multiple and to confine the effects of a cross between the
tip/ring path and the pulse path.

2.01 The detailed operation of all
circuits listed in Table A may be found in
the circuit description for each one. Any
circuit that is shown only in the Network
Frame Circuit St will be explained in
detail in this document.

1.01 The system control periodically
alternates the on- and off-line states of
the two halves cf the ringing and tone
(P6T) plant. Pa this occurs, the RTS relay
on each network traire 1b operated or
released. This causes the audible and

overflow tones from the on-line side to be
connected to one set of splitting
resistors, which are connected to the
junctors. The relay operation causes
either the RST transfer alarm (0) or R6T
transfer alarm (1) scan point to saturate
in the master scanner. If both saturate,
this indicates that a relay on one of the
network frames did not transfer the tones.

2.01 A CONV OFF key on the control
panel is used to turn the battery boost
converter off and on. A lamp in the key
lights when the OFF key is depressed.
There are two keys: one for converter
and one for converter 1. Two diodes are
mounted in the base of the frame. These
allow -48 volt power to be supplied to the
load if the battery boost converters fail
or are removed.

3.01 The TELA and TELB jacks and the SP
jack are mounted on the front of the
control panel. These jacks are multiplied
together on all network frames. Any other
TELA and TELB jacks are also connected in
parallel and finally connected to the
peripheral test circuit on the test frame.
Any other SP jacks are also connected in
parallel. These jacks are used for a
general-purpose beltline. A pair of jacks
on the back of the control panel provides
-48 volt power for testing purposes.

4.01 There are three types of battery
power provided to network fraire circuits.
Signal battery is the -4 8 volt power,
provided to user circuits, which is
unfiltered after entering the frame. Talk
battery is filtered on the network frame
and then distributed to user circuits.
Boosted talk battery la talk hatt«>ry that
is boosted above the battery plant voltaqe
and is used to extend the dc-signaling

range to 1600 chirs without special per-line
treatment. Table B contains a list of
circuits and how the power supplied to them
is fused.

4.02 The LT fuse is a 0.75-A fuse which
supplies power tc the -48 volt test jack.
The MC fuse is a 0.5-A fuse which supplies
power to the CONV OFF lamps, the FA lamp,
and the PTS relay.

4.03 When any fuse supplying power to
the 15A remreed grids blows, the FAA relay
operates. This lights the FA lamp in the
fuse panel and sends a contact closure to
the line-attending-element fuse alarm scan
point in the iraster scanner iratrix circuit.

4.04 When any other fuse blows, the FAB
relay operates and also lights the FA lamp.
A contact closure is sent to the trunks,
junctors, and service circuits common fuse
alarm scan point.

4.05 Both the
no ise- suppr ession
coils. Pesistors
bus and -48E bus
fuse on each bu
both relays, but
battery boost fus
Thus, additional
buses separate an
separate froir the

3.01, This circuit shows the
interconnection of all circuits on the
network frame and the connections to any
other circuits on other frames.

4.01 When these circuits are listed on
the keysheets, the connecting information
thereon is to be followed.

5.02 The manufacturing testing
requirements are specified in the x-79037
specification.

6.01 Information for taking any circuit
on this frame out-of-service is found in
IM-3H000 and OM-3H000.

Electronic Switching Systems, No. 3, Network Frame Circuit