| log_id,tool_name,verilog_files,severity,line_num,log_line,issue_type,module,net,timing_wns,timing_tns,has_timing_violation,fix_hint | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",ERROR,32,"[ERROR] ERROR: routing congestion overflow in region (450,600)-(550,700), overflow=18",ROUTING_CONGESTION,,,,,False,Reduce placement density or add routing blockage in congested region | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",ERROR,45,WNS: -0.85 worst negative slack,TIMING_VIOLATION,adder,,-0.85,-4.23,True,Add pipeline register between adder stages or upsize driver cells on critical path | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",ERROR,52,"[ERROR] FATAL: timing closure failed, 4 paths violate constraints",TIMING_CLOSURE_FAIL,,,-0.85,-4.23,True,Run incremental ECO timing optimization or relax clock constraint | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",ERROR,58,"[ERROR] ERROR: metal spacing violation at (324, 512), layer M2, required=0.14um actual=0.10um",DRC_METAL_SPACING,,,,,False,"Increase spacing between metal traces at coordinates (324,512) on M2 layer" | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",WARNING,65,"[WARNING] WARNING: multi-driven net_reset_sync driven by 2 drivers: rst_gen/out, por_cell/rst",MULTIDRIVEN,,net_reset_sync,,,False,Use OR gate or MUX to combine reset sources; remove one duplicate driver | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",WARNING,70,"[WARNING] CAUTION: latch inferred unexpected in module arbitrator, signal grant_r",LATCH_INFERRED,arbitrator,,,,False,Add default assignment to grant_r or use always_ff with full condition coverage | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",ERROR,75,[ERROR] ERROR: combinational loop detected in module scheduler: path req->grant->req,COMBINATIONAL_LOOP,scheduler,,,,False,Break combinational loop by inserting a register on the req->grant->req path | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",WARNING,22,[WARNING] WARNING: placement density 0.92 exceeds recommended 0.80,PLACEMENT_DENSITY,,,,,False,Increase die area or reduce cell count to bring placement density below 0.80 | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",WARNING,28,[WARNING] WARNING: clock skew 120ps exceeds target 50ps on path clk_div2,CLOCK_SKEW,,clk_div2,,,False,Rebalance clock tree buffers on clk_div2 path to reduce skew below 50ps | |
| openroad_001,OpenROAD,"['top_chip.v', 'alu.v', 'controller.v', 'fsm.v', 'multiplier.v']",WARNING,80,[WARNING] WARNING: IR drop 85mV on power domain VDD_CORE exceeds limit 50mV,IR_DROP,,VDD_CORE,,,False,Add power straps or increase VDD_CORE rail width to reduce IR drop below 50mV | |
| test_log_001,OpenROAD,"['top.v', 'alu.v']",ERROR,1,[ERROR] WNS: -0.42 Timing violation detected in module adder,TIMING_VIOLATION,adder,,-0.42,,True,Upsize drive strength on critical path cells in adder module | |
| test_log_001,OpenROAD,"['top.v', 'alu.v']",ERROR,4,FATAL: latch inferred unexpected in module fsm,LATCH_INFERRED,fsm,,,,False,Add default case or else branch in FSM always block | |
| test_log_001,OpenROAD,"['top.v', 'alu.v']",WARNING,2,[WARNING] multi-driven net_data_bus found at file top.v line 42,MULTIDRIVEN,,net_data_bus,,,False,Identify and remove duplicate driver on net_data_bus at top.v:42 | |
| test_log_001,OpenROAD,"['top.v', 'alu.v']",WARNING,5,[WARNING] TNS: -1.23 total negative slack,TIMING_VIOLATION,,,,-1.23,False,Run global timing optimization to fix all negative slack paths | |