sample_eda_logs.jsonl

{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "ERROR", "line_num": 32, "log_line": "[ERROR] ERROR: routing congestion overflow in region (450,600)-(550,700), overflow=18", "issue_type": "ROUTING_CONGESTION", "module": null, "net": null, "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Reduce placement density or add routing blockage in congested region"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "ERROR", "line_num": 45, "log_line": "WNS: -0.85 worst negative slack", "issue_type": "TIMING_VIOLATION", "module": "adder", "net": null, "timing_wns": -0.85, "timing_tns": -4.23, "has_timing_violation": true, "fix_hint": "Add pipeline register between adder stages or upsize driver cells on critical path"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "ERROR", "line_num": 52, "log_line": "[ERROR] FATAL: timing closure failed, 4 paths violate constraints", "issue_type": "TIMING_CLOSURE_FAIL", "module": null, "net": null, "timing_wns": -0.85, "timing_tns": -4.23, "has_timing_violation": true, "fix_hint": "Run incremental ECO timing optimization or relax clock constraint"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "ERROR", "line_num": 58, "log_line": "[ERROR] ERROR: metal spacing violation at (324, 512), layer M2, required=0.14um actual=0.10um", "issue_type": "DRC_METAL_SPACING", "module": null, "net": null, "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Increase spacing between metal traces at coordinates (324,512) on M2 layer"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "WARNING", "line_num": 65, "log_line": "[WARNING] WARNING: multi-driven net_reset_sync driven by 2 drivers: rst_gen/out, por_cell/rst", "issue_type": "MULTIDRIVEN", "module": null, "net": "net_reset_sync", "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Use OR gate or MUX to combine reset sources; remove one duplicate driver"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "WARNING", "line_num": 70, "log_line": "[WARNING] CAUTION: latch inferred unexpected in module arbitrator, signal grant_r", "issue_type": "LATCH_INFERRED", "module": "arbitrator", "net": null, "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Add default assignment to grant_r or use always_ff with full condition coverage"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "ERROR", "line_num": 75, "log_line": "[ERROR] ERROR: combinational loop detected in module scheduler: path req->grant->req", "issue_type": "COMBINATIONAL_LOOP", "module": "scheduler", "net": null, "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Break combinational loop by inserting a register on the req->grant->req path"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "WARNING", "line_num": 22, "log_line": "[WARNING] WARNING: placement density 0.92 exceeds recommended 0.80", "issue_type": "PLACEMENT_DENSITY", "module": null, "net": null, "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Increase die area or reduce cell count to bring placement density below 0.80"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "WARNING", "line_num": 28, "log_line": "[WARNING] WARNING: clock skew 120ps exceeds target 50ps on path clk_div2", "issue_type": "CLOCK_SKEW", "module": null, "net": "clk_div2", "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Rebalance clock tree buffers on clk_div2 path to reduce skew below 50ps"}
{"log_id": "openroad_001", "tool_name": "OpenROAD", "verilog_files": ["top_chip.v", "alu.v", "controller.v", "fsm.v", "multiplier.v"], "severity": "WARNING", "line_num": 80, "log_line": "[WARNING] WARNING: IR drop 85mV on power domain VDD_CORE exceeds limit 50mV", "issue_type": "IR_DROP", "module": null, "net": "VDD_CORE", "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Add power straps or increase VDD_CORE rail width to reduce IR drop below 50mV"}
{"log_id": "test_log_001", "tool_name": "OpenROAD", "verilog_files": ["top.v", "alu.v"], "severity": "ERROR", "line_num": 1, "log_line": "[ERROR] WNS: -0.42 Timing violation detected in module adder", "issue_type": "TIMING_VIOLATION", "module": "adder", "net": null, "timing_wns": -0.42, "timing_tns": null, "has_timing_violation": true, "fix_hint": "Upsize drive strength on critical path cells in adder module"}
{"log_id": "test_log_001", "tool_name": "OpenROAD", "verilog_files": ["top.v", "alu.v"], "severity": "ERROR", "line_num": 4, "log_line": "FATAL: latch inferred unexpected in module fsm", "issue_type": "LATCH_INFERRED", "module": "fsm", "net": null, "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Add default case or else branch in FSM always block"}
{"log_id": "test_log_001", "tool_name": "OpenROAD", "verilog_files": ["top.v", "alu.v"], "severity": "WARNING", "line_num": 2, "log_line": "[WARNING] multi-driven net_data_bus found at file top.v line 42", "issue_type": "MULTIDRIVEN", "module": null, "net": "net_data_bus", "timing_wns": null, "timing_tns": null, "has_timing_violation": false, "fix_hint": "Identify and remove duplicate driver on net_data_bus at top.v:42"}
{"log_id": "test_log_001", "tool_name": "OpenROAD", "verilog_files": ["top.v", "alu.v"], "severity": "WARNING", "line_num": 5, "log_line": "[WARNING] TNS: -1.23 total negative slack", "issue_type": "TIMING_VIOLATION", "module": null, "net": null, "timing_wns": null, "timing_tns": -1.23, "has_timing_violation": false, "fix_hint": "Run global timing optimization to fix all negative slack paths"}