severity: WARNING

buggy_snippet:
always @(*) begin
  if (sel == 2'b00) out = a;
  else if (sel == 2'b01) out = b;
end

fixed_snippet:
always @(*) begin
  case (sel)
    2'b00: out = a;
    2'b01: out = b;
    default: out = '0;
  endcase
end

description: Incomplete if-else in combinational always block infers latch on out

fix_patch: Replace if-else with case statement and add default branch

tool: OpenROAD


buggy_snippet:
assign net_reset_sync = rst_gen_out;
assign net_reset_sync = por_cell_rst;

fixed_snippet: assign net_reset_sync = rst_gen_out | por_cell_rst;

description: Two concurrent assign statements drive the same net causing contention

fix_patch: Merge drivers using OR gate into single assign statement


severity: ERROR

buggy_snippet:
always @(posedge clk) begin
  sum <= a + b + c + d + e + f;
end

fixed_snippet:
always @(posedge clk) begin
  stage1 <= a + b;
  stage2 <= c + d;
  stage3 <= e + f;
end
always @(posedge clk) begin
  sum <= stage1 + stage2 + stage3;
end

description: Deep combinational path in single-cycle adder causes WNS violation

fix_patch: Pipeline the adder across two clock cycles using intermediate registers


buggy_snippet:
assign grant = req & ~busy;
assign busy  = grant & processing;

fixed_snippet:
always @(posedge clk) begin
  grant <= req & ~busy;
end
assign busy = grant & processing;

description: Combinational feedback loop: req->grant->busy->grant

fix_patch: Register the grant signal to break the combinational loop


buggy_snippet:
always @(posedge clk_fast) begin
  data_out <= data_in_slow;
end

fixed_snippet:
reg data_sync1, data_sync2;
always @(posedge clk_fast) begin
  data_sync1 <= data_in_slow;
  data_sync2 <= data_sync1;
end
assign data_out = data_sync2;

description: Direct sampling of slow-domain signal in fast-domain without synchronizer

fix_patch: Insert 2-flop synchronizer chain between clock domains


buggy_snippet:
module controller(
  input clk,
  input rst,
  input clk_en
);
always @(posedge clk) begin
  if (!rst) state <= IDLE;
end

fixed_snippet:
module controller(
  input clk,
  input rst,
  input clk_en
);
always @(posedge clk) begin
  if (!rst) state <= IDLE;
  else if (clk_en) state <= next_state;
end

description: Input port clk_en declared but never used in logic

fix_patch: Use clk_en as clock enable condition in always block