File size: 17,195 Bytes
b604cbf |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 |
[
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 11,
"question": "Consider the two-dimensional vector field 𝐹⃗(𝑥,𝑦)=𝑥 𝚤⃗+𝑦 𝚥⃗, where 𝚤⃗ and 𝚥⃗ denote the unit vectors along the 𝑥-axis and the 𝑦-axis, respectively. A contour 𝐶 in the 𝑥-𝑦 plane, as shown in the figure, is composed of two horizontal lines connected at the two ends by two semicircular arcs of unit radius. The contour is traversed in the counter-clockwise sense. The value of the closed path integral is _________",
"options": [
"0",
"1",
"8 + 2𝞹",
"-1"
],
"answer": 0,
"image_png": "ec_question_11.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 13,
"question": "The current 𝐼 in the circuit shown is ________.",
"options": [
"1.25×10⁻³ A",
"0.75×10⁻³ A",
"−0.5×10⁻³ A",
"1.16×10⁻³ A"
],
"answer": 1,
"image_png": "ec_question_13.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 14,
"question": "Consider the circuit shown in the figure. The current 𝐼 flowing through the 10 Ω resistor is _________.",
"options": [
"1 A",
"0 A",
"0.1 A",
"-0.1 A"
],
"answer": 1,
"image_png": "ec_question_14.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 18,
"question": "Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width (𝑊) to gate length (𝐿) ratios (𝑊/𝐿) of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is -1 V and the mobility of holes is 40 cm²/V.s . For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is 300 cm²/V.s . The steady state output voltage 𝑉ₒ is ________.",
"options": [
"equal to 0 V",
"more than 2 V",
"less than 2 V",
"equal to 2V"
],
"answer": 2,
"image_png": "ec_question_18.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 19,
"question": "Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for 𝐴₀, 𝐴₁, 𝐴₂, and 𝐴₃ are ____________.",
"options": [
"𝐴₀ = 0, 𝐴₁ = 0, 𝐴₂ = 1, and 𝐴₃ = 1",
"𝐴₀ = 1, 𝐴₁ = 0, 𝐴₂ = 1, and 𝐴₃ = 0",
"𝐴₀ = 0, 𝐴₁ = 1, 𝐴₂ = 1, and 𝐴₃ = 0",
"𝐴₀ = 1, 𝐴₁ = 1, 𝐴₂ = 0, and 𝐴₃ = 0"
],
"answer": 2,
"image_png": "ec_question_19.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 20,
"question": "The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and −1 V, respectively. The MOSFET substrates are connected to their respective sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are _________________.",
"options": [
"V₁ = 5V, V₂ = 5V",
"V₁ = 5V, V₂ = 4V",
"V₁ = 4V, V₂ = 5V",
"V₁ = 4V, V₂ = -5V"
],
"answer": 2,
"image_png": "ec_question_20.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 21,
"question": "Consider a closed-loop control system with unity negative feedback and 𝐾𝐺(𝑠) in the forward path, where the gain 𝐾=2. The complete Nyquist plot of the transfer function 𝐺(𝑠) is shown in the figure. Note that the Nyquist contour has been chosen to have the clockwise sense. Assume 𝐺(𝑠) has no poles on the closed right-half of the complex plane. The number of poles of the closed-loop transfer function in the closed right-half of the complex plane is ___________.",
"options": [
"0",
"1",
"2",
"3"
],
"answer": 2,
"image_png": "ec_question_21.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 22,
"question": "The root-locus plot of a closed-loop system with unity negative feedback and transfer function 𝐾𝐺(𝑠) in the forward path is shown in the figure. Note that 𝐾 is varied from 0 to ∞. Select the transfer function 𝐺(𝑠) that results in the root-locus plot of the closed-loop system as shown in the figure.",
"options": [
"𝐺(𝑠) = 1/(𝑠 + 1)⁵",
"𝐺(𝑠) = 1/(𝑠⁵ + 1)",
"𝐺(𝑠) = (𝑠 - 1)/(𝑠 + 1)⁶",
"𝐺(𝑠) = (𝑠 + 1)/(𝑠⁶ + 1)"
],
"answer": 0,
"image_png": "ec_question_22.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 23,
"question": "The frequency response 𝐻(𝑓) of a linear time-invariant system has magnitude as shown in the figure. Statement I: The system is necessarily a pure delay system for inputs which are bandlimited to −𝛼≤𝑓≤𝛼. Statement II: For any wide-sense stationary input process with power spectral density 𝑆H(𝑓), the output power spectral density 𝑆H(𝑓) obeys 𝑆H(𝑓)=𝑆H(𝑓) for −𝛼≤𝑓≤𝛼. Which one of the following combinations is true?",
"options": [
"Statement I is correct, Statement II is correct",
"Statement I is correct, Statement II is incorrect",
"Statement I is incorrect, Statement II is correct",
"Statement I is incorrect, Statement II is incorrect"
],
"answer": 2,
"image_png": "ec_question_23.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 38,
"question": "For the circuit shown, the locus of the impedance 𝑍(𝑗𝜔) is plotted as 𝜔 increases from zero to infinity. The values of 𝑅₁ and 𝑅₂ are:",
"options": [
"𝑅₁=2 kΩ, 𝑅₂=3 kΩ",
"𝑅₁=5 kΩ, 𝑅₂=2 kΩ",
"𝑅₁=5 kΩ, 𝑅₂=2.5 kΩ",
"𝑅₁=2 kΩ, 𝑅₂=5 kΩ"
],
"answer": 0,
"image_png": "ec_question_38.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 39,
"question": "Consider the circuit shown in the figure with input 𝑉(𝑡) in volts. The sinusoidal steady state current 𝐼(𝑡) flowing through the circuit is shown graphically (where 𝑡 is in seconds). The circuit element 𝑍 can be ________.",
"options": [
"a capacitor of 1 F",
"an inductor of 1 H",
"a capacitor of √3 F",
"an inductor of √3 H"
],
"answer": 1,
"image_png": "ec_question_39.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 41,
"question": "For the following circuit with an ideal OPAMP, the difference between the maximum and the minimum values of the capacitor voltage (𝑉꜀) is __________.",
"options": [
"15 V",
"27 V",
"13 V",
"14 V"
],
"answer": 2,
"image_png": "ec_question_41.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 42,
"question": "A circuit with an ideal OPAMP is shown. The Bode plot for the magnitude (in dB) of the gain transfer function (𝐴ᵥ(𝑗𝜔)=𝑉ₒᵤₜ (𝑗𝜔)/𝑉ᵢₙ(𝑗𝜔)) of the circuit is also provided (here, 𝜔 is the angular frequency in rad/s). The values of 𝑅 and 𝐶 are ____________.",
"options": [
"𝑅=3 kΩ, 𝐶=1 𝜇F",
"𝑅=1 kΩ, 𝐶=3 𝜇F",
"𝑅=4 kΩ, 𝐶=1 𝜇F",
"𝑅=3 kΩ, 𝐶=2 𝜇F"
],
"answer": 0,
"image_png": "ec_question_42.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
},
{
"language": "en",
"country": "India",
"file_name": "ec_2022.pdf",
"source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/ec_2022.pdf",
"license": "Education and Research",
"level": "Graduate Aptitude Test in Engineering (GATE)",
"category_en": "Electronics and Communications Engineering",
"category_original_lang": "इलेक्ट्रॉनिक्स और संचार इंजीनियरिंग",
"original_question_num": 43,
"question": "For the circuit shown, the clock frequency is 𝑓ₒ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, _______.",
"options": [
"frequency is 𝑓ₒ/4 and duty cycle is 50%",
"frequency is 𝑓ₒ/4 and duty cycle is 25%",
"frequency is 𝑓ₒ/2 and duty cycle is 50%",
"frequency is 𝑓ₒ and duty cycle is 25%"
],
"answer": 0,
"image_png": "ec_question_43.png",
"image_information": "essential",
"image_type": "diagram",
"parallel_question_id": null
}
] |