[ { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 19, "question": "The figure shows a Chromel-Alumel thermocouple, where the junction A is held at temperature 𝑇, and a thermal emf 𝐸 is measured using an ideal voltmeter between the open ends B1 and B2, both held at temperature 𝑇 . Two identical copper wires are introduced between B1-C1 and B2-C2 as shown in the figure. When C1 and C2 are held at temperature 𝑇, the voltmeter reads a thermal emf 𝐸. Then, ________", "options": [ "𝐸₁ < 𝐸₂", "𝐸₁ > 𝐸₂", "𝐸₁ = 2E₂", "𝐸₁ = 𝐸₂" ], "answer": 3, "image_png": "in_question_19.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 21, "question": "The logic block shown has an output 𝐹 given by ________", "options": [ "A + B", "A.B'", "A + B'", "B'" ], "answer": 3, "image_png": "in_question_21.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 36, "question": "A signal 𝑉 (𝑡) shown is applied from 𝑡=0 ms to 𝑡=6 ms to the circuit shown. Given the initial voltage across the capacitor is 0.3 V, and that the diode is ideal, the open circuit voltage 𝑉 (𝑡) at 𝑡=5 ms is ________", "options": [ "0.3 V", "0.6 V", "0.7 V", "1.0 V" ], "answer": 3, "image_png": "in_question_36.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 37, "question": "The signal flow graph of a system is shown. The expression for 𝑌(𝑠)/𝑋(𝑠) is ________", "options": [ "A", "B", "C", "D" ], "answer": 0, "image_png": "in_question_37.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 42, "question": "A resistor ladder digital-to-analog converter (DAC) receives a digital input that results in the circuit having the state as shown in the figure. For this digital input, the Thevenin voltage, 𝑉 , and Thevenin resistance, 𝑅 , as seen at the output node are ________", "options": [ "𝑉ₜₕ = 0.5 V, 𝑅ₜₕ = 1 kΩ", "𝑉ₜₕ = 0.5 V, 𝑅ₜₕ = 2 kΩ", "𝑉ₜₕ = 1 V, 𝑅ₜₕ = 1 kΩ", "𝑉ₜₕ = 1 V, 𝑅ₜₕ = 2 kΩ" ], "answer": 2, "image_png": "in_question_42.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 43, "question": "The Nyquist plot of a stable open-loop system 𝐺(𝑗𝜔) is plotted in the frequency range 0≤𝜔<∞ as shown. It is found to intersect a unit circle with center at the origin at the point 𝑃=−0.77−0.64𝑗 . The points 𝑄 and 𝑅 lie on 𝐺(𝑗𝜔) and assume values 𝑄=14.40+0.00𝑗 and 𝑅=−0.21+0.00𝑗. The phase margin (PM) and the gain margin (GM) of the system are ________", "options": [ "PM = 39.7° and GM = 4.76", "PM = 39.7° and GM = 0.07", "PM = ‒39.7° and GM = 4.76", "PM = ‒39.7° and GM = 0.07" ], "answer": 0, "image_png": "in_question_43.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 44, "question": "In the small signal circuit shown, the enhancement mode n-channel MOSFET is biased in saturation with transconductance 𝑔 . If channel length modulation is ignored, the small signal impedance looking into the node P is given by ________", "options": [ "Rₛ || Rₗ || gₘ⁻¹", "Rₛ || gₘ⁻¹", "(Rₛ + Rₗ) || gₘ⁻¹", "(Rₗgₘ / (1 + Rₛgₘ)) * (Rₗ || gₘ⁻¹)" ], "answer": 1, "image_png": "in_question_44.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 46, "question": "The digital circuit shown ________", "options": [ "is a divide-by-5 counter", "is a divide-by-7 counter", "is a divide-by-8 counter", "does not function as a counter due to disjoint cycles of states" ], "answer": 0, "image_png": "in_question_46.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null }, { "language": "en", "country": "India", "file_name": "in_2022.pdf", "source": "https://gate.iitkgp.ac.in/documents/gatepapers/2022/in_2022.pdf", "license": "Education and Research", "level": "Graduate Aptitude Test in Engineering (GATE)", "category_en": "Instrumentation Engineering", "category_original_lang": "इंस्ट्रुमेंटेशन इंजीनियरिंग", "original_question_num": 47, "question": "In the small signal circuit shown, the enhancement mode n-channel MOSFET is biased in saturation with a transconductance 𝑔 . A small signal low-frequency voltage 𝑣 injected at the supply terminal results in a small signal voltage fluctuation 𝑣 at the output. If the channel length modulation of the MOSFET is ignored, the small signal gain 𝑣 /𝑣 is given by ________", "options": [ "-gₘR₀ / (1 + gₘR₀)", "(1 + gₘR₀)⁻¹", "-gₘR₀ / (1 + 2gₘR₀)", "(gₘR₀/2 + 3/2)⁻¹" ], "answer": 3, "image_png": "in_question_47.png", "image_information": "essential", "image_type": "diagram", "parallel_question_id": null } ]