repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
9fans/vx32
| 1,908
|
src/libvxc/msun/x87/s_finite.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(finite)
movl 8(%esp),%eax
andl $0x7ff00000, %eax
cmpl $0x7ff00000, %eax
setneb %al
andl $0x000000ff, %eax
ret
|
9fans/vx32
| 1,889
|
src/libvxc/msun/x87/e_fmod.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(__ieee754_fmod)
fldl 12(%esp)
fldl 4(%esp)
1: fprem
fstsw %ax
sahf
jp 1b
fstp %st(1)
ret
|
9fans/vx32
| 1,895
|
src/libvxc/msun/x87/e_remainder.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(__ieee754_remainder)
fldl 12(%esp)
fldl 4(%esp)
1: fprem1
fstsw %ax
sahf
jp 1b
fstp %st(1)
ret
|
9fans/vx32
| 1,835
|
src/libvxc/msun/x87/e_sqrt.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(__ieee754_sqrt)
fldl 4(%esp)
fsqrt
ret
|
9fans/vx32
| 1,990
|
src/libvxc/msun/x87/s_tan.S
|
/*
* Copyright (c) 1994 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(tan)
fldl 4(%esp)
fptan
fnstsw %ax
andw $0x400,%ax
jnz 1f
fstp %st(0)
ret
1: fldpi
fadd %st(0)
fxch %st(1)
2: fprem1
fstsw %ax
andw $0x400,%ax
jnz 2b
fstp %st(1)
fptan
fstp %st(0)
ret
|
9fans/vx32
| 1,862
|
src/libvxc/msun/x87/e_scalb.S
|
/*
* Copyright (c) 1994 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(__ieee754_scalb)
fldl 12(%esp)
fldl 4(%esp)
fscale
fstp %st(1)
ret
|
9fans/vx32
| 3,027
|
src/libvxc/msun/x87/e_exp.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
/* e^x = 2^(x * log2(e)) */
ENTRY(__ieee754_exp)
/*
* If x is +-Inf, then the subtraction would give Inf-Inf = NaN.
* Avoid this. Also avoid it if x is NaN for convenience.
*/
movl 8(%esp),%eax
andl $0x7fffffff,%eax
cmpl $0x7ff00000,%eax
jae x_Inf_or_NaN
fldl 4(%esp)
/*
* Ensure that the rounding mode is to nearest (to give the smallest
* possible fraction) and that the precision is as high as possible.
* We may as well mask interrupts if we switch the mode.
*/
fstcw 4(%esp)
movl 4(%esp),%eax
andl $0x0300,%eax
cmpl $0x0300,%eax /* RC == 0 && PC == 3? */
je 1f /* jump if mode is good */
movl $0x137f,8(%esp)
fldcw 8(%esp)
1:
fldl2e
fmulp /* x * log2(e) */
fst %st(1)
frndint /* int(x * log2(e)) */
fst %st(2)
fsubrp /* fract(x * log2(e)) */
f2xm1 /* 2^(fract(x * log2(e))) - 1 */
fld1
faddp /* 2^(fract(x * log2(e))) */
fscale /* e^x */
fstp %st(1)
je 1f
fldcw 4(%esp)
1:
ret
x_Inf_or_NaN:
/*
* Return 0 if x is -Inf. Otherwise just return x, although the
* C version would return (x + x) (Real Indefinite) if x is a NaN.
*/
cmpl $0xfff00000,8(%esp)
jne x_not_minus_Inf
cmpl $0,4(%esp)
jne x_not_minus_Inf
fldz
ret
x_not_minus_Inf:
fldl 4(%esp)
ret
|
9fans/vx32
| 1,964
|
src/libvxc/msun/x87/s_cos.S
|
/*
* Copyright (c) 1994 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(cos)
fldl 4(%esp)
fcos
fnstsw %ax
andw $0x400,%ax
jnz 1f
ret
1: fldpi
fadd %st(0)
fxch %st(1)
2: fprem1
fnstsw %ax
andw $0x400,%ax
jnz 2b
fstp %st(1)
fcos
ret
|
9fans/vx32
| 1,464
|
src/libvxc/msun/x87/s_lrint.S
|
/*-
* Copyright (c) 2005 David Schultz <das@FreeBSD.ORG>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <asm.h>
ENTRY(lrint)
fldl 4(%esp)
subl $4,%esp
fistpl (%esp)
popl %eax
ret
|
9fans/vx32
| 1,940
|
src/libvxc/msun/x87/s_copysign.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(copysign)
movl 16(%esp),%edx
andl $0x80000000,%edx
movl 8(%esp),%eax
andl $0x7fffffff,%eax
orl %edx,%eax
movl %eax,8(%esp)
fldl 4(%esp)
ret
|
9fans/vx32
| 1,963
|
src/libvxc/msun/x87/s_sin.S
|
/*
* Copyright (c) 1994 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(sin)
fldl 4(%esp)
fsin
fnstsw %ax
andw $0x400,%ax
jnz 1f
ret
1: fldpi
fadd %st(0)
fxch %st(1)
2: fprem1
fnstsw %ax
andw $0x400,%ax
jnz 2b
fstp %st(1)
fsin
ret
|
9fans/vx32
| 2,140
|
src/libvxc/msun/x87/s_ceil.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(ceil)
pushl %ebp
movl %esp,%ebp
subl $8,%esp
fstcw -4(%ebp) /* store fpu control word */
movw -4(%ebp),%dx
orw $0x0800,%dx /* round towards +oo */
andw $0xfbff,%dx
movw %dx,-8(%ebp)
fldcw -8(%ebp) /* load modfied control word */
fldl 8(%ebp); /* round */
frndint
fldcw -4(%ebp) /* restore original control word */
leave
ret
|
9fans/vx32
| 1,827
|
src/libvxc/msun/x87/s_rint.S
|
/*
* Copyright (c) 1993,94 Winning Strategies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Winning Strategies, Inc.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Written by:
* J.T. Conklin (jtc@wimsey.com), Winning Strategies, Inc.
*/
#include <asm.h>
ENTRY(rint)
fldl 4(%esp)
frndint
ret
|
9fans/vx32
| 1,477
|
src/libvxc/msun/x87/s_llrint.S
|
/*-
* Copyright (c) 2005 David Schultz <das@FreeBSD.ORG>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <asm.h>
ENTRY(llrint)
fldl 4(%esp)
subl $8,%esp
fistpll (%esp)
popl %eax
popl %edx
ret
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_flash/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
9fans/plan9port
| 23,530
|
tmac/tmac.s
|
.lg 0
.ds sd #9/tmac
.\" RT - reset everything to normal state
.de RT
.if \\n(CS \{\
.SR 1
.BG\}
.if !\\n(1T .BG
.ce 0
.if !\\n(IK .if !\\n(IF .if !\\n(IX .if !\\n(BE .if !\\n(FT .di
.ul 0
.if \\n(QP \{\
. ll +\\n(QIu
. in -\\n(QIu
. nr QP -1\}
.if \\n(NX<=1 .if \\n(AJ=0 .if \\n(FT=0 .ll \\n(LLu
.if !\\n(IF \{\
. ps \\n(PS
. ie \\n(VS>=41 .vs \\n(VSu
. el .vs \\n(VSp\}
.ie \\n(IP \{\
. in \\n(I\\n(IRu
. nr IP -1\}
.el .if !\\n(IR \{\
. nr I1 \\n(PIu
. nr I2 0
. nr I3 0
. nr I4 0
. nr I5 0\}
.ft 1
.ta 5n 10n 15n 20n 25n 30n 35n 40n 45n 50n 55n 60n 65n 70n 75n 80n
.hy \\n(HY
.fi
..
. \"IZ - initialization
.de IZ
.so \\*(sd/tmac.sdisp
.nr TN 0
.em EM
. \" ACCENTS say \*'e or \*`e to get e acute or e grave both were 4/10
.ds ' \h'\w'e'u*1/10'\z\(aa\h'-\w'e'u*1/10'
.ds ` \h'\w'e'u*2/10'\z\(ga\h'-\w'e'u*2/10'
. \" UMLAUT \*:u, etc.
.if t .ds : \\v'-0.6m'\\h'(1u-(\\\\n(.fu%2u))*0.13m+0.00m'\\z.\\h'0.2m'\\z.\\h'-((1u-(\\\\n(.fu%2u))*0.13m+0.20m)'\\v'0.6m'
.if n .ds : \z"
. \" TILDE and CIRCUMFLEX
.ds ^ \\\\k:\\h'-\\\\n(.fu+1u/2u*2u+\\\\n(.fu-1u*0.13m+0.06m'\\z^\\h'|\\\\n:u'
.ds ~ \\\\k:\\h'-\\\\n(.fu+1u/2u*2u+\\\\n(.fu-1u*0.13m+0.06m'\\z~\\h'|\\\\n:u'
. \" czech v symbol
.ds v \\\\k:\\\\h'+\\\\w'e'u/4u'\\\\v'-0.6m'\\\\s6v\\\\s0\\\\v'0.6m'\\\\h'|\\\\n:u'
. \" cedilla
.ds , \\\\k:\\\\h'\\\\w'c'u*0.4u'\\\\z,\\\\h'|\\\\n:u'
.so \\*(sd/tmac.srefs
.ch FO \\n(YYu
.if !\\n(FM .nr FM 1i
.nr YY -\\n(FMu
.nr XX 0 1
.nr IP 0
.nr PI 5n
.nr QI 5n
.nr I0 \\n(PIu
.nr PS 10
.nr VS 12
.nr HY 14
.ie n \{\
. if !\\n(PD .nr PD 1v
. nr DV 1v\}
.el \{\
. if !\\n(PD .nr PD 0.3v
. nr DV .5v\}
.nr ML 3v
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.nr IR 0
.nr I0 0
.nr I1 \\n(PIu
.nr TB 0
.nr SJ \\n(.j
.nr LL 6i
.ll \\n(LLu
.nr LT \\n(.l
.lt \\n(LTu
.ev 1
.if !\\n(FL .nr FL \\n(LLu*11u/12u
.ll \\n(FLu
.ps 8
.vs 10p
.ev
.if \\*(CH .ds CH "\(hy \\\\n(PN \(hy
.wh 0 NP
.wh -\\n(FMu FO
.ch FO 16i
.wh -\\n(FMu FX
.ch FO -\\n(FMu
.if t .wh -\\n(FMu/2u BT
.if n .wh -\\n(FMu/2u-1v BT
. \" no overstriking bold or italic; switch underlining to bold italic
. \" (sad historical botch, the .uf font must be 2, 3, or 4)
.if n .uf 4
.if n .bd 3
.nr CW 0-1
.nr GW 0-1
..
.de TM
.if !\\n(IM .if !\\n(MN .pn 0
.so \\*(sd/tmac.scover
.if !\\n(IM .if !\\n(MN .rm IM MF MR
.if n .if !\\n(.T .pi /usr/bin/col
.nr ST 1
.ds QF TECHNICAL MEMORANDUM
.br
.ds MN \\$1
.if !"\\$1"" .nr MM 1
.if !"\\$2"" .nr MC 1
.if !"\\$3"" .nr MG 1
.nr TN 1
.if \\n(.$-1 .ds CA \\$2
.if \\n(.$-2 .ds CC \\$3
.rm RP S0 S2 AX
..
. \" IM - internal memorandum
.de IM
.nr IM 1
.TM "\\$1" "\\$2" "\\$3"
.rm QF
.RA
.rm RA RP MF MR
..
. \" MF - memorandum for file.
.de MF
.nr MN 1
.TM "\\$1" "\\$2" "\\$3"
.rm MR
.rm IM
.RA
.rm RA RP TM
..
. \" MR - memo for record
.de MR
.nr MN 2
.TM "\\$1" "\\$2" "\\$3"
.ds QF MEMORANDUM FOR RECORD
.rm MF
.RA
.rm RA RP IM TM
..
. \" LT - letter
.de LT
.if !\\n(PO .ie n .nr PO 1.5i
.el .nr PO 1.3i
.po \\n(POu
.LP
.rs
.if !"\\$1"" \{\
. vs -2p
.if "\\$1"LT" .ta 3.9i 4.45i
.if !"\\$1"LT" .ta 3.9i 4.45i
. sp .2i
. nf
. if "\\$1"LT" \s36\(FA\s0
. if !"\\$1"LT" \s36\(LH\s0
. br
\s7\l'7i'\s0
.sp
. br
. if !"\\$2"" .ds xR " \\$2
. ds xP 908-582-3000
. if !"\\$3"" .ds xP \\$3
. if "\\$1"LT" \s8\f(HBBell Laboratories\fP \fH600 Mountain Avenue
. if !"\\$1"LT" \s8\f(HBBell Laboratories\fP \fH600 Mountain Avenue
. if !"\\$2"" \\*(xR
Murray Hill, NJ 07974-0636
\\*(xP
. if !"\\$4"" \\$4
. if !"\\$5"" \\$5
. if !"\\$6"" \\$6
. if !"\\$7"" \\$7
.ft 1
.ps
. sp -.75i
. vs
. fi \}
.if n \{\
. sp 1i
. in 4.55i\}
.if t \{\
. sp 1.45i
. in 3.5i\}
.ll 8i
\\*(DY
.ll
.in 0
.br
.if t .sp 3
.if n \{\
. sp
. na\}
.nf
.rm CF
.de SG \" nested defn
.sp 2
.ta 3.5i
Sincerely,
.sp 3
\\\\$1
.ds CH
\\..
..
.de OK
.br
.di
.di OD
..
.de RP \" released paper
.nr ST 2
.pn 0
.rm SG CS TM QF IM MR MF EG
.br
..
.de TR \" Comp. Sci. Tech Rept series.
.nr ST 3
.pn 0
.ds MN \\$1
.rm SG CS TM QF IM MR M EG
.br
..
. \"FP - font position for a family
.de FP
.ds TF \\$1
.if '\\$1'palatino'\{\
. fp 1 R PA
. fp 2 I PI
. fp 3 B PB
. fp 4 BI PX\}
.if '\\$1'lucidabright'\{\
. fp 1 R LucidaBright
. fp 2 I LucidaBright-Italic
. fp 3 B LucidaBright-Demi
. fp 4 BI LucidaBright-DemiItalic
. fp 5 CW LucidaSansCW\}
.if '\\$1'lucidasans'\{\
. fp 1 R LucidaSans
. fp 2 I LucidaSansI
. fp 3 B LucidaSansB
. fp 5 CW LucidaCW\}
.if '\\$1'luxisans'\{\
. fp 1 R LuxiSans
. fp 2 I LuxiSans-Oblique
. fp 3 B LuxiSans-Bold
. fp 4 BI LuxiSans-BoldOblique
. fp 5 CW LuxiMono\}
.if '\\$1'dejavu'\{\
. fp 1 R DejaVuSerif
. fp 2 I DejaVuSerifOblique
. fp 3 B DejaVuSerifBold
. fp 4 BI DejaVuSerifBoldOblique
. fp 5 CW DejaVuMonoSans\}
.if '\\$1'dejavusans'\{\
. fp 1 R DejaVuSans
. fp 2 I DejaVuSansOblique
. fp 3 B DejaVuSansBold
. fp 4 BI DejaVuSansBoldOblique
. fp 5 CW DejaVuMonoSans\}
.if '\\$1'syntax'\{\
. fp 1 R Syntax
. fp 2 I SyntaxI
. fp 3 B SyntaxB
. fp 5 CW LucidaCW\}
.if '\\$1'century'\{\
. ie '\\*(.T'202'\{\
. fp 1 NR Centsb
. fp 2 NI CentI
. fp 3 NB CentB
. fp 4 NX CentBI\}
. el \{\
. fp 1 NR
. fp 2 NI
. fp 3 NB
. fp 4 NX\}\}
.if '\\$1'helvetica'\{\
. fp 1 H
. fp 2 HI
. fp 3 HB
. fp 4 HX\}
.if '\\$1'bembo'\{\
. ie '\\*(.T'202'\{\
. fp 1 B1 Bembo
. fp 2 B2 BemboI
. fp 3 B3 BemboB
. fp 4 B4 BemboBI\}
. el \{\
. fp 1 B1
. fp 2 B2
. fp 3 B3
. fp 4 B4\}\}
.if '\\$1'optima'\{\
. fp 1 R Optima
. fp 2 I OptimaI
. fp 3 B OptimaB
. fp 4 BI OptimaBI\}
.if '\\$1'souvenir'\{\
. fp 1 R Souvenir
. fp 2 I SouvenirI
. fp 3 B SouvenirB
. fp 4 BI SouvenirBI\}
.if '\\$1'melior'\{\
. fp 1 R Melior
. fp 2 I MeliorI
. fp 3 B MeliorB
. fp 4 BI MeliorBI\}
.if '\\$1'times'\{\
. fp 1 R
. fp 2 I
. fp 3 B
. fp 4 BI\}
..
. \"TL - title and initialization
.de TL
.br
.nr TV 1
.if \\n(IM .rm CS
.if \\n(MN .rm CS
.ME
.rm ME
.di WT
.na
.fi
.ie h .ll \\n(LLu
.el \{\
.ll 5.0i
.if n .if \\n(TN .ll 29
.if t .if \\n(TN .ll 3.5i \}
.ft 3
.ps \\n(PS
.if !\\n(TN \{\
. ps +2
. vs \\n(.s+2
. rm CS\}
.hy 0
.if h .ce 999
..
.de TX
.rs
.sp .5i
.ce 1000
.if n .ul 1000
.ps 12
.ft 3
.vs 15p
.ne 4
.hy 0
.WT
.hy \\n(HY
.ce 0
.ul 0
..
. \" AU - author(s)
.de AU
.nr AV 1
.ad \\n(SJ
.br
.di
.br
.nf
.nr NA +1
.ds R\\n(NA \\$1
.ds E\\n(NA \\$2
.di A\\n(NA
.ll \\n(LLu
.ie t \{\
. ie !\\n(TN .ft 2
. el \{\
. ft 3
. ll 1.4i\}\}
.el \{\
. ie !\\n(TN .ft 1
. el \{\
. ft 3
. ll 16\}\}
.ps \\n(PS
.if h .ce 999
..
.de AX
.ft 1
.rs
.ce 1000
.if n .ul 0
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.if t \{\
. sp
. A1
. sp 0.5
. ns
. I1
. if \\n(NA-1 .sp
. A2
. if \\n(NA-1 .sp 0.5
. ns
. I2
. if \\n(NA-2 .sp
. A3
. if \\n(NA-2 .sp 0.5
. ns
. I3
. if \\n(NA-3 .sp
. A4
. if \\n(NA-3 .sp 0.5
. ns
. I4
. if \\n(NA-4 .sp
. A5
. if \\n(NA-4 .sp 0.5
. ns
. I5
. if \\n(NA-5 .sp
. A6
. if \\n(NA-5 .sp 0.5
. ns
. I6
. if \\n(NA-6 .sp
. A7
. if \\n(NA-6 .sp 0.5
. ns
. I7
. if \\n(NA-7 .sp
. A8
. if \\n(NA-7 .sp 0.5
. ns
. I8
. if \\n(NA-8 .sp
. A9
. if \\n(NA-8 .sp 0.5
. ns
. I9\}
.if n \{\
. sp 2
. A1
. sp
. ns
. I1
. if \\n(NA-1 .sp 2
. A2
. if \\n(NA-1 .sp
. ns
. I2
. if \\n(NA-2 .sp 2
. A3
. if \\n(NA-2 .sp
. ns
. I3
. if \\n(NA-3 .sp 2
. A4
. if \\n(NA-3 .sp
. ns
. I4
. if \\n(NA-4 .sp 2
. A5
. if \\n(NA-4 .sp
. ns
. I5
. if \\n(NA-5 .sp 2
. A6
. if \\n(NA-5 .sp
. ns
. I6
. if \\n(NA-6 .sp 2
. A7
. if \\n(NA-6 .sp
. ns
. I7
. if \\n(NA-7 .sp 2
. A8
. if \\n(NA-7 .sp
. ns
. I8
. if \\n(NA-8 .sp 2
. A9
. if \\n(NA-8 .sp
. ns
. I9\}
..
. \"AI - authors institution
.de AI
.br
.ft 1
.di
.di I\\n(NA
.nf
..
. \"AB - begin an abstract
.de AB
.br
.di
.ul 0
.ce 0
.nr 1T 1
.nr IK 1
.nr KI 1
.di WB
.rs
.nr AJ 1
.ce 1
.ft 2
.if n .ul
.ll \\n(LLu
.ie \\n(.$ \{\
. if !"\\$1"-" .if !"\\$1"no" \\$1
. if !"\\$1"-" .if !"\\$1"no" .sp\}
.el \{\
ABSTRACT
.sp\}
.hy \\n(HY
.ul 0
.ce 0
.fi
.ft 1
.nr OJ \\n(.i
.in +\\n(.lu/12u
.ll -\\n(.lu/12u
.br
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.ti +\\n(PIu
..
. \"AE - end of an abstract
.de AE
.br
.di
.ll \\n(LLu
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.nr 1T 0
.nr IK 0
.in \\n(OJu
.nr AJ 0
.di
.ce 0
.if \\n(ST=2 .SY
.if \\n(ST<3 .rm SY
..
. \"S2 - release paper style
. \"SY - cover sheet of released paper
.de SY
.ll \\n(LLu
.ns
.if \\n(TV .TX
.if \\n(AV .AX
.rs
.ce 0
.nf
.sp 3
.ls 1
.pn 2
.WB
.ls
.sp 3v
\\*(DY
.sp |9i
.if \\n(FP .FA
.FG
.if \\n(GA=1 .nr GA 2
.fi
..
. \"S2 - first text page, released paper format
.de S2
.ce 0
.br
.SY
.rm SY
.bp 1
.if \\n(TV .TX
.if \\n(AV .AX
.rs
.ce 0
.ft 1
.ad \\n(SJ
..
. \"S0- mike lesk conserve paper style
.de S0
.ce 0
.br
.ll \\n(LLu
.if \\n(TV+\\n(AV .ns
.if \\n(TV .TX
.if \\n(AV .AX
.if \\n(TV+\\n(AV .rs
.ce 0
.if \\n(TV .sp 2
.ls 1
.if \\n(FP \{\
. FJ
. nf
. FG
. fi
. FK
. nr FP 0\}
.nf
.WB
.ls
.fi
.ad \\n(SJ
..
. \"S3 - CSTR style
.de S3
.rs
.sp |2.25i
.ce 1000
.I1
.if \\n(NA>1 \{\
. sp .5
. I2\}
.if \\n(NA>2 \{\
. sp .5
. I3\}
.if \\n(NA>3 \{\
. sp .5
. I4\}
.if \\n(NA>4 \{\
. sp .5
. I5\}
.if \\n(NA>5 \{\
. sp .5
. I6\}
.if \\n(NA>6 \{\
. sp .5
. I7\}
.if \\n(NA>7 \{\
. sp .5
. I8\}
.if \\n(NA>8 \{\
. sp .5
. I9\}
.sp |4i
. \"check how long title is: can space extra .25 inch if short
.di EZ
.WT
.di
.if \\n(dn<1.5v .if \\n(NA=1 .sp .25i
.ft 1
Computing Science Technical Report No. \\*(MN
.sp
.if t .ft 3
.if n .ul 100
.ps 12
.vs 15p
.hy 0
.WT
.hy \\n(HY
.ft 1
.if n .ul 0
.ps 10
.vs 12p
.sp
.ft 1
.A1
.A2
.A3
.A4
.A5
.A6
.A7
.A8
.A9
.ce 0
.sp |8.5i
.ce 0
\\*(DY
.DZ
.bp 0
.ft 1
.S2
..
. \"SG - signature
.de SG
.br
.KS
.in +2u*\\n(.lu/3u
.sp 4
.A1
.if \\n(NA>1 .sp 4
.A2
.if \\n(NA>2 .sp 4
.A3
.if \\n(NA>3 .sp 4
.A4
.if \\n(NA>4 .sp 4
.A5
.if \\n(NA>5 .sp 4
.A6
.if \\n(NA>6 .sp 4
.A7
.if \\n(NA>7 .sp 4
.A8
.if \\n(NA>8 .sp 4
.A9
.in
.nf
.if \\n(.$<1 .G9
.sp -1
.if \\n(.$>=1 \\$1
.if \\n(.$>=2 \\$2
.if \\n(.$>=3 \\$3
.if \\n(.$>=4 \\$4
.if \\n(.$>=5 \\$5
.if \\n(.$>=6 \\$6
.if \\n(.$>=7 \\$7
.if \\n(.$>=8 \\$8
.if \\n(.$>=9 \\$9
.fi
.br
.KE
..
. \"Tables. TS - table start, TE - table end
.de TS
.br
.if !\\n(1T .RT
.ul 0
.ti \\n(.iu
.if t .sp 0.5
.if n .sp
.if \\$1H .TQ
.nr IX 1
..
.de TQ
.di TT
.nr IT 1
..
.de TH
.if \\n(.d>0.5v \{\
. nr T. 0
. T# 0\}
.di
.nr TQ \\n(.i
.nr HT 1
.in 0
.mk #a
.mk #b
.mk #c
.mk #d
.mk #e
.mk #f
.TT
.in \\n(TQu
.mk #T
..
.de TE
.nr IX 0
.if \\n(IT .if !\\n(HT \{\
. di
. nr EF \\n(.u
. nf
. TT
. if \\n(EF .fi\}
.nr IT 0
.nr HT 0
.if n .sp 1
.if t .sp 0.5
.rm a+ b+ c+ d+ e+ f+ g+ h+ i+ j+ k+ l+ n+ m+
.rr 32 33 34 35 36 37 38 40 79 80 81 82
.rr a| b| c| d| e| f| g| h| i| j| k| l| m|
.rr a- b- c- d- e- f- g- h- i- j- k- l- m-
..
.so \*(sd/tmac.skeep
.de EQ \"equation, breakout and display
.nr EF \\n(.u
.rm EE
.nr LE 1 \" 1 is center
.ds EL \\$1
.if "\\$1"L" \{\
. ds EL \\$2
. nr LE 0\}
.if "\\$1"C" .ds EL \\$2
.if "\\$1"R" \{\
. ds EL \\$2 \" 2 is right adjust
. nr LE 2\}
.if "\\$1"I" \{\
. nr LE 0
. if "\\$3"" .ds EE \\h'|10n'
. el .ds EE \\h'\\$3'
. ds EL \\$2\}
.if \\n(YE .nf
.di EZ
..
.de EN \" end of a displayed equation
.br
.di
.rm EZ
.nr ZN \\n(dn
.if \\n(ZN .if !\\n(YE .LP
.if !\\n(ZN .if !"\\*(EL"" .nr ZN 1
.if \\n(ZN \{\
. ie "\\n(.z"" \{\
. if t .if !\\n(nl=\\n(PE .sp .5
. if n .if !\\n(nl=\\n(PE .sp 1\}
. el \{\
. if t .if !\\n(.d=\\n(PE .sp .5
. if n .if !\\n(.d=\\n(PE .sp 1\}\}
'pc
.if \\n(BD .nr LE 0 \" don't center if block display or mark/lineup
.if \\n(MK \{\
. if \\n(LE=1 .ds EE \\h'|10n'
. nr LE 0\}
'lt \\n(.lu
.if !\\n(EP .if \\n(ZN \{\
. if \\n(LE=1 .tl \(ts\(ts\\*(10\(ts\\*(EL\(ts
. if \\n(LE=2 .tl \(ts\(ts\(ts\\*(10\\*(EL\(ts
. if !\\n(LE \{\
. if !\\n(BD .tl \(ts\\*(EE\\*(10\(ts\(ts\\*(EL\(ts
. if \\n(BD .if \\n(BD<\\w\(ts\\*(10\(ts .nr BD \\w\(ts\\*(10\(ts
. if \\n(BD \!\\*(10\\t\\*(EL\}\}
.if \\n(EP .if \\n(ZN \{\
. if \\n(LE=1 .tl \(ts\\*(EL\(ts\\*(10\(ts\(ts
. if \\n(LE=2 .tl \(ts\\*(EL\(ts\(ts\\*(10\(ts
. if !\\n(LE \{\
. if !\\n(BD .tl \(ts\\*(EL\\*(EE\\*(10\(ts\(ts\(ts
. if \\n(BD .if \\n(BD<\\w\(ts\\*(10\(ts .nr BD \\w\(ts\\*(10\(ts
. if \\n(BD \!\\h'-\\\\n(.iu'\\*(EL\\h'|0'\\*(10\}\}
'lt \\n(LLu
'pc %
.if \\n(YE .if \\n(EF .fi
.if t .if \\n(ZN .sp .5
.if n .if \\n(ZN .sp
.ie "\\n(.z"" .nr PE \\n(nl
.el .nr PE \\n(.d
..
.de PS \" start picture
. \" $1 is height, $2 is width, both in inches
.if \\$1>0 .sp .35
.ie \\$1>0 .nr $1 \\$1
.el .nr $1 0
.in (\\n(.lu-\\$2)/2u
.ne \\$1
..
.de PE \" end of picture
.in
.if \\n($1>0 .sp .65
..
. \" .P1/.P2 macros for programs
.
.nr XP 1 \" delta point size for program
.nr XV 1p \" delta vertical for programs
.nr XT 8 \" delta tab stop for programs
.nr DV .5v \" space before start of program
.
.de P1
.nr P1 .4i \" program indent in .P1
.if \\n(.$ .nr P1 \\$1
.br
.nr v \\n(.v
.di p1
.in \\n(P1u
.nf
.ps -\\n(XP
.vs -\\n(XVu
.ft CW
.nr t \\n(XT*\\w'x'u
.ta 1u*\\ntu 2u*\\ntu 3u*\\ntu 4u*\\ntu 5u*\\ntu 6u*\\ntu 7u*\\ntu 8u*\\ntu 9u*\\ntu 10u*\\ntu 11u*\\ntu 12u*\\ntu 13u*\\ntu 14u*\\ntu
..
.
.de P2
.br
.ps \\n(PS
.vs \\n(VSp
.vs \\nvu
.ft 1
.in -\\n(P1u
.di
.br
.sp \\n(DVu
.br
.if \\n(.$=0 .ne \\n(dnu \" -\\n(DVu
.nf
.p1
.sp \\n(DVu
.br
.fi
..
.
.de ME
.nr SJ \\n(.j
.if \\n(LL .nr LT \\n(LL
.nr YE 1
.if !\\n(PO .nr PO \\n(.o
.if \\n(mo-0 .ds MO January
.if \\n(mo-1 .ds MO February
.if \\n(mo-2 .ds MO March
.if \\n(mo-3 .ds MO April
.if \\n(mo-4 .ds MO May
.if \\n(mo-5 .ds MO June
.if \\n(mo-6 .ds MO July
.if \\n(mo-7 .ds MO August
.if \\n(mo-8 .ds MO September
.if \\n(mo-9 .ds MO October
.if \\n(mo-10 .ds MO November
.if \\n(mo-11 .ds MO December
.if \\n(dw-0 .ds DW Sunday
.if \\n(dw-1 .ds DW Monday
.if \\n(dw-2 .ds DW Tuesday
.if \\n(dw-3 .ds DW Wednesday
.if \\n(dw-4 .ds DW Thursday
.if \\n(dw-5 .ds DW Friday
.if \\n(dw-6 .ds DW Saturday
.nr yP (\\n(yr+2000)/100)
.nr yD (\\n(yr%100
.af yD 01
.if "\\*(DY"" .ds DY \\*(MO \\n(dy, \\n(yP\\n(yD
.if "\\*(CF"" .if n .ds CF "\\*(DY
..
. \"EM end up macro - process left over keep-release
.de EM
.br
.if \\n(AJ .tm Syntax error: no .AE
.if \\n(IF .ab Missing .FE somewhere
.if t .if \\n(TB=0 .wh -1p CM
.if \\n(TB \{\&\c
' bp
. NP
. ch CM 160\}
..
. \"NP new page
.de NP
.rr PE
.if \\n(FM+\\n(HM>=\\n(.p \{\
. tm Margins bigger than page length.
. ab
. ex\}
.if t .CM
.if !\\n(HM .nr HM 1i
'sp \\n(HMu/2u
.ev 1
.nr PX \\n(.s
.nr PF \\n(.f
.nr PV \\n(.v
.lt \\n(LTu
.ps \\n(PS
.vs \\n(PS+2
.ft 1
.if \\n(PO .po \\n(POu
.PT
.ps \\n(PX
.vs \\n(PVu
.ft \\n(PF
.ev
'sp |\\n(HMu
.nr XX 0 1
.nr YY 0-\\n(FMu
.ch FO 16i
.ch FX 17i
.ch FO \\n(.pu-\\n(FMu
.ch FX \\n(.pu-\\n(FMu
.if \\n(MF .FV
.nr MF 0
.mk
.os
.ev 1
.if !\\n(TD .if \\n(TC<5 .XK
.nr TC 0
.ns
.ev
.nr TQ \\n(.i
.nr TK \\n(.u
.if \\n(IT \{\
. in 0
. nf
. TT
. in \\n(TQu
. if \\n(TK .fi\
\}
.mk #T
....if t .if \\n(.o+\\n(LL>7.75i .tm Offset + line length exceeds 7.75 inches, too wide
..
.de XK
.nr TD 1
.nf
.ls 1
.in 0
.rn KJ KL
.KL
.rm KL
.if "\\n(.z"KJ" .di
.nr TB 0
.if "\\n(.z"KJ" .nr TB 1
.br
.in
.ls
.fi
.if (\\n(nl+1v)>(\\n(.p-\\n(FM) \{\
. if \\n(NX>1 .RC
. if \\n(NX<=1 .bp\}
.nr TD 0
..
.de KD
.nr KM 0
.if "\\n(.z"" .if \\$2>0 .if \\n(nl>\\n(HM \{\
. if (\\n(nl+1v)<(\\n(.p-\\n(FM) .di KJ \" full page figure must have new page
. sp 15i\}
.if "\\n(.z"" .if \\n(nl>\\n(HM .if \\$2=0 .if (\\n(nl+1v)>(\\n(.p-\\n(FM) .sp 15i
.if "\\n(.z"KJ" .nr KM 1 \" KM is 1 if in a rediversion of keeps
.if \\n(KM>0 \!.KD \\$1 \\$2
.nr KR \\n(.t
.if \\n(nl<=\\n(HM .nr KR 32767
.if \\n(KM=0 \{\
. if \\n(KR<\\$1 \{\
. di KJ
. nr KM 1\}
. if \\$2>0 .if (\\n(nl+1v)>(\\n(.p-\\n(FM) .sp 15i\}
.rs
.if \\n(KM=0 .if \\$2>0 .sp \\n(.tu-\\$1u
..
.de PT
.lt \\n(LLu
.pc %
.nr PN \\n%
.if \\n%-1 .tl \\*(LH\\*(CH\\*(RH
.lt \\n(.lu
..
. \"FO - footer of page
.de FO
.rn FO FZ
.if \\n(IT>0 \{\
. nr T. 1
. if \\n(FC=0 .T# 1
. br\}
.nr FC +1
.if \\n(NX<2 .nr WF 0
.nr dn 0
.if \\n(FC<=1 .if \\n(XX .XF
.rn FZ FO
.nr MF 0
.if \\n(dn .nr MF 1
.if !\\n(WF \{\
. nr YY 0-\\n(FMu
. ch FO \\n(YYu\}
.if !\\n(dn .nr WF 0
.if \\n(FC<=1 .if \\n(XX=0 \{\
. if \\n(NX>1 .RC
. if \\n(NX<=1 'bp\}
.nr FC -1
.if \\n(ML>0 .ne \\n(MLu
..
. \"2C - begin double column
.de 2C
.MC \" default MC is double column
..
.de MC \" multiple columns- arg is line length
.nr L1 \\n(LL*7/15
.if \\n(CW>=0 .nr L1 \\n(CWu
.if \\n(.$ .nr L1 \\$1n
.if \\n(GW>=0 .nr GW \\n(GWu
.if \\n(.$>1 .nr GW \\$2n
.nr NQ \\n(LL/\\n(L1
.if \\n(NQ<1 .nr NQ 1
.if \\n(NQ>2 .if (\\n(LL%\\n(L1)=0 .nr NQ -1
.if !\\n(1T \{\
. BG
. if n .sp 4
. if t .sp 2\}
.if \\n(NX=0 .nr NX 1
.if !\\n(NX=\\n(NQ \{\
. RT
. if \\n(NX>1 .bp
. mk
. nr NC 1
. po \\n(POu\}
.if \\n(NQ>1 .hy \\n(HY
.nr NX \\n(NQ
.if \\n(NX>1 .nr CW \\n(L1
.ll \\n(L1u
.nr FL \\n(L1u*11u/12u
.if \\n(NX>1 .if \\n(GW<0 .nr GW (\\n(LL-(\\n(NX*\\n(L1))/(\\n(NX-1)
.nr RO \\n(L1+\\n(GW
.ns
..
.de RC
.ie \\n(NC>=\\n(NX .C2
.el .C1
..
.de C1
.rt
.po +\\n(ROu
.nr NC +1
.if \\n(NC>\\n(NX .nr NC 1
.nr XX 0 1
.nr YY 0-\\n(FMu
.if \\n(MF .FV
.ch FX \\n(.pu-\\n(FMu
.ev 1
.if \\n(TB .XK
.nr TC 0
.ev
.nr TQ \\n(.i
.if \\n(IT \{\
. in 0
. TT
. in \\n(TQu\}
.mk #T
.ns
..
.de C2
.po \\n(POu
.nr NC +1
.if \\n(NC>\\n(NX .nr NC 1
'bp
..
. \"1C - return to single column format
.de 1C
.MC \\n(LLu
.hy \\n(HY
..
.de MH
Bell Laboratories
Murray Hill, New Jersey 07974
..
.de PY
Bell Laboratories
Piscataway, New Jersey 08854
..
.de BT
.nr PX \\n(.s
.nr PF \\n(.f
.ft 1
.ps \\n(PS
'lt \\n(LTu
.po \\n(POu
.if \\n%>0 .tl \(ts\\*(LF\(ts\\*(CF\(ts\\*(RF\(ts
.ft \\n(PF
.ps \\n(PX
..
. \"PP - paragraph
.de PP
.RT
.if \\n(1T .sp \\n(PDu
.ti +\\n(PIu
..
. \"SH - (unnumbered) section heading
.de SH
.ti \\n(.iu
.RT
.ie \\n(1T .sp 1
.el .BG
.RT
.ne 4
.ft 3
.if n .ul 1000
..
. \"NH - numbered heading
.de N{
.RT
.ie \\n(1T .sp 1
.el .BG
.RT
.ne 4
.ft 3
.if n .ul 1000
.nr NS \\$1
.if !\\n(.$ .nr NS 1
.if !\\n(NS .nr NS 1
.nr H\\n(NS +1
.if !\\n(NS-4 .nr H5 0
.if !\\n(NS-3 .nr H4 0
.if !\\n(NS-2 .nr H3 0
.if !\\n(NS-1 .nr H2 0
.if !\\$1 .if \\n(.$ .nr H1 1
.ds SN \\n(H1.
.ti \\n(.iu
.if \\n(NS-1 .as SN \\n(H2.
.if \\n(NS-2 .as SN \\n(H3.
.if \\n(NS-3 .as SN \\n(H4.
.if \\n(NS-4 .as SN \\n(H5.
..
.de NH
.N{ \\$1
\\*(SN
..
. \"BG - begin, execute at first PP
.de BG
.br
.ME
.rm ME
.di
.ce 0
.nr KI 0
.hy \\n(HY
.nr 1T 1
.nr CS 0
.S\\n(ST
.rm S0 S1 S2 S3 OD OK TX AX WT CS TM IM MF MR RP I1 I2 I3 I4 I5 CB E1 E2
.de TL
.ft 3
.sp
.if n .ul 100
.ce 100
.ps +2
\\..
.de AU
.ft 2
.if n .ul 0
.ce 100
.sp
.NL
\\..
.de AI
.ft 1
.ce 100
.if n .ul 0
.if n .sp
.if t .sp .5
.NL
\\..
.RA
.rm RA
.rn FJ FS
.rn FK FE
.nf
.ev 1
.ps \\n(PS-2
.vs \\n(.s+2p
.ev
.if !\\n(KG .nr FP 0
.if \\n(GA>1 .if \\n(KG=0 .nr GA 0 \" next UNIX must be flagged.
.nr KG 0
.if \\n(FP \{\
. FS
. FG
. FE\}
.br
.if n .if \\n(TV .sp 2
.if t .if \\n(TV .sp 1
.fi
.ll \\n(LLu
.ev 1
.if !\\n(FL .nr FL \\n(LLu*11u/12u
.ll \\n(FLu
.ev
..
.de RA \"redefine abstract macros
.de AB
.br
.if !\\n(1T .BG
.ce 1
.sp 1
.ie \\n(.$ \{\
. if !"\\$1"-" .if !"\\$1"no" \{\
\\$1
.sp\}\}
.el \{\
ABSTRACT
.sp\}
.sp 1
.nr AJ 1
.in +\\n(.lu/12u
.ll -\\n(.lu/12u
.RT
\\..
.de AE
.nr AJ 0
.br
.in 0
.ll \\n(LLu
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
\\..
..
. \"IP - indented paragraph
.de IP
.RT
.if !\\n(IP .nr IP +1
.ie \\n(ID>0 .sp \\n(IDu
.el .sp \\n(PDu
.nr IU \\n(IR+1
.if \\n(.$>1 .nr I\\n(IU \\$2n+\\n(I\\n(IRu
.if \\n(I\\n(IU=0 .nr I\\n(IU \\n(PIu+\\n(I\\n(IRu
.in \\n(I\\n(IUu
.nr TY \\n(TZ-\\n(.i
.nr JQ \\n(I\\n(IU-\\n(I\\n(IR
.ta \\n(JQu \\n(TYuR
.if \\n(.$ \{\
.ti \\n(I\\n(IRu
\&\\$1\t\c
.\}
..
. \"LP - left aligned (block) paragraph
.de LP
.ti \\n(.iu
.RT
.if \\n(1T .sp \\n(PDu
..
.de QP
.ti \\n(.iu
.RT
.if \\n(1T .sp \\n(PDu
.ne 1.1
.nr QP 1
.in +\\n(QIu
.ll -\\n(QIu
.ti \\n(.iu
..
. \"IE - synonym for .LP
.de IE
.LP
..
. \"RS - prepare for double indenting
.de RS
.nr IS \\n(IP
.RT
.nr IP \\n(IS
.nr IU \\n(IR
.nr IR +1
.if !\\n(I\\n(IR .nr I\\n(IR \\n(I\\n(IU+\\n(PIu
.in \\n(I\\n(IRu
.nr TY \\n(TZ-\\n(.i
.ta \\n(TYuR
..
. \"RE - retreat to the left
.de RE
.nr IS \\n(IP
.RT
.nr IP \\n(IS
.if \\n(IR>0 .nr IR -1
.in \\n(I\\n(IRu
..
.de TC
.nr TZ \\n(.lu
.if \\n(.$ .nr TZ \\$1n
.ta \\n(TZuR
..
.de TD
.LP
.nr TZ 0
..
. \"CM - cut mark
.de CM
.po 0
.lt 7.6i
.ft 1
.ps 10
.vs 4p
.if "\\*(.T"aps" .tl '--''--'
.po
.vs
.lt
.ps
.ft
..
. \" fontname(CW) fontstr(\f(CW) first_arg goes_after goes_before
.de OF \" this is completely WRONG if any argument contains "'s
.nr PQ \\n(.f
.hy 0
.if t .if "\\$3"" .ft \\$1
.if t .if !"\\$3"" \{\
\&\\$5\\$2\\$3\\f\\n(PQ\\$4
.hy \\n(HY\}
.if n \{\
. if \\n(.$=5 \&\\$5
. ie "\\$3"" .ul 1000
. el .ul 1
. if \\n(.$=3 \&\\$3
. if \\n(.$>3 \&\\$3\\c
. if \\n(.$>3 \&\\$4
. hy \\n(HY\}
..
. \"B - bold font
.de B
.OF 3 \\f3 "\\$1" "\\$2" "\\$3"
..
.de BI \" bold italic -- only on 202
.OF 4 \\f4 "\\$1" "\\$2" "\\$3"
..
. \"R - Roman font
.de R
.nr PQ \\n(.f
.ft 1
.ie \\n(.$>0 \&\\$1\f\\n(PQ\\$2
.el .if n .ul 0
..
. \"I - italic font
.de I
.OF 2 \\f2 "\\$1" "\\$2" "\\$3"
..
. \"CW - constant width font
.de CW
.nr PQ \\n(.f
.if t .if \\n(.$>0 \%\&\\$3\f(CW\\$1\f\\n(PQ\&\\$2
.if t .if \\n(.$=0 .OF CW \\f(CW "\\$1" "\\$2" "\\$3"
.if n .OF CW \\f(CW "\\$1" "\\$2" "\\$3"
..
. \"TA - tabs set in ens or chars
.de TA
.ta \\$1n \\$2n \\$3n \\$4n \\$5n \\$6n \\$7n \\$8n \\$9n
..
. \"SM - make smaller size
.de SM
.ie \\n(.$ \&\\$3\s-2\\$1\s0\\$2
.el .ps -2
..
. \"LG - make larger size
.de LG
.ps +2
..
. \"NL - return to normal size
.de NL
.ps \\n(PS
..
. \"DA - force date; ND - no date or new date.
.de DA
.if \\n(.$ .ds DY \\$1 \\$2 \\$3 \\$4
.ds CF \\*(DY
..
.de ND
.ME
.rm ME
.ds DY \\$1 \\$2 \\$3 \\$4
.rm CF
..
.de FN
.FS
..
. \"FS - begin footnote
.de FJ
'ce 0
.nr IA \\n(IP
.nr IB \\n(.i
.ev1
.ll \\n(FLu
.da FF
.br
.if \\n(IF \{\
. tm Footnote within footnote-illegal.
. ab\}
.nr IF 1
.if !\\n+(XX-1 .FA
..
. \"FE - footnote end
.de FK
.br
.in 0
.nr IF 0
.di
.ev
.if !\\n(XX-1 .nr dn +\\n(.v
.nr YY -\\n(dn
.if !\\n(NX .nr WF 1
.if \\n(dl>\\n(CW .nr WF 1
.ie (\\n(nl+\\n(.v)<=(\\n(.p+\\n(YY) .ch FO \\n(YYu
.el \{\
. if \\n(nl>(\\n(HM+1.5v) .ch FO \\n(nlu+\\n(.vu
. if \\n(nl+\\n(FM+1v>\\n(.p .ch FX \\n(.pu-\\n(FMu+2v
. if \\n(nl<=(\\n(HM+1.5v) .ch FO \\n(HMu+(4u*\\n(.vu)\}
.nr IP \\n(IA
'in \\n(IBu
..
.\" First page footer.
.de FS
.ev1
.br
.ll \\n(FLu
.da FG
..
.de FE
.br
.di
.nr FP \\n(dn
.if !\\n(1T .nr KG 1 \"not in abstract repeat next page.
.if "\\n(.z"OD" .nr KG 0 \" if in OK, don't repeat.
.ev
..
.de FA
.if n __________________________
.if t \l'1i'
.br
..
.de FV
.FS
.nf
.ls 1
.FY
.ls
.fi
.FE
..
.de FX
.if \\n(XX \{\
. di FY
. ns\}
..
.de XF
.if \\n(nlu+1v>(\\n(.pu-\\n(FMu) .ch FX \\n(nlu+1.9v
.ev1
.nf
.ls 1
.FF
.rm FF
.nr XX 0 1
.br
.ls
.di
.fi
.ev
..
.de FL
.ev1
.nr FL \\$1n
.ll \\$1
.ev
..
.de HO
Bell Laboratories
Holmdel, New Jersey 07733
..
.de WH
Bell Laboratories
Whippany, New Jersey 07981
..
.de IH
Bell Laboratories
Naperville, Illinois 60540
..
.de UL \" underline argument, don't italicize
.ie t \\$1\l'|0\(ul'\\$2
.el .I "\\$1" "\\$2"
..
.de UX
.ie \\n(GA \\$2\s-1UNIX\s0\\$1
.el \{\
.ie n \{\\$2UNIX\\$1*
.FS
* UNIX is a
.ie \\$3=1 Footnote
.el registered trademark
of X/Open.
.FE\}
.el \\$2\s-1UNIX\\s0\\$1\\f1\(rg\\fP
.nr GA 1\}
..
.de US
the
.UX
operating system\\$1
..
.de QS
.br
.LP
.in +\\n(QIu
.ll -\\n(QIu
..
.de QE
.br
.ll +\\n(QIu
.in -\\n(QIu
.LP
..
.de B1 \" begin boxed stuff
.br
.di BB
.nr BC 0
.if "\\$1"C" .nr BC 1
.nr BE 1
..
.de B2 \" end boxed stuff
.br
.nr BI 1n
.if \\n(.$>0 .nr BI \\$1n
.di
.nr BE 0
.nr BW \\n(dl
.nr BH \\n(dn
.ne \\n(BHu+\\n(.Vu
.nr BQ \\n(.j
.nf
.ti 0
.if \\n(BC>0 .in +(\\n(.lu-\\n(BWu)/2u
.in +\\n(BIu
.ls 1
.BB
.ls
.in -\\n(BIu
.nr BW +2*\\n(BI
.sp -1
\l'\\n(BWu\(ul'\L'-\\n(BHu'\l'|0\(ul'\h'|0'\L'\\n(BHu'
.nr BW -2*\\n(BI
.if \\n(BC>0 .in -(\\n(.lu-\\n(BWu)/2u
.if \\n(BQ .fi
.br
..
.de AT
.nf
.sp
.ne 2
Attached:
..
.de CT
.nf
.sp
.ne 2
.ie \\n(.$ Copy to \\$1:
.el Copy to:
..
.de BX
.ie t \(br\|\\$1\|\(br\l'|0\(rn'\l'|0\(ul'
.el \(br\\kA\|\\$1\|\\kB\(br\v'-1v'\h'|\\nBu'\l'|\\nAu'\v'1v'\l'|\\nAu'
..
.IZ
.rm IZ
.de [
[
..
.de ]
]
..
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_i2c_soft_mpu6050/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_exti/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_led_and_delay/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
9xbt/bentobox
| 3,935
|
kernel/arch/aarch64/vectors.S
|
.extern el1_fault_handler
_fault_stub:
stp x0, x1, [sp, #-16]!
stp x2, x3, [sp, #-16]!
stp x4, x5, [sp, #-16]!
stp x6, x7, [sp, #-16]!
stp x8, x9, [sp, #-16]!
stp x10, x11, [sp, #-16]!
stp x12, x13, [sp, #-16]!
stp x14, x15, [sp, #-16]!
stp x16, x17, [sp, #-16]!
stp x18, x19, [sp, #-16]!
stp x20, x21, [sp, #-16]!
stp x22, x23, [sp, #-16]!
stp x24, x25, [sp, #-16]!
stp x26, x27, [sp, #-16]!
stp x28, x29, [sp, #-16]!
stp x30, xzr, [sp, #-16]!
mov x29, sp
mov x0, sp
bl el1_fault_handler
ldp x30, xzr, [sp], #16
ldp x28, x29, [sp], #16
ldp x26, x27, [sp], #16
ldp x24, x25, [sp], #16
ldp x22, x23, [sp], #16
ldp x20, x21, [sp], #16
ldp x18, x19, [sp], #16
ldp x16, x17, [sp], #16
ldp x14, x15, [sp], #16
ldp x12, x13, [sp], #16
ldp x10, x11, [sp], #16
ldp x8, x9, [sp], #16
ldp x6, x7, [sp], #16
ldp x4, x5, [sp], #16
ldp x2, x3, [sp], #16
ldp x0, x1, [sp], #16
eret
.extern el0_fault_handler
_lower_fault_stub:
stp x0, x1, [sp, #-16]!
stp x2, x3, [sp, #-16]!
stp x4, x5, [sp, #-16]!
stp x6, x7, [sp, #-16]!
stp x8, x9, [sp, #-16]!
stp x10, x11, [sp, #-16]!
stp x12, x13, [sp, #-16]!
stp x14, x15, [sp, #-16]!
stp x16, x17, [sp, #-16]!
stp x18, x19, [sp, #-16]!
stp x20, x21, [sp, #-16]!
stp x22, x23, [sp, #-16]!
stp x24, x25, [sp, #-16]!
stp x26, x27, [sp, #-16]!
stp x28, x29, [sp, #-16]!
stp x30, xzr, [sp, #-16]!
mov x29, sp
mov x0, sp
bl el0_fault_handler
ldp x30, xzr, [sp], #16
ldp x28, x29, [sp], #16
ldp x26, x27, [sp], #16
ldp x24, x25, [sp], #16
ldp x22, x23, [sp], #16
ldp x20, x21, [sp], #16
ldp x18, x19, [sp], #16
ldp x16, x17, [sp], #16
ldp x14, x15, [sp], #16
ldp x12, x13, [sp], #16
ldp x10, x11, [sp], #16
ldp x8, x9, [sp], #16
ldp x6, x7, [sp], #16
ldp x4, x5, [sp], #16
ldp x2, x3, [sp], #16
ldp x0, x1, [sp], #16
eret
.extern irq_handler
_irq_stub:
mov x16, sp
stp x0, x1, [sp, #-16]!
stp x2, x3, [sp, #-16]!
stp x4, x5, [sp, #-16]!
stp x6, x7, [sp, #-16]!
stp x8, x9, [sp, #-16]!
stp x10, x11, [sp, #-16]!
stp x12, x13, [sp, #-16]!
stp x14, x15, [sp, #-16]!
stp x16, x17, [sp, #-16]!
stp x18, x19, [sp, #-16]!
stp x20, x21, [sp, #-16]!
stp x22, x23, [sp, #-16]!
stp x24, x25, [sp, #-16]!
stp x26, x27, [sp, #-16]!
stp x28, x29, [sp, #-16]!
stp x30, xzr, [sp, #-16]!
mov x29, sp
mov x0, sp
bl irq_handler
ldp x30, xzr, [sp], #16
ldp x28, x29, [sp], #16
ldp x26, x27, [sp], #16
ldp x24, x25, [sp], #16
ldp x22, x23, [sp], #16
ldp x20, x21, [sp], #16
ldp x18, x19, [sp], #16
ldp x16, x17, [sp], #16
ldp x14, x15, [sp], #16
ldp x12, x13, [sp], #16
ldp x10, x11, [sp], #16
ldp x8, x9, [sp], #16
ldp x6, x7, [sp], #16
ldp x4, x5, [sp], #16
ldp x2, x3, [sp], #16
ldp x0, x1, [sp], #16
mov sp, x16
eret
.globl _evt
.balign 0x800
_evt:
/* Current EL with SP_EL0 */
_exc_sp0_sync:
b .
.balign 0x80
_exc_sp0_irq:
b .
.balign 0x80
_exc_sp0_fiq:
b .
.balign 0x80
_exc_sp0_serror:
b .
/* Current EL with SP_ELx
* These are kernel exceptions */
.balign 0x80
_exc_spx_sync:
b _fault_stub
.balign 0x80
_exc_spx_irq:
b _irq_stub
.balign 0x80
_exc_spx_fiq:
b .
.balign 0x80
_exc_spx_serror:
b .
/* Lower EL with SP_EL0
* These are userspace exceptions and syscalls */
.balign 0x80
_exc_lower_sync:
b _lower_fault_stub
.balign 0x80
_exc_lower_irq:
b _irq_stub
.balign 0x80
_exc_lower_fiq:
b .
.balign 0x80
_exc_lower_serror:
b .
/* Lower EL aarch32 */
.balign 0x80
_exc_lower_32_sync:
b .
.balign 0x80
_exc_lower_32_irq:
b .
.balign 0x80
_exc_lower_32_fiq:
b .
.balign 0x80
_exc_lower_32_serror:
b .
|
9xbt/bentobox
| 1,348
|
kernel/arch/aarch64/boot.S
|
.globl _start
_start:
mov x20, sp
msr spsel, #1
mov sp, x20
bl kmain
b .
.globl _ap_trampoline
_ap_trampoline:
mov x20, sp
msr spsel, #1
mov sp, x20
bl ap_startup
b .
.globl __aarch64_swp1_acq
__aarch64_swp1_acq:
1: ldaxrb w2, [x1]
stlxrb w3, w0, [x1]
cbnz w3, 1b
mov x0, x2
ret
.globl aarch64_save_fp
aarch64_save_fp:
stp q0, q1, [x0, #0]
stp q2, q3, [x0, #32]
stp q4, q5, [x0, #64]
stp q6, q7, [x0, #96]
stp q8, q9, [x0, #128]
stp q10, q11, [x0, #160]
stp q12, q13, [x0, #192]
stp q14, q15, [x0, #224]
stp q16, q17, [x0, #256]
stp q18, q19, [x0, #288]
stp q20, q21, [x0, #320]
stp q22, q23, [x0, #352]
stp q24, q25, [x0, #384]
stp q26, q27, [x0, #416]
stp q28, q29, [x0, #448]
stp q30, q31, [x0, #480]
ret
.globl aarch64_restore_fp
aarch64_restore_fp:
ldp q0, q1, [x0, #0]
ldp q2, q3, [x0, #32]
ldp q4, q5, [x0, #64]
ldp q6, q7, [x0, #96]
ldp q8, q9, [x0, #128]
ldp q10, q11, [x0, #160]
ldp q12, q13, [x0, #192]
ldp q14, q15, [x0, #224]
ldp q16, q17, [x0, #256]
ldp q18, q19, [x0, #288]
ldp q20, q21, [x0, #320]
ldp q22, q23, [x0, #352]
ldp q24, q25, [x0, #384]
ldp q26, q27, [x0, #416]
ldp q28, q29, [x0, #448]
ldp q30, q31, [x0, #480]
ret
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_timer_irq/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_timer_oc_pwm_tb6612/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_i2c_soft_ap3216c/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_i2c_soft_ssd1306/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_timer_oc_pwm_rgb/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_ds18b20/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_spi_hard_dma_st7735/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_uart/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_key_fifo/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_timer_oc_pwm_servo/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_spi_hard_w25qx/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_i2c_soft_bmp280/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_adc/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
903257958/stm32_oop_driver
| 29,173
|
stm32f407vg_drivers/stm32f407vg_fsmc_ili9341/firmware/cmsis/device/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
a16z/vectorized-fields
| 5,327
|
src/assembly/modsum256.S
|
/*
* void modsum256(uint64_t z[4], const uint64_t *x, uint32_t x_len, const uint64_t m[6])
*
* Copyright (C) 2024 Dag Arne Osvik
*
* Modular sum across components of a vector over finite fields from 225 bits up to 256 bits.
* Requires AVX-512 support.
*
* Parameters:
* z out Result. Canonical least non-negative residue.
* x in Pointer to vector of length x_len.
* x_len in Length of input vector x. Limited to 2^32-1.
* m in Pointer to 6-qword array containing the modulus m, its negative inverse mod 2^64 and 2^288/m.
*/
.global modsum256
.text
.p2align 6,,63
//////////////////////////////////////////////////
// Register roles
//////////////////////////////////////////////////
#ifndef WIN64
// AMD64 calling convention
# define PZ %rdi
# define PX %rsi
# define LEN %edx
# define PM %rcx
# define T0 %r8
# define T1 %r9
# define T2 %r10
# define T3 %r11
# define T4 PX
# define PL %rax
# define PH %rbx
#else
// X64 calling convention
# define PZ %rcx
# define PX %rdx
# define LEN %r8d
# define PM %r9
// TODO: verify correctness of allocations below
# define T0 %r8
# define T1 %rbp
# define T2 %r10
# define T3 %r11
# define T4 PZ
# define PL %rax
# define PH %rbx
#endif
#define MU 40(PM)
modsum256:
#ifdef WIN64
mov PZ, 1*8(%rsp)
mov %rbx, 2*8(%rsp)
mov %rbp, 3*8(%rsp)
#else
push %rbx
#endif
//////////////////////////////////////////////////
// Prepare four accumulators
//////////////////////////////////////////////////
vpxorq %zmm0, %zmm0, %zmm0
vmovdqa64 %zmm0, %zmm1
vmovdqa64 %zmm0, %zmm2
vmovdqa64 %zmm0, %zmm3
xor %r8d, %r8d
xor %r9d, %r9d
xor %r10d, %r10d
xor %r11d, %r11d
mov $0x1555, %eax
kmovw %eax, %k1
mov $0xff80, %eax
kmovw %eax, %k2
mov $0x01ff, %eax
kmovw %eax, %k3
mov LEN, %eax
test %eax, %eax
jz Done
and $3, %eax
shr $2, LEN
cmp $1, %eax
je 1f
cmp $2, %eax
je 2f
cmp $3, %eax
jne Loop4
3: vpmovzxdq 2*32(PX), %zmm4; vpaddq %zmm4, %zmm0, %zmm0
2: vpmovzxdq 1*32(PX), %zmm4; vpaddq %zmm4, %zmm1, %zmm1
1: vpmovzxdq 0*32(PX), %zmm4; vpaddq %zmm4, %zmm2, %zmm2
test LEN, LEN
jz Accumulate
.p2align 6,,63
Loop4:
//////////////////////////////////////////////////
// Zero-expand each dword and add it to a qword
//////////////////////////////////////////////////
vpmovzxdq 0*32(PX), %zmm4; vpaddq %zmm4, %zmm0, %zmm0
vpmovzxdq 1*32(PX), %zmm4; vpaddq %zmm4, %zmm1, %zmm1
vpmovzxdq 2*32(PX), %zmm4; vpaddq %zmm4, %zmm2, %zmm2
vpmovzxdq 3*32(PX), %zmm4; vpaddq %zmm4, %zmm3, %zmm3
sub $-128, PX
dec LEN
jnz Loop4
Accumulate:
//////////////////////////////////////////////////
// Combine accumulators
//////////////////////////////////////////////////
vpaddq %zmm1, %zmm0, %zmm0
vpaddq %zmm3, %zmm2, %zmm2
vpaddq %zmm2, %zmm0, %zmm0
//////////////////////////////////////////////////
// Propagate carries
//////////////////////////////////////////////////
mov $8, %eax
valignd $1, %zmm3, %zmm0, %zmm3{%k2}{z} // Shift lowest dword of zmm0 into zmm3
Propagate:
vpsrlq $32, %zmm0, %zmm1 // Zero-expand high dword carries from zmm0 to zmm1
valignd $2, %zmm0, %zmm0, %zmm0{%k1}{z} // Shift low dwords of zmm0 one qword down
vpaddq %zmm1, %zmm0, %zmm0 // Add carries
valignd $1, %zmm3, %zmm0, %zmm3{%k2}{z} // Shift lowest dword of zmm0 into zmm3
dec %eax
jnz Propagate
//////////////////////////////////////////////////
// Move intermediate result to integer registers
//////////////////////////////////////////////////
// The top 9 dwords of zmm3 now contain the sum. Copy them to the low end of zmm0.
valignd $7, %zmm3, %zmm3, %zmm0{%k3}{z}
// Copy to integer registers
vmovq %xmm0, T0; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, T1; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, T2; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, T3; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, T4
//////////////////////////////////////////////////
// Reduce using single-word Barrett
//////////////////////////////////////////////////
// q1 is low 32 bits of T4 and high 32 bits of T3
movq T3, %rax
shrd $32, T4, %rax
mulq MU // Multiply by mu. q2 in rdx:rax, q3 in rdx
// Subtract r2 from r1
mulx 0*8(PM), PL, PH; sub PL, T0; sbb PH, T1;
mulx 2*8(PM), PL, PH; sbb PL, T2; sbb PH, T3; sbb $0, T4
mulx 1*8(PM), PL, PH; sub PL, T1; sbb PH, T2;
mulx 3*8(PM), PL, PH; sbb PL, T3; sbb PH, T4
// Two conditional subtractions to guarantee canonicity of the result
// Save the result
mov T0, 0*8(PZ)
mov T1, 1*8(PZ)
mov T2, 2*8(PZ)
mov T3, 3*8(PZ)
// Subtract the modulus
sub 0*8(PM), T0
sbb 1*8(PM), T1
sbb 2*8(PM), T2
sbb 3*8(PM), T3
sbb $0, T4
// If borrow, skip to the end
jb Done
// Save the result
mov T0, 0*8(PZ)
mov T1, 1*8(PZ)
mov T2, 2*8(PZ)
mov T3, 3*8(PZ)
// Subtract the modulus
sub 0*8(PM), T0
sbb 1*8(PM), T1
sbb 2*8(PM), T2
sbb 3*8(PM), T3
sbb $0, T4
// If borrow, skip to the end
jb Done
// Save the result
mov T0, 0*8(PZ)
mov T1, 1*8(PZ)
mov T2, 2*8(PZ)
mov T3, 3*8(PZ)
Done:
//////////////////////////////////////////////////
// Cleanup
//////////////////////////////////////////////////
#ifdef WIN64
mov 1*8(%rsp), PZ
mov 2*8(%rsp), %rbx
mov 3*8(%rsp), %rbp
#else
pop %rbx
#endif
ret
// No executable stack
.section .note.GNU-stack
|
a16z/vectorized-fields
| 53,774
|
src/assembly/modmul256.S
|
/*
* void modmul256_mont(uint64_t *z, const uint64_t *x, const uint64_t *y, uint64_t xy_len, const uint64_t m[6])
*
* Copyright (C) 2024 Dag Arne Osvik
*
* Elementwise modular multiplication of vectors.
* 8-way parallel AVX512 and 8-element sequential integer computation per iteration.
*
* Parameters:
* z out Result. Vector of canonical least non-negative residues.
* x,y in Pointers to vectors of length xy_len.
* Elements must be 256-bit little-endian canonical residues.
* xy_len in Length of input vectors. Limited to 2^59-1.
* m in Pointer to 6-qword array containing the modulus m, its negative inverse mod 2^64 and 2^288/m.
*
* The implementation is based on manual coarse interleaving of AVX-512 and integer (AMD64) code.
* Most comments in the interleaved code relate to AVX-512; the integer code is documented under Loop1.
*/
.global modmul256_mont
//////////////////////////////////////////////////
// Register roles
//////////////////////////////////////////////////
// AMD64 WIN64
// %rax PY,Y3 PX
// %rcx LEN PZ, Y1
// %rdx MUL MUL
// %rbx PL PL
// %rsp * *
// %rbp PH PH
// %rsi PX Y0
// %rdi PZ,Y2 PM
// %r8 PM PY, Y3
// %r9 Y1 LEN
// %r10 Z0 Z0
// %r11 Z1 Z1
// %r12 Z2 Z2
// %r13 Z3 Z3
// %r14 Z4 Z4
// %r15 Y0 Y2
// zmm0-zmm7 intermediate result
// zmm8 2^32-1, mask to extract lower dword from qwords
// zmm9 reduction multiplier
// zmm10-zmm17 intermediate results
// zmm16-zmm23 digits of x
// zmm24-zmm31 digits of y
#ifndef WIN64
// AMD64 calling convention
# define PZ %rdi
# define PX %rsi
# define PY %rax
# define LEN %rcx
# define PM %r8
# define Y3 PY
# define Y2 PZ
# define Y1 %r9
# define Y0 %r15
#else
// X64 calling convention
# define PZ %rcx
# define PX %rax
# define PY %r8
# define LEN %r9
# define PM %rax
# define Y0 %rsi
# define Y1 PZ
# define Y2 %r15
# define Y3 PY
#endif
#define MUL %rdx
#define Z0 %r10
#define Z1 %r11
#define Z2 %r12
#define Z3 %r13
#define Z4 %r14
#define PL %rbx
#define PH %rbp
.text
.p2align 6,,63
modmul256_mont:
//////////////////////////////////////////////////
// Init
//////////////////////////////////////////////////
// Free up rdx to be used as multiplier
movq %rdx, %rax
#ifndef WIN64
pushq %rbx
pushq %rbp
#else
// Load pointer to the modulus from stack
movq 5*8(%rsp), PM
movq %rbx, 1*8(%rsp)
movq %rbp, 2*8(%rsp)
movq %rsi, 3*8(%rsp)
movq %rdi, 4*8(%rsp)
#endif
pushq %r12
pushq %r13
pushq %r14
pushq %r15
// Change to negatively-indexed pointers
shlq $5, LEN // 32 bytes per element, 16 elements per batch
addq LEN, PX
addq LEN, PY
addq LEN, PZ
negq LEN
// Process inputs one by one until a multiple of 16 is left
test $0x1e0, LEN
jnz Loop1
Blocksof16:
test LEN, LEN
jz Done // Nothing more to do
#ifdef WIN64
// Save xmm6-xmm15
subq $10*16, %rsp
movdqu xmm6, $0*16(%rsp)
movdqu xmm7, $1*16(%rsp)
movdqu xmm8, $2*16(%rsp)
movdqu xmm9, $3*16(%rsp)
movdqu xmm10, $4*16(%rsp)
movdqu xmm11, $5*16(%rsp)
movdqu xmm12, $6*16(%rsp)
movdqu xmm13, $7*16(%rsp)
movdqu xmm14, $8*16(%rsp)
movdqu xmm15, $9*16(%rsp)
#endif
// Create mask for low dword in each qword
vpcmpeqb %ymm8, %ymm8, %ymm8
vpmovzxdq %ymm8, %zmm8
mov $0x5555, %edx
kmovd %edx, %k1
jmp Loop16
.p2align 6,,63
Loop16:
//////////////////////////////////////////////////
// Load inputs
//////////////////////////////////////////////////
// Save registers
pushq PY
pushq PZ
pushq LEN
// Load x
vmovdqu64 256+0*64(PX, LEN), %zmm16
vmovdqu64 256+1*64(PX, LEN), %zmm17
vmovdqu64 256+2*64(PX, LEN), %zmm18
vmovdqu64 256+3*64(PX, LEN), %zmm19
// Load y
vmovdqu64 256+0*64(PY, LEN), %zmm24
vmovdqu64 256+1*64(PY, LEN), %zmm25
vmovdqu64 256+2*64(PY, LEN), %zmm26
vmovdqu64 256+3*64(PY, LEN), %zmm27
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
//////////////////////////////////////////////////
// Transpose and expand x and y
//////////////////////////////////////////////////
// Step 1
vshufi64x2 $0x88, %zmm17, %zmm16, %zmm20 // 0x88 = 0b1000_1000: even quarters of each input
vshufi64x2 $0xdd, %zmm17, %zmm16, %zmm22 // 0xdd = 0b1101_1101: odd quarters of each input
vshufi64x2 $0x88, %zmm19, %zmm18, %zmm21
vshufi64x2 $0xdd, %zmm19, %zmm18, %zmm23
vshufi64x2 $0x88, %zmm25, %zmm24, %zmm28
vshufi64x2 $0xdd, %zmm25, %zmm24, %zmm30
vshufi64x2 $0x88, %zmm27, %zmm26, %zmm29
vshufi64x2 $0xdd, %zmm27, %zmm26, %zmm31
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
// Step 2
vpermq $0xd8, %zmm20, %zmm20 // 0xd8 = 0b11_01_10_00: swap middle words of each half
vpermq $0xd8, %zmm21, %zmm21
vpermq $0xd8, %zmm22, %zmm22
vpermq $0xd8, %zmm23, %zmm23
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
vpermq $0xd8, %zmm28, %zmm28
vpermq $0xd8, %zmm29, %zmm29
vpermq $0xd8, %zmm30, %zmm30
vpermq $0xd8, %zmm31, %zmm31
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
// Step 3
vshufi64x2 $0xd8, %zmm20, %zmm20, %zmm20 // 0xd8 = 0b11_01_10_00: swap middle words
vshufi64x2 $0xd8, %zmm21, %zmm21, %zmm21
vshufi64x2 $0xd8, %zmm22, %zmm22, %zmm22
vshufi64x2 $0xd8, %zmm23, %zmm23, %zmm23
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
vshufi64x2 $0xd8, %zmm28, %zmm28, %zmm28
vshufi64x2 $0xd8, %zmm29, %zmm29, %zmm29
vshufi64x2 $0xd8, %zmm30, %zmm30, %zmm30
vshufi64x2 $0xd8, %zmm31, %zmm31, %zmm31
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
// Step 4
vshufi64x2 $0x44, %zmm21, %zmm20, %zmm16 // 0x44 = 0b01_00_01_00: low half of each input
vshufi64x2 $0xee, %zmm21, %zmm20, %zmm18 // 0xee = 0b11_10_11_10: high half of each input
vshufi64x2 $0x44, %zmm23, %zmm22, %zmm20
vshufi64x2 $0xee, %zmm23, %zmm22, %zmm22
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
vshufi64x2 $0x44, %zmm29, %zmm28, %zmm24
vshufi64x2 $0xee, %zmm29, %zmm28, %zmm26
vshufi64x2 $0x44, %zmm31, %zmm30, %zmm28
vshufi64x2 $0xee, %zmm31, %zmm30, %zmm30
// Step 5
vpsrlq $32, %zmm16, %zmm17
vpsrlq $32, %zmm18, %zmm19
vpsrlq $32, %zmm20, %zmm21
vpsrlq $32, %zmm22, %zmm23
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
vpsrlq $32, %zmm24, %zmm25
vpsrlq $32, %zmm26, %zmm27
vpsrlq $32, %zmm28, %zmm29
vpsrlq $32, %zmm30, %zmm31
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
vpandq %zmm8, %zmm16, %zmm16
vpandq %zmm8, %zmm18, %zmm18
vpandq %zmm8, %zmm20, %zmm20
vpandq %zmm8, %zmm22, %zmm22
vpandq %zmm8, %zmm24, %zmm24
vpandq %zmm8, %zmm26, %zmm26
vpandq %zmm8, %zmm28, %zmm28
vpandq %zmm8, %zmm30, %zmm30
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
addq $32, LEN
// Save registers
pushq LEN
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
// For each 256-bit input value, each zmm register now represents a 32-bit input word zero-extended to 64 bits.
//////////////////////////////////////////////////
// Multiply y by doubleword 0 of x
//////////////////////////////////////////////////
vpmuludq %zmm16, %zmm24, %zmm0
vpmuludq %zmm16, %zmm25, %zmm1
vpmuludq %zmm16, %zmm26, %zmm2
vpmuludq %zmm16, %zmm27, %zmm3
vpmuludq %zmm16, %zmm28, %zmm4
vpmuludq %zmm16, %zmm29, %zmm5
vpmuludq %zmm16, %zmm30, %zmm6
vpmuludq %zmm16, %zmm31, %zmm7
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9 // Reduction multiplier
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
//////////////////////////////////////////////////
// Reduce
//////////////////////////////////////////////////
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm7, %zmm7
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
//////////////////////////////////////////////////
// Process doubleword 1 of x
//////////////////////////////////////////////////
vpmuludq %zmm17, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm17, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm17, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm17, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
vpmuludq %zmm17, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm17, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm17, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm17, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
addq $32, LEN
// Save registers
pushq LEN
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
//////////////////////////////////////////////////
// Process doubleword 2 of x
//////////////////////////////////////////////////
vpmuludq %zmm18, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm18, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm18, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm18, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
vpmuludq %zmm18, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm18, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm18, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm18, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
addq $32, LEN
// Save registers
pushq LEN
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
//////////////////////////////////////////////////
// Process doubleword 3 of x
//////////////////////////////////////////////////
vpmuludq %zmm19, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm19, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm19, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm19, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
vpmuludq %zmm19, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm19, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm19, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm19, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
addq $32, LEN
// Save registers
pushq LEN
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
//////////////////////////////////////////////////
// Process doubleword 4 of x
//////////////////////////////////////////////////
vpmuludq %zmm20, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm20, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm20, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm20, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
vpmuludq %zmm20, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm20, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm20, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm20, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
mulxq 4*8(PM), MUL, PH
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
mulxq 4*8(PM), MUL, PH
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
addq $32, LEN
// Save registers
pushq LEN
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
//////////////////////////////////////////////////
// Process doubleword 5 of x
//////////////////////////////////////////////////
vpmuludq %zmm21, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm21, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm21, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm21, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
mulxq 4*8(PM), MUL, PH
vpmuludq %zmm21, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm21, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm21, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm21, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
mulxq 4*8(PM), MUL, PH
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
mulxq 4*8(PM), MUL, PH
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
mulxq 4*8(PM), MUL, PH
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
//////////////////////////////////////////////////
// Process doubleword 6 of x
//////////////////////////////////////////////////
vpmuludq %zmm22, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm22, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm22, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm22, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
vpmuludq %zmm22, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm22, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm22, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm22, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
addq $32, LEN
// Save registers
pushq LEN
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
mulxq 4*8(PM), MUL, PH
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
mulxq 4*8(PM), MUL, PH
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
mulxq 4*8(PM), MUL, PH
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
//////////////////////////////////////////////////
// Process doubleword 7 of x
//////////////////////////////////////////////////
vpmuludq %zmm23, %zmm24, %zmm10; vpaddq %zmm10, %zmm0, %zmm0;
vpmuludq %zmm23, %zmm25, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq %zmm23, %zmm26, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq %zmm23, %zmm27, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
mulxq 4*8(PM), MUL, PH
vpmuludq %zmm23, %zmm28, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq %zmm23, %zmm29, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq %zmm23, %zmm30, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq %zmm23, %zmm31, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
vpmuludq 8*4(PM){1to8}, %zmm0, %zmm9; // Compute reduction multipliers
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
// Move high dwords to zmm10-16, add each to the corresponding low dword (propagate 32-bit carries)
vpsrlq $32, %zmm0, %zmm10; vpandq %zmm8, %zmm0, %zmm0; vpaddq %zmm10, %zmm1, %zmm1;
vpsrlq $32, %zmm1, %zmm11; vpandq %zmm8, %zmm1, %zmm1; vpaddq %zmm11, %zmm2, %zmm2;
vpsrlq $32, %zmm2, %zmm12; vpandq %zmm8, %zmm2, %zmm2; vpaddq %zmm12, %zmm3, %zmm3;
vpsrlq $32, %zmm3, %zmm13; vpandq %zmm8, %zmm3, %zmm3; vpaddq %zmm13, %zmm4, %zmm4;
vpsrlq $32, %zmm4, %zmm14; vpandq %zmm8, %zmm4, %zmm4; vpaddq %zmm14, %zmm5, %zmm5;
vpsrlq $32, %zmm5, %zmm15; vpandq %zmm8, %zmm5, %zmm5; vpaddq %zmm15, %zmm6, %zmm6;
vpsrlq $32, %zmm6, %zmm16; vpandq %zmm8, %zmm6, %zmm6; vpaddq %zmm16, %zmm7, %zmm7;
// zmm7 keeps all 64 bits
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
// Restore registers
popq LEN
mov 0(%rsp), PZ
mov 8(%rsp), PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
addq $32, LEN
// Save registers
pushq LEN
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
vpmuludq 0*4(PM){1to8}, %zmm9, %zmm10; vpaddq %zmm10, %zmm0, %zmm0; // Low dword of zmm0 is zero
vpmuludq 1*4(PM){1to8}, %zmm9, %zmm11; vpaddq %zmm11, %zmm1, %zmm1;
vpmuludq 2*4(PM){1to8}, %zmm9, %zmm12; vpaddq %zmm12, %zmm2, %zmm2;
vpmuludq 3*4(PM){1to8}, %zmm9, %zmm13; vpaddq %zmm13, %zmm3, %zmm3;
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
mulxq 4*8(PM), MUL, PH
vpmuludq 4*4(PM){1to8}, %zmm9, %zmm14; vpaddq %zmm14, %zmm4, %zmm4;
vpmuludq 5*4(PM){1to8}, %zmm9, %zmm15; vpaddq %zmm15, %zmm5, %zmm5;
vpmuludq 6*4(PM){1to8}, %zmm9, %zmm16; vpaddq %zmm16, %zmm6, %zmm6;
vpmuludq 7*4(PM){1to8}, %zmm9, %zmm17; vpaddq %zmm17, %zmm7, %zmm7;
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
// Propagate carries and shift down by one dword
vpsrlq $32, %zmm0, %zmm10; vpaddq %zmm10, %zmm1, %zmm1; vpandq %zmm8, %zmm1, %zmm0
vpsrlq $32, %zmm1, %zmm11; vpaddq %zmm11, %zmm2, %zmm2; vpandq %zmm8, %zmm2, %zmm1
vpsrlq $32, %zmm2, %zmm12; vpaddq %zmm12, %zmm3, %zmm3; vpandq %zmm8, %zmm3, %zmm2
vpsrlq $32, %zmm3, %zmm13; vpaddq %zmm13, %zmm4, %zmm4; vpandq %zmm8, %zmm4, %zmm3
vpsrlq $32, %zmm4, %zmm14; vpaddq %zmm14, %zmm5, %zmm5; vpandq %zmm8, %zmm5, %zmm4
vpsrlq $32, %zmm5, %zmm15; vpaddq %zmm15, %zmm6, %zmm6; vpandq %zmm8, %zmm6, %zmm5
vpsrlq $32, %zmm6, %zmm16; vpaddq %zmm16, %zmm7, %zmm7; vpandq %zmm8, %zmm7, %zmm6
vpsrlq $32, %zmm7, %zmm7
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
//////////////////////////////////////////////////
// Conditional subtraction of the modulus
//////////////////////////////////////////////////
vpermd 0*4(PM){1to16}, %zmm8, %zmm10{%k1}{z}
vpermd 1*4(PM){1to16}, %zmm8, %zmm11{%k1}{z}
vpermd 2*4(PM){1to16}, %zmm8, %zmm12{%k1}{z}
vpermd 3*4(PM){1to16}, %zmm8, %zmm13{%k1}{z}
vpermd 4*4(PM){1to16}, %zmm8, %zmm14{%k1}{z}
vpermd 5*4(PM){1to16}, %zmm8, %zmm15{%k1}{z}
vpermd 6*4(PM){1to16}, %zmm8, %zmm16{%k1}{z}
vpermd 7*4(PM){1to16}, %zmm8, %zmm17{%k1}{z}
vpsubq %zmm10, %zmm0, %zmm10; vpsrlq $63, %zmm10, %zmm20; vpandq %zmm8, %zmm10, %zmm10
vpsubq %zmm11, %zmm1, %zmm11; vpsubq %zmm20, %zmm11, %zmm11; vpsrlq $63, %zmm11, %zmm21; vpandq %zmm8, %zmm11, %zmm11
vpsubq %zmm12, %zmm2, %zmm12; vpsubq %zmm21, %zmm12, %zmm12; vpsrlq $63, %zmm12, %zmm22; vpandq %zmm8, %zmm12, %zmm12
vpsubq %zmm13, %zmm3, %zmm13; vpsubq %zmm22, %zmm13, %zmm13; vpsrlq $63, %zmm13, %zmm23; vpandq %zmm8, %zmm13, %zmm13
vpsubq %zmm14, %zmm4, %zmm14; vpsubq %zmm23, %zmm14, %zmm14; vpsrlq $63, %zmm14, %zmm24; vpandq %zmm8, %zmm14, %zmm14
vpsubq %zmm15, %zmm5, %zmm15; vpsubq %zmm24, %zmm15, %zmm15; vpsrlq $63, %zmm15, %zmm25; vpandq %zmm8, %zmm15, %zmm15
vpsubq %zmm16, %zmm6, %zmm16; vpsubq %zmm25, %zmm16, %zmm16; vpsrlq $63, %zmm16, %zmm26; vpandq %zmm8, %zmm16, %zmm16
vpsubq %zmm17, %zmm7, %zmm17; vpsubq %zmm26, %zmm17, %zmm17;
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
vpmovq2m %zmm17, %k2
mulxq 4*8(PM), MUL, PH
knotb %k2, %k2
vmovdqu64 %zmm10, %zmm0{%k2}
vmovdqu64 %zmm11, %zmm1{%k2}
vmovdqu64 %zmm12, %zmm2{%k2}
vmovdqu64 %zmm13, %zmm3{%k2}
vmovdqu64 %zmm14, %zmm4{%k2}
vmovdqu64 %zmm15, %zmm5{%k2}
vmovdqu64 %zmm16, %zmm6{%k2}
vmovdqu64 %zmm17, %zmm7{%k2}
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
//////////////////////////////////////////////////
// Transpose results back
//////////////////////////////////////////////////
vmovdqa64 pattern1(%rip), %zmm11
vmovdqa64 pattern2(%rip), %zmm12
vmovdqa64 pattern3(%rip), %zmm13
vmovdqa64 pattern4(%rip), %zmm14
// Step 1
vpsllq $32, %zmm1, %zmm1; vporq %zmm1, %zmm0, %zmm0
vpsllq $32, %zmm3, %zmm3; vporq %zmm3, %zmm2, %zmm1
vpsllq $32, %zmm5, %zmm5; vporq %zmm5, %zmm4, %zmm2
vpsllq $32, %zmm7, %zmm7; vporq %zmm7, %zmm6, %zmm3
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
// Step 2
vmovdqu64 %zmm0, %zmm4
vmovdqu64 %zmm2, %zmm6
vpermt2q %zmm1, %zmm11, %zmm0
vpermt2q %zmm4, %zmm12, %zmm1
vpermt2q %zmm3, %zmm11, %zmm2
vpermt2q %zmm6, %zmm12, %zmm3
mulxq 4*8(PM), MUL, PH
// Step 3
vmovdqu64 %zmm0, %zmm4
vmovdqu64 %zmm1, %zmm5
vpermt2q %zmm2, %zmm13, %zmm0
vpermt2q %zmm4, %zmm14, %zmm2
vpermt2q %zmm3, %zmm13, %zmm1
vpermt2q %zmm5, %zmm14, %zmm3
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
cmovncq Y0, Z0
cmovncq Y1, Z1
cmovncq Y2, Z2
cmovncq Y3, Z3
// Restore registers
popq LEN
popq PZ
popq PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
addq $32, LEN
//////////////////////////////////////////////////
// Save AVX-512 results
//////////////////////////////////////////////////
vmovdqu64 %zmm0, 0*64(PZ, LEN)
vmovdqu64 %zmm2, 1*64(PZ, LEN)
vmovdqu64 %zmm1, 2*64(PZ, LEN)
vmovdqu64 %zmm3, 3*64(PZ, LEN)
addq $256, LEN
jnz Loop16
Done:
#ifndef WIN64
popq %r15
popq %r14
popq %r13
popq %r12
popq %rbp
popq %rbx
#else
// Restore xmm6-xmm15
movdqu $0*16(%rsp), xmm6
movdqu $1*16(%rsp), xmm7
movdqu $2*16(%rsp), xmm8
movdqu $3*16(%rsp), xmm9
movdqu $4*16(%rsp), xmm10
movdqu $5*16(%rsp), xmm11
movdqu $6*16(%rsp), xmm12
movdqu $7*16(%rsp), xmm13
movdqu $8*16(%rsp), xmm14
movdqu $9*16(%rsp), xmm15
addq $10*16, %rsp
popq %r15
popq %r14
popq %r13
popq %r12
movq 1*8(%rsp), %rbx
movq 2*8(%rsp), %rbp
movq 3*8(%rsp), %rsi
movq 4*8(%rsp), %rdi
#endif
ret
.p2align 6,,63
Loop1:
//////////////////////////////////////////////////
// Process 1-15 elements to leave a multiple of 16
//////////////////////////////////////////////////
// Save registers
pushq PY
pushq PZ
pushq LEN
// Load inputs
movq 0*8(PX,LEN), MUL
movq 0*8(PY,LEN), Y0
movq 1*8(PY,LEN), Y1
movq 2*8(PY,LEN), Y2
movq 3*8(PY,LEN), Y3
// Montgomery multiplication
mulxq Y0, Z1, Z2
mulxq Y1, PL, Z3; addq PL, Z2
mulxq Y2, PL, Z4; adcq PL, Z3
mulxq Y3, PL, Z0; adcq PL, Z4; adcq $0, Z0
movq Z1, MUL
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z1; adcq PH, Z2
mulxq 2*8(PM), PL, PH; adcq PL, Z3; adcq PH, Z4; adcq $0, Z0
mulxq 1*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 3*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
movq 1*8(PX, LEN), MUL
mulxq Y0, PL, PH; addq PL, Z2; adcq PH, Z3
mulxq Y2, PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq Y1, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y3, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq Z2, MUL
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z2; adcq PH, Z3
mulxq 2*8(PM), PL, PH; adcq PL, Z4; adcq PH, Z0; adcq $0, Z1
mulxq 1*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 3*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
movq 2*8(PX, LEN), MUL
mulxq Y0, PL, PH; addq PL, Z3; adcq PH, Z4
mulxq Y2, PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq Y1, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y3, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq Z3, MUL
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z3; adcq PH, Z4
mulxq 2*8(PM), PL, PH; adcq PL, Z0; adcq PH, Z1; adcq $0, Z2
mulxq 1*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 3*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
movq 3*8(PX, LEN), MUL
mulxq Y0, PL, PH; addq PL, Z4; adcq PH, Z0
mulxq Y2, PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq Y1, PL, PH; addq PL, Z0; adcq PH, Z1
mulxq Y3, PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
movq Z4, MUL
mulxq 4*8(PM), MUL, PH
mulxq 0*8(PM), PL, PH; addq PL, Z4; adcq PH, Z0
mulxq 2*8(PM), PL, PH; adcq PL, Z1; adcq PH, Z2; adcq $0, Z3
mulxq 1*8(PM), PL, PH; addq PL, Z0; adcq PH, Z1
mulxq 3*8(PM), PL, PH; adcq PL, Z2; adcq PH, Z3; adcq $0, Z4
// Conditional subtraction of the modulus
movq Z0, Y0
movq Z1, Y1
movq Z2, Y2
movq Z3, Y3
subq 0*8(PM), Y0
sbbq 1*8(PM), Y1
sbbq 2*8(PM), Y2
sbbq 3*8(PM), Y3
sbbq Z4, Z4
cmovzq Y0, Z0
cmovzq Y1, Z1
cmovzq Y2, Z2
cmovzq Y3, Z3
// Restore registers
popq LEN
popq PZ
popq PY
// Store output
movq Z0, 0*8(PZ, LEN)
movq Z1, 1*8(PZ, LEN)
movq Z2, 2*8(PZ, LEN)
movq Z3, 3*8(PZ, LEN)
// Loop
addq $0x020, LEN
test $0x1e0, LEN
jnz Loop1
jmp Blocksof16
//////////////////////////////////////////////////
// Patterns used to transpose results
//////////////////////////////////////////////////
.p2align 6,,63 // 512-bit alignment
pattern1:
.quad 0, 8, 1, 9, 2, 10, 3, 11
pattern2:
.quad 12, 4, 13, 5, 14, 6, 15, 7
pattern3:
.quad 0, 1, 8, 9, 2, 3, 10, 11
pattern4:
.quad 12, 13, 4, 5, 14, 15, 6, 7
// No executable stack
.section .note.GNU-stack
|
a16z/vectorized-fields
| 6,782
|
src/assembly/innerproduct256.S
|
/*
* void innerproduct256(uint64_t z[4], const uint64_t *x, const uint64_t *y, uint32_t xy_len)
*
* Copyright (C) 2024 Dag Arne Osvik
*
* AVX-512 assembler implementation of integer inner product.
*
* Inputs x and y are two vectors of little-endian 256-bit elements
* Vector length is up to 2^32-1 elements.
* Output z is a little-endian 544-bit inner product.
*
* z will always be overwritten
* xy_len can have any 32-bit value
* x and y must each point to a vector of length xy_len*32 bytes
*/
//////////////////////////////////////////////////
// Register roles
//////////////////////////////////////////////////
// Function parameter registers
#ifndef WIN64
// AMD64 calling convention
# define PZ %rdi
# define PX %rsi
# define PY %rdx
# define LEN %ecx
#else
// X64 calling convention
# define PZ %rcx
# define PX %rdx
# define PY %r8
# define LEN %r9d
#endif
// Partial product vector temporaries
#define PPL %zmm2
#define PPH %zmm3
// Zero-extended multiplicand
#define Y %zmm4
// Mask for keeping only low 32 bits of each 64-bit word
#define LSW %zmm5
// NB: Registers zmm6-zmm15 are intentionally not used due to the X64 calling convention designating them as callee-save
// Accumulators for partial product vectors
// NB: in case of changes:
// - ACC and A0L must be the same
// - all references to xmm16 must refer to the low 128 bits of ACC
#define ACC %zmm16
#define A0L %zmm16
#define A1L %zmm17
#define A2L %zmm18
#define A3L %zmm19
#define A4L %zmm20
#define A5L %zmm21
#define A6L %zmm22
#define A7L %zmm23
#define A0H %zmm24
#define A1H %zmm25
#define A2H %zmm26
#define A3H %zmm27
#define A4H %zmm28
#define A5H %zmm29
#define A6H %zmm30
#define A7H %zmm31
// Macro for adding up (halves of) sums of (halves of) partial products
#define ADDPP(AxH, AyL, AyH, AzL, I) \
vpsrlq $32, ACC, PPL; \
valignd $2, ACC, ACC, ACC{%k1}{z}; \
vpaddq PPL, ACC, ACC; \
vpsrlq $32, AxH, AxH; vpaddq AxH, ACC, ACC; \
vpsrlq $32, AyL, AyL; vpaddq AyL, ACC, ACC; \
vpandq LSW, AyH, PPL; vpaddq PPL, ACC, ACC; \
vpandq LSW, AzL, PPL; vpaddq PPL, ACC, ACC; \
valignd $16-I, ACC, ACC, %zmm0{%k2}; \
kaddw %k2, %k2, %k2
.global innerproduct256, innerproduct256_asm
.text
.p2align 6,,63
//////////////////////////////////////////////////
// C callable wrapper for innerproduct256_asm
//////////////////////////////////////////////////
// Return value (544 bits) is in %zmm1 (high 32 bits) and %zmm0 (low 256 bits).
innerproduct256:
// Pass parameters unchanged
call innerproduct256_asm
// Save return value to z (unchanged by the call above)
vmovdqu64 %zmm0, (PZ)
vmovd %xmm1, %eax
mov %eax, 64(PZ)
ret
.p2align 4,,15
//////////////////////////////////////////////////
// Assembler core, return value in zmm1:zmm0
//////////////////////////////////////////////////
// Note: Do not call this from C; use the C wrapper.
innerproduct256_asm:
// Create mask for low dword in each qword
vpcmpeqb %ymm0, %ymm0, %ymm0
vpmovzxdq %ymm0, LSW
// Clear accumulator registers
vpxorq A0L, A0L, A0L
vmovdqa64 A0L, A1L
vmovdqa64 A0L, A2L
vmovdqa64 A0L, A3L
vmovdqa64 A0L, A4L
vmovdqa64 A0L, A5L
vmovdqa64 A0L, A6L
vmovdqa64 A0L, A7L
vmovdqa64 A0L, A0H
vmovdqa64 A0L, A1H
vmovdqa64 A0L, A2H
vmovdqa64 A0L, A3H
vmovdqa64 A0L, A4H
vmovdqa64 A0L, A5H
vmovdqa64 A0L, A6H
vmovdqa64 A0L, A7H
// Skip accumulation of partial products if the input length is zero
test LEN, LEN
jz AddPP
//////////////////////////////////////////////////
// Accumulate partial product halves
//////////////////////////////////////////////////
Loop:
vpmovzxdq (PY), Y
prefetchnta 8192(PY)
prefetchnta 8192(PX)
add $32, PY
vpmuludq 0*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A0L, A0L; vpaddq PPH, A0H, A0H
vpmuludq 1*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A1L, A1L; vpaddq PPH, A1H, A1H
vpmuludq 2*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A2L, A2L; vpaddq PPH, A2H, A2H
vpmuludq 3*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A3L, A3L; vpaddq PPH, A3H, A3H
vpmuludq 4*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A4L, A4L; vpaddq PPH, A4H, A4H
vpmuludq 5*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A5L, A5L; vpaddq PPH, A5H, A5H
vpmuludq 6*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A6L, A6L; vpaddq PPH, A6H, A6H
vpmuludq 7*4(PX){1to8}, Y, PPL; vpsrlq $32, PPL, PPH; vpandq LSW, PPL, PPL; vpaddq PPL, A7L, A7L; vpaddq PPH, A7H, A7H
add $32, PX
dec LEN
jnz Loop
//////////////////////////////////////////////////
// Add partial products
//////////////////////////////////////////////////
AddPP:
// Load mask register values
mov $0x1555, %eax
kmovd %eax, %k1
mov $1, %eax
kmovd %eax, %k2
// ACC starts with the value of A0L
valignd $16, ACC, ACC, %zmm0{%k2}{z} // Store least significant 32 bits of ACC
kshiftlw $1, %k2, %k2
//////////////////////////////////////////////////
vpsrlq $32, ACC, PPL
valignd $2, ACC, ACC, ACC{%k1}{z}
vpaddq PPL, ACC, ACC
vpandq LSW, A0H, PPL
vpaddq PPL, ACC, ACC
vpandq LSW, A1L, PPL
vpaddq PPL, ACC, ACC
// Word 1 of z is ready
valignd $15, ACC, ACC, %zmm0{%k2}
kshiftlw $1, %k2, %k2
//////////////////////////////////////////////////
ADDPP(A0H, A1L, A1H, A2L, 2);
ADDPP(A1H, A2L, A2H, A3L, 3);
ADDPP(A2H, A3L, A3H, A4L, 4);
ADDPP(A3H, A4L, A4H, A5L, 5);
ADDPP(A4H, A5L, A5H, A6L, 6);
ADDPP(A5H, A6L, A6H, A7L, 7);
//////////////////////////////////////////////////
vpsrlq $32, ACC, PPL;
valignd $2, ACC, ACC, ACC{%k1}{z};
vpaddq PPL, ACC, ACC;
vpsrlq $32, A6H, A6H; vpaddq A6H, ACC, ACC;
vpsrlq $32, A7L, A7L; vpaddq A7L, ACC, ACC;
vpandq LSW, A7H, PPL; vpaddq PPL, ACC, ACC;
valignd $16-8, ACC, ACC, %zmm0{%k2}
kshiftlw $1, %k2, %k2
//////////////////////////////////////////////////
vpsrlq $32, ACC, PPL;
valignd $2, ACC, ACC, ACC{%k1}{z};
vpaddq PPL, ACC, ACC;
vpsrlq $32, A7H, A7H; vpaddq A7H, ACC, ACC;
valignd $16-9, ACC, ACC, %zmm0{%k2}
kshiftlw $1, %k2, %k2
//////////////////////////////////////////////////
#undef ADDPP
#define ADDPP(I) \
vpsrlq $32, ACC, PPL; \
valignd $2, ACC, ACC, ACC{%k1}{z}; \
vpaddq PPL, ACC, ACC; \
valignd $16-I, ACC, ACC, %zmm0{%k2}; \
kshiftlw $1, %k2, %k2
ADDPP(10);
ADDPP(11);
ADDPP(12);
ADDPP(13);
ADDPP(14);
ADDPP(15);
//////////////////////////////////////////////////
vpsrlq $32, ACC, PPL;
valignd $2, ACC, ACC, ACC{%k1}{z};
vpaddq PPL, ACC, ACC;
vmovdqa64 ACC, %zmm1{%k1}{z}
ret
//////////////////////////////////////////////////
// No executable stack
.section .note.GNU-stack
|
a16z/vectorized-fields
| 2,935
|
src/assembly/modadd256.S
|
/*
* void modadd256(uint64_t *z, const uint64_t *x, const uint64_t *y, uint64_t xy_len, const uint64_t m[6])
*
* Copyright (C) 2024 Dag Arne Osvik
*
* Modular addition of vectors over finite fields up to 256 bits.
*
* Parameters:
* z out Result. Vector of canonical least non-negative residues.
* x,y in Pointers to vectors of length xy_len.
* Elements are 256-bit little-endian canonical residues.
* xy_len in Length of input vectors. Limited to 2^59-1.
* m in Pointer to 6-qword array containing the modulus m, its negative inverse mod 2^64 and 2^288/m.
*/
.global modadd256
//////////////////////////////////////////////////
// Register roles
//////////////////////////////////////////////////
// AMD64 WIN64
// %rax X0 X0
// %rcx LEN PZ
// %rdx PY PX
// %rbx X1 X1
// %rsp - -
// %rbp X2 X2
// %rsi PX X3
// %rdi PZ PM
// %r8 PM PY
// %r9 X3 LEN
// %r10 X4 X4
// %r11 T0 T0
// %r12 T1 T1
// %r13 T2 T2
// %r14 T3 T3
// %r15 - -
#ifndef WIN64
// AMD64 calling convention
# define PZ %rdi
# define PX %rsi
# define PY %rdx
# define LEN %rcx
# define PM %r8
# define X0 %rax
# define X1 %rbx
# define X2 %rbp
# define X3 %r9
# define X4 %r10
#else
// X64 calling convention
# define PZ %rcx
# define PX %rdx
# define PY %r8
# define LEN %r9
# define PM %rdi
# define X0 %rax
# define X1 %rbx
# define X2 %rbp
# define X3 %rsi
# define X4 %r10
#endif
# define T0 %r11
# define T1 %r12
# define T2 %r13
# define T3 %r14
.text
.p2align 6,,63
modadd256:
#ifndef WIN64
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
#else
movq %rsp, %rax
pushq %rbx
pushq %rbp
pushq %rsi
pushq %rdi
pushq %r12
pushq %r13
pushq %r14
// Load pointer to the modulus from stack
movq 40(%rax), PM
#endif
shlq $5, LEN // 32 bytes per element
jz Done // Zero-length vector, nothing to do
// Change to negatively-indexed pointers
addq LEN, PX
addq LEN, PY
addq LEN, PZ
negq LEN
jmp Loop
.p2align 6,,63
Loop:
// Clear carry and overflow register
xorq X4, X4
// Load x
movq 0*8(PX, LEN), X0
movq 1*8(PX, LEN), X1
movq 2*8(PX, LEN), X2
movq 3*8(PX, LEN), X3
// Add y
addq 0*8(PY, LEN), X0
adcq 1*8(PY, LEN), X1
adcq 2*8(PY, LEN), X2
adcq 3*8(PY, LEN), X3
adcq $0, X4
// Copy x+y to t
movq X0, T0
movq X1, T1
movq X2, T2
movq X3, T3
// Subtract m
subq 0*8(PM), X0
sbbq 1*8(PM), X1
sbbq 2*8(PM), X2
sbbq 3*8(PM), X3
sbbq $0, X4
// Copy x+y-m to t if X4 is zero
testq X4, X4
cmovzq X0, T0
cmovzq X1, T1
cmovzq X2, T2
cmovzq X3, T3
// Copy t to z
movq T0, 0*8(PZ, LEN)
movq T1, 1*8(PZ, LEN)
movq T2, 2*8(PZ, LEN)
movq T3, 3*8(PZ, LEN)
addq $32, LEN
jnz Loop
Done:
#ifndef WIN64
popq %r14
popq %r13
popq %r12
popq %rbp
popq %rbx
#else
popq %r14
popq %r13
popq %r12
popq %rdi
popq %rsi
popq %rbp
popq %rbx
#endif
ret
// No executable stack
.section .note.GNU-stack
|
a16z/vectorized-fields
| 2,951
|
src/assembly/modsub256.S
|
/*
* void modsub256(uint64_t *z, const uint64_t *x, const uint64_t *y, uint64_t xy_len, const uint64_t m[6])
*
* Copyright (C) 2024 Dag Arne Osvik
*
* Modular subtraction of vectors over finite fields up to 256 bits.
*
* Parameters:
* z out Result. Vector of canonical least non-negative residues.
* x,y in Pointers to vectors of length xy_len.
* Elements are 256-bit little-endian canonical residues.
* xy_len in Length of input vectors. Limited to 2^59-1.
* m in Pointer to 6-qword array containing the modulus m, its negative inverse mod 2^64 and 2^288/m.
*/
.global modsub256
//////////////////////////////////////////////////
// Register roles
//////////////////////////////////////////////////
// AMD64 WIN64
// %rax X0 X0
// %rcx LEN PZ
// %rdx PY PX
// %rbx X1 X1
// %rsp - -
// %rbp X2 X2
// %rsi PX X3
// %rdi PZ PM
// %r8 PM PY
// %r9 X3 LEN
// %r10 X4 X4
// %r11 T0 T0
// %r12 T1 T1
// %r13 T2 T2
// %r14 T3 T3
// %r15 - -
#ifndef WIN64
// AMD64 calling convention
# define PZ %rdi
# define PX %rsi
# define PY %rdx
# define LEN %rcx
# define PM %r8
# define X0 %rax
# define X1 %rbx
# define X2 %rbp
# define X3 %r9
# define X4 %r10
#else
// X64 calling convention
# define PZ %rcx
# define PX %rdx
# define PY %r8
# define LEN %r9
# define PM %rdi
# define X0 %rax
# define X1 %rbx
# define X2 %rbp
# define X3 %rsi
# define X4 %r10
#endif
# define T0 %r11
# define T1 %r12
# define T2 %r13
# define T3 %r14
.text
.p2align 6,,63
modsub256:
#ifndef WIN64
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
#else
movq %rsp, %rax
pushq %rbx
pushq %rbp
pushq %rsi
pushq %rdi
pushq %r12
pushq %r13
pushq %r14
// Load pointer to the modulus from stack
movq 40(%rax), PM
#endif
shlq $5, LEN // 32 bytes per element
jz Done // Zero-length vector, nothing to do
// Change to negatively-indexed pointers
addq LEN, PX
addq LEN, PY
addq LEN, PZ
negq LEN
jmp Loop
.p2align 6,,63
Loop:
// Clear carry and underflow register
xorq X4, X4
// Load x
movq 0*8(PX, LEN), X0
movq 1*8(PX, LEN), X1
movq 2*8(PX, LEN), X2
movq 3*8(PX, LEN), X3
// Subtract y
subq 0*8(PY, LEN), X0
sbbq 1*8(PY, LEN), X1
sbbq 2*8(PY, LEN), X2
sbbq 3*8(PY, LEN), X3
sbbq $0, X4
// Copy x-y to t
movq X0, T0
movq X1, T1
movq X2, T2
movq X3, T3
// Add m
addq 0*8(PM), X0
adcq 1*8(PM), X1
adcq 2*8(PM), X2
adcq 3*8(PM), X3
// Copy x-y+m to t if X4 is nonzero (x-y underflowed)
testq X4, X4
cmovnzq X0, T0
cmovnzq X1, T1
cmovnzq X2, T2
cmovnzq X3, T3
// Copy t to z
movq T0, 0*8(PZ, LEN)
movq T1, 1*8(PZ, LEN)
movq T2, 2*8(PZ, LEN)
movq T3, 3*8(PZ, LEN)
addq $32, LEN
jnz Loop
Done:
#ifndef WIN64
popq %r14
popq %r13
popq %r12
popq %rbp
popq %rbx
#else
popq %r14
popq %r13
popq %r12
popq %rdi
popq %rsi
popq %rbp
popq %rbx
#endif
ret
// No executable stack
.section .note.GNU-stack
|
a16z/vectorized-fields
| 5,585
|
src/assembly/modip256_mont.S
|
/*
* void modip256_mont(uint64_t z[4], const uint64_t *x, const uint64_t *y, uint32_t xy_len, const uint64_t m[6])
*
* Copyright (C) 2024 Dag Arne Osvik
*
* Modular inner product for vectors over finite fields from 225 bits up to 256 bits using Montgomery form.
*
* Dependency: innerproduct256() is used to calculate the integer inner product of the vectors.
*
* Parameters:
* z out Result in Montgomery form. Canonical least non-negative residue.
* x,y in Pointers to vectors of length xy_len.
* Elements are 256-bit little-endian residues in Montgomery form.
* xy_len in Length of input vectors. Limited to 2^32-1 by innerproduct256().
* m in Pointer to 6-qword array containing the modulus m, its negative inverse mod 2^64 and 2^288/m.
*/
.global modip256_mont
.extern innerproduct256_asm
.text
.p2align 6,,63
//////////////////////////////////////////////////
// Register roles
//////////////////////////////////////////////////
#ifndef WIN64
// AMD64 calling convention
# define PZ %rdi
//define PX %rsi
//define PY %rdx
//define LEN %ecx
# define PM %r8
#else
// X64 calling convention
# define PZ %rcx
//define PX %rdx
//define PY %r8
//define LEN %r9d
# define PM %r8
#endif
#define INV 32(PM)
#define MU 40(PM)
#ifndef WIN64
# define PL %rax
# define PH %rcx
# define T0 %r10
# define T1 %r11
# define T2 %r12
# define T3 %r13
# define T4 %r14
#else
# define PL %rax
# define PH %r9
# define T0 %r10
# define T1 %r11
# define T2 %r12
# define T3 %r13
# define T4 %r14
#endif
modip256_mont:
//////////////////////////////////////////////////
// Get inner product from innerproduct256_asm
//////////////////////////////////////////////////
// innerproduct256_asm() modifies LEN, PX and PY, but leaves PZ and PM intact.
// It returns its 544-bit (72-byte) result in zmm1:zmm0.
// After innerproduct256_asm() only the modular reduction remains to be computed.
call innerproduct256_asm
#ifdef WIN64
// Load pointer to the modulus from stack
mov 40(%rsp), PM
// Save registers
push %rbx
#endif
push %r14
push %r13
push %r12
// Extract the 4 least significant qwords of %zmm0
vmovq %xmm0, T1; valignq $1, %zmm0, %zmm1, %zmm0 // Shift in low word from zmm1
vmovq %xmm0, T2; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, T3; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, T4; valignq $1, %zmm0, %zmm0, %zmm0
xorq T0, T0
//////////////////////////////////////////////////
// Montgomery reduction
//////////////////////////////////////////////////
// See Handbook of Applied Cryptography, Algorithm 14.32.
movq INV, %rdx // Load negative inverse mod 2^64
mulx T1, %rdx, PH
mulx 0*8(PM), PL, PH; add PL, T1; adc PH, T2
mulx 2*8(PM), PL, PH; adc PL, T3; adc PH, T4; adc $0, T0
mulx 1*8(PM), PL, PH; add PL, T2; adc PH, T3
mulx 3*8(PM), PL, PH; adc PL, T4; adc PH, T0; adc $0, T1
movq INV, %rdx
mulx T2, %rdx, PH
mulx 0*8(PM), PL, PH; add PL, T2; adc PH, T3
mulx 2*8(PM), PL, PH; adc PL, T4; adc PH, T0; adc $0, T1
mulx 1*8(PM), PL, PH; add PL, T3; adc PH, T4
mulx 3*8(PM), PL, PH; adc PL, T0; adc PH, T1; adc $0, T2
movq INV, %rdx
mulx T3, %rdx, PH
mulx 0*8(PM), PL, PH; add PL, T3; adc PH, T4
mulx 2*8(PM), PL, PH; adc PL, T0; adc PH, T1; adc $0, T2
mulx 1*8(PM), PL, PH; add PL, T4; adc PH, T0
mulx 3*8(PM), PL, PH; adc PL, T1; adc PH, T2; adc $0, T3
movq INV, %rdx
mulx T4, %rdx, PH
mulx 0*8(PM), PL, PH; add PL, T4; adc PH, T0
mulx 2*8(PM), PL, PH; adc PL, T1; adc PH, T2; adc $0, T3
mulx 1*8(PM), PL, PH; add PL, T0; adc PH, T1
mulx 3*8(PM), PL, PH; adc PL, T2; adc PH, T3; adc $0, T4
// Add the remaining 5 qwords (9 dwords) from zmm0
vmovq %xmm0, PL; add PL, T0; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, PL; adc PL, T1; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, PL; adc PL, T2; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, PL; adc PL, T3; valignq $1, %zmm0, %zmm0, %zmm0
vmovq %xmm0, PL; adc PL, T4 // T4 < 2^32
//////////////////////////////////////////////////
// Barrett reduction
//////////////////////////////////////////////////
// For explanation of mu, q1, q2, q3, r1, r2, see Handbook of
// Applied Cryptography, Algorithm 14.42.
// q1 is low 32 bits of T4 and high 32 bits of T3
movq T3, %rax
shrd $32, T4, %rax // q1
mulq MU // Multiply by mu. q2 in rdx:rax, q3 in rdx
// 2^32 < mu < 2^64. 0 <= q1 < 2^64. q2 < 2^128.
// r1 is in T4:T3:T2:T1:T0
// Subtract r2 from r1
mulx 0*8(PM), PL, PH; sub PL, T0; sbb PH, T1;
mulx 2*8(PM), PL, PH; sbb PL, T2; sbb PH, T3; sbb $0, T4
mulx 1*8(PM), PL, PH; sub PL, T1; sbb PH, T2;
mulx 3*8(PM), PL, PH; sbb PL, T3; sbb PH, T4
// Two conditional subtractions to guarantee canonicity of the result
// Save the result
mov T0, 0*8(PZ)
mov T1, 1*8(PZ)
mov T2, 2*8(PZ)
mov T3, 3*8(PZ)
// Subtract the modulus
sub 0*8(PM), T0
sbb 1*8(PM), T1
sbb 2*8(PM), T2
sbb 3*8(PM), T3
sbb $0, T4
// If borrow, skip to the end
jb done
// Save the result
mov T0, 0*8(PZ)
mov T1, 1*8(PZ)
mov T2, 2*8(PZ)
mov T3, 3*8(PZ)
// Subtract the modulus
sub 0*8(PM), T0
sbb 1*8(PM), T1
sbb 2*8(PM), T2
sbb 3*8(PM), T3
sbb $0, T4
// If borrow, skip to the end
jb done
// Save result
mov T0, 0*8(PZ)
mov T1, 1*8(PZ)
mov T2, 2*8(PZ)
mov T3, 3*8(PZ)
//////////////////////////////////////////////////
// Cleanup
//////////////////////////////////////////////////
done:
// Restore registers
pop %r12
pop %r13
pop %r14
#ifdef WIN64
pop %rbx
#endif
ret
// No executable stack
.section .note.GNU-stack
|
9front/9front
| 23,114
|
sys/lib/tmac/tmac.s
|
.lg 0
.ds sd /sys/lib/tmac
.\" RT - reset everything to normal state
.de RT
.if \\n(CS \{\
.SR 1
.BG\}
.if !\\n(1T .BG
.ce 0
.if !\\n(IK .if !\\n(IF .if !\\n(IX .if !\\n(BE .if !\\n(FT .di
.ul 0
.if \\n(QP \{\
. ll +\\n(QIu
. in -\\n(QIu
. nr QP -1\}
.if \\n(NX<=1 .if \\n(AJ=0 .if \\n(FT=0 .ll \\n(LLu
.if !\\n(IF \{\
. ps \\n(PS
. ie \\n(VS>=41 .vs \\n(VSu
. el .vs \\n(VSp\}
.ie \\n(IP \{\
. in \\n(I\\n(IRu
. nr IP -1\}
.el .if !\\n(IR \{\
. nr I1 \\n(PIu
. nr I2 0
. nr I3 0
. nr I4 0
. nr I5 0\}
.ft 1
.ta 5n 10n 15n 20n 25n 30n 35n 40n 45n 50n 55n 60n 65n 70n 75n 80n
.hy \\n(HY
.fi
..
. \"IZ - initialization
.de IZ
.so \\*(sd/tmac.sdisp
.nr TN 0
.em EM
. \" ACCENTS say \*'e or \*`e to get e acute or e grave both were 4/10
.ds ' \h'\w'e'u*1/10'\z\(aa\h'-\w'e'u*1/10'
.ds ` \h'\w'e'u*2/10'\z\(ga\h'-\w'e'u*2/10'
. \" UMLAUT \*:u, etc.
.if t .ds : \\v'-0.6m'\\h'(1u-(\\\\n(.fu%2u))*0.13m+0.00m'\\z.\\h'0.2m'\\z.\\h'-((1u-(\\\\n(.fu%2u))*0.13m+0.20m)'\\v'0.6m'
.if n .ds : \z"
. \" TILDE and CIRCUMFLEX
.ds ^ \\\\k:\\h'-\\\\n(.fu+1u/2u*2u+\\\\n(.fu-1u*0.13m+0.06m'\\z^\\h'|\\\\n:u'
.ds ~ \\\\k:\\h'-\\\\n(.fu+1u/2u*2u+\\\\n(.fu-1u*0.13m+0.06m'\\z~\\h'|\\\\n:u'
. \" czech v symbol
.ds v \\\\k:\\\\h'+\\\\w'e'u/4u'\\\\v'-0.6m'\\\\s6v\\\\s0\\\\v'0.6m'\\\\h'|\\\\n:u'
. \" cedilla
.ds , \\\\k:\\\\h'\\\\w'c'u*0.4u'\\\\z,\\\\h'|\\\\n:u'
.so \\*(sd/tmac.srefs
.ch FO \\n(YYu
.if !\\n(FM .nr FM 1i
.nr YY -\\n(FMu
.nr XX 0 1
.nr IP 0
.nr PI 5n
.nr QI 5n
.nr I0 \\n(PIu
.nr PS 10
.nr VS 12
.nr HY 14
.ie n \{\
. if !\\n(PD .nr PD 1v
. nr DV 1v\}
.el \{\
. if !\\n(PD .nr PD 0.3v
. nr DV .5v\}
.nr ML 3v
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.nr IR 0
.nr I0 0
.nr I1 \\n(PIu
.nr TB 0
.nr SJ \\n(.j
.nr LL 6i
.ll \\n(LLu
.nr LT \\n(.l
.lt \\n(LTu
.ev 1
.if !\\n(FL .nr FL \\n(LLu*11u/12u
.ll \\n(FLu
.ps 8
.vs 10p
.ev
.if \\*(CH .ds CH "\(hy \\\\n(PN \(hy
.wh 0 NP
.wh -\\n(FMu FO
.ch FO 16i
.wh -\\n(FMu FX
.ch FO -\\n(FMu
.if t .wh -\\n(FMu/2u BT
.if n .wh -\\n(FMu/2u-1v BT
. \" no overstriking bold or italic; switch underlining to bold italic
. \" (sad historical botch, the .uf font must be 2, 3, or 4)
.if n .uf 4
.if n .bd 3
.nr CW 0-1
.nr GW 0-1
..
.de TM
.if !\\n(IM .if !\\n(MN .pn 0
.so \\*(sd/tmac.scover
.if !\\n(IM .if !\\n(MN .rm IM MF MR
.if n .if !\\n(.T .pi /bin/col
.nr ST 1
.ds QF TECHNICAL MEMORANDUM
.br
.ds MN \\$1
.if !"\\$1"" .nr MM 1
.if !"\\$2"" .nr MC 1
.if !"\\$3"" .nr MG 1
.nr TN 1
.if \\n(.$-1 .ds CA \\$2
.if \\n(.$-2 .ds CC \\$3
.rm RP S0 S2 AX
..
. \" IM - internal memorandum
.de IM
.nr IM 1
.TM "\\$1" "\\$2" "\\$3"
.rm QF
.RA
.rm RA RP MF MR
..
. \" MF - memorandum for file.
.de MF
.nr MN 1
.TM "\\$1" "\\$2" "\\$3"
.rm MR
.rm IM
.RA
.rm RA RP TM
..
. \" MR - memo for record
.de MR
.nr MN 2
.TM "\\$1" "\\$2" "\\$3"
.ds QF MEMORANDUM FOR RECORD
.rm MF
.RA
.rm RA RP IM TM
..
. \" LT - letter
.de LT
.if !\\n(PO .ie n .nr PO 1.5i
.el .nr PO 1.3i
.po \\n(POu
.LP
.rs
.if !"\\$1"" \{\
. vs -2p
.if "\\$1"LT" .ta 3.9i 4.45i
.if !"\\$1"LT" .ta 3.9i 4.45i
. sp .2i
. nf
. if "\\$1"LT" \s36\(FA\s0
. if !"\\$1"LT" \s36\(LH\s0
. br
\s7\l'7i'\s0
.sp
. br
. if !"\\$2"" .ds xR " \\$2
. ds xP 908-582-3000
. if !"\\$3"" .ds xP \\$3
. if "\\$1"LT" \s8\f(HBBell Laboratories\fP \fH600 Mountain Avenue
. if !"\\$1"LT" \s8\f(HBBell Laboratories\fP \fH600 Mountain Avenue
. if !"\\$2"" \\*(xR
Murray Hill, NJ 07974-0636
\\*(xP
. if !"\\$4"" \\$4
. if !"\\$5"" \\$5
. if !"\\$6"" \\$6
. if !"\\$7"" \\$7
.ft 1
.ps
. sp -.75i
. vs
. fi \}
.if n \{\
. sp 1i
. in 4.55i\}
.if t \{\
. sp 1.45i
. in 3.5i\}
.ll 8i
\\*(DY
.ll
.in 0
.br
.if t .sp 3
.if n \{\
. sp
. na\}
.nf
.rm CF
.de SG \" nested defn
.sp 2
.ta 3.5i
Sincerely,
.sp 3
\\\\$1
.ds CH
\\..
..
.de OK
.br
.di
.di OD
..
.de RP \" released paper
.nr ST 2
.pn 0
.rm SG CS TM QF IM MR MF EG
.br
..
.de TR \" Comp. Sci. Tech Rept series.
.nr ST 3
.pn 0
.ds MN \\$1
.rm SG CS TM QF IM MR M EG
.br
..
. \"FP - font position for a family
.de FP
.ds TF \\$1
.if '\\$1'palatino'\{\
. fp 1 R PA
. fp 2 I PI
. fp 3 B PB
. fp 4 BI PX\}
.if '\\$1'lucidabright'\{\
. fp 1 R LucidaBright
. fp 2 I LucidaBright-Italic
. fp 3 B LucidaBright-Demi
. fp 4 BI LucidaBright-DemiItalic
. fp 5 CW LucidaSansCW\}
.if '\\$1'lucidasans'\{\
. fp 1 R LucidaSans
. fp 2 I LucidaSansI
. fp 3 B LucidaSansB
. fp 5 CW LucidaCW\}
.if '\\$1'syntax'\{\
. fp 1 R Syntax
. fp 2 I SyntaxI
. fp 3 B SyntaxB
. fp 5 CW LucidaCW\}
.if '\\$1'century'\{\
. ie '\\*(.T'202'\{\
. fp 1 NR Centsb
. fp 2 NI CentI
. fp 3 NB CentB
. fp 4 NX CentBI\}
. el \{\
. fp 1 NR
. fp 2 NI
. fp 3 NB
. fp 4 NX\}\}
.if '\\$1'helvetica'\{\
. fp 1 H
. fp 2 HI
. fp 3 HB
. fp 4 HX\}
.if '\\$1'bembo'\{\
. ie '\\*(.T'202'\{\
. fp 1 B1 Bembo
. fp 2 B2 BemboI
. fp 3 B3 BemboB
. fp 4 B4 BemboBI\}
. el \{\
. fp 1 B1
. fp 2 B2
. fp 3 B3
. fp 4 B4\}\}
.if '\\$1'optima'\{\
. fp 1 R Optima
. fp 2 I OptimaI
. fp 3 B OptimaB
. fp 4 BI OptimaBI\}
.if '\\$1'souvenir'\{\
. fp 1 R Souvenir
. fp 2 I SouvenirI
. fp 3 B SouvenirB
. fp 4 BI SouvenirBI\}
.if '\\$1'melior'\{\
. fp 1 R Melior
. fp 2 I MeliorI
. fp 3 B MeliorB
. fp 4 BI MeliorBI\}
.if '\\$1'times'\{\
. fp 1 R
. fp 2 I
. fp 3 B
. fp 4 BI\}
..
. \"TL - title and initialization
.de TL
.br
.nr TV 1
.if \\n(IM .rm CS
.if \\n(MN .rm CS
.ME
.rm ME
.di WT
.na
.fi
.ie h .ll \\n(LLu
.el \{\
.ll 5.0i
.if n .if \\n(TN .ll 29
.if t .if \\n(TN .ll 3.5i \}
.ft 3
.ps \\n(PS
.if !\\n(TN \{\
. ps +2
. vs \\n(.s+2
. rm CS\}
.hy 0
.if h .ce 999
..
.de TX
.rs
.sp .5i
.ce 1000
.if n .ul 1000
.ps 12
.ft 3
.vs 15p
.ne 4
.hy 0
.WT
.hy \\n(HY
.ce 0
.ul 0
..
. \" AU - author(s)
.de AU
.nr AV 1
.ad \\n(SJ
.br
.di
.br
.nf
.nr NA +1
.ds R\\n(NA \\$1
.ds E\\n(NA \\$2
.di A\\n(NA
.ll \\n(LLu
.ie t \{\
. ie !\\n(TN .ft 2
. el \{\
. ft 3
. ll 1.4i\}\}
.el \{\
. ie !\\n(TN .ft 1
. el \{\
. ft 3
. ll 16\}\}
.ps \\n(PS
.if h .ce 999
..
.de AX
.ft 1
.rs
.ce 1000
.if n .ul 0
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.if t \{\
. sp
. A1
. sp 0.5
. ns
. I1
. if \\n(NA-1 .sp
. A2
. if \\n(NA-1 .sp 0.5
. ns
. I2
. if \\n(NA-2 .sp
. A3
. if \\n(NA-2 .sp 0.5
. ns
. I3
. if \\n(NA-3 .sp
. A4
. if \\n(NA-3 .sp 0.5
. ns
. I4
. if \\n(NA-4 .sp
. A5
. if \\n(NA-4 .sp 0.5
. ns
. I5
. if \\n(NA-5 .sp
. A6
. if \\n(NA-5 .sp 0.5
. ns
. I6
. if \\n(NA-6 .sp
. A7
. if \\n(NA-6 .sp 0.5
. ns
. I7
. if \\n(NA-7 .sp
. A8
. if \\n(NA-7 .sp 0.5
. ns
. I8
. if \\n(NA-8 .sp
. A9
. if \\n(NA-8 .sp 0.5
. ns
. I9\}
.if n \{\
. sp 2
. A1
. sp
. ns
. I1
. if \\n(NA-1 .sp 2
. A2
. if \\n(NA-1 .sp
. ns
. I2
. if \\n(NA-2 .sp 2
. A3
. if \\n(NA-2 .sp
. ns
. I3
. if \\n(NA-3 .sp 2
. A4
. if \\n(NA-3 .sp
. ns
. I4
. if \\n(NA-4 .sp 2
. A5
. if \\n(NA-4 .sp
. ns
. I5
. if \\n(NA-5 .sp 2
. A6
. if \\n(NA-5 .sp
. ns
. I6
. if \\n(NA-6 .sp 2
. A7
. if \\n(NA-6 .sp
. ns
. I7
. if \\n(NA-7 .sp 2
. A8
. if \\n(NA-7 .sp
. ns
. I8
. if \\n(NA-8 .sp 2
. A9
. if \\n(NA-8 .sp
. ns
. I9\}
..
. \"AI - authors institution
.de AI
.br
.ft 1
.di
.di I\\n(NA
.nf
..
. \"AB - begin an abstract
.de AB
.br
.di
.ul 0
.ce 0
.nr 1T 1
.nr IK 1
.nr KI 1
.di WB
.rs
.nr AJ 1
.ce 1
.ft 2
.if n .ul
.ll \\n(LLu
.ie \\n(.$ \{\
. if !"\\$1"-" .if !"\\$1"no" \\$1
. if !"\\$1"-" .if !"\\$1"no" .sp\}
.el \{\
ABSTRACT
.sp\}
.hy \\n(HY
.ul 0
.ce 0
.fi
.ft 1
.nr OJ \\n(.i
.in +\\n(.lu/12u
.ll -\\n(.lu/12u
.br
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.ti +\\n(PIu
..
. \"AE - end of an abstract
.de AE
.br
.di
.ll \\n(LLu
.ps \\n(PS
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
.nr 1T 0
.nr IK 0
.in \\n(OJu
.nr AJ 0
.di
.ce 0
.if \\n(ST=2 .SY
.if \\n(ST<3 .rm SY
..
. \"S2 - release paper style
. \"SY - cover sheet of released paper
.de SY
.ll \\n(LLu
.ns
.if \\n(TV .TX
.if \\n(AV .AX
.rs
.ce 0
.nf
.sp 3
.ls 1
.pn 2
.WB
.ls
.sp 3v
\\*(DY
.sp |9i
.if \\n(FP .FA
.FG
.if \\n(GA=1 .nr GA 2
.fi
..
. \"S2 - first text page, released paper format
.de S2
.ce 0
.br
.SY
.rm SY
.bp 1
.if \\n(TV .TX
.if \\n(AV .AX
.rs
.ce 0
.ft 1
.ad \\n(SJ
..
. \"S0- mike lesk conserve paper style
.de S0
.ce 0
.br
.ll \\n(LLu
.if \\n(TV+\\n(AV .ns
.if \\n(TV .TX
.if \\n(AV .AX
.if \\n(TV+\\n(AV .rs
.ce 0
.if \\n(TV .sp 2
.ls 1
.if \\n(FP \{\
. FJ
. nf
. FG
. fi
. FK
. nr FP 0\}
.nf
.WB
.ls
.fi
.ad \\n(SJ
..
. \"S3 - CSTR style
.de S3
.rs
.sp |2.25i
.ce 1000
.I1
.if \\n(NA>1 \{\
. sp .5
. I2\}
.if \\n(NA>2 \{\
. sp .5
. I3\}
.if \\n(NA>3 \{\
. sp .5
. I4\}
.if \\n(NA>4 \{\
. sp .5
. I5\}
.if \\n(NA>5 \{\
. sp .5
. I6\}
.if \\n(NA>6 \{\
. sp .5
. I7\}
.if \\n(NA>7 \{\
. sp .5
. I8\}
.if \\n(NA>8 \{\
. sp .5
. I9\}
.sp |4i
. \"check how long title is: can space extra .25 inch if short
.di EZ
.WT
.di
.if \\n(dn<1.5v .if \\n(NA=1 .sp .25i
.ft 1
Computing Science Technical Report No. \\*(MN
.sp
.if t .ft 3
.if n .ul 100
.ps 12
.vs 15p
.hy 0
.WT
.hy \\n(HY
.ft 1
.if n .ul 0
.ps 10
.vs 12p
.sp
.ft 1
.A1
.A2
.A3
.A4
.A5
.A6
.A7
.A8
.A9
.ce 0
.sp |8.5i
.ce 0
\\*(DY
.DZ
.bp 0
.ft 1
.S2
..
. \"SG - signature
.de SG
.br
.KS
.in +2u*\\n(.lu/3u
.sp 4
.A1
.if \\n(NA>1 .sp 4
.A2
.if \\n(NA>2 .sp 4
.A3
.if \\n(NA>3 .sp 4
.A4
.if \\n(NA>4 .sp 4
.A5
.if \\n(NA>5 .sp 4
.A6
.if \\n(NA>6 .sp 4
.A7
.if \\n(NA>7 .sp 4
.A8
.if \\n(NA>8 .sp 4
.A9
.in
.nf
.if \\n(.$<1 .G9
.sp -1
.if \\n(.$>=1 \\$1
.if \\n(.$>=2 \\$2
.if \\n(.$>=3 \\$3
.if \\n(.$>=4 \\$4
.if \\n(.$>=5 \\$5
.if \\n(.$>=6 \\$6
.if \\n(.$>=7 \\$7
.if \\n(.$>=8 \\$8
.if \\n(.$>=9 \\$9
.fi
.br
.KE
..
. \"Tables. TS - table start, TE - table end
.de TS
.br
.if !\\n(1T .RT
.ul 0
.ti \\n(.iu
.if t .sp 0.5
.if n .sp
.if \\$1H .TQ
.nr IX 1
..
.de TQ
.di TT
.nr IT 1
..
.de TH
.if \\n(.d>0.5v \{\
. nr T. 0
. T# 0\}
.di
.nr TQ \\n(.i
.nr HT 1
.in 0
.mk #a
.mk #b
.mk #c
.mk #d
.mk #e
.mk #f
.TT
.in \\n(TQu
.mk #T
..
.de TE
.nr IX 0
.if \\n(IT .if !\\n(HT \{\
. di
. nr EF \\n(.u
. nf
. TT
. if \\n(EF .fi\}
.nr IT 0
.nr HT 0
.if n .sp 1
.if t .sp 0.5
.rm a+ b+ c+ d+ e+ f+ g+ h+ i+ j+ k+ l+ n+ m+
.rr 32 33 34 35 36 37 38 40 79 80 81 82
.rr a| b| c| d| e| f| g| h| i| j| k| l| m|
.rr a- b- c- d- e- f- g- h- i- j- k- l- m-
..
.so \*(sd/tmac.skeep
.de EQ \"equation, breakout and display
.nr EF \\n(.u
.rm EE
.nr LE 1 \" 1 is center
.ds EL \\$1
.if "\\$1"L" \{\
. ds EL \\$2
. nr LE 0\}
.if "\\$1"C" .ds EL \\$2
.if "\\$1"R" \{\
. ds EL \\$2 \" 2 is right adjust
. nr LE 2\}
.if "\\$1"I" \{\
. nr LE 0
. if "\\$3"" .ds EE \\h'|10n'
. el .ds EE \\h'\\$3'
. ds EL \\$2\}
.if \\n(YE .nf
.di EZ
..
.de EN \" end of a displayed equation
.br
.di
.rm EZ
.nr ZN \\n(dn
.if \\n(ZN .if !\\n(YE .LP
.if !\\n(ZN .if !"\\*(EL"" .nr ZN 1
.if \\n(ZN \{\
. ie "\\n(.z"" \{\
. if t .if !\\n(nl=\\n(PE .sp .5
. if n .if !\\n(nl=\\n(PE .sp 1\}
. el \{\
. if t .if !\\n(.d=\\n(PE .sp .5
. if n .if !\\n(.d=\\n(PE .sp 1\}\}
'pc
.if \\n(BD .nr LE 0 \" don't center if block display or mark/lineup
.if \\n(MK \{\
. if \\n(LE=1 .ds EE \\h'|10n'
. nr LE 0\}
'lt \\n(.lu
.if !\\n(EP .if \\n(ZN \{\
. if \\n(LE=1 .tl \(ts\(ts\\*(10\(ts\\*(EL\(ts
. if \\n(LE=2 .tl \(ts\(ts\(ts\\*(10\\*(EL\(ts
. if !\\n(LE \{\
. if !\\n(BD .tl \(ts\\*(EE\\*(10\(ts\(ts\\*(EL\(ts
. if \\n(BD .if \\n(BD<\\w\(ts\\*(10\(ts .nr BD \\w\(ts\\*(10\(ts
. if \\n(BD \!\\*(10\\t\\*(EL\}\}
.if \\n(EP .if \\n(ZN \{\
. if \\n(LE=1 .tl \(ts\\*(EL\(ts\\*(10\(ts\(ts
. if \\n(LE=2 .tl \(ts\\*(EL\(ts\(ts\\*(10\(ts
. if !\\n(LE \{\
. if !\\n(BD .tl \(ts\\*(EL\\*(EE\\*(10\(ts\(ts\(ts
. if \\n(BD .if \\n(BD<\\w\(ts\\*(10\(ts .nr BD \\w\(ts\\*(10\(ts
. if \\n(BD \!\\h'-\\\\n(.iu'\\*(EL\\h'|0'\\*(10\}\}
'lt \\n(LLu
'pc %
.if \\n(YE .if \\n(EF .fi
.if t .if \\n(ZN .sp .5
.if n .if \\n(ZN .sp
.ie "\\n(.z"" .nr PE \\n(nl
.el .nr PE \\n(.d
..
.de PS \" start picture
. \" $1 is height, $2 is width, both in inches
.if \\$1>0 .sp .35
.ie \\$1>0 .nr $1 \\$1
.el .nr $1 0
.in (\\n(.lu-\\$2)/2u
.ne \\$1
..
.de PE \" end of picture
.in
.if \\n($1>0 .sp .65
..
. \" .P1/.P2 macros for programs
.
.nr XP 1 \" delta point size for program
.nr XV 1p \" delta vertical for programs
.nr XT 8 \" delta tab stop for programs
.nr DV .5v \" space before start of program
.
.de P1
.br
.nr v \\n(.v
.nr i 2m
.if \\n(.$ .nr i \\$1
.di p1
.in \\niu
.nf
.ps -\\n(XP
.vs -\\n(XVu
.ft CW
.nr t \\n(XT*\\w'x'u
.ta 1u*\\ntu 2u*\\ntu 3u*\\ntu 4u*\\ntu 5u*\\ntu 6u*\\ntu 7u*\\ntu 8u*\\ntu 9u*\\ntu 10u*\\ntu 11u*\\ntu 12u*\\ntu 13u*\\ntu 14u*\\ntu
..
.
.de P2
.br
.ps \\n(PS
.vs \\n(VSp
.vs \\nvu
.ft 1
.in 0
.di
.br
.sp \\n(DVu
.RT
.if \\n(.$=0 .ne \\n(dnu \" -\\n(DVu
.nf
.p1
.sp \\n(DVu
.RT
..
.
.de ME
.nr SJ \\n(.j
.if \\n(LL .nr LT \\n(LL
.nr YE 1
.if !\\n(PO .nr PO \\n(.o
.if \\n(mo-0 .ds MO January
.if \\n(mo-1 .ds MO February
.if \\n(mo-2 .ds MO March
.if \\n(mo-3 .ds MO April
.if \\n(mo-4 .ds MO May
.if \\n(mo-5 .ds MO June
.if \\n(mo-6 .ds MO July
.if \\n(mo-7 .ds MO August
.if \\n(mo-8 .ds MO September
.if \\n(mo-9 .ds MO October
.if \\n(mo-10 .ds MO November
.if \\n(mo-11 .ds MO December
.if \\n(dw-0 .ds DW Sunday
.if \\n(dw-1 .ds DW Monday
.if \\n(dw-2 .ds DW Tuesday
.if \\n(dw-3 .ds DW Wednesday
.if \\n(dw-4 .ds DW Thursday
.if \\n(dw-5 .ds DW Friday
.if \\n(dw-6 .ds DW Saturday
.nr yP (\\n(yr+2000)/100)
.nr yD (\\n(yr%100
.af yD 01
.if "\\*(DY"" .ds DY \\*(MO \\n(dy, \\n(yP\\n(yD
.if "\\*(CF"" .if n .ds CF "\\*(DY
..
. \"EM end up macro - process left over keep-release
.de EM
.br
.if \\n(AJ .tm Syntax error: no .AE
.if \\n(IF .ab Missing .FE somewhere
.if t .if \\n(TB=0 .wh -1p CM
.if \\n(TB \{\&\c
' bp
. NP
. ch CM 160\}
..
. \"NP new page
.de NP
.rr PE
.if \\n(FM+\\n(HM>=\\n(.p \{\
. tm Margins bigger than page length.
. ab
. ex\}
.if t .CM
.if !\\n(HM .nr HM 1i
'sp \\n(HMu/2u
.ev 1
.nr PX \\n(.s
.nr PF \\n(.f
.nr PV \\n(.v
.lt \\n(LTu
.ps \\n(PS
.vs \\n(PS+2
.ft 1
.if \\n(PO .po \\n(POu
.PT
.ps \\n(PX
.vs \\n(PVu
.ft \\n(PF
.ev
'sp |\\n(HMu
.nr XX 0 1
.nr YY 0-\\n(FMu
.ch FO 16i
.ch FX 17i
.ch FO \\n(.pu-\\n(FMu
.ch FX \\n(.pu-\\n(FMu
.if \\n(MF .FV
.nr MF 0
.mk
.os
.ev 1
.if !\\n(TD .if \\n(TC<5 .XK
.nr TC 0
.ns
.ev
.nr TQ \\n(.i
.nr TK \\n(.u
.if \\n(IT \{\
. in 0
. nf
. TT
. in \\n(TQu
. if \\n(TK .fi\
\}
.mk #T
....if t .if \\n(.o+\\n(LL>7.75i .tm Offset + line length exceeds 7.75 inches, too wide
..
.de XK
.nr TD 1
.nf
.ls 1
.in 0
.rn KJ KL
.KL
.rm KL
.if "\\n(.z"KJ" .di
.nr TB 0
.if "\\n(.z"KJ" .nr TB 1
.br
.in
.ls
.fi
.if (\\n(nl+1v)>(\\n(.p-\\n(FM) \{\
. if \\n(NX>1 .RC
. if \\n(NX<=1 .bp\}
.nr TD 0
..
.de KD
.nr KM 0
.if "\\n(.z"" .if \\$2>0 .if \\n(nl>\\n(HM \{\
. if (\\n(nl+1v)<(\\n(.p-\\n(FM) .di KJ \" full page figure must have new page
. sp 15i\}
.if "\\n(.z"" .if \\n(nl>\\n(HM .if \\$2=0 .if (\\n(nl+1v)>(\\n(.p-\\n(FM) .sp 15i
.if "\\n(.z"KJ" .nr KM 1 \" KM is 1 if in a rediversion of keeps
.if \\n(KM>0 \!.KD \\$1 \\$2
.nr KR \\n(.t
.if \\n(nl<=\\n(HM .nr KR 32767
.if \\n(KM=0 \{\
. if \\n(KR<\\$1 \{\
. di KJ
. nr KM 1\}
. if \\$2>0 .if (\\n(nl+1v)>(\\n(.p-\\n(FM) .sp 15i\}
.rs
.if \\n(KM=0 .if \\$2>0 .sp \\n(.tu-\\$1u
..
.de PT
.lt \\n(LLu
.pc %
.nr PN \\n%
.if \\n%-1 .tl \\*(LH\\*(CH\\*(RH
.lt \\n(.lu
..
. \"FO - footer of page
.de FO
.rn FO FZ
.if \\n(IT>0 \{\
. nr T. 1
. if \\n(FC=0 .T# 1
. br\}
.nr FC +1
.if \\n(NX<2 .nr WF 0
.nr dn 0
.if \\n(FC<=1 .if \\n(XX .XF
.rn FZ FO
.nr MF 0
.if \\n(dn .nr MF 1
.if !\\n(WF \{\
. nr YY 0-\\n(FMu
. ch FO \\n(YYu\}
.if !\\n(dn .nr WF 0
.if \\n(FC<=1 .if \\n(XX=0 \{\
. if \\n(NX>1 .RC
. if \\n(NX<=1 'bp\}
.nr FC -1
.if \\n(ML>0 .ne \\n(MLu
..
. \"2C - begin double column
.de 2C
.MC \" default MC is double column
..
.de MC \" multiple columns- arg is line length
.nr L1 \\n(LL*7/15
.if \\n(CW>=0 .nr L1 \\n(CWu
.if \\n(.$ .nr L1 \\$1n
.if \\n(GW>=0 .nr GW \\n(GWu
.if \\n(.$>1 .nr GW \\$2n
.nr NQ \\n(LL/\\n(L1
.if \\n(NQ<1 .nr NQ 1
.if \\n(NQ>2 .if (\\n(LL%\\n(L1)=0 .nr NQ -1
.if !\\n(1T \{\
. BG
. if n .sp 4
. if t .sp 2\}
.if \\n(NX=0 .nr NX 1
.if !\\n(NX=\\n(NQ \{\
. RT
. if \\n(NX>1 .bp
. mk
. nr NC 1
. po \\n(POu\}
.if \\n(NQ>1 .hy \\n(HY
.nr NX \\n(NQ
.if \\n(NX>1 .nr CW \\n(L1
.ll \\n(L1u
.nr FL \\n(L1u*11u/12u
.if \\n(NX>1 .if \\n(GW<0 .nr GW (\\n(LL-(\\n(NX*\\n(L1))/(\\n(NX-1)
.nr RO \\n(L1+\\n(GW
.ns
..
.de RC
.ie \\n(NC>=\\n(NX .C2
.el .C1
..
.de C1
.rt
.po +\\n(ROu
.nr NC +1
.if \\n(NC>\\n(NX .nr NC 1
.nr XX 0 1
.nr YY 0-\\n(FMu
.if \\n(MF .FV
.ch FX \\n(.pu-\\n(FMu
.ev 1
.if \\n(TB .XK
.nr TC 0
.ev
.nr TQ \\n(.i
.if \\n(IT \{\
. in 0
. TT
. in \\n(TQu\}
.mk #T
.ns
..
.de C2
.po \\n(POu
.nr NC +1
.if \\n(NC>\\n(NX .nr NC 1
'bp
..
. \"1C - return to single column format
.de 1C
.MC \\n(LLu
.hy \\n(HY
..
.de MH
Bell Laboratories
Murray Hill, New Jersey 07974
..
.de PY
Bell Laboratories
Piscataway, New Jersey 08854
..
.de AW
Bell Laboratories
2018 Antwerp, Belgium
..
.de BT
.nr PX \\n(.s
.nr PF \\n(.f
.ft 1
.ps \\n(PS
'lt \\n(LTu
.po \\n(POu
.if \\n%>0 .tl \(ts\\*(LF\(ts\\*(CF\(ts\\*(RF\(ts
.ft \\n(PF
.ps \\n(PX
..
. \"PP - paragraph
.de PP
.RT
.if \\n(1T .sp \\n(PDu
.ne 2v
.ti +\\n(PIu
..
. \"SH - (unnumbered) section heading
.de SH
.ti \\n(.iu
.RT
.ie \\n(1T .sp 1
.el .BG
.RT
.ne 4
.ft 3
.if n .ul 1000
..
. \"NH - numbered heading
.de N{
.RT
.ie \\n(1T .sp 1
.el .BG
.RT
.ne 4
.ft 3
.if n .ul 1000
.nr NS \\$1
.if !\\n(.$ .nr NS 1
.if !\\n(NS .nr NS 1
.nr H\\n(NS +1
.if !\\n(NS-4 .nr H5 0
.if !\\n(NS-3 .nr H4 0
.if !\\n(NS-2 .nr H3 0
.if !\\n(NS-1 .nr H2 0
.if !\\$1 .if \\n(.$ .nr H1 1
.ds SN \\n(H1.
.ti \\n(.iu
.if \\n(NS-1 .as SN \\n(H2.
.if \\n(NS-2 .as SN \\n(H3.
.if \\n(NS-3 .as SN \\n(H4.
.if \\n(NS-4 .as SN \\n(H5.
..
.de NH
.N{ \\$1
\\*(SN
..
. \"BG - begin, execute at first PP
.de BG
.br
.ME
.rm ME
.di
.ce 0
.nr KI 0
.hy \\n(HY
.nr 1T 1
.nr CS 0
.S\\n(ST
.rm S0 S1 S2 S3 OD OK TX AX WT CS TM IM MF MR RP I1 I2 I3 I4 I5 CB E1 E2
.de TL
.ft 3
.sp
.if n .ul 100
.ce 100
.ps +2
\\..
.de AU
.ft 2
.if n .ul 0
.ce 100
.sp
.NL
\\..
.de AI
.ft 1
.ce 100
.if n .ul 0
.if n .sp
.if t .sp .5
.NL
\\..
.RA
.rm RA
.rn FJ FS
.rn FK FE
.nf
.ev 1
.ps \\n(PS-2
.vs \\n(.s+2p
.ev
.if !\\n(KG .nr FP 0
.if \\n(GA>1 .if \\n(KG=0 .nr GA 0 \" next UNIX must be flagged.
.nr KG 0
.if \\n(FP \{\
. FS
. FG
. FE\}
.br
.if n .if \\n(TV .sp 2
.if t .if \\n(TV .sp 1
.fi
.ll \\n(LLu
.ev 1
.if !\\n(FL .nr FL \\n(LLu*11u/12u
.ll \\n(FLu
.ev
..
.de RA \"redefine abstract macros
.de AB
.br
.if !\\n(1T .BG
.ce 1
.sp 1
.ie \\n(.$ \{\
. if !"\\$1"-" .if !"\\$1"no" \{\
\\$1
.sp\}\}
.el \{\
ABSTRACT
.sp\}
.sp 1
.nr AJ 1
.in +\\n(.lu/12u
.ll -\\n(.lu/12u
.RT
\\..
.de AE
.nr AJ 0
.br
.in 0
.ll \\n(LLu
.ie \\n(VS>=41 .vs \\n(VSu
.el .vs \\n(VSp
\\..
..
. \"IP - indented paragraph
.de IP
.RT
.if !\\n(IP .nr IP +1
.ie \\n(ID>0 .sp \\n(IDu
.el .sp \\n(PDu
.nr IU \\n(IR+1
.if \\n(.$>1 .nr I\\n(IU \\n(I\\n(IRu+\\$2n
.if \\n(I\\n(IU=0 .nr I\\n(IU \\n(PIu+\\n(I\\n(IRu
.in \\n(I\\n(IUu
.nr TY \\n(TZ-\\n(.i
.nr JQ \\n(I\\n(IU-\\n(I\\n(IR
.ta \\n(JQu \\n(TYuR
.if \\n(.$ \{\
.ti \\n(I\\n(IRu
\&\\$1\t\c
.\}
..
. \"LP - left aligned (block) paragraph
.de LP
.ti \\n(.iu
.RT
.if \\n(1T .sp \\n(PDu
..
.de QP
.ti \\n(.iu
.RT
.if \\n(1T .sp \\n(PDu
.ne 1.1
.nr QP 1
.in +\\n(QIu
.ll -\\n(QIu
.ti \\n(.iu
..
. \"IE - synonym for .LP
.de IE
.LP
..
. \"RS - prepare for double indenting
.de RS
.nr IS \\n(IP
.RT
.nr IP \\n(IS
.nr IR \\n(IU
.nr IU +1
.if !\\n(I\\n(IR .nr I\\n(IR \\n(I\\n(IU+\\n(PIu
.in \\n(I\\n(IRu
.nr TY \\n(TZ-\\n(.i
.ta \\n(TYuR
..
. \"RE - retreat to the left
.de RE
.nr IS \\n(IP
.RT
.nr IP \\n(IS
.nr IU \\n(IR
.if \\n(IR>0 .nr IR -1
.in \\n(I\\n(IRu
..
.de TC
.nr TZ \\n(.lu
.if \\n(.$ .nr TZ \\$1n
.ta \\n(TZuR
..
.de TD
.LP
.nr TZ 0
..
. \"CM - cut mark
.de CM
.po 0
.lt 7.6i
.ft 1
.ps 10
.vs 4p
.if "\\*(.T"aps" .tl '--''--'
.po
.vs
.lt
.ps
.ft
..
. \" fontname(CW) fontstr(\f(CW) first_arg goes_after goes_before
.de OF \" this is completely WRONG if any argument contains "'s
.nr PQ \\n(.f
.hy 0
.if t .if "\\$3"" .ft \\$1
.if t .if !"\\$3"" \{\
\&\\$5\\$2\\$3\\f\\n(PQ\\$4
.hy \\n(HY\}
.if n \{\
. if \\n(.$=5 \&\\$5
. ie "\\$3"" .ul 1000
. el .ul 1
. if \\n(.$=3 \&\\$3
. if \\n(.$>3 \&\\$3\\c
. if \\n(.$>3 \&\\$4
. hy \\n(HY\}
..
. \"B - bold font
.de B
.OF 3 \\f3 "\\$1" "\\$2" "\\$3"
..
.de BI \" bold italic -- only on 202
.OF 4 \\f4 "\\$1" "\\$2" "\\$3"
..
. \"R - Roman font
.de R
.nr PQ \\n(.f
.ft 1
.ie \\n(.$>0 \&\\$1\f\\n(PQ\\$2
.el .if n .ul 0
..
. \"I - italic font
.de I
.OF 2 \\f2 "\\$1" "\\$2" "\\$3"
..
. \"CW - constant width font
.de CW
.nr PQ \\n(.f
.if t .if \\n(.$>0 \%\&\\$3\f(CW\\$1\f\\n(PQ\&\\$2
.if t .if \\n(.$=0 .OF CW \\f(CW "\\$1" "\\$2" "\\$3"
.if n .OF CW \\f(CW "\\$1" "\\$2" "\\$3"
..
. \"TA - tabs set in ens or chars
.de TA
.ta \\$1n \\$2n \\$3n \\$4n \\$5n \\$6n \\$7n \\$8n \\$9n
..
. \"SM - make smaller size
.de SM
.ie \\n(.$ \&\\$3\s-2\\$1\s0\\$2
.el .ps -2
..
. \"LG - make larger size
.de LG
.ps +2
..
. \"NL - return to normal size
.de NL
.ps \\n(PS
..
. \"DA - force date; ND - no date or new date.
.de DA
.if \\n(.$ .ds DY \\$1 \\$2 \\$3 \\$4
.ds CF \\*(DY
..
.de ND
.ME
.rm ME
.ds DY \\$1 \\$2 \\$3 \\$4
.rm CF
..
.de FN
.FS
..
. \"FS - begin footnote
.de FJ
'ce 0
.nr IA \\n(IP
.nr IB \\n(.i
.ev1
.ll \\n(FLu
.da FF
.br
.if \\n(IF \{\
. tm Footnote within footnote-illegal.
. ab\}
.nr IF 1
.if !\\n+(XX-1 .FA
..
. \"FE - footnote end
.de FK
.br
.in 0
.nr IF 0
.di
.ev
.if !\\n(XX-1 .nr dn +\\n(.v
.nr YY -\\n(dn
.if !\\n(NX .nr WF 1
.if \\n(dl>\\n(CW .nr WF 1
.ie (\\n(nl+\\n(.v)<=(\\n(.p+\\n(YY) .ch FO \\n(YYu
.el \{\
. if \\n(nl>(\\n(HM+1.5v) .ch FO \\n(nlu+\\n(.vu
. if \\n(nl+\\n(FM+1v>\\n(.p .ch FX \\n(.pu-\\n(FMu+2v
. if \\n(nl<=(\\n(HM+1.5v) .ch FO \\n(HMu+(4u*\\n(.vu)\}
.nr IP \\n(IA
'in \\n(IBu
..
.\" First page footer.
.de FS
.ev1
.br
.ll \\n(FLu
.da FG
..
.de FE
.br
.di
.nr FP \\n(dn
.if !\\n(1T .nr KG 1 \"not in abstract repeat next page.
.if "\\n(.z"OD" .nr KG 0 \" if in OK, don't repeat.
.ev
..
.de FA
.if n __________________________
.if t \l'1i'
.br
..
.de FV
.FS
.nf
.ls 1
.FY
.ls
.fi
.FE
..
.de FX
.if \\n(XX \{\
. di FY
. ns\}
..
.de XF
.if \\n(nlu+1v>(\\n(.pu-\\n(FMu) .ch FX \\n(nlu+1.9v
.ev1
.nf
.ls 1
.FF
.rm FF
.nr XX 0 1
.br
.ls
.di
.fi
.ev
..
.de FL
.ev1
.nr FL \\$1n
.ll \\$1
.ev
..
.de HO
Bell Laboratories
Holmdel, New Jersey 07733
..
.de WH
Bell Laboratories
Whippany, New Jersey 07981
..
.de IH
Bell Laboratories
Naperville, Illinois 60540
..
.de UL \" underline argument, don't italicize
.ie t \\$1\l'|0\(ul'\\$2
.el .I "\\$1" "\\$2"
..
.de UX
.ie \\n(GA \\$2\s-1UNIX\s0\\$1
.el \{\
.ie n \{\\$2UNIX\\$1*
.FS
* UNIX is a
.ie \\$3=1 Footnote
.el registered trademark
of X/Open.
.FE\}
.el \\$2\s-1UNIX\\s0\\$1\\f1\(rg\\fP
.nr GA 1\}
..
.de US
the
.UX
operating system\\$1
..
.de QS
.br
.LP
.in +\\n(QIu
.ll -\\n(QIu
..
.de QE
.br
.ll +\\n(QIu
.in -\\n(QIu
.LP
..
.de B1 \" begin boxed stuff
.br
.di BB
.nr BC 0
.if "\\$1"C" .nr BC 1
.nr BE 1
..
.de B2 \" end boxed stuff
.br
.nr BI 1n
.if \\n(.$>0 .nr BI \\$1n
.di
.nr BE 0
.nr BW \\n(dl
.nr BH \\n(dn
.ne \\n(BHu+\\n(.Vu
.nr BQ \\n(.j
.nf
.ti 0
.if \\n(BC>0 .in +(\\n(.lu-\\n(BWu)/2u
.in +\\n(BIu
.ls 1
.BB
.ls
.in -\\n(BIu
.nr BW +2*\\n(BI
.sp -1
\l'\\n(BWu\(ul'\L'-\\n(BHu'\l'|0\(ul'\h'|0'\L'\\n(BHu'
.nr BW -2*\\n(BI
.if \\n(BC>0 .in -(\\n(.lu-\\n(BWu)/2u
.if \\n(BQ .fi
.br
..
.de AT
.nf
.sp
.ne 2
Attached:
..
.de CT
.nf
.sp
.ne 2
.ie \\n(.$ Copy to \\$1:
.el Copy to:
..
.de BX
.ie t \(br\|\\$1\|\(br\l'|0\(rn'\l'|0\(ul'
.el \(br\\kA\|\\$1\|\\kB\(br\v'-1v'\h'|\\nBu'\l'|\\nAu'\v'1v'\l'|\\nAu'
..
.IZ
.rm IZ
.de [
[
..
.de ]
]
..
|
a1ive/NkArc
| 14,123
|
grub/lib/zstd/decompress/huf_decompress_amd64.S
|
/*
* Copyright (c) Meta Platforms, Inc. and affiliates.
* All rights reserved.
*
* This source code is licensed under both the BSD-style license (found in the
* LICENSE file in the root directory of this source tree) and the GPLv2 (found
* in the COPYING file in the root directory of this source tree).
* You may select, at your option, one of the above-listed licenses.
*/
#include "../common/portability_macros.h"
/* Stack marking
* ref: https://wiki.gentoo.org/wiki/Hardened/GNU_stack_quickstart
*/
#if defined(__ELF__) && defined(__GNUC__)
.section .note.GNU-stack,"",%progbits
#endif
#if ZSTD_ENABLE_ASM_X86_64_BMI2
/* Calling convention:
*
* %rdi contains the first argument: HUF_DecompressAsmArgs*.
* %rbp isn't maintained (no frame pointer).
* %rsp contains the stack pointer that grows down.
* No red-zone is assumed, only addresses >= %rsp are used.
* All register contents are preserved.
*
* TODO: Support Windows calling convention.
*/
ZSTD_HIDE_ASM_FUNCTION(HUF_decompress4X1_usingDTable_internal_fast_asm_loop)
ZSTD_HIDE_ASM_FUNCTION(HUF_decompress4X2_usingDTable_internal_fast_asm_loop)
ZSTD_HIDE_ASM_FUNCTION(_HUF_decompress4X2_usingDTable_internal_fast_asm_loop)
ZSTD_HIDE_ASM_FUNCTION(_HUF_decompress4X1_usingDTable_internal_fast_asm_loop)
.global HUF_decompress4X1_usingDTable_internal_fast_asm_loop
.global HUF_decompress4X2_usingDTable_internal_fast_asm_loop
.global _HUF_decompress4X1_usingDTable_internal_fast_asm_loop
.global _HUF_decompress4X2_usingDTable_internal_fast_asm_loop
.text
/* Sets up register mappings for clarity.
* op[], bits[], dtable & ip[0] each get their own register.
* ip[1,2,3] & olimit alias var[].
* %rax is a scratch register.
*/
#define op0 rsi
#define op1 rbx
#define op2 rcx
#define op3 rdi
#define ip0 r8
#define ip1 r9
#define ip2 r10
#define ip3 r11
#define bits0 rbp
#define bits1 rdx
#define bits2 r12
#define bits3 r13
#define dtable r14
#define olimit r15
/* var[] aliases ip[1,2,3] & olimit
* ip[1,2,3] are saved every iteration.
* olimit is only used in compute_olimit.
*/
#define var0 r15
#define var1 r9
#define var2 r10
#define var3 r11
/* 32-bit var registers */
#define vard0 r15d
#define vard1 r9d
#define vard2 r10d
#define vard3 r11d
/* Calls X(N) for each stream 0, 1, 2, 3. */
#define FOR_EACH_STREAM(X) \
X(0); \
X(1); \
X(2); \
X(3)
/* Calls X(N, idx) for each stream 0, 1, 2, 3. */
#define FOR_EACH_STREAM_WITH_INDEX(X, idx) \
X(0, idx); \
X(1, idx); \
X(2, idx); \
X(3, idx)
/* Define both _HUF_* & HUF_* symbols because MacOS
* C symbols are prefixed with '_' & Linux symbols aren't.
*/
_HUF_decompress4X1_usingDTable_internal_fast_asm_loop:
HUF_decompress4X1_usingDTable_internal_fast_asm_loop:
ZSTD_CET_ENDBRANCH
/* Save all registers - even if they are callee saved for simplicity. */
push %rax
push %rbx
push %rcx
push %rdx
push %rbp
push %rsi
push %rdi
push %r8
push %r9
push %r10
push %r11
push %r12
push %r13
push %r14
push %r15
/* Read HUF_DecompressAsmArgs* args from %rax */
movq %rdi, %rax
movq 0(%rax), %ip0
movq 8(%rax), %ip1
movq 16(%rax), %ip2
movq 24(%rax), %ip3
movq 32(%rax), %op0
movq 40(%rax), %op1
movq 48(%rax), %op2
movq 56(%rax), %op3
movq 64(%rax), %bits0
movq 72(%rax), %bits1
movq 80(%rax), %bits2
movq 88(%rax), %bits3
movq 96(%rax), %dtable
push %rax /* argument */
push 104(%rax) /* ilowest */
push 112(%rax) /* oend */
push %olimit /* olimit space */
subq $24, %rsp
.L_4X1_compute_olimit:
/* Computes how many iterations we can do safely
* %r15, %rax may be clobbered
* rbx, rdx must be saved
* op3 & ip0 mustn't be clobbered
*/
movq %rbx, 0(%rsp)
movq %rdx, 8(%rsp)
movq 32(%rsp), %rax /* rax = oend */
subq %op3, %rax /* rax = oend - op3 */
/* r15 = (oend - op3) / 5 */
movabsq $-3689348814741910323, %rdx
mulq %rdx
movq %rdx, %r15
shrq $2, %r15
movq %ip0, %rax /* rax = ip0 */
movq 40(%rsp), %rdx /* rdx = ilowest */
subq %rdx, %rax /* rax = ip0 - ilowest */
movq %rax, %rbx /* rbx = ip0 - ilowest */
/* rdx = (ip0 - ilowest) / 7 */
movabsq $2635249153387078803, %rdx
mulq %rdx
subq %rdx, %rbx
shrq %rbx
addq %rbx, %rdx
shrq $2, %rdx
/* r15 = min(%rdx, %r15) */
cmpq %rdx, %r15
cmova %rdx, %r15
/* r15 = r15 * 5 */
leaq (%r15, %r15, 4), %r15
/* olimit = op3 + r15 */
addq %op3, %olimit
movq 8(%rsp), %rdx
movq 0(%rsp), %rbx
/* If (op3 + 20 > olimit) */
movq %op3, %rax /* rax = op3 */
cmpq %rax, %olimit /* op3 == olimit */
je .L_4X1_exit
/* If (ip1 < ip0) go to exit */
cmpq %ip0, %ip1
jb .L_4X1_exit
/* If (ip2 < ip1) go to exit */
cmpq %ip1, %ip2
jb .L_4X1_exit
/* If (ip3 < ip2) go to exit */
cmpq %ip2, %ip3
jb .L_4X1_exit
/* Reads top 11 bits from bits[n]
* Loads dt[bits[n]] into var[n]
*/
#define GET_NEXT_DELT(n) \
movq $53, %var##n; \
shrxq %var##n, %bits##n, %var##n; \
movzwl (%dtable,%var##n,2),%vard##n
/* var[n] must contain the DTable entry computed with GET_NEXT_DELT
* Moves var[n] to %rax
* bits[n] <<= var[n] & 63
* op[n][idx] = %rax >> 8
* %ah is a way to access bits [8, 16) of %rax
*/
#define DECODE_FROM_DELT(n, idx) \
movq %var##n, %rax; \
shlxq %var##n, %bits##n, %bits##n; \
movb %ah, idx(%op##n)
/* Assumes GET_NEXT_DELT has been called.
* Calls DECODE_FROM_DELT then GET_NEXT_DELT
*/
#define DECODE_AND_GET_NEXT(n, idx) \
DECODE_FROM_DELT(n, idx); \
GET_NEXT_DELT(n) \
/* // ctz & nbBytes is stored in bits[n]
* // nbBits is stored in %rax
* ctz = CTZ[bits[n]]
* nbBits = ctz & 7
* nbBytes = ctz >> 3
* op[n] += 5
* ip[n] -= nbBytes
* // Note: x86-64 is little-endian ==> no bswap
* bits[n] = MEM_readST(ip[n]) | 1
* bits[n] <<= nbBits
*/
#define RELOAD_BITS(n) \
bsfq %bits##n, %bits##n; \
movq %bits##n, %rax; \
andq $7, %rax; \
shrq $3, %bits##n; \
leaq 5(%op##n), %op##n; \
subq %bits##n, %ip##n; \
movq (%ip##n), %bits##n; \
orq $1, %bits##n; \
shlx %rax, %bits##n, %bits##n
/* Store clobbered variables on the stack */
movq %olimit, 24(%rsp)
movq %ip1, 0(%rsp)
movq %ip2, 8(%rsp)
movq %ip3, 16(%rsp)
/* Call GET_NEXT_DELT for each stream */
FOR_EACH_STREAM(GET_NEXT_DELT)
.p2align 6
.L_4X1_loop_body:
/* Decode 5 symbols in each of the 4 streams (20 total)
* Must have called GET_NEXT_DELT for each stream
*/
FOR_EACH_STREAM_WITH_INDEX(DECODE_AND_GET_NEXT, 0)
FOR_EACH_STREAM_WITH_INDEX(DECODE_AND_GET_NEXT, 1)
FOR_EACH_STREAM_WITH_INDEX(DECODE_AND_GET_NEXT, 2)
FOR_EACH_STREAM_WITH_INDEX(DECODE_AND_GET_NEXT, 3)
FOR_EACH_STREAM_WITH_INDEX(DECODE_FROM_DELT, 4)
/* Load ip[1,2,3] from stack (var[] aliases them)
* ip[] is needed for RELOAD_BITS
* Each will be stored back to the stack after RELOAD
*/
movq 0(%rsp), %ip1
movq 8(%rsp), %ip2
movq 16(%rsp), %ip3
/* Reload each stream & fetch the next table entry
* to prepare for the next iteration
*/
RELOAD_BITS(0)
GET_NEXT_DELT(0)
RELOAD_BITS(1)
movq %ip1, 0(%rsp)
GET_NEXT_DELT(1)
RELOAD_BITS(2)
movq %ip2, 8(%rsp)
GET_NEXT_DELT(2)
RELOAD_BITS(3)
movq %ip3, 16(%rsp)
GET_NEXT_DELT(3)
/* If op3 < olimit: continue the loop */
cmp %op3, 24(%rsp)
ja .L_4X1_loop_body
/* Reload ip[1,2,3] from stack */
movq 0(%rsp), %ip1
movq 8(%rsp), %ip2
movq 16(%rsp), %ip3
/* Re-compute olimit */
jmp .L_4X1_compute_olimit
#undef GET_NEXT_DELT
#undef DECODE_FROM_DELT
#undef DECODE
#undef RELOAD_BITS
.L_4X1_exit:
addq $24, %rsp
/* Restore stack (oend & olimit) */
pop %rax /* olimit */
pop %rax /* oend */
pop %rax /* ilowest */
pop %rax /* arg */
/* Save ip / op / bits */
movq %ip0, 0(%rax)
movq %ip1, 8(%rax)
movq %ip2, 16(%rax)
movq %ip3, 24(%rax)
movq %op0, 32(%rax)
movq %op1, 40(%rax)
movq %op2, 48(%rax)
movq %op3, 56(%rax)
movq %bits0, 64(%rax)
movq %bits1, 72(%rax)
movq %bits2, 80(%rax)
movq %bits3, 88(%rax)
/* Restore registers */
pop %r15
pop %r14
pop %r13
pop %r12
pop %r11
pop %r10
pop %r9
pop %r8
pop %rdi
pop %rsi
pop %rbp
pop %rdx
pop %rcx
pop %rbx
pop %rax
ret
_HUF_decompress4X2_usingDTable_internal_fast_asm_loop:
HUF_decompress4X2_usingDTable_internal_fast_asm_loop:
ZSTD_CET_ENDBRANCH
/* Save all registers - even if they are callee saved for simplicity. */
push %rax
push %rbx
push %rcx
push %rdx
push %rbp
push %rsi
push %rdi
push %r8
push %r9
push %r10
push %r11
push %r12
push %r13
push %r14
push %r15
movq %rdi, %rax
movq 0(%rax), %ip0
movq 8(%rax), %ip1
movq 16(%rax), %ip2
movq 24(%rax), %ip3
movq 32(%rax), %op0
movq 40(%rax), %op1
movq 48(%rax), %op2
movq 56(%rax), %op3
movq 64(%rax), %bits0
movq 72(%rax), %bits1
movq 80(%rax), %bits2
movq 88(%rax), %bits3
movq 96(%rax), %dtable
push %rax /* argument */
push %rax /* olimit */
push 104(%rax) /* ilowest */
movq 112(%rax), %rax
push %rax /* oend3 */
movq %op3, %rax
push %rax /* oend2 */
movq %op2, %rax
push %rax /* oend1 */
movq %op1, %rax
push %rax /* oend0 */
/* Scratch space */
subq $8, %rsp
.L_4X2_compute_olimit:
/* Computes how many iterations we can do safely
* %r15, %rax may be clobbered
* rdx must be saved
* op[1,2,3,4] & ip0 mustn't be clobbered
*/
movq %rdx, 0(%rsp)
/* We can consume up to 7 input bytes each iteration. */
movq %ip0, %rax /* rax = ip0 */
movq 40(%rsp), %rdx /* rdx = ilowest */
subq %rdx, %rax /* rax = ip0 - ilowest */
movq %rax, %r15 /* r15 = ip0 - ilowest */
/* rdx = rax / 7 */
movabsq $2635249153387078803, %rdx
mulq %rdx
subq %rdx, %r15
shrq %r15
addq %r15, %rdx
shrq $2, %rdx
/* r15 = (ip0 - ilowest) / 7 */
movq %rdx, %r15
/* r15 = min(r15, min(oend0 - op0, oend1 - op1, oend2 - op2, oend3 - op3) / 10) */
movq 8(%rsp), %rax /* rax = oend0 */
subq %op0, %rax /* rax = oend0 - op0 */
movq 16(%rsp), %rdx /* rdx = oend1 */
subq %op1, %rdx /* rdx = oend1 - op1 */
cmpq %rax, %rdx
cmova %rax, %rdx /* rdx = min(%rdx, %rax) */
movq 24(%rsp), %rax /* rax = oend2 */
subq %op2, %rax /* rax = oend2 - op2 */
cmpq %rax, %rdx
cmova %rax, %rdx /* rdx = min(%rdx, %rax) */
movq 32(%rsp), %rax /* rax = oend3 */
subq %op3, %rax /* rax = oend3 - op3 */
cmpq %rax, %rdx
cmova %rax, %rdx /* rdx = min(%rdx, %rax) */
movabsq $-3689348814741910323, %rax
mulq %rdx
shrq $3, %rdx /* rdx = rdx / 10 */
/* r15 = min(%rdx, %r15) */
cmpq %rdx, %r15
cmova %rdx, %r15
/* olimit = op3 + 5 * r15 */
movq %r15, %rax
leaq (%op3, %rax, 4), %olimit
addq %rax, %olimit
movq 0(%rsp), %rdx
/* If (op3 + 10 > olimit) */
movq %op3, %rax /* rax = op3 */
cmpq %rax, %olimit /* op3 == olimit */
je .L_4X2_exit
/* If (ip1 < ip0) go to exit */
cmpq %ip0, %ip1
jb .L_4X2_exit
/* If (ip2 < ip1) go to exit */
cmpq %ip1, %ip2
jb .L_4X2_exit
/* If (ip3 < ip2) go to exit */
cmpq %ip2, %ip3
jb .L_4X2_exit
#define DECODE(n, idx) \
movq %bits##n, %rax; \
shrq $53, %rax; \
movzwl 0(%dtable,%rax,4),%r8d; \
movzbl 2(%dtable,%rax,4),%r15d; \
movzbl 3(%dtable,%rax,4),%eax; \
movw %r8w, (%op##n); \
shlxq %r15, %bits##n, %bits##n; \
addq %rax, %op##n
#define RELOAD_BITS(n) \
bsfq %bits##n, %bits##n; \
movq %bits##n, %rax; \
shrq $3, %bits##n; \
andq $7, %rax; \
subq %bits##n, %ip##n; \
movq (%ip##n), %bits##n; \
orq $1, %bits##n; \
shlxq %rax, %bits##n, %bits##n
movq %olimit, 48(%rsp)
.p2align 6
.L_4X2_loop_body:
/* We clobber r8, so store it on the stack */
movq %r8, 0(%rsp)
/* Decode 5 symbols from each of the 4 streams (20 symbols total). */
FOR_EACH_STREAM_WITH_INDEX(DECODE, 0)
FOR_EACH_STREAM_WITH_INDEX(DECODE, 1)
FOR_EACH_STREAM_WITH_INDEX(DECODE, 2)
FOR_EACH_STREAM_WITH_INDEX(DECODE, 3)
FOR_EACH_STREAM_WITH_INDEX(DECODE, 4)
/* Reload r8 */
movq 0(%rsp), %r8
FOR_EACH_STREAM(RELOAD_BITS)
cmp %op3, 48(%rsp)
ja .L_4X2_loop_body
jmp .L_4X2_compute_olimit
#undef DECODE
#undef RELOAD_BITS
.L_4X2_exit:
addq $8, %rsp
/* Restore stack (oend & olimit) */
pop %rax /* oend0 */
pop %rax /* oend1 */
pop %rax /* oend2 */
pop %rax /* oend3 */
pop %rax /* ilowest */
pop %rax /* olimit */
pop %rax /* arg */
/* Save ip / op / bits */
movq %ip0, 0(%rax)
movq %ip1, 8(%rax)
movq %ip2, 16(%rax)
movq %ip3, 24(%rax)
movq %op0, 32(%rax)
movq %op1, 40(%rax)
movq %op2, 48(%rax)
movq %op3, 56(%rax)
movq %bits0, 64(%rax)
movq %bits1, 72(%rax)
movq %bits2, 80(%rax)
movq %bits3, 88(%rax)
/* Restore registers */
pop %r15
pop %r14
pop %r13
pop %r12
pop %r11
pop %r10
pop %r9
pop %r8
pop %rdi
pop %rsi
pop %rbp
pop %rdx
pop %rcx
pop %rbx
pop %rax
ret
#endif
|
9front/9front
| 1,493
|
sys/src/libip/ptclbsum386.s
|
TEXT ptclbsum(SB), $0
MOVL addr+0(FP), SI
MOVL len+4(FP), CX
XORL AX, AX /* sum */
TESTL $1, SI /* byte aligned? */
MOVL SI, DI
JEQ _2align
DECL CX
JLT _return
MOVB 0x00(SI), AH
INCL SI
_2align:
TESTL $2, SI /* word aligned? */
JEQ _32loop
CMPL CX, $2 /* less than 2 bytes? */
JLT _1dreg
SUBL $2, CX
XORL BX, BX
MOVW 0x00(SI), BX
ADDL BX, AX
ADCL $0, AX
LEAL 2(SI), SI
_32loop:
CMPL CX, $0x20
JLT _8loop
MOVL CX, BP
SHRL $5, BP
ANDL $0x1F, CX
_32loopx:
MOVL 0x00(SI), BX
MOVL 0x1C(SI), DX
ADCL BX, AX
MOVL 0x04(SI), BX
ADCL DX, AX
MOVL 0x10(SI), DX
ADCL BX, AX
MOVL 0x08(SI), BX
ADCL DX, AX
MOVL 0x14(SI), DX
ADCL BX, AX
MOVL 0x0C(SI), BX
ADCL DX, AX
MOVL 0x18(SI), DX
ADCL BX, AX
LEAL 0x20(SI), SI
ADCL DX, AX
DECL BP
JNE _32loopx
ADCL $0, AX
_8loop:
CMPL CX, $0x08
JLT _2loop
MOVL CX, BP
SHRL $3, BP
ANDL $0x07, CX
_8loopx:
MOVL 0x00(SI), BX
ADCL BX, AX
MOVL 0x04(SI), DX
ADCL DX, AX
LEAL 0x08(SI), SI
DECL BP
JNE _8loopx
ADCL $0, AX
_2loop:
CMPL CX, $0x02
JLT _1dreg
MOVL CX, BP
SHRL $1, BP
ANDL $0x01, CX
_2loopx:
MOVWLZX 0x00(SI), BX
ADCL BX, AX
LEAL 0x02(SI), SI
DECL BP
JNE _2loopx
ADCL $0, AX
_1dreg:
TESTL $1, CX /* 1 byte left? */
JEQ _fold
XORL BX, BX
MOVB 0x00(SI), BX
ADDL BX, AX
ADCL $0, AX
_fold:
MOVL AX, BX
SHRL $16, BX
JEQ _swab
ANDL $0xFFFF, AX
ADDL BX, AX
JMP _fold
_swab:
TESTL $1, addr+0(FP)
/*TESTL $1, DI*/
JNE _return
XCHGB AH, AL
_return:
RET
|
a1ive/ZenEmu
| 4,146
|
wimldr/prefix.S
|
/*
* Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* @file
*
* bzImage prefix
*
*/
#include "wimboot.h"
/** Standard number of setup sectors */
#define SETUP_SECTS 4
/** Sector size */
#define SECTOR_SIZE 512
/** Setup code length */
#define SETUP_LEN ( ( SETUP_SECTS + 1 ) * SECTOR_SIZE )
/** Protected-mode code will be loaded high */
#define LOADED_HIGH 0x01
/** Protected-mode code will be loaded to this linear address */
#define LOADED_HIGH_ADDRESS 0x100000
/** Protected-mode bit in CR0 */
#define CR0_PE 0x01
/** 32-bit protected mode code segment based at real-mode %cs:0000 */
#define PREFIX_CS 0x08
/** 32 bit protected mode flat code segment */
#define PREFIX_FLAT_CS 0x10
/** 32 bit protected mode flat data segment */
#define PREFIX_FLAT_DS 0x18
.section ".note.GNU-stack", "", @progbits
.text
.section ".prefix", "ax", @progbits
.org 0
_prefix:
#if defined(__i386__) || defined(__x86_64__)
.code32
.org 0x1f1
setup_sects:
.byte SETUP_SECTS
.org 0x1fe
boot_flag:
.word 0xaa55
.org 0x200
jump:
.byte 0xeb, setup - 1f
1:
.org 0x202
header:
.ascii "HdrS"
.org 0x206
version:
.word 0x206 /* Version 2.06 */
.org 0x20e
kernel_version:
.word ( version_string - _prefix - 0x200 )
.org 0x211
loadflags:
.byte LOADED_HIGH
.org 0x218
ramdisk_image:
.long 0 /* Filled in by boot loader */
.org 0x21c
ramdisk_size:
.long 0 /* Filled in by boot loader */
.org 0x228
cmd_line_ptr:
.long 0 /* Filled in by boot loader */
.org 0x22c
ramdisk_max:
.long 0xffffffff
.org 0x238
cmdline_size:
.long 4096
version_string:
.asciz VERSION
/* Setup code */
.code16
setup:
#ifdef BIOS
/* Reset %cs so that labels work */
pushw %ds
pushw $( 1f - _prefix )
lret
1:
/* Fix up GDT */
xorl %eax, %eax
movw %cs, %ax
shll $4, %eax
addl %eax, ( gdt - _prefix + 2 )
addl %eax, ( gdt - _prefix + PREFIX_CS + 2 )
/* Switch to protected mode and jump to startup code */
cli
data32 lgdt ( gdt - _prefix )
movl %cr0, %eax
orb $CR0_PE, %al
movl %eax, %cr0
data32 ljmp $PREFIX_CS, $( 1f - _prefix )
.code32
1:
/* Load data segment registers */
movw $PREFIX_FLAT_DS, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
/* Zero real-mode and protected-mode .bss sections */
xorl %eax, %eax
movl $_bss16, %edi
movl $_bss16_len, %ecx
rep stosb
movl $_bss, %edi
movl $_bss_len, %ecx
rep stosb
/* Copy payload to runtime address */
movl $( LOADED_HIGH_ADDRESS + _payload_pos - SETUP_LEN ), %esi
movl $_payload, %edi
movl $_payload_len, %ecx
cld
rep movsb
/* Copy parameters required by runtime */
movl %cs:( cmd_line_ptr - _prefix ), %eax
movl %eax, cmdline
movl %cs:( ramdisk_image - _prefix ), %eax
movl %eax, initrd
movl %cs:( ramdisk_size - _prefix ), %eax
movl %eax, initrd_len
/* Jump to payload */
ljmp $PREFIX_FLAT_CS, $startup
.size setup, . - setup
/* Global descriptor table */
gdt:
.word gdt_limit
.long ( gdt - _prefix )
/* 32-bit protected mode code segment based at real-mode %cs:0000 */
.org ( gdt + PREFIX_CS )
.word 0xffff, 0
.byte 0, 0x9f, 0xcf, 0
/* 32 bit protected mode flat code segment */
.org ( gdt + PREFIX_FLAT_CS )
.word 0xffff, 0
.byte 0, 0x9f, 0xcf, 0
/* 32 bit protected mode flat data segment */
.org ( gdt + PREFIX_FLAT_DS )
.word 0xffff, 0
.byte 0, 0x93, 0xcf, 0
.size gdt, . - gdt
.equ gdt_limit, . - gdt - 1
#endif
#endif
.org SETUP_LEN
|
a1ive/ZenEmu
| 5,342
|
wimldr/callback.S
|
/*
* Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* @file
*
* Real-mode callbacks
*
*/
#include "wimboot.h"
/* Offsets within parameter block */
#define PARAM_VECTOR 0x00
#define PARAM_EAX 0x04
#define PARAM_EBX 0x08
#define PARAM_ECX 0x0c
#define PARAM_EDX 0x10
#define PARAM_ESI 0x1c
#define PARAM_EDI 0x20
#define PARAM_DS 0x28
#define PARAM_ES 0x30
#define PARAM_FS 0x34
#define PARAM_GS 0x38
#define PARAM_EFLAGS 0x3c
#define PARAM_LEN 0x40
/** Protected-mode bit in CR0 */
#define CR0_PE 0x00000001
/** Paging bit in CR0 */
#define CR0_PG 0x80000000
.section ".note.GNU-stack", "", @progbits
#if defined(__i386__) || defined(__x86_64__)
.code32
.arch i386
/* Call an arbitrary real-mode function */
.section ".text", "ax", @progbits
.globl call_real
call_real:
/* Preserve registers */
pushl %ebp
pushl %ebx
pushl %esi
pushl %edi
/* Switch to real-mode stack, store original stack pointer,
* copy parameter block to stack, store original parameter block
* address.
*/
movl 20(%esp), %esi
movl %esp, %ebp
movl $_ermstack, %esp
pushl %ebp
subl $PARAM_LEN, %esp
movl %esp, %edi
movl $( PARAM_LEN / 4 ), %ecx
cld
rep movsl
movl %esp, %ebp /* %ebp points to parameter block copy */
subl $PARAM_LEN, %esi
pushl %esi
/* Set up 16-bit segment registers and stack */
ljmp $REAL_CS, $( 1f - BASE_ADDRESS )
1: .code16
movw $REAL_DS, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
subl $BASE_ADDRESS, %esp
subl $BASE_ADDRESS, %ebp
/* Switch to real mode */
movl %cr0, %eax
pushl %eax
andl $~( CR0_PG | CR0_PE ), %eax
movl %eax, %cr0
data32 ljmp $BASE_SEG, $( 1f - BASE_ADDRESS )
1: movw $BASE_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
addr32 data32 lidt %cs:( rm_idtr - BASE_ADDRESS )
/* Load registers from parameter block copy */
movl PARAM_EAX(%bp), %eax
movl PARAM_EBX(%bp), %ebx
movl PARAM_ECX(%bp), %ecx
movl PARAM_EDX(%bp), %edx
movl PARAM_ESI(%bp), %esi
movl PARAM_EDI(%bp), %edi
movw PARAM_DS(%bp), %ds
movw PARAM_ES(%bp), %es
movw PARAM_FS(%bp), %fs
movw PARAM_GS(%bp), %gs
/* Call real-mode function with interrupts enabled */
pushw %bp
sti
lcall *PARAM_VECTOR(%bp)
cli
popw %bp
/* Save registers and flags to parameter block copy */
pushfl
popl PARAM_EFLAGS(%bp)
movl %eax, PARAM_EAX(%bp)
movl %ebx, PARAM_EBX(%bp)
movl %ecx, PARAM_ECX(%bp)
movl %edx, PARAM_EDX(%bp)
movl %esi, PARAM_ESI(%bp)
movl %edi, PARAM_EDI(%bp)
movw %ds, PARAM_DS(%bp)
movw %es, PARAM_ES(%bp)
movw %fs, PARAM_FS(%bp)
movw %gs, PARAM_GS(%bp)
/* Switch back to protected mode */
addr32 data32 lgdt %cs:( gdtr - BASE_ADDRESS )
addr32 data32 lidt %cs:( idtr - BASE_ADDRESS )
popl %eax
movl %eax, %cr0
data32 ljmp $FLAT_CS, $1f
1: .code32
movw $FLAT_DS, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
addl $BASE_ADDRESS, %esp
/* Copy modified parameter block back to original location and
* return to original stack
*/
popl %edi
movl %esp, %esi
movl $( PARAM_LEN / 4 ), %ecx
cld
rep movsl
movl 0(%esi), %esp
/* Restore registers and return */
popl %edi
popl %esi
popl %ebx
popl %ebp
ret
.size call_real, . - call_real
/* Call an arbitrary real-mode interrupt */
.section ".text", "ax", @progbits
.globl call_interrupt
call_interrupt:
/* Enter function */
pushl %ebp
movl %esp, %ebp
pushl %ebx
pushl %esi
/* Extract INT number from parameter block and update INT instruction */
movl 8(%ebp), %esi /* %esi points to parameter block */
movl PARAM_VECTOR(%esi), %ebx
movb %bl, ( dynamic_int + 1 )
/* Overwrite vector with dynamic INT code fragment */
movw $BASE_SEG, (PARAM_VECTOR + 2)(%esi)
movl $( dynamic_int - BASE_ADDRESS ), %eax
movw %ax, PARAM_VECTOR(%esi)
/* Call dynamic INT code fragment */
pushl %esi
call call_real
popl %esi
/* Restore INT number in parameter block */
movl %ebx, PARAM_VECTOR(%esi)
/* Restore registers and return */
popl %esi
popl %ebx
popl %ebp
ret
.size call_interrupt, . - call_interrupt
/* Dynamic interrupt code fragment */
.section ".text16", "ax", @progbits
dynamic_int:
int $0x00
lret
.size dynamic_int, . - dynamic_int
/* Real-mode interrupt descriptor table */
.section ".data16", "ax", @progbits
rm_idtr:
.word ( ( 256 * 4 ) - 1 ) /* Limit (256 segment:offset pairs) */
.long 0 /* Base */
.size rm_idtr, . - rm_idtr
/* Real-mode stack */
.section ".stack16", "aw", @nobits
.balign 8
_rmstack:
.space 8192
.size _rmstack, . - _rmstack
_ermstack:
#endif /* defined(__i386__) || defined(__x86_64__) */
|
a1ive/ZenEmu
| 3,224
|
wimldr/startup.S
|
/*
* Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
/**
* @file
*
* Startup code
*
*/
#include "wimboot.h"
#define WARM_REBOOT_FLAG 0x0472
#define WARM_REBOOT_MAGIC 0x1234
#define KC_CMD 0x64
#define KC_CMD_RESET 0xfe
.section ".note.GNU-stack", "", @progbits
#if defined(__i386__) || defined(__x86_64__)
.code32
.arch i386
/* Startup code */
.section ".text", "ax", @progbits
.globl startup
startup:
/* Reload GDT, IDT, and all segment registers, and set up stack */
lgdt gdtr
lidt idtr
ljmp $FLAT_CS, $1f
1: movw $FLAT_DS, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
movl $_estack, %esp
/* Jump to C code */
call main
/* Should never return */
jmp reboot
.size startup, . - startup
/* Reboot system */
.section ".text", "ax", @progbits
.globl reboot
reboot:
/* Attempt a warm reboot via the keyboard controller */
movw $WARM_REBOOT_MAGIC, WARM_REBOOT_FLAG
movb $KC_CMD_RESET, %al
outb %al, $KC_CMD
/* If that failed, generate a CPU triple fault */
int $0xff
/* If even that failed, hang the system */
1: hlt
jmp 1b
.size reboot, . - reboot
/* Global descriptor table */
.section ".rodata16", "aw", @progbits
.balign 8
gdt:
.globl gdtr
gdtr:
.word gdt_limit
.long gdt
/* 64 bit long mode code segment */
.org ( gdt + LM_CS )
.word 0, 0
.byte 0, 0x9b, 0x20, 0
/* 32 bit protected mode flat code segment */
.org ( gdt + FLAT_CS )
.word 0xffff, 0
.byte 0, 0x9f, 0xcf, 0
/* 32 bit protected mode flat data segment */
.org ( gdt + FLAT_DS )
.word 0xffff, 0
.byte 0, 0x93, 0xcf, 0
/* 16 bit flat real mode code segment with base BASE_ADDRESS */
.org ( gdt + REAL_CS )
.word 0xffff, ( BASE_ADDRESS & 0xffff )
.byte ( BASE_ADDRESS >> 16 ), 0x9b, 0x8f, 0
/* 16 bit flat real mode data segment with base BASE_ADDRESS */
.org ( gdt + REAL_DS )
.word 0xffff, ( BASE_ADDRESS & 0xffff )
.byte ( BASE_ADDRESS >> 16 ), 0x93, 0x8f, 0
.size gdt, . - gdt
.equ gdt_limit, . - gdt - 1
/* Interrupt descriptor table */
.section ".bss16", "aw", @nobits
.balign 8
idt:
.space ( 256 * 8 ) /* 256 8-byte entries */
.size idt, . - idt
.equ idt_limit, . - idt - 1
/* Interrupt descriptor table register */
.section ".rodata16", "aw", @progbits
.globl idtr
idtr:
.word idt_limit
.long idt
.size idtr, . - idtr
/* Stack */
.section ".stack", "aw", @nobits
.balign 8
_stack:
.space ( 64 * 1024 )
.size _stack, . - _stack
_estack:
#endif /* defined(__i386__) || defined(__x86_64__) */
|
a1k0n/cycloid
| 9,884
|
stm32/startup_stm32f030x6.s
|
/**
******************************************************************************
* @file startup_stm32f030x6.s
* @author MCD Application Team
* @brief STM32F030x4/STM32F030x6 devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* Reserved */
.word RTC_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* Reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word 0 /* Reserved */
.word TIM3_IRQHandler /* TIM3 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word TIM14_IRQHandler /* TIM14 */
.word 0 /* Reserved */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word 0 /* Reserved */
.word SPI1_IRQHandler /* SPI1 */
.word 0 /* Reserved */
.word USART1_IRQHandler /* USART1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
a1ive/grub
| 4,246
|
grub-core/gdb/i386/machdep.S
|
/* machdep.S - machine dependent assembly routines for the GDB stub */
/*
* Copyright (C) 2006 Lubomir Kundrak
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <grub/cpu/gdb.h>
#include <grub/symbol.h>
#define EC_PRESENT 1
#define EC_ABSENT 0
#define GRUB_GDB_STACKSIZE 40000
#define SEP ,
#ifdef __APPLE__
.zerofill __DATA, __bss, LOCAL(grub_gdb_stack_end), GRUB_GDB_STACKSIZE, 4
LOCAL(grub_gdb_stack) = LOCAL(grub_gdb_stack_end)
#else
/*
* The .data index for the address vector.
*/
#define VECTOR 1
.bss
.space GRUB_GDB_STACKSIZE
VARIABLE(grub_gdb_stack)
#endif
/*
* Supplemental macros for register saving/restoration
* on exception handler entry/leave.
*/
#ifdef __APPLE__
.macro save32
#define REG $0
#define NDX $1
#else
.macro save32 reg ndx
#define REG \reg
#define NDX \ndx
#endif
movl REG, EXT_C(grub_gdb_regs)+(NDX * 4)
.endm
#undef REG
#undef NDX
#ifdef __APPLE__
.macro save16
#define REG $0
#define NDX $1
#else
.macro save16 reg ndx
#define REG \reg
#define NDX \ndx
#endif
xorl %eax, %eax
movw REG, EXT_C(grub_gdb_regs)+(NDX * 4)
movw %ax, EXT_C(grub_gdb_regs)+(NDX * 4 + 2)
movl EXT_C(grub_gdb_regs)+(EAX * 4), %eax
.endm
#undef REG
#undef NDX
#ifdef __APPLE__
.macro load32
#define NDX $0
#define REG $1
#else
.macro load32 ndx reg
#define REG \reg
#define NDX \ndx
#endif
movl EXT_C(grub_gdb_regs)+(NDX * 4), REG
.endm
#undef REG
#undef NDX
#ifdef __APPLE__
.macro load16
#define NDX $0
#define REG $1
#else
.macro load16 ndx reg
#define NDX \ndx
#define REG \reg
#endif
movw EXT_C(grub_gdb_regs)+(NDX * 4), REG
.endm
#undef REG
#undef NDX
.macro save_context
save32 %eax, EAX
save32 %ecx, ECX
save32 %edx, EDX
save32 %ebx, EBX
save32 %ebp, EBP
save32 %esi, ESI
save32 %edi, EDI
popl %ebx
save32 %ebx, EIP
popl %ebx
save32 %ebx, CS
popl %ebx
save32 %ebx, EFLAGS
save32 %esp, ESP
save16 %ds, DS
save16 %es, ES
save16 %fs, FS
save16 %gs, GS
save16 %ss, SS
.endm
.macro load_context
load16 SS, %ss
load32 ESP, %esp
load32 EBP, %ebp
load32 ESI, %esi
load32 EDI, %edi
load16 DS, %ds
load16 ES, %es
load16 FS, %fs
load16 GS, %gs
load32 EFLAGS, %eax
pushl %eax
load32 CS, %eax
pushl %eax
load32 EIP, %eax
pushl %eax
load32 EBX, %ebx
load32 EDX, %edx
load32 ECX, %ecx
load32 EAX, %eax
.endm
/*
* This macro creates handlers for a given range of exception numbers
* and adds their addresses to the grub_gdb_trapvec array.
*/
#ifdef __APPLE__
.macro ent
#define EC $0
#define BEG $1
#define END $2
#else
.macro ent ec beg end=0
#define EC \ec
#define BEG \beg
#define END \end
#endif
/*
* Wrapper body itself.
*/
.text
1:
.if EC
add MACRO_DOLLAR(4), %esp
.endif
save_context
#ifdef __APPLE__
mov $LOCAL(grub_gdb_stack), %esp
#else
mov $EXT_C(grub_gdb_stack), %esp
#endif
mov $(BEG), %eax /* trap number */
call EXT_C(grub_gdb_trap)
load_context
iret
/*
* Address entry in trapvec array.
*/
#ifdef __APPLE__
.section __DATA, VECTOR
#else
.data VECTOR
#endif
.long 1b
/*
* Next... (recursion).
*/
.if END-BEG > 0
#ifdef __APPLE__
ent EC, (BEG+1), END
#else
ent \ec "(\beg+1)" \end
#endif
.endif
.endm
/*
* Here does the actual construction of the address array and handlers
* take place.
*/
#ifdef __APPLE__
.section __DATA, VECTOR
#else
.data VECTOR
#endif
VARIABLE(grub_gdb_trapvec)
ent EC_ABSENT, 0, 7
ent EC_PRESENT, 8
ent EC_ABSENT, 9
ent EC_PRESENT, 10, 14
/*
* You may have to split this further or as(1)
* will complain about nesting being too deep.
*/
ent EC_ABSENT, 15, GRUB_GDB_LAST_TRAP
|
a1ive/grub
| 2,745
|
grub-core/efiemu/runtime/efiemu.S
|
/* callwrap.S - wrapper for x86_64 efi calls */
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
/*
* x86_64 uses registry to pass parameters. Unfortunately, gcc and efi use
* different call conversion, so we need to do some conversion.
*
* gcc:
* %rdi, %rsi, %rdx, %rcx, %r8, %r9, 8(%rsp), 16(%rsp), ...
*
* efi:
* %rcx, %rdx, %r8, %r9, 32(%rsp), 40(%rsp), 48(%rsp), ...
*
*/
.file "efiemu.S"
.text
.code64
FUNCTION(efi_wrap_0)
subq $40, %rsp
call *%rdi
addq $40, %rsp
ret
FUNCTION(efi_wrap_1)
subq $40, %rsp
mov %rsi, %rcx
call *%rdi
addq $40, %rsp
ret
FUNCTION(efi_wrap_2)
subq $40, %rsp
mov %rsi, %rcx
call *%rdi
addq $40, %rsp
ret
FUNCTION(efi_wrap_3)
subq $40, %rsp
mov %rcx, %r8
mov %rsi, %rcx
call *%rdi
addq $40, %rsp
ret
FUNCTION(efi_wrap_4)
subq $40, %rsp
mov %r8, %r9
mov %rcx, %r8
mov %rsi, %rcx
call *%rdi
addq $40, %rsp
ret
FUNCTION(efi_wrap_5)
subq $40, %rsp
mov %r9, 32(%rsp)
mov %r8, %r9
mov %rcx, %r8
mov %rsi, %rcx
call *%rdi
addq $40, %rsp
ret
FUNCTION(efi_wrap_6)
subq $56, %rsp
mov 56+8(%rsp), %rax
mov %rax, 40(%rsp)
mov %r9, 32(%rsp)
mov %r8, %r9
mov %rcx, %r8
mov %rsi, %rcx
call *%rdi
addq $56, %rsp
ret
FUNCTION(efi_wrap_7)
subq $88, %rsp
mov 88+16(%rsp), %rax
mov %rax, 48(%rsp)
mov 88+8(%rsp), %rax
mov %rax, 40(%rsp)
mov %r9, 32(%rsp)
mov %r8, %r9
mov %rcx, %r8
mov %rsi, %rcx
call *%rdi
addq $88, %rsp
ret
FUNCTION(efi_wrap_10)
subq $88, %rsp
mov 88+40(%rsp), %rax
mov %rax, 72(%rsp)
mov 88+32(%rsp), %rax
mov %rax, 64(%rsp)
mov 88+24(%rsp), %rax
mov %rax, 56(%rsp)
mov 88+16(%rsp), %rax
mov %rax, 48(%rsp)
mov 88+8(%rsp), %rax
mov %rax, 40(%rsp)
mov %r9, 32(%rsp)
mov %r8, %r9
mov %rcx, %r8
mov %rsi, %rcx
call *%rdi
addq $88, %rsp
ret
|
a1ive/grub
| 3,298
|
grub-core/mmap/i386/pc/mmap_helper.S
|
/* Mmap management. */
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#define DS(x) ((x) - LOCAL (segstart))
LOCAL (segstart):
VARIABLE(grub_machine_mmaphook_start)
.code16
VARIABLE(grub_machine_mmaphook_int12)
push %ds
push %cs
pop %ds
#ifdef __APPLE__
LOCAL(kblow_offset) = DS (LOCAL (kblow))
movw LOCAL(kblow_offset), %ax
#else
movw DS (LOCAL (kblow)), %ax
#endif
pop %ds
iret
VARIABLE(grub_machine_mmaphook_int15)
pushf
cmpw $0xe801, %ax
jz LOCAL (e801)
cmpw $0xe820, %ax
jz LOCAL (e820)
cmpb $0x88, %ah
jz LOCAL (h88)
popf
/* ljmp */
.byte 0xea
VARIABLE (grub_machine_mmaphook_int15offset)
.word 0
VARIABLE (grub_machine_mmaphook_int15segment)
.word 0
LOCAL (e801):
popf
push %ds
push %cs
pop %ds
#ifdef __APPLE__
LOCAL(kbin16mb_offset) = DS (LOCAL (kbin16mb))
LOCAL(m64kbin4gb_offset) = DS (LOCAL (m64kbin4gb))
movw LOCAL(kbin16mb_offset), %ax
movw LOCAL(m64kbin4gb_offset), %bx
#else
movw DS (LOCAL (kbin16mb)), %ax
movw DS (LOCAL (m64kbin4gb)), %bx
#endif
movw %ax, %cx
movw %bx, %dx
pop %ds
clc
jmp LOCAL (iret_cf)
LOCAL (h88):
popf
push %ds
push %cs
pop %ds
#ifdef __APPLE__
movw LOCAL(kbin16mb_offset), %ax
#else
movw DS (LOCAL (kbin16mb)), %ax
#endif
pop %ds
clc
jmp LOCAL (iret_cf)
LOCAL (e820):
popf
push %ds
push %cs
pop %ds
cmpw $20, %cx
jb LOCAL (errexit)
#ifdef __APPLE__
LOCAL(mmap_num_offset) = DS (LOCAL (mmap_num))
cmpw LOCAL(mmap_num_offset), %bx
#else
cmpw DS (LOCAL (mmap_num)), %bx
#endif
jae LOCAL (errexit)
cmp $0x534d4150, %edx
jne LOCAL (errexit)
push %si
push %di
movw $20, %cx
#ifdef __APPLE__
LOCAL(mmaphook_map_offset) = DS(LOCAL (mmaphook_mmap))
movw $LOCAL(mmaphook_map_offset), %si
#else
movw $(DS(LOCAL (mmaphook_mmap))), %si
#endif
mov %bx, %ax
imul $20, %ax
add %ax, %si
rep movsb
pop %di
pop %si
movl $20, %ecx
inc %bx
#ifdef __APPLE__
cmpw LOCAL(mmap_num_offset), %bx
#else
cmpw DS(LOCAL (mmap_num)), %bx
#endif
jb LOCAL (noclean)
xor %bx, %bx
LOCAL (noclean):
mov $0x534d4150, %eax
pop %ds
clc
jmp LOCAL (iret_cf)
LOCAL (errexit):
mov $0x534d4150, %eax
pop %ds
xor %bx, %bx
stc
LOCAL (iret_cf):
push %bp
mov %sp, %bp
setc 6(%bp)
pop %bp
iret
VARIABLE(grub_machine_mmaphook_mmap_num)
LOCAL (mmap_num):
.word 0
VARIABLE(grub_machine_mmaphook_kblow)
LOCAL (kblow):
.word 0
VARIABLE (grub_machine_mmaphook_kbin16mb)
LOCAL (kbin16mb):
.word 0
VARIABLE (grub_machine_mmaphook_64kbin4gb)
LOCAL (m64kbin4gb):
.word 0
LOCAL (mmaphook_mmap):
/* Memory map is placed just after the interrupt handlers. */
VARIABLE(grub_machine_mmaphook_end)
.byte 0
|
a1ive/grub
| 4,785
|
grub-core/lib/i386/relocator64.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009,2010 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#define CODE32_SEGMENT 0x18
#define CODE_SEGMENT 0x08
/* The data segment of the protected mode. */
#define DATA_SEGMENT 0x10
#include "relocator_common.S"
.p2align 4 /* force 16-byte alignment */
VARIABLE(grub_relocator64_start)
PREAMBLE
#ifndef __x86_64__
DISABLE_PAGING
/* Turn on PAE. */
movl %cr4, %eax
orl $(GRUB_MEMORY_CPU_CR4_PAE_ON | GRUB_MEMORY_CPU_CR4_PSE_ON), %eax
movl %eax, %cr4
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator64_cr3)
.long 0
movl %eax, %cr3
/* Turn on amd64. */
movl $GRUB_MEMORY_CPU_AMD64_MSR, %ecx
rdmsr
orl $GRUB_MEMORY_CPU_AMD64_MSR_ON, %eax
wrmsr
/* Enable paging. */
movl %cr0, %eax
orl $GRUB_MEMORY_CPU_CR0_PAGING_ON, %eax
movl %eax, %cr0
RELOAD_GDT
#else
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator64_cr3)
.quad 0
movq %rax, %cr3
#endif
#ifdef __x86_64__
.code64
#endif
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator64_rsp)
.quad 0
#ifdef __x86_64__
movq %rax, %rsp
#else
/* movq %rax, %rsp */
.byte 0x48
.byte 0x89
.byte 0xc4
#endif
#ifdef GRUB_MACHINE_EFI
jmp LOCAL(skip_efi_stack_align)
/*
* Here is grub_relocator64_efi_start() entry point. Most of the
* code below is shared between grub_relocator64_efi_start()
* and grub_relocator64_start().
*
* Think twice before changing anything there!!!
*/
VARIABLE(grub_relocator64_efi_start)
/* Align the stack as UEFI spec requires. */
#ifdef __x86_64__
andq $~15, %rsp
#else
/* andq $~15, %rsp */
.byte 0x48
.byte 0x83
.byte 0xe4
.byte 0xf0
#endif
LOCAL(skip_efi_stack_align):
#endif
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator64_rsi)
.quad 0
#ifdef __x86_64__
movq %rax, %rsi
#else
/* movq %rax, %rsi */
.byte 0x48
.byte 0x89
.byte 0xc6
#endif
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator64_rax)
.quad 0
/* mov imm64, %rbx */
.byte 0x48
.byte 0xbb
VARIABLE(grub_relocator64_rbx)
.quad 0
/* mov imm64, %rcx */
.byte 0x48
.byte 0xb9
VARIABLE(grub_relocator64_rcx)
.quad 0
/* mov imm64, %rdx */
.byte 0x48
.byte 0xba
VARIABLE(grub_relocator64_rdx)
.quad 0
/* Cleared direction flag is of no problem with any current
payload and makes this implementation easier. */
cld
#if defined (__APPLE__) || !defined (__x86_64__)
.byte 0xff, 0x25
.quad 0
#else
jmp *LOCAL(jump_addr) (%rip)
#endif
LOCAL(jump_addr):
VARIABLE(grub_relocator64_rip)
.quad 0
#ifdef GRUB_MACHINE_EFI
/* Here grub_relocator64_efi_start() ends. Ufff... */
VARIABLE(grub_relocator64_efi_end)
#endif
#ifndef __x86_64__
.p2align 4
LOCAL(gdt):
/* NULL. */
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/* 64-bit segment. */
.word 0xffff /* Limit xffff. */
.word 0x0000 /* Base xxxx0000. */
.byte 0x00 /* Base xx00xxxx. */
.byte (0x8 /* Type 8. */ | (1 << 4) /* Code. */ \
| (0 << 5) /* Ring 0. */ | (1 << 7) /* Present. */)
.byte (0xf /* Limit fxxxx. */ | (0 << 4) /* AVL flag. */ \
| (1 << 5) /* 64-bit. */ | (0 << 6) \
| (1 << 7) /* 4K granular. */)
.byte 0x00 /* Base 00xxxxxx. */
/* Data segment*/
.word 0xffff /* Limit xffff. */
.word 0x0000 /* Base xxxx0000. */
.byte 0x00 /* Base xx00xxxx. */
.byte (0x0 /* Type 0. */ | (0 << 4) /* Data. */ \
| (0 << 5) /* Ring 0. */ | (1 << 7) /* Present. */)
.byte (0xf /* Limit fxxxx. */ | (0 << 4) /* AVL flag. */ \
| (0 << 5) /* Data. */ | (0 << 6) \
| (1 << 7) /* 4K granular. */)
.byte 0x00 /* Base 00xxxxxx. */
/* Compatibility segment. */
.word 0xffff /* Limit xffff. */
.word 0x0000 /* Base xxxx0000. */
.byte 0x00 /* Base xx00xxxx. */
.byte (0x8 /* Type 8. */ | (1 << 4) /* Code. */ \
| (0 << 5) /* Ring 0. */ | (1 << 7) /* Present. */)
.byte (0xf /* Limit fxxxx. */ | (0 << 4) /* AVL flag. */ \
| (0 << 5) /* 32-bit. */ | (1 << 6) /* 32-bit. */ \
| (1 << 7) /* 4K granular. */)
.byte 0x00 /* Base 00xxxxxx. */
LOCAL(gdt_end):
#endif
VARIABLE(grub_relocator64_end)
|
a1ive/grub
| 2,766
|
grub-core/lib/i386/relocator_common.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009,2010 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/i386/memory.h>
#ifdef __x86_64__
#define RAX %rax
#define RSI %rsi
#else
#define RAX %eax
#define RSI %esi
#endif
.macro DISABLE_PAGING
movl %cr0, %eax
andl $(~GRUB_MEMORY_CPU_CR0_PAGING_ON), %eax
movl %eax, %cr0
.endm
.macro PREAMBLE
LOCAL(base):
/* %rax contains now our new 'base'. */
mov RAX, RSI
#if defined (__APPLE__) && defined (__x86_64__)
leaq LOCAL(cont0) (%rip), RAX
#elif defined (__APPLE__)
LOCAL(cont0_offset) = LOCAL(cont0) - LOCAL(base)
add $LOCAL(cont0_offset), RAX
#else
add $(LOCAL(cont0) - LOCAL(base)), RAX
#endif
jmp *RAX
LOCAL(cont0):
.endm
.macro RELOAD_GDT
#ifdef __APPLE__
LOCAL(cont1_offset) = LOCAL(cont1) - LOCAL(base)
LOCAL(jump_vector_offset) = LOCAL(jump_vector) - LOCAL(base)
LOCAL(gdt_offset) = LOCAL(gdt) - LOCAL(base)
LOCAL(gdt_addr_offset) = LOCAL(gdt_addr) - LOCAL(base)
LOCAL(gdtdesc_offset) = LOCAL(gdtdesc) - LOCAL(base)
lea LOCAL(cont1_offset) (RSI, 1), RAX
movl %eax, LOCAL(jump_vector_offset) (RSI, 1)
lea LOCAL(gdt_offset) (RSI, 1), RAX
mov RAX, (LOCAL(gdt_addr_offset)) (RSI, 1)
/* Switch to compatibility mode. */
lgdt (LOCAL(gdtdesc_offset)) (RSI, 1)
/* Update %cs. */
ljmp *(LOCAL(jump_vector_offset)) (RSI, 1)
.p2align 4
LOCAL(gdtdesc):
LOCAL(gdtsize) = LOCAL(gdt_end) - LOCAL(gdt)
.word LOCAL(gdtsize)
#else
lea (LOCAL(cont1) - LOCAL(base)) (RSI, 1), RAX
movl %eax, (LOCAL(jump_vector) - LOCAL(base)) (RSI, 1)
lea (LOCAL(gdt) - LOCAL(base)) (RSI, 1), RAX
mov RAX, (LOCAL(gdt_addr) - LOCAL(base)) (RSI, 1)
/* Switch to compatibility mode. */
lgdt (LOCAL(gdtdesc) - LOCAL(base)) (RSI, 1)
/* Update %cs. */
ljmp *(LOCAL(jump_vector) - LOCAL(base)) (RSI, 1)
.p2align 4
LOCAL(gdtdesc):
.word LOCAL(gdt_end) - LOCAL(gdt)
#endif
LOCAL(gdt_addr):
#ifdef __x86_64__
/* Filled by the code. */
.quad 0
#else
/* Filled by the code. */
.long 0
#endif
.p2align 4
LOCAL(jump_vector):
/* Jump location. Is filled by the code */
.long 0
.long CODE_SEGMENT
LOCAL(cont1):
.endm
|
a1ive/grub
| 1,404
|
grub-core/lib/i386/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2003,2007 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
movl %ebx, 0(%eax) /* EBX */
movl %esi, 4(%eax) /* ESI */
movl %edi, 8(%eax) /* EDI */
movl %ebp, 12(%eax) /* EBP */
popl %ecx
movl %esp, 16(%eax) /* ESP */
movl %ecx, 20(%eax) /* EIP */
xorl %eax, %eax
jmp *%ecx
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
movl 0(%eax), %ebx
movl 4(%eax), %esi
movl 8(%eax), %edi
movl 12(%eax), %ebp
movl 16(%eax), %esp
movl 20(%eax), %ecx
movl %edx, %eax
testl %eax, %eax
jnz 1f
incl %eax
1: jmp *%ecx
|
a1ive/grub
| 1,752
|
grub-core/lib/i386/relocator_asm.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/i386/memory.h>
.p2align 2
VARIABLE(grub_relocator_backward_start)
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator_backward_dest)
.long 0
movl %eax, %edi
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator_backward_src)
.long 0
movl %eax, %esi
/* mov imm32, %ecx */
.byte 0xb9
VARIABLE(grub_relocator_backward_chunk_size)
.long 0
add %ecx, %esi
add %ecx, %edi
/* Backward movsb is implicitly off-by-one. compensate that. */
sub $1, %esi
sub $1, %edi
/* Backward copy. */
std
rep
movsb
VARIABLE(grub_relocator_backward_end)
VARIABLE(grub_relocator_forward_start)
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator_forward_dest)
.long 0
movl %eax, %edi
/* mov imm32, %rax */
.byte 0xb8
VARIABLE(grub_relocator_forward_src)
.long 0
movl %eax, %esi
/* mov imm32, %ecx */
.byte 0xb9
VARIABLE(grub_relocator_forward_chunk_size)
.long 0
/* Forward copy. */
cld
rep
movsb
VARIABLE(grub_relocator_forward_end)
|
a1ive/grub
| 2,757
|
grub-core/lib/i386/relocator32.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009,2010 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
/* The code segment of the protected mode. */
#define CODE_SEGMENT 0x10
/* The data segment of the protected mode. */
#define DATA_SEGMENT 0x18
#include "relocator_common.S"
.p2align 4 /* force 16-byte alignment */
VARIABLE(grub_relocator32_start)
PREAMBLE
RELOAD_GDT
.code32
/* Update other registers. */
movl $DATA_SEGMENT, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %fs
movl %eax, %gs
movl %eax, %ss
DISABLE_PAGING
#ifdef __x86_64__
/* Disable amd64. */
movl $GRUB_MEMORY_CPU_AMD64_MSR, %ecx
rdmsr
andl $(~GRUB_MEMORY_CPU_AMD64_MSR_ON), %eax
wrmsr
#endif
/* Turn off PAE. */
movl %cr4, %eax
andl $(~GRUB_MEMORY_CPU_CR4_PAE_ON), %eax
movl %eax, %cr4
jmp LOCAL(cont2)
LOCAL(cont2):
.code32
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator32_esp)
.long 0
movl %eax, %esp
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator32_ebp)
.long 0
movl %eax, %ebp
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator32_esi)
.long 0
movl %eax, %esi
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator32_edi)
.long 0
movl %eax, %edi
/* mov imm32, %eax */
.byte 0xb8
VARIABLE(grub_relocator32_eax)
.long 0
/* mov imm32, %ebx */
.byte 0xbb
VARIABLE(grub_relocator32_ebx)
.long 0
/* mov imm32, %ecx */
.byte 0xb9
VARIABLE(grub_relocator32_ecx)
.long 0
/* mov imm32, %edx */
.byte 0xba
VARIABLE(grub_relocator32_edx)
.long 0
/* Cleared direction flag is of no problem with any current
payload and makes this implementation easier. */
cld
.byte 0xea
VARIABLE(grub_relocator32_eip)
.long 0
.word CODE_SEGMENT
/* GDT. Copied from loader/i386/linux.c. */
.p2align 4
LOCAL(gdt):
/* NULL. */
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/* Reserved. */
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
/* Code segment. */
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00
/* Data segment. */
.byte 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00
LOCAL(gdt_end):
VARIABLE(grub_relocator32_end)
|
a1ive/grub
| 7,618
|
grub-core/lib/i386/relocator16.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009,2010 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
/* The code segment of the protected mode. */
#define CODE_SEGMENT 0x08
/* The data segment of the protected mode. */
#define DATA_SEGMENT 0x10
#define PSEUDO_REAL_CSEG 0x18
#define PSEUDO_REAL_DSEG 0x20
#include <grub/i386/relocator_private.h>
#include "relocator_common.S"
.p2align 4 /* force 16-byte alignment */
VARIABLE(grub_relocator16_start)
PREAMBLE
#ifdef __APPLE__
LOCAL(cs_base_bytes12_offset) = LOCAL (cs_base_bytes12) - LOCAL (base)
LOCAL(cs_base_byte3_offset) = LOCAL (cs_base_byte3) - LOCAL (base)
LOCAL(ds_base_bytes12_offset) = LOCAL (ds_base_bytes12) - LOCAL (base)
LOCAL(ds_base_byte3_offset) = LOCAL (ds_base_byte3) - LOCAL (base)
movl %esi, %eax
movw %ax, (LOCAL(cs_base_bytes12_offset)) (RSI, 1)
movw %ax, (LOCAL(ds_base_bytes12_offset)) (RSI, 1)
shrl $16, %eax
movb %al, (LOCAL (cs_base_byte3_offset)) (RSI, 1)
movb %al, (LOCAL (ds_base_byte3_offset)) (RSI, 1)
#else
movl %esi, %eax
movw %ax, (LOCAL (cs_base_bytes12) - LOCAL (base)) (RSI, 1)
movw %ax, (LOCAL (ds_base_bytes12) - LOCAL (base)) (RSI, 1)
shrl $16, %eax
movb %al, (LOCAL (cs_base_byte3) - LOCAL (base)) (RSI, 1)
movb %al, (LOCAL (ds_base_byte3) - LOCAL (base)) (RSI, 1)
#endif
RELOAD_GDT
.code32
/* Update other registers. */
movl $DATA_SEGMENT, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %fs
movl %eax, %gs
movl %eax, %ss
DISABLE_PAGING
#ifdef __x86_64__
/* Disable amd64. */
movl $GRUB_MEMORY_CPU_AMD64_MSR, %ecx
rdmsr
andl $(~GRUB_MEMORY_CPU_AMD64_MSR_ON), %eax
wrmsr
#endif
/* Turn off PAE. */
movl %cr4, %eax
andl $(~GRUB_MEMORY_CPU_CR4_PAE_ON), %eax
movl %eax, %cr4
/* Update other registers. */
movl $PSEUDO_REAL_DSEG, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %fs
movl %eax, %gs
movl %eax, %ss
movl %esi, %eax
shrl $4, %eax
#ifdef __APPLE__
LOCAL(segment_offset) = LOCAL (segment) - LOCAL (base)
LOCAL(idt_offset) = LOCAL(relocator16_idt) - LOCAL (base)
LOCAL(cont2_offset) = LOCAL (cont2) - LOCAL(base)
movw %ax, (LOCAL(segment_offset))
lidt (LOCAL(idt_offset))
/* jump to a 16 bit segment */
ljmp $PSEUDO_REAL_CSEG, $(LOCAL(cont2_offset))
#else
movw %ax, (LOCAL (segment) - LOCAL (base))
lidt (EXT_C(grub_relocator16_idt) - LOCAL (base))
/* jump to a 16 bit segment */
ljmp $PSEUDO_REAL_CSEG, $(LOCAL (cont2) - LOCAL(base))
#endif
LOCAL(cont2):
.code16
/* clear the PE bit of CR0 */
movl %cr0, %eax
andl $(~GRUB_MEMORY_CPU_CR0_PE_ON), %eax
movl %eax, %cr0
/* flush prefetch queue, reload %cs */
/* ljmp */
.byte 0xea
#ifdef __APPLE__
LOCAL(cont3_offset) = LOCAL(cont3) - LOCAL(base)
.word LOCAL(cont3_offset)
#else
.word LOCAL(cont3)-LOCAL(base)
#endif
LOCAL(segment):
.word 0
LOCAL(cont3):
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_keep_a20_enabled)
.word 0
test %ax, %ax
jnz LOCAL(gate_a20_done)
movw %cs, %ax
movw %ax, %ss
#ifdef __APPLE__
LOCAL(relocator16_end_offset) = LOCAL(relocator16_end) - LOCAL(base)
leaw LOCAL(relocator16_end_offset), %sp
#else
leaw LOCAL(relocator16_end) - LOCAL(base), %sp
#endif
addw $GRUB_RELOCATOR16_STACK_SIZE, %sp
/* second, try a BIOS call */
movw $0x2400, %ax
int $0x15
call LOCAL(gate_a20_check_state)
testb %al, %al
jz LOCAL(gate_a20_done)
/*
* In macbook, the keyboard test would hang the machine, so we move
* this forward.
*/
/* fourth, try the system control port A */
inb $0x92
andb $(~0x03), %al
outb $0x92
/* When turning off Gate A20, do not check the state strictly,
because a failure is not fatal usually, and Gate A20 is always
on some modern machines. */
jmp LOCAL(gate_a20_done)
LOCAL(gate_a20_check_state):
/* iterate the checking for a while */
movw $100, %cx
1:
xorw %ax, %ax
movw %ax, %ds
decw %ax
movw %ax, %es
xorw %ax, %ax
movw $0x8000, %ax
/* compare the byte at ADDR with that at 0x100000 + ADDR */
movw %ax, %si
addw $0x10, %ax
movw %ax, %di
/* save the original byte in DL */
movb %ds:(%si), %dl
movb %es:(%di), %al
/* try to set one less value at ADDR */
movb %al, %dh
decb %dh
movb %dh, %ds:(%si)
/* serialize */
outb %al, $0x80
outb %al, $0x80
/* obtain the value at 0x100000 + ADDR in CH */
movb %es:(%di), %dh
/* this result is 1 if A20 is on or 0 if it is off */
subb %dh, %al
xorb $1, %al
/* restore the original */
movb %dl, %ds:(%si)
testb %al, %al
jz LOCAL(gate_a20_done)
loop 1b
2:
ret
LOCAL(gate_a20_done):
/*
* We are in real mode now. Set up the real mode segment registers and
* all the other general purpose registers. cs is updated with ljmp.
*/
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_ds)
.word 0
movw %ax, %ds
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_es)
.word 0
movw %ax, %es
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_fs)
.word 0
movw %ax, %fs
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_gs)
.word 0
movw %ax, %gs
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_ss)
.word 0
movw %ax, %ss
/* movw imm16, %ax. */
.byte 0xb8
VARIABLE(grub_relocator16_sp)
.word 0
movzwl %ax, %esp
/* movw imm32, %eax. */
.byte 0x66, 0xb8
VARIABLE(grub_relocator16_esi)
.long 0
movl %eax, %esi
/* movw imm32, %edx. */
.byte 0x66, 0xba
VARIABLE(grub_relocator16_edx)
.long 0
/* movw imm32, %ebx. */
.byte 0x66, 0xbb
VARIABLE(grub_relocator16_ebx)
.long 0
/* movl imm32, %ebp. */
.byte 0x66, 0xbd
VARIABLE(grub_relocator16_ebp)
.long 0
/* Cleared direction flag is of no problem with any current
payload and makes this implementation easier. */
cld
/* ljmp */
.byte 0xea
VARIABLE(grub_relocator16_ip)
.word 0
VARIABLE(grub_relocator16_cs)
.word 0
.code32
/* GDT. Copied from loader/i386/linux.c. */
.p2align 4
LOCAL(gdt):
.word 0, 0
.byte 0, 0, 0, 0
/* -- code segment --
* base = 0x00000000, limit = 0xFFFFF (4 KiB Granularity), present
* type = 32bit code execute/read, DPL = 0
*/
.word 0xFFFF, 0
.byte 0, 0x9A, 0xCF, 0
/* -- data segment --
* base = 0x00000000, limit 0xFFFFF (4 KiB Granularity), present
* type = 32 bit data read/write, DPL = 0
*/
.word 0xFFFF, 0
.byte 0, 0x92, 0xCF, 0
/* -- 16 bit real mode CS --
* base = filled by code, limit 0x0FFFF (1 B Granularity), present
* type = 16 bit code execute/read only/conforming, DPL = 0
*/
.word 0xFFFF
LOCAL(cs_base_bytes12):
.word 0
LOCAL(cs_base_byte3):
.byte 0
.byte 0x9E, 0, 0
/* -- 16 bit real mode DS --
* base = filled by code, limit 0x0FFFF (1 B Granularity), present
* type = 16 bit data read/write, DPL = 0
*/
.word 0xFFFF
LOCAL(ds_base_bytes12):
.word 0
LOCAL(ds_base_byte3):
.byte 0
.byte 0x92, 0, 0
LOCAL(gdt_end):
#ifdef __APPLE__
LOCAL(relocator16_idt):
#endif
VARIABLE(grub_relocator16_idt)
.word 0
.long 0
LOCAL(relocator16_end):
VARIABLE(grub_relocator16_end)
.byte 0
|
a1ive/grub
| 3,856
|
grub-core/lib/ia64/setjmp.S
|
/* Copyright (C) 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA.
The layout of the jmp_buf is as follows. This is subject to change
and user-code should never depend on the particular layout of
jmp_buf!
offset: description:
------- ------------
0x000 stack pointer (r12) ; unchangeable (see _JMPBUF_UNWINDS)
0x008 r1 (gp)
0x010 caller's unat
0x018 fpsr
0x020 r4
0x028 r5
0x030 r6
0x038 r7
0x040 rp (b0)
0x048 b1
0x050 b2
0x058 b3
0x060 b4
0x068 b5
0x070 ar.pfs
0x078 ar.lc
0x080 pr
0x088 ar.bsp ; unchangeable (see __longjmp.S)
0x090 ar.unat
0x098 &__jmp_buf ; address of the jmpbuf (needed to locate NaT bits in unat)
0x0a0 f2
0x0b0 f3
0x0c0 f4
0x0d0 f5
0x0e0 f16
0x0f0 f17
0x100 f18
0x110 f19
0x120 f20
0x130 f21
0x130 f22
0x140 f23
0x150 f24
0x160 f25
0x170 f26
0x180 f27
0x190 f28
0x1a0 f29
0x1b0 f30
0x1c0 f31 */
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv2+"
/* The following two entry points are the traditional entry points: */
.text
.proc EXT_C(grub_setjmp)
FUNCTION(grub_setjmp)
alloc r8=ar.pfs,2,0,0,0
mov in1=1
br.cond.sptk.many __sigsetjmp
.endp EXT_C(grub_setjmp)
/* __sigsetjmp(__jmp_buf buf, int savemask) */
.proc __sigsetjmp
__sigsetjmp:
//.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
alloc loc1=ar.pfs,2,2,2,0
mov r16=ar.unat
;;
mov r17=ar.fpsr
mov r2=in0
add r3=8,in0
;;
st8.spill.nta [r2]=sp,16 // r12 (sp)
st8.spill.nta [r3]=gp,16 // r1 (gp)
;;
st8.nta [r2]=r16,16 // save caller's unat
st8.nta [r3]=r17,16 // save fpsr
add r8=0xa0,in0
;;
st8.spill.nta [r2]=r4,16 // r4
st8.spill.nta [r3]=r5,16 // r5
add r9=0xb0,in0
;;
stf.spill.nta [r8]=f2,32
stf.spill.nta [r9]=f3,32
mov loc0=rp
.body
;;
stf.spill.nta [r8]=f4,32
stf.spill.nta [r9]=f5,32
mov r17=b1
;;
stf.spill.nta [r8]=f16,32
stf.spill.nta [r9]=f17,32
mov r18=b2
;;
stf.spill.nta [r8]=f18,32
stf.spill.nta [r9]=f19,32
mov r19=b3
;;
stf.spill.nta [r8]=f20,32
stf.spill.nta [r9]=f21,32
mov r20=b4
;;
stf.spill.nta [r8]=f22,32
stf.spill.nta [r9]=f23,32
mov r21=b5
;;
stf.spill.nta [r8]=f24,32
stf.spill.nta [r9]=f25,32
mov r22=ar.lc
;;
stf.spill.nta [r8]=f26,32
stf.spill.nta [r9]=f27,32
mov r24=pr
;;
stf.spill.nta [r8]=f28,32
stf.spill.nta [r9]=f29,32
;;
stf.spill.nta [r8]=f30
stf.spill.nta [r9]=f31
st8.spill.nta [r2]=r6,16 // r6
st8.spill.nta [r3]=r7,16 // r7
;;
mov r23=ar.bsp
mov r25=ar.unat
mov out0=in0
st8.nta [r2]=loc0,16 // b0
st8.nta [r3]=r17,16 // b1
mov out1=in1
;;
st8.nta [r2]=r18,16 // b2
st8.nta [r3]=r19,16 // b3
;;
st8.nta [r2]=r20,16 // b4
st8.nta [r3]=r21,16 // b5
;;
st8.nta [r2]=loc1,16 // ar.pfs
st8.nta [r3]=r22,16 // ar.lc
;;
st8.nta [r2]=r24,16 // pr
st8.nta [r3]=r23,16 // ar.bsp
;;
st8.nta [r2]=r25 // ar.unat
st8.nta [r3]=in0 // &__jmp_buf
mov r8=0
mov rp=loc0
mov ar.pfs=loc1
br.ret.sptk.many rp
.endp __sigsetjmp
|
a1ive/grub
| 4,420
|
grub-core/lib/ia64/longjmp.S
|
/* Copyright (C) 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA.
Note that __sigsetjmp() did NOT flush the register stack. Instead,
we do it here since __longjmp() is usually much less frequently
invoked than __sigsetjmp(). The only difficulty is that __sigsetjmp()
didn't (and wouldn't be able to) save ar.rnat either. This is a problem
because if we're not careful, we could end up loading random NaT bits.
There are two cases:
(i) ar.bsp < ia64_rse_rnat_addr(jmpbuf.ar_bsp)
ar.rnat contains the desired bits---preserve ar.rnat
across loadrs and write to ar.bspstore
(ii) ar.bsp >= ia64_rse_rnat_addr(jmpbuf.ar_bsp)
The desired ar.rnat is stored in
ia64_rse_rnat_addr(jmpbuf.ar_bsp). Load those
bits into ar.rnat after setting ar.bspstore. */
# define pPos p6 /* is rotate count positive? */
# define pNeg p7 /* is rotate count negative? */
/* __longjmp(__jmp_buf buf, int val) */
.text
.proc EXT_C(grub_longjmp)
FUNCTION(grub_longjmp)
alloc r8=ar.pfs,2,1,0,0
mov r27=ar.rsc
add r2=0x98,in0 // r2 <- &jmpbuf.orig_jmp_buf_addr
;;
ld8 r8=[r2],-16 // r8 <- orig_jmp_buf_addr
mov r10=ar.bsp
and r11=~0x3,r27 // clear ar.rsc.mode
;;
flushrs // flush dirty regs to backing store (must be first in insn grp)
ld8 r23=[r2],8 // r23 <- jmpbuf.ar_bsp
sub r8=r8,in0 // r8 <- &orig_jmpbuf - &jmpbuf
;;
ld8 r25=[r2] // r25 <- jmpbuf.ar_unat
extr.u r8=r8,3,6 // r8 <- (&orig_jmpbuf - &jmpbuf)/8 & 0x3f
;;
cmp.lt pNeg,pPos=r8,r0
mov r2=in0
;;
(pPos) mov r16=r8
(pNeg) add r16=64,r8
(pPos) sub r17=64,r8
(pNeg) sub r17=r0,r8
;;
mov ar.rsc=r11 // put RSE in enforced lazy mode
shr.u r8=r25,r16
add r3=8,in0 // r3 <- &jmpbuf.r1
shl r9=r25,r17
;;
or r25=r8,r9
;;
mov r26=ar.rnat
mov ar.unat=r25 // setup ar.unat (NaT bits for r1, r4-r7, and r12)
;;
ld8.fill.nta sp=[r2],16 // r12 (sp)
ld8.fill.nta gp=[r3],16 // r1 (gp)
dep r11=-1,r23,3,6 // r11 <- ia64_rse_rnat_addr(jmpbuf.ar_bsp)
;;
ld8.nta r16=[r2],16 // caller's unat
ld8.nta r17=[r3],16 // fpsr
;;
ld8.fill.nta r4=[r2],16 // r4
ld8.fill.nta r5=[r3],16 // r5 (gp)
cmp.geu p8,p0=r10,r11 // p8 <- (ar.bsp >= jmpbuf.ar_bsp)
;;
ld8.fill.nta r6=[r2],16 // r6
ld8.fill.nta r7=[r3],16 // r7
;;
mov ar.unat=r16 // restore caller's unat
mov ar.fpsr=r17 // restore fpsr
;;
ld8.nta r16=[r2],16 // b0
ld8.nta r17=[r3],16 // b1
;;
(p8) ld8 r26=[r11] // r26 <- *ia64_rse_rnat_addr(jmpbuf.ar_bsp)
mov ar.bspstore=r23 // restore ar.bspstore
;;
ld8.nta r18=[r2],16 // b2
ld8.nta r19=[r3],16 // b3
;;
ld8.nta r20=[r2],16 // b4
ld8.nta r21=[r3],16 // b5
;;
ld8.nta r11=[r2],16 // ar.pfs
ld8.nta r22=[r3],56 // ar.lc
;;
ld8.nta r24=[r2],32 // pr
mov b0=r16
;;
ldf.fill.nta f2=[r2],32
ldf.fill.nta f3=[r3],32
mov b1=r17
;;
ldf.fill.nta f4=[r2],32
ldf.fill.nta f5=[r3],32
mov b2=r18
;;
ldf.fill.nta f16=[r2],32
ldf.fill.nta f17=[r3],32
mov b3=r19
;;
ldf.fill.nta f18=[r2],32
ldf.fill.nta f19=[r3],32
mov b4=r20
;;
ldf.fill.nta f20=[r2],32
ldf.fill.nta f21=[r3],32
mov b5=r21
;;
ldf.fill.nta f22=[r2],32
ldf.fill.nta f23=[r3],32
mov ar.lc=r22
;;
ldf.fill.nta f24=[r2],32
ldf.fill.nta f25=[r3],32
cmp.eq p8,p9=0,in1
;;
ldf.fill.nta f26=[r2],32
ldf.fill.nta f27=[r3],32
mov ar.pfs=r11
;;
ldf.fill.nta f28=[r2],32
ldf.fill.nta f29=[r3],32
;;
ldf.fill.nta f30=[r2]
ldf.fill.nta f31=[r3]
(p8) mov r8=1
mov ar.rnat=r26 // restore ar.rnat
;;
mov ar.rsc=r27 // restore ar.rsc
(p9) mov r8=in1
invala // virt. -> phys. regnum mapping may change
mov pr=r24,-1
br.ret.dptk.few rp
.endp EXT_C(grub_longjmp)
|
a1ive/grub
| 2,202
|
grub-core/lib/riscv/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2018 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
#if __riscv_xlen == 64
#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
#else
#define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
#define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
#endif
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
/* Preserve all callee-saved registers and the SP */
STORE_IDX(s0, 0)
STORE_IDX(s1, 1)
STORE_IDX(s2, 2)
STORE_IDX(s3, 3)
STORE_IDX(s4, 4)
STORE_IDX(s5, 5)
STORE_IDX(s6, 6)
STORE_IDX(s7, 7)
STORE_IDX(s8, 8)
STORE_IDX(s9, 9)
STORE_IDX(s10, 10)
STORE_IDX(s11, 11)
STORE_IDX(ra, 12)
STORE_IDX(sp, 13)
li a0, 0
ret
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
LOAD_IDX(s0, 0)
LOAD_IDX(s1, 1)
LOAD_IDX(s2, 2)
LOAD_IDX(s3, 3)
LOAD_IDX(s4, 4)
LOAD_IDX(s5, 5)
LOAD_IDX(s6, 6)
LOAD_IDX(s7, 7)
LOAD_IDX(s8, 8)
LOAD_IDX(s9, 9)
LOAD_IDX(s10, 10)
LOAD_IDX(s11, 11)
LOAD_IDX(ra, 12)
LOAD_IDX(sp, 13)
/* Move the return value in place, but return 1 if passed 0. */
beq a1, zero, longjmp_1
mv a0, a1
ret
longjmp_1:
li a0, 1
ret
|
a1ive/grub
| 1,303
|
grub-core/lib/sparc64/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2005,2007,2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
stx %o7, [%o0 + 0x00]
stx %sp, [%o0 + 0x08]
stx %fp, [%o0 + 0x10]
retl
clr %o0
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
ldx [%o0 + 0x10], %g1
movrz %o1, 1, %o1
save %sp, -64, %sp
flushw
restore
ldx [%o0 + 0x00], %o7
ldx [%o0 + 0x08], %fp
sub %fp, 192, %sp
stx %g1, [%sp + 2047 + (14 * 8)]
retl
restore %o1, 0, %o0
|
a1ive/grub
| 1,189
|
grub-core/lib/arm/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2013 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.syntax unified
#if !defined (__thumb2__)
.arm
#else
.thumb
#endif
.text
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
mov r12, sp
stm r0, { r4-r12, lr }
mov r0, #0
bx lr
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
ldm r0, { r4-r12, lr }
mov sp, r12
movs r0, r1
it eq
moveq r0, #1
bx lr
|
a1ive/grub
| 1,401
|
grub-core/lib/arm64/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2013 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
stp x19, x20, [x0], #16
stp x21, x22, [x0], #16
stp x23, x24, [x0], #16
stp x25, x26, [x0], #16
stp x27, x28, [x0], #16
stp x29, x30, [x0], #16
mov x1, sp
str x1, [x0]
mov x0, #0
ret
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
ldp x19, x20, [x0], #16
ldp x21, x22, [x0], #16
ldp x23, x24, [x0], #16
ldp x25, x26, [x0], #16
ldp x27, x28, [x0], #16
ldp x29, x30, [x0], #16
ldr x2, [x0]
mov sp, x2
mov x0, #1
cmp x1, #0
csel x0, x1, x0, ne
ret
|
a1ive/grub
| 1,642
|
grub-core/lib/x86_64/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2003,2007 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
/*
* jmp_buf:
* rbx rsp rbp r12 r13 r14 r15 rip
* 0 8 16 24 32 40 48 56
*/
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
pop %rsi /* Return address, and adjust the stack */
xorq %rax, %rax
movq %rbx, 0(%rdi) /* RBX */
movq %rsp, 8(%rdi) /* RSP */
push %rsi
movq %rbp, 16(%rdi) /* RBP */
movq %r12, 24(%rdi) /* R12 */
movq %r13, 32(%rdi) /* R13 */
movq %r14, 40(%rdi) /* R14 */
movq %r15, 48(%rdi) /* R15 */
movq %rsi, 56(%rdi) /* RSI */
ret
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
movl %esi, %eax
orl %eax, %eax
jnz 1f
incl %eax
1:
movq (%rdi), %rbx
movq 8(%rdi), %rsp
movq 16(%rdi), %rbp
movq 24(%rdi), %r12
movq 32(%rdi), %r13
movq 40(%rdi), %r14
movq 48(%rdi), %r15
jmp *56(%rdi)
|
a1ive/grub
| 1,840
|
grub-core/lib/x86_64/relocator_asm.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/i386/memory.h>
.p2align 2
VARIABLE(grub_relocator_backward_start)
/* mov imm32, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator_backward_dest)
.long 0, 0
movq %rax, %rdi
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator_backward_src)
.long 0, 0
movq %rax, %rsi
/* mov imm64, %rcx */
.byte 0x48
.byte 0xb9
VARIABLE(grub_relocator_backward_chunk_size)
.long 0, 0
add %rcx, %rsi
add %rcx, %rdi
/* Backward movsb is implicitly off-by-one. compensate that. */
sub $1, %rsi
sub $1, %rdi
/* Backward copy. */
std
rep
movsb
VARIABLE(grub_relocator_backward_end)
VARIABLE(grub_relocator_forward_start)
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator_forward_dest)
.long 0, 0
movq %rax, %rdi
/* mov imm64, %rax */
.byte 0x48
.byte 0xb8
VARIABLE(grub_relocator_forward_src)
.long 0, 0
movq %rax, %rsi
/* mov imm64, %rcx */
.byte 0x48
.byte 0xb9
VARIABLE(grub_relocator_forward_chunk_size)
.long 0, 0
/* Forward copy. */
cld
rep
movsb
VARIABLE(grub_relocator_forward_end)
|
a1ive/grub
| 1,850
|
grub-core/lib/mips/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2003,2007,2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
#include <grub/mips/asm.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
GRUB_ASM_REG_S $s0, 0($a0)
GRUB_ASM_REG_S $s1, 8($a0)
GRUB_ASM_REG_S $s2, 16($a0)
GRUB_ASM_REG_S $s3, 24($a0)
GRUB_ASM_REG_S $s4, 32($a0)
GRUB_ASM_REG_S $s5, 40($a0)
GRUB_ASM_REG_S $s6, 48($a0)
GRUB_ASM_REG_S $s7, 56($a0)
GRUB_ASM_REG_S $s8, 64($a0)
GRUB_ASM_REG_S $gp, 72($a0)
GRUB_ASM_REG_S $sp, 80($a0)
GRUB_ASM_REG_S $ra, 88($a0)
move $v0, $zero
move $v1, $zero
jr $ra
nop
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
GRUB_ASM_REG_L $s0, 0($a0)
GRUB_ASM_REG_L $s1, 8($a0)
GRUB_ASM_REG_L $s2, 16($a0)
GRUB_ASM_REG_L $s3, 24($a0)
GRUB_ASM_REG_L $s4, 32($a0)
GRUB_ASM_REG_L $s5, 40($a0)
GRUB_ASM_REG_L $s6, 48($a0)
GRUB_ASM_REG_L $s7, 56($a0)
GRUB_ASM_REG_L $s8, 64($a0)
GRUB_ASM_REG_L $gp, 72($a0)
GRUB_ASM_REG_L $sp, 80($a0)
GRUB_ASM_REG_L $ra, 88($a0)
move $v0, $a1
bne $v0, $zero, 1f
addiu $v0, $v0, 1
1:
move $v1, $zero
jr $ra
nop
|
a1ive/grub
| 1,522
|
grub-core/lib/mips/relocator_asm.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
.p2align 4 /* force 16-byte alignment */
.set noreorder
.set nomacro
VARIABLE (grub_relocator_forward_start)
move $a0, $9
move $a1, $10
copycont1:
lb $11,0($8)
sb $11,0($9)
addiu $8, $8, 1
addiu $10, $10, -1
bne $10, $0, copycont1
addiu $9, $9, 1
#include "../../kern/mips/cache_flush.S"
VARIABLE (grub_relocator_forward_end)
VARIABLE (grub_relocator_backward_start)
move $a0, $9
move $a1, $10
addu $9, $9, $10
addu $8, $8, $10
/* Backward movsl is implicitly off-by-one. compensate that. */
addiu $9, $9, -1
addiu $8, $8, -1
copycont2:
lb $11,0($8)
sb $11,0($9)
addiu $8, $8, -1
addiu $10, $10, -1
bne $10, $0, copycont2
addiu $9, $9, -1
#include "../../kern/mips/cache_flush.S"
VARIABLE (grub_relocator_backward_end)
|
a1ive/grub
| 1,688
|
grub-core/lib/powerpc/setjmp.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2004,2007 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
#include <grub/dl.h>
.file "setjmp.S"
GRUB_MOD_LICENSE "GPLv3+"
.text
/*
* int grub_setjmp (grub_jmp_buf env)
*/
FUNCTION(grub_setjmp)
stw 1, 0(3)
stw 14, 4(3)
stw 15, 8(3)
stw 16, 12(3)
stw 17, 16(3)
stw 18, 20(3)
stw 19, 24(3)
stw 20, 28(3)
stw 21, 32(3)
stw 22, 36(3)
stw 23, 40(3)
stw 24, 44(3)
stw 25, 48(3)
stw 26, 52(3)
stw 27, 56(3)
stw 28, 60(3)
stw 29, 64(3)
stw 30, 68(3)
stw 31, 72(3)
mflr 4
stw 4, 76(3)
mfcr 4
stw 4, 80(3)
li 3, 0
blr
/*
* int grub_longjmp (grub_jmp_buf env, int val)
*/
FUNCTION(grub_longjmp)
lwz 1, 0(3)
lwz 14, 4(3)
lwz 15, 8(3)
lwz 16, 12(3)
lwz 17, 16(3)
lwz 18, 20(3)
lwz 19, 24(3)
lwz 20, 28(3)
lwz 21, 32(3)
lwz 22, 36(3)
lwz 23, 40(3)
lwz 24, 44(3)
lwz 25, 48(3)
lwz 26, 52(3)
lwz 27, 56(3)
lwz 28, 60(3)
lwz 29, 64(3)
lwz 30, 68(3)
lwz 31, 72(3)
lwz 5, 76(3)
mtlr 5
lwz 5, 80(3)
mtcr 5
mr. 3, 4
bne 1f
li 3, 1
1: blr
|
a1ive/grub
| 1,456
|
grub-core/lib/powerpc/relocator_asm.S
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2009,2010 Free Software Foundation, Inc.
*
* GRUB is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GRUB is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
*/
#include <grub/symbol.h>
.p2align 4 /* force 16-byte alignment */
VARIABLE (grub_relocator_forward_start)
mr 3, 9
mr 4, 10
copycont1:
lbz 11,0(8)
stb 11,0(9)
addi 8, 8, 0x1
addi 9, 9, 0x1
addi 10, 10, -1
cmpwi 10, 0
bne copycont1
#include "../../kern/powerpc/cache_flush.S"
VARIABLE (grub_relocator_forward_end)
VARIABLE (grub_relocator_backward_start)
mr 3, 9
mr 4, 10
add 9, 9, 10
add 8, 8, 10
/* Backward movsl is implicitly off-by-one. compensate that. */
addi 9, 9, -1
addi 8, 8, -1
copycont2:
lbz 11,0(8)
stb 11,0(9)
addi 8, 8, -1
addi 9, 9, -1
addi 10, 10, -1
cmpwi 10, 0
bne copycont2
#include "../../kern/powerpc/cache_flush.S"
VARIABLE (grub_relocator_backward_end)
|
a1ive/grub
| 2,545
|
grub-core/lib/libgcrypt/mpi/i586/mpih-mul1.S
|
/* i80586 mul_1 -- Multiply a limb vector with a limb and store
* the result in a second limb vector.
*
* Copyright (C) 1992, 1994, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_mul_1( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_size_t s1_size, (sp + 12)
* mpi_limb_t s2_limb) (sp + 16)
*/
#define res_ptr edi
#define s1_ptr esi
#define size ecx
#define s2_limb ebp
TEXT
ALIGN (3)
GLOBL C_SYMBOL_NAME(_gcry_mpih_mul_1)
C_SYMBOL_NAME(_gcry_mpih_mul_1:)
INSN1(push,l ,R(edi))
INSN1(push,l ,R(esi))
INSN1(push,l ,R(ebx))
INSN1(push,l ,R(ebp))
INSN2(mov,l ,R(res_ptr),MEM_DISP(esp,20))
INSN2(mov,l ,R(s1_ptr),MEM_DISP(esp,24))
INSN2(mov,l ,R(size),MEM_DISP(esp,28))
INSN2(mov,l ,R(s2_limb),MEM_DISP(esp,32))
INSN2(lea,l ,R(res_ptr),MEM_INDEX(res_ptr,size,4))
INSN2(lea,l ,R(s1_ptr),MEM_INDEX(s1_ptr,size,4))
INSN1(neg,l ,R(size))
INSN2(xor,l ,R(ebx),R(ebx))
ALIGN (3)
Loop: INSN2(adc,l ,R(ebx),$0)
INSN2(mov,l ,R(eax),MEM_INDEX(s1_ptr,size,4))
INSN1(mul,l ,R(s2_limb))
INSN2(add,l ,R(ebx),R(eax))
INSN2(mov,l ,MEM_INDEX(res_ptr,size,4),R(ebx))
INSN1(inc,l ,R(size))
INSN2(mov,l ,R(ebx),R(edx))
INSN1(jnz, ,Loop)
INSN2(adc,l ,R(ebx),$0)
INSN2(mov,l ,R(eax),R(ebx))
INSN1(pop,l ,R(ebp))
INSN1(pop,l ,R(ebx))
INSN1(pop,l ,R(esi))
INSN1(pop,l ,R(edi))
ret
|
a1ive/grub
| 2,684
|
grub-core/lib/libgcrypt/mpi/i586/mpih-mul2.S
|
/* i80586 addmul_1 -- Multiply a limb vector with a limb and add
* the result to a second limb vector.
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_addmul_1( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_size_t s1_size, (sp + 12)
* mpi_limb_t s2_limb) (sp + 16)
*/
#define res_ptr edi
#define s1_ptr esi
#define size ecx
#define s2_limb ebp
TEXT
ALIGN (3)
GLOBL C_SYMBOL_NAME(_gcry_mpih_addmul_1)
C_SYMBOL_NAME(_gcry_mpih_addmul_1:)
INSN1(push,l ,R(edi))
INSN1(push,l ,R(esi))
INSN1(push,l ,R(ebx))
INSN1(push,l ,R(ebp))
INSN2(mov,l ,R(res_ptr),MEM_DISP(esp,20))
INSN2(mov,l ,R(s1_ptr),MEM_DISP(esp,24))
INSN2(mov,l ,R(size),MEM_DISP(esp,28))
INSN2(mov,l ,R(s2_limb),MEM_DISP(esp,32))
INSN2(lea,l ,R(res_ptr),MEM_INDEX(res_ptr,size,4))
INSN2(lea,l ,R(s1_ptr),MEM_INDEX(s1_ptr,size,4))
INSN1(neg,l ,R(size))
INSN2(xor,l ,R(ebx),R(ebx))
ALIGN (3)
Loop: INSN2(adc,l ,R(ebx),$0)
INSN2(mov,l ,R(eax),MEM_INDEX(s1_ptr,size,4))
INSN1(mul,l ,R(s2_limb))
INSN2(add,l ,R(eax),R(ebx))
INSN2(mov,l ,R(ebx),MEM_INDEX(res_ptr,size,4))
INSN2(adc,l ,R(edx),$0)
INSN2(add,l ,R(ebx),R(eax))
INSN2(mov,l ,MEM_INDEX(res_ptr,size,4),R(ebx))
INSN1(inc,l ,R(size))
INSN2(mov,l ,R(ebx),R(edx))
INSN1(jnz, ,Loop)
INSN2(adc,l ,R(ebx),$0)
INSN2(mov,l ,R(eax),R(ebx))
INSN1(pop,l ,R(ebp))
INSN1(pop,l ,R(ebx))
INSN1(pop,l ,R(esi))
INSN1(pop,l ,R(edi))
ret
|
a1ive/grub
| 4,816
|
grub-core/lib/libgcrypt/mpi/i586/mpih-lshift.S
|
/* i80586 lshift
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_lshift( mpi_ptr_t wp, (sp + 4)
* mpi_ptr_t up, (sp + 8)
* mpi_size_t usize, (sp + 12)
* unsigned cnt) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_lshift)
C_SYMBOL_NAME(_gcry_mpih_lshift:)
pushl %edi
pushl %esi
pushl %ebx
pushl %ebp
movl 20(%esp),%edi /* res_ptr */
movl 24(%esp),%esi /* s_ptr */
movl 28(%esp),%ebp /* size */
movl 32(%esp),%ecx /* cnt */
/* We can use faster code for shift-by-1 under certain conditions. */
cmp $1,%ecx
jne Lnormal
leal 4(%esi),%eax
cmpl %edi,%eax
jnc Lspecial /* jump if s_ptr + 1 >= res_ptr */
leal (%esi,%ebp,4),%eax
cmpl %eax,%edi
jnc Lspecial /* jump if res_ptr >= s_ptr + size */
Lnormal:
leal -4(%edi,%ebp,4),%edi
leal -4(%esi,%ebp,4),%esi
movl (%esi),%edx
subl $4,%esi
xorl %eax,%eax
shldl %cl,%edx,%eax /* compute carry limb */
pushl %eax /* push carry limb onto stack */
decl %ebp
pushl %ebp
shrl $3,%ebp
jz Lend
movl (%edi),%eax /* fetch destination cache line */
ALIGN (2)
Loop: movl -28(%edi),%eax /* fetch destination cache line */
movl %edx,%ebx
movl (%esi),%eax
movl -4(%esi),%edx
shldl %cl,%eax,%ebx
shldl %cl,%edx,%eax
movl %ebx,(%edi)
movl %eax,-4(%edi)
movl -8(%esi),%ebx
movl -12(%esi),%eax
shldl %cl,%ebx,%edx
shldl %cl,%eax,%ebx
movl %edx,-8(%edi)
movl %ebx,-12(%edi)
movl -16(%esi),%edx
movl -20(%esi),%ebx
shldl %cl,%edx,%eax
shldl %cl,%ebx,%edx
movl %eax,-16(%edi)
movl %edx,-20(%edi)
movl -24(%esi),%eax
movl -28(%esi),%edx
shldl %cl,%eax,%ebx
shldl %cl,%edx,%eax
movl %ebx,-24(%edi)
movl %eax,-28(%edi)
subl $32,%esi
subl $32,%edi
decl %ebp
jnz Loop
Lend: popl %ebp
andl $7,%ebp
jz Lend2
Loop2: movl (%esi),%eax
shldl %cl,%eax,%edx
movl %edx,(%edi)
movl %eax,%edx
subl $4,%esi
subl $4,%edi
decl %ebp
jnz Loop2
Lend2: shll %cl,%edx /* compute least significant limb */
movl %edx,(%edi) /* store it */
popl %eax /* pop carry limb */
popl %ebp
popl %ebx
popl %esi
popl %edi
ret
/* We loop from least significant end of the arrays, which is only
permissable if the source and destination don't overlap, since the
function is documented to work for overlapping source and destination.
*/
Lspecial:
movl (%esi),%edx
addl $4,%esi
decl %ebp
pushl %ebp
shrl $3,%ebp
addl %edx,%edx
incl %ebp
decl %ebp
jz LLend
movl (%edi),%eax /* fetch destination cache line */
ALIGN (2)
LLoop: movl 28(%edi),%eax /* fetch destination cache line */
movl %edx,%ebx
movl (%esi),%eax
movl 4(%esi),%edx
adcl %eax,%eax
movl %ebx,(%edi)
adcl %edx,%edx
movl %eax,4(%edi)
movl 8(%esi),%ebx
movl 12(%esi),%eax
adcl %ebx,%ebx
movl %edx,8(%edi)
adcl %eax,%eax
movl %ebx,12(%edi)
movl 16(%esi),%edx
movl 20(%esi),%ebx
adcl %edx,%edx
movl %eax,16(%edi)
adcl %ebx,%ebx
movl %edx,20(%edi)
movl 24(%esi),%eax
movl 28(%esi),%edx
adcl %eax,%eax
movl %ebx,24(%edi)
adcl %edx,%edx
movl %eax,28(%edi)
leal 32(%esi),%esi /* use leal not to clobber carry */
leal 32(%edi),%edi
decl %ebp
jnz LLoop
LLend: popl %ebp
sbbl %eax,%eax /* save carry in %eax */
andl $7,%ebp
jz LLend2
addl %eax,%eax /* restore carry from eax */
LLoop2: movl %edx,%ebx
movl (%esi),%edx
adcl %edx,%edx
movl %ebx,(%edi)
leal 4(%esi),%esi /* use leal not to clobber carry */
leal 4(%edi),%edi
decl %ebp
jnz LLoop2
jmp LL1
LLend2: addl %eax,%eax /* restore carry from eax */
LL1: movl %edx,(%edi) /* store last limb */
sbbl %eax,%eax
negl %eax
popl %ebp
popl %ebx
popl %esi
popl %edi
ret
|
a1ive/grub
| 4,825
|
grub-core/lib/libgcrypt/mpi/i586/mpih-rshift.S
|
/* i80586 rshift
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_rshift( mpi_ptr_t wp, (sp + 4)
* mpi_ptr_t up, (sp + 8)
* mpi_size_t usize, (sp + 12)
* unsigned cnt) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_rshift)
C_SYMBOL_NAME(_gcry_mpih_rshift:)
pushl %edi
pushl %esi
pushl %ebx
pushl %ebp
movl 20(%esp),%edi /* res_ptr */
movl 24(%esp),%esi /* s_ptr */
movl 28(%esp),%ebp /* size */
movl 32(%esp),%ecx /* cnt */
/* We can use faster code for shift-by-1 under certain conditions. */
cmp $1,%ecx
jne Rnormal
leal 4(%edi),%eax
cmpl %esi,%eax
jnc Rspecial /* jump if res_ptr + 1 >= s_ptr */
leal (%edi,%ebp,4),%eax
cmpl %eax,%esi
jnc Rspecial /* jump if s_ptr >= res_ptr + size */
Rnormal:
movl (%esi),%edx
addl $4,%esi
xorl %eax,%eax
shrdl %cl,%edx,%eax /* compute carry limb */
pushl %eax /* push carry limb onto stack */
decl %ebp
pushl %ebp
shrl $3,%ebp
jz Rend
movl (%edi),%eax /* fetch destination cache line */
ALIGN (2)
Roop: movl 28(%edi),%eax /* fetch destination cache line */
movl %edx,%ebx
movl (%esi),%eax
movl 4(%esi),%edx
shrdl %cl,%eax,%ebx
shrdl %cl,%edx,%eax
movl %ebx,(%edi)
movl %eax,4(%edi)
movl 8(%esi),%ebx
movl 12(%esi),%eax
shrdl %cl,%ebx,%edx
shrdl %cl,%eax,%ebx
movl %edx,8(%edi)
movl %ebx,12(%edi)
movl 16(%esi),%edx
movl 20(%esi),%ebx
shrdl %cl,%edx,%eax
shrdl %cl,%ebx,%edx
movl %eax,16(%edi)
movl %edx,20(%edi)
movl 24(%esi),%eax
movl 28(%esi),%edx
shrdl %cl,%eax,%ebx
shrdl %cl,%edx,%eax
movl %ebx,24(%edi)
movl %eax,28(%edi)
addl $32,%esi
addl $32,%edi
decl %ebp
jnz Roop
Rend: popl %ebp
andl $7,%ebp
jz Rend2
Roop2: movl (%esi),%eax
shrdl %cl,%eax,%edx /* compute result limb */
movl %edx,(%edi)
movl %eax,%edx
addl $4,%esi
addl $4,%edi
decl %ebp
jnz Roop2
Rend2: shrl %cl,%edx /* compute most significant limb */
movl %edx,(%edi) /* store it */
popl %eax /* pop carry limb */
popl %ebp
popl %ebx
popl %esi
popl %edi
ret
/* We loop from least significant end of the arrays, which is only
permissable if the source and destination don't overlap, since the
function is documented to work for overlapping source and destination.
*/
Rspecial:
leal -4(%edi,%ebp,4),%edi
leal -4(%esi,%ebp,4),%esi
movl (%esi),%edx
subl $4,%esi
decl %ebp
pushl %ebp
shrl $3,%ebp
shrl $1,%edx
incl %ebp
decl %ebp
jz RLend
movl (%edi),%eax /* fetch destination cache line */
ALIGN (2)
RLoop: movl -28(%edi),%eax /* fetch destination cache line */
movl %edx,%ebx
movl (%esi),%eax
movl -4(%esi),%edx
rcrl $1,%eax
movl %ebx,(%edi)
rcrl $1,%edx
movl %eax,-4(%edi)
movl -8(%esi),%ebx
movl -12(%esi),%eax
rcrl $1,%ebx
movl %edx,-8(%edi)
rcrl $1,%eax
movl %ebx,-12(%edi)
movl -16(%esi),%edx
movl -20(%esi),%ebx
rcrl $1,%edx
movl %eax,-16(%edi)
rcrl $1,%ebx
movl %edx,-20(%edi)
movl -24(%esi),%eax
movl -28(%esi),%edx
rcrl $1,%eax
movl %ebx,-24(%edi)
rcrl $1,%edx
movl %eax,-28(%edi)
leal -32(%esi),%esi /* use leal not to clobber carry */
leal -32(%edi),%edi
decl %ebp
jnz RLoop
RLend: popl %ebp
sbbl %eax,%eax /* save carry in %eax */
andl $7,%ebp
jz RLend2
addl %eax,%eax /* restore carry from eax */
RLoop2: movl %edx,%ebx
movl (%esi),%edx
rcrl $1,%edx
movl %ebx,(%edi)
leal -4(%esi),%esi /* use leal not to clobber carry */
leal -4(%edi),%edi
decl %ebp
jnz RLoop2
jmp RL1
RLend2: addl %eax,%eax /* restore carry from eax */
RL1: movl %edx,(%edi) /* store last limb */
movl $0,%eax
rcrl $1,%eax
popl %ebp
popl %ebx
popl %esi
popl %edi
ret
|
a1ive/grub
| 2,683
|
grub-core/lib/libgcrypt/mpi/i586/mpih-mul3.S
|
/* i80586 submul_1 -- Multiply a limb vector with a limb and add
* the result to a second limb vector.
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_submul_1( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_size_t s1_size, (sp + 12)
* mpi_limb_t s2_limb) (sp + 16)
*/
#define res_ptr edi
#define s1_ptr esi
#define size ecx
#define s2_limb ebp
TEXT
ALIGN (3)
GLOBL C_SYMBOL_NAME(_gcry_mpih_submul_1)
C_SYMBOL_NAME(_gcry_mpih_submul_1:)
INSN1(push,l ,R(edi))
INSN1(push,l ,R(esi))
INSN1(push,l ,R(ebx))
INSN1(push,l ,R(ebp))
INSN2(mov,l ,R(res_ptr),MEM_DISP(esp,20))
INSN2(mov,l ,R(s1_ptr),MEM_DISP(esp,24))
INSN2(mov,l ,R(size),MEM_DISP(esp,28))
INSN2(mov,l ,R(s2_limb),MEM_DISP(esp,32))
INSN2(lea,l ,R(res_ptr),MEM_INDEX(res_ptr,size,4))
INSN2(lea,l ,R(s1_ptr),MEM_INDEX(s1_ptr,size,4))
INSN1(neg,l ,R(size))
INSN2(xor,l ,R(ebx),R(ebx))
ALIGN (3)
Loop: INSN2(adc,l ,R(ebx),$0)
INSN2(mov,l ,R(eax),MEM_INDEX(s1_ptr,size,4))
INSN1(mul,l ,R(s2_limb))
INSN2(add,l ,R(eax),R(ebx))
INSN2(mov,l ,R(ebx),MEM_INDEX(res_ptr,size,4))
INSN2(adc,l ,R(edx),$0)
INSN2(sub,l ,R(ebx),R(eax))
INSN2(mov,l ,MEM_INDEX(res_ptr,size,4),R(ebx))
INSN1(inc,l ,R(size))
INSN2(mov,l ,R(ebx),R(edx))
INSN1(jnz, ,Loop)
INSN2(adc,l ,R(ebx),$0)
INSN2(mov,l ,R(eax),R(ebx))
INSN1(pop,l ,R(ebp))
INSN1(pop,l ,R(ebx))
INSN1(pop,l ,R(esi))
INSN1(pop,l ,R(edi))
ret
|
a1ive/grub
| 2,820
|
grub-core/lib/libgcrypt/mpi/i586/mpih-add1.S
|
/* i80586 add_n -- Add two limb vectors of the same length > 0 and store
* sum in a third limb vector.
*
* Copyright (C) 1992, 1994, 1995, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_add_n( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_ptr_t s2_ptr, (sp + 12)
* mpi_size_t size) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_add_n)
C_SYMBOL_NAME(_gcry_mpih_add_n:)
pushl %edi
pushl %esi
pushl %ebx
pushl %ebp
movl 20(%esp),%edi /* res_ptr */
movl 24(%esp),%esi /* s1_ptr */
movl 28(%esp),%ebp /* s2_ptr */
movl 32(%esp),%ecx /* size */
movl (%ebp),%ebx
decl %ecx
movl %ecx,%edx
shrl $3,%ecx
andl $7,%edx
testl %ecx,%ecx /* zero carry flag */
jz Lend
pushl %edx
ALIGN (3)
Loop: movl 28(%edi),%eax /* fetch destination cache line */
leal 32(%edi),%edi
L1: movl (%esi),%eax
movl 4(%esi),%edx
adcl %ebx,%eax
movl 4(%ebp),%ebx
adcl %ebx,%edx
movl 8(%ebp),%ebx
movl %eax,-32(%edi)
movl %edx,-28(%edi)
L2: movl 8(%esi),%eax
movl 12(%esi),%edx
adcl %ebx,%eax
movl 12(%ebp),%ebx
adcl %ebx,%edx
movl 16(%ebp),%ebx
movl %eax,-24(%edi)
movl %edx,-20(%edi)
L3: movl 16(%esi),%eax
movl 20(%esi),%edx
adcl %ebx,%eax
movl 20(%ebp),%ebx
adcl %ebx,%edx
movl 24(%ebp),%ebx
movl %eax,-16(%edi)
movl %edx,-12(%edi)
L4: movl 24(%esi),%eax
movl 28(%esi),%edx
adcl %ebx,%eax
movl 28(%ebp),%ebx
adcl %ebx,%edx
movl 32(%ebp),%ebx
movl %eax,-8(%edi)
movl %edx,-4(%edi)
leal 32(%esi),%esi
leal 32(%ebp),%ebp
decl %ecx
jnz Loop
popl %edx
Lend:
decl %edx /* test %edx w/o clobbering carry */
js Lend2
incl %edx
Loop2:
leal 4(%edi),%edi
movl (%esi),%eax
adcl %ebx,%eax
movl 4(%ebp),%ebx
movl %eax,-4(%edi)
leal 4(%esi),%esi
leal 4(%ebp),%ebp
decl %edx
jnz Loop2
Lend2:
movl (%esi),%eax
adcl %ebx,%eax
movl %eax,(%edi)
sbbl %eax,%eax
negl %eax
popl %ebp
popl %ebx
popl %esi
popl %edi
ret
|
a1ive/grub
| 3,126
|
grub-core/lib/libgcrypt/mpi/i586/mpih-sub1.S
|
/* i80586 sub_n -- Sub two limb vectors of the same length > 0 and store
* sum in a third limb vector.
*
* Copyright (C) 1992, 1994, 1995, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_sub_n( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_ptr_t s2_ptr, (sp + 12)
* mpi_size_t size) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_sub_n)
C_SYMBOL_NAME(_gcry_mpih_sub_n:)
pushl %edi
pushl %esi
pushl %ebx
pushl %ebp
movl 20(%esp),%edi /* res_ptr */
movl 24(%esp),%esi /* s1_ptr */
movl 28(%esp),%ebp /* s2_ptr */
movl 32(%esp),%ecx /* size */
movl (%ebp),%ebx
decl %ecx
movl %ecx,%edx
shrl $3,%ecx
andl $7,%edx
testl %ecx,%ecx /* zero carry flag */
jz Lend
pushl %edx
ALIGN (3)
Loop: movl 28(%edi),%eax /* fetch destination cache line */
leal 32(%edi),%edi
L1: movl (%esi),%eax
movl 4(%esi),%edx
sbbl %ebx,%eax
movl 4(%ebp),%ebx
sbbl %ebx,%edx
movl 8(%ebp),%ebx
movl %eax,-32(%edi)
movl %edx,-28(%edi)
L2: movl 8(%esi),%eax
movl 12(%esi),%edx
sbbl %ebx,%eax
movl 12(%ebp),%ebx
sbbl %ebx,%edx
movl 16(%ebp),%ebx
movl %eax,-24(%edi)
movl %edx,-20(%edi)
L3: movl 16(%esi),%eax
movl 20(%esi),%edx
sbbl %ebx,%eax
movl 20(%ebp),%ebx
sbbl %ebx,%edx
movl 24(%ebp),%ebx
movl %eax,-16(%edi)
movl %edx,-12(%edi)
L4: movl 24(%esi),%eax
movl 28(%esi),%edx
sbbl %ebx,%eax
movl 28(%ebp),%ebx
sbbl %ebx,%edx
movl 32(%ebp),%ebx
movl %eax,-8(%edi)
movl %edx,-4(%edi)
leal 32(%esi),%esi
leal 32(%ebp),%ebp
decl %ecx
jnz Loop
popl %edx
Lend:
decl %edx /* test %edx w/o clobbering carry */
js Lend2
incl %edx
Loop2:
leal 4(%edi),%edi
movl (%esi),%eax
sbbl %ebx,%eax
movl 4(%ebp),%ebx
movl %eax,-4(%edi)
leal 4(%esi),%esi
leal 4(%ebp),%ebp
decl %edx
jnz Loop2
Lend2:
movl (%esi),%eax
sbbl %ebx,%eax
movl %eax,(%edi)
sbbl %eax,%eax
negl %eax
popl %ebp
popl %ebx
popl %esi
popl %edi
ret
|
a1ive/grub
| 4,214
|
grub-core/lib/libgcrypt/mpi/m68k/mpih-lshift.S
|
/* mc68020 lshift -- Shift left a low-level natural-number integer.
*
* Copyright (C) 1996, 1998, 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_lshift( mpi_ptr_t wp, (sp + 4)
* mpi_ptr_t up, (sp + 8)
* mpi_size_t usize, (sp + 12)
* unsigned cnt) (sp + 16)
*/
#define res_ptr a1
#define s_ptr a0
#define s_size d6
#define cnt d4
TEXT
ALIGN
GLOBL C_SYMBOL_NAME(_gcry_mpih_lshift)
C_SYMBOL_NAME(_gcry_mpih_lshift:)
PROLOG(_gcry_mpih_lshift)
/* Save used registers on the stack. */
moveml R(d2)-R(d6)/R(a2),MEM_PREDEC(sp)
/* Copy the arguments to registers. */
movel MEM_DISP(sp,28),R(res_ptr)
movel MEM_DISP(sp,32),R(s_ptr)
movel MEM_DISP(sp,36),R(s_size)
movel MEM_DISP(sp,40),R(cnt)
moveql #1,R(d5)
cmpl R(d5),R(cnt)
bne L(Lnormal)
cmpl R(s_ptr),R(res_ptr)
bls L(Lspecial) /* jump if s_ptr >= res_ptr */
#if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
lea MEM_INDX1(s_ptr,s_size,l,4),R(a2)
#else /* not mc68020 */
movel R(s_size),R(d0)
asll #2,R(d0)
lea MEM_INDX(s_ptr,d0,l),R(a2)
#endif
cmpl R(res_ptr),R(a2)
bls L(Lspecial) /* jump if res_ptr >= s_ptr + s_size */
L(Lnormal:)
moveql #32,R(d5)
subl R(cnt),R(d5)
#if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
lea MEM_INDX1(s_ptr,s_size,l,4),R(s_ptr)
lea MEM_INDX1(res_ptr,s_size,l,4),R(res_ptr)
#else /* not mc68000 */
movel R(s_size),R(d0)
asll #2,R(d0)
addl R(s_size),R(s_ptr)
addl R(s_size),R(res_ptr)
#endif
movel MEM_PREDEC(s_ptr),R(d2)
movel R(d2),R(d0)
lsrl R(d5),R(d0) /* compute carry limb */
lsll R(cnt),R(d2)
movel R(d2),R(d1)
subql #1,R(s_size)
beq L(Lend)
lsrl #1,R(s_size)
bcs L(L1)
subql #1,R(s_size)
L(Loop:)
movel MEM_PREDEC(s_ptr),R(d2)
movel R(d2),R(d3)
lsrl R(d5),R(d3)
orl R(d3),R(d1)
movel R(d1),MEM_PREDEC(res_ptr)
lsll R(cnt),R(d2)
L(L1:)
movel MEM_PREDEC(s_ptr),R(d1)
movel R(d1),R(d3)
lsrl R(d5),R(d3)
orl R(d3),R(d2)
movel R(d2),MEM_PREDEC(res_ptr)
lsll R(cnt),R(d1)
dbf R(s_size),L(Loop)
subl #0x10000,R(s_size)
bcc L(Loop)
L(Lend:)
movel R(d1),MEM_PREDEC(res_ptr) /* store least significant limb */
/* Restore used registers from stack frame. */
moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
rts
/* We loop from least significant end of the arrays, which is only
permissable if the source and destination don't overlap, since the
function is documented to work for overlapping source and destination. */
L(Lspecial:)
clrl R(d0) /* initialize carry */
eorw #1,R(s_size)
lsrl #1,R(s_size)
bcc L(LL1)
subql #1,R(s_size)
L(LLoop:)
movel MEM_POSTINC(s_ptr),R(d2)
addxl R(d2),R(d2)
movel R(d2),MEM_POSTINC(res_ptr)
L(LL1:)
movel MEM_POSTINC(s_ptr),R(d2)
addxl R(d2),R(d2)
movel R(d2),MEM_POSTINC(res_ptr)
dbf R(s_size),L(LLoop)
addxl R(d0),R(d0) /* save cy in lsb */
subl #0x10000,R(s_size)
bcs L(LLend)
lsrl #1,R(d0) /* restore cy */
bra L(LLoop)
L(LLend:)
/* Restore used registers from stack frame. */
moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
rts
EPILOG(_gcry_mpih_lshift)
|
a1ive/grub
| 4,201
|
grub-core/lib/libgcrypt/mpi/m68k/mpih-rshift.S
|
/* mc68020 rshift -- Shift right a low-level natural-number integer.
*
* Copyright (C) 1996, 1998, 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_rshift( mpi_ptr_t wp, (sp + 4)
* mpi_ptr_t up, (sp + 8)
* mpi_size_t usize, (sp + 12)
* unsigned cnt) (sp + 16)
*/
#define res_ptr a1
#define s_ptr a0
#define s_size d6
#define cnt d4
TEXT
ALIGN
GLOBL C_SYMBOL_NAME(_gcry_mpih_rshift)
C_SYMBOL_NAME(_gcry_mpih_rshift:)
PROLOG(_gcry_mpih_rshift)
/* Save used registers on the stack. */
moveml R(d2)-R(d6)/R(a2),MEM_PREDEC(sp)
/* Copy the arguments to registers. */
movel MEM_DISP(sp,28),R(res_ptr)
movel MEM_DISP(sp,32),R(s_ptr)
movel MEM_DISP(sp,36),R(s_size)
movel MEM_DISP(sp,40),R(cnt)
moveql #1,R(d5)
cmpl R(d5),R(cnt)
bne L(Rnormal)
cmpl R(res_ptr),R(s_ptr)
bls L(Rspecial) /* jump if res_ptr >= s_ptr */
#if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
lea MEM_INDX1(res_ptr,s_size,l,4),R(a2)
#else /* not mc68020 */
movel R(s_size),R(d0)
asll #2,R(d0)
lea MEM_INDX(res_ptr,d0,l),R(a2)
#endif
cmpl R(s_ptr),R(a2)
bls L(Rspecial) /* jump if s_ptr >= res_ptr + s_size */
L(Rnormal:)
moveql #32,R(d5)
subl R(cnt),R(d5)
movel MEM_POSTINC(s_ptr),R(d2)
movel R(d2),R(d0)
lsll R(d5),R(d0) /* compute carry limb */
lsrl R(cnt),R(d2)
movel R(d2),R(d1)
subql #1,R(s_size)
beq L(Rend)
lsrl #1,R(s_size)
bcs L(R1)
subql #1,R(s_size)
L(Roop:)
movel MEM_POSTINC(s_ptr),R(d2)
movel R(d2),R(d3)
lsll R(d5),R(d3)
orl R(d3),R(d1)
movel R(d1),MEM_POSTINC(res_ptr)
lsrl R(cnt),R(d2)
L(R1:)
movel MEM_POSTINC(s_ptr),R(d1)
movel R(d1),R(d3)
lsll R(d5),R(d3)
orl R(d3),R(d2)
movel R(d2),MEM_POSTINC(res_ptr)
lsrl R(cnt),R(d1)
dbf R(s_size),L(Roop)
subl #0x10000,R(s_size)
bcc L(Roop)
L(Rend:)
movel R(d1),MEM(res_ptr) /* store most significant limb */
/* Restore used registers from stack frame. */
moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
rts
/* We loop from most significant end of the arrays, which is only
permissable if the source and destination don't overlap, since the
function is documented to work for overlapping source and destination. */
L(Rspecial:)
#if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
lea MEM_INDX1(s_ptr,s_size,l,4),R(s_ptr)
lea MEM_INDX1(res_ptr,s_size,l,4),R(res_ptr)
#else /* not mc68000 */
movel R(s_size),R(d0)
asll #2,R(d0)
addl R(s_size),R(s_ptr)
addl R(s_size),R(res_ptr)
#endif
clrl R(d0) /* initialize carry */
eorw #1,R(s_size)
lsrl #1,R(s_size)
bcc L(LR1)
subql #1,R(s_size)
L(LRoop:)
movel MEM_PREDEC(s_ptr),R(d2)
roxrl #1,R(d2)
movel R(d2),MEM_PREDEC(res_ptr)
L(LR1:)
movel MEM_PREDEC(s_ptr),R(d2)
roxrl #1,R(d2)
movel R(d2),MEM_PREDEC(res_ptr)
dbf R(s_size),L(LRoop)
roxrl #1,R(d0) /* save cy in msb */
subl #0x10000,R(s_size)
bcs L(LRend)
addl R(d0),R(d0) /* restore cy */
bra L(LRoop)
L(LRend:)
/* Restore used registers from stack frame. */
moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
rts
EPILOG(_gcry_mpih_rshift)
|
a1ive/grub
| 2,643
|
grub-core/lib/libgcrypt/mpi/m68k/mpih-add1.S
|
/* mc68020 __mpn_add_n -- Add two limb vectors of the same length > 0 and store
* sum in a third limb vector.
*
* Copyright (C) 1992, 1994,1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_add_n( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_ptr_t s2_ptr, (sp + 16)
* mpi_size_t size) (sp + 12)
*/
TEXT
ALIGN
GLOBL C_SYMBOL_NAME(_gcry_mpih_add_n)
C_SYMBOL_NAME(_gcry_mpih_add_n:)
PROLOG(_gcry_mpih_add_n)
/* Save used registers on the stack. */
movel R(d2),MEM_PREDEC(sp)
movel R(a2),MEM_PREDEC(sp)
/* Copy the arguments to registers. Better use movem? */
movel MEM_DISP(sp,12),R(a2)
movel MEM_DISP(sp,16),R(a0)
movel MEM_DISP(sp,20),R(a1)
movel MEM_DISP(sp,24),R(d2)
eorw #1,R(d2)
lsrl #1,R(d2)
bcc L(L1)
subql #1,R(d2) /* clears cy as side effect */
L(Loop:)
movel MEM_POSTINC(a0),R(d0)
movel MEM_POSTINC(a1),R(d1)
addxl R(d1),R(d0)
movel R(d0),MEM_POSTINC(a2)
L(L1:) movel MEM_POSTINC(a0),R(d0)
movel MEM_POSTINC(a1),R(d1)
addxl R(d1),R(d0)
movel R(d0),MEM_POSTINC(a2)
dbf R(d2),L(Loop) /* loop until 16 lsb of %4 == -1 */
subxl R(d0),R(d0) /* d0 <= -cy; save cy as 0 or -1 in d0 */
subl #0x10000,R(d2)
bcs L(L2)
addl R(d0),R(d0) /* restore cy */
bra L(Loop)
L(L2:)
negl R(d0)
/* Restore used registers from stack frame. */
movel MEM_POSTINC(sp),R(a2)
movel MEM_POSTINC(sp),R(d2)
rts
EPILOG(_gcry_mpih_add_n)
|
a1ive/grub
| 2,652
|
grub-core/lib/libgcrypt/mpi/m68k/mpih-sub1.S
|
/* mc68020 __mpn_sub_n -- Subtract two limb vectors of the same length > 0 and
* store difference in a third limb vector.
*
* Copyright (C) 1992, 1994, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_sub_n( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_ptr_t s2_ptr, (sp + 16)
* mpi_size_t size) (sp + 12)
*/
TEXT
ALIGN
GLOBL C_SYMBOL_NAME(_gcry_mpih_sub_n)
C_SYMBOL_NAME(_gcry_mpih_sub_n:)
PROLOG(_gcry_mpih_sub_n)
/* Save used registers on the stack. */
movel R(d2),MEM_PREDEC(sp)
movel R(a2),MEM_PREDEC(sp)
/* Copy the arguments to registers. Better use movem? */
movel MEM_DISP(sp,12),R(a2)
movel MEM_DISP(sp,16),R(a0)
movel MEM_DISP(sp,20),R(a1)
movel MEM_DISP(sp,24),R(d2)
eorw #1,R(d2)
lsrl #1,R(d2)
bcc L(L1)
subql #1,R(d2) /* clears cy as side effect */
L(Loop:)
movel MEM_POSTINC(a0),R(d0)
movel MEM_POSTINC(a1),R(d1)
subxl R(d1),R(d0)
movel R(d0),MEM_POSTINC(a2)
L(L1:) movel MEM_POSTINC(a0),R(d0)
movel MEM_POSTINC(a1),R(d1)
subxl R(d1),R(d0)
movel R(d0),MEM_POSTINC(a2)
dbf R(d2),L(Loop) /* loop until 16 lsb of %4 == -1 */
subxl R(d0),R(d0) /* d0 <= -cy; save cy as 0 or -1 in d0 */
subl #0x10000,R(d2)
bcs L(L2)
addl R(d0),R(d0) /* restore cy */
bra L(Loop)
L(L2:)
negl R(d0)
/* Restore used registers from stack frame. */
movel MEM_POSTINC(sp),R(a2)
movel MEM_POSTINC(sp),R(d2)
rts
EPILOG(_gcry_mpih_sub_n)
|
a1ive/grub
| 2,509
|
grub-core/lib/libgcrypt/mpi/i386/mpih-mul1.S
|
/* i80386 mul_1 -- Multiply a limb vector with a limb and store
* the result in a second limb vector.
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_mul_1( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_size_t s1_size, (sp + 12)
* mpi_limb_t s2_limb) (sp + 16)
*/
#define res_ptr edi
#define s1_ptr esi
#define size ecx
#define s2_limb ebp
TEXT
ALIGN (3)
GLOBL C_SYMBOL_NAME(_gcry_mpih_mul_1)
C_SYMBOL_NAME(_gcry_mpih_mul_1:)
INSN1(push,l ,R(edi))
INSN1(push,l ,R(esi))
INSN1(push,l ,R(ebx))
INSN1(push,l ,R(ebp))
INSN2(mov,l ,R(res_ptr),MEM_DISP(esp,20))
INSN2(mov,l ,R(s1_ptr),MEM_DISP(esp,24))
INSN2(mov,l ,R(size),MEM_DISP(esp,28))
INSN2(mov,l ,R(s2_limb),MEM_DISP(esp,32))
INSN2(lea,l ,R(res_ptr),MEM_INDEX(res_ptr,size,4))
INSN2(lea,l ,R(s1_ptr),MEM_INDEX(s1_ptr,size,4))
INSN1(neg,l ,R(size))
INSN2(xor,l ,R(ebx),R(ebx))
ALIGN (3)
Loop:
INSN2(mov,l ,R(eax),MEM_INDEX(s1_ptr,size,4))
INSN1(mul,l ,R(s2_limb))
INSN2(add,l ,R(eax),R(ebx))
INSN2(mov,l ,MEM_INDEX(res_ptr,size,4),R(eax))
INSN2(adc,l ,R(edx),$0)
INSN2(mov,l ,R(ebx),R(edx))
INSN1(inc,l ,R(size))
INSN1(jnz, ,Loop)
INSN2(mov,l ,R(eax),R(ebx))
INSN1(pop,l ,R(ebp))
INSN1(pop,l ,R(ebx))
INSN1(pop,l ,R(esi))
INSN1(pop,l ,R(edi))
ret
|
a1ive/grub
| 2,577
|
grub-core/lib/libgcrypt/mpi/i386/mpih-mul2.S
|
/* i80386 addmul_1 -- Multiply a limb vector with a limb and add
* the result to a second limb vector.
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_addmul_1( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_size_t s1_size, (sp + 12)
* mpi_limb_t s2_limb) (sp + 16)
*/
#define res_ptr edi
#define s1_ptr esi
#define size ecx
#define s2_limb ebp
TEXT
ALIGN (3)
GLOBL C_SYMBOL_NAME(_gcry_mpih_addmul_1)
C_SYMBOL_NAME(_gcry_mpih_addmul_1:)
INSN1(push,l ,R(edi))
INSN1(push,l ,R(esi))
INSN1(push,l ,R(ebx))
INSN1(push,l ,R(ebp))
INSN2(mov,l ,R(res_ptr),MEM_DISP(esp,20))
INSN2(mov,l ,R(s1_ptr),MEM_DISP(esp,24))
INSN2(mov,l ,R(size),MEM_DISP(esp,28))
INSN2(mov,l ,R(s2_limb),MEM_DISP(esp,32))
INSN2(lea,l ,R(res_ptr),MEM_INDEX(res_ptr,size,4))
INSN2(lea,l ,R(s1_ptr),MEM_INDEX(s1_ptr,size,4))
INSN1(neg,l ,R(size))
INSN2(xor,l ,R(ebx),R(ebx))
ALIGN (3)
Loop:
INSN2(mov,l ,R(eax),MEM_INDEX(s1_ptr,size,4))
INSN1(mul,l ,R(s2_limb))
INSN2(add,l ,R(eax),R(ebx))
INSN2(adc,l ,R(edx),$0)
INSN2(add,l ,MEM_INDEX(res_ptr,size,4),R(eax))
INSN2(adc,l ,R(edx),$0)
INSN2(mov,l ,R(ebx),R(edx))
INSN1(inc,l ,R(size))
INSN1(jnz, ,Loop)
INSN2(mov,l ,R(eax),R(ebx))
INSN1(pop,l ,R(ebp))
INSN1(pop,l ,R(ebx))
INSN1(pop,l ,R(esi))
INSN1(pop,l ,R(edi))
ret
|
a1ive/grub
| 2,551
|
grub-core/lib/libgcrypt/mpi/i386/mpih-lshift.S
|
/* i80386 lshift
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_lshift( mpi_ptr_t wp, (sp + 4)
* mpi_ptr_t up, (sp + 8)
* mpi_size_t usize, (sp + 12)
* unsigned cnt) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_lshift)
C_SYMBOL_NAME(_gcry_mpih_lshift:)
pushl %edi
pushl %esi
pushl %ebx
movl 16(%esp),%edi /* res_ptr */
movl 20(%esp),%esi /* s_ptr */
movl 24(%esp),%edx /* size */
movl 28(%esp),%ecx /* cnt */
subl $4,%esi /* adjust s_ptr */
movl (%esi,%edx,4),%ebx /* read most significant limb */
xorl %eax,%eax
shldl %cl,%ebx,%eax /* compute carry limb */
decl %edx
jz Lend
pushl %eax /* push carry limb onto stack */
testb $1,%dl
jnz L1 /* enter loop in the middle */
movl %ebx,%eax
ALIGN (3)
Loop: movl (%esi,%edx,4),%ebx /* load next lower limb */
shldl %cl,%ebx,%eax /* compute result limb */
movl %eax,(%edi,%edx,4) /* store it */
decl %edx
L1: movl (%esi,%edx,4),%eax
shldl %cl,%eax,%ebx
movl %ebx,(%edi,%edx,4)
decl %edx
jnz Loop
shll %cl,%eax /* compute least significant limb */
movl %eax,(%edi) /* store it */
popl %eax /* pop carry limb */
popl %ebx
popl %esi
popl %edi
ret
Lend: shll %cl,%ebx /* compute least significant limb */
movl %ebx,(%edi) /* store it */
popl %ebx
popl %esi
popl %edi
ret
|
a1ive/grub
| 2,583
|
grub-core/lib/libgcrypt/mpi/i386/mpih-rshift.S
|
/* i80386 rshift
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_rshift( mpi_ptr_t wp, (sp + 4)
* mpi_ptr_t up, (sp + 8)
* mpi_size_t usize, (sp + 12)
* unsigned cnt) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_rshift)
C_SYMBOL_NAME(_gcry_mpih_rshift:)
pushl %edi
pushl %esi
pushl %ebx
movl 16(%esp),%edi /* wp */
movl 20(%esp),%esi /* up */
movl 24(%esp),%edx /* usize */
movl 28(%esp),%ecx /* cnt */
leal -4(%edi,%edx,4),%edi
leal (%esi,%edx,4),%esi
negl %edx
movl (%esi,%edx,4),%ebx /* read least significant limb */
xorl %eax,%eax
shrdl %cl,%ebx,%eax /* compute carry limb */
incl %edx
jz Lend2
pushl %eax /* push carry limb onto stack */
testb $1,%dl
jnz L2 /* enter loop in the middle */
movl %ebx,%eax
ALIGN (3)
Loop2: movl (%esi,%edx,4),%ebx /* load next higher limb */
shrdl %cl,%ebx,%eax /* compute result limb */
movl %eax,(%edi,%edx,4) /* store it */
incl %edx
L2: movl (%esi,%edx,4),%eax
shrdl %cl,%eax,%ebx
movl %ebx,(%edi,%edx,4)
incl %edx
jnz Loop2
shrl %cl,%eax /* compute most significant limb */
movl %eax,(%edi) /* store it */
popl %eax /* pop carry limb */
popl %ebx
popl %esi
popl %edi
ret
Lend2: shrl %cl,%ebx /* compute most significant limb */
movl %ebx,(%edi) /* store it */
popl %ebx
popl %esi
popl %edi
ret
|
a1ive/grub
| 2,578
|
grub-core/lib/libgcrypt/mpi/i386/mpih-mul3.S
|
/* i80386 submul_1 -- Multiply a limb vector with a limb and add
* the result to a second limb vector.
*
* Copyright (C) 1992, 1994, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_submul_1( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_size_t s1_size, (sp + 12)
* mpi_limb_t s2_limb) (sp + 16)
*/
#define res_ptr edi
#define s1_ptr esi
#define size ecx
#define s2_limb ebp
TEXT
ALIGN (3)
GLOBL C_SYMBOL_NAME(_gcry_mpih_submul_1)
C_SYMBOL_NAME(_gcry_mpih_submul_1:)
INSN1(push,l ,R(edi))
INSN1(push,l ,R(esi))
INSN1(push,l ,R(ebx))
INSN1(push,l ,R(ebp))
INSN2(mov,l ,R(res_ptr),MEM_DISP(esp,20))
INSN2(mov,l ,R(s1_ptr),MEM_DISP(esp,24))
INSN2(mov,l ,R(size),MEM_DISP(esp,28))
INSN2(mov,l ,R(s2_limb),MEM_DISP(esp,32))
INSN2(lea,l ,R(res_ptr),MEM_INDEX(res_ptr,size,4))
INSN2(lea,l ,R(s1_ptr),MEM_INDEX(s1_ptr,size,4))
INSN1(neg,l ,R(size))
INSN2(xor,l ,R(ebx),R(ebx))
ALIGN (3)
Loop:
INSN2(mov,l ,R(eax),MEM_INDEX(s1_ptr,size,4))
INSN1(mul,l ,R(s2_limb))
INSN2(add,l ,R(eax),R(ebx))
INSN2(adc,l ,R(edx),$0)
INSN2(sub,l ,MEM_INDEX(res_ptr,size,4),R(eax))
INSN2(adc,l ,R(edx),$0)
INSN2(mov,l ,R(ebx),R(edx))
INSN1(inc,l ,R(size))
INSN1(jnz, ,Loop)
INSN2(mov,l ,R(eax),R(ebx))
INSN1(pop,l ,R(ebp))
INSN1(pop,l ,R(ebx))
INSN1(pop,l ,R(esi))
INSN1(pop,l ,R(edi))
ret
|
a1ive/grub
| 3,246
|
grub-core/lib/libgcrypt/mpi/i386/mpih-add1.S
|
/* i80386 add_n -- Add two limb vectors of the same length > 0 and store
* sum in a third limb vector.
*
* Copyright (C) 1992, 1994, 1995, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_add_n( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_ptr_t s2_ptr, (sp + 12)
* mpi_size_t size) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_add_n)
C_SYMBOL_NAME(_gcry_mpih_add_n:)
pushl %edi
pushl %esi
movl 12(%esp),%edi /* res_ptr */
movl 16(%esp),%esi /* s1_ptr */
movl 20(%esp),%edx /* s2_ptr */
movl 24(%esp),%ecx /* size */
movl %ecx,%eax
shrl $3,%ecx /* compute count for unrolled loop */
negl %eax
andl $7,%eax /* get index where to start loop */
jz Loop /* necessary special case for 0 */
incl %ecx /* adjust loop count */
shll $2,%eax /* adjustment for pointers... */
subl %eax,%edi /* ... since they are offset ... */
subl %eax,%esi /* ... by a constant when we ... */
subl %eax,%edx /* ... enter the loop */
shrl $2,%eax /* restore previous value */
#ifdef PIC
/* Calculate start address in loop for PIC. Due to limitations in some
assemblers, Loop-L0-3 cannot be put into the leal */
call L0
L0: leal (%eax,%eax,8),%eax
addl (%esp),%eax
addl $(Loop-L0-3),%eax
addl $4,%esp
#else
/* Calculate start address in loop for non-PIC. */
leal (Loop - 3)(%eax,%eax,8),%eax
#endif
jmp *%eax /* jump into loop */
ALIGN (3)
Loop: movl (%esi),%eax
adcl (%edx),%eax
movl %eax,(%edi)
movl 4(%esi),%eax
adcl 4(%edx),%eax
movl %eax,4(%edi)
movl 8(%esi),%eax
adcl 8(%edx),%eax
movl %eax,8(%edi)
movl 12(%esi),%eax
adcl 12(%edx),%eax
movl %eax,12(%edi)
movl 16(%esi),%eax
adcl 16(%edx),%eax
movl %eax,16(%edi)
movl 20(%esi),%eax
adcl 20(%edx),%eax
movl %eax,20(%edi)
movl 24(%esi),%eax
adcl 24(%edx),%eax
movl %eax,24(%edi)
movl 28(%esi),%eax
adcl 28(%edx),%eax
movl %eax,28(%edi)
leal 32(%edi),%edi
leal 32(%esi),%esi
leal 32(%edx),%edx
decl %ecx
jnz Loop
sbbl %eax,%eax
negl %eax
popl %esi
popl %edi
ret
|
a1ive/grub
| 3,247
|
grub-core/lib/libgcrypt/mpi/i386/mpih-sub1.S
|
/* i80386 sub_n -- Sub two limb vectors of the same length > 0 and store
* sum in a third limb vector.
*
* Copyright (C) 1992, 1994, 1995, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*******************
* mpi_limb_t
* _gcry_mpih_sub_n( mpi_ptr_t res_ptr, (sp + 4)
* mpi_ptr_t s1_ptr, (sp + 8)
* mpi_ptr_t s2_ptr, (sp + 12)
* mpi_size_t size) (sp + 16)
*/
.text
ALIGN (3)
.globl C_SYMBOL_NAME(_gcry_mpih_sub_n)
C_SYMBOL_NAME(_gcry_mpih_sub_n:)
pushl %edi
pushl %esi
movl 12(%esp),%edi /* res_ptr */
movl 16(%esp),%esi /* s1_ptr */
movl 20(%esp),%edx /* s2_ptr */
movl 24(%esp),%ecx /* size */
movl %ecx,%eax
shrl $3,%ecx /* compute count for unrolled loop */
negl %eax
andl $7,%eax /* get index where to start loop */
jz Loop /* necessary special case for 0 */
incl %ecx /* adjust loop count */
shll $2,%eax /* adjustment for pointers... */
subl %eax,%edi /* ... since they are offset ... */
subl %eax,%esi /* ... by a constant when we ... */
subl %eax,%edx /* ... enter the loop */
shrl $2,%eax /* restore previous value */
#ifdef PIC
/* Calculate start address in loop for PIC. Due to limitations in some
assemblers, Loop-L0-3 cannot be put into the leal */
call L0
L0: leal (%eax,%eax,8),%eax
addl (%esp),%eax
addl $(Loop-L0-3),%eax
addl $4,%esp
#else
/* Calculate start address in loop for non-PIC. */
leal (Loop - 3)(%eax,%eax,8),%eax
#endif
jmp *%eax /* jump into loop */
ALIGN (3)
Loop: movl (%esi),%eax
sbbl (%edx),%eax
movl %eax,(%edi)
movl 4(%esi),%eax
sbbl 4(%edx),%eax
movl %eax,4(%edi)
movl 8(%esi),%eax
sbbl 8(%edx),%eax
movl %eax,8(%edi)
movl 12(%esi),%eax
sbbl 12(%edx),%eax
movl %eax,12(%edi)
movl 16(%esi),%eax
sbbl 16(%edx),%eax
movl %eax,16(%edi)
movl 20(%esi),%eax
sbbl 20(%edx),%eax
movl %eax,20(%edi)
movl 24(%esi),%eax
sbbl 24(%edx),%eax
movl %eax,24(%edi)
movl 28(%esi),%eax
sbbl 28(%edx),%eax
movl %eax,28(%edi)
leal 32(%edi),%edi
leal 32(%esi),%esi
leal 32(%edx),%edx
decl %ecx
jnz Loop
sbbl %eax,%eax
negl %eax
popl %esi
popl %edi
ret
|
a1ive/grub
| 2,152
|
grub-core/lib/libgcrypt/mpi/sparc32/mpih-lshift.S
|
/* sparc lshift
*
* Copyright (C) 1995, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
! INPUT PARAMETERS
! res_ptr %o0
! src_ptr %o1
! size %o2
! cnt %o3
#include "sysdep.h"
.text
.align 4
.global C_SYMBOL_NAME(_gcry_mpih_lshift)
C_SYMBOL_NAME(_gcry_mpih_lshift):
sll %o2,2,%g1
add %o1,%g1,%o1 ! make %o1 point at end of src
ld [%o1-4],%g2 ! load first limb
sub %g0,%o3,%o5 ! negate shift count
add %o0,%g1,%o0 ! make %o0 point at end of res
add %o2,-1,%o2
andcc %o2,4-1,%g4 ! number of limbs in first loop
srl %g2,%o5,%g1 ! compute function result
be L0 ! if multiple of 4 limbs, skip first loop
st %g1,[%sp+80]
sub %o2,%g4,%o2 ! adjust count for main loop
Loop0: ld [%o1-8],%g3
add %o0,-4,%o0
add %o1,-4,%o1
addcc %g4,-1,%g4
sll %g2,%o3,%o4
srl %g3,%o5,%g1
mov %g3,%g2
or %o4,%g1,%o4
bne Loop0
st %o4,[%o0+0]
L0: tst %o2
be Lend
nop
Loop: ld [%o1-8],%g3
add %o0,-16,%o0
addcc %o2,-4,%o2
sll %g2,%o3,%o4
srl %g3,%o5,%g1
ld [%o1-12],%g2
sll %g3,%o3,%g4
or %o4,%g1,%o4
st %o4,[%o0+12]
srl %g2,%o5,%g1
ld [%o1-16],%g3
sll %g2,%o3,%o4
or %g4,%g1,%g4
st %g4,[%o0+8]
srl %g3,%o5,%g1
ld [%o1-20],%g2
sll %g3,%o3,%g4
or %o4,%g1,%o4
st %o4,[%o0+4]
srl %g2,%o5,%g1
add %o1,-16,%o1
or %g4,%g1,%g4
bne Loop
st %g4,[%o0+0]
Lend: sll %g2,%o3,%g2
st %g2,[%o0-4]
retl
ld [%sp+80],%o0
|
a1ive/grub
| 3,960
|
grub-core/lib/libgcrypt/mpi/sparc32/udiv.S
|
/* SPARC v7 __udiv_qrnnd division support, used from longlong.h.
* This is for v7 CPUs without a floating-point unit.
*
* Copyright (C) 1993, 1994, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
! INPUT PARAMETERS
! rem_ptr o0
! n1 o1
! n0 o2
! d o3
#include "sysdep.h"
.text
.align 4
.global C_SYMBOL_NAME(__udiv_qrnnd)
C_SYMBOL_NAME(__udiv_qrnnd):
tst %o3
bneg Largedivisor
mov 8,%g1
b Lp1
addxcc %o2,%o2,%o2
Lplop: bcc Ln1
addxcc %o2,%o2,%o2
Lp1: addx %o1,%o1,%o1
subcc %o1,%o3,%o4
bcc Ln2
addxcc %o2,%o2,%o2
Lp2: addx %o1,%o1,%o1
subcc %o1,%o3,%o4
bcc Ln3
addxcc %o2,%o2,%o2
Lp3: addx %o1,%o1,%o1
subcc %o1,%o3,%o4
bcc Ln4
addxcc %o2,%o2,%o2
Lp4: addx %o1,%o1,%o1
addcc %g1,-1,%g1
bne Lplop
subcc %o1,%o3,%o4
bcc Ln5
addxcc %o2,%o2,%o2
Lp5: st %o1,[%o0]
retl
xnor %g0,%o2,%o0
Lnlop: bcc Lp1
addxcc %o2,%o2,%o2
Ln1: addx %o4,%o4,%o4
subcc %o4,%o3,%o1
bcc Lp2
addxcc %o2,%o2,%o2
Ln2: addx %o4,%o4,%o4
subcc %o4,%o3,%o1
bcc Lp3
addxcc %o2,%o2,%o2
Ln3: addx %o4,%o4,%o4
subcc %o4,%o3,%o1
bcc Lp4
addxcc %o2,%o2,%o2
Ln4: addx %o4,%o4,%o4
addcc %g1,-1,%g1
bne Lnlop
subcc %o4,%o3,%o1
bcc Lp5
addxcc %o2,%o2,%o2
Ln5: st %o4,[%o0]
retl
xnor %g0,%o2,%o0
Largedivisor:
and %o2,1,%o5 ! %o5 = n0 & 1
srl %o2,1,%o2
sll %o1,31,%g2
or %g2,%o2,%o2 ! %o2 = lo(n1n0 >> 1)
srl %o1,1,%o1 ! %o1 = hi(n1n0 >> 1)
and %o3,1,%g2
srl %o3,1,%g3 ! %g3 = floor(d / 2)
add %g3,%g2,%g3 ! %g3 = ceil(d / 2)
b LLp1
addxcc %o2,%o2,%o2
LLplop: bcc LLn1
addxcc %o2,%o2,%o2
LLp1: addx %o1,%o1,%o1
subcc %o1,%g3,%o4
bcc LLn2
addxcc %o2,%o2,%o2
LLp2: addx %o1,%o1,%o1
subcc %o1,%g3,%o4
bcc LLn3
addxcc %o2,%o2,%o2
LLp3: addx %o1,%o1,%o1
subcc %o1,%g3,%o4
bcc LLn4
addxcc %o2,%o2,%o2
LLp4: addx %o1,%o1,%o1
addcc %g1,-1,%g1
bne LLplop
subcc %o1,%g3,%o4
bcc LLn5
addxcc %o2,%o2,%o2
LLp5: add %o1,%o1,%o1 ! << 1
tst %g2
bne Oddp
add %o5,%o1,%o1
st %o1,[%o0]
retl
xnor %g0,%o2,%o0
LLnlop: bcc LLp1
addxcc %o2,%o2,%o2
LLn1: addx %o4,%o4,%o4
subcc %o4,%g3,%o1
bcc LLp2
addxcc %o2,%o2,%o2
LLn2: addx %o4,%o4,%o4
subcc %o4,%g3,%o1
bcc LLp3
addxcc %o2,%o2,%o2
LLn3: addx %o4,%o4,%o4
subcc %o4,%g3,%o1
bcc LLp4
addxcc %o2,%o2,%o2
LLn4: addx %o4,%o4,%o4
addcc %g1,-1,%g1
bne LLnlop
subcc %o4,%g3,%o1
bcc LLp5
addxcc %o2,%o2,%o2
LLn5: add %o4,%o4,%o4 ! << 1
tst %g2
bne Oddn
add %o5,%o4,%o4
st %o4,[%o0]
retl
xnor %g0,%o2,%o0
Oddp: xnor %g0,%o2,%o2
! q' in %o2. r' in %o1
addcc %o1,%o2,%o1
bcc LLp6
addx %o2,0,%o2
sub %o1,%o3,%o1
LLp6: subcc %o1,%o3,%g0
bcs LLp7
subx %o2,-1,%o2
sub %o1,%o3,%o1
LLp7: st %o1,[%o0]
retl
mov %o2,%o0
Oddn: xnor %g0,%o2,%o2
! q' in %o2. r' in %o4
addcc %o4,%o2,%o4
bcc LLn6
addx %o2,0,%o2
sub %o4,%o3,%o4
LLn6: subcc %o4,%o3,%g0
bcs LLn7
subx %o2,-1,%o2
sub %o4,%o3,%o4
LLn7: st %o4,[%o0]
retl
mov %o2,%o0
|
a1ive/grub
| 2,034
|
grub-core/lib/libgcrypt/mpi/sparc32/mpih-rshift.S
|
/* sparc rshift
*
* Copyright (C) 1995, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
! INPUT PARAMETERS
! res_ptr %o0
! src_ptr %o1
! size %o2
! cnt %o3
#include "sysdep.h"
.text
.align 4
.global C_SYMBOL_NAME(_gcry_mpih_rshift)
C_SYMBOL_NAME(_gcry_mpih_rshift):
ld [%o1],%g2 ! load first limb
sub %g0,%o3,%o5 ! negate shift count
add %o2,-1,%o2
andcc %o2,4-1,%g4 ! number of limbs in first loop
sll %g2,%o5,%g1 ! compute function result
be L0 ! if multiple of 4 limbs, skip first loop
st %g1,[%sp+80]
sub %o2,%g4,%o2 ! adjust count for main loop
Loop0: ld [%o1+4],%g3
add %o0,4,%o0
add %o1,4,%o1
addcc %g4,-1,%g4
srl %g2,%o3,%o4
sll %g3,%o5,%g1
mov %g3,%g2
or %o4,%g1,%o4
bne Loop0
st %o4,[%o0-4]
L0: tst %o2
be Lend
nop
Loop: ld [%o1+4],%g3
add %o0,16,%o0
addcc %o2,-4,%o2
srl %g2,%o3,%o4
sll %g3,%o5,%g1
ld [%o1+8],%g2
srl %g3,%o3,%g4
or %o4,%g1,%o4
st %o4,[%o0-16]
sll %g2,%o5,%g1
ld [%o1+12],%g3
srl %g2,%o3,%o4
or %g4,%g1,%g4
st %g4,[%o0-12]
sll %g3,%o5,%g1
ld [%o1+16],%g2
srl %g3,%o3,%g4
or %o4,%g1,%o4
st %o4,[%o0-8]
sll %g2,%o5,%g1
add %o1,16,%o1
or %g4,%g1,%g4
bne Loop
st %g4,[%o0-4]
Lend: srl %g2,%o3,%g2
st %g2,[%o0-0]
retl
ld [%sp+80],%o0
|
a1ive/grub
| 5,746
|
grub-core/lib/libgcrypt/mpi/sparc32/mpih-add1.S
|
/* SPARC _add_n -- Add two limb vectors of the same length > 0 and store
* sum in a third limb vector.
*
* Copyright (C) 1995, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*******************
* mpi_limb_t
* _gcry_mpih_add_n( mpi_ptr_t res_ptr,
* mpi_ptr_t s1_ptr,
* mpi_ptr_t s2_ptr,
* mpi_size_t size)
*/
! INPUT PARAMETERS
#define res_ptr %o0
#define s1_ptr %o1
#define s2_ptr %o2
#define size %o3
#include "sysdep.h"
.text
.align 4
.global C_SYMBOL_NAME(_gcry_mpih_add_n)
C_SYMBOL_NAME(_gcry_mpih_add_n):
xor s2_ptr,res_ptr,%g1
andcc %g1,4,%g0
bne L1 ! branch if alignment differs
nop
! ** V1a **
L0: andcc res_ptr,4,%g0 ! res_ptr unaligned? Side effect: cy=0
be L_v1 ! if no, branch
nop
/* Add least significant limb separately to align res_ptr and s2_ptr */
ld [s1_ptr],%g4
add s1_ptr,4,s1_ptr
ld [s2_ptr],%g2
add s2_ptr,4,s2_ptr
add size,-1,size
addcc %g4,%g2,%o4
st %o4,[res_ptr]
add res_ptr,4,res_ptr
L_v1: addx %g0,%g0,%o4 ! save cy in register
cmp size,2 ! if size < 2 ...
bl Lend2 ! ... branch to tail code
subcc %g0,%o4,%g0 ! restore cy
ld [s1_ptr+0],%g4
addcc size,-10,size
ld [s1_ptr+4],%g1
ldd [s2_ptr+0],%g2
blt Lfin1
subcc %g0,%o4,%g0 ! restore cy
/* Add blocks of 8 limbs until less than 8 limbs remain */
Loop1: addxcc %g4,%g2,%o4
ld [s1_ptr+8],%g4
addxcc %g1,%g3,%o5
ld [s1_ptr+12],%g1
ldd [s2_ptr+8],%g2
std %o4,[res_ptr+0]
addxcc %g4,%g2,%o4
ld [s1_ptr+16],%g4
addxcc %g1,%g3,%o5
ld [s1_ptr+20],%g1
ldd [s2_ptr+16],%g2
std %o4,[res_ptr+8]
addxcc %g4,%g2,%o4
ld [s1_ptr+24],%g4
addxcc %g1,%g3,%o5
ld [s1_ptr+28],%g1
ldd [s2_ptr+24],%g2
std %o4,[res_ptr+16]
addxcc %g4,%g2,%o4
ld [s1_ptr+32],%g4
addxcc %g1,%g3,%o5
ld [s1_ptr+36],%g1
ldd [s2_ptr+32],%g2
std %o4,[res_ptr+24]
addx %g0,%g0,%o4 ! save cy in register
addcc size,-8,size
add s1_ptr,32,s1_ptr
add s2_ptr,32,s2_ptr
add res_ptr,32,res_ptr
bge Loop1
subcc %g0,%o4,%g0 ! restore cy
Lfin1: addcc size,8-2,size
blt Lend1
subcc %g0,%o4,%g0 ! restore cy
/* Add blocks of 2 limbs until less than 2 limbs remain */
Loope1: addxcc %g4,%g2,%o4
ld [s1_ptr+8],%g4
addxcc %g1,%g3,%o5
ld [s1_ptr+12],%g1
ldd [s2_ptr+8],%g2
std %o4,[res_ptr+0]
addx %g0,%g0,%o4 ! save cy in register
addcc size,-2,size
add s1_ptr,8,s1_ptr
add s2_ptr,8,s2_ptr
add res_ptr,8,res_ptr
bge Loope1
subcc %g0,%o4,%g0 ! restore cy
Lend1: addxcc %g4,%g2,%o4
addxcc %g1,%g3,%o5
std %o4,[res_ptr+0]
addx %g0,%g0,%o4 ! save cy in register
andcc size,1,%g0
be Lret1
subcc %g0,%o4,%g0 ! restore cy
/* Add last limb */
ld [s1_ptr+8],%g4
ld [s2_ptr+8],%g2
addxcc %g4,%g2,%o4
st %o4,[res_ptr+8]
Lret1: retl
addx %g0,%g0,%o0 ! return carry-out from most sign. limb
L1: xor s1_ptr,res_ptr,%g1
andcc %g1,4,%g0
bne L2
nop
! ** V1b **
mov s2_ptr,%g1
mov s1_ptr,s2_ptr
b L0
mov %g1,s1_ptr
! ** V2 **
/* If we come here, the alignment of s1_ptr and res_ptr as well as the
alignment of s2_ptr and res_ptr differ. Since there are only two ways
things can be aligned (that we care about) we now know that the alignment
of s1_ptr and s2_ptr are the same. */
L2: cmp size,1
be Ljone
nop
andcc s1_ptr,4,%g0 ! s1_ptr unaligned? Side effect: cy=0
be L_v2 ! if no, branch
nop
/* Add least significant limb separately to align s1_ptr and s2_ptr */
ld [s1_ptr],%g4
add s1_ptr,4,s1_ptr
ld [s2_ptr],%g2
add s2_ptr,4,s2_ptr
add size,-1,size
addcc %g4,%g2,%o4
st %o4,[res_ptr]
add res_ptr,4,res_ptr
L_v2: addx %g0,%g0,%o4 ! save cy in register
addcc size,-8,size
blt Lfin2
subcc %g0,%o4,%g0 ! restore cy
/* Add blocks of 8 limbs until less than 8 limbs remain */
Loop2: ldd [s1_ptr+0],%g2
ldd [s2_ptr+0],%o4
addxcc %g2,%o4,%g2
st %g2,[res_ptr+0]
addxcc %g3,%o5,%g3
st %g3,[res_ptr+4]
ldd [s1_ptr+8],%g2
ldd [s2_ptr+8],%o4
addxcc %g2,%o4,%g2
st %g2,[res_ptr+8]
addxcc %g3,%o5,%g3
st %g3,[res_ptr+12]
ldd [s1_ptr+16],%g2
ldd [s2_ptr+16],%o4
addxcc %g2,%o4,%g2
st %g2,[res_ptr+16]
addxcc %g3,%o5,%g3
st %g3,[res_ptr+20]
ldd [s1_ptr+24],%g2
ldd [s2_ptr+24],%o4
addxcc %g2,%o4,%g2
st %g2,[res_ptr+24]
addxcc %g3,%o5,%g3
st %g3,[res_ptr+28]
addx %g0,%g0,%o4 ! save cy in register
addcc size,-8,size
add s1_ptr,32,s1_ptr
add s2_ptr,32,s2_ptr
add res_ptr,32,res_ptr
bge Loop2
subcc %g0,%o4,%g0 ! restore cy
Lfin2: addcc size,8-2,size
blt Lend2
subcc %g0,%o4,%g0 ! restore cy
Loope2: ldd [s1_ptr+0],%g2
ldd [s2_ptr+0],%o4
addxcc %g2,%o4,%g2
st %g2,[res_ptr+0]
addxcc %g3,%o5,%g3
st %g3,[res_ptr+4]
addx %g0,%g0,%o4 ! save cy in register
addcc size,-2,size
add s1_ptr,8,s1_ptr
add s2_ptr,8,s2_ptr
add res_ptr,8,res_ptr
bge Loope2
subcc %g0,%o4,%g0 ! restore cy
Lend2: andcc size,1,%g0
be Lret2
subcc %g0,%o4,%g0 ! restore cy
/* Add last limb */
Ljone: ld [s1_ptr],%g4
ld [s2_ptr],%g2
addxcc %g4,%g2,%o4
st %o4,[res_ptr]
Lret2: retl
addx %g0,%g0,%o0 ! return carry-out from most sign. limb
|
a1ive/grub
| 2,960
|
grub-core/lib/libgcrypt/mpi/power/mpih-mul1.S
|
/* IBM POWER mul_1 -- Multiply a limb vector with a limb and store
* the result in a second limb vector.
*
* Copyright (C) 1992, 1994, 1999, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s1_ptr r4
# size r5
# s2_limb r6
# The RS/6000 has no unsigned 32x32->64 bit multiplication instruction. To
# obtain that operation, we have to use the 32x32->64 signed multiplication
# instruction, and add the appropriate compensation to the high limb of the
# result. We add the multiplicand if the multiplier has its most significant
# bit set, and we add the multiplier if the multiplicand has its most
# significant bit set. We need to preserve the carry flag between each
# iteration, so we have to compute the compensation carefully (the natural,
# srai+and doesn't work). Since the POWER architecture has a branch unit
# we can branch in zero cycles, so that's how we perform the additions.
*/
.toc
.csect ._gcry_mpih_mul_1[PR]
.align 2
.globl _gcry_mpih_mul_1
.globl ._gcry_mpih_mul_1
.csect _gcry_mpih_mul_1[DS]
_gcry_mpih_mul_1:
.long ._gcry_mpih_mul_1[PR], TOC[tc0], 0
.csect ._gcry_mpih_mul_1[PR]
._gcry_mpih_mul_1:
cal 3,-4(3)
l 0,0(4)
cmpi 0,6,0
mtctr 5
mul 9,0,6
srai 7,0,31
and 7,7,6
mfmq 8
ai 0,0,0 # reset carry
cax 9,9,7
blt Lneg
Lpos: bdz Lend
Lploop: lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 10,0,6
mfmq 0
ae 8,0,9
bge Lp0
cax 10,10,6 # adjust high limb for negative limb from s1
Lp0: bdz Lend0
lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 9,0,6
mfmq 0
ae 8,0,10
bge Lp1
cax 9,9,6 # adjust high limb for negative limb from s1
Lp1: bdn Lploop
b Lend
Lneg: cax 9,9,0
bdz Lend
Lnloop: lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 10,0,6
cax 10,10,0 # adjust high limb for negative s2_limb
mfmq 0
ae 8,0,9
bge Ln0
cax 10,10,6 # adjust high limb for negative limb from s1
Ln0: bdz Lend0
lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 9,0,6
cax 9,9,0 # adjust high limb for negative s2_limb
mfmq 0
ae 8,0,10
bge Ln1
cax 9,9,6 # adjust high limb for negative limb from s1
Ln1: bdn Lnloop
b Lend
Lend0: cal 9,0(10)
Lend: st 8,4(3)
aze 3,9
br
|
a1ive/grub
| 3,169
|
grub-core/lib/libgcrypt/mpi/power/mpih-mul2.S
|
/* IBM POWER addmul_1 -- Multiply a limb vector with a limb and add
* the result to a second limb vector.
*
* Copyright (C) 1992, 1994, 1999, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s1_ptr r4
# size r5
# s2_limb r6
# The RS/6000 has no unsigned 32x32->64 bit multiplication instruction. To
# obtain that operation, we have to use the 32x32->64 signed multiplication
# instruction, and add the appropriate compensation to the high limb of the
# result. We add the multiplicand if the multiplier has its most significant
# bit set, and we add the multiplier if the multiplicand has its most
# significant bit set. We need to preserve the carry flag between each
# iteration, so we have to compute the compensation carefully (the natural,
# srai+and doesn't work). Since the POWER architecture has a branch unit
# we can branch in zero cycles, so that's how we perform the additions.
*/
.toc
.csect ._gcry_mpih_addmul_1[PR]
.align 2
.globl _gcry_mpih_addmul_1
.globl ._gcry_mpih_addmul_1
.csect _gcry_mpih_addmul_1[DS]
_gcry_mpih_addmul_1:
.long ._gcry_mpih_addmul_1[PR], TOC[tc0], 0
.csect ._gcry_mpih_addmul_1[PR]
._gcry_mpih_addmul_1:
cal 3,-4(3)
l 0,0(4)
cmpi 0,6,0
mtctr 5
mul 9,0,6
srai 7,0,31
and 7,7,6
mfmq 8
cax 9,9,7
l 7,4(3)
a 8,8,7 # add res_limb
blt Lneg
Lpos: bdz Lend
Lploop: lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 10,0,6
mfmq 0
ae 8,0,9 # low limb + old_cy_limb + old cy
l 7,4(3)
aze 10,10 # propagate cy to new cy_limb
a 8,8,7 # add res_limb
bge Lp0
cax 10,10,6 # adjust high limb for negative limb from s1
Lp0: bdz Lend0
lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 9,0,6
mfmq 0
ae 8,0,10
l 7,4(3)
aze 9,9
a 8,8,7
bge Lp1
cax 9,9,6 # adjust high limb for negative limb from s1
Lp1: bdn Lploop
b Lend
Lneg: cax 9,9,0
bdz Lend
Lnloop: lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 10,0,6
mfmq 7
ae 8,7,9
l 7,4(3)
ae 10,10,0 # propagate cy to new cy_limb
a 8,8,7 # add res_limb
bge Ln0
cax 10,10,6 # adjust high limb for negative limb from s1
Ln0: bdz Lend0
lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 9,0,6
mfmq 7
ae 8,7,10
l 7,4(3)
ae 9,9,0 # propagate cy to new cy_limb
a 8,8,7 # add res_limb
bge Ln1
cax 9,9,6 # adjust high limb for negative limb from s1
Ln1: bdn Lnloop
b Lend
Lend0: cal 9,0(10)
Lend: st 8,4(3)
aze 3,9
br
|
a1ive/grub
| 1,943
|
grub-core/lib/libgcrypt/mpi/power/mpih-lshift.S
|
/* IBM POWER lshift
*
* Copyright (C) 1992, 1994, 1999, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s_ptr r4
# size r5
# cnt r6
*/
.toc
.extern _gcry_mpih_lshift[DS]
.extern ._gcry_mpih_lshift
.csect [PR]
.align 2
.globl _gcry_mpih_lshift
.globl ._gcry_mpih_lshift
.csect _gcry_mpih_lshift[DS]
_gcry_mpih_lshift:
.long ._gcry_mpih_lshift, TOC[tc0], 0
.csect [PR]
._gcry_mpih_lshift:
sli 0,5,2
cax 9,3,0
cax 4,4,0
sfi 8,6,32
mtctr 5 # put limb count in CTR loop register
lu 0,-4(4) # read most significant limb
sre 3,0,8 # compute carry out limb, and init MQ register
bdz Lend2 # if just one limb, skip loop
lu 0,-4(4) # read 2:nd most significant limb
sreq 7,0,8 # compute most significant limb of result
bdz Lend # if just two limb, skip loop
Loop: lu 0,-4(4) # load next lower limb
stu 7,-4(9) # store previous result during read latency
sreq 7,0,8 # compute result limb
bdn Loop # loop back until CTR is zero
Lend: stu 7,-4(9) # store 2:nd least significant limb
Lend2: sle 7,0,6 # compute least significant limb
st 7,-4(9) # store it
br
|
a1ive/grub
| 1,962
|
grub-core/lib/libgcrypt/mpi/power/mpih-rshift.S
|
/* IBM POWER rshift
*
* Copyright (C) 1992, 1994, 1999, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s_ptr r4
# size r5
# cnt r6
*/
.toc
.extern _gcry_mpih_rshift[DS]
.extern ._gcry_mpih_rshift
.csect [PR]
.align 2
.globl _gcry_mpih_rshift
.globl ._gcry_mpih_rshift
.csect _gcry_mpih_rshift[DS]
_gcry_mpih_rshift:
.long ._gcry_mpih_rshift, TOC[tc0], 0
.csect [PR]
._gcry_mpih_rshift:
sfi 8,6,32
mtctr 5 # put limb count in CTR loop register
l 0,0(4) # read least significant limb
ai 9,3,-4 # adjust res_ptr since it's offset in the stu:s
sle 3,0,8 # compute carry limb, and init MQ register
bdz Lend2 # if just one limb, skip loop
lu 0,4(4) # read 2:nd least significant limb
sleq 7,0,8 # compute least significant limb of result
bdz Lend # if just two limb, skip loop
Loop: lu 0,4(4) # load next higher limb
stu 7,4(9) # store previous result during read latency
sleq 7,0,8 # compute result limb
bdn Loop # loop back until CTR is zero
Lend: stu 7,4(9) # store 2:nd most significant limb
Lend2: sre 7,0,6 # compute most significant limb
st 7,4(9) # store it
br
|
a1ive/grub
| 3,381
|
grub-core/lib/libgcrypt/mpi/power/mpih-mul3.S
|
/* IBM POWER submul_1 -- Multiply a limb vector with a limb and subtract
* the result from a second limb vector.
*
* Copyright (C) 1992, 1994, 1999, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s1_ptr r4
# size r5
# s2_limb r6
# The RS/6000 has no unsigned 32x32->64 bit multiplication instruction. To
# obtain that operation, we have to use the 32x32->64 signed multiplication
# instruction, and add the appropriate compensation to the high limb of the
# result. We add the multiplicand if the multiplier has its most significant
# bit set, and we add the multiplier if the multiplicand has its most
# significant bit set. We need to preserve the carry flag between each
# iteration, so we have to compute the compensation carefully (the natural,
# srai+and doesn't work). Since the POWER architecture has a branch unit
# we can branch in zero cycles, so that's how we perform the additions.
*/
.toc
.csect ._gcry_mpih_submul_1[PR]
.align 2
.globl _gcry_mpih_submul_1
.globl ._gcry_mpih_submul_1
.csect _gcry_mpih_submul_1[DS]
_gcry_mpih_submul_1:
.long ._gcry_mpih_submul_1[PR], TOC[tc0], 0
.csect ._gcry_mpih_submul_1[PR]
._gcry_mpih_submul_1:
cal 3,-4(3)
l 0,0(4)
cmpi 0,6,0
mtctr 5
mul 9,0,6
srai 7,0,31
and 7,7,6
mfmq 11
cax 9,9,7
l 7,4(3)
sf 8,11,7 # add res_limb
a 11,8,11 # invert cy (r11 is junk)
blt Lneg
Lpos: bdz Lend
Lploop: lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 10,0,6
mfmq 0
ae 11,0,9 # low limb + old_cy_limb + old cy
l 7,4(3)
aze 10,10 # propagate cy to new cy_limb
sf 8,11,7 # add res_limb
a 11,8,11 # invert cy (r11 is junk)
bge Lp0
cax 10,10,6 # adjust high limb for negative limb from s1
Lp0: bdz Lend0
lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 9,0,6
mfmq 0
ae 11,0,10
l 7,4(3)
aze 9,9
sf 8,11,7
a 11,8,11 # invert cy (r11 is junk)
bge Lp1
cax 9,9,6 # adjust high limb for negative limb from s1
Lp1: bdn Lploop
b Lend
Lneg: cax 9,9,0
bdz Lend
Lnloop: lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 10,0,6
mfmq 7
ae 11,7,9
l 7,4(3)
ae 10,10,0 # propagate cy to new cy_limb
sf 8,11,7 # add res_limb
a 11,8,11 # invert cy (r11 is junk)
bge Ln0
cax 10,10,6 # adjust high limb for negative limb from s1
Ln0: bdz Lend0
lu 0,4(4)
stu 8,4(3)
cmpi 0,0,0
mul 9,0,6
mfmq 7
ae 11,7,10
l 7,4(3)
ae 9,9,0 # propagate cy to new cy_limb
sf 8,11,7 # add res_limb
a 11,8,11 # invert cy (r11 is junk)
bge Ln1
cax 9,9,6 # adjust high limb for negative limb from s1
Ln1: bdn Lnloop
b Lend
Lend0: cal 9,0(10)
Lend: st 8,4(3)
aze 3,9
br
|
a1ive/grub
| 2,763
|
grub-core/lib/libgcrypt/mpi/power/mpih-add1.S
|
/* IBM POWER add_n -- Add two limb vectors of equal, non-zero length.
*
* Copyright (C) 1992, 1994, 1996, 1999,
* 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s1_ptr r4
# s2_ptr r5
# size r6
*/
.toc
.extern _gcry_mpih_add_n[DS]
.extern ._gcry_mpih_add_n
.csect [PR]
.align 2
.globl _gcry_mpih_add_n
.globl ._gcry_mpih_add_n
.csect _gcry_mpih_add_n[DS]
_gcry_mpih_add_n:
.long ._gcry_mpih_add_n, TOC[tc0], 0
.csect [PR]
._gcry_mpih_add_n:
andil. 10,6,1 # odd or even number of limbs?
l 8,0(4) # load least significant s1 limb
l 0,0(5) # load least significant s2 limb
cal 3,-4(3) # offset res_ptr, it's updated before it's used
sri 10,6,1 # count for unrolled loop
a 7,0,8 # add least significant limbs, set cy
mtctr 10 # copy count into CTR
beq 0,Leven # branch if even # of limbs (# of limbs >= 2)
# We have an odd # of limbs. Add the first limbs separately.
cmpi 1,10,0 # is count for unrolled loop zero?
bne 1,L1 # branch if not
st 7,4(3)
aze 3,10 # use the fact that r10 is zero...
br # return
# We added least significant limbs. Now reload the next limbs to enter loop.
L1: lu 8,4(4) # load s1 limb and update s1_ptr
lu 0,4(5) # load s2 limb and update s2_ptr
stu 7,4(3)
ae 7,0,8 # add limbs, set cy
Leven: lu 9,4(4) # load s1 limb and update s1_ptr
lu 10,4(5) # load s2 limb and update s2_ptr
bdz Lend # If done, skip loop
Loop: lu 8,4(4) # load s1 limb and update s1_ptr
lu 0,4(5) # load s2 limb and update s2_ptr
ae 11,9,10 # add previous limbs with cy, set cy
stu 7,4(3) #
lu 9,4(4) # load s1 limb and update s1_ptr
lu 10,4(5) # load s2 limb and update s2_ptr
ae 7,0,8 # add previous limbs with cy, set cy
stu 11,4(3) #
bdn Loop # decrement CTR and loop back
Lend: ae 11,9,10 # add limbs with cy, set cy
st 7,4(3) #
st 11,8(3) #
lil 3,0 # load cy into ...
aze 3,3 # ... return value register
br
|
a1ive/grub
| 2,835
|
grub-core/lib/libgcrypt/mpi/power/mpih-sub1.S
|
/* IBM POWER sub_n -- Subtract two limb vectors of equal, non-zero length.
*
* Copyright (C) 1992, 1994, 1995, 1996, 1999,
* 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include "sysdep.h"
#include "asm-syntax.h"
/*
# INPUT PARAMETERS
# res_ptr r3
# s1_ptr r4
# s2_ptr r5
# size r6
*/
.toc
.extern _gcry_mpih_sub_n[DS]
.extern ._gcry_mpih_sub_n
.csect [PR]
.align 2
.globl _gcry_mpih_sub_n
.globl ._gcry_mpih_sub_n
.csect _gcry_mpih_sub_n[DS]
_gcry_mpih_sub_n:
.long ._gcry_mpih_sub_n, TOC[tc0], 0
.csect [PR]
._gcry_mpih_sub_n:
andil. 10,6,1 # odd or even number of limbs?
l 8,0(4) # load least significant s1 limb
l 0,0(5) # load least significant s2 limb
cal 3,-4(3) # offset res_ptr, it's updated before it's used
sri 10,6,1 # count for unrolled loop
sf 7,0,8 # subtract least significant limbs, set cy
mtctr 10 # copy count into CTR
beq 0,Leven # branch if even # of limbs (# of limbs >= 2)
# We have an odd # of limbs. Add the first limbs separately.
cmpi 1,10,0 # is count for unrolled loop zero?
bne 1,L1 # branch if not
st 7,4(3)
sfe 3,0,0 # load !cy into ...
sfi 3,3,0 # ... return value register
br # return
# We added least significant limbs. Now reload the next limbs to enter loop.
L1: lu 8,4(4) # load s1 limb and update s1_ptr
lu 0,4(5) # load s2 limb and update s2_ptr
stu 7,4(3)
sfe 7,0,8 # subtract limbs, set cy
Leven: lu 9,4(4) # load s1 limb and update s1_ptr
lu 10,4(5) # load s2 limb and update s2_ptr
bdz Lend # If done, skip loop
Loop: lu 8,4(4) # load s1 limb and update s1_ptr
lu 0,4(5) # load s2 limb and update s2_ptr
sfe 11,10,9 # subtract previous limbs with cy, set cy
stu 7,4(3) #
lu 9,4(4) # load s1 limb and update s1_ptr
lu 10,4(5) # load s2 limb and update s2_ptr
sfe 7,0,8 # subtract previous limbs with cy, set cy
stu 11,4(3) #
bdn Loop # decrement CTR and loop back
Lend: sfe 11,10,9 # subtract limbs with cy, set cy
st 7,4(3) #
st 11,8(3) #
sfe 3,0,0 # load !cy into ...
sfi 3,3,0 # ... return value register
br
|
a1ive/grub
| 2,600
|
grub-core/lib/libgcrypt/mpi/supersparc/udiv.S
|
/* SuperSPARC __udiv_qrnnd division support, used from longlong.h.
* This is for SuperSPARC only, to compensate for its
* semi-functional udiv instruction.
*
* Copyright (C) 1993, 1994, 1996, 1998,
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* Note: This code is heavily based on the GNU MP Library.
* Actually it's the same code with only minor changes in the
* way the data is stored; this is to support the abstraction
* of an optional secure memory allocation which may be used
* to avoid revealing of sensitive data due to paging etc.
*/
! INPUT PARAMETERS
! rem_ptr i0
! n1 i1
! n0 i2
! d i3
#include "sysdep.h"
#undef ret /* Kludge for glibc */
.text
.align 8
LC0: .double 0r4294967296
LC1: .double 0r2147483648
.align 4
.global C_SYMBOL_NAME(__udiv_qrnnd)
C_SYMBOL_NAME(__udiv_qrnnd):
!#PROLOGUE# 0
save %sp,-104,%sp
!#PROLOGUE# 1
st %i1,[%fp-8]
ld [%fp-8],%f10
sethi %hi(LC0),%o7
fitod %f10,%f4
ldd [%o7+%lo(LC0)],%f8
cmp %i1,0
bge L248
mov %i0,%i5
faddd %f4,%f8,%f4
L248:
st %i2,[%fp-8]
ld [%fp-8],%f10
fmuld %f4,%f8,%f6
cmp %i2,0
bge L249
fitod %f10,%f2
faddd %f2,%f8,%f2
L249:
st %i3,[%fp-8]
faddd %f6,%f2,%f2
ld [%fp-8],%f10
cmp %i3,0
bge L250
fitod %f10,%f4
faddd %f4,%f8,%f4
L250:
fdivd %f2,%f4,%f2
sethi %hi(LC1),%o7
ldd [%o7+%lo(LC1)],%f4
fcmped %f2,%f4
nop
fbge,a L251
fsubd %f2,%f4,%f2
fdtoi %f2,%f2
st %f2,[%fp-8]
b L252
ld [%fp-8],%i4
L251:
fdtoi %f2,%f2
st %f2,[%fp-8]
ld [%fp-8],%i4
sethi %hi(-2147483648),%g2
xor %i4,%g2,%i4
L252:
umul %i3,%i4,%g3
rd %y,%i0
subcc %i2,%g3,%o7
subxcc %i1,%i0,%g0
be L253
cmp %o7,%i3
add %i4,-1,%i0
add %o7,%i3,%o7
st %o7,[%i5]
ret
restore
L253:
blu L246
mov %i4,%i0
add %i4,1,%i0
sub %o7,%i3,%o7
L246:
st %o7,[%i5]
ret
restore
|
a1ive/grub
| 1,872
|
grub-core/lib/libgcrypt/mpi/hppa/mpih-lshift.S
|
/* hppa lshift
*
* Copyright (C) 1992, 1994, 1998
* 2001, 2002 Free Software Foundation, Inc.
*
* This file is part of Libgcrypt.
*
* Libgcrypt is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* Libgcrypt is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*******************
* mpi_limb_t
* _gcry_mpih_lshift( mpi_ptr_t wp, (gr26)
* mpi_ptr_t up, (gr25)
* mpi_size_t usize, (gr24)
* unsigned cnt) (gr23)
*/
.code
.export _gcry_mpih_lshift
.label _gcry_mpih_lshift
.proc
.callinfo frame=64,no_calls
.entry
sh2add %r24,%r25,%r25
sh2add %r24,%r26,%r26
ldws,mb -4(0,%r25),%r22
subi 32,%r23,%r1
mtsar %r1
addib,= -1,%r24,L$0004
vshd %r0,%r22,%r28 ; compute carry out limb
ldws,mb -4(0,%r25),%r29
addib,= -1,%r24,L$0002
vshd %r22,%r29,%r20
.label L$loop
ldws,mb -4(0,%r25),%r22
stws,mb %r20,-4(0,%r26)
addib,= -1,%r24,L$0003
vshd %r29,%r22,%r20
ldws,mb -4(0,%r25),%r29
stws,mb %r20,-4(0,%r26)
addib,<> -1,%r24,L$loop
vshd %r22,%r29,%r20
.label L$0002
stws,mb %r20,-4(0,%r26)
vshd %r29,%r0,%r20
bv 0(%r2)
stw %r20,-4(0,%r26)
.label L$0003
stws,mb %r20,-4(0,%r26)
.label L$0004
vshd %r22,%r0,%r20
bv 0(%r2)
stw %r20,-4(0,%r26)
.exit
.procend
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.