repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
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| content
stringlengths 590
5.01M
|
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb
| 1,702
|
gas/testsuite/gas/visium/allinsn_def.s
|
begin:
write.l (r2),r1
write.l 0(r2),r1
write.w 1(r1),r2
write.b 31(r3),r7
write.b (r4),r7
eamwrite 0,r4,r5
eamwrite 31,r7,r10
writemd r14,r15
writemdc r9
divs r5
divu r6
divds r10
divdu r11
asrd r12
lsrd r13
asld r14
dsi
mults r7,r8
multu r9,r10
eni
dsi
rfi
nsrel:
brr fa,nsrel
rflag r0
brr eq,nsrel
rflag r0
brr cs,nsrel
rflag r0
brr os,nsrel
rflag r0
brr ns,sreg
rflag r0
brr ne,sreg
rflag r0
brr cc,sreg
rflag r0
brr oc,sreg
rflag r0
brr nc,sreg
rflag r0
brr ge,sreg
rflag r0
brr gt,sreg
rflag r0
brr hi,sreg
rflag r0
brr le,sreg
rflag r0
brr ls,sreg
rflag r0
brr lt,sreg
rflag r0
brr tr,sreg
rflag r0
brr eq,nsrel
nop
brr fa,.
nop
sreg:
adc.l r0,r0,r1
adc.w r2,r0,r3
adc.b r4,r0,r5
add.l r2,r0,r1
add.w r5,r4,r3
add.b r7,r7,r6
and.l r2,r0,r1
and.w r5,r4,r3
and.b r7,r7,r6
asl.l r4,r3,r4
asl.w r6,r5,0
asl.w r6,r5,1
asl.b r8,r7,31
asr.l r4,r3,r4
asr.w r6,r5,0
asr.w r6,r5,1
asr.b r8,r7,31
bra eq,r9,r10
rflag r0
bra ne,r7,r1
eamread r11,0
eamread r12,31
extb.l r12,r13
extb.w r14,r15
extb.b r0,r1
extw.l r2,r3
extw.w r4,r5
lsr.l r6,r7,r8
lsr.w r9,r10,0
lsr.w r9,r10,1
lsr.b r9,r10,31
not.l r11,r12
not.w r13,r14
not.b r15,r10
or.l r5,r6,r7
or.w r8,r9,r10
or.b r1,r2,r3
read.l r4,(r5)
read.l r4,0(r5)
read.w r6,1(r7)
read.b r8,31(r9)
read.b r6,1(r9)
readmda r10
readmdb r11
readmdc r17
rflag r4
rflag r7
sub.l r4,r5,r6
sub.w r7,r8,r9
sub.b r0,r1,r2
subc.l r4,r5,r6
subc.w r7,r8,r9
subc.b r0,r1,r2
xor.l r4,r3,r2
xor.w r5,r6,r7
xor.b r1,r9,r8
addi r7,65535
movil r7,32768
moviu r7,32767
moviq r6,1
subi r7,65535
bra tr,r6,r0
add.l r0,r0,r0
.end
|
tactcomplabs/xbgas-binutils-gdb
| 1,446
|
gas/testsuite/gas/mmix/comment-1.s
|
# Check that "naked" comments are accepted and ignored on all different
# mnemonic types and pseudos. The goal is to use all combinations of
# operands where varying number of operands are allowed. If any
# combinations are missing, for simplicity, add them to another file.
Main TRAP 123 ignore; x y z
TRAP 1,23 all; x y z
TRAP 1,2,3 these; x y z
FCMP $3,$2,$1 comments; x y z
FLOT $5,6 and; x y z
FLOT $7,ROUND_UP,8 do; x y z
FIX $9,$10 nothing; x y z
FIX $11,ROUND_DOWN,$12 that; x y z
ADDU $15,$16,17 would make; x y z
LDA $18,$19 a; x y z
LDA $20,$21,22 difference; x y z
NEG $23,$24 in; x y z
NEG $25,26,$27 the; x y z
bn $28,target + 44 generated; x y z
SYNCD 29,$30,31 code; x y z
PUSHGO 32,$33,34 so; x y z
SET $35,$36 it; x y z
SETH $37,target2 + 48 is; x y z
JMP target3 + 56 as; x y z
POP 38,39 if; x y z
RESUME 40 it; x y z
PUSHJ $41,target3 had; x y z
SAVE $42,0 never; x y z
UNSAVE 0,$43 been; x y z
PUT rJ,$44 there; x y z
GET $45,rJ at all.; x y z
LOC @+4 likewise; x y z
PREFIX : with; x y z
BYTE 3,2,1,0+4 the; x y z
WYDE 7,4+8 different; x y z
TETRA 8+12 pseudo; x y z
OCTA 12+16 ops,; x y z
LOCAL 48 they; x y z
BSPEC 49 too; x y z
# Specifying an operand field (although ignored) is necessary for a comment
# with a ';' to be ignorable and not interpreted as eoln, both for GAS and
# mmixal.
ESPEC 0 ignore; x y z
GREG 50 + 1 naked; x y z
z IS 9 + 8 + 7 comments; x y z
x SWYM 34,21,56
|
tactcomplabs/xbgas-binutils-gdb
| 1,784
|
gas/testsuite/gas/mmix/regt-op.s
|
# All-registers, 'T'-type operands; optional third operand is
# register or constant.
Main LDA X,Y,Z
LDT $32,Y,Z
LDBU Y,$32,Z
LDTU $232,$133,Z
LDO X,Y,$73
LDOU $31,Y,$233
LDW X,$38,$212
LDWU $4,$175,$181
LDB X,Y,Z0
LDSF $32,Y,Z0
LDVTS Y,$32,Z0
LDUNC $232,$133,Z0
STHT X,Y,203
LDHT $31,Y,213
CSWAP X,$38,211
GO $4,$175,161
LDA X,Y
LDB X,Y
LDT X,Y
LDBU X,Y
LDTU X,Y
LDO X,Y
LDOU X,Y
LDW X,Y
LDWU X,Y
LDSF X,Y
LDHT X,Y
CSWAP X,Y
LDUNC X,Y
LDVTS X,Y
GO X,Y
STB X,Y
STT X,Y
STBU X,Y
STTU X,Y
STO X,Y
STOU X,Y
STW X,Y
STWU X,Y
STSF X,Y
STHT X,Y
STUNC X,Y
LDA $41,Y
LDB $121,Y
LDT $78,Y
LDBU $127,Y
LDTU $49,Y
LDO $52,Y
LDOU $42,Y
LDW $123,Y
LDWU $234,Y
LDSF $41,Y
LDHT $89,Y
CSWAP $93,Y
LDUNC $42,Y
LDVTS $33,Y
GO $59,Y
STB $59,Y
STT $59,Y
STBU $59,Y
STTU $59,Y
STO $59,Y
STOU $59,Y
STW $59,Y
STWU $59,Y
STSF $59,Y
STHT $59,Y
STUNC $59,Y
LDA X,$27
LDB X,$48
LDT X,$168
LDBU X,$234
LDTU X,$176
LDO X,$29
LDOU X,$222
LDW X,$222
LDWU X,$222
LDSF X,$222
LDHT X,$222
CSWAP X,$222
LDUNC X,$222
LDVTS X,$222
GO X,$222
STB X,$222
STT X,$222
STBU X,$222
STTU X,$222
STO X,$222
STOU X,$222
STW X,$222
STWU X,$222
STSF X,$222
STHT X,$222
STUNC X,$222
LDA $223,$219
LDB $223,$239
LDT $223,$239
LDBU $223,$29
LDTU $223,$239
LDO $23,$239
LDOU $223,$239
LDW $223,$209
LDWU $123,$239
LDSF $223,$239
LDHT $223,$29
CSWAP $223,$239
LDUNC $123,$239
LDVTS $223,$239
GO $223,$239
STB $223,$239
STT $223,$249
STBU $203,$239
STTU $73,$239
STO $223,$239
STOU $223,$39
STW $223,$239
STWU $233,$239
STSF $223,$239
STHT $223,$23
STUNC $223,$239
GO X,Y,0
LDVTS $32,Y,0
STB Y,$32,0
STUNC $232,$133,0
STWU X,Y,0
STO $31,Y,0
GO X,$38,0
CSWAP $4,$175,0
X IS $23
Y IS $12
Z IS $67
Z0 IS 176
|
tactcomplabs/xbgas-binutils-gdb
| 5,977
|
gas/testsuite/gas/mmix/pr25331.s
|
# 1 "pr25331.c"
! mmixal:= 8H LOC Data_Section
.text ! mmixal:= 9H LOC 8B
.global f
.data ! mmixal:= 8H LOC 9B
.p2align 3
LOC @+(8-@)&7
f IS @
LOC @+8
.global g
.p2align 2
LOC @+(4-@)&3
g IS @
LOC @+4
.global h
.p2align 3
LOC @+(8-@)&7
h IS @
LOC @+8
.section .rodata
.p2align 2
LOC @+(4-@)&3
LC:0 IS @
BYTE #0
.text ! mmixal:= 9H LOC 8B
.p2align 2
LOC @+(4-@)&3
.global i
i IS @
SUBU $254,$254,240
STOU $253,$254,232
ADDU $253,$254,240
SUBU $254,$254,168
GET $1,rJ
SETL $5,#198
NEGU $5,0,$5
ADDU $4,$253,$5
STOU $0,$4,0
SUBU $0,$253,16
LDO $6,__stack_chk_guard
STOU $6,$0,0
SETL $7,#184
NEGU $7,0,$7
ADDU $0,$253,$7
PUSHJ $8,ak
PUT rJ,$1
STTU $8,$0,0
PUSHJ $8,o
PUT rJ,$1
SET $4,$8
SETL $5,#18b
NEGU $5,0,$5
ADDU $0,$253,$5
STBU $4,$0,0
PUSHJ $8,ag
PUT rJ,$1
SETL $6,#18a
NEGU $6,0,$6
ADDU $0,$253,$6
LDW $0,$0,0
SET $0,$0
SLU $0,$0,16
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
SR $0,$0,16
SET $0,$0
AND $0,$0,8
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:2
SETL $7,#168
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
CMP $0,$0,0
BZ $0,L:2
GETA $9,c
PUSHJ $8,t
PUT rJ,$1
SET $0,$8
SLU $0,$0,32
SR $0,$0,32
SETL $5,#168
NEGU $5,0,$5
ADDU $4,$253,$5
STOU $0,$4,0
L:2 IS @
SETL $6,#168
NEGU $6,0,$6
ADDU $0,$253,$6
LDO $0,$0,0
CMP $0,$0,0
BZ $0,L:3
SETL $7,#174
NEGU $7,0,$7
ADDU $0,$253,$7
SETL $1,#2
STTU $1,$0,0
JMP L:4
L:3 IS @
PUSHJ $8,u
PUT rJ,$1
JMP L:5
L:7 IS @
LDT $0,g
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:5
SETL $4,#184
NEGU $4,0,$4
ADDU $0,$253,$4
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:29
L:5 IS @
PUSHJ $8,c
PUT rJ,$1
SET $0,$8
LDO $0,$0,0
PUSHGO $8,$0,0
PUT rJ,$1
SET $0,$8
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:7
JMP L:6
L:29 IS @
SWYM 0,0,0
L:6 IS @
LDT $0,g
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:30
SWYM 0,0,0
JMP L:9
L:31 IS @
SWYM 0,0,0
JMP L:9
L:32 IS @
SWYM 0,0,0
L:9 IS @
LDO $0,f
SET $2,$0
JMP L:8
L:30 IS @
SWYM 0,0,0
L:8 IS @
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,71
BZ $0,L:10
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,71
BP $0,L:4
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,32
BZ $0,L:12
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,68
BZ $0,L:13
JMP L:4
L:12 IS @
SETL $5,#18b
NEGU $5,0,$5
ADDU $0,$253,$5
LDB $0,$0,0
SLU $0,$0,56
SR $0,$0,56
CMP $0,$0,0
BZ $0,L:14
SETL $6,#18b
NEGU $6,0,$6
ADDU $0,$253,$6
SETL $7,#20
STBU $7,$0,0
L:14 IS @
SETL $2,#198
NEGU $2,0,$2
ADDU $0,$253,$2
LDO $0,$0,0
ADDU $4,$0,8
SETL $5,#198
NEGU $5,0,$5
ADDU $2,$253,$5
STOU $4,$2,0
ADDU $2,$0,4
SETL $6,#180
NEGU $6,0,$6
ADDU $0,$253,$6
LDT $7,$2,0
STTU $7,$0,0
SETL $2,#180
NEGU $2,0,$2
ADDU $0,$253,$2
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:31
SETL $4,#180
NEGU $4,0,$4
ADDU $0,$253,$4
SETL $5,#180
NEGU $5,0,$5
ADDU $2,$253,$5
LDT $6,$2,0
STTU $6,$0,0
LDO $0,f
ADDU $2,$0,1
STOU $2,f
LDB $0,$0,0
SET $0,$0
SLU $0,$0,24
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
SR $0,$0,24
SET $2,$0
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:16
SETL $7,#198
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
ADDU $5,$0,8
SETL $6,#198
NEGU $6,0,$6
ADDU $4,$253,$6
STOU $5,$4,0
ADDU $0,$0,4
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
STOU $0,f
L:16 IS @
SETL $7,#17c
NEGU $7,0,$7
ADDU $0,$253,$7
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:32
SWYM 0,0,0
L:18 IS @
SET $0,$2
SLU $0,$0,32
SRU $0,$0,32
CMPU $0,$0,9
BNP $0,L:18
JMP L:19
L:22 IS @
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:20
AND $0,$3,6
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:21
L:20 IS @
PUSHJ $8,ak
PUT rJ,$1
SETL $4,#198
NEGU $4,0,$4
ADDU $0,$253,$4
LDO $0,$0,0
ADDU $5,$0,8
SETL $6,#198
NEGU $6,0,$6
ADDU $4,$253,$6
STOU $5,$4,0
ADDU $0,$0,4
LDT $0,$0,0
SETL $7,#178
NEGU $7,0,$7
ADDU $4,$253,$7
SETL $5,#188
NEGU $5,0,$5
ADDU $6,$253,$5
SLU $0,$0,32
SR $0,$0,32
SETL $7,#170
NEGU $7,0,$7
ADDU $5,$253,$7
SET $11,$6
SET $10,$0
LDO $9,$5,0
PUSHJ $8,ao
PUT rJ,$1
STTU $8,$4,0
JMP L:19
L:21 IS @
LDO $4,h
SETL $5,#198
NEGU $5,0,$5
ADDU $0,$253,$5
LDO $0,$0,0
ADDU $6,$0,8
SETL $7,#198
NEGU $7,0,$7
ADDU $5,$253,$7
STOU $6,$5,0
ADDU $0,$0,4
LDT $0,$0,0
STTU $0,$4,0
L:19 IS @
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:22
JMP L:4
L:13 IS @
AND $0,$3,6
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:23
SETL $1,#198
NEGU $1,0,$1
ADDU $0,$253,$1
LDO $0,$0,0
ADDU $4,$0,8
SETL $5,#198
NEGU $5,0,$5
ADDU $1,$253,$5
STOU $4,$1,0
LDO $0,$0,0
JMP L:24
L:23 IS @
AND $0,$3,4
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:25
SETL $6,#198
NEGU $6,0,$6
ADDU $0,$253,$6
LDO $0,$0,0
ADDU $4,$0,8
SETL $7,#198
NEGU $7,0,$7
ADDU $1,$253,$7
STOU $4,$1,0
ADDU $0,$0,4
LDT $0,$0,0
SET $0,$0
SLU $0,$0,48
SR $0,$0,48
JMP L:24
L:25 IS @
SETL $1,#198
NEGU $1,0,$1
ADDU $0,$253,$1
LDO $0,$0,0
ADDU $4,$0,8
SETL $5,#198
NEGU $5,0,$5
ADDU $1,$253,$5
STOU $4,$1,0
ADDU $0,$0,4
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
L:24 IS @
SETL $6,#158
NEGU $6,0,$6
ADDU $1,$253,$6
STOU $0,$1,0
L:10 IS @
AND $0,$3,8
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:27
SETL $7,#198
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
ADDU $3,$0,8
SETL $4,#198
NEGU $4,0,$4
ADDU $1,$253,$4
STOU $3,$1,0
SETL $5,#160
NEGU $5,0,$5
ADDU $1,$253,$5
LDO $6,$0,0
STOU $6,$1,0
L:27 IS @
SETL $7,#168
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
CMP $0,$0,0
BZ $0,L:4
SETL $1,#160
NEGU $1,0,$1
ADDU $0,$253,$1
LDO $0,$0,0
SRU $0,$0,63
SET $0,$0
AND $0,$0,1
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:4
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:4
GETA $2,LC:0
STOU $2,h
L:4 IS @
SUBU $0,$253,16
LDO $1,$0,0
LDO $0,__stack_chk_guard
CMP $0,$1,$0
BZ $0,L:28
PUSHJ $8,__stack_chk_fail
L:28 IS @
SET $0,$2
INCL $254,#190
LDO $253,$254,0
ADDU $254,$254,8
POP 1,0
.data ! mmixal:= 8H LOC 9B
|
tactcomplabs/xbgas-binutils-gdb
| 1,122
|
gas/testsuite/gas/mmix/pushgo-op.s
|
# PUSHGO. Like T, but $X can be expressed as a constant.
# Using regt-op as a template caused this to go out of control.
Main PUSHGO X,Y,Z
PUSHGO XC,Y,Z
PUSHGO $32,Y,Z
PUSHGO 32,Y,Z
PUSHGO X,$32,Z
PUSHGO XC,$32,Z
PUSHGO $232,$133,Z
PUSHGO 232,$133,Z
PUSHGO X,Y,$73
PUSHGO XC,Y,$73
PUSHGO $31,Y,$233
PUSHGO 31,Y,$233
PUSHGO X,$38,$212
PUSHGO XC,$38,$212
PUSHGO $4,$175,$181
PUSHGO 4,$175,$181
PUSHGO X,Y,Z0
PUSHGO XC,Y,Z0
PUSHGO $32,Y,Z0
PUSHGO 32,Y,Z0
PUSHGO X,$32,Z0
PUSHGO XC,$32,Z0
PUSHGO $232,$133,Z0
PUSHGO 232,$133,Z0
PUSHGO X,Y,203
PUSHGO XC,Y,203
PUSHGO $31,Y,213
PUSHGO 31,Y,213
PUSHGO X,$38,211
PUSHGO XC,$38,211
PUSHGO $4,$175,161
PUSHGO 4,$175,161
PUSHGO X,Y
PUSHGO XC,Y
PUSHGO $41,Y
PUSHGO 241,Y
PUSHGO X,$27
PUSHGO XC,$48
PUSHGO $223,$219
PUSHGO 223,$229
PUSHGO X,Y,0
PUSHGO XC,Y,0
PUSHGO $32,Y,0
PUSHGO 32,Y,0
PUSHGO X,$32,0
PUSHGO XC,$32,0
PUSHGO $232,$133,0
PUSHGO 232,$133,0
PUSHGO X,Y,0
PUSHGO XC,Y,0
PUSHGO $31,Y,0
PUSHGO 31,Y,0
PUSHGO X,$38,0
PUSHGO XC,$38,0
PUSHGO $4,$175,0
PUSHGO 4,$175,0
X IS $23
XC IS 203
Y IS $12
Z IS $67
Z0 IS 176
|
tactcomplabs/xbgas-binutils-gdb
| 4,890
|
gas/testsuite/gas/mmix/list-insns.s
|
#
# Somewhat complete instruction set and operand type check. No
# relocations or deferred register definitions here.
#
#
#
Main TETRA 3
TRAP 3,4,5
FCMP $12,$23,$241
FLOT $112,ROUND_OFF,$41
FLOT $112,ROUND_NEAR,141
FLOT $191,$242
FLOT $195,42
FUN $122,$203,$4
FEQL $102,$30,$40
FLOTU $102,$14
FLOTU $132,ROUND_UP,$14
FLOTU $102,ROUND_DOWN,$104
FLOTU $172,ROUND_NEAR,$140
FLOTU $1,ROUND_OFF,$134
FADD $112,$223,$41
FIX $112,ROUND_OFF,$41
FIX $11,$141
SFLOT $112,ROUND_OFF,$41
SFLOT $112,ROUND_NEAR,141
FSUB $112,$223,$41
FIXU $102,$14
FIXU $132,ROUND_UP,$14
SFLOTU $11,$141
SFLOTU $112,141
SFLOTU $112,ROUND_NEAR,141
SFLOTU $112,ROUND_OFF,$41
FMUL $102,$30,$40
FCMPE $12,$223,$1
MUL $122,$203,44
MUL $102,$30,$40
FEQLE $12,$223,$1
FUNE $12,$223,$11
MULU $122,$213,44
MULU $132,$30,$40
FDIV $12,$223,$11
FSQRT $132,ROUND_UP,$14
FSQRT $11,$141
DIV $122,$213,44
DIV $132,$30,$40
FREM $12,$223,$11
FINT $132,ROUND_UP,$14
FINT $11,$141
DIVU $12,$223,$1
DIVU $122,$203,255
ADD $12,$223,$1
ADD $122,$203,255
2ADDU $12,$223,$11
2ADDU $122,$203,0
ADDU $122,$203,255
ADDU $12,$223,$11
LDA $122,$203,255
LDA $12,$223,$11
4ADDU $122,$203,205
4ADDU $12,$223,$111
SUB $12,$223,$11
SUB $122,$203,205
8ADDU $12,$223,$11
8ADDU $122,$203,205
SUBU $2,$223,$11
SUBU $12,$20,205
16ADDU $2,$223,$11
16ADDU $12,$20,205
CMP $2,$223,$11
CMP $12,$20,205
SL $2,$223,$11
SL $12,$20,205
CMPU $2,$223,$11
CMPU $12,$20,205
SLU $2,$223,$11
SLU $12,$20,205
NEG $2,23,$11
NEG $12,0,205
NEG $192,10,205
SR $12,$20,205
SR $2,$223,$11
NEGU $2,23,$11
NEGU $12,0,205
SRU $12,$20,205
SRU $2,$223,$11
1H BN $2,2F
2H BN $2,1B
1H BNN $2,2B
2H BNN $2,1B
1H BZ $255,2F
2H BZ $255,1B
1H BNZ $255,2F
2H BNZ $255,1B
1H BP $25,2F
2H BP $25,1B
1H BNP $25,2F
2H BNP $25,1B
1H BOD $25,2F
2H BOD $25,1B
1H BEV $25,2F
2H BEV $25,1B
1H PBN $2,2F
2H PBN $2,1B
1H PBNN $2,2F
2H PBNN $2,1B
1H PBZ $12,2F
2H PBZ $22,1B
1H PBNZ $32,2F
2H PBNZ $52,1B
1H PBOD $25,2F
2H PBOD $25,1B
1H PBEV $25,2F
2H PBEV $25,1B
CSN $2,$223,$11
CSN $12,$20,205
CSNN $2,$223,$11
CSNN $12,$20,205
CSZ $2,$203,$11
CSZ $12,$200,205
CSNZ $2,$203,$11
CSNZ $12,$200,205
CSP $2,$203,$11
CSP $12,$200,205
CSNP $2,$203,$11
CSNP $12,$200,205
CSOD $2,$203,$11
CSOD $12,$200,205
CSEV $2,$203,$11
CSEV $12,$200,205
ZSN $2,$223,$11
ZSN $12,$20,205
ZSNN $2,$223,$11
ZSNN $12,$20,205
ZSZ $2,$203,$11
ZSZ $12,$200,205
ZSNZ $2,$203,$11
ZSNZ $12,$200,205
ZSP $2,$203,$11
ZSP $12,$200,205
ZSNP $2,$203,$11
ZSNP $12,$200,205
ZSOD $2,$203,$11
ZSOD $12,$200,205
ZSEV $2,$203,$11
ZSEV $12,$200,205
LDB $2,$0,$11
LDB $12,$20,205
LDT $2,$0,$11
LDT $12,$20,205
LDBU $2,$0,$11
LDBU $12,$20,205
LDTU $2,$0,$11
LDTU $12,$20,205
LDW $2,$0,$11
LDW $12,$20,205
LDO $2,$0,$11
LDO $12,$20,205
LDWU $2,$0,$11
LDWU $12,$20,205
LDOU $2,$0,$11
LDOU $12,$20,205
LDVTS $2,$0,$11
LDVTS $12,$20,205
LDHT $2,$0,$11
LDHT $12,$20,205
PRELD 112,$20,205
PRELD 112,$20,$225
CSWAP $2,$0,$11
CSWAP $12,$20,205
PREGO 112,$20,205
PREGO 112,$20,$225
LDUNC $2,$0,$11
LDUNC $12,$20,205
GO $2,$0,$11
GO $12,$20,205
STB $2,$10,$151
STB $12,$20,205
STT $32,$10,$151
STT $12,$20,205
STBU $2,$10,$151
STBU $12,$20,205
STTU $32,$10,$151
STTU $12,$20,205
STW $2,$10,$151
STW $12,$220,205
STO $32,$170,$151
STO $182,$20,245
STWU $2,$10,$151
STWU $12,$220,205
STOU $32,$170,$151
STOU $182,$20,245
STSF $32,$170,$151
STSF $182,$20,245
SYNCD 112,$20,205
SYNCD 112,$20,$225
STHT $32,$170,$151
STHT $182,$20,245
PREST 112,$20,205
PREST 112,$20,$225
STCO 32,$170,$151
STCO 182,$20,245
SYNCID 112,$20,205
SYNCID 0,$20,$225
STUNC $32,$170,$151
STUNC $182,$20,245
PUSHGO $32,$170,$151
PUSHGO $182,$20,245
SET $142,$200
OR $32,$170,$151
OR $182,$20,245
AND $32,$170,$151
AND $182,$20,245
ORN $32,$170,$151
ORN $182,$20,245
ANDN $32,$170,$151
ANDN $182,$20,245
NOR $32,$170,$151
NOR $182,$20,245
NAND $32,$170,$151
NAND $182,$20,245
XOR $32,$170,$151
XOR $182,$20,245
NXOR $32,$170,$151
NXOR $182,$20,245
BDIF $32,$170,$151
BDIF $182,$20,245
MUX $32,$170,$151
MUX $182,$20,245
WDIF $32,$170,$151
WDIF $182,$20,245
SADD $32,$170,$151
SADD $182,$0,245
TDIF $32,$170,$151
TDIF $182,$20,245
MOR $32,$170,$151
MOR $182,$20,245
ODIF $32,$170,$151
ODIF $182,$20,245
MXOR $32,$17,$151
MXOR $82,$180,24
SETH $4,65535
SETH $94,0
SETH $4,255
SETH $94,1234
SETMH $94,1234
ORH $94,1234
ORMH $94,1234
SETML $94,1234
SETL $94,1234
ORML $94,1234
ORL $94,1234
INCH $94,1234
INCMH $94,1234
ANDNH $94,1234
ANDNMH $94,1234
INCML $94,1234
INCL $94,1234
ANDNML $94,1234
0H ANDNL $94,1234
JMP 0B
JMP 0F
0H POP 42,65534
RESUME 255
RESUME 0
RESUME 1
1H PUSHJ $25,2F
2H PUSHJ $25,1B
SAVE $4,0
UNSAVE 0,$234
1H GETA $25,2F
2H GETA $25,1B
SYNC 8000001
SWYM 1,2,3
SWYM 0,0,0
PUT rJ,34
PUT rJ,$134
GET $234,rJ
TRIP 0,0,0
TRIP 5,6,7
|
tactcomplabs/xbgas-binutils-gdb
| 1,027
|
gas/testsuite/gas/mmix/relax2.s
|
# PUSHJ stub border-cases: two with either or both stubs unreachable,
# local symbols, ditto non-local labels, similar with three PUSHJs.
# Note the absence of ":" on labels: because it's a symbol-character,
# it's concatenated with the parameter macro name and parsed as "\x:".
# This happens before gas deals with ":" as it usually does; not being
# part of the name when ending a label at the beginning of a line.
# (Since we're LABELS_WITHOUT_COLONS it inserts one for us, but
# that would be disabled with --gnu-syntax.)
Main SWYM
.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12
.section .text.a\x,"ax"
aa\x .space 4,0
a\x .space 65536*4,0
PUSHJ $33,aa\x
PUSHJ $22,a\x
.space 65535*4-4*\x
.section .text.b\x,"ax"
bbb\x .space 4,0
bb\x .space 4,0
b\x .space 65535*4
PUSHJ $12,bbb\x
PUSHJ $13,bb\x
PUSHJ $14,b\x
.space 65535*4-4*\x
.section .text.c\x,"ax"
c\x PUSHJ $100,ca\x
PUSHJ $101,cb\x
.space 65535*4-4*\x
.section .text.d\x,"ax"
d\x PUSHJ $99,da\x
PUSHJ $98,db\x
PUSHJ $97,dc\x
.space 65535*4-4*\x
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 1,152
|
gas/testsuite/gas/mmix/relax1.s
|
# Relaxation border-cases: just-within reach, just-out-of-reach, forward
# and backward. Have a few variable-length thingies in-between so it
# doesn't get too easy.
Main JMP l6
l0 JMP l6
l1 JMP l6
l01 JMP l6
GETA $7,nearfar1 % Within reach.
PUSHJ $191,nearfar2 % Within reach.
l2 JMP nearfar2 % Dummy.
.space 65530*4,0
BNP $72,l0 % Within reach
GETA $4,l1 % Within reach.
nearfar1 PUSHJ 5,l01 % Within reach.
nearfar2 GETA $9,l1 % Out of reach.
PUSHJ $11,l3 % Out of reach.
l4 BP $55,l3 % Within reach.
.space 65533*4,0
JMP l1 % Dummy.
l3 JMP l0 % Dummy.
BOD $88,l4 % Within reach.
BOD $88,l4 % Out of reach.
JMP l5 % Out of reach.
l6 JMP l5 % Within reach.
BZ $111,l3 % Dummy.
.space (256*256*256-3)*4,0
l5 JMP l8 % Dummy.
JMP l6 % Within reach
JMP l6 % Out of reach.
BNN $44,l9 % Out of reach.
l8 BNN $44,l9 % Within reach.
JMP l5 % Dummy.
JMP l5 % Dummy.
.space 65531*4,0
l10 JMP l5 % Dummy.
l9 JMP l11 % Dummy
l7 PUSHJ $33,l8 % Within reach.
PUSHJ $33,l8 % Out of reach.
l11 JMP l5 % Dummy.
JMP l8 % Dummy.
.space 65534*4,0
GETA $61,l11 % Within reach.
GETA $72,l11 % Out of reach.
|
tactcomplabs/xbgas-binutils-gdb
| 1,872
|
gas/testsuite/gas/arm/sp-pc-usage-t.s
|
.arch armv7-r
.syntax unified
.text
.thumb
.global foo
foo:
.align 4
@ Section A6.1.3 "Use of 0b1101 as a register specifier".
@ R13 as the source or destination register of a mov instruction.
@ only register to register transfers without shifts are supported,
@ with no flag setting
mov sp,r0
mov r0,sp
@ Using the following instructions to adjust r13 up or down by a
@ multiple of 4:
add sp,sp,#0
addw sp,sp,#0
sub sp,sp,#0
subw sp,sp,#0
add sp,sp,r0
add sp,sp,r0,lsl #1
sub sp,sp,r0
sub sp,sp,r0,lsl #1
@ R13 as a base register <Rn> of any load/store instruction.
ldr r0, [sp]
ldr r0, [pc]
ldr pc, [r0]
ldr sp, [r0]
ldr pc, [pc]
ldr sp, [sp]
ldr pc, [sp]
ldr sp, [pc]
str r0, [sp]
str sp, [r0]
str sp, [sp]
@ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction.
add r0, sp, r0
adds r0, sp, r0
add r0, sp, r0, lsl #1
adds r0, sp, r0, lsl #1
cmn sp, #0
cmn sp, r0
cmn sp, r0, lsl #1
cmp sp, #0
cmp sp, r0
cmp sp, r0, lsl #1
sub sp, #0
subs sp, #0
sub r0, sp, #0
subs r0, sp, #0
@ ADD (sp plus immediate).
add sp, #4
add r0, sp, #4
adds sp, #4
adds r0, sp, #4
addw r0, sp, #4
add sp, sp, #4
adds sp, sp, #4
addw sp, sp, #4
@ ADD (sp plus register).
add sp, r0
add r0, sp, r0
add r0, sp, r0, lsl #1
adds sp, r0
adds r0, sp, r0
adds r0, sp, r0, lsl #1
add sp, sp, r0
add sp, sp, r0, lsl #1
adds sp, sp, r0
adds sp, sp, r0, lsl #1
add sp, sp, sp
@ SUB (sp minus immediate).
sub r0, sp , #0
subs r0, sp , #0
subw r0, sp , #0
sub sp, sp , #0
subs sp, sp , #0
subw sp, sp , #0
@ SUB (sp minus register).
sub sp, #0
subs sp, #0
sub r0, sp, r0, lsl #1
subs r0, sp, r0, lsl #1
sub sp, sp, r0, lsl #1
subs sp, sp, r0, lsl #1
@ PC-related insns (equivalent to adr).
add r0, pc, #4
sub r0, pc, #4
adds r0, pc, #4
subs r0, pc, #4
addw r0, pc, #4
subw r0, pc, #4
@ nops to pad the section out to an alignment boundary.
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 4,433
|
gas/testsuite/gas/arm/vfp1.s
|
@ VFP Instructions for D variants (Double precision)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fcmped d0, d0
fcmpezd d0
fcmpd d0, d0
fcmpzd d0
@ Monadic data operations
fabsd d0, d0
fcpyd d0, d0
fnegd d0, d0
fsqrtd d0, d0
@ Dyadic data operations
faddd d0, d0, d0
fdivd d0, d0, d0
fmacd d0, d0, d0
fmscd d0, d0, d0
fmuld d0, d0, d0
fnmacd d0, d0, d0
fnmscd d0, d0, d0
fnmuld d0, d0, d0
fsubd d0, d0, d0
@ Load/store operations
fldd d0, [r0]
fstd d0, [r0]
@ Load/store multiple operations
fldmiad r0, {d0}
fldmfdd r0, {d0}
fldmiad r0!, {d0}
fldmfdd r0!, {d0}
fldmdbd r0!, {d0}
fldmead r0!, {d0}
fstmiad r0, {d0}
fstmead r0, {d0}
fstmiad r0!, {d0}
fstmead r0!, {d0}
fstmdbd r0!, {d0}
fstmfdd r0!, {d0}
@ Conversion operations
fsitod d0, s0
fuitod d0, s0
ftosid s0, d0
ftosizd s0, d0
ftouid s0, d0
ftouizd s0, d0
fcvtds d0, s0
fcvtsd s0, d0
@ ARM from VFP operations
fmrdh r0, d0
fmrdl r0, d0
@ VFP From ARM operations
fmdhr d0, r0
fmdlr d0, r0
@ Now we test that the register fields are updated correctly for
@ each class of instruction.
@ Single register operations (compare-zero):
fcmpzd d1
fcmpzd d2
fcmpzd d15
@ Two register comparison operations:
fcmpd d0, d1
fcmpd d0, d2
fcmpd d0, d15
fcmpd d1, d0
fcmpd d2, d0
fcmpd d15, d0
fcmpd d5, d12
@ Two register data operations (monadic)
fnegd d0, d1
fnegd d0, d2
fnegd d0, d15
fnegd d1, d0
fnegd d2, d0
fnegd d15, d0
fnegd d12, d5
@ Three register data operations (dyadic)
faddd d0, d0, d1
faddd d0, d0, d2
faddd d0, d0, d15
faddd d0, d1, d0
faddd d0, d2, d0
faddd d0, d15, d0
faddd d1, d0, d0
faddd d2, d0, d0
faddd d15, d0, d0
faddd d12, d9, d5
@ Conversion operations
fcvtds d0, s1
fcvtds d0, s2
fcvtds d0, s31
fcvtds d1, s0
fcvtds d2, s0
fcvtds d15, s0
fcvtsd s1, d0
fcvtsd s2, d0
fcvtsd s31, d0
fcvtsd s0, d1
fcvtsd s0, d2
fcvtsd s0, d15
@ Move to VFP from ARM
fmrdh r1, d0
fmrdh r14, d0
fmrdh r0, d1
fmrdh r0, d2
fmrdh r0, d15
fmrdl r1, d0
fmrdl r14, d0
fmrdl r0, d1
fmrdl r0, d2
fmrdl r0, d15
@ Move to ARM from VFP
fmdhr d0, r1
fmdhr d0, r14
fmdhr d1, r0
fmdhr d2, r0
fmdhr d15, r0
fmdlr d0, r1
fmdlr d0, r14
fmdlr d1, r0
fmdlr d2, r0
fmdlr d15, r0
@ Load/store operations
fldd d0, [r1]
fldd d0, [r14]
fldd d0, [r0, #0]
fldd d0, [r0, #1020]
fldd d0, [r0, #-1020]
fldd d1, [r0]
fldd d2, [r0]
fldd d15, [r0]
fstd d12, [r12, #804]
@ Load/store multiple operations
fldmiad r0, {d1}
fldmiad r0, {d2}
fldmiad r0, {d15}
fldmiad r0, {d0-d1}
fldmiad r0, {d0-d2}
fldmiad r0, {d0-d15}
fldmiad r0, {d1-d15}
fldmiad r0, {d2-d15}
fldmiad r0, {d14-d15}
fldmiad r1, {d0}
fldmiad r14, {d0}
@ Check that we assemble all the register names correctly
fcmpzd d0
fcmpzd d1
fcmpzd d2
fcmpzd d3
fcmpzd d4
fcmpzd d5
fcmpzd d6
fcmpzd d7
fcmpzd d8
fcmpzd d9
fcmpzd d10
fcmpzd d11
fcmpzd d12
fcmpzd d13
fcmpzd d14
fcmpzd d15
@ Now we check the placement of the conditional execution substring.
@ On VFP this is always at the end of the instruction.
@ Comparison operations
fcmpedeq d1, d15
fcmpezdeq d2
fcmpdeq d3, d14
fcmpzdeq d4
@ Monadic data operations
fabsdeq d5, d13
fcpydeq d6, d12
fnegdeq d7, d11
fsqrtdeq d8, d10
@ Dyadic data operations
fadddeq d9, d1, d15
fdivdeq d2, d3, d14
fmacdeq d4, d13, d12
fmscdeq d5, d6, d11
fmuldeq d7, d10, d9
fnmacdeq d8, d9, d10
fnmscdeq d7, d6, d11
fnmuldeq d5, d4, d12
fsubdeq d3, d13, d14
@ Load/store operations
flddeq d2, [r5]
fstdeq d1, [r12]
@ Load/store multiple operations
fldmiadeq r1, {d1}
fldmfddeq r2, {d2}
fldmiadeq r3!, {d3}
fldmfddeq r4!, {d4}
fldmdbdeq r5!, {d5}
fldmeadeq r6!, {d6}
fstmiadeq r7, {d15}
fstmeadeq r8, {d14}
fstmiadeq r9!, {d13}
fstmeadeq r10!, {d12}
fstmdbdeq r11!, {d11}
fstmfddeq r12!, {d10}
@ Conversion operations
fsitodeq d15, s1
fuitodeq d1, s31
ftosideq s1, d15
ftosizdeq s31, d2
ftouideq s15, d2
ftouizdeq s11, d3
fcvtdseq d1, s10
fcvtsdeq s11, d1
@ ARM from VFP operations
fmrdheq r8, d1
fmrdleq r7, d15
@ VFP From ARM operations
fmdhreq d1, r15
fmdlreq d15, r1
# Add three nop instructions to ensure that the
# output is 32-byte aligned as required for arm-aout.
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,311
|
gas/testsuite/gas/arm/armv8_3-a-simd.s
|
.text
A1:
.arm
vcadd.f32 q1,q2,q3,#90
vcadd.f32 q1,q2,q3,#270
vcadd.f16 d21,d22,d23,#90
vcadd.f16 q1,q2,q3,#90
vcadd.f32 d21,d22,d23,#90
vcmla.f32 q1,q2,q3,#0
vcmla.f32 q1,q2,q3,#90
vcmla.f32 q1,q2,q3,#180
vcmla.f32 q1,q2,q3,#270
vcmla.f16 d21,d22,d23,#90
vcmla.f16 q1,q2,q3,#90
vcmla.f32 d21,d22,d23,#90
vcmla.f16 d21,d22,d3[0],#90
vcmla.f16 d21,d22,d3[1],#90
vcmla.f16 q1,q2,d3[0],#90
vcmla.f16 q1,q2,d3[1],#90
vcmla.f32 d21,d22,d23[0],#90
vcmla.f32 q1,q2,d23[0],#90
vcmla.f16 q1,q2,d3[1],#0
vcmla.f16 q1,q2,d3[1],#180
vcmla.f16 q1,q2,d3[1],#270
vcmla.f32 q1,q2,d3[0],#0
vcmla.f32 q1,q2,d3[0],#180
vcmla.f32 q1,q2,d3[0],#270
T1:
.thumb
vcadd.f32 q1,q2,q3,#90
vcadd.f32 q1,q2,q3,#270
vcadd.f16 d21,d22,d23,#90
vcadd.f16 q1,q2,q3,#90
vcadd.f32 d21,d22,d23,#90
vcmla.f32 q1,q2,q3,#0
vcmla.f32 q1,q2,q3,#90
vcmla.f32 q1,q2,q3,#180
vcmla.f32 q1,q2,q3,#270
vcmla.f16 d21,d22,d23,#90
vcmla.f16 q1,q2,q3,#90
vcmla.f32 d21,d22,d23,#90
vcmla.f16 d21,d22,d3[0],#90
vcmla.f16 d21,d22,d3[1],#90
vcmla.f16 q1,q2,d3[0],#90
vcmla.f16 q1,q2,d3[1],#90
vcmla.f32 d21,d22,d23[0],#90
vcmla.f32 q1,q2,d23[0],#90
vcmla.f16 q1,q2,d3[1],#0
vcmla.f16 q1,q2,d3[1],#180
vcmla.f16 q1,q2,d3[1],#270
vcmla.f32 q1,q2,d3[0],#0
vcmla.f32 q1,q2,d3[0],#180
vcmla.f32 q1,q2,d3[0],#270
|
tactcomplabs/xbgas-binutils-gdb
| 1,917
|
gas/testsuite/gas/arm/mve-vstrldr-2.s
|
.syntax unified
.thumb
.macro all_vstr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
.endr
.endr
.endm
.irp data, .32, .u32, .s32, .f32
.irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 480
all_vstr vstrw\data, \imm
.endr
.endr
.irp data, .64, .u64, .s64
.irp imm, 0, 8, 16, 32, 64, 128, 256, 512, 1016, 680, 336, 960, 120
all_vstr vstrd\data, \imm
.endr
.endr
vpstete
vstrwt.32 q0, [q1, #4]
vstrwe.u32 q1, [q0, #-4]
vstrwt.s32 q2, [q2]
vstrwe.f32 q3, [q4, #-508]
vpstet
vstrdt.64 q4, [q5, #512]
vstrde.u64 q5, [q6, #1016]
vstrdt.s64 q6, [q7, #-1016]
.macro all_vldr_qq op, op1, op2, imm
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
.endm
.macro all_vldr_q0 op, imm
.irp op2, q1, q2, q4, q7
all_vldr_qq \op, q0, \op2, \imm
.endr
.endm
.macro all_vldr_q1 op, imm
.irp op2, q0, q2, q4, q7
all_vldr_qq \op, q1, \op2, \imm
.endr
.endm
.macro all_vldr_q2 op, imm
.irp op2, q0, q1, q4, q7
all_vldr_qq \op, q2, \op2, \imm
.endr
.endm
.macro all_vldr_q4 op, imm
.irp op2, q0, q1, q2, q7
all_vldr_qq \op, q4, \op2, \imm
.endr
.endm
.macro all_vldr_q7 op, imm
.irp op2, q0, q1, q2, q4
all_vldr_qq \op, q7, \op2, \imm
.endr
.endm
.macro all_vldr op, imm
all_vldr_q0 \op, \imm
all_vldr_q1 \op, \imm
all_vldr_q2 \op, \imm
all_vldr_q4 \op, \imm
all_vldr_q7 \op, \imm
.endm
.irp data, .32, .u32, .s32, .f32
.irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 480
all_vldr vldrw\data, \imm
.endr
.endr
.irp data, .64, .u64, .s64
.irp imm, 0, 8, 16, 32, 64, 128, 256, 512, 1016, 680, 336, 960, 120
all_vldr vldrd\data, \imm
.endr
.endr
vpstete
vldrwt.32 q0, [q1, #4]
vldrwe.u32 q1, [q0, #-4]
vldrwt.s32 q2, [q3]
vldrwe.f32 q3, [q4, #-508]
vpstet
vldrdt.64 q4, [q5, #512]
vldrde.u64 q5, [q6, #1016]
vldrdt.s64 q6, [q7, #-1016]
|
tactcomplabs/xbgas-binutils-gdb
| 1,276
|
gas/testsuite/gas/arm/group-reloc-ldrs.s
|
@ Tests for LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.endm
.macro ldrtest load store sym offset
ldrtest2 \load \sym \offset
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the
@ magnitude of the addend. So these should all (just) work.
ldrtest ldrd strd f "+ 255"
ldrtest ldrh strh f "+ 255"
ldrtest2 ldrsh f "+ 255"
ldrtest2 ldrsb f "+ 255"
ldrtest ldrd strd f "- 255"
ldrtest ldrh strh f "- 255"
ldrtest2 ldrsh f "- 255"
ldrtest2 ldrsb f "- 255"
@ The same as the above, but for a local symbol.
ldrtest ldrd strd localsym "+ 255"
ldrtest ldrh strh localsym "+ 255"
ldrtest2 ldrsh localsym "+ 255"
ldrtest2 ldrsb localsym "+ 255"
ldrtest ldrd strd localsym "- 255"
ldrtest ldrh strh localsym "- 255"
ldrtest2 ldrsh localsym "- 255"
ldrtest2 ldrsb localsym "- 255"
localsym:
mov r0, #0
|
tactcomplabs/xbgas-binutils-gdb
| 2,618
|
gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
|
.thumb
.syntax unified
T:
clrm {r0, r2} @ Accepts list without APSR
clrm {APSR} @ Accepts APSR alone
clrm {r3, APSR} @ Accepts core register and APSR together
clrmeq {r4} @ Accepts conditional execution
vscclrm {VPR} @ Accepts list with only VPR
vscclrm {s30, VPR} @ Accept single-precision VFP register and VPR together
vscclrm {d14, VPR} @ Likewise for double-precision VFP register
vscclrm {s1-s4, VPR} @ Accept range of single-precision VFP registers
@ and VPR together
vscclrm {d1-d4, VPR} @ Likewise for double-precision VFP registers
vscclrm {s0-s31, VPR} @ Accept all single-precision VFP registers and VPR
@ together
vscclrm {d0-d15, VPR} @ Likewise for double-precision VFP registers
vscclrmne {s3, VPR} @ Accepts conditional execution
vldr FPSCR, [r2] @ Accepts offset variant without immediate
vldr FPSCR, [r2, #8] @ Likewise but with immediate without sign
vldr FPSCR, [r2, #+8] @ Likewise but with positive sign
vldr FPSCR, [r2, #-8] @ Likewise but with negative sign
vldr FPSCR, [r2, #8]! @ Accepts pre-index variant with immediate without sign
vldr FPSCR, [r2, #+8]! @ Likewise but with positive sign
vldr FPSCR, [r2, #-8]! @ Likewise but with negative sign
vldr FPSCR, [r2], #8 @ Accepts post-index variant with immediate without sign
vldr FPSCR, [r2], #+8 @ Likewise but with positive sign
vldr FPSCR, [r2], #-8 @ Likewise but with negative sign
vldr FPSCR_nzcvqc, [r3] @ Accepts FPSCR_nzcvqc system register
vldr VPR, [r3] @ Accepts VPR system register
vldr P0, [r3] @ Accepts P0 system register
vldr FPCXTNS, [r3] @ Accepts FPCXTNS system register
vldr FPCXTS, [r3] @ Accepts FPCXTS system register
vldrge FPCXTS, [r3] @ Accepts conditional execution
vstr FPSCR, [r2] @ Accepts offset variant without immediate
vstr FPSCR, [r2, #8] @ Likewise but with immediate without sign
vstr FPSCR, [r2, #+8] @ Likewise but with positive sign
vstr FPSCR, [r2, #-8] @ Likewise but with negative sign
vstr FPSCR, [r2, #8]! @ Accepts pre-index variant with immediate without sign
vstr FPSCR, [r2, #+8]! @ Likewise but with positive sign
vstr FPSCR, [r2, #-8]! @ Likewise but with negative sign
vstr FPSCR, [r2], #8 @ Accepts post-index variant with immediate without sign
vstr FPSCR, [r2], #+8 @ Likewise but with positive sign
vstr FPSCR, [r2], #-8 @ Likewise but with negative sign
vstr FPSCR_nzcvqc, [r3] @ Accepts FPSCR_nzcvqc system register
vstr VPR, [r3] @ Accepts VPR system register
vstr P0, [r3] @ Accepts P0 system register
vstr FPCXTNS, [r3] @ Accepts FPCXTNS system register
vstr FPCXTS, [r3] @ Accepts FPCXTS system register
vstrge FPCXTS, [r3] @ Accepts conditional execution
|
tactcomplabs/xbgas-binutils-gdb
| 1,112
|
gas/testsuite/gas/arm/group-reloc-ldr.s
|
@ Tests for LDR group relocations.
.text
.macro ldrtest load store sym offset
\load r0, [r0, #:pc_g0:(\sym \offset)]
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
\store r0, [r0, #:pc_g0:(\sym \offset)]
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
@ So these should all (just) work.
ldrtest ldr str f "+ 4095"
ldrtest ldrb strb f "+ 4095"
ldrtest ldr str f "- 4095"
ldrtest ldrb strb f "- 4095"
@ The same as the above, but for a local symbol. These should not be
@ resolved by the assembler but instead left to the linker.
ldrtest ldr str localsym "+ 4095"
ldrtest ldrb strb localsym "+ 4095"
ldrtest ldr str localsym "- 4095"
ldrtest ldrb strb localsym "- 4095"
localsym:
mov r0, #0
|
tactcomplabs/xbgas-binutils-gdb
| 3,847
|
gas/testsuite/gas/arm/unpredictable.s
|
.text
.global upredictable
unpredictable:
.word 0x004f00b1 @ strheq r0, [pc], #-1
.word 0x005fffff @ ldrsheq pc, [pc], #-255
.word 0x007fffff @ ldrsheq pc, [pc, #-255]!
.word 0x00cf00b0 @ strheq r0, [pc], #0
.word 0x00df00b0 @ ldrheq r0, [pc], #0
.word 0x00dfffff @ ldrsheq pc, [pc], #255
.word 0x00ffffff @ ldrsheq pc, [pc, #255]
.word 0x0000f0b0 @ strheq pc, [r0], -r0
.word 0x000ff0be @ strheq pc, [pc], -lr
.word 0xe16fff10 @ clz pc, r0
.word 0xe16f0f1f @ clz r0, r15
.word 0xe99f0001 @ ldmib r15, { r0 }
.word 0xe9910000 @ ldmib r1, { }
.word 0xe89f0002 @ ldmia pc, { r1 }
.word 0xe93f0004 @ ldmdb r15!, { r2 }
.word 0xe83f0008 @ ldmda pc!, { r3 }
.word 0xe7d0f001 @ ldrb pc, [r0, r1]
.word 0xe6f0f001 @ ldrbt pc, [r0], r1
.word 0xe190f0b1 @ ldrh pc, [r0, r1]
.word 0xe190f0d1 @ ldrsb pc, [r0, r1]
.word 0xe010f0d0 @ ldrsb pc, [r0], -r0
.word 0xe190f0f1 @ ldrsh pc, [r0, r1]
.word 0xe6b0f001 @ ldrt pc, [r0], r1
.word 0xe020f291 @ mla r0, r1, r2, pc
.word 0xe0202f91 @ mla r0, r1, pc, r2
.word 0xe020219f @ mla r0, pc, r1, r2
.word 0xe02f2190 @ mla pc, r0, r1, r2
.word 0xe10ff000 @ mrs pc, cpsr
.word 0xe0000f91 @ mul r0, r1, pc
.word 0xe001009f @ mul r0, pc, r1
.word 0xe00f0091 @ mul pc, r1, r0
.word 0xe0e21f93 @ smlal r1, r2, r3, pc
.word 0xe0e2149f @ smlal r1, r2, pc, r4
.word 0xe0ef1493 @ smlal r1, pc, r3, r4
.word 0xe0e2f493 @ smlal pc, r2, r3, r4
.word 0xe0e11493 @ smlal r1, r1, r3, r4
.word 0xe0c21f93 @ smull r1, r2, r3, pc
.word 0xe0c2149f @ smull r1, r2, pc, r4
.word 0xe0cf1493 @ smull r1, pc, r3, r4
.word 0xe0c2f493 @ smull pc, r2, r3, r4
.word 0xe0c11493 @ smull r1, r1, r3, r4
.word 0xe98f0004 @ stmib r15, { r2 }
.word 0xe88f0008 @ stmia r15, { r3 }
.word 0xe92f0010 @ stmdb r15!, { r4 }
.word 0xe82f0020 @ stmda r15!, { r5 }
.word 0xe180f0b1 @ strh pc, [r0, r1]
.word 0xe103f092 @ swp r15, r2, [r3]
.word 0xe103109f @ swp r1, r15, [r3]
.word 0xe10f1092 @ swp r1, r2, [r15]
.word 0xe1031093 @ swp r1, r3, [r3]
.word 0xe1033092 @ swp r3, r2, [r3]
.word 0xe143f092 @ swpb r15, r2, [r3]
.word 0xe143109f @ swpb r1, r15, [r3]
.word 0xe14f1092 @ swpb r1, r2, [r15]
.word 0xe1431093 @ swpb r1, r3, [r3]
.word 0xe1433092 @ swpb r3, r2, [r3]
.word 0xe0a21f93 @ umlal r1, r2, r3, r15
.word 0xe0a2149f @ umlal r1, r2, r15, r4
.word 0xe0af1493 @ umlal r1, r15, r3, r4
.word 0xe0a2f493 @ umlal r15, r2, r3, r4
.word 0xe0a11493 @ umlal r1, r1, r3, r4
.word 0xe0821f93 @ umull r1, r2, r3, r15
.word 0xe082149f @ umull r1, r2, r15, r4
.word 0xe08f1493 @ umull r1, r15, r3, r4
.word 0xe082f493 @ umull r15, r2, r3, r4
.word 0xe0811493 @ umull r1, r1, r3, r4
nop @ Marker to indicated end of unpredictable insns.
|
tactcomplabs/xbgas-binutils-gdb
| 1,975
|
gas/testsuite/gas/arm/armv8-ar-bad.s
|
.syntax unified
.text
// SWP
.arm
swp r0, r1, [r2]
// deprecated MCRs
mcr p15, 0, r0, c7, c5, 4
mcr p15, 0, r1, c7, c10, 4
mcr p15, 0, r2, c7, c10, 5
mrc p14, 6, r1, c0, c0, 0
mrc p14, 6, r0, c1, c0, 0
// deprecated SETEND
setend be
.thumb
setend le
// HLT A32
.arm
hlt 0x10000
hltne 0x1
// HLT T32
.thumb
hlt 64
it ne
hltne 0
// STL A32
.arm
stlb pc, [r0]
stlb r0, [pc]
stlh pc, [r0]
stlh r0, [pc]
stl pc, [r0]
stl r0, [pc]
stlexb r1, pc, [r0]
stlexb r1, r0, [pc]
stlexb pc, r0, [r1]
stlexb r0, r0, [r1]
stlexb r0, r1, [r0]
stlexh r1, pc, [r0]
stlexh r1, r0, [pc]
stlexh pc, r0, [r1]
stlexh r0, r0, [r1]
stlexh r0, r1, [r0]
stlex r1, pc, [r0]
stlex r1, r0, [pc]
stlex pc, r0, [r1]
stlex r0, r0, [r1]
stlex r0, r1, [r0]
stlexd r1, lr, [r0]
stlexd r1, r0, [pc]
stlexd pc, r0, [r1]
stlexd r0, r0, [r1]
stlexd r0, r2, [r0]
stlexd r0, r1, [r2]
// STL T32
.thumb
stlb pc, [r0]
stlb r0, [pc]
stlh pc, [r0]
stlh r0, [pc]
stl pc, [r0]
stl r0, [pc]
stlexb r1, pc, [r0]
stlexb r1, r0, [pc]
stlexb pc, r0, [r1]
stlexb r0, r0, [r1]
stlexb r0, r1, [r0]
stlexh r1, pc, [r0]
stlexh r1, r0, [pc]
stlexh pc, r0, [r1]
stlexh r0, r0, [r1]
stlexh r0, r1, [r0]
stlex r1, pc, [r0]
stlex r1, r0, [pc]
stlex pc, r0, [r1]
stlex r0, r0, [r1]
stlex r0, r1, [r0]
stlexd r1, lr, [r0]
stlexd r1, r0, [pc]
stlexd pc, r0, [r1]
stlexd r0, r0, [r1]
stlexd r0, r2, [r0]
stlexd r0, r1, [r2]
// LDA A32
.arm
ldab pc, [r0]
ldab r0, [pc]
ldah pc, [r0]
ldah r0, [pc]
lda pc, [r0]
lda r0, [pc]
ldaexb pc, [r0]
ldaexb r0, [pc]
ldaexh pc, [r0]
ldaexh r0, [pc]
ldaex pc, [r0]
ldaex r0, [pc]
ldaexd lr, [r0]
ldaexd r0, [pc]
ldaexd r1, [r2]
// LDA T32
.thumb
ldab pc, [r0]
ldab r0, [pc]
ldah pc, [r0]
ldah r0, [pc]
lda pc, [r0]
lda r0, [pc]
ldaexb pc, [r0]
ldaexb r0, [pc]
ldaexh pc, [r0]
ldaexh r0, [pc]
ldaex pc, [r0]
ldaex r0, [pc]
ldaexd r0, pc, [r0]
ldaexd pc, r0, [r0]
ldaexd r1, r0, [pc]
|
tactcomplabs/xbgas-binutils-gdb
| 7,483
|
gas/testsuite/gas/arm/neon-const.s
|
@ test floating-point constant parsing.
.arm
.text
.syntax unified
vmov.f32 q0, 0.0
vmov.f32 q0, 2.0
vmov.f32 q0, 4.0
vmov.f32 q0, 8.0
vmov.f32 q0, 16.0
vmov.f32 q0, 0.125
vmov.f32 q0, 0.25
vmov.f32 q0, 0.5
vmov.f32 q0, 1.0
vmov.f32 q0, 2.125
vmov.f32 q0, 4.25
vmov.f32 q0, 8.5
vmov.f32 q0, 17.0
vmov.f32 q0, 0.1328125
vmov.f32 q0, 0.265625
vmov.f32 q0, 0.53125
vmov.f32 q0, 1.0625
vmov.f32 q0, 2.25
vmov.f32 q0, 4.5
vmov.f32 q0, 9.0
vmov.f32 q0, 18.0
vmov.f32 q0, 0.140625
vmov.f32 q0, 0.28125
vmov.f32 q0, 0.5625
vmov.f32 q0, 1.125
vmov.f32 q0, 2.375
vmov.f32 q0, 4.75
vmov.f32 q0, 9.5
vmov.f32 q0, 19.0
vmov.f32 q0, 0.1484375
vmov.f32 q0, 0.296875
vmov.f32 q0, 0.59375
vmov.f32 q0, 1.1875
vmov.f32 q0, 2.5
vmov.f32 q0, 5.0
vmov.f32 q0, 10.0
vmov.f32 q0, 20.0
vmov.f32 q0, 0.15625
vmov.f32 q0, 0.3125
vmov.f32 q0, 0.625
vmov.f32 q0, 1.25
vmov.f32 q0, 2.625
vmov.f32 q0, 5.25
vmov.f32 q0, 10.5
vmov.f32 q0, 21.0
vmov.f32 q0, 0.1640625
vmov.f32 q0, 0.328125
vmov.f32 q0, 0.65625
vmov.f32 q0, 1.3125
vmov.f32 q0, 2.75
vmov.f32 q0, 5.5
vmov.f32 q0, 11.0
vmov.f32 q0, 22.0
vmov.f32 q0, 0.171875
vmov.f32 q0, 0.34375
vmov.f32 q0, 0.6875
vmov.f32 q0, 1.375
vmov.f32 q0, 2.875
vmov.f32 q0, 5.75
vmov.f32 q0, 11.5
vmov.f32 q0, 23.0
vmov.f32 q0, 0.1796875
vmov.f32 q0, 0.359375
vmov.f32 q0, 0.71875
vmov.f32 q0, 1.4375
vmov.f32 q0, 3.0
vmov.f32 q0, 6.0
vmov.f32 q0, 12.0
vmov.f32 q0, 24.0
vmov.f32 q0, 0.1875
vmov.f32 q0, 0.375
vmov.f32 q0, 0.75
vmov.f32 q0, 1.5
vmov.f32 q0, 3.125
vmov.f32 q0, 6.25
vmov.f32 q0, 12.5
vmov.f32 q0, 25.0
vmov.f32 q0, 0.1953125
vmov.f32 q0, 0.390625
vmov.f32 q0, 0.78125
vmov.f32 q0, 1.5625
vmov.f32 q0, 3.25
vmov.f32 q0, 6.5
vmov.f32 q0, 13.0
vmov.f32 q0, 26.0
vmov.f32 q0, 0.203125
vmov.f32 q0, 0.40625
vmov.f32 q0, 0.8125
vmov.f32 q0, 1.625
vmov.f32 q0, 3.375
vmov.f32 q0, 6.75
vmov.f32 q0, 13.5
vmov.f32 q0, 27.0
vmov.f32 q0, 0.2109375
vmov.f32 q0, 0.421875
vmov.f32 q0, 0.84375
vmov.f32 q0, 1.6875
vmov.f32 q0, 3.5
vmov.f32 q0, 7.0
vmov.f32 q0, 14.0
vmov.f32 q0, 28.0
vmov.f32 q0, 0.21875
vmov.f32 q0, 0.4375
vmov.f32 q0, 0.875
vmov.f32 q0, 1.75
vmov.f32 q0, 3.625
vmov.f32 q0, 7.25
vmov.f32 q0, 14.5
vmov.f32 q0, 29.0
vmov.f32 q0, 0.2265625
vmov.f32 q0, 0.453125
vmov.f32 q0, 0.90625
vmov.f32 q0, 1.8125
vmov.f32 q0, 3.75
vmov.f32 q0, 7.5
vmov.f32 q0, 15.0
vmov.f32 q0, 30.0
vmov.f32 q0, 0.234375
vmov.f32 q0, 0.46875
vmov.f32 q0, 0.9375
vmov.f32 q0, 1.875
vmov.f32 q0, 3.875
vmov.f32 q0, 7.75
vmov.f32 q0, 15.5
vmov.f32 q0, 31.0
vmov.f32 q0, 0.2421875
vmov.f32 q0, 0.484375
vmov.f32 q0, 0.96875
vmov.f32 q0, 1.9375
vmov.f32 q0, -0.0
vmov.f32 q0, -2.0
vmov.f32 q0, -4.0
vmov.f32 q0, -8.0
vmov.f32 q0, -16.0
vmov.f32 q0, -0.125
vmov.f32 q0, -0.25
vmov.f32 q0, -0.5
vmov.f32 q0, -1.0
vmov.f32 q0, -2.125
vmov.f32 q0, -4.25
vmov.f32 q0, -8.5
vmov.f32 q0, -17.0
vmov.f32 q0, -0.1328125
vmov.f32 q0, -0.265625
vmov.f32 q0, -0.53125
vmov.f32 q0, -1.0625
vmov.f32 q0, -2.25
vmov.f32 q0, -4.5
vmov.f32 q0, -9.0
vmov.f32 q0, -18.0
vmov.f32 q0, -0.140625
vmov.f32 q0, -0.28125
vmov.f32 q0, -0.5625
vmov.f32 q0, -1.125
vmov.f32 q0, -2.375
vmov.f32 q0, -4.75
vmov.f32 q0, -9.5
vmov.f32 q0, -19.0
vmov.f32 q0, -0.1484375
vmov.f32 q0, -0.296875
vmov.f32 q0, -0.59375
vmov.f32 q0, -1.1875
vmov.f32 q0, -2.5
vmov.f32 q0, -5.0
vmov.f32 q0, -10.0
vmov.f32 q0, -20.0
vmov.f32 q0, -0.15625
vmov.f32 q0, -0.3125
vmov.f32 q0, -0.625
vmov.f32 q0, -1.25
vmov.f32 q0, -2.625
vmov.f32 q0, -5.25
vmov.f32 q0, -10.5
vmov.f32 q0, -21.0
vmov.f32 q0, -0.1640625
vmov.f32 q0, -0.328125
vmov.f32 q0, -0.65625
vmov.f32 q0, -1.3125
vmov.f32 q0, -2.75
vmov.f32 q0, -5.5
vmov.f32 q0, -11.0
vmov.f32 q0, -22.0
vmov.f32 q0, -0.171875
vmov.f32 q0, -0.34375
vmov.f32 q0, -0.6875
vmov.f32 q0, -1.375
vmov.f32 q0, -2.875
vmov.f32 q0, -5.75
vmov.f32 q0, -11.5
vmov.f32 q0, -23.0
vmov.f32 q0, -0.1796875
vmov.f32 q0, -0.359375
vmov.f32 q0, -0.71875
vmov.f32 q0, -1.4375
vmov.f32 q0, -3.0
vmov.f32 q0, -6.0
vmov.f32 q0, -12.0
vmov.f32 q0, -24.0
vmov.f32 q0, -0.1875
vmov.f32 q0, -0.375
vmov.f32 q0, -0.75
vmov.f32 q0, -1.5
vmov.f32 q0, -3.125
vmov.f32 q0, -6.25
vmov.f32 q0, -12.5
vmov.f32 q0, -25.0
vmov.f32 q0, -0.1953125
vmov.f32 q0, -0.390625
vmov.f32 q0, -0.78125
vmov.f32 q0, -1.5625
vmov.f32 q0, -3.25
vmov.f32 q0, -6.5
vmov.f32 q0, -13.0
vmov.f32 q0, -26.0
vmov.f32 q0, -0.203125
vmov.f32 q0, -0.40625
vmov.f32 q0, -0.8125
vmov.f32 q0, -1.625
vmov.f32 q0, -3.375
vmov.f32 q0, -6.75
vmov.f32 q0, -13.5
vmov.f32 q0, -27.0
vmov.f32 q0, -0.2109375
vmov.f32 q0, -0.421875
vmov.f32 q0, -0.84375
vmov.f32 q0, -1.6875
vmov.f32 q0, -3.5
vmov.f32 q0, -7.0
vmov.f32 q0, -14.0
vmov.f32 q0, -28.0
vmov.f32 q0, -0.21875
vmov.f32 q0, -0.4375
vmov.f32 q0, -0.875
vmov.f32 q0, -1.75
vmov.f32 q0, -3.625
vmov.f32 q0, -7.25
vmov.f32 q0, -14.5
vmov.f32 q0, -29.0
vmov.f32 q0, -0.2265625
vmov.f32 q0, -0.453125
vmov.f32 q0, -0.90625
vmov.f32 q0, -1.8125
vmov.f32 q0, -3.75
vmov.f32 q0, -7.5
vmov.f32 q0, -15.0
vmov.f32 q0, -30.0
vmov.f32 q0, -0.234375
vmov.f32 q0, -0.46875
vmov.f32 q0, -0.9375
vmov.f32 q0, -1.875
vmov.f32 q0, -3.875
vmov.f32 q0, -7.75
vmov.f32 q0, -15.5
vmov.f32 q0, -31.0
vmov.f32 q0, -0.2421875
vmov.f32 q0, -0.484375
vmov.f32 q0, -0.96875
vmov.f32 q0, -1.9375
vmov.i64 d9, #0xffffffffffffffff
|
tactcomplabs/xbgas-binutils-gdb
| 2,786
|
gas/testsuite/gas/arm/bfloat16-bad.s
|
.syntax unified
// Test warnings about type specifier being incorrect.
vdot.b16 d0, d0, d0
vmmla q0.b16, q0, q0
vdot.bf32 d0, d0, d0[1]
vdot d0.bf32, d0, d0
vdot d0.bf32, d0.bf16, d0.bf16
// Test conditions are not allowed in ARM.
vdotne d0, d0, d0
vdotne d0, d0, d0[1]
vmmlane q0, q0, q0
vfmatne.bf16 q0, d0, d0
vfmatne.bf16 q0, d0, d0[0]
vfmabne.bf16 q0, d0, d0
vfmabne.bf16 q0, d0, d0[0]
vcvtne.bf16.f32 d0, q0
// d register out of range
vdot d32, d0, d0
vdot d0, d32, d0
vdot d0, d0, d32
vdot d32, d0, d0[0]
vdot d0, d32, d0[0]
vdot d0, d0, d16[0]
vcvtne.bf16.f32 d32, q0
// q register out of range
vdot q16, q0, q0
vdot q0, q16, q0
vdot q0, q0, q16
vdot q16, q0, d0[0]
vdot q0, q16, d0[0]
vmmla q16, q0, q0
vmmla q0, q16, q0
vmmla q0, q0, q16
vfmab.bf16 q16, d0, d0
vfmab.bf16 q16, d0, d0[0]
vfmab.bf16 q0, q32, d0
vfmab.bf16 q0, q32, d0[0]
vfmab.bf16 q0, q0, d8[0]
vfmat.bf16 q16, d0, d0
vfmat.bf16 q16, d0, d0[0]
vfmat.bf16 q0, q32, d0
vfmat.bf16 q0, q32, d0[0]
vfmat.bf16 q0, q0, d8[0]
vcvt.bf16.f32 d0, q16
// Incorrect set of arguments
vdot q0, q0, d5
vdot q0, d5, q0
vdot d5, q0, q0
vdot q0, d5, q0[0]
vdot d5, q0, q0[0]
vmmla q0, q0, d5
vmmla q0, d5, q0
vmmla d5, q0, q0
vfmab.bf16 d0, q0, d0
vfmab.bf16 d0, q0, d0[0]
vfmat.bf16 d0, q0, d0
vfmat.bf16 d0, q0, d0[0]
vcvt.bf16.f32 q0, d0
// vdot index out of range
vdot q0, q0, d0[2]
// vfma<bt> index out of range
vfmab.bf16 q0, d0, d0[4]
vfmat.bf16 q0, d0, d0[4]
// Non neon encodings (this file gets assembled more than once but with
// different flags, providing different error messages each time).
// Type specifier warnings
.macro conversion_type_specifier_check insn, dest, source
\insn\().b16.f32 \dest, \source
\insn\().bf32.f32 \dest, \source
\insn \dest\().b16, \source\().f32
\insn \dest\().bf32, \source\().f32
\insn \dest\().f32, \source\().bf16
.endm
conversion_type_specifier_check vcvtb, s0, s0
conversion_type_specifier_check vcvtt, s0, s0
conversion_type_specifier_check vcvt, d0, q0
// Conditions allowed (and checked in the "Valid" source file).
// Incorrect set of operands & registers out of range
.macro bad_args insn
\insn\().bf16.f32 s0, s0, #0
\insn\().bf16.f32 s0, s0, #1
\insn\().bf16.f32 d0, s0
\insn\().bf16.f32 s0
\insn\().bf16.f32 s0, s0, s0, s0
\insn\().bf16.f32 s0, s0, s0
\insn\().bf16.f32 s0, s32
\insn\().bf16.f32 s32, s32
.endm
bad_args vcvtt
bad_args vcvtb
// Allowed in thumb mode but not allowed in arm mode.
it ne
vcvtne.bf16.f32 d0, q0
// Ensure these instructions are not allowed to have a conditional suffix.
ittt ne
vdotne.bf16 d0, d20, d11
vdotne.bf16 d0, d20, d11[1]
vmmlane.bf16 q0, q0, q0
// Ensure we are warned these instructions are UNPREDICTABLE in an IT block in
// thumb.
ittt ne
vdot.bf16 d0, d20, d11
vdot.bf16 d0, d20, d11[1]
vmmla.bf16 q0, q0, q0
|
tactcomplabs/xbgas-binutils-gdb
| 2,628
|
gas/testsuite/gas/arm/thumb.s
|
.text
.code 16
.foo:
lsl r2, r1, #3
lsr r3, r4, #31
wibble/data:
asr r7, r0, #5
lsl r1, r2, #0
lsr r3, r4, #0
asr r4, r5, #0
lsr r6, r7, #32
asr r0, r1, #32
add r1, r2, r3
add r2, r4, #2
sub r3, r5, r7
sub r2, r4, #7
mov r4, #255
cmp r3, #250
add r6, #123
sub r5, #128
and r3, r5
eor r4, r6
lsl r1, r0
lsr r2, r3
asr r4, r6
adc r5, r7
sbc r0, r4
ror r1, r4
tst r2, r5
neg r1, r1
cmp r2, r3
cmn r1, r4
orr r0, r3
mul r4, r5
bic r5, r7
mvn r5, r5
add r1, r13
add r12, r2
add r9, r9
cmp r1, r14
cmp r8, r0
cmp r12, r14
mov r0, r9
mov r9, r4
mov r8, r8
bx r7
bx r8
.align 0
bx pc
ldr r3, [pc, #128]
ldr r4, bar
str r0, [r1, r2]
strb r1, [r2, r4]
ldr r5, [r6, r7]
ldrb r2, [r4, r5]
.align 0
bar:
strh r1, [r2, r3]
ldrh r3, [r4, r0]
ldsb r1, [r6, r7]
ldsh r2, [r0, r5]
str r3, [r3, #124]
ldr r1, [r4, #124]
ldr r5, [r5]
strb r1, [r5, #31]
strb r1, [r4, #5]
strb r2, [r6]
strh r4, [r5, #62]
ldrh r5, [r0, #4]
ldrh r3, [r2]
str r3, [r13, #1020]
ldr r1, [r13, #44]
ldr r2, [r13]
add r7, r15, #1020
add r4, r13, #512
add r13, #268
add r13, #-104
sub r13, #268
sub r13, #-108
push {r0, r1, r2, r4}
push {r0, r3-r7, lr}
pop {r3, r4, r7}
pop {r0-r7, r15}
stmia r3!, {r0, r1, r4-r7}
ldmia r0!, {r1-r7}
beq bar
bne bar
bcs bar
bcc bar
bmi bar
bpl bar
bvs bar
bvc bar
bhi bar
bls bar
bge bar
bgt bar
blt bar
bgt bar
ble bar
bhi bar
blo bar
bul bar
bal bar
close:
lsl r4, r5, #near - close
near:
add r2, r3, #near - close
add sp, sp, #127 << 2
sub sp, sp, #127 << 2
add r0, sp, #255 << 2
add r0, pc, #255 << 2
add sp, sp, #bar - .foo
sub sp, sp, #bar - .foo
add r0, sp, #bar - .foo
add r0, pc, #bar - .foo
add r1, #bar - .foo
mov r6, #bar - .foo
cmp r7, #bar - .foo
nop
nop
.arm
.localbar:
b .localbar
b .back
bl .localbar
bl .back
bx r0
swi 0x123456
.thumb
@ The following will be disassembled incorrectly if we do not
@ have a Thumb symbol defined before the first Thumb instruction:
morethumb:
adr r0, forwardonly
b .foo
b .back
bl .foo
bl .back
bx r0
swi 0xff
.align 0
forwardonly:
beq .back
bne .back
bcs .back
bcc .back
bmi .back
bpl .back
bvs .back
bvc .back
bhi .back
bls .back
bge .back
bgt .back
blt .back
bgt .back
ble .back
bhi .back
blo .back
bul .back
.back:
bl .local
.space (1 << 11) @ leave space to force long offsets
.local:
bl .back
ldr r0, .target
ldr r0, .target
ldr r0, [pc, #4]
ldr r0, [pc, #4]
.target:
baz:
mov r0, r1
nop
adr r0, pr18541
adr r0, pr18541
adr r0, pr18541
nop
.align
.global pr18541
pr18541:
.long 0
|
tactcomplabs/xbgas-binutils-gdb
| 2,844
|
gas/testsuite/gas/arm/arch7em.s
|
# Instructions included in v7E-M architecture over v7-M.
.text
.thumb
.syntax unified
pkh:
pkhbt r0, r0, r0
pkhbt r9, r0, r0
pkhbt r0, r9, r0
pkhbt r0, r0, r9
pkhbt r0, r0, r0, lsl #0x14
pkhbt r0, r0, r0, lsl #3
pkhtb r1, r2, r3
pkhtb r1, r2, r3, asr #0x11
qadd:
qadd r1, r2, r3
qadd16 r1, r2, r3
qadd8 r1, r2, r3
qasx r1, r2, r3
qaddsubx r1, r2, r3
qdadd r1, r2, r3
qdsub r1, r2, r3
qsub r1, r2, r3
qsub16 r1, r2, r3
qsub8 r1, r2, r3
qsax r1, r2, r3
qsubaddx r1, r2, r3
sadd16 r1, r2, r3
sadd8 r1, r2, r3
sasx r1, r2, r3
saddsubx r1, r2, r3
ssub16 r1, r2, r3
ssub8 r1, r2, r3
ssax r1, r2, r3
ssubaddx r1, r2, r3
shadd16 r1, r2, r3
shadd8 r1, r2, r3
shasx r1, r2, r3
shaddsubx r1, r2, r3
shsub16 r1, r2, r3
shsub8 r1, r2, r3
shsax r1, r2, r3
shsubaddx r1, r2, r3
uadd16 r1, r2, r3
uadd8 r1, r2, r3
uasx r1, r2, r3
uaddsubx r1, r2, r3
usub16 r1, r2, r3
usub8 r1, r2, r3
usax r1, r2, r3
usubaddx r1, r2, r3
uhadd16 r1, r2, r3
uhadd8 r1, r2, r3
uhasx r1, r2, r3
uhaddsubx r1, r2, r3
uhsub16 r1, r2, r3
uhsub8 r1, r2, r3
uhsax r1, r2, r3
uhsubaddx r1, r2, r3
uqadd16 r1, r2, r3
uqadd8 r1, r2, r3
uqasx r1, r2, r3
uqaddsubx r1, r2, r3
uqsub16 r1, r2, r3
uqsub8 r1, r2, r3
uqsax r1, r2, r3
uqsubaddx r1, r2, r3
sel r1, r2, r3
smla:
smlabb r0, r0, r0, r0
smlabb r9, r0, r0, r0
smlabb r0, r9, r0, r0
smlabb r0, r0, r9, r0
smlabb r0, r0, r0, r9
smlatb r0, r0, r0, r0
smlabt r0, r0, r0, r0
smlatt r0, r0, r0, r0
smlawb r0, r0, r0, r0
smlawt r0, r0, r0, r0
smlad r0, r0, r0, r0
smladx r0, r0, r0, r0
smlsd r0, r0, r0, r0
smlsdx r0, r0, r0, r0
smmla r0, r0, r0, r0
smmlar r0, r0, r0, r0
smmls r0, r0, r0, r0
smmlsr r0, r0, r0, r0
usada8 r0, r0, r0, r0
smlal:
smlalbb r0, r0, r0, r0
smlalbb r9, r0, r0, r0
smlalbb r0, r9, r0, r0
smlalbb r0, r0, r9, r0
smlalbb r0, r0, r0, r9
smlaltb r0, r0, r0, r0
smlalbt r0, r0, r0, r0
smlaltt r0, r0, r0, r0
smlald r0, r0, r0, r0
smlaldx r0, r0, r0, r0
smlsld r0, r0, r0, r0
smlsldx r0, r0, r0, r0
umaal r0, r0, r0, r0
smul:
smulbb r0, r0, r0
smulbb r9, r0, r0
smulbb r0, r9, r0
smulbb r0, r0, r9
smultb r0, r0, r0
smulbt r0, r0, r0
smultt r0, r0, r0
smulwb r0, r0, r0
smulwt r0, r0, r0
smmul r0, r0, r0
smmulr r0, r0, r0
smuad r0, r0, r0
smuadx r0, r0, r0
smusd r0, r0, r0
smusdx r0, r0, r0
usad8 r0, r0, r0
sat:
ssat16 r0, #1, r0
ssat16 r9, #1, r0
ssat16 r0, #10, r0
ssat16 r0, #1, r9
usat16 r0, #0, r0
usat16 r9, #0, r0
usat16 r0, #9, r0
usat16 r0, #0, r9
xt:
sxtb16 r1, r2
sxtb16 r8, r9
uxtb16 r1, r2
uxtb16 r8, r9
xta:
sxtab r0, r0, r0
sxtab r0, r0, r0, ror #0
sxtab r9, r0, r0, ror #8
sxtab r0, r9, r0, ror #16
sxtab r0, r0, r9, ror #24
sxtab16 r1, r2, r3
sxtah r1, r2, r3
uxtab r1, r2, r3
uxtab16 r1, r2, r3
uxtah r1, r2, r3
|
tactcomplabs/xbgas-binutils-gdb
| 5,464
|
gas/testsuite/gas/arm/mve-vstld-bad.s
|
.syntax unified
.thumb
vst20.8 {q0, q2}, [r0]
vst20.8 {q0, q1, q2}, [r0]
vst20.8 {q0}, [r0]
vst20.8 {q0, q1}, [pc]
vst20.8 {q0, q1}, [pc]!
vst20.8 {q0, q1}, [sp]!
vst20.8 {q3, q2}, [r0]
vst20.64 {q0, q1}, [r0]
vst21.8 {q0, q2}, [r0]
vst21.8 {q0, q1, q2}, [r0]
vst21.8 {q0}, [r0]
vst21.8 {q0, q1}, [pc]
vst21.8 {q0, q1}, [pc]!
vst21.8 {q0, q1}, [sp]!
vst21.8 {q3, q2}, [r0]
vst21.64 {q0, q1}, [r0]
vst40.8 {q0, q2, q3, q4}, [r0]
vst40.8 {q0, q1, q3, q4}, [r0]
vst40.8 {q0, q1, q2, q4}, [r0]
vst40.8 {q3, q1, q2, q3}, [r0]
vst40.8 {q0, q1, q2, q3, q4}, [r0]
vst40.8 {q0, q1, q2}, [r0]
vst40.8 {q0, q1}, [r0]
vst40.8 {q0}, [r0]
vst40.8 {q0, q1, q2, q3}, [pc]
vst40.8 {q0, q1, q2, q3}, [pc]!
vst40.8 {q0, q1, q2, q3}, [sp]!
vst40.64 {q0, q1, q2, q3}, [r0]
vst41.8 {q0, q2, q3, q4}, [r0]
vst41.8 {q0, q1, q3, q4}, [r0]
vst41.8 {q0, q1, q2, q4}, [r0]
vst41.8 {q3, q1, q2, q3}, [r0]
vst41.8 {q0, q1, q2, q3, q4}, [r0]
vst41.8 {q0, q1, q2}, [r0]
vst41.8 {q0, q1}, [r0]
vst41.8 {q0}, [r0]
vst41.8 {q0, q1, q2, q3}, [pc]
vst41.8 {q0, q1, q2, q3}, [pc]!
vst41.8 {q0, q1, q2, q3}, [sp]!
vst41.64 {q0, q1, q2, q3}, [r0]
vst42.8 {q0, q2, q3, q4}, [r0]
vst42.8 {q0, q1, q3, q4}, [r0]
vst42.8 {q0, q1, q2, q4}, [r0]
vst42.8 {q3, q1, q2, q3}, [r0]
vst42.8 {q0, q1, q2, q3, q4}, [r0]
vst42.8 {q0, q1, q2}, [r0]
vst42.8 {q0, q1}, [r0]
vst42.8 {q0}, [r0]
vst42.8 {q0, q1, q2, q3}, [pc]
vst42.8 {q0, q1, q2, q3}, [pc]!
vst42.8 {q0, q1, q2, q3}, [sp]!
vst42.64 {q0, q1, q2, q3}, [r0]
vst43.8 {q0, q2, q3, q4}, [r0]
vst43.8 {q0, q1, q3, q4}, [r0]
vst43.8 {q0, q1, q2, q4}, [r0]
vst43.8 {q3, q1, q2, q3}, [r0]
vst43.8 {q0, q1, q2, q3, q4}, [r0]
vst43.8 {q0, q1, q2}, [r0]
vst43.8 {q0, q1}, [r0]
vst43.8 {q0}, [r0]
vst43.8 {q0, q1, q2, q3}, [pc]
vst43.8 {q0, q1, q2, q3}, [pc]!
vst43.8 {q0, q1, q2, q3}, [sp]!
vst43.64 {q0, q1, q2, q3}, [r0]
vst1.8 {q0, q1}, [r0]
vst2.8 {q0, q1}, [r0]
vst3.8 {q0, q1}, [r0]
vst4.8 {q0, q1}, [r0]
vst23.32 {q0, q1}, [r0]
vst44.32 {q0, q1, q2, q3}, [r0]
vld20.8 {q0, q2}, [r0]
vld20.8 {q0, q1, q2}, [r0]
vld20.8 {q0}, [r0]
vld20.8 {q0, q1}, [pc]
vld20.8 {q0, q1}, [pc]!
vld20.8 {q0, q1}, [sp]!
vld20.8 {q3, q2}, [r0]
vld20.64 {q0, q1}, [r0]
vld21.8 {q0, q2}, [r0]
vld21.8 {q0, q1, q2}, [r0]
vld21.8 {q0}, [r0]
vld21.8 {q0, q1}, [pc]
vld21.8 {q0, q1}, [pc]!
vld21.8 {q0, q1}, [sp]!
vld21.8 {q3, q2}, [r0]
vld21.64 {q0, q1}, [r0]
vld40.8 {q0, q2, q3, q4}, [r0]
vld40.8 {q0, q1, q3, q4}, [r0]
vld40.8 {q0, q1, q2, q4}, [r0]
vld40.8 {q3, q1, q2, q3}, [r0]
vld40.8 {q0, q1, q2, q3, q4}, [r0]
vld40.8 {q0, q1, q2}, [r0]
vld40.8 {q0, q1}, [r0]
vld40.8 {q0}, [r0]
vld40.8 {q0, q1, q2, q3}, [pc]
vld40.8 {q0, q1, q2, q3}, [pc]!
vld40.8 {q0, q1, q2, q3}, [sp]!
vld40.64 {q0, q1, q2, q3}, [r0]
vld41.8 {q0, q2, q3, q4}, [r0]
vld41.8 {q0, q1, q3, q4}, [r0]
vld41.8 {q0, q1, q2, q4}, [r0]
vld41.8 {q3, q1, q2, q3}, [r0]
vld41.8 {q0, q1, q2, q3, q4}, [r0]
vld41.8 {q0, q1, q2}, [r0]
vld41.8 {q0, q1}, [r0]
vld41.8 {q0}, [r0]
vld41.8 {q0, q1, q2, q3}, [pc]
vld41.8 {q0, q1, q2, q3}, [pc]!
vld41.8 {q0, q1, q2, q3}, [sp]!
vld41.64 {q0, q1, q2, q3}, [r0]
vld42.8 {q0, q2, q3, q4}, [r0]
vld42.8 {q0, q1, q3, q4}, [r0]
vld42.8 {q0, q1, q2, q4}, [r0]
vld42.8 {q3, q1, q2, q3}, [r0]
vld42.8 {q0, q1, q2, q3, q4}, [r0]
vld42.8 {q0, q1, q2}, [r0]
vld42.8 {q0, q1}, [r0]
vld42.8 {q0}, [r0]
vld42.8 {q0, q1, q2, q3}, [pc]
vld42.8 {q0, q1, q2, q3}, [pc]!
vld42.8 {q0, q1, q2, q3}, [sp]!
vld42.64 {q0, q1, q2, q3}, [r0]
vld43.8 {q0, q2, q3, q4}, [r0]
vld43.8 {q0, q1, q3, q4}, [r0]
vld43.8 {q0, q1, q2, q4}, [r0]
vld43.8 {q3, q1, q2, q3}, [r0]
vld43.8 {q0, q1, q2, q3, q4}, [r0]
vld43.8 {q0, q1, q2}, [r0]
vld43.8 {q0, q1}, [r0]
vld43.8 {q0}, [r0]
vld43.8 {q0, q1, q2, q3}, [pc]
vld43.8 {q0, q1, q2, q3}, [pc]!
vld43.8 {q0, q1, q2, q3}, [sp]!
vld43.64 {q0, q1, q2, q3}, [r0]
vld1.8 {q0, q1}, [r0]
vld2.8 {q0, q1}, [r0]
vld3.8 {q0, q1}, [r0]
vld4.8 {q0, q1}, [r0]
vld23.32 {q0, q1}, [r0]
vld44.32 {q0, q1, q2, q3}, [r0]
.macro cond2 op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().32 {q0, q1}, [r0]
.endr
.endm
.macro cond4 op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().32 {q0, q1, q2, q3}, [r0]
.endr
.endm
cond2 vst20
cond2 vst21
cond4 vst40
cond4 vst41
cond4 vst42
cond4 vst43
vpste
vst20t.32 {q0, q1}, [r0]
vst20e.32 {q0, q1}, [r0]
vpste
vst21t.32 {q0, q1}, [r0]
vst21e.32 {q0, q1}, [r0]
vpste
vst40t.32 {q0, q1, q2, q3}, [r0]
vst40e.32 {q0, q1, q2, q3}, [r0]
vpste
vst41t.32 {q0, q1, q2, q3}, [r0]
vst41e.32 {q0, q1, q2, q3}, [r0]
vpste
vst42t.32 {q0, q1, q2, q3}, [r0]
vst42e.32 {q0, q1, q2, q3}, [r0]
vpste
vst43t.32 {q0, q1, q2, q3}, [r0]
vst43e.32 {q0, q1, q2, q3}, [r0]
vpst
vst20.32 {q0, q1}, [r0]
vpst
vst21.32 {q0, q1}, [r0]
vpst
vst40.32 {q0, q1, q2, q3}, [r0]
vpst
vst41.32 {q0, q1, q2, q3}, [r0]
vpst
vst42.32 {q0, q1, q2, q3}, [r0]
vpst
vst43.32 {q0, q1, q2, q3}, [r0]
cond2 vld20
cond2 vld21
cond4 vld40
cond4 vld41
cond4 vld42
cond4 vld43
vpste
vld20t.32 {q0, q1}, [r0]
vld20e.32 {q0, q1}, [r0]
vpste
vld21t.32 {q0, q1}, [r0]
vld21e.32 {q0, q1}, [r0]
vpste
vld40t.32 {q0, q1, q2, q3}, [r0]
vld40e.32 {q0, q1, q2, q3}, [r0]
vpste
vld41t.32 {q0, q1, q2, q3}, [r0]
vld41e.32 {q0, q1, q2, q3}, [r0]
vpste
vld42t.32 {q0, q1, q2, q3}, [r0]
vld42e.32 {q0, q1, q2, q3}, [r0]
vpste
vld43t.32 {q0, q1, q2, q3}, [r0]
vld43e.32 {q0, q1, q2, q3}, [r0]
vpst
vld20.32 {q0, q1}, [r0]
vpst
vld21.32 {q0, q1}, [r0]
vpst
vld40.32 {q0, q1, q2, q3}, [r0]
vpst
vld41.32 {q0, q1, q2, q3}, [r0]
vpst
vld42.32 {q0, q1, q2, q3}, [r0]
vpst
vld43.32 {q0, q1, q2, q3}, [r0]
|
tactcomplabs/xbgas-binutils-gdb
| 1,985
|
gas/testsuite/gas/arm/cde-mve-or-neon.s
|
.syntax unified
vcx1 p0, s0, #0
vcx1 p0, s0, #1920
vcx1 p0, s0, #64
vcx1 p0, s0, #63
vcx1 p7, s0, #0
vcx1 p0, s1, #0
vcx1 p0, s30, #0
vcx1 p0, d0, #0
vcx1 p0, d0, #1920
vcx1 p0, d0, #64
vcx1 p0, d0, #63
vcx1 p7, d0, #0
vcx1 p0, d15, #0
vcx1a p0, s0, #0
vcx1a p0, s0, #1920
vcx1a p0, s0, #64
vcx1a p0, s0, #63
vcx1a p7, s0, #0
vcx1a p0, s1, #0
vcx1a p0, s30, #0
vcx1a p0, d0, #0
vcx1a p0, d0, #1920
vcx1a p0, d0, #64
vcx1a p0, d0, #63
vcx1a p7, d0, #0
vcx1a p0, d15, #0
vcx2 p0, s0, s0, #0
vcx2 p0, s0, s0, #60
vcx2 p0, s0, s0, #2
vcx2 p0, s0, s0, #1
vcx2 p7, s0, s0, #0
vcx2 p0, s1, s0, #0
vcx2 p0, s30, s0, #0
vcx2 p0, s0, s1, #0
vcx2 p0, s0, s30, #0
vcx2 p0, d0, d0, #0
vcx2 p0, d0, d0, #60
vcx2 p0, d0, d0, #2
vcx2 p0, d0, d0, #1
vcx2 p7, d0, d0, #0
vcx2 p0, d15, d0, #0
vcx2 p0, d0, d15, #0
vcx2a p0, s0, s0, #0
vcx2a p0, s0, s0, #60
vcx2a p0, s0, s0, #2
vcx2a p0, s0, s0, #1
vcx2a p7, s0, s0, #0
vcx2a p0, s1, s0, #0
vcx2a p0, s30, s0, #0
vcx2a p0, s0, s1, #0
vcx2a p0, s0, s30, #0
vcx2a p0, d0, d0, #0
vcx2a p0, d0, d0, #60
vcx2a p0, d0, d0, #2
vcx2a p0, d0, d0, #1
vcx2a p7, d0, d0, #0
vcx2a p0, d15, d0, #0
vcx2a p0, d0, d15, #0
vcx3 p0, s0, s0, s0, #0
vcx3 p0, s0, s0, s0, #6
vcx3 p0, s0, s0, s0, #1
vcx3 p7, s0, s0, s0, #0
vcx3 p0, s1, s0, s0, #0
vcx3 p0, s30, s0, s0, #0
vcx3 p0, s0, s1, s0, #0
vcx3 p0, s0, s30, s0, #0
vcx3 p0, s0, s0, s1, #0
vcx3 p0, s0, s0, s30, #0
vcx3 p0, d0, d0, d0, #0
vcx3 p0, d0, d0, d0, #6
vcx3 p0, d0, d0, d0, #1
vcx3 p7, d0, d0, d0, #0
vcx3 p0, d15, d0, d0, #0
vcx3 p0, d0, d15, d0, #0
vcx3 p0, d0, d0, d15, #0
vcx3a p0, s0, s0, s0, #0
vcx3a p0, s0, s0, s0, #6
vcx3a p0, s0, s0, s0, #1
vcx3a p7, s0, s0, s0, #0
vcx3a p0, s1, s0, s0, #0
vcx3a p0, s30, s0, s0, #0
vcx3a p0, s0, s1, s0, #0
vcx3a p0, s0, s30, s0, #0
vcx3a p0, s0, s0, s1, #0
vcx3a p0, s0, s0, s30, #0
vcx3a p0, d0, d0, d0, #0
vcx3a p0, d0, d0, d0, #6
vcx3a p0, d0, d0, d0, #1
vcx3a p7, d0, d0, d0, #0
vcx3a p0, d15, d0, d0, #0
vcx3a p0, d0, d15, d0, #0
vcx3a p0, d0, d0, d15, #0
|
tactcomplabs/xbgas-binutils-gdb
| 1,723
|
gas/testsuite/gas/arm/mve-vqdmlsdh.s
|
.syntax unified
.thumb
.irp data, s8, s16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
vqdmlsdh.\data \op1, \op2, \op3
vqdmlsdhx.\data \op1, \op2, \op3
vqrdmlsdh.\data \op1, \op2, \op3
vqrdmlsdhx.\data \op1, \op2, \op3
.endr
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3, q1, q2, q4, q7
vqdmlsdh.s32 q0, \op2, \op3
vqdmlsdhx.s32 q0, \op2, \op3
vqrdmlsdh.s32 q0, \op2, \op3
vqrdmlsdhx.s32 q0, \op2, \op3
.endr
.endr
.irp op2, q0, q2, q4, q7
.irp op3, q0, q2, q4, q7
vqdmlsdh.s32 q1, \op2, \op3
vqdmlsdhx.s32 q1, \op2, \op3
vqrdmlsdh.s32 q1, \op2, \op3
vqrdmlsdhx.s32 q1, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
vqdmlsdh.s32 q2, \op2, \op3
vqdmlsdhx.s32 q2, \op2, \op3
vqrdmlsdh.s32 q2, \op2, \op3
vqrdmlsdhx.s32 q2, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
vqdmlsdh.s32 q2, \op2, \op3
vqdmlsdhx.s32 q2, \op2, \op3
vqrdmlsdh.s32 q2, \op2, \op3
vqrdmlsdhx.s32 q2, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q2, q7
.irp op3, q0, q1, q2, q7
vqdmlsdh.s32 q4, \op2, \op3
vqdmlsdhx.s32 q4, \op2, \op3
vqrdmlsdh.s32 q4, \op2, \op3
vqrdmlsdhx.s32 q4, \op2, \op3
.endr
.endr
.irp op2, q0, q1, q2, q4
.irp op3, q0, q1, q2, q4
vqdmlsdh.s32 q7, \op2, \op3
vqdmlsdhx.s32 q7, \op2, \op3
vqrdmlsdh.s32 q7, \op2, \op3
vqrdmlsdhx.s32 q7, \op2, \op3
.endr
.endr
vpstete
vqdmlsdht.s8 q0, q1, q2
vqdmlsdhe.s8 q0, q1, q2
vqdmlsdhxt.s16 q0, q1, q2
vqdmlsdhxe.s16 q0, q1, q2
vpstete
vqrdmlsdht.s32 q0, q1, q2
vqrdmlsdhe.s32 q0, q1, q2
vqrdmlsdhxt.s16 q0, q1, q2
vqrdmlsdhxe.s16 q0, q1, q2
vqdmlsdh.s32 q0, q0, q0
vqrdmlsdh.s32 q0, q0, q0
vqdmlsdh.s32 q1, q1, q2
vqrdmlsdh.s32 q2, q2, q3
vqdmlsdh.s32 q3, q4, q3
vqrdmlsdh.s32 q4, q5, q4
|
tactcomplabs/xbgas-binutils-gdb
| 6,275
|
gas/testsuite/gas/arm/sp-pc-validations-bad.s
|
.syntax unified
@ Loads, ARM ================================================================
.arm
@ LDR (immediate, ARM)
@ LDR (literal)
@No unpredictable or undefined combinations.
@ LDR (register)
ldr r0,[r1,pc, LSL #2] @ Unpredictable
ldr r0,[r1,pc, LSL #2]! @ ditto
ldr r0,[r1],pc, LSL #2 @ ditto
ldr r0,[pc,r1, LSL #2]! @ ditto
ldr r0,[pc],r1, LSL #2 @ ditto
@ LDRB (immediate, ARM)
ldrb pc,[r0,#4] @ Unpredictable
ldrb pc,[r0],#4 @ ditto
ldrb pc,[r0,#4]! @ ditto
@ LDRB (literal)
ldrb pc, label @ Unpredictable
ldrb pc,[pc,#-0] @ ditto
@ LDRB (register)
ldrb pc,[r0,r1, LSL #2] @ Unpredictable
ldrb pc,[r0,r1, LSL #2]! @ ditto
ldrb pc,[r0],r1, LSL #2 @ ditto
ldrb r0,[r1,pc, LSL #2] @ ditto
ldrb r0,[r1,pc, LSL #2]! @ ditto
ldrb r0,[r1],pc, LSL #2 @ ditto
ldrb r0,[pc,r1, LSL #2]! @ ditto
ldrb r0,[pc],r1, LSL #2 @ ditto
@ LDRBT
ldrbt pc,[r0],#4 @ Unpredictable
ldrbt r0,[pc],#4 @ ditto
ldrbt pc,[r0],r1, LSL #4 @ ditto
ldrbt r0,[pc],r1, LSL #4 @ ditto
ldrbt r0,[r1],pc, LSL #4 @ ditto
@ LDRD (immediate)
ldrd r0,pc,[r1,#4] @ Unpredictable
ldrd r0,pc,[r1],#4 @ ditto
ldrd r0,pc,[r1,#4]! @ ditto
@ LDRD (literal)
ldrd r0,pc, label @ Unpredictable
ldrd r0,pc,[PC,#-0] @ ditto
@ LDRD (register)
ldrd r0,pc,[r1,r2] @ Unpredictable
ldrd r0,pc,[r1,r2]! @ ditto
ldrd r0,pc,[r1],r2 @ ditto
ldrd r0,r1,[r2,pc] @ ditto
ldrd r0,r1,[r2,pc]! @ ditto
ldrd r0,r1,[r2],pc @ ditto
ldrd r0,r1,[pc,r2]! @ ditto
ldrd r0,r1,[pc],r2 @ ditto
@ LDREX
ldrex pc,[r0] @ Unpredictable
ldrex r0,[pc] @ ditto
@ LDREXB
ldrexb pc,[r0] @ Unpredictable
ldrexb r0,[pc] @ ditto
@ LDREXD
ldrexd r0,r1,[pc] @ Unpredictable
@ LDREXH
ldrexh pc,[r0] @ Unpredictable
ldrexh r0,[pc] @ ditto
@ LDRH (immediate, ARM)
ldrh pc,[r0,#4] @ Unpredictable
ldrh pc,[r0],#4 @ ditto
ldrh pc,[r0,#4]! @ ditto
@ LDRH (literal)
ldrh pc, label @ Unpredictable
ldrh pc,[pc,#-0] @ ditto
@ LDRH (register)
ldrh pc,[r0,r1] @ Unpredictable
ldrh pc,[r0,r1]! @ ditto
ldrh pc,[r0],r1 @ ditto
ldrh r0,[r1,pc] @ ditto
ldrh r0,[r1,pc]! @ ditto
ldrh r0,[r1],pc @ ditto
ldrh r0,[pc,r1]! @ ditto
ldrh r0,[pc],r1 @ ditto
@ LDRHT
ldrht pc, [r0], #4 @ Unpredictable
ldrht r0, [pc], #4 @ ditto
ldrht pc, [r0], r1 @ ditto
ldrht r0, [pc], r1 @ ditto
ldrht r0, [r1], pc @ ditto
@ LDRSB (immediate)
ldrsb pc,[r0,#4] @ Unpredictable
ldrsb pc,[r0],#4 @ ditto
ldrsb pc,[r0,#4]! @ ditto
@ LDRSB (literal)
ldrsb pc, label @ Unpredictable
ldrsb pc,[pc,#-0] @ ditto
@ LDRSB (register)
ldrsb pc,[r0,r1] @ Unpredictable
ldrsb pc,[r0,r1]! @ ditto
ldrsb pc,[r0],r1 @ ditto
ldrsb r0,[r1,pc] @ ditto
ldrsb r0,[r1,pc]! @ ditto
ldrsb r0,[r1],pc @ ditto
ldrsb r0,[pc,r1]! @ ditto
ldrsb r0,[pc],r1 @ ditto
@ LDRSBT
ldrsbt pc, [r0], #4 @ Unpredictable
ldrsbt r0, [pc], #4 @ ditto
ldrsbt pc, [r0], r1 @ ditto
ldrsbt r0, [pc], r1 @ ditto
ldrsbt r0, [r1], pc @ ditto
@ LDRSH (immediate)
ldrsh pc,[r0,#4] @ Unpredictable
ldrsh pc,[r0],#4 @ ditto
ldrsh pc,[r0,#4]! @ ditto
@ LDRSH (literal)
ldrsh pc, label @ Unpredictable
ldrsh pc,[pc,#-0] @ ditto
@ LDRSH (register)
ldrsh pc,[r0,r1] @ Unpredictable
ldrsh pc,[r0,r1]! @ ditto
ldrsh pc,[r0],r1 @ ditto
ldrsh r0,[r1,pc] @ ditto
ldrsh r0,[r1,pc]! @ ditto
ldrsh r0,[r1],pc @ ditto
ldrsh r0,[pc,r1]! @ ditto
ldrsh r0,[pc],r1 @ ditto
@ LDRSHT
ldrsht pc, [r0], #4 @ Unpredictable
ldrsht r0, [pc], #4 @ ditto
ldrsht pc, [r0], r1 @ ditto
ldrsht r0, [pc], r1 @ ditto
ldrsht r0, [r1], pc @ ditto
@ LDRT
ldrt pc, [r0], #4 @ Unpredictable
ldrt r0, [pc], #4 @ ditto
ldrt pc,[r0],r1, LSL #4 @ ditto
ldrt r0,[pc],r1, LSL #4 @ ditto
ldrt r0,[r1],pc, LSL #4 @ ditto
@ Stores, ARM ================================================================
@ STR (immediate, ARM)
str r0,[pc],#4 @ Unpredictable
str r0,[pc,#4]! @ ditto
@ STR (register)
str r0,[r1,pc, LSL #4] @ Unpredictable
str r0,[r1,pc, LSL #4]! @ ditto
str r0,[r1],pc, LSL #4 @ ditto
@ STRB (immediate, ARM)
strb pc,[r0,#4] @ Unpredictable
strb pc,[r0],#4 @ ditto
strb pc,[r0,#4]! @ ditto
strb r0,[pc],#4 @ ditto
strb r0,[pc,#4]! @ ditto
@ STRB (register)
strb pc,[r0,r1, LSL #4] @ Unpredictable
strb pc,[r0,r1, LSL #4]! @ ditto
strb pc,[r0],r1, LSL #4 @ ditto
strb r1,[r0,pc, LSL #4] @ ditto
strb r1,[r0,pc, LSL #4]! @ ditto
strb r1,[r0],pc, LSL #4 @ ditto
strb r0,[pc,r1, LSL #4]! @ ditto
strb r0,[pc],r1, LSL #4 @ ditto
@ STRBT
strbt pc,[r0],#4 @ Unpredictable
strbt r0,[pc],#4 @ ditto
strbt pc,[r0],r1, LSL #4 @ ditto
strbt r0,[pc],r1, LSL #4 @ ditto
strbt r0,[r1],pc, LSL #4 @ ditto
@ STRD (immediate)
strd r0,pc,[r1,#4] @ ditto
strd r0,pc,[r1],#4 @ ditto
strd r0,pc,[r1,#4]! @ ditto
strd r0,r1,[pc],#4 @ ditto
strd r0,r1,[pc,#4]! @ ditto
@STRD (register)
strd r0,pc,[r1,r2] @ Unpredictable
strd r0,pc,[r1,r2]! @ ditto
strd r0,pc,[r1],r2 @ ditto
strd r0,r1,[r2,pc] @ ditto
strd r0,r1,[r2,pc]! @ ditto
strd r0,r1,[r2],pc @ ditto
strd r0,r1,[pc,r2]! @ ditto
strd r0,r1,[pc],r2 @ ditto
@ STREX
strex pc,r0,[r1] @ Unpredictable
strex r0,pc,[r1] @ ditto
strex r0,r1,[pc] @ ditto
@ STREXB
strexb pc,r0,[r1] @ Unpredictable
strexb r0,pc,[r1] @ ditto
strexb r0,r1,[pc] @ ditto
@ STREXD
strexd pc,r0,r1,[r2] @ Unpredictable
strexd r0,r1,r2,[pc] @ ditto
@ STREXH
strexh pc,r0,[r1] @ Unpredictable
strexh r0,pc,[r1] @ ditto
strexh r0,r1,[pc] @ ditto
@ STRH (immediate, ARM)
strh pc,[r0,#4] @ Unpredictable
strh pc,[r0],#4 @ ditto
strh pc,[r0,#4]! @ ditto
strh r0,[pc],#4 @ ditto
strh r0,[pc,#4]! @ ditto
@ STRH (register)
strh pc,[r0,r1] @ Unpredictable
strh pc,[r0,r1]! @ ditto
strh pc,[r0],r1 @ ditto
strh r0,[r1,pc] @ ditto
strh r0,[r1,pc]! @ ditto
strh r0,[r1],pc @ ditto
strh r0,[pc,r1]! @ ditto
strh r0,[pc],r1 @ ditto
@ STRHT
strht pc, [r0], #4 @ Unpredictable
strht r0, [pc], #4 @ ditto
strht pc, [r0], r1 @ ditto
strht r0, [pc], r1 @ ditto
strht r0, [r1], pc @ ditto
@ STRT
strt r0, [pc], #4 @ Unpredictable
strt r0, [pc],r1, LSL #4 @ ditto
strt r0, [r1],pc, LSL #4 @ ditto
@ ============================================================================
.label:
ldr r0, [r1]
|
tactcomplabs/xbgas-binutils-gdb
| 2,896
|
gas/testsuite/gas/arm/mve-vmov-1.s
|
.syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vmov \op0, \op1, s2, s3
vmov \op0, \op1, s4, s5
vmov \op0, \op1, s8, s9
vmov \op0, \op1, s16, s17
vmov \op0, \op1, s30, s31
vmov s0, s1, \op0, \op1
vmov s1, s2, \op0, \op1
vmov s2, s3, \op0, \op1
vmov s4, s5, \op0, \op1
vmov s8, s9, \op0, \op1
vmov s16, s17, \op0, \op1
vmov s30, s31, \op0, \op1
.endm
.irp op0, r1, r2, r4, r7, r8, r10, r12, r14
vmov_rr r0, \op0
.endr
.irp op0, r0, r2, r4, r7, r8, r10, r12, r14
vmov_rr r1, \op0
.endr
.irp op0, r0, r1, r4, r7, r8, r10, r12, r14
vmov_rr r2, \op0
.endr
.irp op0, r0, r1, r2, r7, r8, r10, r12, r14
vmov_rr r4, \op0
.endr
.irp op0, r0, r1, r2, r4, r8, r10, r12, r14
vmov_rr r7, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r10, r12, r14
vmov_rr r8, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r12, r14
vmov_rr r10, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r10, r14
vmov_rr r12, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r10, r12
vmov_rr r14, \op0
.endr
.macro vmov_qidx_r size, idx
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov\size \op1[\idx], \op2
.endr
.endr
.endm
.irp idx, 0, 1, 2, 4, 8, 15, 13, 6
vmov_qidx_r .8, \idx
.endr
.irp idx, 0, 1, 2, 4, 7
vmov_qidx_r .16, \idx
.endr
.irp idx, 0, 1, 2, 3
vmov_qidx_r .32, \idx
.endr
.macro vmov_r_qidx size, idx
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
.irp op2, q0, q1, q2, q4, q7
vmov\size \op1, \op2[\idx]
.endr
.endr
.endm
.irp data, .u8, .s8
.irp idx, 0, 1, 2, 4, 8, 15, 13, 6
vmov_r_qidx \data, \idx
.endr
.endr
.irp data, .u16, .s16
.irp idx, 0, 1, 2, 4, 7
vmov_r_qidx \data, \idx
.endr
.endr
.irp idx, 0, 1, 2, 3
vmov_r_qidx .32, \idx
.endr
vmov.i32 q0, #0
vmov.i32 q0, #255 @ 0x000000FF 000000FF
vmov.i32 q0, #65280 @ 0x0000FF00 0000FF00
vmov.i32 q0, #4278190080 @ 0xFF000000 FF000000
vmov.i32 q0, #16711680 @ 0x00FF0000 00FF0000
vmov.i16 q0, #0
vmov.i16 q0, #255 @ 0x00FF 00FF 00FF 00FF
vmov.i16 q0, #65280 @ 0xFF00 FF00 FF00 FF00
vmov.i8 q0, #0
vmov.i8 q0, #255 @ 0xFF FF FF FF FF FF FF FF
vmov.i64 q0, #18374686479671623680 @ 0xFF00000000000000
vmov.i64 q0, #71776119061217280 @ 0x00FF000000000000
vmov.i64 q0, #280375465082880 @ 0x0000FF0000000000
vmov.i64 q0, #1095216660480 @ 0x000000FF00000000
vmov.i64 q0, #4278190080 @ 0x00000000FF000000
vmov.i64 q0, #16711680 @ 0x00000000000FF0000
vmov.i64 q0, #65280 @ 0x0000000000000FF00
vmov.i64 q0, #255 @ 0x000000000000000FF
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
vmov \op1, \op2
.endr
.endr
.irp op1, d0, d1, d2, d4, d8, d15
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op1, \op2
vmov.f64 \op1, \op2
.endr
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 1,105
|
gas/testsuite/gas/arm/mve-vqdmull-bad.s
|
.macro cond op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vqdmullt.s8 q0, q1, q2
vqdmullt.u8 q0, q1, q2
vqdmullt.i16 q0, q1, q2
vqdmullt.s64 q0, q1, q2
vqdmullb.s8 q0, q1, q2
vqdmullb.u8 q0, q1, q2
vqdmullb.i16 q0, q1, q2
vqdmullb.s64 q0, q1, q2
vqdmullt.s8 q0, q1, r2
vqdmullt.u8 q0, q1, r2
vqdmullt.i16 q0, q1, r2
vqdmullt.s64 q0, q1, r2
vqdmullb.s8 q0, q1, r2
vqdmullb.u8 q0, q1, r2
vqdmullb.i16 q0, q1, r2
vqdmullb.s64 q0, q1, r2
vqdmullt.s32 q0, q0, q2
vqdmullt.s32 q0, q1, q0
vqdmullb.s32 q0, q0, q2
vqdmullb.s32 q0, q1, q0
vqdmullt.s32 q0, q0, r2
vqdmullb.s32 q0, q0, r2
vqdmullt.s16 q0, q0, sp
vqdmullt.s16 q0, q0, pc
vqdmullb.s16 q0, q0, sp
vqdmullb.s16 q0, q0, pc
cond vqdmullt, q2
cond vqdmullb, q2
cond vqdmullt, r2
cond vqdmullb, r2
it eq
vqdmullteq.s32 q0, q1, q2
vqdmullteq.s32 q0, q1, q2
vpst
vqdmullteq.s32 q0, q1, q2
vqdmulltt.s32 q0, q1, q2
vpst
vqdmullt.s32 q0, q1, q2
it eq
vqdmullbeq.s32 q0, q1, q2
vqdmullbeq.s32 q0, q1, q2
vpst
vqdmullbeq.s32 q0, q1, q2
vqdmullbt.s32 q0, q1, q2
vpst
vqdmullb.s32 q0, q1, q2
|
tactcomplabs/xbgas-binutils-gdb
| 2,306
|
gas/testsuite/gas/arm/armv7-a+virt.s
|
.text
.syntax unified
.arm
foo:
hvc 0x0000
hvc 0xffff
eret
mrs r1, R8_usr
mrs r1, R9_usr
mrs r1, R10_usr
mrs r1, R11_usr
mrs r1, R12_usr
mrs r1, SP_usr
mrs r1, LR_usr
mrs r1, R8_fiq
mrs r1, R9_fiq
mrs r1, R10_fiq
mrs r1, R11_fiq
mrs r1, R12_fiq
mrs r1, SP_fiq
mrs r1, LR_fiq
mrs r1, SPSR_fiq
mrs r1, SP_irq
mrs r1, LR_irq
mrs r1, SPSR_irq
mrs r1, SP_svc
mrs r1, LR_svc
mrs r1, SPSR_svc
mrs r1, SP_abt
mrs r1, LR_abt
mrs r1, SPSR_abt
mrs r1, SP_und
mrs r1, LR_und
mrs r1, SPSR_und
mrs r1, SP_mon
mrs r1, LR_mon
mrs r1, SPSR_mon
mrs r1, SP_hyp
mrs r1, ELR_hyp
mrs r1, SPSR_hyp
msr R8_usr, r1
msr R9_usr, r1
msr R10_usr, r1
msr R11_usr, r1
msr R12_usr, r1
msr SP_usr, r1
msr LR_usr, r1
msr R8_fiq, r1
msr R9_fiq, r1
msr R10_fiq, r1
msr R11_fiq, r1
msr R12_fiq, r1
msr SP_fiq, r1
msr LR_fiq, r1
msr SPSR_fiq, r1
msr SP_irq, r1
msr LR_irq, r1
msr SPSR_irq, r1
msr SP_svc, r1
msr LR_svc, r1
msr SPSR_svc, r1
msr SP_abt, r1
msr LR_abt, r1
msr SPSR_abt, r1
msr SP_und, r1
msr LR_und, r1
msr SPSR_und, r1
msr SP_mon, r1
msr LR_mon, r1
msr SPSR_mon, r1
msr SP_hyp, r1
msr ELR_hyp, r1
msr SPSR_hyp, r1
.thumb
bar:
hvc 0x0000
hvc 0xffff
eret
mrs r1, R8_usr
mrs r1, R9_usr
mrs r1, R10_usr
mrs r1, R11_usr
mrs r1, R12_usr
mrs r1, SP_usr
mrs r1, LR_usr
mrs r1, R8_fiq
mrs r1, R9_fiq
mrs r1, R10_fiq
mrs r1, R11_fiq
mrs r1, R12_fiq
mrs r1, SP_fiq
mrs r1, LR_fiq
mrs r1, SPSR_fiq
mrs r1, SP_irq
mrs r1, LR_irq
mrs r1, SPSR_irq
mrs r1, SP_svc
mrs r1, LR_svc
mrs r1, SPSR_svc
mrs r1, SP_abt
mrs r1, LR_abt
mrs r1, SPSR_abt
mrs r1, SP_und
mrs r1, LR_und
mrs r1, SPSR_und
mrs r1, SP_mon
mrs r1, LR_mon
mrs r1, SPSR_mon
mrs r1, SP_hyp
mrs r1, ELR_hyp
mrs r1, SPSR_hyp
msr R8_usr, r1
msr R9_usr, r1
msr R10_usr, r1
msr R11_usr, r1
msr R12_usr, r1
msr SP_usr, r1
msr LR_usr, r1
msr R8_fiq, r1
msr R9_fiq, r1
msr R10_fiq, r1
msr R11_fiq, r1
msr R12_fiq, r1
msr SP_fiq, r1
msr LR_fiq, r1
msr SPSR_fiq, r1
msr SP_irq, r1
msr LR_irq, r1
msr SPSR_irq, r1
msr SP_svc, r1
msr LR_svc, r1
msr SPSR_svc, r1
msr SP_abt, r1
msr LR_abt, r1
msr SPSR_abt, r1
msr SP_und, r1
msr LR_und, r1
msr SPSR_und, r1
msr SP_mon, r1
msr LR_mon, r1
msr SPSR_mon, r1
msr SP_hyp, r1
msr ELR_hyp, r1
msr SPSR_hyp, r1
|
tactcomplabs/xbgas-binutils-gdb
| 2,846
|
gas/testsuite/gas/arm/mve-vstr-bad-3.s
|
.macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0]
.endr
.endm
.syntax unified
.thumb
vstrb.8 q0, [r0, #128]
vstrb.8 q0, [r0, #-128]
vstrb.16 q0, [r0, #128]
vstrb.16 q0, [r0, #-128]
vstrb.32 q0, [r0, #128]
vstrb.32 q0, [r0, #-128]
vstrb.8 q0, [r0, #128]!
vstrb.8 q0, [r0, #-128]!
vstrb.16 q0, [r0, #128]!
vstrb.16 q0, [r0, #-128]!
vstrb.32 q0, [r0, #128]!
vstrb.32 q0, [r0, #-128]!
vstrb.8 q0, [r0], #128
vstrb.8 q0, [r0], #-128
vstrb.16 q0, [r0], #128
vstrb.16 q0, [r0], #-128
vstrb.32 q0, [r0], #128
vstrb.32 q0, [r0], #-128
vstrb.16 q0, [r10, #2]
vstrb.16 q0, [r10, #2]!
vstrb.16 q0, [r10], #2
vstrb.8 q0, [sp, #2]!
vstrb.8 q0, [sp], #2
vstrb.8 q0, [pc, #2]
cond vstrb
vstrb.u16 q0, [r0]
vstrb.s16 q0, [r0]
vstrb.f16 q0, [r0]
vstrb.p16 q0, [r0]
vstrb.u32 q0, [r0]
vstrb.s32 q0, [r0]
vstrb.f32 q0, [r0]
vstrh.16 q0, [r0, #1]
vstrh.16 q0, [r0, #17]
vstrh.16 q0, [r0, #-17]
vstrh.16 q0, [r0, #256]
vstrh.16 q0, [r0, #-256]
vstrh.32 q0, [r0, #1]
vstrh.32 q0, [r0, #17]
vstrh.32 q0, [r0, #-17]
vstrh.32 q0, [r0, #256]
vstrh.32 q0, [r0, #-256]
vstrh.16 q0, [r0, #1]!
vstrh.16 q0, [r0, #17]!
vstrh.16 q0, [r0, #-17]!
vstrh.16 q0, [r0, #256]!
vstrh.16 q0, [r0, #-256]!
vstrh.32 q0, [r0, #1]!
vstrh.32 q0, [r0, #17]!
vstrh.32 q0, [r0, #-17]!
vstrh.32 q0, [r0, #256]!
vstrh.32 q0, [r0, #-256]!
vstrh.16 q0, [r0], #1
vstrh.16 q0, [r0], #17
vstrh.16 q0, [r0], #-17
vstrh.16 q0, [r0], #256
vstrh.16 q0, [r0], #-256
vstrh.32 q0, [r0], #1
vstrh.32 q0, [r0], #17
vstrh.32 q0, [r0], #-17
vstrh.32 q0, [r0], #256
vstrh.32 q0, [r0], #-256
vstrh.32 q0, [r10, #4]
vstrh.16 q0, [sp, #2]!
vstrh.16 q0, [sp], #2
vstrh.16 q0, [pc, #2]
cond vstrh
vstrh.8 q0, [r0]
vstrh.u8 q0, [r0]
vstrh.s8 q0, [r0]
vstrh.p8 q0, [r0]
vstrh.u32 q0, [r0]
vstrh.s32 q0, [r0]
vstrh.f32 q0, [r0]
vstrw.32 q0, [r0, #3]
vstrw.32 q0, [r0, #-3]
vstrw.32 q0, [r0, #514]
vstrw.32 q0, [r0, #-258]
vstrw.32 q0, [r0, #258]
vstrw.32 q0, [r0, #516]
vstrw.32 q0, [r0, #-516]
vstrw.32 q0, [r0, #3]!
vstrw.32 q0, [r0, #-3]!
vstrw.32 q0, [r0, #514]!
vstrw.32 q0, [r0, #-258]!
vstrw.32 q0, [r0, #258]!
vstrw.32 q0, [r0, #516]!
vstrw.32 q0, [r0, #-516]!
vstrw.32 q0, [r0], #3
vstrw.32 q0, [r0], #-3
vstrw.32 q0, [r0], #514
vstrw.32 q0, [r0], #-258
vstrw.32 q0, [r0], #258
vstrw.32 q0, [r0], #516
vstrw.32 q0, [r0], #-516
vstrw.32 q0, [sp, #4]!
vstrw.32 q0, [pc, #4]
cond vstrw
vstrw.8 q0, [r0]
vstrw.u8 q0, [r0]
vstrw.s8 q0, [r0]
vstrw.p8 q0, [r0]
vstrw.16 q0, [r0]
vstrw.u16 q0, [r0]
vstrw.s16 q0, [r0]
vstrw.f16 q0, [r0]
vstrw.p16 q0, [r0]
it eq
vstrbeq.8 q0, [r0]
vstrbeq.8 q0, [r0]
vpst
vstrbeq.8 q0, [r0]
vstrbt.8 q0, [r0]
vpst
vstrb.8 q0, [r0]
it eq
vstrheq.16 q0, [r0]
vstrheq.16 q0, [r0]
vpst
vstrheq.16 q0, [r0]
vstrht.16 q0, [r0]
vpst
vstrh.16 q0, [r0]
it eq
vstrweq.32 q0, [r0]
vstrweq.32 q0, [r0]
vpst
vstrweq.32 q0, [r0]
vstrwt.32 q0, [r0]
vpst
vstrw.32 q0, [r0]
|
tactcomplabs/xbgas-binutils-gdb
| 1,190
|
gas/testsuite/gas/arm/cde.s
|
.syntax unified
.include "cde-scalar.s"
# vcx1{a} encoding has the following form
# 111a110i0d10iiiidddd0pppi1iiiiii (vector form)
# 111a110s0d10iiiidddd0pppi0iiiiii (S/D register form)
#
# Variants to test:
# - immediates that set each set of `i` to ones in turn.
# - each register set to something non-zero
# (where each block of register sets is set to all-ones if possible)
# - coprocessor set to 7
# vcx2{a} encoding has the following form
# 111a110i0d11iiiidddd0pppi1mimmmm (vector form)
# 111a110s0d11iiiidddd0pppi0mimmmm (S/D register form)
#
# Variants to test:
# - immediates that set each set of `i` to ones in turn.
# - each register set to something non-zero
# (where each block of register sets is set to all-ones if possible)
# - coprocessor set to 7
# vcx3{a} encoding has the following form
# 111a110i1diinnnndddd0pppn1mimmmm (vector form)
# 111a110s1diinnnndddd0pppn0mimmmm (S/D register form)
#
# Variants to test:
# - immediates that set each set of `i` to ones in turn.
# - each register set to something non-zero
# (where each block of register sets is set to all-ones if possible)
# - coprocessor set to 7
.include "cde-mve.s"
.include "cde-mve-or-neon.s"
|
tactcomplabs/xbgas-binutils-gdb
| 1,394
|
gas/testsuite/gas/arm/mve-vqrshrn-bad.s
|
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q0, #1
.endr
.endm
.syntax unified
.thumb
vqrshrnt.s8 q0, q1, #1
vqrshrnt.s64 q0, q1, #1
vqrshrnt.s16 q0, q1, #0
vqrshrnt.s16 q0, q1, #9
vqrshrnt.s32 q0, q1, #0
vqrshrnt.s32 q0, q1, #17
vqrshrnb.s8 q0, q1, #1
vqrshrnb.s64 q0, q1, #1
vqrshrnb.s16 q0, q1, #0
vqrshrnb.s16 q0, q1, #9
vqrshrnb.s32 q0, q1, #0
vqrshrnb.s32 q0, q1, #17
vqrshrunt.s8 q0, q1, #1
vqrshrunt.s64 q0, q1, #1
vqrshrunt.s16 q0, q1, #0
vqrshrunt.s16 q0, q1, #9
vqrshrunt.s32 q0, q1, #0
vqrshrunt.s32 q0, q1, #17
vqrshrunt.u16 q0, q1, #1
vqrshrunb.s8 q0, q1, #1
vqrshrunb.s64 q0, q1, #1
vqrshrunb.s16 q0, q1, #0
vqrshrunb.s16 q0, q1, #9
vqrshrunb.s32 q0, q1, #0
vqrshrunb.s32 q0, q1, #17
vqrshrunb.u16 q0, q1, #1
cond vqrshrnt
cond vqrshrnb
cond vqrshrunt
cond vqrshrunb
it eq
vqrshrnteq.s16 q0, q1, #1
vqrshrnteq.s16 q0, q1, #1
vpst
vqrshrnteq.s16 q0, q1, #1
vqrshrntt.s16 q0, q1, #1
vpst
vqrshrnt.s16 q0, q1, #1
it eq
vqrshrnbeq.s16 q0, q1, #1
vqrshrnbeq.s16 q0, q1, #1
vpst
vqrshrnbeq.s16 q0, q1, #1
vqrshrnbt.s16 q0, q1, #1
vpst
vqrshrnb.s16 q0, q1, #1
it eq
vqrshrunteq.s16 q0, q1, #1
vqrshrunteq.s16 q0, q1, #1
vpst
vqrshrunteq.s16 q0, q1, #1
vqrshruntt.s16 q0, q1, #1
vpst
vqrshrunt.s16 q0, q1, #1
it eq
vqrshrunbeq.s16 q0, q1, #1
vqrshrunbeq.s16 q0, q1, #1
vpst
vqrshrunbeq.s16 q0, q1, #1
vqrshrunbt.s16 q0, q1, #1
vpst
vqrshrunb.s16 q0, q1, #1
|
tactcomplabs/xbgas-binutils-gdb
| 3,936
|
gas/testsuite/gas/arm/iwmmxt.s
|
.text
.global iwmmxt
iwmmxt:
tandcb r15
TANDCHLE r15
TANDCWge r15
TBCSTBlt wr0, r1
tbcsth wr1, r2
TBCSTWGT wr2, r3
textrcb r15, #7
textrcheq r15, #2
TEXTRCW r15, #0
TEXTRMUB r14, wr3, #6
textrmsbne r13, wr4, #5
textrmUH r12, wr5, #2
textrmSh r11, wr6, #0
TEXTRMUWcs r10, wr7, #1
textrmswhs r9, wr8, #0
TINSRB wr9, r8, #4
tinsrhcc wr10, r7, #0
tinsrw wr11, r6, #1
tmcrul wcid, r5
TMCRR wr12, r6, r7
tmialo wr13, r5, r4
tmiaphMI wr14, r3, r2
TMIAbb wr15, r0, r1
TMIAbTpl wr13, r2, r3
tmiaBtvs wr1, r4, r5
tmiaTTvc wr2, r6, r7
tmovmskB r8, wr3
TMOVMSKHhi r9, wr4
tmovmskwls r10, wr5
tmrc r11, wcon
TMRRCge r12, r13, wr6
torcb r15
torchlt r15
TORCW r15
waccb wr7, wr8
WACCHlt wr9, wr10
WACCWGT wr11, wr12
waddble wr13, wr14, wr15
waddBUS wr0, wr2, wr4
waddbssal wr6, wr8, wr10
waddH wr12, wr14, wr15
WADDHUSLE wr13, wr12, wr11
WADDHSSeq wr10, wr9, wr8
WADDWne wr7, wr6, wr5
waddwus wr4, wr3, wr2
waddwsscs wr1, wr0, wr15
waligni wr3, wr5, wr7, #5
WALIGNR0hs wr9, wr11, wr13
walignr1 wr7, wr6, wr5
walignr2cc wr2, wr4, wr8
WALIGNR3ul wr5, wr9, wr1
wand wr3, wr8, wr1
wandn wr3, wr2, wr6
wavg2b wr7, wr8, wr9
wavg2hle wr10, wr11, wr12
wavg2brge wr13, wr14, wr15
wavg2hr wr0, wr1, wr12
wcmpeqb wr13, wr4, wr5
wcmpeqheq wr4, wr7, wr0
wcmpeqWlt wr6, wr9, wr8
wcmpgtUbul wr1, wr2, wr3
wcmpgtsb wr4, wr5, wr6
wcmpgtuhcc wr7, wr8, wr9
wcmpgtsh wr10, wr11, wr13
wcmpgtuw wr2, wr4, wr3
wcmpgtswhi wr5, wr6, wr3
wldrb wr1, [r0, #36]
wldrheq wr2, [r1, #24]!
wldrwne wr3, [r2], #16
wldrdvs wr4, [r3, #-332]
wldrw wcssf, [r1, #20]!
wmacu wr4, wr7, wr9
wmacscs wr8, wr10, wr14
wmacuzal wr15, wr12, wr11
wmacsz wr3, wr8, wr10
wmaddu wr12, wr11, wr7
wmaddsgt wr5, wr3, wr15
wmaxubhs wr3, wr4, wr5
wmaxsb wr3, wr4, wr5
wmaxuhpl wr3, wr4, wr5
wmaxshmi wr3, wr4, wr5
wmaxuwge wr3, wr4, wr5
wmaxswle wr3, wr4, wr5
wminubul wr4, wr12, wr10
wminsb wr4, wr12, wr10
wminuhvc wr4, wr12, wr10
wminsh wr4, wr12, wr10
wminuw wr4, wr12, wr10
wminswcc wr4, wr12, wr10
wmoveq wr3, wr4
wmulum wr2, wr1, wr8
wmulsm wr2, wr1, wr8
wmulul wr2, wr1, wr8
wmulslle wr2, wr1, wr8
woreq wr11, wr8, wr14
wpackhuseq wr0, wr1, wr3
wpackwus wr0, wr1, wr3
wpackdusal wr0, wr1, wr3
wpackhsshi wr0, wr1, wr3
wpackwss wr0, wr1, wr3
wpackdsseq wr0, wr1, wr3
wrorh wr4, wr5, wr6
wrorwmi wr4, wr5, wr6
wrord wr4, wr5, wr6
wrorhg wr9, wr10, wcgr0
wrorwgge wr9, wr10, wcgr1
wrordg wr9, wr10, wcgr2
wsadb wr2, wr0, wr10
wsadhal wr2, wr0, wr10
wsadbz wr2, wr0, wr10
wsadhzle wr2, wr0, wr10
wshufheq wr4, wr9, #251
wsllh wr2, wr9, wr4
wsllw wr2, wr9, wr4
wslldeq wr2, wr9, wr4
wsllhgeq wr2, wr9, wcgr3
wsllwgvc wr2, wr9, wcgr2
wslldg wr2, wr9, wcgr1
wsrah wr1, wr5, wr7
wsraw wr1, wr5, wr7
wsradeq wr1, wr5, wr7
wsrahg wr1, wr5, wcgr3
wsrawgmi wr1, wr5, wcgr0
wsradg wr1, wr5, wcgr1
wsrlh wr1, wr5, wr7
wsrlw wr1, wr5, wr7
wsrldeq wr1, wr5, wr7
wsrlhg wr1, wr5, wcgr3
wsrlwgmi wr1, wr5, wcgr0
wsrldg wr1, wr5, wcgr1
wstrb wr1, [r1, #0xFF]
wstrh wr1, [r1, #-0xFF]!
wstrw wr1, [r1], #4
wstrd wr1, [r1, #0x3FC]
wstrw wcasf, [r1], #300
wsubbusul wr1, wr3, wr14
wsubhus wr1, wr3, wr14
wsubwusul wr1, wr3, wr14
wsubbssul wr1, wr3, wr14
wsubhssul wr1, wr3, wr14
wsubwss wr1, wr3, wr14
wunpckehub wr3, wr6
wunpckehuhmi wr3, wr6
wunpckehuw wr3, wr6
wunpckehsb wr3, wr6
wunpckehsh wr3, wr6
wunpckehsweq wr3, wr6
wunpckihb wr5, wr12, wr10
wunpckihhhi wr5, wr12, wr10
wunpckihw wr5, wr12, wr10
wunpckelub wr3, wr5
wunpckeluhne wr3, wr5
wunpckeluw wr3, wr5
wunpckelsbgt wr3, wr5
wunpckelsh wr3, wr5
wunpckelsw wr3, wr5
wunpckilb wr4, wr5, wr10
wunpckilh wr4, wr5, wr10
wunpckilweq wr4, wr5, wr10
wxorne wr3, wr4, wr5
wzeroge wr7
tmcr wcgr0, r0
tmrc r1, wcgr2
@ a.out-required section size padding
nop
|
tactcomplabs/xbgas-binutils-gdb
| 4,160
|
gas/testsuite/gas/arm/mve-vmov-3.s
|
vmov r0, r1, q1[2], q1[0]
vmov r0, r1, q2[2], q2[0]
vmov r0, r1, q3[2], q3[0]
vmov r0, r1, q4[2], q4[0]
vmov r0, r1, q5[2], q5[0]
vmov r0, r1, q6[2], q6[0]
vmov r0, r1, q7[2], q7[0]
vmov r1, r0, q0[2], q0[0]
vmov r2, r0, q0[2], q0[0]
vmov r3, r0, q0[2], q0[0]
vmov r4, r0, q0[2], q0[0]
vmov r5, r0, q0[2], q0[0]
vmov r6, r0, q0[2], q0[0]
vmov r7, r0, q0[2], q0[0]
vmov r8, r0, q0[2], q0[0]
vmov r9, r0, q0[2], q0[0]
vmov sl, r0, q0[2], q0[0]
vmov fp, r0, q0[2], q0[0]
vmov ip, r0, q0[2], q0[0]
vmov lr, r0, q0[2], q0[0]
vmov r0, r1, q0[2], q0[0]
vmov r0, r2, q0[2], q0[0]
vmov r0, r3, q0[2], q0[0]
vmov r0, r4, q0[2], q0[0]
vmov r0, r5, q0[2], q0[0]
vmov r0, r6, q0[2], q0[0]
vmov r0, r7, q0[2], q0[0]
vmov r0, r8, q0[2], q0[0]
vmov r0, r9, q0[2], q0[0]
vmov r0, sl, q0[2], q0[0]
vmov r0, fp, q0[2], q0[0]
vmov r0, ip, q0[2], q0[0]
vmov r0, lr, q0[2], q0[0]
vmov r0, r1, q1[3], q1[1]
vmov r0, r1, q2[3], q2[1]
vmov r0, r1, q3[3], q3[1]
vmov r0, r1, q4[3], q4[1]
vmov r0, r1, q5[3], q5[1]
vmov r0, r1, q6[3], q6[1]
vmov r0, r1, q7[3], q7[1]
vmov r1, r0, q0[3], q0[1]
vmov r2, r0, q0[3], q0[1]
vmov r3, r0, q0[3], q0[1]
vmov r4, r0, q0[3], q0[1]
vmov r5, r0, q0[3], q0[1]
vmov r6, r0, q0[3], q0[1]
vmov r7, r0, q0[3], q0[1]
vmov r8, r0, q0[3], q0[1]
vmov r9, r0, q0[3], q0[1]
vmov sl, r0, q0[3], q0[1]
vmov fp, r0, q0[3], q0[1]
vmov ip, r0, q0[3], q0[1]
vmov lr, r0, q0[3], q0[1]
vmov r0, r1, q0[3], q0[1]
vmov r0, r2, q0[3], q0[1]
vmov r0, r3, q0[3], q0[1]
vmov r0, r4, q0[3], q0[1]
vmov r0, r5, q0[3], q0[1]
vmov r0, r6, q0[3], q0[1]
vmov r0, r7, q0[3], q0[1]
vmov r0, r8, q0[3], q0[1]
vmov r0, r9, q0[3], q0[1]
vmov r0, sl, q0[3], q0[1]
vmov r0, fp, q0[3], q0[1]
vmov r0, ip, q0[3], q0[1]
vmov r0, lr, q0[3], q0[1]
vmov q1[2], q1[0], r0, r1
vmov q2[2], q2[0], r0, r1
vmov q3[2], q3[0], r0, r1
vmov q4[2], q4[0], r0, r1
vmov q5[2], q5[0], r0, r1
vmov q6[2], q6[0], r0, r1
vmov q7[2], q7[0], r0, r1
vmov q0[2], q0[0], r0, r0
vmov q0[2], q0[0], r1, r0
vmov q0[2], q0[0], r2, r0
vmov q0[2], q0[0], r3, r0
vmov q0[2], q0[0], r4, r0
vmov q0[2], q0[0], r5, r0
vmov q0[2], q0[0], r6, r0
vmov q0[2], q0[0], r7, r0
vmov q0[2], q0[0], r8, r0
vmov q0[2], q0[0], r9, r0
vmov q0[2], q0[0], sl, r0
vmov q0[2], q0[0], fp, r0
vmov q0[2], q0[0], ip, r0
vmov q0[2], q0[0], lr, r0
vmov q0[2], q0[0], r0, r1
vmov q0[2], q0[0], r0, r2
vmov q0[2], q0[0], r0, r3
vmov q0[2], q0[0], r0, r4
vmov q0[2], q0[0], r0, r5
vmov q0[2], q0[0], r0, r6
vmov q0[2], q0[0], r0, r7
vmov q0[2], q0[0], r0, r8
vmov q0[2], q0[0], r0, r9
vmov q0[2], q0[0], r0, sl
vmov q0[2], q0[0], r0, fp
vmov q0[2], q0[0], r0, ip
vmov q0[2], q0[0], r0, lr
vmov q0[2], q0[0], r1, r1
vmov q0[2], q0[0], r2, r2
vmov q0[2], q0[0], r3, r3
vmov q0[2], q0[0], r4, r4
vmov q0[2], q0[0], r5, r5
vmov q0[2], q0[0], r6, r6
vmov q0[2], q0[0], r7, r7
vmov q0[2], q0[0], r8, r8
vmov q0[2], q0[0], r9, r9
vmov q0[2], q0[0], sl, sl
vmov q0[2], q0[0], fp, fp
vmov q0[2], q0[0], ip, ip
vmov q0[2], q0[0], lr, lr
vmov q1[3], q1[1], r0, r1
vmov q2[3], q2[1], r0, r1
vmov q3[3], q3[1], r0, r1
vmov q4[3], q4[1], r0, r1
vmov q5[3], q5[1], r0, r1
vmov q6[3], q6[1], r0, r1
vmov q7[3], q7[1], r0, r1
vmov q0[3], q0[1], r0, r0
vmov q0[3], q0[1], r1, r0
vmov q0[3], q0[1], r2, r0
vmov q0[3], q0[1], r3, r0
vmov q0[3], q0[1], r4, r0
vmov q0[3], q0[1], r5, r0
vmov q0[3], q0[1], r6, r0
vmov q0[3], q0[1], r7, r0
vmov q0[3], q0[1], r8, r0
vmov q0[3], q0[1], r9, r0
vmov q0[3], q0[1], sl, r0
vmov q0[3], q0[1], fp, r0
vmov q0[3], q0[1], ip, r0
vmov q0[3], q0[1], lr, r0
vmov q0[3], q0[1], r0, r1
vmov q0[3], q0[1], r0, r2
vmov q0[3], q0[1], r0, r3
vmov q0[3], q0[1], r0, r4
vmov q0[3], q0[1], r0, r5
vmov q0[3], q0[1], r0, r6
vmov q0[3], q0[1], r0, r7
vmov q0[3], q0[1], r0, r8
vmov q0[3], q0[1], r0, r9
vmov q0[3], q0[1], r0, sl
vmov q0[3], q0[1], r0, fp
vmov q0[3], q0[1], r0, ip
vmov q0[3], q0[1], r0, lr
vmov q0[3], q0[1], r1, r1
vmov q0[3], q0[1], r2, r2
vmov q0[3], q0[1], r3, r3
vmov q0[3], q0[1], r4, r4
vmov q0[3], q0[1], r5, r5
vmov q0[3], q0[1], r6, r6
vmov q0[3], q0[1], r7, r7
vmov q0[3], q0[1], r8, r8
vmov q0[3], q0[1], r9, r9
vmov q0[3], q0[1], sl, sl
vmov q0[3], q0[1], fp, fp
vmov q0[3], q0[1], ip, ip
vmov q0[3], q0[1], lr, lr
|
tactcomplabs/xbgas-binutils-gdb
| 13,442
|
gas/testsuite/gas/arm/neon-cov.s
|
@ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
@ possible, but without causing instructions to be badly-formed.
.arm
.syntax unified
.text
.macro regs3_1 op opq vtype
\op\vtype q0,q0,q0
\opq\vtype q0,q0,q0
\op\vtype d0,d0,d0
.endm
.macro dregs3_1 op vtype
\op\vtype d0,d0,d0
.endm
.macro regn3_1 op operand2 vtype
\op\vtype d0,q0,\operand2
.endm
.macro regl3_1 op operand2 vtype
\op\vtype q0,d0,\operand2
.endm
.macro regw3_1 op operand2 vtype
\op\vtype q0,q0,\operand2
.endm
.macro regs2_1 op opq vtype
\op\vtype q0,q0
\opq\vtype q0,q0
\op\vtype d0,d0
.endm
.macro regs3_su_32 op opq
regs3_1 \op \opq .s8
regs3_1 \op \opq .s16
regs3_1 \op \opq .s32
regs3_1 \op \opq .u8
regs3_1 \op \opq .u16
regs3_1 \op \opq .u32
.endm
regs3_su_32 vaba vabaq
regs3_su_32 vhadd vhaddq
regs3_su_32 vrhadd vrhaddq
regs3_su_32 vhsub vhsubq
.macro regs3_su_64 op opq
regs3_1 \op \opq .s8
regs3_1 \op \opq .s16
regs3_1 \op \opq .s32
regs3_1 \op \opq .s64
regs3_1 \op \opq .u8
regs3_1 \op \opq .u16
regs3_1 \op \opq .u32
regs3_1 \op \opq .u64
.endm
regs3_su_64 vqadd vqaddq
regs3_su_64 vqsub vqsubq
regs3_su_64 vrshl vrshlq
regs3_su_64 vqrshl vqrshlq
regs3_su_64 vshl vshlq
regs3_su_64 vqshl vqshlq
.macro regs2i_1 op opq imm vtype
\op\vtype q0,q0,\imm
\opq\vtype q0,q0,\imm
\op\vtype d0,d0,\imm
.endm
.macro regs2i_su_64 op opq imm
regs2i_1 \op \opq \imm .s8
regs2i_1 \op \opq \imm .s16
regs2i_1 \op \opq \imm .s32
regs2i_1 \op \opq \imm .s64
regs2i_1 \op \opq \imm .u8
regs2i_1 \op \opq \imm .u16
regs2i_1 \op \opq \imm .u32
regs2i_1 \op \opq \imm .u64
.endm
.macro regs2i_i_64 op opq imm
regs2i_1 \op \opq \imm .i8
regs2i_1 \op \opq \imm .i16
regs2i_1 \op \opq \imm .i32
regs2i_1 \op \opq \imm .s32
regs2i_1 \op \opq \imm .u32
regs2i_1 \op \opq \imm .i64
.endm
regs2i_i_64 vshl vshlq 0
regs2i_su_64 vqshl vqshlq 0
.macro regs3_ntyp op opq
regs3_1 \op \opq .8
.endm
regs3_ntyp vand vandq
regs3_ntyp vbic vbicq
regs3_ntyp vorr vorrq
regs3_ntyp vorn vornq
regs3_ntyp veor veorq
.macro logic_imm_1 op opq imm vtype
\op\vtype q0,\imm
\opq\vtype q0,\imm
\op\vtype d0,\imm
.endm
.macro logic_imm op opq
logic_imm_1 \op \opq 0x000000a5000000a5 .i64
logic_imm_1 \op \opq 0x0000a5000000a500 .i64
logic_imm_1 \op \opq 0x00a5000000a50000 .i64
logic_imm_1 \op \opq 0xa5000000a5000000 .i64
logic_imm_1 \op \opq 0x00a500a500a500a5 .i64
logic_imm_1 \op \opq 0xa500a500a500a500 .i64
logic_imm_1 \op \opq 0x000000ff .i32
logic_imm_1 \op \opq 0x000000ff .s32
logic_imm_1 \op \opq 0x000000ff .u32
logic_imm_1 \op \opq 0x0000ff00 .i32
logic_imm_1 \op \opq 0x00ff0000 .i32
logic_imm_1 \op \opq 0xff000000 .i32
logic_imm_1 \op \opq 0x00a500a5 .i32
logic_imm_1 \op \opq 0xa500a500 .i32
logic_imm_1 \op \opq 0x00ff .i16
logic_imm_1 \op \opq 0xff00 .i16
logic_imm_1 \op \opq 0x00 .i8
.endm
logic_imm vbic vbicq
logic_imm vorr vorrq
.macro logic_inv_imm op opq
logic_imm_1 \op \opq 0xffffff5affffff5a .i64
logic_imm_1 \op \opq 0xffff5affffff5aff .i64
logic_imm_1 \op \opq 0xff5affffff5affff .i64
logic_imm_1 \op \opq 0x5affffff5affffff .i64
logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64
logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64
logic_imm_1 \op \opq 0xffffff00 .i32
logic_imm_1 \op \opq 0xffffff00 .s32
logic_imm_1 \op \opq 0xffffff00 .u32
logic_imm_1 \op \opq 0xffff00ff .i32
logic_imm_1 \op \opq 0xff00ffff .i32
logic_imm_1 \op \opq 0x00ffffff .i32
logic_imm_1 \op \opq 0xff5aff5a .i32
logic_imm_1 \op \opq 0x5aff5aff .i32
logic_imm_1 \op \opq 0xff00 .i16
logic_imm_1 \op \opq 0x00ff .i16
logic_imm_1 \op \opq 0xff .i8
.endm
logic_inv_imm vand vandq
logic_inv_imm vorn vornq
regs3_ntyp vbsl vbslq
regs3_ntyp vbit vbitq
regs3_ntyp vbif vbifq
.macro regs3_suf_32 op opq
regs3_1 \op \opq .s8
regs3_1 \op \opq .s16
regs3_1 \op \opq .s32
regs3_1 \op \opq .u8
regs3_1 \op \opq .u16
regs3_1 \op \opq .u32
regs3_1 \op \opq .f32
.endm
.macro regs3_if_32 op opq
regs3_1 \op \opq .i8
regs3_1 \op \opq .i16
regs3_1 \op \opq .i32
regs3_1 \op \opq .s32
regs3_1 \op \opq .u32
regs3_1 \op \opq .f32
.endm
regs3_suf_32 vabd vabdq
regs3_suf_32 vmax vmaxq
regs3_suf_32 vmin vminq
regs3_suf_32 vcge vcgeq
regs3_suf_32 vcgt vcgtq
regs3_suf_32 vcle vcleq
regs3_suf_32 vclt vcltq
regs3_if_32 vceq vceqq
.macro regs2i_sf_0 op opq
regs2i_1 \op \opq 0 .s8
regs2i_1 \op \opq 0 .s16
regs2i_1 \op \opq 0 .s32
regs2i_1 \op \opq 0 .f32
.endm
regs2i_sf_0 vcge vcgeq
regs2i_sf_0 vcgt vcgtq
regs2i_sf_0 vcle vcleq
regs2i_sf_0 vclt vcltq
.macro regs2i_if_0 op opq
regs2i_1 \op \opq 0 .i8
regs2i_1 \op \opq 0 .i16
regs2i_1 \op \opq 0 .i32
regs2i_1 \op \opq 0 .s32
regs2i_1 \op \opq 0 .u32
regs2i_1 \op \opq 0 .f32
.endm
regs2i_if_0 vceq vceqq
.macro dregs3_suf_32 op
dregs3_1 \op .s8
dregs3_1 \op .s16
dregs3_1 \op .s32
dregs3_1 \op .u8
dregs3_1 \op .u16
dregs3_1 \op .u32
dregs3_1 \op .f32
.endm
dregs3_suf_32 vpmax
dregs3_suf_32 vpmin
.macro sregs3_1 op opq vtype
\op\vtype q0,q0,q0
\opq\vtype q0,q0,q0
\op\vtype d0,d0,d0
.endm
.macro sclr21_1 op opq vtype
\op\vtype q0,q0,d0[0]
\opq\vtype q0,q0,d0[0]
\op\vtype d0,d0,d0[0]
.endm
.macro mul_incl_scalar op opq
regs3_1 \op \opq .i8
regs3_1 \op \opq .i16
regs3_1 \op \opq .i32
regs3_1 \op \opq .s32
regs3_1 \op \opq .u32
regs3_1 \op \opq .f32
sclr21_1 \op \opq .i16
sclr21_1 \op \opq .i32
sclr21_1 \op \opq .s32
sclr21_1 \op \opq .u32
sclr21_1 \op \opq .f32
.endm
mul_incl_scalar vmla vmlaq
mul_incl_scalar vmls vmlsq
.macro dregs3_if_32 op
dregs3_1 \op .i8
dregs3_1 \op .i16
dregs3_1 \op .i32
dregs3_1 \op .s32
dregs3_1 \op .u32
dregs3_1 \op .f32
.endm
dregs3_if_32 vpadd
.macro regs3_if_64 op opq
regs3_1 \op \opq .i8
regs3_1 \op \opq .i16
regs3_1 \op \opq .i32
regs3_1 \op \opq .s32
regs3_1 \op \opq .u32
regs3_1 \op \opq .i64
regs3_1 \op \opq .f32
.endm
regs3_if_64 vadd vaddq
regs3_if_64 vsub vsubq
.macro regs3_sz_32 op opq
regs3_1 \op \opq .8
regs3_1 \op \opq .16
regs3_1 \op \opq .32
.endm
regs3_sz_32 vtst vtstq
.macro regs3_ifp_32 op opq
regs3_1 \op \opq .i8
regs3_1 \op \opq .i16
regs3_1 \op \opq .i32
regs3_1 \op \opq .s32
regs3_1 \op \opq .u32
regs3_1 \op \opq .f32
regs3_1 \op \opq .p8
.endm
regs3_ifp_32 vmul vmulq
.macro dqmulhs op opq
regs3_1 \op \opq .s16
regs3_1 \op \opq .s32
sclr21_1 \op \opq .s16
sclr21_1 \op \opq .s32
.endm
dqmulhs vqdmulh vqdmulhq
dqmulhs vqrdmulh vqrdmulhq
regs3_1 vacge vacgeq .f32
regs3_1 vacgt vacgtq .f32
regs3_1 vacle vacleq .f32
regs3_1 vaclt vacltq .f32
regs3_1 vrecps vrecpsq .f32
regs3_1 vrsqrts vrsqrtsq .f32
.macro regs2_sf_32 op opq
regs2_1 \op \opq .s8
regs2_1 \op \opq .s16
regs2_1 \op \opq .s32
regs2_1 \op \opq .f32
.endm
regs2_sf_32 vabs vabsq
regs2_sf_32 vneg vnegq
.macro rshift_imm op opq
regs2i_1 \op \opq 7 .s8
regs2i_1 \op \opq 15 .s16
regs2i_1 \op \opq 31 .s32
regs2i_1 \op \opq 63 .s64
regs2i_1 \op \opq 7 .u8
regs2i_1 \op \opq 15 .u16
regs2i_1 \op \opq 31 .u32
regs2i_1 \op \opq 63 .u64
.endm
rshift_imm vshr vshrq
rshift_imm vrshr vrshrq
rshift_imm vsra vsraq
rshift_imm vrsra vrsraq
regs2i_1 vsli vsliq 0 .8
regs2i_1 vsli vsliq 0 .16
regs2i_1 vsli vsliq 0 .32
regs2i_1 vsli vsliq 0 .64
regs2i_1 vsri vsriq 7 .8
regs2i_1 vsri vsriq 15 .16
regs2i_1 vsri vsriq 31 .32
regs2i_1 vsri vsriq 63 .64
regs2i_1 vqshlu vqshluq 0 .s8
regs2i_1 vqshlu vqshluq 0 .s16
regs2i_1 vqshlu vqshluq 0 .s32
regs2i_1 vqshlu vqshluq 0 .s64
.macro qrshift_imm op
regn3_1 \op 7 .s16
regn3_1 \op 15 .s32
regn3_1 \op 31 .s64
regn3_1 \op 7 .u16
regn3_1 \op 15 .u32
regn3_1 \op 31 .u64
.endm
.macro qrshiftu_imm op
regn3_1 \op 7 .s16
regn3_1 \op 15 .s32
regn3_1 \op 31 .s64
.endm
.macro qrshifti_imm op
regn3_1 \op 7 .i16
regn3_1 \op 15 .i32
regn3_1 \op 15 .s32
regn3_1 \op 15 .u32
regn3_1 \op 31 .i64
.endm
qrshift_imm vqshrn
qrshift_imm vqrshrn
qrshiftu_imm vqshrun
qrshiftu_imm vqrshrun
qrshifti_imm vshrn
qrshifti_imm vrshrn
regl3_1 vshll 1 .s8
regl3_1 vshll 1 .s16
regl3_1 vshll 1 .s32
regl3_1 vshll 1 .u8
regl3_1 vshll 1 .u16
regl3_1 vshll 1 .u32
regl3_1 vshll 8 .i8
regl3_1 vshll 16 .i16
regl3_1 vshll 32 .i32
regl3_1 vshll 32 .s32
regl3_1 vshll 32 .u32
.macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
\op\t1 \opr,\opr\arg
\op\t2 \opr,\opr\arg
\op\t3 \opr,\opr\arg
\op\t4 \opr,\opr\arg
.endm
convert vcvt q0
convert vcvtq q0
convert vcvt d0
convert vcvt q0 ",1"
convert vcvtq q0 ",1"
convert vcvt d0 ",1"
vmov q0,q0
vmov d0,d0
vmov.8 d0[0],r0
vmov.16 d0[0],r0
vmov.32 d0[0],r0
vmov d0,r0,r0
vmov.s8 r0,d0[0]
vmov.s16 r0,d0[0]
vmov.u8 r0,d0[0]
vmov.u16 r0,d0[0]
vmov.32 r0,d0[0]
vmov r0,r1,d0
.macro mov_imm op imm vtype
\op\vtype q0,\imm
\op\vtype d0,\imm
.endm
mov_imm vmov 0x00000077 .i32
mov_imm vmov 0x00000077 .s32
mov_imm vmov 0x00000077 .u32
mov_imm vmvn 0x00000077 .i32
mov_imm vmvn 0x00000077 .s32
mov_imm vmvn 0x00000077 .u32
mov_imm vmov 0x00007700 .i32
mov_imm vmvn 0x00007700 .i32
mov_imm vmov 0x00770000 .i32
mov_imm vmvn 0x00770000 .i32
mov_imm vmov 0x77000000 .i32
mov_imm vmvn 0x77000000 .i32
mov_imm vmov 0x0077 .i16
mov_imm vmvn 0x0077 .i16
mov_imm vmov 0x7700 .i16
mov_imm vmvn 0x7700 .i16
mov_imm vmov 0x000077ff .i32
mov_imm vmvn 0x000077ff .i32
mov_imm vmov 0x0077ffff .i32
mov_imm vmvn 0x0077ffff .i32
mov_imm vmov 0x77 .i8
mov_imm vmov 0xff0000ff000000ff .i64
mov_imm vmov 4.25 .f32
mov_imm vmov 0xa5a5 .i16
mov_imm vmvn 0xa5a5 .i16
mov_imm vmov 0xa5a5a5a5 .i32
mov_imm vmvn 0xa5a5a5a5 .i32
mov_imm vmov 0x00a500a5 .i32
mov_imm vmov 0xa500a500 .i32
mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64
mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64
mov_imm vmov 0x00a500a500a500a5 .i64
mov_imm vmov 0xa500a500a500a500 .i64
mov_imm vmov 0x000000a5000000a5 .i64
mov_imm vmov 0x0000a5000000a500 .i64
mov_imm vmov 0x00a5000000a50000 .i64
mov_imm vmov 0xa5000000a5000000 .i64
mov_imm vmov 0x0000a5ff0000a5ff .i64
mov_imm vmov 0x00a5ffff00a5ffff .i64
mov_imm vmov 0xa5ffffffa5ffffff .i64
vmvn q0,q0
vmvnq q0,q0
vmvn d0,d0
.macro long_ops op
regl3_1 \op d0 .s8
regl3_1 \op d0 .s16
regl3_1 \op d0 .s32
regl3_1 \op d0 .u8
regl3_1 \op d0 .u16
regl3_1 \op d0 .u32
.endm
long_ops vabal
long_ops vabdl
long_ops vaddl
long_ops vsubl
.macro long_mac op
regl3_1 \op d0 .s8
regl3_1 \op d0 .s16
regl3_1 \op d0 .s32
regl3_1 \op d0 .u8
regl3_1 \op d0 .u16
regl3_1 \op d0 .u32
regl3_1 \op "d0[0]" .s16
regl3_1 \op "d0[0]" .s32
regl3_1 \op "d0[0]" .u16
regl3_1 \op "d0[0]" .u32
.endm
long_mac vmlal
long_mac vmlsl
.macro wide_ops op
regw3_1 \op d0 .s8
regw3_1 \op d0 .s16
regw3_1 \op d0 .s32
regw3_1 \op d0 .u8
regw3_1 \op d0 .u16
regw3_1 \op d0 .u32
.endm
wide_ops vaddw
wide_ops vsubw
.macro narr_ops op
regn3_1 \op q0 .i16
regn3_1 \op q0 .i32
regn3_1 \op q0 .s32
regn3_1 \op q0 .u32
regn3_1 \op q0 .i64
.endm
narr_ops vaddhn
narr_ops vraddhn
narr_ops vsubhn
narr_ops vrsubhn
.macro long_dmac op
regl3_1 \op d0 .s16
regl3_1 \op d0 .s32
regl3_1 \op "d0[0]" .s16
regl3_1 \op "d0[0]" .s32
.endm
long_dmac vqdmlal
long_dmac vqdmlsl
long_dmac vqdmull
regl3_1 vmull d0 .s8
regl3_1 vmull d0 .s16
regl3_1 vmull d0 .s32
regl3_1 vmull d0 .u8
regl3_1 vmull d0 .u16
regl3_1 vmull d0 .u32
regl3_1 vmull d0 .p8
regl3_1 vmull "d0[0]" .s16
regl3_1 vmull "d0[0]" .s32
regl3_1 vmull "d0[0]" .u16
regl3_1 vmull "d0[0]" .u32
vext.8 q0,q0,q0,0
vextq.8 q0,q0,q0,0
vext.8 d0,d0,d0,0
vext.8 q0,q0,q0,8
.macro revs op opq vtype
\op\vtype q0,q0
\opq\vtype q0,q0
\op\vtype d0,d0
.endm
revs vrev64 vrev64q .8
revs vrev64 vrev64q .16
revs vrev64 vrev64q .32
revs vrev32 vrev32q .8
revs vrev32 vrev32q .16
revs vrev16 vrev16q .8
.macro dups op opq vtype
\op\vtype q0,r0
\opq\vtype q0,r0
\op\vtype d0,r0
\op\vtype q0,d0[0]
\opq\vtype q0,d0[0]
\op\vtype d0,d0[0]
.endm
dups vdup vdupq .8
dups vdup vdupq .16
dups vdup vdupq .32
.macro binop_3typ op op1 op2 t1 t2 t3
\op\t1 \op1,\op2
\op\t2 \op1,\op2
\op\t3 \op1,\op2
.endm
binop_3typ vmovl q0 d0 .s8 .s16 .s32
binop_3typ vmovl q0 d0 .u8 .u16 .u32
binop_3typ vmovn d0 q0 .i16 .i32 .i64
vmovn.s32 d0, q0
vmovn.u32 d0, q0
binop_3typ vqmovn d0 q0 .s16 .s32 .s64
binop_3typ vqmovn d0 q0 .u16 .u32 .u64
binop_3typ vqmovun d0 q0 .s16 .s32 .s64
.macro binops op opq vtype="" rhs="0"
\op\vtype q0,q\rhs
\opq\vtype q0,q\rhs
\op\vtype d0,d\rhs
.endm
.macro regs2_sz_32 op opq
binops \op \opq .8 1
binops \op \opq .16 1
binops \op \opq .32 1
.endm
regs2_sz_32 vzip vzipq
regs2_sz_32 vuzp vuzpq
.macro regs2_s_32 op opq
binops \op \opq .s8
binops \op \opq .s16
binops \op \opq .s32
.endm
regs2_s_32 vqabs vqabsq
regs2_s_32 vqneg vqnegq
.macro regs2_su_32 op opq
regs2_s_32 \op \opq
binops \op \opq .u8
binops \op \opq .u16
binops \op \opq .u32
.endm
regs2_su_32 vpadal vpadalq
regs2_su_32 vpaddl vpaddlq
binops vrecpe vrecpeq .u32
binops vrecpe vrecpeq .f32
binops vrsqrte vrsqrteq .u32
binops vrsqrte vrsqrteq .f32
regs2_s_32 vcls vclsq
.macro regs2_i_32 op opq
binops \op \opq .i8
binops \op \opq .i16
binops \op \opq .i32
binops \op \opq .s32
binops \op \opq .u32
.endm
regs2_i_32 vclz vclzq
binops vcnt vcntq .8
binops vswp vswpq "" 1
regs2_sz_32 vtrn vtrnq
vtbl.8 d0,{d0},d0
vtbx.8 d0,{d0},d0
|
tactcomplabs/xbgas-binutils-gdb
| 2,093
|
gas/testsuite/gas/arm/mve-vldr-bad-1.s
|
.macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vldrb.16 q0, [r0, q1]
vldrb.p16 q0, [r0, q1]
vldrb.f16 q0, [r0, q1]
vldrb.32 q0, [r0, q1]
vldrb.f32 q0, [r0, q1]
vldrb.64 q0, [r0, q1]
vldrb.u64 q0, [r0, q1]
vldrb.s64 q0, [r0, q1]
vldrb.u32 q0, [pc, q1]
vldrb.u32 q0, [r0, q0]
cond vldrb
it eq
vldrbeq.u32 q0, [r0, q1]
vldrbeq.u32 q0, [r0, q1]
vpst
vldrbeq.u32 q0, [r0, q1]
vldrbt.u32 q0, [r0, q1]
vpst
vldrb.u32 q0, [r0, q1]
vldrh.32 q0, [r0, q1]
vldrh.f32 q0, [r0, q1]
vldrh.64 q0, [r0, q1]
vldrh.u64 q0, [r0, q1]
vldrh.s64 q0, [r0, q1]
vldrh.u32 q0, [pc, q1]
vldrh.u32 q0, [r0, q0]
cond vldrh
it eq
vldrheq.u32 q0, [r0, q1]
vldrheq.u32 q0, [r0, q1]
vpst
vldrheq.u32 q0, [r0, q1]
vldrht.u32 q0, [r0, q1]
vpst
vldrh.u32 q0, [r0, q1]
vldrw.64 q0, [r0, q1]
vldrw.u64 q0, [r0, q1]
vldrw.s64 q0, [r0, q1]
vldrw.u32 q0, [pc, q1]
vldrw.u32 q0, [r0, q0]
cond vldrw
it eq
vldrweq.u32 q0, [r0, q1]
vldrweq.u32 q0, [r0, q1]
vpst
vldrweq.u32 q0, [r0, q1]
vldrwt.u32 q0, [r0, q1]
vpst
vldrw.u32 q0, [r0, q1]
.macro cond64
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vldrd.u64 q0, [r0, q1]
.endr
.endm
vldrd.8 q0, [r0, q1]
vldrd.u8 q0, [r0, q1]
vldrd.s8 q0, [r0, q1]
vldrd.p8 q0, [r0, q1]
vldrd.16 q0, [r0, q1]
vldrd.u16 q0, [r0, q1]
vldrd.s16 q0, [r0, q1]
vldrd.p16 q0, [r0, q1]
vldrd.f16 q0, [r0, q1]
vldrd.32 q0, [r0, q1]
vldrd.u32 q0, [r0, q1]
vldrd.s32 q0, [r0, q1]
vldrd.f32 q0, [r0, q1]
cond64
it eq
vldrdeq.u64 q0, [r0, q1]
vldrdeq.u64 q0, [r0, q1]
vpst
vldrdeq.u64 q0, [r0, q1]
vldrdt.u64 q0, [r0, q1]
vpst
vldrd.u64 q0, [r0, q1]
vldrb.u8 q0, [r0, q1, #0]
vldrb.u8 q0, [r0, q1, UXTW #1]
vldrb.u16 q0, [r0, q1, UXTW #1]
vldrb.u32 q0, [r0, q1, UXTW #1]
vldrh.u16 q0, [r0, q1, #1]
vldrh.u16 q0, [r0, q1, UXTW #2]
vldrh.u32 q0, [r0, q1, UXTW #2]
vldrh.u16 q0, [r0, q1, UXTW #3]
vldrh.u32 q0, [r0, q1, UXTW #3]
vldrw.u32 q0, [r0, q1, #2]
vldrw.u32 q0, [r0, q1, UXTW #1]
vldrw.u32 q0, [r0, q1, UXTW #3]
vldrd.u64 q0, [r0, q1, #3]
vldrd.u64 q0, [r0, q1, UXTW #1]
vldrd.u64 q0, [r0, q1, UXTW #2]
vldrd.u64 q0, [r0, q1, UXTW #4]
|
tactcomplabs/xbgas-binutils-gdb
| 1,716
|
gas/testsuite/gas/arm/armv8-ar.s
|
.syntax unified
.text
.arch armv8-a
.arm
foo:
sevl
hlt 0x0
hlt 0xf
hlt 0xfff0
stlb r0, [r0]
stlb r1, [r1]
stlb r14, [r14]
stlh r0, [r0]
stlh r1, [r1]
stlh r14, [r14]
stl r0, [r0]
stl r1, [r1]
stl r14, [r14]
stlexb r0, r1, [r14]
stlexb r1, r14, [r0]
stlexb r14, r0, [r1]
stlexh r0, r1, [r14]
stlexh r1, r14, [r0]
stlexh r14, r0, [r1]
stlex r0, r1, [r14]
stlex r1, r14, [r0]
stlex r14, r0, [r1]
stlexd r0, r2, r3, [r14]
stlexd r1, r12, r13, [r0]
stlexd r14, r0, r1, [r1]
ldab r0, [r0]
ldab r1, [r1]
ldab r14, [r14]
ldah r0, [r0]
ldah r1, [r1]
ldah r14, [r14]
lda r0, [r0]
lda r1, [r1]
lda r14, [r14]
ldaexb r0, [r0]
ldaexb r1, [r1]
ldaexb r14, [r14]
ldaexh r0, [r0]
ldaexh r1, [r1]
ldaexh r14, [r14]
ldaex r0, [r0]
ldaex r1, [r1]
ldaex r14, [r14]
ldaexd r0, r1, [r0]
ldaexd r2, r3, [r1]
ldaexd r12, r13, [r14]
.thumb
.thumb_func
bar:
sevl
sevl.n
sevl.w
dcps1
dcps2
dcps3
hlt 0
hlt 63
stlb r0, [r0]
stlb r1, [r1]
stlb r14, [r14]
stlh r0, [r0]
stlh r1, [r1]
stlh r14, [r14]
stl r0, [r0]
stl r1, [r1]
stl r14, [r14]
stlexb r0, r1, [r14]
stlexb r1, r14, [r0]
stlexb r14, r0, [r1]
stlexh r0, r1, [r14]
stlexh r1, r14, [r0]
stlexh r14, r0, [r1]
stlex r0, r1, [r14]
stlex r1, r14, [r0]
stlex r14, r0, [r1]
stlexd r0, r1, r1, [r14]
stlexd r1, r14, r14, [r0]
stlexd r14, r0, r0, [r1]
ldab r0, [r0]
ldab r1, [r1]
ldab r14, [r14]
ldah r0, [r0]
ldah r1, [r1]
ldah r14, [r14]
lda r0, [r0]
lda r1, [r1]
lda r14, [r14]
ldaexb r0, [r0]
ldaexb r1, [r1]
ldaexb r14, [r14]
ldaexh r0, [r0]
ldaexh r1, [r1]
ldaexh r14, [r14]
ldaex r0, [r0]
ldaex r1, [r1]
ldaex r14, [r14]
ldaexd r0, r1, [r0]
ldaexd r1, r14, [r1]
ldaexd r14, r0, [r14]
|
tactcomplabs/xbgas-binutils-gdb
| 1,917
|
gas/testsuite/gas/arm/armv8-2-fp16-scalar.s
|
.macro f16_sss_arithmetic reg0, reg1, reg2
.irp op, vdiv.f16, vfma.f16, vfms.f16, vfnma.f16, vfnms.f16, vmaxnm.f16, vminnm.f16, vmla.f16, vmls.f16, vmul.f16, vnmla.f16, vnmls.f16, vnmul.f16, vsub.f16
\op s\reg0, s\reg1, s\reg2
.endr
.endm
.macro f16_ss_arithmetic reg0, reg1
.irp op, vabs.f16, vadd.f16, vsqrt.f16, vneg.f16
\op s\reg0, s\reg1
.endr
.endm
.macro f16_si_cmp reg0, imm
.irp op, vcmp.f16, vcmpe.f16
\op s\reg0, \imm
.endr
.endm
.macro f16_ss_cmp reg0, reg1
.irp op, vcmp.f16, vcmpe.f16
\op s\reg0, s\reg1
.endr
.endm
.macro f16_sss_vsel reg0, reg1, reg2
.irp op, vseleq.f16 vselge.f16, vselvs.f16
\op s\reg0, s\reg1, s\reg2
.endr
.endm
.macro f16_ss_cvt reg0, reg1
.irp op, vcvt.s32.f16, vcvt.u32.f16, vcvt.f16.s32, vcvt.f16.u32
\op s\reg0, s\reg1
.endr
.endm
.macro f16_ssi_cvt_imm32 reg0, reg1, imm
.irp op, vcvt.f16.s32, vcvt.f16.u32, vcvt.s32.f16, vcvt.u32.f16
\op s\reg0, s\reg1, \imm
.endr
.endm
.macro f16_ss_cvt_amnpr reg0, reg1
.irp op, vcvta.s32.f16, vcvta.u32.f16, vcvtm.s32.f16, vcvtm.u32.f16, vcvtn.s32.f16, vcvtn.u32.f16, vcvtp.s32.f16, vcvtp.u32.f16, vcvtr.u32.f16, vcvtr.s32.f16
\op s\reg0, s\reg1
.endr
.endm
.macro f16_ss_vrint reg0, reg1
.irp op, vrinta.f16, vrintm.f16, vrintn.f16, vrintp.f16, vrintr.f16, vrintx.f16, vrintz.f16
\op s\reg0, s\reg1
.endr
.endm
.macro f16_ss_mov reg0, reg1
.irp op, vins.f16, vmovx.f16
\op s\reg0, s\reg1
.endr
.endm
.text
vmov.f16 s0, r1
vmov.f16 r0, s1
vmov.f16 s0, #2.0
label:
.word 0xffe
vldr.16 s3, label
vldr.16 s6, [pc, #-4]
vldr.16 s3, [pc, #4]
vldr.16 s1, [r0, #4]
vldr.16 s2, [r0, #-4]
vstr.16 s6 , [r0, #4]
vstr.16 s11 , [r0, #-4]
f16_sss_arithmetic 5, 13, 24
f16_ss_arithmetic 5, 12
f16_si_cmp 2, #0.0
f16_ss_cmp 5, 13
f16_sss_vsel 5, 13, 23
f16_ss_cvt 3, 8
f16_ssi_cvt_imm32 7, 7, #29
f16_ss_cvt_amnpr 5, 10
f16_ss_vrint 3, 11
f16_ss_mov 5, 9
|
tactcomplabs/xbgas-binutils-gdb
| 2,081
|
gas/testsuite/gas/arm/float.s
|
.text
.align 0
l:
mvfe f0, f1
mvfeqe f3, f5
mvfeqd f4, #1.0
mvfs f4, f7
mvfsp f0, f1
mvfdm f3, f4
mvfez f7, f7
adfe f0, f1, #2.0
adfeqe f1, f2, #0.5
adfsm f3, f4, f5
sufd f0, f0, #2.0
sufs f1, f2, #10.0
sufneez f3, f4, f5
rsfs f1, f1, #0.0
rsfdp f3, f0, #5.0
rsfled f7, f6, f0
mufd f0, f0, f0
mufez f1, f2, #3.0
mufals f0, f0, #4.0
dvfd f0, f0, #1.0000
dvfez f0, f1, #10e0
dvfmism f3, f4, f5
rdfe f0, f1, #1.0e1
rdfs f3, f7, #0f1
rdfccdp f4, f4, f3
powd f0, f2, f3
pows f1, f3, #0e1e1
powcsez f4, f7, #1
rpws f7, f6, f7
rpweqd f0, f1, f2
rpwem f2, f2, f3
rmfd f1, f2, #3
rmfvss f3, f4, f4
rmfep f4, f7, f0
fmls f0, f1, f2
fmleqs f1, f3, f5
fmlplsz f4, f6, f0
fdvs f1, f3, #10
fdvsp f0, f1, f2
fdvhssm f4, f4, f4
frds f1, f1, #1.0
frdgts f2, f1, f0
frdgtsz f4, f4, f5
pold f0, f1, f2
polsz f4, f6, #3.0
poleqe f5, f6, f7
mnfs f0, f1
mnfd f0, #3.0
mnfez f0, #4.0
mnfeqez f0, f5
mnfsp f0, f4
mnfdm f1, f7
absd f0, f1
abssp f1, #3.0
abseqe f4, f5
rnds f1, f2
rndd f3, f4
rndeqez f6, #4.0
sqts f5, f5
sqtdp f6, f6
sqtplez f7, f6
logs f0, #10
loge f0, #0f10
lognedz f0, f1
lgne f1, f2
lgndz f1, f3
lgnvcs f3, f4
exps f1, f3
expem f3, #10.0
exppld f6, f7
sind f0, f1
sinsm f1, f2
singte f4, #5
cosd f1, f3
cosem f4, f5
cosnedp f6, f1
tane f1, f5
tansz f4, f7
tangedz f1, #4.0
asne f4, f5
asnsp f6, #5e-1
asnmidz f5, f5
acss f5, f6
acsd f6, f0
acshsem f1, #0.05e1
atne f0, f5
atnsz f1, #5
atnltd f3, f2
urde f5, f4
nrme f6, f5
nrmpldz f7, f5
fltsp f0, r8
flte f1, r0
flteqdz f5, r7
fix r0, f1
fixz r1, f7
fixcsm r5, f5
wfc r0
wfs r1
rfseq r2
rfc r4
cmf f0, #1
cmf f1, f2
cmfeq f0, f1
cnf f0, #3
cnf f1, #0.5
cnfvs f3, f4
cmfe f0, f1
cmfeeq f1, f2
cmfeqe f3, #5.0
cnfe f1, f3
cnfeeq f3, f4
cnfeqe f4, f7
cnfale f4, #5.0
lfm f0, 4, [r0]
lfm f0, 4, [r0, #0]
lfm f1, 4, [r1, #64]
sfm f2, 4, [r14, #1020]!
sfmeq f7, 3, [r8], #-1020
lfmfd f6, 2, [r15]
sfmea f7, 1, [r8]!
lfmeqea f5, 4, [r6]
sfmnefd f4, 3, [r2]
sfmnefd f4, 3, [r2]!
|
tactcomplabs/xbgas-binutils-gdb
| 1,334
|
gas/testsuite/gas/arm/mve-vmlsldav-bad.s
|
.macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlsldav.s16 r0, sp, q1, q2
vmlsldav.u16 r0, r1, q1, q2
cond vmlsldav
cond vmlsldava
cond vmlsldavx
cond vmlsldavax
vmlsldav.s64 r0, r1, q1, q2
vmlsldav.f32 r0, r1, q1, q2
vmlsldav.s8 r0, r1, q1, q2
vmlsldav.s16 r0, q1, q2
vmlsldava.s64 r0, r1, q1, q2
vmlsldava.f32 r0, r1, q1, q2
vmlsldava.s8 r0, r1, q1, q2
vmlsldava.s16 r0, q1, q2
vmlsldavx.s64 r0, r1, q1, q2
vmlsldavx.f32 r0, r1, q1, q2
vmlsldavx.s8 r0, r1, q1, q2
vmlsldavx.s16 r0, q1, q2
vmlsldavax.s64 r0, r1, q1, q2
vmlsldavax.f32 r0, r1, q1, q2
vmlsldavax.s8 r0, r1, q1, q2
vmlsldavax.s16 r0, q1, q2
it eq
vmlsldaveq.s16 r0, r1, q1, q2
vmlsldaveq.s16 r0, r1, q1, q2
vmlsldaveq.s16 r0, r1, q1, q2
vmlsldavt.s16 r0, r1, q1, q2
vpst
vmlsldav.s16 r0, r1, q1, q2
it eq
vmlsldavaeq.s16 r0, r1, q1, q2
vmlsldavaeq.s16 r0, r1, q1, q2
vmlsldavaeq.s16 r0, r1, q1, q2
vmlsldavat.s16 r0, r1, q1, q2
vpst
vmlsldava.s16 r0, r1, q1, q2
it eq
vmlsldavxeq.s16 r0, r1, q1, q2
vmlsldavxeq.s16 r0, r1, q1, q2
vmlsldavxeq.s16 r0, r1, q1, q2
vmlsldavxt.s16 r0, r1, q1, q2
vpst
vmlsldavx.s16 r0, r1, q1, q2
it eq
vmlsldavaxeq.s16 r0, r1, q1, q2
vmlsldavaxeq.s16 r0, r1, q1, q2
vmlsldavaxeq.s16 r0, r1, q1, q2
vmlsldavaxt.s16 r0, r1, q1, q2
vpst
vmlsldavax.s16 r0, r1, q1, q2
|
tactcomplabs/xbgas-binutils-gdb
| 2,675
|
gas/testsuite/gas/arm/fpa-monadic.s
|
.text
.globl F
F:
mvfs f0, f0
mvfsp f0, f0
mvfsm f0, f0
mvfsz f0, f0
mvfd f0, f0
mvfdp f0, f0
mvfdm f0, f0
mvfdz f0, f0
mvfe f0, f0
mvfep f0, f0
mvfem f0, f0
mvfez f0, f0
mnfs f0, f0
mnfsp f0, f0
mnfsm f0, f0
mnfsz f0, f0
mnfd f0, f0
mnfdp f0, f0
mnfdm f0, f0
mnfdz f0, f0
mnfe f0, f0
mnfep f0, f0
mnfem f0, f0
mnfez f0, f0
abss f0, f0
abssp f0, f0
abssm f0, f0
abssz f0, f0
absd f0, f0
absdp f0, f0
absdm f0, f0
absdz f0, f0
abse f0, f0
absep f0, f0
absem f0, f0
absez f0, f0
rnds f0, f0
rndsp f0, f0
rndsm f0, f0
rndsz f0, f0
rndd f0, f0
rnddp f0, f0
rnddm f0, f0
rnddz f0, f0
rnde f0, f0
rndep f0, f0
rndem f0, f0
rndez f0, f0
sqts f0, f0
sqtsp f0, f0
sqtsm f0, f0
sqtsz f0, f0
sqtd f0, f0
sqtdp f0, f0
sqtdm f0, f0
sqtdz f0, f0
sqte f0, f0
sqtep f0, f0
sqtem f0, f0
sqtez f0, f0
logs f0, f0
logsp f0, f0
logsm f0, f0
logsz f0, f0
logd f0, f0
logdp f0, f0
logdm f0, f0
logdz f0, f0
loge f0, f0
logep f0, f0
logem f0, f0
logez f0, f0
lgns f0, f0
lgnsp f0, f0
lgnsm f0, f0
lgnsz f0, f0
lgnd f0, f0
lgndp f0, f0
lgndm f0, f0
lgndz f0, f0
lgne f0, f0
lgnep f0, f0
lgnem f0, f0
lgnez f0, f0
exps f0, f0
expsp f0, f0
expsm f0, f0
expsz f0, f0
expd f0, f0
expdp f0, f0
expdm f0, f0
expdz f0, f0
expe f0, f0
expep f0, f0
expem f0, f0
expdz f0, f0
sins f0, f0
sinsp f0, f0
sinsm f0, f0
sinsz f0, f0
sind f0, f0
sindp f0, f0
sindm f0, f0
sindz f0, f0
sine f0, f0
sinep f0, f0
sinem f0, f0
sinez f0, f0
coss f0, f0
cossp f0, f0
cossm f0, f0
cossz f0, f0
cosd f0, f0
cosdp f0, f0
cosdm f0, f0
cosdz f0, f0
cose f0, f0
cosep f0, f0
cosem f0, f0
cosez f0, f0
tans f0, f0
tansp f0, f0
tansm f0, f0
tansz f0, f0
tand f0, f0
tandp f0, f0
tandm f0, f0
tandz f0, f0
tane f0, f0
tanep f0, f0
tanem f0, f0
tanez f0, f0
asns f0, f0
asnsp f0, f0
asnsm f0, f0
asnsz f0, f0
asnd f0, f0
asndp f0, f0
asndm f0, f0
asndz f0, f0
asne f0, f0
asnep f0, f0
asnem f0, f0
asnez f0, f0
acss f0, f0
acssp f0, f0
acssm f0, f0
acssz f0, f0
acsd f0, f0
acsdp f0, f0
acsdm f0, f0
acsdz f0, f0
acse f0, f0
acsep f0, f0
acsem f0, f0
acsez f0, f0
atns f0, f0
atnsp f0, f0
atnsm f0, f0
atnsz f0, f0
atnd f0, f0
atndp f0, f0
atndm f0, f0
atndz f0, f0
atne f0, f0
atnep f0, f0
atnem f0, f0
atnez f0, f0
urds f0, f0
urdsp f0, f0
urdsm f0, f0
urdsz f0, f0
urdd f0, f0
urddp f0, f0
urddm f0, f0
urddz f0, f0
urde f0, f0
urdep f0, f0
urdem f0, f0
urdez f0, f0
nrms f0, f0
nrmsp f0, f0
nrmsm f0, f0
nrmsz f0, f0
nrmd f0, f0
nrmdp f0, f0
nrmdm f0, f0
nrmdz f0, f0
nrme f0, f0
nrmep f0, f0
nrmem f0, f0
nrmez f0, f0
|
tactcomplabs/xbgas-binutils-gdb
| 2,975
|
gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
|
@ VFP with Neon-style syntax
.syntax unified
.arch armv7-a
.include "itblock.s"
func:
.macro testvmov cond="" f32=".f32" f64=".f64"
itblock 4 \cond
vmov\cond\f32 s0,s1
vmov\cond\f64 d0,d1
vmov\cond\f32 s0,#0.25
vmov\cond\f64 d0,#1.0
itblock 4 \cond
vmov\cond r0,s1
vmov\cond s0,r1
vmov\cond r0,r1,s2,s3
vmov\cond s0,s1,r2,r4
.endm
@ Test VFP vmov variants. These can all be conditional.
testvmov
testvmov eq
.macro monadic op cond="" f32=".f32" f64=".f64"
itblock 2 \cond
\op\cond\f32 s0,s1
\op\cond\f64 d0,d1
.endm
.macro monadic_c op
monadic \op
monadic \op eq
.endm
.macro dyadic op cond="" f32=".f32" f64=".f64"
itblock 2 \cond
\op\cond\f32 s0,s1,s2
\op\cond\f64 d0,d1,d2
.endm
.macro dyadic_c op
dyadic \op
dyadic \op eq
.endm
.macro dyadicz op cond="" f32=".f32" f64=".f64"
itblock 2 \cond
\op\cond\f32 s0,#0
\op\cond\f64 d0,#0
.endm
.macro dyadicz_c op
dyadicz \op
dyadicz \op eq
.endm
monadic_c vsqrt
monadic_c vabs
monadic_c vneg
monadic_c vcmp
monadic_c vcmpe
dyadic_c vnmul
dyadic_c vnmla
dyadic_c vnmls
dyadic_c vmul
dyadic_c vmla
dyadic_c vmls
dyadic_c vadd
dyadic_c vsub
dyadic_c vdiv
dyadicz_c vcmp
dyadicz_c vcmpe
.macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
itblock 4 \cond
vcvtz\cond\s32\f32 s0,s1
vcvtz\cond\u32\f32 s0,s1
vcvtz\cond\s32\f64 s0,d1
vcvtz\cond\u32\f64 s0,d1
.endm
cvtz
cvtz eq
.macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
itblock 4 \cond
vcvt\cond\s32\f32 s0,s1
vcvt\cond\u32\f32 s0,s1
vcvt\cond\f32\s32 s0,s1
vcvt\cond\f32\u32 s0,s1
itblock 4 \cond
vcvt\cond\f32\f64 s0,d1
vcvt\cond\f64\f32 d0,s1
vcvt\cond\s32\f64 s0,d1
vcvt\cond\u32\f64 s0,d1
itblock 2 \cond
vcvt\cond\f64\s32 d0,s1
vcvt\cond\f64\u32 d0,s1
.endm
cvt
cvt eq
.macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
itblock 4 \cond
vcvt\cond\s32\f32 s0,s0,#1
vcvt\cond\u32\f32 s0,s0,#1
vcvt\cond\f32\s32 s0,s0,#1
vcvt\cond\f32\u32 s0,s0,#1
itblock 4 \cond
vcvt\cond\s32\f64 d0,d0,#1
vcvt\cond\u32\f64 d0,d0,#1
vcvt\cond\f64\s32 d0,d0,#1
vcvt\cond\f64\u32 d0,d0,#1
itblock 4 \cond
vcvt\cond\f32\s16 s0,s0,#1
vcvt\cond\f32\u16 s0,s0,#1
vcvt\cond\f64\s16 d0,d0,#1
vcvt\cond\f64\u16 d0,d0,#1
itblock 4 \cond
vcvt\cond\s16\f32 s0,s0,#1
vcvt\cond\u16\f32 s0,s0,#1
vcvt\cond\s16\f64 d0,d0,#1
vcvt\cond\u16\f64 d0,d0,#1
.endm
cvti
cvti eq
.macro multi op cond="" n="" ia="ia" db="db"
itblock 4 \cond
\op\n\cond r0,{s3-s6}
\op\ia\cond r0,{s3-s6}
\op\ia\cond r0!,{s3-s6}
\op\db\cond r0!,{s3-s6}
itblock 4 \cond
\op\n\cond r0,{d3-d6}
\op\ia\cond r0,{d3-d6}
\op\ia\cond r0!,{d3-d6}
\op\db\cond r0!,{d3-d6}
.endm
multi vldm
multi vldm eq
multi vstm
multi vstm eq
.macro single op cond=""
itblock 2 \cond
\op\cond s0,[r0,#4]
\op\cond d0,[r0,#4]
.endm
single vldr
single vldr eq
single vstr
single vstr eq
|
tactcomplabs/xbgas-binutils-gdb
| 2,460
|
gas/testsuite/gas/arm/armv8-a+crypto.s
|
.syntax unified
.arch armv8-a
.arch_extension crypto
.arm
vmull.p64 q0, d0, d0
vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
aese.8 q15, q15
aesd.8 q0, q0
aesd.8 q7, q7
aesd.8 q8, q8
aesd.8 q15, q15
aesmc.8 q0, q0
aesmc.8 q7, q7
aesmc.8 q8, q8
aesmc.8 q15, q15
aesimc.8 q0, q0
aesimc.8 q7, q7
aesimc.8 q8, q8
aesimc.8 q15, q15
sha1c.32 q0, q0, q0
sha1c.32 q7, q7, q7
sha1c.32 q8, q8, q8
sha1c.32 q15, q15, q15
sha1p.32 q0, q0, q0
sha1p.32 q7, q7, q7
sha1p.32 q8, q8, q8
sha1p.32 q15, q15, q15
sha1m.32 q0, q0, q0
sha1m.32 q7, q7, q7
sha1m.32 q8, q8, q8
sha1m.32 q15, q15, q15
sha1su0.32 q0, q0, q0
sha1su0.32 q7, q7, q7
sha1su0.32 q8, q8, q8
sha1su0.32 q15, q15, q15
sha256h.32 q0, q0, q0
sha256h.32 q7, q7, q7
sha256h.32 q8, q8, q8
sha256h.32 q15, q15, q15
sha256h2.32 q0, q0, q0
sha256h2.32 q7, q7, q7
sha256h2.32 q8, q8, q8
sha256h2.32 q15, q15, q15
sha256su1.32 q0, q0, q0
sha256su1.32 q7, q7, q7
sha256su1.32 q8, q8, q8
sha256su1.32 q15, q15, q15
sha1h.32 q0, q0
sha1h.32 q7, q7
sha1h.32 q8, q8
sha1h.32 q15, q15
sha1su1.32 q0, q0
sha1su1.32 q7, q7
sha1su1.32 q8, q8
sha1su1.32 q15, q15
sha256su0.32 q0, q0
sha256su0.32 q7, q7
sha256su0.32 q8, q8
sha256su0.32 q15, q15
.thumb
vmull.p64 q0, d0, d0
vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
aese.8 q15, q15
aesd.8 q0, q0
aesd.8 q7, q7
aesd.8 q8, q8
aesd.8 q15, q15
aesmc.8 q0, q0
aesmc.8 q7, q7
aesmc.8 q8, q8
aesmc.8 q15, q15
aesimc.8 q0, q0
aesimc.8 q7, q7
aesimc.8 q8, q8
aesimc.8 q15, q15
sha1c.32 q0, q0, q0
sha1c.32 q7, q7, q7
sha1c.32 q8, q8, q8
sha1c.32 q15, q15, q15
sha1p.32 q0, q0, q0
sha1p.32 q7, q7, q7
sha1p.32 q8, q8, q8
sha1p.32 q15, q15, q15
sha1m.32 q0, q0, q0
sha1m.32 q7, q7, q7
sha1m.32 q8, q8, q8
sha1m.32 q15, q15, q15
sha1su0.32 q0, q0, q0
sha1su0.32 q7, q7, q7
sha1su0.32 q8, q8, q8
sha1su0.32 q15, q15, q15
sha256h.32 q0, q0, q0
sha256h.32 q7, q7, q7
sha256h.32 q8, q8, q8
sha256h.32 q15, q15, q15
sha256h2.32 q0, q0, q0
sha256h2.32 q7, q7, q7
sha256h2.32 q8, q8, q8
sha256h2.32 q15, q15, q15
sha256su1.32 q0, q0, q0
sha256su1.32 q7, q7, q7
sha256su1.32 q8, q8, q8
sha256su1.32 q15, q15, q15
sha1h.32 q0, q0
sha1h.32 q7, q7
sha1h.32 q8, q8
sha1h.32 q15, q15
sha1su1.32 q0, q0
sha1su1.32 q7, q7
sha1su1.32 q8, q8
sha1su1.32 q15, q15
sha256su0.32 q0, q0
sha256su0.32 q7, q7
sha256su0.32 q8, q8
sha256su0.32 q15, q15
|
tactcomplabs/xbgas-binutils-gdb
| 3,072
|
gas/testsuite/gas/arm/mve-vmov-2.s
|
.syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vmov \op0, \op1, s2, s3
vmov \op0, \op1, s4, s5
vmov \op0, \op1, s8, s9
vmov \op0, \op1, s16, s17
vmov \op0, \op1, s30, s31
vmov s0, s1, \op0, \op1
vmov s1, s2, \op0, \op1
vmov s2, s3, \op0, \op1
vmov s4, s5, \op0, \op1
vmov s8, s9, \op0, \op1
vmov s16, s17, \op0, \op1
vmov s30, s31, \op0, \op1
.endm
.irp op0, r1, r2, r4, r7, r8, r10, r12, r14
vmov_rr r0, \op0
.endr
.irp op0, r0, r2, r4, r7, r8, r10, r12, r14
vmov_rr r1, \op0
.endr
.irp op0, r0, r1, r4, r7, r8, r10, r12, r14
vmov_rr r2, \op0
.endr
.irp op0, r0, r1, r2, r7, r8, r10, r12, r14
vmov_rr r4, \op0
.endr
.irp op0, r0, r1, r2, r4, r8, r10, r12, r14
vmov_rr r7, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r10, r12, r14
vmov_rr r8, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r12, r14
vmov_rr r10, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r10, r14
vmov_rr r12, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r10, r12
vmov_rr r14, \op0
.endr
.macro vmov_qidx_r size, idx
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov\size \op1[\idx], \op2
.endr
.endr
.endm
.irp idx, 0, 1, 2, 4, 8, 15, 13, 6
vmov_qidx_r .8, \idx
.endr
.irp idx, 0, 1, 2, 4, 7
vmov_qidx_r .16, \idx
.endr
.irp idx, 0, 1, 2, 3
vmov_qidx_r .32, \idx
.endr
.macro vmov_r_qidx size, idx
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
.irp op2, q0, q1, q2, q4, q7
vmov\size \op1, \op2[\idx]
.endr
.endr
.endm
.irp data, .u8, .s8
.irp idx, 0, 1, 2, 4, 8, 15, 13, 6
vmov_r_qidx \data, \idx
.endr
.endr
.irp data, .u16, .s16
.irp idx, 0, 1, 2, 4, 7
vmov_r_qidx \data, \idx
.endr
.endr
.irp idx, 0, 1, 2, 3
vmov_r_qidx .32, \idx
.endr
vmov.i32 q0, #0
vmov.i32 q0, #255 @ 0x000000FF 000000FF
vmov.i32 q0, #65280 @ 0x0000FF00 0000FF00
vmov.i32 q0, #4278190080 @ 0xFF000000 FF000000
vmov.i32 q0, #16711680 @ 0x00FF0000 00FF0000
vmov.i16 q0, #0
vmov.i16 q0, #255 @ 0x00FF 00FF 00FF 00FF
vmov.i16 q0, #65280 @ 0xFF00 FF00 FF00 FF00
vmov.i8 q0, #0
vmov.i8 q0, #255 @ 0xFF FF FF FF FF FF FF FF
vmov.i64 q0, #18374686479671623680 @ 0xFF00000000000000
vmov.i64 q0, #71776119061217280 @ 0x00FF000000000000
vmov.i64 q0, #280375465082880 @ 0x0000FF0000000000
vmov.i64 q0, #1095216660480 @ 0x000000FF00000000
vmov.i64 q0, #4278190080 @ 0x00000000FF000000
vmov.i64 q0, #16711680 @ 0x00000000000FF0000
vmov.i64 q0, #65280 @ 0x0000000000000FF00
vmov.i64 q0, #255 @ 0x000000000000000FF
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov.f16 \op0, \op1
vmov.f16 \op1, \op0
.endr
.endr
vmov.f32 q0, #0.0
vmov.f32 q0, #-31.0 @ 0xC1F80000 C1F80000
vmov.f32 q0, #-31.0 @ 0xC1F80000 C1F80000
vmov.f32 q0, #-1.9375 @ 0xBFF80000 BFF80000
vmov.f32 q0, #1.0 @ 0x3F800000 3F800000
vmov.f16 s0, #2.0
vmov.f32 s0, #2.5
|
tactcomplabs/xbgas-binutils-gdb
| 5,726
|
gas/testsuite/gas/arm/vfp1xD_t2.s
|
@ VFP Instructions for v1xD variants (Single precision only)
@ Same as vfp1xD.s, but for Thumb-2
.syntax unified
.thumb
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fmstat
fcmpes s0, s0
fcmpezs s0
fcmps s0, s0
fcmpzs s0
@ Monadic data operations
fabss s0, s0
fcpys s0, s0
fnegs s0, s0
fsqrts s0, s0
@ Dyadic data operations
fadds s0, s0, s0
fdivs s0, s0, s0
fmacs s0, s0, s0
fmscs s0, s0, s0
fmuls s0, s0, s0
fnmacs s0, s0, s0
fnmscs s0, s0, s0
fnmuls s0, s0, s0
fsubs s0, s0, s0
@ Load/store operations
flds s0, [r0]
fsts s0, [r0]
@ Load/store multiple operations
fldmias r0, {s0}
fldmfds r0, {s0}
fldmias r0!, {s0}
fldmfds r0!, {s0}
fldmdbs r0!, {s0}
fldmeas r0!, {s0}
fldmiax r0, {d0}
fldmfdx r0, {d0}
fldmiax r0!, {d0}
fldmfdx r0!, {d0}
fldmdbx r0!, {d0}
fldmeax r0!, {d0}
fstmias r0, {s0}
fstmeas r0, {s0}
fstmias r0!, {s0}
fstmeas r0!, {s0}
fstmdbs r0!, {s0}
fstmfds r0!, {s0}
fstmiax r0, {d0}
fstmeax r0, {d0}
fstmiax r0!, {d0}
fstmeax r0!, {d0}
fstmdbx r0!, {d0}
fstmfdx r0!, {d0}
@ Conversion operations
fsitos s0, s0
fuitos s0, s0
ftosis s0, s0
ftosizs s0, s0
ftouis s0, s0
ftouizs s0, s0
@ ARM from VFP operations
fmrs r0, s0
fmrx r0, fpsid
fmrx r0, fpscr
fmrx r0, fpexc
@ VFP From ARM operations
fmsr s0, r0
fmxr fpsid, r0
fmxr fpscr, r0
fmxr fpexc, r0
@ Now we test that the register fields are updated correctly for
@ each class of instruction.
@ Single register operations (compare-zero):
fcmpzs s1
fcmpzs s2
fcmpzs s31
@ Two register comparison operations:
fcmps s0, s1
fcmps s0, s2
fcmps s0, s31
fcmps s1, s0
fcmps s2, s0
fcmps s31, s0
fcmps s21, s12
@ Two register data operations (monadic)
fnegs s0, s1
fnegs s0, s2
fnegs s0, s31
fnegs s1, s0
fnegs s2, s0
fnegs s31, s0
fnegs s12, s21
@ Three register data operations (dyadic)
fadds s0, s0, s1
fadds s0, s0, s2
fadds s0, s0, s31
fadds s0, s1, s0
fadds s0, s2, s0
fadds s0, s31, s0
fadds s1, s0, s0
fadds s2, s0, s0
fadds s31, s0, s0
fadds s12, s21, s5
@ Conversion operations
fsitos s0, s1
fsitos s0, s2
fsitos s0, s31
fsitos s1, s0
fsitos s2, s0
fsitos s31, s0
ftosis s0, s1
ftosis s0, s2
ftosis s0, s31
ftosis s1, s0
ftosis s2, s0
ftosis s31, s0
@ Move to VFP from ARM
fmsr s0, r1
fmsr s0, r7
fmsr s0, r14
fmsr s1, r0
fmsr s2, r0
fmsr s31, r0
fmsr s21, r7
fmxr fpsid, r1
fmxr fpsid, r14
@ Move to ARM from VFP
fmrs r0, s1
fmrs r0, s2
fmrs r0, s31
fmrs r1, s0
fmrs r7, s0
fmrs r14, s0
fmrs r9, s11
fmrx r1, fpsid
fmrx r14, fpsid
@ Load/store operations
flds s0, [r1]
flds s0, [r14]
flds s0, [r0, #0]
flds s0, [r0, #1020]
flds s0, [r0, #-1020]
flds s1, [r0]
flds s2, [r0]
flds s31, [r0]
fsts s21, [r12, #804]
@ Load/store multiple operations
fldmias r0, {s1}
fldmias r0, {s2}
fldmias r0, {s31}
fldmias r0, {s0-s1}
fldmias r0, {s0-s2}
fldmias r0, {s0-s31}
fldmias r0, {s1-s31}
fldmias r0, {s2-s31}
fldmias r0, {s30-s31}
fldmias r1, {s0}
fldmias r14, {s0}
fstmiax r0, {d1}
fstmiax r0, {d2}
fstmiax r0, {d15}
fstmiax r0, {d0-d1}
fstmiax r0, {d0-d2}
fstmiax r0, {d0-d15}
fstmiax r0, {d1-d15}
fstmiax r0, {d2-d15}
fstmiax r0, {d14-d15}
fstmiax r1, {d0}
fstmiax r14, {d0}
@ Check that we assemble all the register names correctly
fcmpzs s0
fcmpzs s1
fcmpzs s2
fcmpzs s3
fcmpzs s4
fcmpzs s5
fcmpzs s6
fcmpzs s7
fcmpzs s8
fcmpzs s9
fcmpzs s10
fcmpzs s11
fcmpzs s12
fcmpzs s13
fcmpzs s14
fcmpzs s15
fcmpzs s16
fcmpzs s17
fcmpzs s18
fcmpzs s19
fcmpzs s20
fcmpzs s21
fcmpzs s22
fcmpzs s23
fcmpzs s24
fcmpzs s25
fcmpzs s26
fcmpzs s27
fcmpzs s28
fcmpzs s29
fcmpzs s30
fcmpzs s31
@ Now we check the placement of the conditional execution substring.
@ On VFP this is always at the end of the instruction.
@ We use different register numbers here to check for correct
@ disassembly
@ Comparison operations
itttt eq
fmstateq
fcmpeseq s3, s7
fcmpezseq s5
fcmpseq s1, s2
itttt eq
fcmpzseq s1
@ Monadic data operations
fabsseq s1, s3
fcpyseq s31, s19
fnegseq s20, s8
itttt eq
fsqrtseq s5, s7
@ Dyadic data operations
faddseq s6, s5, s4
fdivseq s3, s2, s1
fmacseq s31, s30, s29
itttt eq
fmscseq s28, s27, s26
fmulseq s25, s24, s23
fnmacseq s22, s21, s20
fnmscseq s19, s18, s17
itttt eq
fnmulseq s16, s15, s14
fsubseq s13, s12, s11
@ Load/store operations
fldseq s10, [r8]
fstseq s9, [r7]
@ Load/store multiple operations
itttt eq
fldmiaseq r1, {s8}
fldmfdseq r2, {s7}
fldmiaseq r3!, {s6}
fldmfdseq r4!, {s5}
itttt eq
fldmdbseq r5!, {s4}
fldmeaseq r6!, {s3}
fldmiaxeq r7, {d1}
fldmfdxeq r8, {d2}
itttt eq
fldmiaxeq r9!, {d3}
fldmfdxeq r10!, {d4}
fldmdbxeq r11!, {d5}
fldmeaxeq r12!, {d6}
itttt eq
fstmiaseq r13, {s2}
fstmeaseq r14, {s1}
fstmiaseq r1!, {s31}
fstmeaseq r2!, {s30}
itttt eq
fstmdbseq r3!, {s29}
fstmfdseq r4!, {s28}
fstmiaxeq r5, {d7}
fstmeaxeq r6, {d8}
itttt eq
fstmiaxeq r7!, {d9}
fstmeaxeq r8!, {d10}
fstmdbxeq r9!, {d11}
fstmfdxeq r10!, {d12}
@ Conversion operations
itttt eq
fsitoseq s27, s6
ftosiseq s25, s5
ftosizseq s23, s4
ftouiseq s21, s3
itttt eq
ftouizseq s19, s2
fuitoseq s17, s1
@ ARM from VFP operations
fmrseq r11, s3
fmrxeq r9, fpsid
@ VFP From ARM operations
itt eq
fmsreq s3, r9
fmxreq fpsid, r8
@ Implementation specific system registers
fmrx r0, fpinst
fmrx r0, fpinst2
fmrx r0, mvfr0
fmrx r0, mvfr1
fmrx r0, c12
fmxr fpinst, r0
fmxr fpinst2, r0
fmxr mvfr0, r0
fmxr mvfr1, r0
fmxr c12, r0
nop
nop
nop
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,240
|
gas/testsuite/gas/arm/archv6t2-bad.s
|
@ We do not bother testing simple cases, e.g. immediates where
@ registers belong, trailing junk at end of line.
.text
x:
@ pc not allowed
bfc pc,#0,#1
bfi pc,r0,#0,#1
movw pc,#0
movt pc,#0
@ bitfield range limits
bfc r0,#0,#0
bfc r0,#32,#0
bfc r0,#0,#33
bfc r0,#33,#1
bfc r0,#32,#1
bfc r0,#28,#10
bfi r0,r1,#0,#0
bfi r0,r1,#32,#0
bfi r0,r1,#0,#33
bfi r0,r1,#33,#1
bfi r0,r1,#32,#1
bfi r0,r1,#28,#10
sbfx r0,r1,#0,#0
sbfx r0,r1,#32,#0
sbfx r0,r1,#0,#33
sbfx r0,r1,#33,#1
sbfx r0,r1,#32,#1
sbfx r0,r1,#28,#10
ubfx r0,r1,#0,#0
ubfx r0,r1,#32,#0
ubfx r0,r1,#0,#33
ubfx r0,r1,#33,#1
ubfx r0,r1,#32,#1
ubfx r0,r1,#28,#10
@ bfi accepts only #0 in Rm position
bfi r0,#1,#2,#3
@ mov16 range limits
movt r0,#65537
movw r0,#65537
movt r0,#-1
movw r0,#-1
@ ldsttv4 Rd == Rn (warning)
ldrht r0,[r0]
ldrsbt r0,[r0]
ldrsht r0,[r0]
strht r0,[r0]
@ Bug reported by user. GAS used to issue an error message
@ "r15 not allowed here" for these two instructions because
@ it thought that the "r2" operand was a PC-relative branch
@ to a label called "r2".
ldrex r0, r2
strex r1, r0, r2
@ movs shouldn't be extened to accept UINT16 can't fit into ARM modified
@ immediate format.
movs r0, #0x0999
|
tactcomplabs/xbgas-binutils-gdb
| 5,939
|
gas/testsuite/gas/arm/cde-scalar.s
|
.syntax unified
# Extra tests everywhere:
# Ensure that setting the register to something in r[1-12] works.
# cx1{a} Has arguments in the following form
# 111a111000iiiiiidddd0pppi0iiiiii
#
# Variants to test:
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# concatenated)
# - Each register 9 (0b1001), APSR_nzcv, or all zeros
# - Coprocessor num set to 7
# - Everything again with the `a` version (to double check parsing).
# - Accumulator versions without optional argument (to check parsing)
#
# IT blocks:
# Non-accumulator versions are UNPREDICTABLE in IT blocks.
# Accumulator versions are allowed in IT blocks.
# cx1{a} extra tests.
# Arm conditional
cx1 p0, r0, #0
cx1 p0, r0, #8064
cx1 p0, r0, #64
cx1 p0, r0, #63
cx1 p7, r0, #0
cx1 p0, APSR_nzcv, #0
cx1 p0, r9, #0
cx1a p0, r0, #0
cx1a p0, r0, #8064
cx1a p0, r0, #64
cx1a p0, r0, #63
cx1a p7, r0, #0
cx1a p0, APSR_nzcv, #0
cx1a p0, r9, #0
it ne
cx1ane p0, r0, #0
# cx1d{a} encoding of following form:
# 111a111000iiiiiidddd0pppi1iiiiii
#
# Variants to test:
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# concatenated)
# - Destination register 10 (0b1010) or all zeros
# - Coprocessor num set to 7
# - Everything again with the `a` version (to double check parsing).
# - Accumulator versions without optional argument (to check parsing)
cx1d p0, r0, r1, #0
cx1d p0, r0, r1, #8064
cx1d p0, r0, r1, #64
cx1d p0, r0, r1, #63
cx1d p7, r0, r1, #0
cx1d p0, r10, r11, #0
cx1da p0, r0, r1, #0
cx1da p0, r0, r1, #8064
cx1da p0, r0, r1, #64
cx1da p0, r0, r1, #63
cx1da p7, r0, r1, #0
cx1da p0, r10, r11, #0
it ne
cx1dane p0, r0, r1, #0
# cx2{a} Has arguments of the following form:
# 111a111001iinnnndddd0pppi0iiiiii
#
# Variants to test:
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# concatenated)
# - Each register 9 (0b1001), APSR_nzcv, or all zeros
# - Coprocessor num set to 7
# - Everything again with the `a` version (to double check parsing).
# - Accumulator versions without optional argument (to check parsing)
cx2 p0, r0, r0, #0
cx2 p0, r0, r0, #384
cx2 p0, r0, r0, #64
cx2 p0, r0, r0, #63
cx2 p7, r0, r0, #0
cx2 p0, APSR_nzcv, r0, #0
cx2 p0, r9, r0, #0
cx2 p0, r0, APSR_nzcv, #0
cx2 p0, r0, r9, #0
cx2a p0, r0, r0, #0
cx2a p0, r0, r0, #384
cx2a p0, r0, r0, #64
cx2a p0, r0, r0, #63
cx2a p7, r0, r0, #0
cx2a p0, APSR_nzcv, r0, #0
cx2a p0, r9, r0, #0
cx2a p0, r0, APSR_nzcv, #0
cx2a p0, r0, r9, #0
it ne
cx2ane p0, r0, r0, #0
# cx2d{a} encoding has following form:
# 111a111001iinnnndddd0pppi1iiiiii
#
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# concatenated)
# - Destination register 10 (0b1010) or all zeros
# - Coprocessor num set to 7
# - Everything again with the `a` version (to double check parsing).
# - Accumulator versions without optional argument (to check parsing)
cx2d p0, r0, r1, r0, #0
cx2d p0, r0, r1, r0, #384
cx2d p0, r0, r1, r0, #64
cx2d p0, r0, r1, r0, #63
cx2d p7, r0, r1, r0, #0
cx2d p0, r10, r11, r0, #0
cx2d p0, r0, r1, APSR_nzcv, #0
cx2d p0, r0, r1, r9, #0
cx2da p0, r0, r1, r0, #0
cx2da p0, r0, r1, r0, #384
cx2da p0, r0, r1, r0, #64
cx2da p0, r0, r1, r0, #63
cx2da p7, r0, r1, r0, #0
cx2da p0, r10, r11, r0, #0
cx2da p0, r0, r1, APSR_nzcv, #0
cx2da p0, r0, r1, r9, #0
# cx3{a} Has arguments in the following form:
# 111a11101iiinnnnmmmm0pppi0iidddd
#
# Variants to test:
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# concatenated)
# - Each register 9 (0b1001), APSR_nzcv, or all zeros
# - Coprocessor num set to 7
# - Everything again with the `a` version (to double check parsing).
# - Accumulator versions without optional argument (to check parsing)
cx3 p0, r0, r0, r0, #0
cx3 p0, r0, r0, r0, #56
cx3 p0, r0, r0, r0, #4
cx3 p0, r0, r0, r0, #3
cx3 p7, r0, r0, r0, #0
cx3 p0, APSR_nzcv, r0, r0, #0
cx3 p0, r9, r0, r0, #0
cx3 p0, r0, APSR_nzcv, r0, #0
cx3 p0, r0, r9, r0, #0
cx3 p0, r0, r0, APSR_nzcv, #0
cx3 p0, r0, r0, r9, #0
cx3a p0, r0, r0, r0, #0
cx3a p0, r0, r0, r0, #56
cx3a p0, r0, r0, r0, #4
cx3a p0, r0, r0, r0, #3
cx3a p7, r0, r0, r0, #0
cx3a p0, APSR_nzcv, r0, r0, #0
cx3a p0, r9, r0, r0, #0
cx3a p0, r0, APSR_nzcv, r0, #0
cx3a p0, r0, r9, r0, #0
cx3a p0, r0, r0, APSR_nzcv, #0
cx3a p0, r0, r0, r9, #0
it ne
cx3ane p0, r0, r0, r0, #0
# cx3d{a} encoding has following form:
# 111a11101iiinnnnmmmm0pppi1iidddd
#
# Variants to test:
# - Toggle 'a'
# - immediates that set each set of `i` to ones in turn.
# (imm = op1:op2:op3 , which is each group of `i` from left to write
# concatenated)
# - Destination register 10 (0b1010) or all zeros
# - Source register 9 (0b1001), APSR_nzcv, or all zeros
# No longer allows APSR_nzcv in destination register
cx3d p0, r0, r1, r0, r0, #0
cx3d p0, r0, r1, r0, r0, #56
cx3d p0, r0, r1, r0, r0, #4
cx3d p0, r0, r1, r0, r0, #3
cx3d p7, r0, r1, r0, r0, #0
cx3d p0, r10, r11, r0, r0, #0
cx3d p0, r0, r1, APSR_nzcv, r0, #0
cx3d p0, r0, r1, r9, r0, #0
cx3d p0, r0, r1, r0, APSR_nzcv, #0
cx3d p0, r0, r1, r0, r9, #0
cx3da p0, r0, r1, r0, r0, #0
cx3da p0, r0, r1, r0, r0, #56
cx3da p0, r0, r1, r0, r0, #4
cx3da p0, r0, r1, r0, r0, #3
cx3da p7, r0, r1, r0, r0, #0
cx3da p0, r10, r11, r0, r0, #0
cx3da p0, r0, r1, APSR_nzcv, r0, #0
cx3da p0, r0, r1, r9, r0, #0
cx3da p0, r0, r1, r0, APSR_nzcv, #0
cx3da p0, r0, r1, r0, r9, #0
|
tactcomplabs/xbgas-binutils-gdb
| 1,830
|
gas/testsuite/gas/arm/thumb2_vpool.s
|
.text
.fpu neon
.thumb
.syntax unified
.thumb_func
thumb2_ldr:
.macro vlxr regtype const
.irp regindex, 0, 14, 28, 31
vldr \regtype\regindex, \const
.endr
.endm
# Thumb-2 support vldr literal pool also.
vlxr s "=0"
vlxr s "=0xff000000"
vlxr s "=-1"
vlxr s "=0x0fff0000"
.pool
vlxr s "=0"
vlxr s "=0x00ff0000"
vlxr s "=0xff00ffff"
vlxr s "=0x00fff000"
.pool
vlxr d "=0"
vlxr d "=0xca000000"
vlxr d "=-1"
vlxr d "=0x0fff0000"
.pool
vlxr d "=0"
vlxr d "=0x00ff0000"
vlxr d "=0xff0000ff"
vlxr d "=0x00fff000"
.pool
vlxr d "=0"
vlxr d "=0xff00000000000000"
vlxr d "=-1"
vlxr d "=0x0fff000000000000"
.pool
vlxr d "=0"
vlxr d "=0x00ff00000000000"
vlxr d "=0xff00ffff0000000"
vlxr d "=0xff00ffff0000000"
.pool
# pool should be aligned to 8-byte.
.p2align 3
vldr d1, =0x0000fff000000000
.pool
# no error when code is align already.
.p2align 3
add r0, r1, #0
vldr d1, =0x0000fff000000000
.pool
.p2align 3
vldr d1, =0x0000fff000000000
vldr s2, =0xff000000
# padding A
vldr d3, =0x0000fff000000001
# reuse padding slot A
vldr s4, =0xff000001
# reuse d3
vldr d5, =0x0000fff000000001
# new 8-byte entry
vldr d6, =0x0000fff000000002
# new 8-byte entry
vldr d7, =0x0000fff000000003
# new 4-byte entry
vldr s8, =0xff000002
# padding B
vldr d9, =0x0000fff000000004
# reuse padding slot B
vldr s10, =0xff000003
# new 8-byte entry
vldr d11, =0x0000fff000000005
# new 4 entry
vldr s12, =0xff000004
# new 4 entry
vldr s13, =0xff000005
# reuse value of s4 in pool
vldr s14, =0xff000001
# reuse high part of d1 in pool
vldr s15, =0x0000fff0
# 8-byte entry reuse two 4-byte entries.
# d16 reuse s12, s13
vldr d16, =0xff000005ff000004
# d17 should not reuse high part of d11 and s12.
# because the it's align 8-byte aligned.
vldr d17, =0xff0000040000fff0
.pool
|
tactcomplabs/xbgas-binutils-gdb
| 2,689
|
gas/testsuite/gas/arm/mve-vstrldr-3.s
|
.syntax unified
.thumb
.macro n_vstr_w_vldr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
\op \op1, [\op2], #\imm
\op \op1, [\op2], #-\imm
.endr
.endr
.endm
.irp mnem, vstrb.16, vstrb.32
.irp imm, 0, 1, 2, 4, 8, 16, 32, 64, 127, 120, 15
n_vstr_w_vldr \mnem, \imm
.endr
.endr
.irp imm, 0, 2, 4, 8, 16, 32, 64, 128, 254, 240, 30
n_vstr_w_vldr vstrh.32, \imm
.endr
.macro wb_same_size_vstr_vldr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
\op \op1, [\op2], #\imm
\op \op1, [\op2], #-\imm
.endr
.endr
.endm
.macro no_wb_same_size_vstr_vldr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
.endr
.endr
.endm
.irp mnem, vstrb.8, vstrb.s8, vstrb.u8
.irp imm, 0, 1, 2, 4, 8, 16, 32, 64, 127, 120, 15
wb_same_size_vstr_vldr \mnem, \imm
no_wb_same_size_vstr_vldr \mnem, \imm
.endr
.endr
.irp mnem, vstrh.16, vstrh.s16, vstrh.u16, vstrh.f16
.irp imm, 0, 2, 4, 8, 16, 32, 64, 128, 254, 240, 30
wb_same_size_vstr_vldr \mnem, \imm
no_wb_same_size_vstr_vldr \mnem, \imm
.endr
.endr
.irp mnem, vstrw.32, vstrw.s32, vstrw.u32, vstrw.f32
.irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 480, 60
wb_same_size_vstr_vldr \mnem, \imm
no_wb_same_size_vstr_vldr \mnem, \imm
.endr
.endr
vpstet
vstrbt.u8 q0, [r12, #1]
vstrbe.16 q3, [r2, #-127]
vstrbt.32 q3, [r3, #-93]!
vpstete
vstrht.f16 q5, [r4], #254
vstrhe.32 q5, [r0, #126]
vstrwt.32 q3, [r5, #508]
vstrwe.u32 q5, [r8], #244
.irp mnem, vldrb.s16, vldrb.u16, vldrb.s32, vldrb.u32
.irp imm, 0, 1, 2, 4, 8, 16, 32, 64, 127, 120, 15
n_vstr_w_vldr \mnem, \imm
.endr
.endr
.irp mnem, vldrh.s32, vldrh.u32
.irp imm, 0, 2, 4, 8, 16, 32, 64, 128, 254, 240, 30
n_vstr_w_vldr \mnem, \imm
.endr
.endr
.irp mnem, vldrb.8, vldrb.s8, vldrb.u8
.irp imm, 0, 1, 2, 4, 8, 16, 32, 64, 127, 120, 15
wb_same_size_vstr_vldr \mnem, \imm
no_wb_same_size_vstr_vldr \mnem, \imm
.endr
.endr
.irp mnem, vldrh.16, vldrh.s16, vldrh.u16, vldrh.f16
.irp imm, 0, 2, 4, 8, 16, 32, 64, 128, 254, 240, 30
wb_same_size_vstr_vldr \mnem, \imm
no_wb_same_size_vstr_vldr \mnem, \imm
.endr
.endr
.irp mnem, vldrw.32, vldrw.s32, vldrw.u32, vldrw.f32
.irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 480, 60
wb_same_size_vstr_vldr \mnem, \imm
no_wb_same_size_vstr_vldr \mnem, \imm
.endr
.endr
vpstet
vldrbt.u8 q0, [r12, #1]
vldrbe.u16 q3, [r2, #-127]
vldrbt.u32 q3, [r3, #-93]!
vpstete
vldrht.f16 q5, [r4], #254
vldrhe.s32 q5, [r0, #126]
vldrwt.32 q3, [r5, #508]
vldrwe.u32 q5, [r8], #244
|
tactcomplabs/xbgas-binutils-gdb
| 1,983
|
gas/testsuite/gas/arm/neon-ldst-es.s
|
@ test element and structure loads and stores.
.text
.arm
.syntax unified
vst2.8 {d2,d3},[r6,:128]
vld3.8 {d1,d2,d3},[r7]!
vst3.16 {d1,d3,d5},[r9:64],r3
vld4.32 {d2,d3,d4,d5},[r10]
vst4.16 {d1,d3,d5,d7},[r10]
vld1.16 {d1[],d2[]},[r10]
vld1.16 {d1[]},[r10,:16]
vld2.32 {d1[],d3[]},[r10:64]
vld3.s8 {d3[],d4[],d5[]},[r10],r12
vld4.16 {d10[],d12[],d14[],d16[]},[r9]!
vld4.16 {d10[],d11[],d12[],d13[]},[r9,:64]
vld4.32 {d10[],d11[],d12[],d13[]},[r9,:64]
vld4.32 {d10[],d11[],d12[],d13[]},[r9,:128]
vld1.8 {d3[7]},[r5]!
vst1.16 {d5[3]},[r5,:16]
vld2.16 {d3[3],d4[3]},[r5,:32]!
vst3.32 {d8[1],d9[1],d10[1]},[r5],r3
vld1.8 {d8[2]},[r7]
vld1.16 {d8[2]},[r7]
vld1.16 {d8[2]},[r7:16]
vld1.32 {d8[1]},[r7]
vld1.32 {d8[1]},[r7:32]
vld2.8 {d8[1],d9[1]},[r7]
vld2.8 {d8[1],d9[1]},[r7:16]
vld2.16 {d8[1],d9[1]},[r7]
vld2.16 {d8[1],d9[1]},[r7:32]
vld2.16 {d8[1],d10[1]},[r7]
vld2.16 {d8[1],d10[1]},[r7:32]
vld2.32 {d8[1],d9[1]},[r7]
vld2.32 {d8[1],d9[1]},[r7:64]
vld2.32 {d8[1],d10[1]},[r7]
vld2.32 {d8[1],d10[1]},[r7:64]
vld3.8 {d8[1],d9[1],d10[1]},[r7]
vld3.16 {d8[1],d9[1],d10[1]},[r7]
vld3.16 {d8[1],d10[1],d12[1]},[r7]
vld3.32 {d8[1],d9[1],d10[1]},[r7]
vld3.32 {d8[1],d10[1],d12[1]},[r7]
vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7]
vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7:32]
vld4.16 {d8[1],d10[1],d12[1],d14[1]},[r7]
vld4.16 {d8[1],d9[1],d10[1],d11[1]},[r7:64]
vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7]
vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7:64]
vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7:128]
vtbl.8 d3,{d4},d5
vtbl.8 d3,{q1-q2},d5
vtbl.8 d3,{q15},d5
vld2.32 {q1},[r7]
vld4.32 {q1-q2},[r7]
vld4.32 {q14-q15},[r7]
@ PR 14987 and 14887: Allow for whitespace in the instruction.
vld1.32 { d1 [ ] } , [ r2 ] , r3
vld1.64 {d0}, [r0]
vld1.64 {d0-d3}, [r0]
|
tactcomplabs/xbgas-binutils-gdb
| 2,872
|
gas/testsuite/gas/arm/iwmmxt2.s
|
.text
.global iwmmxt2
iwmmxt2:
waddhc wr4, wr5, wr6
waddwc wr7, wr8, wr9
wmadduxgt wr4, wr5, wr6
wmadduneq wr7, wr8, wr9
wmaddsxne wr4, wr5, wr6
wmaddsnge wr7, wr8, wr9
wmulumr wr1, wr2, wr3
wmulsmr wr1, wr2, wr3
torvscbgt r15
torvschne r15
torvscweq r15
wabsb wr1, wr2
wabsh wr3, wr4
wabsw wr5, wr6
wabsbgt wr1, wr2
wabsdiffb wr1, wr2, wr3
wabsdiffh wr4, wr5, wr6
wabsdiffw wr7, wr8, wr9
wabsdiffbgt wr1, wr2, wr3
waddbhusm wr1, wr2, wr3
waddbhusl wr4, wr5, wr6
waddbhusmgt wr1, wr2, wr3
waddbhuslgt wr4, wr5, wr6
waddsubhx wr1, wr2, wr3
waddsubhxlt wr4, wr5, wr6
waddsubhxeq wr1, wr2, wr3
waddsubhxgt wr4, wr5, wr6
wavg4 wr1, wr2, wr3
wavg4gt wr4, wr5, wr6
wavg4r wr1, wr2, wr3
wavg4rgt wr4, wr5, wr6
wldrd wr1, [r1], -r2
wldrd wr2, [r1], -r2,lsl #3
wldrd wr3, [r1], +r2
wldrd wr4, [r1], +r2,lsl #4
wldrd wr5, [r1, -r2]
wldrd wr6, [r1, -r2,lsl #3]
wldrd wr7, [r1, +r2]
wldrd wr8, [r1, +r2,lsl #4]
wldrd wr9, [r1, -r2]!
wldrd wr10, [r1, -r2,lsl #3]!
wldrd wr11, [r1, +r2]!
wldrd wr12, [r1, +r2,lsl #4]!
wmerge wr1, wr2, wr3, #4
wmergegt wr1, wr2, wr3, #4
wmiatteq wr1, wr2, wr3
wmiatbgt wr1, wr2, wr3
wmiabtne wr1, wr2, wr3
wmiabbgt wr1, wr2, wr3
wmiattneq wr1, wr2, wr3
wmiatbnne wr1, wr2, wr3
wmiabtngt wr1, wr2, wr3
wmiabbneq wr1, wr2, wr3
wmiawtteq wr1, wr2, wr3
wmiawtbgt wr1, wr2, wr3
wmiawbtne wr1, wr2, wr3
wmiawbbgt wr1, wr2, wr3
wmiawttnne wr1, wr2, wr3
wmiawtbngt wr1, wr2, wr3
wmiawbtneq wr1, wr2, wr3
wmiawbbnne wr1, wr2, wr3
wmulwumeq wr1, wr2, wr3
wmulwumrgt wr1, wr2, wr3
wmulwsmne wr1, wr2, wr3
wmulwsmreq wr1, wr2, wr3
wmulwlgt wr1, wr2, wr3
wmulwlge wr1, wr2, wr3
wqmiattne wr1, wr2, wr3
wqmiattneq wr1, wr2, wr3
wqmiatbgt wr1, wr2, wr3
wqmiatbnge wr1, wr2, wr3
wqmiabtne wr1, wr2, wr3
wqmiabtneq wr1, wr2, wr3
wqmiabbgt wr1, wr2, wr3
wqmiabbnne wr1, wr2, wr3
wqmulmgt wr1, wr2, wr3
wqmulmreq wr1, wr2, wr3
wqmulwmgt wr1, wr2, wr3
wqmulwmreq wr1, wr2, wr3
wstrd wr1, [r1], -r2
wstrd wr2, [r1], -r2,lsl #3
wstrd wr3, [r1], +r2
wstrd wr4, [r1], +r2,lsl #4
wstrd wr5, [r1, -r2]
wstrd wr6, [r1, -r2,lsl #3]
wstrd wr7, [r1, +r2]
wstrd wr8, [r1, +r2,lsl #4]
wstrd wr9, [r1, -r2]!
wstrd wr10, [r1, -r2,lsl #3]!
wstrd wr11, [r1, +r2]!
wstrd wr12, [r1, +r2,lsl #4]!
wsubaddhxgt wr1, wr2, wr3
wrorh wr1, wr2, #0
wrorw wr1, wr2, #0
wrord wr1, wr2, #0
wrorh wr1, wr2, #21
wrorw wr1, wr2, #13
wrord wr1, wr2, #14
wsllh wr1, wr2, #0
wsllw wr1, wr2, #0
wslld wr1, wr2, #0
wsllh wr2, wr9, #11
wsllw wr3, wr5, #13
wslld wr3, wr8, #15
wsrah wr1, wr2, #0
wsraw wr1, wr2, #0
wsrad wr1, wr2, #0
wsrah wr2, wr9, #12
wsraw wr3, wr5, #14
wsrad wr3, wr8, #16
wsrlh wr1, wr2, #0
wsrlw wr1, wr2, #0
wsrld wr1, wr2, #0
wsrlh wr2, wr9, #12
wsrlw wr3, wr5, #14
wsrld wr3, wr8, #16
|
tactcomplabs/xbgas-binutils-gdb
| 4,601
|
gas/testsuite/gas/arm/vfp1_t2.s
|
@ VFP Instructions for D variants (Double precision)
@ Same as vfp1.s, but for Thumb-2
.syntax unified
.thumb
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fcmped d0, d0
fcmpezd d0
fcmpd d0, d0
fcmpzd d0
@ Monadic data operations
fabsd d0, d0
fcpyd d0, d0
fnegd d0, d0
fsqrtd d0, d0
@ Dyadic data operations
faddd d0, d0, d0
fdivd d0, d0, d0
fmacd d0, d0, d0
fmscd d0, d0, d0
fmuld d0, d0, d0
fnmacd d0, d0, d0
fnmscd d0, d0, d0
fnmuld d0, d0, d0
fsubd d0, d0, d0
@ Load/store operations
fldd d0, [r0]
fstd d0, [r0]
@ Load/store multiple operations
fldmiad r0, {d0}
fldmfdd r0, {d0}
fldmiad r0!, {d0}
fldmfdd r0!, {d0}
fldmdbd r0!, {d0}
fldmead r0!, {d0}
fstmiad r0, {d0}
fstmead r0, {d0}
fstmiad r0!, {d0}
fstmead r0!, {d0}
fstmdbd r0!, {d0}
fstmfdd r0!, {d0}
@ Conversion operations
fsitod d0, s0
fuitod d0, s0
ftosid s0, d0
ftosizd s0, d0
ftouid s0, d0
ftouizd s0, d0
fcvtds d0, s0
fcvtsd s0, d0
@ ARM from VFP operations
fmrdh r0, d0
fmrdl r0, d0
@ VFP From ARM operations
fmdhr d0, r0
fmdlr d0, r0
@ Now we test that the register fields are updated correctly for
@ each class of instruction.
@ Single register operations (compare-zero):
fcmpzd d1
fcmpzd d2
fcmpzd d15
@ Two register comparison operations:
fcmpd d0, d1
fcmpd d0, d2
fcmpd d0, d15
fcmpd d1, d0
fcmpd d2, d0
fcmpd d15, d0
fcmpd d5, d12
@ Two register data operations (monadic)
fnegd d0, d1
fnegd d0, d2
fnegd d0, d15
fnegd d1, d0
fnegd d2, d0
fnegd d15, d0
fnegd d12, d5
@ Three register data operations (dyadic)
faddd d0, d0, d1
faddd d0, d0, d2
faddd d0, d0, d15
faddd d0, d1, d0
faddd d0, d2, d0
faddd d0, d15, d0
faddd d1, d0, d0
faddd d2, d0, d0
faddd d15, d0, d0
faddd d12, d9, d5
@ Conversion operations
fcvtds d0, s1
fcvtds d0, s2
fcvtds d0, s31
fcvtds d1, s0
fcvtds d2, s0
fcvtds d15, s0
fcvtsd s1, d0
fcvtsd s2, d0
fcvtsd s31, d0
fcvtsd s0, d1
fcvtsd s0, d2
fcvtsd s0, d15
@ Move to VFP from ARM
fmrdh r1, d0
fmrdh r14, d0
fmrdh r0, d1
fmrdh r0, d2
fmrdh r0, d15
fmrdl r1, d0
fmrdl r14, d0
fmrdl r0, d1
fmrdl r0, d2
fmrdl r0, d15
@ Move to ARM from VFP
fmdhr d0, r1
fmdhr d0, r14
fmdhr d1, r0
fmdhr d2, r0
fmdhr d15, r0
fmdlr d0, r1
fmdlr d0, r14
fmdlr d1, r0
fmdlr d2, r0
fmdlr d15, r0
@ Load/store operations
fldd d0, [r1]
fldd d0, [r14]
fldd d0, [r0, #0]
fldd d0, [r0, #1020]
fldd d0, [r0, #-1020]
fldd d1, [r0]
fldd d2, [r0]
fldd d15, [r0]
fstd d12, [r12, #804]
@ Load/store multiple operations
fldmiad r0, {d1}
fldmiad r0, {d2}
fldmiad r0, {d15}
fldmiad r0, {d0-d1}
fldmiad r0, {d0-d2}
fldmiad r0, {d0-d15}
fldmiad r0, {d1-d15}
fldmiad r0, {d2-d15}
fldmiad r0, {d14-d15}
fldmiad r1, {d0}
fldmiad r14, {d0}
@ Check that we assemble all the register names correctly
fcmpzd d0
fcmpzd d1
fcmpzd d2
fcmpzd d3
fcmpzd d4
fcmpzd d5
fcmpzd d6
fcmpzd d7
fcmpzd d8
fcmpzd d9
fcmpzd d10
fcmpzd d11
fcmpzd d12
fcmpzd d13
fcmpzd d14
fcmpzd d15
@ Now we check the placement of the conditional execution substring.
@ On VFP this is always at the end of the instruction.
@ Comparison operations
itttt eq
fcmpedeq d1, d15
fcmpezdeq d2
fcmpdeq d3, d14
fcmpzdeq d4
@ Monadic data operations
itttt eq
fabsdeq d5, d13
fcpydeq d6, d12
fnegdeq d7, d11
fsqrtdeq d8, d10
@ Dyadic data operations
itttt eq
fadddeq d9, d1, d15
fdivdeq d2, d3, d14
fmacdeq d4, d13, d12
fmscdeq d5, d6, d11
itttt eq
fmuldeq d7, d10, d9
fnmacdeq d8, d9, d10
fnmscdeq d7, d6, d11
fnmuldeq d5, d4, d12
ittt eq
fsubdeq d3, d13, d14
@ Load/store operations
flddeq d2, [r5]
fstdeq d1, [r12]
@ Load/store multiple operations
itttt eq
fldmiadeq r1, {d1}
fldmfddeq r2, {d2}
fldmiadeq r3!, {d3}
fldmfddeq r4!, {d4}
itttt eq
fldmdbdeq r5!, {d5}
fldmeadeq r6!, {d6}
fstmiadeq r7, {d15}
fstmeadeq r8, {d14}
itttt eq
fstmiadeq r9!, {d13}
fstmeadeq r10!, {d12}
fstmdbdeq r11!, {d11}
fstmfddeq r12!, {d10}
@ Conversion operations
itttt eq
fsitodeq d15, s1
fuitodeq d1, s31
ftosideq s1, d15
ftosizdeq s31, d2
itttt eq
ftouideq s15, d2
ftouizdeq s11, d3
fcvtdseq d1, s10
fcvtsdeq s11, d1
@ ARM from VFP operations
itttt eq
fmrdheq r8, d1
fmrdleq r7, d15
@ VFP From ARM operations
fmdhreq d1, r15
fmdlreq d15, r1
# Add three nop instructions to ensure that the
# output is 32-byte aligned as required for arm-aout.
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,975
|
gas/testsuite/gas/arm/mve-vpt.s
|
.syntax unified
.thumb
.macro ins_2 cond2
vaddt.i32 q0, q1, q2
vadd\cond2\().i32 q0, q1, q2
.endm
.macro ins_3 cond2, cond3
ins_2 \cond2
vadd\cond3\().i32 q0, q1, q2
.endm
.macro ins_4 cond2, cond3, cond4
ins_3 \cond2, \cond3
vadd\cond4\().i32 q0, q1, q2
.endm
.macro vpt_1 data, cond, op1, op2
vpt\data \cond, \op1, \op2
vaddt.i32 q0, q1, q2
.endm
.macro help mask, data, cond, op1, op2
vpt\mask\data \cond, \op1, \op2
.endm
.macro vpt_2 data, cond, op1, op2
.irp cond2, t, e
help \cond2, \data, \cond, \op1, \op2
ins_2 \cond2
.endr
.endm
.macro vpt_3 data, cond, op1, op2
.irp cond2, t, e
.irp cond3, t, e
help \cond2\cond3, \data, \cond, \op1, \op2
ins_3 \cond2, \cond3
.endr
.endr
.endm
.macro vpt_4 data, cond, op1, op2
.irp cond2, t, e
.irp cond3, t, e
.irp cond4, t, e
help \cond2\cond3\cond4, \data, \cond, \op1, \op2
ins_4 \cond2, \cond3, \cond4
.endr
.endr
.endr
.endm
.macro vpt_qq data, cond
.irp op1, q0, q1, q4, q7
.irp op2, q0, q2, q5, q7
vpt_1 \data, \cond, \op1, \op2
vpt_2 \data, \cond, \op1, \op2
vpt_3 \data, \cond, \op1, \op2
vpt_4 \data, \cond, \op1, \op2
.endr
.endr
.endm
.macro vpt_qr data, cond
.irp op1, q0, q1, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r9, r10, r12, r14, zr
vpt_1 \data, \cond, \op1, \op2
vpt_2 \data, \cond, \op1, \op2
vpt_3 \data, \cond, \op1, \op2
vpt_4 \data, \cond, \op1, \op2
.endr
.endr
.endm
.irp data, .f16, .f32
.irp cond, eq, ne, gt, le, ge, lt
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
.irp data, .i8, .i16, .i32
.irp cond, eq, ne
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
.irp data, .u8, .u16, .u32
.irp cond, cs, hi
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
.irp data, .s8, .s16, .s32
.irp cond, ge, lt, gt, le
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
vpst
vaddt.i32 q0, q1, q2
.irp cond2, t, e
vpst\cond2
ins_2 \cond2
.irp cond3, t, e
vpst\cond2\cond3
ins_3 \cond2, \cond3
.irp cond4, t, e
vpst\cond2\cond3\cond4
ins_4 \cond2, \cond3, \cond4
.endr
.endr
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 3,155
|
gas/testsuite/gas/arm/mve-vldr-bad-3.s
|
.macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0]
.endr
.endm
.syntax unified
.thumb
vldrb.8 q0, [r0, #128]
vldrb.8 q0, [r0, #-128]
vldrb.u16 q0, [r0, #128]
vldrb.u16 q0, [r0, #-128]
vldrb.u32 q0, [r0, #128]
vldrb.u32 q0, [r0, #-128]
vldrb.8 q0, [r0, #128]!
vldrb.8 q0, [r0, #-128]!
vldrb.u16 q0, [r0, #128]!
vldrb.u16 q0, [r0, #-128]!
vldrb.u32 q0, [r0, #128]!
vldrb.u32 q0, [r0, #-128]!
vldrb.8 q0, [r0], #128
vldrb.8 q0, [r0], #-128
vldrb.u16 q0, [r0], #128
vldrb.u16 q0, [r0], #-128
vldrb.u32 q0, [r0], #128
vldrb.u32 q0, [r0], #-128
vldrb.u16 q0, [r10, #2]
vldrb.u16 q0, [r10, #2]!
vldrb.u16 q0, [r10], #2
vldrb.8 q0, [sp, #2]!
vldrb.8 q0, [sp], #2
vldrb.8 q0, [pc, #2]
cond vldrb
vldrb.16 q0, [r0]
vldrb.f16 q0, [r0]
vldrb.p16 q0, [r0]
vldrb.32 q0, [r0]
vldrb.f32 q0, [r0]
vldrh.16 q0, [r0, #1]
vldrh.16 q0, [r0, #17]
vldrh.16 q0, [r0, #-17]
vldrh.16 q0, [r0, #256]
vldrh.16 q0, [r0, #-256]
vldrh.u32 q0, [r0, #1]
vldrh.u32 q0, [r0, #17]
vldrh.u32 q0, [r0, #-17]
vldrh.u32 q0, [r0, #256]
vldrh.u32 q0, [r0, #-256]
vldrh.16 q0, [r0, #1]!
vldrh.16 q0, [r0, #17]!
vldrh.16 q0, [r0, #-17]!
vldrh.16 q0, [r0, #256]!
vldrh.16 q0, [r0, #-256]!
vldrh.s32 q0, [r0, #1]!
vldrh.s32 q0, [r0, #17]!
vldrh.s32 q0, [r0, #-17]!
vldrh.s32 q0, [r0, #256]!
vldrh.s32 q0, [r0, #-256]!
vldrh.16 q0, [r0], #1
vldrh.16 q0, [r0], #17
vldrh.16 q0, [r0], #-17
vldrh.16 q0, [r0], #256
vldrh.16 q0, [r0], #-256
vldrh.u32 q0, [r0], #1
vldrh.u32 q0, [r0], #17
vldrh.u32 q0, [r0], #-17
vldrh.u32 q0, [r0], #256
vldrh.u32 q0, [r0], #-256
vldrh.u32 q0, [r10, #4]
vldrh.16 q0, [sp, #2]!
vldrh.16 q0, [sp], #2
vldrh.16 q0, [pc, #2]
cond vldrh
vldrh.8 q0, [r0]
vldrh.u8 q0, [r0]
vldrh.s8 q0, [r0]
vldrh.p8 q0, [r0]
vldrh.32 q0, [r0]
vldrh.f32 q0, [r0]
vldrw.32 q0, [r0, #3]
vldrw.32 q0, [r0, #-3]
vldrw.32 q0, [r0, #514]
vldrw.32 q0, [r0, #-258]
vldrw.32 q0, [r0, #258]
vldrw.32 q0, [r0, #516]
vldrw.32 q0, [r0, #-516]
vldrw.32 q0, [r0, #3]!
vldrw.32 q0, [r0, #-3]!
vldrw.32 q0, [r0, #514]!
vldrw.32 q0, [r0, #-258]!
vldrw.32 q0, [r0, #258]!
vldrw.32 q0, [r0, #516]!
vldrw.32 q0, [r0, #-516]!
vldrw.32 q0, [r0], #3
vldrw.32 q0, [r0], #-3
vldrw.32 q0, [r0], #514
vldrw.32 q0, [r0], #-258
vldrw.32 q0, [r0], #258
vldrw.32 q0, [r0], #516
vldrw.32 q0, [r0], #-516
vldrw.32 q0, [sp, #4]!
vldrw.32 q0, [pc, #4]
cond vldrw
vldrw.8 q0, [r0]
vldrw.u8 q0, [r0]
vldrw.s8 q0, [r0]
vldrw.p8 q0, [r0]
vldrw.16 q0, [r0]
vldrw.u16 q0, [r0]
vldrw.s16 q0, [r0]
vldrw.f16 q0, [r0]
vldrw.p16 q0, [r0]
it eq
vldrbeq.8 q0, [r0]
vldrbeq.8 q0, [r0]
vpst
vldrbeq.8 q0, [r0]
vldrbt.8 q0, [r0]
vpst
vldrb.8 q0, [r0]
it eq
vldrheq.16 q0, [r0]
vldrheq.16 q0, [r0]
vpst
vldrheq.16 q0, [r0]
vldrht.16 q0, [r0]
vpst
vldrh.16 q0, [r0]
it eq
vldrweq.32 q0, [r0]
vldrweq.32 q0, [r0]
vpst
vldrweq.32 q0, [r0]
vldrwt.32 q0, [r0]
vpst
vldrw.32 q0, [r0]
.irp op1, 16, 32, 64, f16, f32, f64, p16, p32, p64, s8
vldrb.\op1 q0, [r2, q3]
.endr
.irp op1, 8, 32, 64, f32, f64, p32, p64, s16
vldrh.\op1 q0, [r2, q3, uxtw #1]
.endr
.irp op1, 8, 16, 64, f16, f64, p16, p64, s32
vldrw.\op1 q0, [r2, q3, uxtw #2]
.endr
.irp op1, 8, 16, 32, f16, f32, p16, p32, s64
vldrd.\op1 q0, [r2, q3, uxtw #3]
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 4,535
|
gas/testsuite/gas/arm/archv6.s
|
.text
.align 0
label:
cps #15
cpsid if
cpsie if
ldrex r2, [r4]
ldrexne r4, [r8]
mcrr2 p0, 12, r7, r5, c3
mrrc2 p0, 12, r7, r5, c3
pkhbt r2, r5, r8
pkhbt r2, r5, r8, LSL #3
pkhbtal r2, r5, r8, LSL #3
pkhbteq r2, r5, r8, LSL #3
pkhtb r2, r5, r8 @ Equivalent to pkhbt r2, r8, r5.
pkhtb r2, r5, r8, ASR #3
pkhtbal r2, r5, r8, ASR #3
pkhtbeq r2, r5, r8, ASR #3
qadd16 r2, r4, r7
qadd16ne r2, r4, r7
qadd8 r2, r4, r7
qadd8ne r2, r4, r7
qaddsubx r2, r4, r7
qaddsubxne r2, r4, r7
qsub16 r2, r4, r7
qsub16ne r2, r4, r7
qsub8 r2, r4, r7
qsub8ne r2, r4, r7
qsubaddx r2, r4, r7
qsubaddx r2, r4, r7
rev r2, r4
rev16 r2, r4
rev16ne r3, r5
revne r3, r5
revsh r2, r4
revshne r3, r5
rfeda r2
rfefa r2!
rfedb r2
rfeea r2!
rfeia r2
rfefd r2!
rfeib r2
rfeed r2!
rfe r2
rfe r2!
sadd16 r2, r4, r7
sadd16ne r2, r4, r7
sxtah r2, r4, r5
sxtah r2, r4, r5, ROR #8
sxtahne r2, r4, r5
sxtahne r2, r4, r5, ROR #8
sadd8 r2, r4, r7
sadd8ne r2, r4, r7
sxtab16 r2, r4, r5
sxtab16 r2, r4, r5, ROR #8
sxtab16ne r2, r4, r5
sxtab16ne r2, r4, r5, ROR #8
sxtab r2, r4, r5
sxtab r2, r4, r5, ROR #8
sxtabne r2, r4, r5
sxtabne r2, r4, r5, ROR #8
saddsubx r2, r4, r7
saddsubxne r2, r4, r7
sel r1, r2, r3
selne r1, r2, r3
setend be
setend le
shadd16 r2, r4, r7
shadd16ne r2, r4, r7
shadd8 r2, r4, r7
shadd8ne r2, r4, r7
shaddsubx r2, r4, r7
shaddsubxne r2, r4, r7
shsub16 r2, r4, r7
shsub16ne r2, r4, r7
shsub8 r2, r4, r7
shsub8ne r2, r4, r7
shsubaddx r2, r4, r7
shsubaddxne r2, r4, r7
smlad r1,r2,r3,r4
smladle r1,r2,r3,r4
smladx r1,r2,r3,r4
smladxle r1,r2,r3,r4
smlald r1,r2,r3,r4
smlaldle r1,r2,r3,r4
smlaldx r1,r2,r3,r4
smlaldxle r1,r2,r3,r4
smlsd r1,r2,r3,r4
smlsdle r1,r2,r3,r4
smlsdx r1,r2,r3,r4
smlsdxle r1,r2,r3,r4
smlsld r1,r2,r3,r4
smlsldle r1,r2,r3,r4
smlsldx r1,r2,r3,r4
smlsldxle r1,r2,r3,r4
smmla r1,r2,r3,r4
smmlale r1,r2,r3,r4
smmlar r1,r2,r3,r4
smmlarle r1,r2,r3,r4
smmls r1,r2,r3,r4
smmlsle r1,r2,r3,r4
smmlsr r1,r2,r3,r4
smmlsrle r1,r2,r3,r4
smmul r1,r2,r3
smmulle r1,r2,r3
smmulr r1,r2,r3
smmulrle r1,r2,r3
smuad r1,r2,r3
smuadle r1,r2,r3
smuadx r1,r2,r3
smuadxle r1,r2,r3
smusd r1,r2,r3
smusdle r1,r2,r3
smusdx r1,r2,r3
smusdxle r1,r2,r3
srsia #16
srsib #16!
ssat r1, #1, r2
ssat r1, #1, r2, ASR #2
ssat r1, #1, r2, LSL #2
ssat16 r1, #1, r1
ssat16le r1, #1, r1
ssub16 r2, r4, r7
ssub16ne r2, r4, r7
ssub8 r2, r4, r7
ssub8ne r2, r4, r7
ssubaddx r2, r4, r7
ssubaddxne r2, r4, r7
strex r1, r2, [r3]
strexne r1, r2, [r3]
sxth r2, r5
sxth r2, r5, ROR #8
sxthne r2, r5
sxthne r2, r5, ROR #8
sxtb16 r2, r5
sxtb16 r2, r5, ROR #8
sxtb16ne r2, r5
sxtb16ne r2, r5, ROR #8
sxtb r2, r5
sxtb r2, r5, ROR #8
sxtbne r2, r5
sxtbne r2, r5, ROR #8
uadd16 r2, r4, r7
uadd16ne r2, r4, r7
uxtah r2, r3, r5
uxtah r2, r3, r5, ROR #8
uxtahne r2, r3, r5
uxtahne r2, r3, r5, ROR #8
uadd8 r2, r4, r7
uadd8ne r2, r4, r7
uxtab16 r2, r3, r5
uxtab16 r2, r3, r5, ROR #8
uxtab16ne r2, r3, r5
uxtab16ne r2, r3, r5, ROR #8
uxtab r2, r3, r5
uxtab r2, r3, r5, ROR #8
uxtabne r2, r3, r5
uxtabne r2, r3, r5, ROR #8
uaddsubx r2, r4, r7
uaddsubxne r2, r4, r7
uhadd16 r2, r4, r7
uhadd16ne r2, r4, r7
uhadd8 r2, r4, r7
uhadd8ne r2, r4, r7
uhaddsubx r2, r4, r7
uhaddsubxne r2, r4, r7
uhsub16 r2, r4, r7
uhsub16ne r2, r4, r7
uhsub8 r2, r4, r7
uhsub8ne r2, r4, r7
uhsubaddx r2, r4, r7
uhsubaddxne r2, r4, r7
umaal r1, r2, r3, r4
umaalle r1, r2, r3, r4
uqadd16 r2, r4, r7
uqadd16ne r2, r4, r7
uqadd8 r2, r4, r7
uqadd8ne r2, r4, r7
uqaddsubx r2, r4, r7
uqaddsubxne r2, r4, r7
uqsub16 r2, r4, r7
uqsub16ne r2, r4, r7
uqsub8 r2, r4, r7
uqsub8ne r2, r4, r7
uqsubaddx r2, r4, r7
uqsubaddxne r2, r4, r7
usad8 r1, r2, r3
usad8ne r1, r2, r3
usada8 r1, r2, r3, r4
usada8ne r1, r2, r3, r4
usat r1, #15, r2
usat r1, #15, r2, ASR #4
usat r1, #15, r2, LSL #4
usat16 r1, #15, r2
usat16le r1, #15, r2
usatle r1, #15, r2
usatle r1, #15, r2, ASR #4
usatle r1, #15, r2, LSL #4
usub16 r2, r4, r7
usub16ne r2, r4, r7
usub8 r2, r4, r7
usub8ne r2, r4, r7
usubaddx r2, r4, r7
usubaddxne r2, r4, r7
uxth r2, r5
uxth r2, r5, ROR #8
uxthne r2, r5
uxthne r2, r5, ROR #8
uxtb16 r2, r5
uxtb16 r2, r5, ROR #8
uxtb16ne r2, r5
uxtb16ne r2, r5, ROR #8
uxtb r2, r5
uxtb r2, r5, ROR #8
uxtbne r2, r5
uxtbne r2, r5, ROR #8
cpsie if, #10
cpsie if, #21
srsia sp, #16
srsib sp!, #16
|
tactcomplabs/xbgas-binutils-gdb
| 1,332
|
gas/testsuite/gas/arm/arm7t.s
|
.text
.align 0
loadhalfwords:
ldrh r0, [r1]
ldrh r0, [r1]!
ldrh r0, [r1, r2]
ldrh r0, [r1, r2]!
ldrh r0, [r1,#0x0C]
ldrh r0, [r1,#0x0C]!
ldrh r0, [r1,#-0x0C]
ldrh r0, [r1], r2
ldrh r0, =0xFF00
ldrh r0, =0xC0DE
ldrh r0, .L2
storehalfwords:
strh r0, [r1]
strh r0, [r1]!
strh r0, [r1, r2]
strh r0, [r1, r2]!
strh r0, [r1,#0x0C]
strh r0, [r1,#0x0C]!
strh r0, [r1,#-0x0C]
strh r0, [r1], r2
strh r0, .L2
loadsignedbytes:
ldrsb r0, [r1]
ldrsb r0, [r1]!
ldrsb r0, [r1, r2]
ldrsb r0, [r1, r2]!
ldrsb r0, [r1,#0x0C]
ldrsb r0, [r1,#0x0C]!
ldrsb r0, [r1,#-0x0C]
ldrsb r0, [r1], r2
ldrsb r0, =0xDE
ldrsb r0, .L2
loadsignedhalfwords:
ldrsh r0, [r1]
ldrsh r0, [r1]!
ldrsh r0, [r1, r2]
ldrsh r0, [r1, r2]!
ldrsh r0, [r1, #0x0C]
ldrsh r0, [r1, #0x0C]!
ldrsh r0, [r1, #-0x0C]
ldrsh r0, [r1], r2
ldrsh r0, =0xFF00
ldrsh r0, =0xC0DE
ldrsh r0, .L2
misc:
ldralh r0, [r1, r2]
ldrneh r0, [r1, r2]
ldrhih r0, [r1, r2]
ldrlth r0, [r1, r2]
ldralsh r0, [r1, r2]
ldrnesh r0, [r1, r2]
ldrhish r0, [r1, r2]
ldrltsh r0, [r1, r2]
ldralsb r0, [r1, r2]
ldrnesb r0, [r1, r2]
ldrhisb r0, [r1, r2]
ldrltsb r0, [r1, r2]
ldrsh r0, =0xC0DE
ldrsh r0, =0xDEAD
.align
.L2:
.word fred
.ltorg
# Add two nop instructions to ensure that the
# output is 32-byte aligned as required for arm-aout.
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,166
|
gas/testsuite/gas/arm/vfpv3-32drs.s
|
.arm
.syntax unified
fcpyd d3,d22
fcpyd d22,d3
fcvtds d22,s22
fcvtsd s22,d22
fmdhr d21,r4
fmdlr d27,r5
fmrdh r6,d23
fmrdl r7,d25
fsitod d22,s22
fuitod d21,s21
ftosid s20,d20
ftosizd s20,d20
ftouid s19,d19
ftouizd s19,d19
fldd d19,[r10,#4]
fstd d21,[r10,#4]
fldmiad r10!,{d5,d6}
fldmiad r10!,{d18,d19,d20}
fldmiax r10!,{d5,d6}
fldmiax r10!,{d18,d19,d20}
fldmdbx r10!,{d18,d19}
fstmiad r9,{d20,d21,d22,d23,d24}
fabsd d3,d5
fabsd d12,d18
fabsd d18,d19
fnegd d3,d5
fnegd d12,d18
fnegd d18,d19
fsqrtd d3,d5
fsqrtd d12,d18
fsqrtd d18,d19
faddd d3,d5,d6
faddd d12,d18,d4
faddd d18,d19,d20
fsubd d3,d5,d6
fsubd d12,d18,d4
fsubd d18,d19,d20
fmuld d3,d5,d6
fmuld d12,d18,d4
fmuld d18,d19,d20
fdivd d3,d5,d6
fdivd d12,d18,d4
fdivd d18,d19,d20
fmacd d3,d5,d6
fmacd d12,d18,d4
fmacd d18,d19,d20
fmscd d3,d5,d6
fmscd d12,d18,d4
fmscd d18,d19,d20
fnmuld d3,d5,d6
fnmuld d12,d18,d4
fnmuld d18,d19,d20
fnmacd d3,d5,d6
fnmacd d12,d18,d4
fnmacd d18,d19,d20
fnmscd d3,d5,d6
fnmscd d12,d18,d4
fnmscd d18,d19,d20
fcmpd d3,d18
fcmpd d18,d3
fcmpzd d19
fcmped d3,d18
fcmped d18,d3
fcmpezd d19
fmdrr d31,r3,r4
fmrrd r5,r6,d30
|
tactcomplabs/xbgas-binutils-gdb
| 1,602
|
gas/testsuite/gas/arm/half-prec-vfpv3.s
|
.text
vcvtt.f32.f16 s0, s1
vcvtteq.f32.f16 s2, s3
vcvttne.f32.f16 s2, s3
vcvttcs.f32.f16 s2, s3
vcvttcc.f32.f16 s2, s3
vcvttmi.f32.f16 s2, s3
vcvttpl.f32.f16 s2, s3
vcvttvs.f32.f16 s2, s3
vcvttvc.f32.f16 s2, s3
vcvtthi.f32.f16 s2, s3
vcvttls.f32.f16 s2, s3
vcvttge.f32.f16 s2, s3
vcvttlt.f32.f16 s2, s3
vcvttgt.f32.f16 s2, s3
vcvttle.f32.f16 s2, s3
vcvttal.f32.f16 s2, s3
vcvtt.f16.f32 s0, s1
vcvtteq.f16.f32 s2, s3
vcvttne.f16.f32 s2, s3
vcvttcs.f16.f32 s2, s3
vcvttcc.f16.f32 s2, s3
vcvttmi.f16.f32 s2, s3
vcvttpl.f16.f32 s2, s3
vcvttvs.f16.f32 s2, s3
vcvttvc.f16.f32 s2, s3
vcvtthi.f16.f32 s2, s3
vcvttls.f16.f32 s2, s3
vcvttge.f16.f32 s2, s3
vcvttlt.f16.f32 s2, s3
vcvttgt.f16.f32 s2, s3
vcvttle.f16.f32 s2, s3
vcvttal.f16.f32 s2, s3
vcvtb.f32.f16 s0, s1
vcvtbeq.f32.f16 s2, s3
vcvtbne.f32.f16 s2, s3
vcvtbcs.f32.f16 s2, s3
vcvtbcc.f32.f16 s2, s3
vcvtbmi.f32.f16 s2, s3
vcvtbpl.f32.f16 s2, s3
vcvtbvs.f32.f16 s2, s3
vcvtbvc.f32.f16 s2, s3
vcvtbhi.f32.f16 s2, s3
vcvtbls.f32.f16 s2, s3
vcvtbge.f32.f16 s2, s3
vcvtblt.f32.f16 s2, s3
vcvtbgt.f32.f16 s2, s3
vcvtble.f32.f16 s2, s3
vcvtbal.f32.f16 s2, s3
vcvtb.f16.f32 s0, s1
vcvtbeq.f16.f32 s2, s3
vcvtbne.f16.f32 s2, s3
vcvtbcs.f16.f32 s2, s3
vcvtbcc.f16.f32 s2, s3
vcvtbmi.f16.f32 s2, s3
vcvtbpl.f16.f32 s2, s3
vcvtbvs.f16.f32 s2, s3
vcvtbvc.f16.f32 s2, s3
vcvtbhi.f16.f32 s2, s3
vcvtbls.f16.f32 s2, s3
vcvtbge.f16.f32 s2, s3
vcvtblt.f16.f32 s2, s3
vcvtbgt.f16.f32 s2, s3
vcvtble.f16.f32 s2, s3
vcvtbal.f16.f32 s2, s3
|
tactcomplabs/xbgas-binutils-gdb
| 9,347
|
gas/testsuite/gas/arm/sp-pc-validations-bad-t.s
|
.syntax unified
@ Enable Thumb mode
.thumb
.macro it_test opcode operands:vararg
itt eq
\opcode\()eq r15, \operands
moveq r0, r0
.endm
.macro it_testw opcode operands:vararg
itt eq
\opcode\()eq.w r15, \operands
moveq r0, r0
.endm
.macro LOAD operands:vararg
it_test ldr, \operands
.endm
.macro LOADw operands:vararg
it_testw ldr, \operands
.endm
@ Loads ===============================================================
@ LDR (register)
LOAD [r0]
LOAD [r0,#0]
LOAD [sp]
LOAD [sp,#0]
LOADw [r0]
LOADw [r0,#0]
LOAD [r0,#-4]
LOAD [r0],#4
LOAD [r0,#0]!
@ LDR (literal)
LOAD label
LOADw label
LOADw [pc, #-0]
@ LDR (register)
LOAD [r0, r1]
LOADw [r0, r1]
LOADw [r0, r1, LSL #2]
@ LDRB (immediate, Thumb)
ldrb pc, [r0,#4] @ low reg
@ldrb r0, [pc,#4] @ ALLOWED!
ldrb.w sp, [r0,#4] @ Unpredictable
ldrb.w pc, [r0,#4] @ => PLD
ldrb pc, [r0, #-4] @ => PLD
@ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT
ldrb pc, [r0],#4 @ BadReg
ldrb sp, [r0],#4 @ ditto
ldrb pc,[r0,#4]! @ ditto
ldrb sp,[r0,#4]! @ ditto
@ LDRB (literal)
ldrb pc,label @ => PLD
ldrb pc,[PC,#-0] @ => PLD (special case)
ldrb sp,label @ Unpredictable
ldrb sp,[PC,#-0] @ ditto
@ LDRB (register)
ldrb pc,[r0,r1] @ low reg
ldrb r0,[pc,r1] @ ditto
ldrb r0,[r1,pc] @ ditto
ldrb.w pc,[r0,r1,LSL #1] @ => PLD
ldrb.w sp,[r0,r1] @ Unpredictable
ldrb.w r2,[r0,pc,LSL #2] @ BadReg
ldrb.w r2,[r0,sp,LSL #2] @ ditto
@ LDRBT
ldrbt pc, [r0, #4] @ BadReg
ldrbt sp, [r0, #4] @ ditto
@ LDRD (immediate)
ldrd pc, r0, [r1] @ BadReg
ldrd sp, r0, [r1] @ ditto
ldrd r12, [r1] @ ditto
ldrd r14, [r1] @ ditto
ldrd r0, pc, [r1] @ ditto
ldrd r0, sp, [r1] @ ditto
ldrd pc, r0, [r1], #4 @ ditto
ldrd sp, r0, [r1], #4 @ ditto
ldrd r0, pc, [r1], #4 @ ditto
ldrd r0, sp, [r1], #4 @ ditto
ldrd r12, [r1], #4 @ ditto
ldrd r14, [r1], #4 @ ditto
ldrd pc, r0, [r1, #4]! @ ditto
ldrd sp, r0, [r1, #4]! @ ditto
ldrd r0, pc, [r1, #4]! @ ditto
ldrd r0, sp, [r1, #4]! @ ditto
ldrd r12, [r1, #4]! @ ditto
ldrd r14, [r1, #4]! @ ditto
@ LDRD (literal)
ldrd pc, r0, label @ BadReg
ldrd sp, r0, label @ ditto
ldrd r0, pc, label @ ditto
ldrd r0, sp, label @ ditto
ldrd pc, r0, [pc, #-0] @ ditto
ldrd sp, r0, [pc, #-0] @ ditto
ldrd r0, pc, [pc, #-0] @ ditto
ldrd r0, sp, [pc, #-0] @ ditto
@ LDRD (register): ARM only
@ LDREX/B/D/H
ldrex pc, [r0] @ BadReg
ldrex sp, [r0] @ ditto
ldrex r0, [pc] @ Unpredictable
ldrexb pc, [r0] @ BadReg
ldrexb sp, [r0] @ ditto
ldrexb r0, [pc] @ Unpredictable
ldrexd pc, r0, [r1] @ BadReg
ldrexd sp, r0, [r1] @ ditto
ldrexd r0, pc, [r1] @ ditto
ldrexd r0, sp, [r1] @ ditto
ldrexd r0, r1, [pc] @ Unpredictable
ldrexh pc, [r0] @ BadReg
ldrexh sp, [r0] @ ditto
ldrexh r0, [pc] @ Unpredictable
@ LDRH (immediate)
ldrh pc, [r0] @ low reg
ldrh pc, [r0, #4] @ ditto
@ldrh r0, [pc] @ ALLOWED!
@ldrh r0, [pc, #4] @ ditto
ldrh.w pc, [r0] @ => Unallocated memory hints
ldrh.w pc, [r0, #4] @ ditto
ldrh.w sp, [r0] @ Unpredictable
ldrh.w sp, [r0, #4] @ ditto
ldrh pc, [r0, #-3] @ => Unallocated memory hint
@ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT
ldrh pc,[r0],#4 @ BadReg
ldrh sp,[r0],#4 @ ditto
ldrh pc,[r0,#4]! @ ditto
ldrh sp,[r0,#4]! @ ditto
@ LDRH (literal)
ldrh pc, label @ Unallocated memory hint
ldrh pc, [pc, #-0] @ ditto
ldrh sp, label @ Unpredictable
ldrh sp, [pc, #-0] @ ditto
@ LDRH (register)
ldrh pc, [r0, r1] @ low reg
ldrh r0, [pc, r1] @ ditto
ldrh r0, [r1, pc] @ ditto
ldrh.w pc,[r0,r1,LSL #1] @ => Unallocated memory hints
ldrh.w sp,[r0,r1,LSL #1] @ Unpredictable
ldrh.w r2,[r0,pc,LSL #1] @ ditto
ldrh.w r2,[r0,sp,LSL #1] @ ditto
@ LDRHT
ldrht pc, [r0, #4] @ BadReg
ldrht sp, [r0, #4] @ ditto
@ LDRSB (immediate)
ldrsb pc, [r0, #4] @ => PLI
@ldrsb r0, [pc, #4] => LDRSB (literal)
ldrsb sp, [r0, #4] @ Unpredictable
ldrsb pc, [r0, #-4] @ => PLI
ldrsb sp,[r0,#-4] @ BadReg
ldrsb pc,[r0],#4 @ ditto
ldrsb sp,[r0],#4 @ ditto
ldrsb pc,[r0,#4]! @ ditto
ldrsb sp,[r0,#4]! @ ditto
@ LDRSB (literal)
ldrsb pc, label @ => PLI
ldrsb pc, [pc, #-0] @ => PLI
ldrsb sp, label @ Unpredictable
ldrsb sp, [pc, #-0] @ ditto
@ LDRSB (register)
ldrsb pc, [r0, r1] @ low reg
ldrsb r0, [pc, r1] @ ditto
ldrsb r0, [r1, pc] @ ditto
ldrsb.w pc, [r0, r1, LSL #2] @ => PLI
@ldrsb.w r0, [pc, r0, LSL #2] => LDRSB (literal)
ldrsb.w sp, [r0, r1, LSL #2] @ Unpredictable
ldrsb.w r2, [r0, pc, LSL #2] @ ditto
ldrsb.w r2, [r0, sp, LSL #2] @ ditto
@ LDRSBT
@ldrsbt r0, [pc, #4] => LDRSB (literal)
ldrsbt pc, [r0, #4] @ BadReg
ldrsbt sp, [r0, #4] @ ditto
@ LDRSH (immediate)
@ldrsh r0,[pc,#4] => LDRSH (literal)
ldrsh pc,[r0,#4] @ => Unallocated memory hints
ldrsh sp,[r0,#4] @ Unpredictable
ldrsh pc, [r0, #-4] @ => Unallocated memory hints
ldrsh pc,[r0],#4 @ BadReg
ldrsh pc,[r0,#4]! @ ditto
ldrsh sp,[r0,#-4] @ ditto
ldrsh sp,[r0],#4 @ ditto
ldrsh sp,[r0,#4]! @ ditto
@ LDRSH (literal)
ldrsh pc, label @ => Unallocated memory hints
ldrsh sp, label @ Unpredictable
ldrsh sp, [pc,#-0] @ ditto
@ LDRSH (register)
ldrsh pc,[r0,r1] @ low reg
ldrsh r0,[pc,r1] @ ditto
ldrsh r0,[r1,pc] @ ditto
@ldrsh.w r0,[pc,r1,LSL #3] => LDRSH (literal)
ldrsh.w pc,[r0,r1,LSL #3] @ => Unallocated memory hints
ldrsh.w sp,[r0,r1,LSL #3] @ Unpredictable
ldrsh.w r0,[r1,sp,LSL #3] @ BadReg
ldrsh.w r0,[r1,pc,LSL #3] @ ditto
@ LDRSHT
@ldrsht r0,[pc,#4] => LDRSH (literal)
ldrsht pc,[r0,#4] @ BadReg
ldrsht sp,[r0,#4] @ ditto
@ LDRT
@ldrt r0,[pc,#4] => LDR (literal)
ldrt pc,[r0,#4] @ BadReg
ldrt sp,[r0,#4] @ ditto
@ Stores ==============================================================
@ STR (immediate, Thumb)
str pc, [r0, #4] @ Unpredictable
str.w r0, [pc, #4] @ Undefined
str r0, [pc, #-4] @ ditto
str r0, [pc], #4 @ ditto
str r0, [pc, #4]! @ ditto
@ STR (register)
str.w r0,[pc,r1] @ Undefined
str.w r0,[pc,r1,LSL #2] @ ditto
@str.w pc,[r0,r1{,LSL #<imm2>}] @ Unpredictable
@str.w r1,[r0,sp{,LSL #<imm2>}] @ ditto
@str.w r1,[r0,pc{,LSL #<imm2>}] @ ditto
@ STRB (immediate, Thumb)
strb.w r0,[pc,#4] @ Undefined
strb.w pc,[r0,#4] @ Unpredictable
strb.w sp,[r0,#4] @ ditto
strb r0,[pc,#-4] @ Undefined
strb r0,[pc],#4 @ ditto
strb r0,[pc,#4]! @ ditto
strb pc,[r0,#-4] @ Unpredictable
strb pc,[r0],#4 @ ditto
strb pc,[r0,#4]! @ ditto
strb sp,[r0,#-4] @ ditto
strb sp,[r0],#4 @ ditto
strb sp,[r0,#4]! @ ditto
@ STRB (register)
strb.w r0,[pc,r1] @ Undefined
strb.w r0,[pc,r1,LSL #2] @ ditto
strb.w pc,[r0,r1] @ Unpredictable
strb.w pc,[r0,r1,LSL #2] @ ditto
strb.w sp,[r0,r1] @ ditto
strb.w sp,[r0,r1,LSL #2] @ ditto
strb.w r0,[r1,pc] @ ditto
strb.w r0,[r1,pc,LSL #2] @ ditto
strb.w r0,[r1,sp] @ ditto
strb.w r0,[r1,sp,LSL #2] @ ditto
@ STRBT
strbt r0,[pc,#4] @ Undefined
strbt pc,[r0,#4] @ Unpredictable
strbt sp,[r0,#4] @ ditto
@ STRD (immediate)
strd r0,r1,[pc,#4] @ Unpredictable
strd r0,r1,[pc],#4 @ ditto
strd r0,r1,[pc,#4]! @ ditto
strd pc,r0,[r1,#4] @ ditto
strd pc,r0,[r1],#4 @ ditto
strd pc,r0,[r1,#4]! @ ditto
strd sp,r0,[r1,#4] @ ditto
strd sp,r0,[r1],#4 @ ditto
strd sp,r0,[r1,#4]! @ ditto
strd r0,pc,[r1,#4] @ ditto
strd r0,pc,[r1],#4 @ ditto
strd r0,pc,[r1,#4]! @ ditto
strd r0,sp,[r1,#4] @ ditto
strd r0,sp,[r1],#4 @ ditto
strd r0,sp,[r1,#4]! @ ditto
@ STRD (register)
@No thumb.
@ STREX
strex pc,r0,[r1] @ Unpredictable
strex pc,r0,[r1,#4] @ ditto
strex sp,r0,[r1] @ ditto
strex sp,r0,[r1,#4] @ ditto
strex r0,pc,[r1] @ ditto
strex r0,pc,[r1,#4] @ ditto
strex r0,sp,[r1] @ ditto
strex r0,sp,[r1,#4] @ ditto
strex r0,r1,[pc] @ ditto
strex r0,r1,[pc,#4] @ ditto
@ STREXB
strexb pc,r0,[r1] @ Unpredictable
strexb sp,r0,[r1] @ ditto
strexb r0,pc,[r1] @ ditto
strexb r0,sp,[r1] @ ditto
strexb r0,r1,[pc] @ ditto
@ STREXD
strexd pc,r0,r1,[r2] @ Unpredictable
strexd sp,r0,r1,[r2] @ ditto
strexd r0,pc,r1,[r2] @ ditto
strexd r0,sp,r1,[r2] @ ditto
strexd r0,r1,pc,[r2] @ ditto
strexd r0,r1,sp,[r2] @ ditto
strexd r0,r1,r2,[pc] @ ditto
@ STREXH
strexh pc,r0,[r1] @ Unpredictable
strexh sp,r0,[r1] @ ditto
strexh r0,pc,[r1] @ ditto
strexh r0,sp,[r1] @ ditto
strexh r0,r1,[pc] @ ditto
@ STRH (immediate, Thumb)
strh.w r0,[pc] @ Undefined
strh.w r0,[pc,#4] @ ditto
strh r0,[pc,#-4] @ ditto
strh r0,[pc],#4 @ ditto
strh r0,[pc,#4]! @ ditto
@ STRH (register)
strh.w r0,[pc,r1] @ Undefined
strh.w r0,[pc,r1,LSL #2] @ ditto
strh.w pc,[r0,#4] @ Unpredictable
strh.w pc,[r0] @ ditto
strh.w sp,[r0,#4] @ ditto
strh.w sp,[r0] @ ditto
strh pc,[r0,#-4] @ ditto
strh pc,[r0],#4 @ ditto
strh pc,[r0,#4]! @ ditto
strh sp,[r0,#-4] @ ditto
strh sp,[r0],#4 @ ditto
strh sp,[r0,#4]! @ ditto
strh.w pc,[r0,r1] @ ditto
strh.w sp,[r0,r1] @ ditto
strh.w r0,[r1,pc] @ ditto
strh.w r0,[r1,sp] @ ditto
strh.w pc,[r0,r1,LSL #2] @ ditto
strh.w sp,[r0,r1,LSL #2] @ ditto
strh.w r0,[r1,pc,LSL #2] @ ditto
strh.w r0,[r1,sp,LSL #2] @ ditto
@ STRHT
strht r0,[pc,#4] @ Undefined
strht pc,[r0,#4] @ Unpredictable
strht sp,[pc,#4] @ ditto
@ STRT
strt r0,[pc,#4] @ Undefined
strt pc,[r0,#4] @ Unpredictable
strt sp,[r0,#4] @ ditto
@ ============================================================================
.label:
ldr r0, [r1]
|
tactcomplabs/xbgas-binutils-gdb
| 4,202
|
gas/testsuite/gas/arm/msr-imm.s
|
@ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from Immediate
@ Write to application status register
msr APSR_nzcvq,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0xc0000004
@ Write to CPSR flags
msr CPSR,#0xc0000004
msr CPSR_s,#0xc0000004
msr CPSR_f,#0xc0000004
msr CPSR_c,#0xc0000004
msr CPSR_x,#0xc0000004
@ Write to CPSR flag combos
msr CPSR_fs, #0xc0000004
msr CPSR_fx, #0xc0000004
msr CPSR_fc, #0xc0000004
msr CPSR_sf, #0xc0000004
msr CPSR_sx, #0xc0000004
msr CPSR_sc, #0xc0000004
msr CPSR_xf, #0xc0000004
msr CPSR_xs, #0xc0000004
msr CPSR_xc, #0xc0000004
msr CPSR_cf, #0xc0000004
msr CPSR_cs, #0xc0000004
msr CPSR_cx, #0xc0000004
msr CPSR_fsx, #0xc0000004
msr CPSR_fsc, #0xc0000004
msr CPSR_fxs, #0xc0000004
msr CPSR_fxc, #0xc0000004
msr CPSR_fcs, #0xc0000004
msr CPSR_fcx, #0xc0000004
msr CPSR_sfx, #0xc0000004
msr CPSR_sfc, #0xc0000004
msr CPSR_sxf, #0xc0000004
msr CPSR_sxc, #0xc0000004
msr CPSR_scf, #0xc0000004
msr CPSR_scx, #0xc0000004
msr CPSR_xfs, #0xc0000004
msr CPSR_xfc, #0xc0000004
msr CPSR_xsf, #0xc0000004
msr CPSR_xsc, #0xc0000004
msr CPSR_xcf, #0xc0000004
msr CPSR_xcs, #0xc0000004
msr CPSR_cfs, #0xc0000004
msr CPSR_cfx, #0xc0000004
msr CPSR_csf, #0xc0000004
msr CPSR_csx, #0xc0000004
msr CPSR_cxf, #0xc0000004
msr CPSR_cxs, #0xc0000004
msr CPSR_fsxc, #0xc0000004
msr CPSR_fscx, #0xc0000004
msr CPSR_fxsc, #0xc0000004
msr CPSR_fxcs, #0xc0000004
msr CPSR_fcsx, #0xc0000004
msr CPSR_fcxs, #0xc0000004
msr CPSR_sfxc, #0xc0000004
msr CPSR_sfcx, #0xc0000004
msr CPSR_sxfc, #0xc0000004
msr CPSR_sxcf, #0xc0000004
msr CPSR_scfx, #0xc0000004
msr CPSR_scxf, #0xc0000004
msr CPSR_xfsc, #0xc0000004
msr CPSR_xfcs, #0xc0000004
msr CPSR_xsfc, #0xc0000004
msr CPSR_xscf, #0xc0000004
msr CPSR_xcfs, #0xc0000004
msr CPSR_xcsf, #0xc0000004
msr CPSR_cfsx, #0xc0000004
msr CPSR_cfxs, #0xc0000004
msr CPSR_csfx, #0xc0000004
msr CPSR_csxf, #0xc0000004
msr CPSR_cxfs, #0xc0000004
msr CPSR_cxsf, #0xc0000004
@ Write to Saved status register
@ Write to SPSR flags
msr SPSR, #0xc0000004
msr SPSR_s, #0xc0000004
msr SPSR_f, #0xc0000004
msr SPSR_c, #0xc0000004
msr SPSR_x, #0xc0000004
@Write to SPSR flag combos
msr SPSR_fs, #0xc0000004
msr SPSR_fx, #0xc0000004
msr SPSR_fc, #0xc0000004
msr SPSR_sf, #0xc0000004
msr SPSR_sx, #0xc0000004
msr SPSR_sc, #0xc0000004
msr SPSR_xf, #0xc0000004
msr SPSR_xs, #0xc0000004
msr SPSR_xc, #0xc0000004
msr SPSR_cf, #0xc0000004
msr SPSR_cs, #0xc0000004
msr SPSR_cx, #0xc0000004
msr SPSR_fsx, #0xc0000004
msr SPSR_fsc, #0xc0000004
msr SPSR_fxs, #0xc0000004
msr SPSR_fxc, #0xc0000004
msr SPSR_fcs, #0xc0000004
msr SPSR_fcx, #0xc0000004
msr SPSR_sfx, #0xc0000004
msr SPSR_sfc, #0xc0000004
msr SPSR_sxf, #0xc0000004
msr SPSR_sxc, #0xc0000004
msr SPSR_scf, #0xc0000004
msr SPSR_scx, #0xc0000004
msr SPSR_xfs, #0xc0000004
msr SPSR_xfc, #0xc0000004
msr SPSR_xsf, #0xc0000004
msr SPSR_xsc, #0xc0000004
msr SPSR_xcf, #0xc0000004
msr SPSR_xcs, #0xc0000004
msr SPSR_cfs, #0xc0000004
msr SPSR_cfx, #0xc0000004
msr SPSR_csf, #0xc0000004
msr SPSR_csx, #0xc0000004
msr SPSR_cxf, #0xc0000004
msr SPSR_cxs, #0xc0000004
msr SPSR_fsxc, #0xc0000004
msr SPSR_fscx, #0xc0000004
msr SPSR_fxsc, #0xc0000004
msr SPSR_fxcs, #0xc0000004
msr SPSR_fcsx, #0xc0000004
msr SPSR_fcxs, #0xc0000004
msr SPSR_sfxc, #0xc0000004
msr SPSR_sfcx, #0xc0000004
msr SPSR_sxfc, #0xc0000004
msr SPSR_sxcf, #0xc0000004
msr SPSR_scfx, #0xc0000004
msr SPSR_scxf, #0xc0000004
msr SPSR_xfsc, #0xc0000004
msr SPSR_xfcs, #0xc0000004
msr SPSR_xsfc, #0xc0000004
msr SPSR_xscf, #0xc0000004
msr SPSR_xcfs, #0xc0000004
msr SPSR_xcsf, #0xc0000004
msr SPSR_cfsx, #0xc0000004
msr SPSR_cfxs, #0xc0000004
msr SPSR_csfx, #0xc0000004
msr SPSR_csxf, #0xc0000004
msr SPSR_cxfs, #0xc0000004
msr SPSR_cxsf, #0xc0000004
|
tactcomplabs/xbgas-binutils-gdb
| 2,724
|
gas/testsuite/gas/arm/mve-vstrldr-1.s
|
.syntax unified
.thumb
.macro all_vstr op, size, ext
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
.irp op3, q0, q1, q2, q4, q7
\op\()\size \op1, [\op2, \op3]
\op\()\size \op1, [\op2, \op3, uxtw #\ext]
.endr
.endr
.endr
.endm
.irp size, .8, .16, .32
all_vstr vstrb, \size, 0
.endr
.irp size, .16, .32
all_vstr vstrh, \size, 1
.endr
all_vstr vstrw, .32, 2
all_vstr vstrd, .64, 3
vpstete
vstrbt.8 q1, [r0, q0]
vstrbe.8 q1, [r2, q2]
vstrbt.16 q2, [r3, q1]
vstrbe.16 q3, [r4, q6]
vpstete
vstrbt.32 q4, [r8, q2]
vstrbe.32 q7, [sp, q6]
vstrht.16 q0, [r0, q1]
vstrhe.16 q2, [r2, q0]
vpstet
vstrht.32 q1, [r1, q7]
vstrhe.32 q3, [r3, q2]
vstrht.16 q4, [r6, q5, UXTW #1]
vpstete
vstrht.16 q6, [r10, q3, UXTW #1]
vstrhe.32 q5, [r7, q4, UXTW #1]
vstrht.32 q7, [sp, q6, UXTW #1]
vstrwe.32 q0, [r2, q1]
vpstete
vstrwt.32 q1, [r5, q7]
vstrwe.32 q2, [r8, q3, UXTW #2]
vstrwt.32 q5, [sp, q0, UXTW #2]
vstrde.64 q0, [sp, q7]
vpstte
vstrdt.64 q2, [r0, q1]
vstrdt.64 q3, [r3, q5, UXTW #3]
vstrde.64 q7, [r7, q4, UXTW #3]
.macro all_vldr op, size, ext
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
.irp op3, q1, q2, q4, q7
\op\()\size q0, [\op2, \op3]
\op\()\size q0, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q2, q4, q7
\op\()\size q1, [\op2, \op3]
\op\()\size q1, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q1, q4, q7
\op\()\size q2, [\op2, \op3]
\op\()\size q2, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q1, q2, q7
\op\()\size q4, [\op2, \op3]
\op\()\size q4, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q1, q2, q4
\op\()\size q7, [\op2, \op3]
\op\()\size q7, [\op2, \op3, uxtw #\ext]
.endr
.endr
.endm
.irp data, .u8, .s16, .u16, .s32, .u32
all_vldr vldrb, \data, 0
.endr
.irp data, .u16, .s32, .u32
all_vldr vldrh, \data, 1
.endr
all_vldr vldrw, .u32, 2
all_vldr vldrd, .u64, 3
vpstete
vldrbt.u8 q1, [r0, q0]
vldrbe.u8 q1, [r2, q2]
vldrbt.u16 q2, [r3, q1]
vldrbe.s16 q3, [r4, q6]
vpstete
vldrbt.u32 q4, [r8, q2]
vldrbe.s32 q7, [sp, q6]
vldrht.u16 q0, [r0, q1]
vldrhe.u16 q2, [r2, q0]
vpstete
vldrht.u32 q1, [r1, q7]
vldrhe.u32 q3, [r3, q2]
vldrht.u16 q4, [r6, q5, UXTW #1]
vldrhe.u16 q6, [r10, q3, UXTW #1]
vpstete
vldrht.u32 q5, [r7, q4, UXTW #1]
vldrhe.u32 q7, [sp, q6, UXTW #1]
vldrwt.u32 q0, [r2, q1]
vldrwe.u32 q1, [r5, q7]
vpstete
vldrwt.u32 q2, [r8, q3, UXTW #2]
vldrwe.u32 q5, [sp, q0, UXTW #2]
vldrdt.u64 q0, [sp, q7]
vldrde.u64 q2, [r0, q1]
vpste
vldrdt.u64 q3, [r3, q5, UXTW #3]
vldrde.u64 q7, [r7, q4, UXTW #3]
.irp dt, u8, s16, 8
vldrb.\dt q0, [r2, q3]
.endr
.irp dt, 16, u16, s32, f16, p16, u32
vldrh.\dt q0, [r2, q3, UXTW #1]
.endr
.irp dt, 32, u32, f32, p32
vldrw.\dt q0, [r2, q3, UXTW #2]
.endr
.irp dt, 64, u64, f64, p64
vldrd.\dt q0, [r2, q3, UXTW #3]
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 1,135
|
gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
|
@ Tests for LDC group relocations that are meant to fail during parsing.
.macro ldctest insn reg
\insn 0, \reg, [r0, #:pc_g0_nc:(sym)]
\insn 0, \reg, [r0, #:pc_g1_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g0_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g1_nc:(sym)]
\insn 0, \reg, [r0, #:foo:(sym)]
.endm
.macro ldctest2 insn reg
\insn \reg, [r0, #:pc_g0_nc:(sym)]
\insn \reg, [r0, #:pc_g1_nc:(sym)]
\insn \reg, [r0, #:sb_g0_nc:(sym)]
\insn \reg, [r0, #:sb_g1_nc:(sym)]
\insn \reg, [r0, #:foo:(sym)]
.endm
ldctest ldc c0
ldctest ldcl c0
ldctest ldc2 c0
ldctest ldc2l c0
ldctest stc c0
ldctest stcl c0
ldctest stc2 c0
ldctest stc2l c0
.fpu fpa
ldctest2 ldfs f0
ldctest2 stfs f0
ldctest2 ldfd f0
ldctest2 stfd f0
ldctest2 ldfe f0
ldctest2 stfe f0
ldctest2 ldfp f0
ldctest2 stfp f0
.fpu vfp
ldctest2 flds s0
ldctest2 fsts s0
ldctest2 fldd d0
ldctest2 fstd d0
ldctest2 vldr d0 FIXME
ldctest2 vstr d0
.cpu ep9312
ldctest2 cfldrs mvf0
ldctest2 cfstrs mvf0
ldctest2 cfldrd mvd0
ldctest2 cfstrd mvd0
ldctest2 cfldr32 mvfx0
ldctest2 cfstr32 mvfx0
ldctest2 cfldr64 mvdx0
ldctest2 cfstr64 mvdx0
|
tactcomplabs/xbgas-binutils-gdb
| 1,461
|
gas/testsuite/gas/arm/mve-vstld.s
|
.syntax unified
.thumb
.macro all_vstld2 op
.irp part, 0, 1
.irp size, .8, .16, .32
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op\()\part\()\size {q0, q1}, [\op2]
\op\()\part\()\size {q1, q2}, [\op2]
\op\()\part\()\size {q2, q3}, [\op2]
\op\()\part\()\size {q3, q4}, [\op2]
\op\()\part\()\size {q4, q5}, [\op2]
\op\()\part\()\size {q5, q6}, [\op2]
\op\()\part\()\size {q6, q7}, [\op2]
.endr
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op\()\part\()\size {q0, q1}, [\op2]!
\op\()\part\()\size {q1, q2}, [\op2]!
\op\()\part\()\size {q2, q3}, [\op2]!
\op\()\part\()\size {q3, q4}, [\op2]!
\op\()\part\()\size {q4, q5}, [\op2]!
\op\()\part\()\size {q5, q6}, [\op2]!
\op\()\part\()\size {q6, q7}, [\op2]!
.endr
.endr
.endr
.endm
.macro all_vstld4 op
.irp part, 0, 1, 2, 3
.irp size, .8, .16, .32
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op\()\part\()\size {q0, q1, q2, q3}, [\op2]
\op\()\part\()\size {q1, q2, q3, q4}, [\op2]
\op\()\part\()\size {q2, q3, q4, q5}, [\op2]
\op\()\part\()\size {q3, q4, q5, q6}, [\op2]
\op\()\part\()\size {q4, q5, q6, q7}, [\op2]
.endr
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op\()\part\()\size {q0, q1, q2, q3}, [\op2]!
\op\()\part\()\size {q1, q2, q3, q4}, [\op2]!
\op\()\part\()\size {q2, q3, q4, q5}, [\op2]!
\op\()\part\()\size {q3, q4, q5, q6}, [\op2]!
\op\()\part\()\size {q4, q5, q6, q7}, [\op2]!
.endr
.endr
.endr
.endm
all_vstld2 vst2
all_vstld2 vld2
all_vstld4 vst4
all_vstld4 vld4
|
tactcomplabs/xbgas-binutils-gdb
| 1,173
|
gas/testsuite/gas/arm/thumb2_ldmstm_bad.s
|
.syntax unified
.thumb
ldmstm_bad:
@ UNPREDICTABLE Thumb-2 encodings of LDM/LDMIA/LDMFD as specified
@ by section A8.6.53 of the ARMARM.
ldmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE
ldmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE
ldmia r1, {r14, r15} @ Encoding T2, UNPREDICTABLE
ldmia r0!, {r0-r3} @ Encoding T2, UNPREDICTABLE
itt eq
ldmiaeq r0, {r12, r15} @ Encoding T2, UNPREDICTABLE
ldmiaeq r0!, {r0, r1} @ Encoding T2, UNPREDICTABLE
@ UNPREDICTABLE Thumb-2 encodings of STM/STMIA/STMEA as specified
@ by section A8.6.189 of the ARMARM.
stmia.w r0!, {r0-r3} @ Encoding T2, UNPREDICTABLE
stmia r1!, {r0-r3} @ Encoding T1, r1 is UNKNOWN
stmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE
stmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE
stmia r8!, {r0-r11} @ Encoding T2, UNPREDICTABLE
@ The following are technically UNDEFINED, but gas converts them to
@ an equivalent, and well-defined instruction automatically.
@stmia.w r0!, {r1} @ str.w r1, [r0], #4
@stmia r8!, {r9} @ str.w r9, [r8], #4
@stmia r8, {r9} @ str.w r9, [r8]
@ldmia.w r0!, {r1} @ ldr.w r1, [r0], #4
@ldmia r8!, {r9} @ ldr.w r9, [r8], #4
@ldmia r8, {r9} @ ldr.w r9, [r8]
|
tactcomplabs/xbgas-binutils-gdb
| 1,138
|
gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s
|
.macro cond, op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s8 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vhadd.i8 q0, q1, q2
vhadd.s64 q0, q1, q2
vhadd.i8 q0, q1, r2
vhadd.s64 q0, q1, r2
vhsub.i16 q0, q1, q2
vhsub.u64 q0, q1, q2
vhsub.i16 q0, q1, r2
vhsub.u64 q0, q1, r2
vrhadd.i32 q0, q1, q2
vrhadd.s64 q0, q1, q2
vhadd.s8 q0, q1, sp
vhadd.s8 q0, q1, pc
vhsub.s8 q0, q1, sp
vhsub.s8 q0, q1, pc
vrhadd.s8 q0, q1, r2
cond vhadd, r2
cond vhadd, q2
cond vhsub, r2
cond vhsub, q2
cond vrhadd, q2
it eq
vhaddeq.s8 q0, q1, r2
vhaddeq.s8 q0, q1, r2
vpst
vhaddeq.s8 q0, q1, r2
vhaddt.s8 q0, q1, r2
vpst
vhadd.s8 q0, q1, r2
it eq
vhaddeq.s8 q0, q1, q2
vhaddeq.s8 q0, q1, q2
vpst
vhaddeq.s8 q0, q1, q2
vhaddt.s8 q0, q1, q2
vpst
vhadd.s8 q0, q1, q2
it eq
vhsubeq.s8 q0, q1, r2
vhsubeq.s8 q0, q1, r2
vpst
vhsubeq.s8 q0, q1, r2
vhsubt.s8 q0, q1, r2
vpst
vhsub.s8 q0, q1, r2
it eq
vhsubeq.s8 q0, q1, q2
vhsubeq.s8 q0, q1, q2
vpst
vhsubeq.s8 q0, q1, q2
vhsubt.s8 q0, q1, q2
vpst
vhsub.s8 q0, q1, q2
it eq
vrhaddeq.s8 q0, q1, q2
vrhaddeq.s8 q0, q1, q2
vpst
vrhaddeq.s8 q0, q1, q2
vrhaddt.s8 q0, q1, q2
vpst
vrhadd.s8 q0, q1, q2
|
tactcomplabs/xbgas-binutils-gdb
| 1,055
|
gas/testsuite/gas/arm/arch7.s
|
# ARMV7 instructions
.text
.arch armv7r
label1:
pli [r6, r8]
pli [r9, r7]
pli [r0, r1, lsl #2]
pli [r5]
pli [r5, #4095]
pli [r5, #-4095]
dbg #0
dbg #15
dmb
dmb sy
dsb
dsb sy
dsb un
dsb st
dsb unst
isb
isb sy
.thumb
.thumb_func
label2:
pli [r6, r8]
pli [r9, r7]
pli [r0, r1, lsl #2]
pli [r5]
pli [r5, #4095]
pli [r5, #-255]
pli [pc, #4095]
pli [pc, #-4095]
dbg #0
dbg #15
dmb
dmb sy
dsb
dsb sy
dsb un
dsb st
dsb unst
isb
isb sy
sdiv r6, r9, r12
sdiv r9, r6, r3
udiv r9, r6, r3
udiv r6, r9, r12
.arch armv7m
mrs r0, apsr
mrs r0, iapsr
mrs r0, eapsr
mrs r0, psr
mrs r0, ipsr
mrs r0, epsr
mrs r0, iepsr
mrs r0, msp
mrs r0, psp
mrs r0, primask
mrs r0, basepri
mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
msr apsr_nzcvq, r0
msr iapsr_nzcvq, r0
msr eapsr_nzcvq, r0
msr psr_nzcvq, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
msr msp, r0
msr psp, r0
msr primask, r0
msr basepri, r0
msr BASEPRI_MAX, r0
msr faultmask, r0
msr control, r0
mrs r0, xpsr
msr xpsr_nzcvq, r0
svc 0
|
tactcomplabs/xbgas-binutils-gdb
| 1,206
|
gas/testsuite/gas/arm/archv6t2.s
|
.text
x:
bfi r0, r0, #0, #1
bfine r0, r0, #0, #1
bfi r9, r0, #0, #1
bfi r0, r9, #0, #1
bfi r0, r0, #0, #18
bfi r0, r0, #17, #1
bfi r0, #0, #0, #1
bfc r0, #0, #1
bfcne r0, #0, #1
bfc r9, #0, #1
bfc r0, #0, #18
bfc r0, #17, #1
sbfx r0, r0, #0, #1
sbfxne r0, r0, #0, #1
ubfx r0, r0, #0, #1
sbfx r9, r0, #0, #1
sbfx r0, r9, #0, #1
sbfx r0, r0, #17, #1
sbfx r0, r0, #0, #18
rbit r0, r0
rbitne r0, r0
rbit r9, r0
rbit r0, r9
mls r0, r0, r0, r0
mlsne r0, r0, r0, r0
mls r9, r0, r0, r0
mls r0, r9, r0, r0
mls r0, r0, r9, r0
mls r0, r0, r0, r9
movw r0, #0
movt r0, #0
movwne r0, #0
movw r9, #0
movw r0, #0x0999
movw r0, #0x9000
@ for these, we must avoid write-back warnings
ldrht r0, [r9]
ldrsht r0, [r9]
ldrsbt r0, [r9]
strht r0, [r9]
ldrneht r0, [r9]
ldrht r9, [r0], r9
ldrht r9, [r0], -r9
ldrht r9, [r0], #0x99
ldrht r9, [r0], #-0x99
ldrneht r9, [r0], r9
ldrneht r9, [r0], -r9
ldrneht r9, [r0], #0x99
ldrneht r9, [r0], #-0x99
strht r0, [r1], -r2
strneht r0, [r1], -r2
strht r0, [r1], r2
strneht r0, [r1], r2
strht r0, [r1], #2
strht r0, [r1], #-2
strneht r0, [r1], #2
strneht r0, [r1], #-2
@ mov accept A2 encoding as well.
mov r9, #0x0999
|
tactcomplabs/xbgas-binutils-gdb
| 1,265
|
gas/testsuite/gas/arm/neon-cond-bad-inc.s
|
# Check for illegal conditional Neon instructions in ARM mode. The instructions
# which overlap with VFP are the tricky cases, so test those.
.include "itblock.s"
.syntax unified
.arch armv7-a
.fpu neon
.text
func:
itblock 4 eq
vmoveq q0,q1
vmoveq d0,d1
vmoveq.i32 q0,#0
vmoveq.i32 d0,#0
@ Following four *can* be conditional.
itblock 4 eq
vmoveq.32 d0[1], r2
vmoveq d0,r1,r2
vmoveq.32 r2,d1[0]
vmoveq r0,r1,d2
.macro dyadic_eq op eq="eq" f32=".f32"
itblock 2 eq
\op\eq\f32 d0,d1,d2
\op\eq\f32 q0,q1,q2
.endm
dyadic_eq vmul
dyadic_eq vmla
dyadic_eq vmls
dyadic_eq vadd
dyadic_eq vsub
itblock 2 eq
vcvteq.f16.f32 d1, q1
vcvteq.f32.f16 q1, d1
.macro monadic_eq op eq="eq" f32=".f32"
itblock 2 eq
\op\eq\f32 d0,d1
\op\eq\f32 q0,q1
.endm
monadic_eq vabs
monadic_eq vneg
.macro cvt to from dot="."
itblock 2 eq
vcvteq\dot\to\dot\from d0,d1
vcvteq\dot\to\dot\from q0,q1
.endm
cvt s32 f32
cvt u32 f32
cvt f32 s32
cvt f32 u32
itblock 4 eq
vdupeq.32 d0,r1
vdupeq.32 q0,r1
vdupeq.32 d0,d1[0]
vdupeq.32 q0,d1[1]
|
tactcomplabs/xbgas-binutils-gdb
| 1,317
|
gas/testsuite/gas/arm/ldr-t.s
|
.syntax unified
.arch armv7-a
.thumb
.global foo
foo:
.align 4
@ldr-immediate
@!wback && (n == t)
ldr r1, [r1, #5]
@wback && !(n == t)
ldr r1, [r2, #5]!
@!(rt == r15) && rn == r15
@ && bits<0..1> (immediate) != 00
ldr r1, [r15, #5]
@rt == r15 && !(rn == r15)
@ && bits<0..1> (immediate) != 00
ldr r15, [r1, #5]
@rt == r15 && rn == r15
@ && bits<0..1> (immediate) == 00
ldr r15, [r15, #4]
@inITBlock && !(rt == 15) && !lastInITBlock
ittt ge
ldrge r1, [r15, #4]
nopge
nopge
@inITBlock && rt == 15 && lastInITBlock
it ge
ldrge r15, [r15, #4]
@ldr-literal
@inITBlock && !(rt == 15) && !lastInITBlock
ittt ge
ldrge r1, .-0xab4
nopge
nopge
@inITBlock && (rt == 15) && lastInITBlock
it ge
ldrge r15, .-0xab4
@!(rt == r15) && bits<0..1> (immediate) != 00
ldr r1, .-0xab7
@rt == r15 && bits<0..1> (immediate) == 00
ldr r15, .-0xab4
@ldr-register
@inITBlock && !(rt == 15) && !lastInITBlock
ittt ge
ldrge r1, [r2, r1]
nopge
nopge
@inITBlock && (rt == 15) && lastInITBlock
it ge
ldrge r15, [r2, r1]
@!(rm == 13 || rm == 15)
ldr r1, [r2, r3]
@str-immediate
@!(rt == 15 || rn == 15)
str r1, [r2, #10]
@!wback && (n == t)
str r1, [r1, #10]
@wback && !(n == t)
str r1, [r2, #10]!
@str-register
@!(rt == 15 || rm == 13 || rm == 15)
str r1, [r2, r3]
|
tactcomplabs/xbgas-binutils-gdb
| 1,129
|
gas/testsuite/gas/arm/neon-psyn.s
|
.arm
.syntax unified
fish .qn q2
cow .dn d2[1]
chips .dn d2
banana .dn d3
vmul fish.s16, fish.s16, fish.s16
vmul banana, banana, cow.s32
vmul d3.s32, d3.s32, d2.s32
vadd d2.s32, d3.s32
vmull fish.u32, chips.u16, chips.u16[1]
X .dn D0.S16
Y .dn D1.S16
Z .dn Y[2]
VMLA X, Y, Z
VMLA X, Y, Y[2]
foo .dn d5
bar .dn d7
foos .dn foo[1]
vadd foo, foo, foo.u32
vmov foo, bar
vmov d2.s16[1], r1
vmov d5.s32[1], r1
vmov foo, r2, r3
vmov r4, foos.s8
vmov r5, r6, foo
baa .qn q5
moo .dn d6
sheep .dn d7
chicken .dn d8
vabal baa, moo.u16, sheep.u16
vcvt q1.s32, q2.f32
vcvt d4.f, d5.u32, #5
vdup bar, foos.32
vtbl d1, {baa}, d4.8
el1 .dn d4.16[1]
el2 .dn d6.16[1]
el3 .dn d8.16[1]
el4 .dn d10.16[1]
vld2 {moo.32[1], sheep.32[1]}, [r10]
vld4 {el1, el2, el3, el4}, [r10]
vld3 {moo.16[], sheep.16[], chicken.16[]}, [r10]
vmov r0,d0.s16[0]
el5 .qn q3.16
el6 .qn q4.16
vld4 {el5,el6}, [r10]
vld3 {d2.s16[1], d4.s16[1], d6.s16[1]}, [r10]
chicken8 .dn chicken.8
vtbl d7.8, {d4, d5}, chicken8
vbsl q1.8, q2.16, q3.8
vcge d2.32, d3.f, d4.f
vcge d2.16, d3.s16, #0
dupme .dn d2.s16
vdup dupme, r3
|
tactcomplabs/xbgas-binutils-gdb
| 1,284
|
gas/testsuite/gas/arm/r15-bad.s
|
.text
.align 0
label:
mul r15, r1, r2
mul r1, r15, r2
mla r15, r2, r3, r4
mla r1, r15, r3, r4
mla r1, r2, r15, r4
mla r1, r2, r3, r15
smlabb r15, r2, r3, r4
smlabb r1, r15, r3, r4
smlabb r1, r2, r15, r4
smlabb r1, r2, r3, r15
smlalbb r15, r2, r3, r4
smlalbb r1, r15, r3, r4
smlalbb r1, r2, r15, r4
smlalbb r1, r2, r3, r15
smulbb r15, r2, r3
smulbb r1, r15, r3
smulbb r1, r2, r15
qadd r15, r2, r3
qadd r1, r15, r3
qadd r1, r2, r15
qadd16 r15, r2, r3
qadd16 r1, r15, r3
qadd16 r1, r2, r15
clz r15, r2
clz r1, r15
umaal r15, r2, r3, r4
umaal r1, r15, r3, r4
umaal r1, r2, r15, r4
umaal r1, r2, r3, r15
strex r15, r2, [r3]
strex r1, r15, [r3]
strex r1, r2, [r15]
ssat r15, #1, r2
ssat r1, #1, r15
ssat16 r15, #1, r2
ssat16 r1, #1, r15
smmul r15, r2, r3
smmul r1, r15, r3
smmul r1, r2, r15
smlald r15, r2, r3, r4
smlald r1, r15, r3, r4
smlald r1, r2, r15, r4
smlald r1, r2, r3, r15
smlad r15, r2, r3, r4
smlad r1, r15, r3, r4
smlad r1, r2, r15, r4
smlad r1, r2, r3, r15
sxth r15, r2
sxth r1, r15
sxtah r15, r2, r3
sxtah r1, r15, r3
sxtah r1, r2, r15
rfeda r15
rev r15, r2
rev r1, r15
pkhtb r15, r2, r3
pkhtb r1, r15, r3
pkhtb r1, r2, r15
ldrex r15, [r2]
ldrex r1, [r15]
swp r15, r2, [r3]
swp r1, r15, [r3]
swp r1, r2, [r15]
|
tactcomplabs/xbgas-binutils-gdb
| 1,314
|
gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s
|
@ Tests that are meant to fail during encoding of LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.endm
.macro ldrtest load store sym offset
ldrtest2 \load \sym \offset
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the
@ magnitude of the addend. So these should all (just) fail.
ldrtest ldrd strd f "+ 256"
ldrtest ldrh strh f "+ 256"
ldrtest2 ldrsh f "+ 256"
ldrtest2 ldrsb f "+ 256"
ldrtest ldrd strd f "- 256"
ldrtest ldrh strh f "- 256"
ldrtest2 ldrsh f "- 256"
ldrtest2 ldrsb f "- 256"
@ The same as the above, but for a local symbol.
ldrtest ldrd strd localsym "+ 256"
ldrtest ldrh strh localsym "+ 256"
ldrtest2 ldrsh localsym "+ 256"
ldrtest2 ldrsb localsym "+ 256"
ldrtest ldrd strd localsym "- 256"
ldrtest ldrh strh localsym "- 256"
ldrtest2 ldrsh localsym "- 256"
ldrtest2 ldrsb localsym "- 256"
localsym:
mov r0, #0
|
tactcomplabs/xbgas-binutils-gdb
| 1,392
|
gas/testsuite/gas/arm/bundle.s
|
.syntax unified
.bundle_align_mode 4
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,16) by 2 or 4.
.macro offset_insn insn_name, offset, size
.p2align 4
\insn_name\()_offset_\offset\():
.rept \offset / \size
bkpt
.endr
\insn_name
.endm
.macro test_offsets_arm insn_name
.arm
offset_insn \insn_name, 0, 4
offset_insn \insn_name, 4, 4
offset_insn \insn_name, 8, 4
offset_insn \insn_name, 12, 4
.endm
.macro test_offsets_thumb insn_name
.thumb
offset_insn \insn_name, 0, 2
offset_insn \insn_name, 2, 2
offset_insn \insn_name, 4, 2
offset_insn \insn_name, 6, 2
offset_insn \insn_name, 8, 2
offset_insn \insn_name, 10, 2
offset_insn \insn_name, 12, 2
offset_insn \insn_name, 14, 2
.endm
.macro test_arm
add r0, r1
.endm
.macro test_thumb_2
adds r0, r1
.endm
.macro test_thumb_4
adds r8, r9
.endm
test_offsets_arm test_arm
test_offsets_thumb test_thumb_2
test_offsets_thumb test_thumb_4
# There are many relaxation cases for Thumb instructions.
# But we use as representative the simple branch cases.
.macro test_thumb_b_2
b 0f
bkpt 1
0: bkpt 2
.endm
.macro test_thumb_b_4
b far_target
.endm
test_offsets_thumb test_thumb_b_2
test_offsets_thumb test_thumb_b_4
# This is to set up a branch target surely too far for a short branch.
pad_for_far_target:
.rept 1025
bkpt 1
.endr
far_target:
bkpt 2
.p2align 4
bkpt
|
tactcomplabs/xbgas-binutils-gdb
| 2,802
|
gas/testsuite/gas/arm/fpa-dyadic.s
|
.text
.globl F
F:
adfs f0, f0, f0
adfsp f0, f0, f0
adfsm f0, f0, f0
adfsz f0, f0, f0
adfd f0, f0, f0
adfdp f0, f0, f0
adfdm f0, f0, f0
adfdz f0, f0, f0
adfe f0, f0, f0
adfep f0, f0, f0
adfem f0, f0, f0
adfez f0, f0, f0
sufs f0, f0, f0
sufsp f0, f0, f0
sufsm f0, f0, f0
sufsz f0, f0, f0
sufd f0, f0, f0
sufdp f0, f0, f0
sufdm f0, f0, f0
sufdz f0, f0, f0
sufe f0, f0, f0
sufep f0, f0, f0
sufem f0, f0, f0
sufez f0, f0, f0
rsfs f0, f0, f0
rsfsp f0, f0, f0
rsfsm f0, f0, f0
rsfsz f0, f0, f0
rsfd f0, f0, f0
rsfdp f0, f0, f0
rsfdm f0, f0, f0
rsfdz f0, f0, f0
rsfe f0, f0, f0
rsfep f0, f0, f0
rsfem f0, f0, f0
rsfez f0, f0, f0
mufs f0, f0, f0
mufsp f0, f0, f0
mufsm f0, f0, f0
mufsz f0, f0, f0
mufd f0, f0, f0
mufdp f0, f0, f0
mufdm f0, f0, f0
mufdz f0, f0, f0
mufe f0, f0, f0
mufep f0, f0, f0
mufem f0, f0, f0
mufez f0, f0, f0
dvfs f0, f0, f0
dvfsp f0, f0, f0
dvfsm f0, f0, f0
dvfsz f0, f0, f0
dvfd f0, f0, f0
dvfdp f0, f0, f0
dvfdm f0, f0, f0
dvfdz f0, f0, f0
dvfe f0, f0, f0
dvfep f0, f0, f0
dvfem f0, f0, f0
dvfez f0, f0, f0
rdfs f0, f0, f0
rdfsp f0, f0, f0
rdfsm f0, f0, f0
rdfsz f0, f0, f0
rdfd f0, f0, f0
rdfdp f0, f0, f0
rdfdm f0, f0, f0
rdfdz f0, f0, f0
rdfe f0, f0, f0
rdfep f0, f0, f0
rdfem f0, f0, f0
rdfez f0, f0, f0
pows f0, f0, f0
powsp f0, f0, f0
powsm f0, f0, f0
powsz f0, f0, f0
powd f0, f0, f0
powdp f0, f0, f0
powdm f0, f0, f0
powdz f0, f0, f0
powe f0, f0, f0
powep f0, f0, f0
powem f0, f0, f0
powez f0, f0, f0
rpws f0, f0, f0
rpwsp f0, f0, f0
rpwsm f0, f0, f0
rpwsz f0, f0, f0
rpwd f0, f0, f0
rpwdp f0, f0, f0
rpwdm f0, f0, f0
rpwdz f0, f0, f0
rpwe f0, f0, f0
rpwep f0, f0, f0
rpwem f0, f0, f0
rpwez f0, f0, f0
rmfs f0, f0, f0
rmfsp f0, f0, f0
rmfsm f0, f0, f0
rmfsz f0, f0, f0
rmfd f0, f0, f0
rmfdp f0, f0, f0
rmfdm f0, f0, f0
rmfdz f0, f0, f0
rmfe f0, f0, f0
rmfep f0, f0, f0
rmfem f0, f0, f0
rmfez f0, f0, f0
fmls f0, f0, f0
fmlsp f0, f0, f0
fmlsm f0, f0, f0
fmlsz f0, f0, f0
fmld f0, f0, f0
fmldp f0, f0, f0
fmldm f0, f0, f0
fmldz f0, f0, f0
fmle f0, f0, f0
fmlep f0, f0, f0
fmlem f0, f0, f0
fmlez f0, f0, f0
fdvs f0, f0, f0
fdvsp f0, f0, f0
fdvsm f0, f0, f0
fdvsz f0, f0, f0
fdvd f0, f0, f0
fdvdp f0, f0, f0
fdvdm f0, f0, f0
fdvdz f0, f0, f0
fdve f0, f0, f0
fdvep f0, f0, f0
fdvem f0, f0, f0
fdvez f0, f0, f0
frds f0, f0, f0
frdsp f0, f0, f0
frdsm f0, f0, f0
frdsz f0, f0, f0
frdd f0, f0, f0
frddp f0, f0, f0
frddm f0, f0, f0
frddz f0, f0, f0
frde f0, f0, f0
frdep f0, f0, f0
frdem f0, f0, f0
frdez f0, f0, f0
pols f0, f0, f0
polsp f0, f0, f0
polsm f0, f0, f0
polsz f0, f0, f0
pold f0, f0, f0
poldp f0, f0, f0
poldm f0, f0, f0
poldz f0, f0, f0
pole f0, f0, f0
polep f0, f0, f0
polem f0, f0, f0
polez f0, f0, f0
|
tactcomplabs/xbgas-binutils-gdb
| 6,271
|
gas/testsuite/gas/arm/vfp1xD.s
|
@ VFP Instructions for v1xD variants (Single precision only)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fmstat
fcmpes s0, s0
fcmpezs s0
fcmps s0, s0
fcmpzs s0
@ Monadic data operations
fabss s0, s0
fcpys s0, s0
fnegs s0, s0
fsqrts s0, s0
@ Dyadic data operations
fadds s0, s0, s0
fdivs s0, s0, s0
fmacs s0, s0, s0
fmscs s0, s0, s0
fmuls s0, s0, s0
fnmacs s0, s0, s0
fnmscs s0, s0, s0
fnmuls s0, s0, s0
fsubs s0, s0, s0
@ Load/store operations
flds s0, [r0]
fsts s0, [r0]
@ Load/store multiple operations
fldmias r0, {s0}
fldmfds r0, {s0}
fldmias r0!, {s0}
fldmfds r0!, {s0}
fldmdbs r0!, {s0}
fldmeas r0!, {s0}
fldmiax r0, {d0}
fldmfdx r0, {d0}
fldmiax r0!, {d0}
fldmfdx r0!, {d0}
fldmdbx r0!, {d0}
fldmeax r0!, {d0}
fstmias r0, {s0}
fstmeas r0, {s0}
fstmias r0!, {s0}
fstmeas r0!, {s0}
fstmdbs r0!, {s0}
fstmfds r0!, {s0}
fstmiax r0, {d0}
fstmeax r0, {d0}
fstmiax r0!, {d0}
fstmeax r0!, {d0}
fstmdbx r0!, {d0}
fstmfdx r0!, {d0}
@ Conversion operations
fsitos s0, s0
fuitos s0, s0
ftosis s0, s0
ftosizs s0, s0
ftouis s0, s0
ftouizs s0, s0
@ ARM from VFP operations
fmrs r0, s0
fmrx r0, fpsid
fmrx r0, fpscr
fmrx r0, fpexc
@ VFP From ARM operations
fmsr s0, r0
fmxr fpsid, r0
fmxr fpscr, r0
fmxr fpexc, r0
@ Now we test that the register fields are updated correctly for
@ each class of instruction.
@ Single register operations (compare-zero):
fcmpzs s1
fcmpzs s2
fcmpzs s31
@ Two register comparison operations:
fcmps s0, s1
fcmps s0, s2
fcmps s0, s31
fcmps s1, s0
fcmps s2, s0
fcmps s31, s0
fcmps s21, s12
@ Two register data operations (monadic)
fnegs s0, s1
fnegs s0, s2
fnegs s0, s31
fnegs s1, s0
fnegs s2, s0
fnegs s31, s0
fnegs s12, s21
@ Three register data operations (dyadic)
fadds s0, s0, s1
fadds s0, s0, s2
fadds s0, s0, s31
fadds s0, s1, s0
fadds s0, s2, s0
fadds s0, s31, s0
fadds s1, s0, s0
fadds s2, s0, s0
fadds s31, s0, s0
fadds s12, s21, s5
@ Conversion operations
fsitos s0, s1
fsitos s0, s2
fsitos s0, s31
fsitos s1, s0
fsitos s2, s0
fsitos s31, s0
ftosis s0, s1
ftosis s0, s2
ftosis s0, s31
ftosis s1, s0
ftosis s2, s0
ftosis s31, s0
@ Move to VFP from ARM
fmsr s0, r1
fmsr s0, r7
fmsr s0, r14
fmsr s1, r0
fmsr s2, r0
fmsr s31, r0
fmsr s21, r7
fmxr fpsid, r1
fmxr fpsid, r14
@ Move to ARM from VFP
fmrs r0, s1
fmrs r0, s2
fmrs r0, s31
fmrs r1, s0
fmrs r7, s0
fmrs r14, s0
fmrs r9, s11
fmrx r1, fpsid
fmrx r14, fpsid
@ Load/store operations
flds s0, [r1]
flds s0, [r14]
flds s0, [r0, #0]
flds s0, [r0, #1020]
flds s0, [r0, #-1020]
flds s1, [r0]
flds s2, [r0]
flds s31, [r0]
fsts s21, [r12, #804]
@ Load/store multiple operations
fldmias r0, {s1}
fldmias r0, {s2}
fldmias r0, {s31}
fldmias r0, {s0-s1}
fldmias r0, {s0-s2}
fldmias r0, {s0-s31}
fldmias r0, {s1-s31}
fldmias r0, {s2-s31}
fldmias r0, {s30-s31}
fldmias r1, {s0}
fldmias r14, {s0}
fstmiax r0, {d1}
fstmiax r0, {d2}
fstmiax r0, {d15}
fstmiax r0, {d0-d1}
fstmiax r0, {d0-d2}
fstmiax r0, {d0-d15}
fstmiax r0, {d1-d15}
fstmiax r0, {d2-d15}
fstmiax r0, {d14-d15}
fstmiax r1, {d0}
fstmiax r14, {d0}
@ Check that we assemble all the register names correctly
fcmpzs s0
fcmpzs s1
fcmpzs s2
fcmpzs s3
fcmpzs s4
fcmpzs s5
fcmpzs s6
fcmpzs s7
fcmpzs s8
fcmpzs s9
fcmpzs s10
fcmpzs s11
fcmpzs s12
fcmpzs s13
fcmpzs s14
fcmpzs s15
fcmpzs s16
fcmpzs s17
fcmpzs s18
fcmpzs s19
fcmpzs s20
fcmpzs s21
fcmpzs s22
fcmpzs s23
fcmpzs s24
fcmpzs s25
fcmpzs s26
fcmpzs s27
fcmpzs s28
fcmpzs s29
fcmpzs s30
fcmpzs s31
@ Now we check the placement of the conditional execution substring.
@ On VFP this is always at the end of the instruction.
@ We use different register numbers here to check for correct
@ disassembly
@ Comparison operations
fmstateq
fcmpeseq s3, s7
fcmpezseq s5
fcmpseq s1, s2
fcmpzseq s1
@ Monadic data operations
fabsseq s1, s3
fcpyseq s31, s19
fnegseq s20, s8
fsqrtseq s5, s7
@ Dyadic data operations
faddseq s6, s5, s4
fdivseq s3, s2, s1
fmacseq s31, s30, s29
fmscseq s28, s27, s26
fmulseq s25, s24, s23
fnmacseq s22, s21, s20
fnmscseq s19, s18, s17
fnmulseq s16, s15, s14
fsubseq s13, s12, s11
@ Load/store operations
fldseq s10, [r8]
fstseq s9, [r7]
@ Load/store multiple operations
fldmiaseq r1, {s8}
fldmfdseq r2, {s7}
fldmiaseq r3!, {s6}
fldmfdseq r4!, {s5}
fldmdbseq r5!, {s4}
fldmeaseq r6!, {s3}
fldmiaxeq r7, {d1}
fldmfdxeq r8, {d2}
fldmiaxeq r9!, {d3}
fldmfdxeq r10!, {d4}
fldmdbxeq r11!, {d5}
fldmeaxeq r12!, {d6}
fstmiaseq r13, {s2}
fstmeaseq r14, {s1}
fstmiaseq r1!, {s31}
fstmeaseq r2!, {s30}
fstmdbseq r3!, {s29}
fstmfdseq r4!, {s28}
fstmiaxeq r5, {d7}
fstmeaxeq r6, {d8}
fstmiaxeq r7!, {d9}
fstmeaxeq r8!, {d10}
fstmdbxeq r9!, {d11}
fstmfdxeq r10!, {d12}
@ Conversion operations
fsitoseq s27, s6
ftosiseq s25, s5
ftosizseq s23, s4
ftouiseq s21, s3
ftouizseq s19, s2
fuitoseq s17, s1
@ ARM from VFP operations
fmrseq r11, s3
fmrxeq r9, fpsid
@ VFP From ARM operations
fmsreq s3, r9
fmxreq fpsid, r8
@ Implementation specific system registers
fmrx r0, fpinst
fmrx r0, fpinst2
fmrx r0, mvfr0
fmrx r0, mvfr1
fmrx r0, c12
fmxr fpinst, r0
fmxr fpinst2, r0
fmxr mvfr0, r0
fmxr mvfr1, r0
fmxr c12, r0
@ ARM VMSR/VMRS instructions
vmrs r0, FPSCR
vmrs r1, FPSCR
vmrs r2, FPSCR
vmrs r3, FPSCR
vmrs r4, FPSCR
vmrs r5, FPSCR
vmrs r6, FPSCR
vmrs r7, FPSCR
vmrs r8, FPSCR
vmrs r9, FPSCR
vmrs r10, FPSCR
vmrs r11, FPSCR
vmrs r12, FPSCR
vmrs r14, FPSCR
vmrs APSR_nzcv, FPSCR
vmsr FPSCR, r0
vmsr FPSCR, r1
vmsr FPSCR, r2
vmsr FPSCR, r3
vmsr FPSCR, r4
vmsr FPSCR, r5
vmsr FPSCR, r6
vmsr FPSCR, r7
vmsr FPSCR, r8
vmsr FPSCR, r9
vmsr FPSCR, r10
vmsr FPSCR, r11
vmsr FPSCR, r12
vmsr FPSCR, r14
@ Priviledged extensions to VMSR/VMRS instructions
vmsr FPSID, r1
vmsr FPEXC, r2
vmsr FPINST, r3
vmsr FPINST2, r4
vmsr C15, r5
vmrs r3, FPSID
vmrs r4, MVFR1
vmrs r5, MVFR0
vmrs r6, FPEXC
vmrs r7, FPINST
vmrs r8, FPINST2
vmrs r9, C15
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 3,870
|
gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s
|
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s32 r0, r1, q2, q3
.endr
.endm
.syntax unified
.thumb
vrmlaldavh.s16 r0, r1, q2, q3
vrmlaldavh.i32 r0, r1, q2, q3
vrmlaldavha.s16 r0, r1, q2, q3
vrmlaldavha.i32 r0, r1, q2, q3
vrmlalvh.s16 r0, r1, q2, q3
vrmlalvh.i32 r0, r1, q2, q3
vrmlalvha.s16 r0, r1, q2, q3
vrmlalvha.i32 r0, r1, q2, q3
vrmlaldavhx.u32 r0, r1, q2, q3
vrmlaldavhax.u32 r0, r1, q2, q3
vrmlaldavhx.i32 r0, r1, q2, q3
vrmlaldavhax.i32 r0, r1, q2, q3
vrmlsldavh.s16 r0, r1, q2, q3
vrmlsldavh.u32 r0, r1, q2, q3
vrmlsldavha.s16 r0, r1, q2, q3
vrmlsldavha.u32 r0, r1, q2, q3
vrmlsldavhx.s16 r0, r1, q2, q3
vrmlsldavhx.u32 r0, r1, q2, q3
vrmlsldavhax.s16 r0, r1, q2, q3
vrmlsldavhax.u32 r0, r1, q2, q3
vrmlaldavh.s32 r1, r1, q2, q3
vrmlaldavh.s32 r0, r0, q2, q3
vrmlaldavh.s32 r0, sp, q2, q3
vrmlaldavh.s32 r0, pc, q2, q3
vrmlaldavha.s32 r1, r1, q2, q3
vrmlaldavha.s32 r0, r0, q2, q3
vrmlaldavha.s32 r0, sp, q2, q3
vrmlaldavha.s32 r0, pc, q2, q3
vrmlaldavhx.s32 r1, r1, q2, q3
vrmlaldavhx.s32 r0, r0, q2, q3
vrmlaldavhx.s32 r0, sp, q2, q3
vrmlaldavhx.s32 r0, pc, q2, q3
vrmlaldavhax.s32 r1, r1, q2, q3
vrmlaldavhax.s32 r0, r0, q2, q3
vrmlaldavhax.s32 r0, sp, q2, q3
vrmlaldavhax.s32 r0, pc, q2, q3
vrmlalvh.s32 r1, r1, q2, q3
vrmlalvh.s32 r0, r0, q2, q3
vrmlalvh.s32 r0, sp, q2, q3
vrmlalvh.s32 r0, pc, q2, q3
vrmlalvha.s32 r1, r1, q2, q3
vrmlalvha.s32 r0, r0, q2, q3
vrmlalvha.s32 r0, sp, q2, q3
vrmlalvha.s32 r0, pc, q2, q3
vrmlsldavh.s32 r1, r1, q2, q3
vrmlsldavh.s32 r0, r0, q2, q3
vrmlsldavh.s32 r0, sp, q2, q3
vrmlsldavh.s32 r0, pc, q2, q3
vrmlsldavha.s32 r1, r1, q2, q3
vrmlsldavha.s32 r0, r0, q2, q3
vrmlsldavha.s32 r0, sp, q2, q3
vrmlsldavha.s32 r0, pc, q2, q3
vrmlsldavhx.s32 r1, r1, q2, q3
vrmlsldavhx.s32 r0, r0, q2, q3
vrmlsldavhx.s32 r0, sp, q2, q3
vrmlsldavhx.s32 r0, pc, q2, q3
vrmlsldavhax.s32 r1, r1, q2, q3
vrmlsldavhax.s32 r0, r0, q2, q3
vrmlsldavhax.s32 r0, sp, q2, q3
vrmlsldavhax.s32 r0, pc, q2, q3
cond vrmlaldavh
cond vrmlaldavha
cond vrmlaldavhx
cond vrmlaldavhax
cond vrmlalvh
cond vrmlalvha
cond vrmlsldavh
cond vrmlsldavha
cond vrmlsldavhx
cond vrmlsldavhax
it eq
vrmlaldavheq.s32 r0, r1, q2, q3
vrmlaldavheq.s32 r0, r1, q2, q3
vpst
vrmlaldavheq.s32 r0, r1, q2, q3
vrmlaldavht.s32 r0, r1, q2, q3
vpst
vrmlaldavh.s32 r0, r1, q2, q3
it eq
vrmlaldavhaeq.s32 r0, r1, q2, q3
vrmlaldavhaeq.s32 r0, r1, q2, q3
vpst
vrmlaldavhaeq.s32 r0, r1, q2, q3
vrmlaldavhat.s32 r0, r1, q2, q3
vpst
vrmlaldavha.s32 r0, r1, q2, q3
it eq
vrmlaldavhxeq.s32 r0, r1, q2, q3
vrmlaldavhxeq.s32 r0, r1, q2, q3
vpst
vrmlaldavhxeq.s32 r0, r1, q2, q3
vrmlaldavhxt.s32 r0, r1, q2, q3
vpst
vrmlaldavhx.s32 r0, r1, q2, q3
it eq
vrmlaldavhaxeq.s32 r0, r1, q2, q3
vrmlaldavhaxeq.s32 r0, r1, q2, q3
vpst
vrmlaldavhaxeq.s32 r0, r1, q2, q3
vrmlaldavhaxt.s32 r0, r1, q2, q3
vpst
vrmlaldavhax.s32 r0, r1, q2, q3
it eq
vrmlalvheq.s32 r0, r1, q2, q3
vrmlalvheq.s32 r0, r1, q2, q3
vpst
vrmlalvheq.s32 r0, r1, q2, q3
vrmlalvht.s32 r0, r1, q2, q3
vpst
vrmlalvh.s32 r0, r1, q2, q3
it eq
vrmlalvhaeq.s32 r0, r1, q2, q3
vrmlalvhaeq.s32 r0, r1, q2, q3
vpst
vrmlalvhaeq.s32 r0, r1, q2, q3
vrmlalvhat.s32 r0, r1, q2, q3
vpst
vrmlalvha.s32 r0, r1, q2, q3
it eq
vrmlsldavheq.s32 r0, r1, q2, q3
vrmlsldavheq.s32 r0, r1, q2, q3
vpst
vrmlsldavheq.s32 r0, r1, q2, q3
vrmlsldavht.s32 r0, r1, q2, q3
vpst
vrmlsldavh.s32 r0, r1, q2, q3
it eq
vrmlsldavhaeq.s32 r0, r1, q2, q3
vrmlsldavhaeq.s32 r0, r1, q2, q3
vpst
vrmlsldavhaeq.s32 r0, r1, q2, q3
vrmlsldavhat.s32 r0, r1, q2, q3
vpst
vrmlsldavha.s32 r0, r1, q2, q3
it eq
vrmlsldavhxeq.s32 r0, r1, q2, q3
vrmlsldavhxeq.s32 r0, r1, q2, q3
vpst
vrmlsldavhxeq.s32 r0, r1, q2, q3
vrmlsldavhxt.s32 r0, r1, q2, q3
vpst
vrmlsldavhx.s32 r0, r1, q2, q3
it eq
vrmlsldavhaxeq.s32 r0, r1, q2, q3
vrmlsldavhaxeq.s32 r0, r1, q2, q3
vpst
vrmlsldavhaxeq.s32 r0, r1, q2, q3
vrmlsldavhaxt.s32 r0, r1, q2, q3
vpst
vrmlsldavhax.s32 r0, r1, q2, q3
|
tactcomplabs/xbgas-binutils-gdb
| 1,520
|
gas/testsuite/gas/arm/arm-it-auto.s
|
.syntax unified
.arch armv7
.thumb
main:
@These branches are to see the labels in the generated file
bl .L888
bl .L111
bl .L777
@No IT block here:
bne .L4
@The following groups should be an IT block each.
@it ne
addne.n pc, r0
@it ne
tbbne [r0, r1]
@it eq
tbheq [r1, r0]
@The following group should be left as is:
itet eq
.L111: moveq r0, #2
movne r0, #3
moveq r0, #4
@Same, reverted condition:
itet ne
movne r0, #2
moveq r0, #3
movne r0, #4
@Two groups shall be generated, due to the label:
movne r0, #1
@ second group, the label should be at the IT insn
.L777: moveq r0, #2
ldrne pc, [r1]
@it ne
blne .L4
@it lt
bllt .L9
@itett ne
.L888: movne r0, #45
moveq r0, #5
movne r0, #6
addne.n pc, r0
@iteet eq
moveq r0, #7
movne r0, #8
movne r0, #3
moveq r0, #4
@itete eq
moveq r0, #5
movne r0, #6
moveq r0, #7
movne r0, #8
@ite eq - this group finishes due to the mov.n pc, rn
moveq r0, #5
movne r0, #6
mov.n pc, r0
@itete eq
moveq r0, #7
movne r0, #8
moveq r0, #5
movne r0, #6
@this shall not generate an IT block
add.n pc, r0
@ite eq - testing condition change (eq -> gt)
moveq r0, #7
movne r0, #8
@ite gt (group shall finish due to another condition change)
movgt r0, #9
movle r0, #10
@it eq
moveq r0, #11
@it le
movle r0, #12
@it ne
movne r0, #13
bl f
.L4:
pop {r4, pc}
.L9:
bl f
@Only the movlt shall be enclosed in the IT block
movlt r0, #0
muls r0, r0, r1
@Same here:
movlt r0, #0
muls r0, r0, r1
|
tactcomplabs/xbgas-binutils-gdb
| 1,561
|
gas/testsuite/gas/arm/archv8m-cmse-msr.s
|
T:
## MRS ##
# MSP
mrs r0, MSP
mrs r0, MSP_NS
mrs r0, msp
mrs r0, msp_ns
# PSP
mrs r1, PSP
mrs r1, PSP_NS
mrs r1, psp
mrs r1, psp_ns
# MSPLIM
mrs r2, MSPLIM
mrs r2, MSPLIM_NS
mrs r2, msplim
mrs r2, msplim_ns
# PSPLIM
mrs r3, PSPLIM
mrs r3, PSPLIM_NS
mrs r3, psplim
mrs r3, psplim_ns
# PRIMASK
mrs r4, PRIMASK
mrs r4, PRIMASK_NS
mrs r4, primask
mrs r4, primask_ns
# BASEPRI
mrs r5, BASEPRI
mrs r5, BASEPRI_NS
mrs r5, basepri
mrs r5, basepri_ns
# FAULTMASK
mrs r6, FAULTMASK
mrs r6, FAULTMASK_NS
mrs r6, faultmask
mrs r6, faultmask_ns
# CONTROL
mrs r7, CONTROL
mrs r7, CONTROL_NS
mrs r7, control
mrs r7, control_ns
# SP_NS
mrs r8, SP_NS
mrs r8, sp_ns
## MSR ##
# MSP
msr MSP, r0
msr MSP_NS, r0
msr msp, r0
msr msp_ns, r0
# PSP
msr PSP, r1
msr PSP_NS, r1
msr psp, r1
msr psp_ns, r1
# MSPLIM
msr MSPLIM, r2
msr MSPLIM_NS, r2
msr msplim, r2
msr msplim_ns, r2
# PSPLIM
msr PSPLIM, r3
msr PSPLIM_NS, r3
msr psplim, r3
msr psplim_ns, r3
# PRIMASK
msr PRIMASK, r4
msr PRIMASK_NS, r4
msr primask, r4
msr primask_ns, r4
# BASEPRI
msr BASEPRI, r5
msr BASEPRI_NS, r5
msr basepri, r5
msr basepri_ns, r5
# FAULTMASK
msr FAULTMASK, r6
msr FAULTMASK_NS, r6
msr faultmask, r6
msr faultmask_ns, r6
# CONTROL
msr CONTROL, r7
msr CONTROL_NS, r7
msr control, r7
msr control_ns, r7
# SP_NS
msr SP_NS, r8
msr sp_ns, r8
|
tactcomplabs/xbgas-binutils-gdb
| 1,822
|
gas/testsuite/gas/arm/thumb2_ldmstm.s
|
.syntax unified
.thumb
ldmstm:
ldmia sp!, {r0}
ldmia sp!, {r8}
ldmia r1, {r9}
ldmia r2!, {ip}
ldmdb sp!, {r2}
ldmdb sp!, {r8}
ldmdb r6, {r4}
ldmdb r6, {r8}
ldmdb r2!, {r4}
ldmdb r2!, {ip}
stmia sp!, {r3}
stmia sp!, {r9}
stmia r3, {ip}
stmia r4!, {ip}
stmdb sp!, {r3}
stmdb sp!, {r9}
stmdb r7, {r5}
stmdb r6, {ip}
stmdb r6!, {fp}
stmdb r5!, {r8}
@ Valid Thumb-2 encodings of LDM/LDMIA/LDMFD as specified by section
@ A8.6.53 of the ARM ARM
ldmia r0!, {r1-r3} @ Encoding T1
ldmia r0, {r0-r3} @ Encoding T1
ldmia r0!, {r1} @ Encoding T1
ldmia r0, {r8-r11} @ Encoding T2
ldmia.w r0!, {r1-r3} @ Encoding T2
ldmia r0!, {r8-r11} @ Encoding T2
ldmia r0!, {r12, r14} @ Encoding T2
ldmia r0!, {r12, pc} @ Encoding T2
it eq
ldmiaeq r0!, {r12, pc} @ Encoding T2
@ Valid Thumb-2 encodings of STM/STMIA/STMEA as specified by section
@ A8.6.189 of the ARMARM.
stmia r0!, {r0-r3} @ Encoding T1, Allowed as r0 is lowest reg
stmia r0!, {r4-r7} @ Encoding T1
stmia.w r0!, {r4-r7} @ Encoding T2
stmia r0!, {r8-r11} @ Encoding T2
stmia r0, {r0-r3} @ Encoding T2
stmia r0, {r8-r11} @ Encoding T2
@ The following are technically UNPREDICTABLE if we assemble them
@ as written, but gas translates (stm|ldm) rn(!), {rd} into an
@ equivalent, and well-defined, (ldr, str) rd, [rn], (#4).
ldmia.w r0!, {r1} @ ldr.w r1, [r0], #4
ldmia.w r0, {r1} @ ldr.w r1, [r0]
ldmia r8!, {r9} @ ldr.w r9, [r8], #4
ldmia r8, {r9} @ ldr.w r9, [r8]
stmia.w r0!, {r1} @ str.w r1, [r0], #4
stmia r0, {r1} @ T1 str r1, [r0]
ldmia r1, {r2} @ T1 ldr r2, [r1]
ldmia r0, {r7} @ T1 ldr r7, [r0]
stmia sp, {r7} @ T1 str r7, [sp]
stmia sp, {r0} @ T1 str r0, [sp]
ldmia sp, {r7} @ T1 ldr r7, [sp]
ldmia sp, {r0} @ T1 ldr r0, [sp]
stmia r8!, {r9} @ str.w r9, [r8], #4
stmia r8, {r9} @ str.w r9, [r8]
|
tactcomplabs/xbgas-binutils-gdb
| 13,220
|
gas/testsuite/gas/arm/thumb32.s
|
.text
.thumb
.syntax unified
encode_thumb32_immediate:
orr r0, r1, #0x00000000
orr r0, r1, #0x000000a5
orr r0, r1, #0x00a500a5
orr r0, r1, #0xa500a500
orr r0, r1, #0xa5a5a5a5
orr r0, r1, #0xa5 << 31
orr r0, r1, #0xa5 << 30
orr r0, r1, #0xa5 << 29
orr r0, r1, #0xa5 << 28
orr r0, r1, #0xa5 << 27
orr r0, r1, #0xa5 << 26
orr r0, r1, #0xa5 << 25
orr r0, r1, #0xa5 << 24
orr r0, r1, #0xa5 << 23
orr r0, r1, #0xa5 << 22
orr r0, r1, #0xa5 << 21
orr r0, r1, #0xa5 << 20
orr r0, r1, #0xa5 << 19
orr r0, r1, #0xa5 << 18
orr r0, r1, #0xa5 << 17
orr r0, r1, #0xa5 << 16
orr r0, r1, #0xa5 << 15
orr r0, r1, #0xa5 << 14
orr r0, r1, #0xa5 << 13
orr r0, r1, #0xa5 << 12
orr r0, r1, #0xa5 << 11
orr r0, r1, #0xa5 << 10
orr r0, r1, #0xa5 << 9
orr r0, r1, #0xa5 << 8
orr r0, r1, #0xa5 << 7
orr r0, r1, #0xa5 << 6
orr r0, r1, #0xa5 << 5
orr r0, r1, #0xa5 << 4
orr r0, r1, #0xa5 << 3
orr r0, r1, #0xa5 << 2
orr r0, r1, #0xa5 << 1
add_sub:
@ Should be format 1, Some have equivalent format 2 encodings
adds r0, r0, #0
adds r5, r0, #0
adds r0, r5, #0
adds r0, r2, #5
adds r0, #129 @ format 2
adds r0, r0, #129
adds r5, #126
adds r0, r0, r0 @ format 3
adds r5, r0, r0
adds r0, r5, r0
adds r0, r0, r5
adds r1, r2, r3
add r8, r0 @ format 4
add r0, r8
add r0, r8, r0
add r0, r0, r8
add r8, r0, r0 @ ... not this one
add r1, r0
add r0, r1
add r0, pc, #0 @ format 5
add r5, pc, #0
add r0, pc, #516
add r0, sp, #0 @ format 6
add r5, sp, #0
add r0, sp, #516
add sp, #0 @ format 7
add sp, sp, #0
add sp, #260
add.w r0, r0, #0 @ T32 format 1
adds.w r0, r0, #0
add.w r9, r0, #0
add.w r0, r9, #0
add.w r0, r0, #129
adds r5, r3, #0x10000
add r0, sp, #1
add r9, sp, #0
add.w sp, sp, #4
add.w r0, r0, r0 @ T32 format 2
adds.w r0, r0, r0
add.w r9, r0, r0
add.w r0, r9, r0
add.w r0, r0, r9
add.w r8, r9, r10
add.w r8, r9, r10, lsl #17
add.w r8, r8, r10, lsr #32
add.w r8, r8, r10, lsr #17
add.w r8, r9, r10, asr #32
add.w r8, r9, r10, asr #17
add.w r8, r9, r10, rrx
add.w r8, r9, r10, ror #17
subs r0, r0, #0 @ format 1
subs r5, r0, #0
subs r0, r5, #0
subs r0, r2, #5
subs r0, r0, #129
subs r5, #8
subs r0, r0, r0 @ format 3
subs r5, r0, r0
subs r0, r5, r0
subs r0, r0, r5
sub sp, #260 @ format 4
sub sp, sp, #260
subs r8, r0 @ T32 format 2
subs r0, r8
subs r0, #260 @ T32 format 1
subs.w r1, r2, #4
subs r5, r3, #0x10000
sub r1, sp, #4
sub r9, sp, #0
sub.w sp, sp, #4
arit3:
.macro arit3 op ops opw opsw
\ops r0, r0
\ops r5, r0
\ops r0, r5
\ops r0, r0, r5
\ops r0, r5, r0
\op r0, r5, r0
\op r0, r1, r2
\op r9, r0, r0
\op r0, r9, r0
\op r0, r0, r9
\opsw r0, r0, r0
\opw r0, r1, r2, asr #17
\opw r0, r1, #129
.endm
arit3 adc adcs adc.w adcs.w
arit3 and ands and.w ands.w
arit3 bic bics bic.w bics.w
arit3 eor eors eor.w eors.w
arit3 orr orrs orr.w orrs.w
arit3 rsb rsbs rsb.w rsbs.w
arit3 sbc sbcs sbc.w sbcs.w
arit3 orn orns orn orns
.purgem arit3
bfc_bfi_bfx:
bfc r0, #0, #1
bfc r9, #0, #1
bfi r9, #0, #0, #1
bfc r0, #21, #1
bfc r0, #0, #18
bfi r0, r0, #0, #1
bfi r9, r0, #0, #1
bfi r0, r9, #0, #1
bfi r0, r0, #21, #1
bfi r0, r0, #0, #18
sbfx r0, r0, #0, #1
ubfx r9, r0, #0, #1
sbfx r0, r9, #0, #1
ubfx r0, r0, #21, #1
sbfx r0, r0, #0, #18
.globl branches
branches:
.macro bra op
\op 1b
\op 1f
.endm
1:
bra beq.n
bra bne.n
bra bcs.n
bra bhs.n
bra bcc.n
bra bul.n
bra blo.n
bra bmi.n
bra bpl.n
bra bvs.n
bra bvc.n
bra bhi.n
bra bls.n
bra bvc.n
bra bhi.n
bra bls.n
bra bge.n
bra blt.n
bra bgt.n
bra ble.n
bra bal.n
bra b.n
@ bl, blx have no short form.
.balign 4
1:
bra beq.w
bra bne.w
bra bcs.w
bra bhs.w
bra bcc.w
bra bul.w
bra blo.w
bra bmi.w
bra bpl.w
bra bvs.w
bra bvc.w
bra bhi.w
bra bls.w
bra bvc.w
bra bhi.w
bra bls.w
bra bge.w
bra blt.w
bra bgt.w
bra ble.w
bra b.w
bra bl
bra blx
.balign 4
1:
bx r9
blx r0
blx r9
bxj r0
bxj r9
.purgem bra
clz:
clz r0, r0
clz r9, r0
clz r0, r9
cps:
cpsie f
cpsid i
cpsie a
cpsid.w f
cpsie.w i
cpsid.w a
cpsie i, #0
cpsid i, #17
cps #0
cps #17
cpy:
cpy r0, r0
cpy r9, r0
cpy r0, r9
cpy.w r0, r0
cpy.w r9, r0
cpy.w r0, r9
czb:
cbnz r0, 2f
cbz r5, 1f
nop_hint:
nop
1: yield
2: wfe
wfi
sev
nop.w
yield.w
wfe.w
wfi.w
sev.w
nop {9}
nop {129}
it:
.macro nop1 cond ncond a
.ifc \a,t
nop\cond
.else
nop\ncond
.endif
.endm
.macro it0 cond m=
it\m \cond
nop\cond
.endm
.macro it1 cond ncond a m=
it0 \cond \a\m
nop1 \cond \ncond \a
.endm
.macro it2 cond ncond a b m=
it1 \cond \ncond \a \b\m
nop1 \cond \ncond \b
.endm
.macro it3 cond ncond a b c
it2 \cond \ncond \a \b \c
nop1 \cond \ncond \c
.endm
it0 eq
it0 ne
it0 cs
it0 hs
it0 cc
it0 ul
it0 lo
it0 mi
it0 pl
it0 vs
it0 vc
it0 hi
it0 ge
it0 lt
it0 gt
it0 le
it0 al
it1 eq ne t
it1 eq ne e
it2 eq ne t t
it2 eq ne e t
it2 eq ne t e
it2 eq ne e e
it3 eq ne t t t
it3 eq ne e t t
it3 eq ne t e t
it3 eq ne t t e
it3 eq ne t e e
it3 eq ne e t e
it3 eq ne e e t
it3 eq ne e e e
it1 ne eq t
it1 ne eq e
it2 ne eq t t
it2 ne eq e t
it2 ne eq t e
it2 ne eq e e
it3 ne eq t t t
it3 ne eq e t t
it3 ne eq t e t
it3 ne eq t t e
it3 ne eq t e e
it3 ne eq e t e
it3 ne eq e e t
it3 ne eq e e e
ldst:
1:
pld [r5]
pld [r5, #0x330]
pld [r5, #-0x30]
pld [r5], #0x30
pld [r5], #-0x30
pld [r5, #0x30]!
pld [r5, #-0x30]!
pld [r5, r4]
pld [r9, ip]
pld 1f
pld 1b
1:
nop
here:
ldrd r2, r3, [r5]
ldrd r2, [r5, #0x30]
ldrd r2, [r5, #-0x30]
ldrd r4, r5, here
strd r2, r3, [r5]
strd r2, [r5, #0x30]
strd r2, [r5, #-0x30]
ldrbt r1, [r5]
ldrbt r1, [r5, #0x30]
ldrsbt r1, [r5]
ldrsbt r1, [r5, #0x30]
ldrht r1, [r5]
ldrht r1, [r5, #0x30]
ldrsht r1, [r5]
ldrsht r1, [r5, #0x30]
ldrt r1, [r5]
ldrt r1, [r5, #0x30]
ldxstx:
ldrexb r1, [r4]
ldrexh r1, [r4]
ldrex r1, [r4]
ldrexd r1, r2, [r4]
strexb r1, r2, [r4]
strexh r1, r2, [r4]
strex r1, r2, [r4]
strexd r1, r2, r3, [r4]
strexd r1, r3, r3, [r4]
ldrex r1, [r4,#516]
strex r1, r2, [r4,#516]
ldmstm:
ldmia r0!, {r1,r2,r3}
ldmia r2, {r0,r1,r2}
ldmia.w r2, {r0,r1,r2}
ldmia r9, {r0,r1,r2}
ldmia r0, {r7,r8,r10}
ldmia r0!, {r7,r8,r10}
stmia r0!, {r1,r2,r3}
stmia r2!, {r0,r1,r3}
stmia.w r2!, {r0,r1,r3}
stmia r9, {r0,r1,r2}
stmia r0, {r7,r8,r10}
stmia r0!, {r7,r8,r10}
ldmdb r0, {r7,r8,r10}
stmdb r0, {r7,r8,r10}
mlas:
mla r0, r0, r0, r0
mls r0, r0, r0, r0
mla r9, r0, r0, r0
mla r0, r9, r0, r0
mla r0, r0, r9, r0
mla r0, r0, r0, r9
tst_teq_cmp_cmn_mov_mvn:
.macro mt op ops opw opsw
\ops r0, r0
\op r0, r0
\ops r5, r0
\op r0, r5
\op r0, r5, asr #17
\opw r0, r0
\ops r9, r0
\opsw r0, r9
\opw r0, #129
\opw r5, #129
.endm
mt tst tsts tst.w tsts.w
mt teq teqs teq.w teqs.w
mt cmp cmps cmp.w cmps.w
mt cmn cmns cmn.w cmns.w
mt mov movs mov.w movs.w
mt mvn mvns mvn.w mvns.w
.purgem mt
mov16:
movw r0, #0
movt r0, #0
movw r9, #0
movw r0, #0x9000
movw r0, #0x0800
movw r0, #0x0500
movw r0, #0x0081
movw r0, #0xffff
mrs_msr:
mrs r0, CPSR
mrs r0, SPSR
mrs r9, CPSR_all
mrs r9, SPSR_all
msr CPSR_c, r0
msr SPSR_c, r0
msr CPSR_c, r9
msr CPSR_x, r0
msr CPSR_s, r0
msr CPSR_f, r0
mul:
mul r0, r0, r0
mul r0, r9, r0
mul r0, r0, r9
mul r0, r0
mul r9, r0
muls r5, r0
muls r5, r0, r5
muls r0, r5
mull:
smull r0, r1, r0, r0
umull r0, r1, r0, r0
smlal r0, r1, r0, r0
umlal r0, r1, r0, r0
smull r9, r0, r0, r0
smull r0, r9, r0, r0
smull r0, r1, r9, r0
smull r0, r1, r0, r9
neg:
negs r0, r0
negs r0, r5
negs r5, r0
negs.w r0, r0
negs.w r5, r0
negs.w r0, r5
neg r0, r9
neg r9, r0
negs r0, r9
negs r9, r0
pkh:
pkhbt r0, r0, r0
pkhbt r9, r0, r0
pkhbt r0, r9, r0
pkhbt r0, r0, r9
pkhbt r0, r0, r0, lsl #0x14
pkhbt r0, r0, r0, lsl #3
pkhtb r1, r2, r3
pkhtb r1, r2, r3, asr #0x11
push_pop:
push {r0}
pop {r0}
push {r1,lr}
pop {r1,pc}
push {r8,r9,r10,r11,r12}
pop {r8,r9,r10,r11,r12}
qadd:
qadd r1, r2, r3
qadd16 r1, r2, r3
qadd8 r1, r2, r3
qasx r1, r2, r3
qaddsubx r1, r2, r3
qdadd r1, r2, r3
qdsub r1, r2, r3
qsub r1, r2, r3
qsub16 r1, r2, r3
qsub8 r1, r2, r3
qsax r1, r2, r3
qsubaddx r1, r2, r3
sadd16 r1, r2, r3
sadd8 r1, r2, r3
sasx r1, r2, r3
saddsubx r1, r2, r3
ssub16 r1, r2, r3
ssub8 r1, r2, r3
ssax r1, r2, r3
ssubaddx r1, r2, r3
shadd16 r1, r2, r3
shadd8 r1, r2, r3
shasx r1, r2, r3
shaddsubx r1, r2, r3
shsub16 r1, r2, r3
shsub8 r1, r2, r3
shsax r1, r2, r3
shsubaddx r1, r2, r3
uadd16 r1, r2, r3
uadd8 r1, r2, r3
uasx r1, r2, r3
uaddsubx r1, r2, r3
usub16 r1, r2, r3
usub8 r1, r2, r3
usax r1, r2, r3
usubaddx r1, r2, r3
uhadd16 r1, r2, r3
uhadd8 r1, r2, r3
uhasx r1, r2, r3
uhaddsubx r1, r2, r3
uhsub16 r1, r2, r3
uhsub8 r1, r2, r3
uhsax r1, r2, r3
uhsubaddx r1, r2, r3
uqadd16 r1, r2, r3
uqadd8 r1, r2, r3
uqasx r1, r2, r3
uqaddsubx r1, r2, r3
uqsub16 r1, r2, r3
uqsub8 r1, r2, r3
uqsax r1, r2, r3
uqsubaddx r1, r2, r3
sel r1, r2, r3
rbit_rev:
.macro rx op opw
\op r0, r0
\opw r0, r0
\op r0, r5
\op r5, r0
\op r0, r9
\op r9, r0
.endm
rx rev rev.w
rx rev16 rev16.w
rx revsh revsh.w
rx rbit rbit.w
.purgem rx
shift:
.macro sh op ops opw opsw
\ops r0, #17 @ 16-bit format 1
\ops r0, r0, #14
\ops r5, r0, #17
\ops r0, r5, #14
\ops r0, r0 @ 16-bit format 2
\ops r0, r5
\ops r0, r0, r5
\op r9, #17 @ 32-bit format 1
\op r9, r9, #14
\ops r0, r9, #17
\op r9, r0, #14
\opw r0, r0, r0 @ 32-bit format 2
\op r9, r9
\ops r9, r0
\op r0, r9
\op r0, r5
\ops r0, r1, r2
.endm
sh lsl lsls lsl.w lsls.w
sh lsr lsrs lsr.w lsrs.w
sh asr asrs asr.w asrs.w
sh ror rors ror.w rors.w
.purgem sh
rrx:
rrx r1, r2
rrxs r3, r4
.arch armv7-a
.arch_extension sec
smc:
smc #0
smc #0xd
smla:
smlabb r0, r0, r0, r0
smlabb r9, r0, r0, r0
smlabb r0, r9, r0, r0
smlabb r0, r0, r9, r0
smlabb r0, r0, r0, r9
smlatb r0, r0, r0, r0
smlabt r0, r0, r0, r0
smlatt r0, r0, r0, r0
smlawb r0, r0, r0, r0
smlawt r0, r0, r0, r0
smlad r0, r0, r0, r0
smladx r0, r0, r0, r0
smlsd r0, r0, r0, r0
smlsdx r0, r0, r0, r0
smmla r0, r0, r0, r0
smmlar r0, r0, r0, r0
smmls r0, r0, r0, r0
smmlsr r0, r0, r0, r0
usada8 r0, r0, r0, r0
smlal:
smlalbb r0, r0, r0, r0
smlalbb r9, r0, r0, r0
smlalbb r0, r9, r0, r0
smlalbb r0, r0, r9, r0
smlalbb r0, r0, r0, r9
smlaltb r0, r0, r0, r0
smlalbt r0, r0, r0, r0
smlaltt r0, r0, r0, r0
smlald r0, r0, r0, r0
smlaldx r0, r0, r0, r0
smlsld r0, r0, r0, r0
smlsldx r0, r0, r0, r0
umaal r0, r0, r0, r0
smul:
smulbb r0, r0, r0
smulbb r9, r0, r0
smulbb r0, r9, r0
smulbb r0, r0, r9
smultb r0, r0, r0
smulbt r0, r0, r0
smultt r0, r0, r0
smulwb r0, r0, r0
smulwt r0, r0, r0
smmul r0, r0, r0
smmulr r0, r0, r0
smuad r0, r0, r0
smuadx r0, r0, r0
smusd r0, r0, r0
smusdx r0, r0, r0
usad8 r0, r0, r0
sat:
ssat r0, #1, r0
ssat r0, #1, r0, lsl #0
ssat r0, #1, r0, asr #0
ssat r9, #1, r0
ssat r0, #18, r0
ssat r0, #1, r9
ssat r0, #1, r0, lsl #0x1c
ssat r0, #1, r0, asr #0x03
ssat16 r0, #1, r0
ssat16 r9, #1, r0
ssat16 r0, #10, r0
ssat16 r0, #1, r9
usat r0, #0, r0
usat r0, #0, r0, lsl #0
usat r0, #0, r0, asr #0
usat r9, #0, r0
usat r0, #17, r0
usat r0, #0, r9
usat r0, #0, r0, lsl #0x1c
usat r0, #0, r0, asr #0x03
usat16 r0, #0, r0
usat16 r9, #0, r0
usat16 r0, #9, r0
usat16 r0, #0, r9
xt:
sxtb r0, r0
sxtb r0, r0, ror #0
sxtb r5, r0
sxtb r0, r5
sxtb.w r1, r2
sxtb r1, r2, ror #8
sxtb r1, r2, ror #16
sxtb r1, r2, ror #24
sxtb16 r1, r2
sxtb16 r8, r9
sxth r1, r2
sxth r8, r9
uxtb r1, r2
uxtb r8, r9
uxtb16 r1, r2
uxtb16 r8, r9
uxth r1, r2
uxth r8, r9
xta:
sxtab r0, r0, r0
sxtab r0, r0, r0, ror #0
sxtab r9, r0, r0, ror #8
sxtab r0, r9, r0, ror #16
sxtab r0, r0, r9, ror #24
sxtab16 r1, r2, r3
sxtah r1, r2, r3
uxtab r1, r2, r3
uxtab16 r1, r2, r3
uxtah r1, r2, r3
.macro ldpcimm op
\op r1, [pc, #0x2aa]
\op r1, [pc, #0x155]
\op r1, [pc, #-0x2aa]
\op r1, [pc, #-0x155]
.endm
ldpcimm ldrb
ldpcimm ldrsb
ldpcimm ldrh
ldpcimm ldrsh
ldpcimm ldr
addw r9, r0, #0
addw r6, pc, #0xfff
subw r6, r9, #0xa85
subw r6, r9, #0x57a
tbb [pc, r6]
tbb [r0, r9]
tbh [pc, r7, lsl #1]
tbh [r0, r8, lsl #1]
push {r8}
pop {r8}
ldmdb r0!, {r7,r8,r10}
stmdb r0!, {r7,r8,r10}
ldm r0!, {r1, r2}
stm r0!, {r1, r2}
ldm r0, {r8, r9}
stm r0, {r8, r9}
itttt eq
ldmeq r0!, {r1, r2}
stmeq r0!, {r1, r2}
ldmeq r0, {r8, r9}
stmeq r0, {r8, r9}
nop
srs:
srsia sp, #16
srsdb sp, #16
srsia sp!, #21
srsia sp!, #10
movs pc, lr
subs pc, lr, #0
subs pc, lr, #4
subs pc, lr, #255
ldrd r2, r4, [r9, #48]!
ldrd r2, r4, [r9, #-48]!
strd r2, r4, [r9, #48]!
strd r2, r4, [r9, #-48]!
ldrd r2, r4, [r9], #48
ldrd r2, r4, [r9], #-48
strd r2, r4, [r9], #48
strd r2, r4, [r9], #-48
.macro ldaddr op
ldr\op r1, [r5, #0x301]
ldr\op r1, [r5, #0x30]!
ldr\op r1, [r5, #-0x30]!
ldr\op r1, [r5], #0x30
ldr\op r1, [r5], #-0x30
ldr\op r1, [r5, r9]
.endm
ldaddr
ldaddr b
ldaddr sb
ldaddr h
ldaddr sh
.macro movshift op s="s"
movs r1, r4, \op #2
movs r3, r9, \op #2
movs r1, r2, \op r3
movs r1, r1, \op r3
movs r1, r1, \op r9
mov r1, r2, \op r3
mov r1, r1, \op r3
.endm
movshift lsl
movshift lsr
movshift asr
movshift ror
nop
|
tactcomplabs/xbgas-binutils-gdb
| 1,091
|
gas/testsuite/gas/arm/armv1.s
|
.global entry
.text
entry:
and r0, r0, r0
ands r0, r0, r0
eor r0, r0, r0
eors r0, r0, r0
sub r0, r0, r0
subs r0, r0, r0
rsb r0, r0, r0
rsbs r0, r0, r0
add r0, r0, r0
adds r0, r0, r0
adc r0, r0, r0
adcs r0, r0, r0
sbc r0, r0, r0
sbcs r0, r0, r0
rsc r0, r0, r0
rscs r0, r0, r0
orr r0, r0, r0
orrs r0, r0, r0
bic r0, r0, r0
bics r0, r0, r0
tst r0, r0
tsts r0, r0
tstp r0, r0
teq r0, r0
teqs r0, r0
teqp r0, r0
cmp r0, r0
cmps r0, r0
cmpp r0, r0
cmn r0, r0
cmns r0, r0
cmnp r0, r0
mov r0, r0
movs r0, r0
mvn r0, r0
mvns r0, r0
swi #0
ldr r0, [r0, #-0]
ldrb r0, [r0, #-0]
ldrt r0, [r1]
ldrbt r0, [r1]
str r0, [r0, #-0]
strb r0, [r0, #-0]
strt r0, [r1]
strbt r0, [r1]
stmia r0, {r0}
stmib r0, {r0}
stmda r0, {r0}
stmdb r0, {r0}
stmfd r0, {r0}
stmfa r0, {r0}
stmea r0, {r0}
stmed r0, {r0}
ldmia r0, {r0}
ldmib r0, {r0}
ldmda r0, {r0}
ldmdb r0, {r0}
ldmfd r0, {r0}
ldmfa r0, {r0}
ldmea r0, {r0}
ldmed r0, {r0}
# Add three nop instructions to ensure that the
# output is 32-byte aligned as required for arm-aout.
nop
nop
nop
|
tactcomplabs/xbgas-binutils-gdb
| 18,592
|
gas/testsuite/gas/arm/thumb2_bad_reg.s
|
.syntax unified
.text
.align 2
.thumb
.thumb_func
test:
@ ADC (immediate)
adc r13, r0, #1
adc r15, r0, #1
adc r0, r13, #1
adc r0, r15, #1
@ ADC (register)
adc.w r13, r0, r1
adc.w r15, r0, r1
adc.w r0, r13, r1
adc.w r0, r15, r1
adc.w r0, r1, r13
adc.w r0, r1, r15
@ ADD (immediate)
add.w r13, r0, #1
add.w r15, r0, #1
add.w r0, r13, #1 @ ADD (SP plus immediate)
add.w r0, r15, #1 @ Converted implicitly to ADDW
addw r13, r0, #1
addw r15, r0, #1
addw r0, r13, #1 @ ADD (SP plus immediate)
addw r0, r15, #1 @ ADR
@ ADD (register)
add.w r13, r0, r1
add.w r15, r0, r1
adds.w r15, r0, r1
add.w r0, r13, r1 @ ADD (SP plus register)
add.w r0, r15, r1
add.w r0, r1, r13
add.w r0, r1, r15
@ ADD (SP plus immediate)
add.w r0, r13, #1 @ OK
add.w r15, r13, #1
adds.w r15, r13, #1
addw r15, r13, #1
@ ADD (SP plus register)
add.w r15, r13, r0
add.w r0, r13, r13
add.w r0, r13, r15
@ ADR
adr.w r13, test
adr.w r15, test
@ AND (immediate)
and r13, r0, #1
and r15, r0, #1
and r0, r13, #1
and r0, r15, #1
@ AND (register)
and.w r13, r0, r1
and.w r15, r0, r1
and.w r0, r13, r1
and.w r0, r15, r1
and.w r0, r1, r13
and.w r0, r1, r15
@ ASR (immediate)
asr r13, r0, #1
asr r15, r0, #1
asr r0, r13, #1
asr r0, r15, #1
@ ASR (register)
asr.w r13, r0, r1
asr.w r15, r0, r1
asr.w r0, r13, r1
asr.w r0, r15, r1
asr.w r0, r1, r13
asr.w r0, r1, r15
@ BFC
bfc r13, #1, #1
bfc r15, #1, #1
@ BFI
bfi r13, r0, #1, #1
bfi r15, r0, #1, #1
bfi r0, r13, #1, #1
bfi r0, r15, #1, #1
@ BIC (immediate)
bic r13, r0, #1
bic r15, r0, #1
bic r0, r13, #1
bic r0, r15, #1
@ BIC (register)
bic.w r13, r0, r1
bic.w r15, r0, r1
bic.w r0, r13, r1
bic.w r0, r15, r1
bic.w r0, r1, r13
bic.w r0, r1, r15
@ BLX (register)
blx r13 @ OK
blx r15
@ BXJ
bxj r13
bxj r15
@ CLZ
clz r13, r0
clz r15, r0
clz r0, r13
clz r0, r15
@ CMN (immediate)
cmn r13, #1 @ OK
cmn r15, #1
@ CMN (register)
cmn.w r13, r0 @ OK
cmn.w r15, r0
cmn.w r0, r13
cmn.w r0, r15
@ CMP (immediate)
cmp.w r13, #1 @ OK
cmp.w r15, #1
@ CMP (register)
cmp r13, r0 @ OK
cmp r15, r0
cmp r0, r13 @ Deprecated
cmp r0, r15
cmp.n r0, r13 @ Deprecated
cmp.n r0, r15
cmp.w r13, r0 @ OK
cmp.w r15, r0
cmp.w r0, r13
cmp.w r0, r15
@ EOR (immediate)
eor r13, r0, #1
eor r15, r0, #1
eor r0, r13, #1
eor r0, r15, #1
@ EOR (register)
eor.w r13, r0, r1
eor.w r15, r0, r1
eor.w r0, r13, r1
eor.w r0, r15, r1
eor.w r0, r1, r13
eor.w r0, r1, r15
@ LSL (immediate)
lsl r13, r0, #1
lsl r15, r0, #1
lsl r0, r13, #1
lsl r0, r15, #1
@ LSL (register)
lsl.w r13, r0, r1
lsl.w r15, r0, r1
lsl.w r0, r13, r1
lsl.w r0, r15, r1
lsl.w r0, r1, r13
lsl.w r0, r1, r15
@ LSR (immediate)
lsr r13, r0, #1
lsr r15, r0, #1
lsr r0, r13, #1
lsr r0, r15, #1
@ LSR (register)
lsr.w r13, r0, r1
lsr.w r15, r0, r1
lsr.w r0, r13, r1
lsr.w r0, r15, r1
lsr.w r0, r1, r13
lsr.w r0, r1, r15
@ MCR
mcr p0, #1, r13, cr0, cr0
mcr p0, #1, r15, cr0, cr0 @ OK
@ MCRR
mcrr p0, #1, r13, r0, cr0
mcrr p0, #1, r15, r0, cr0
mcrr p0, #1, r0, r13, cr0
mcrr p0, #1, r0, r15, cr0
@ MLA
mla r13, r0, r0, r0
mla r15, r0, r0, r0
mla r0, r13, r0, r0
mla r0, r15, r0, r0
mla r0, r0, r13, r0
mla r0, r0, r15, r0
mla r0, r0, r0, r13
mla r0, r0, r0, r15
@ MLS
mls r13, r0, r0, r0
mls r15, r0, r0, r0
mls r0, r13, r0, r0
mls r0, r15, r0, r0
mls r0, r0, r13, r0
mls r0, r0, r15, r0
mls r0, r0, r0, r13
mls r0, r0, r0, r15
@ MOV (immediate)
mov.w r13, #1
mov.w r15, #1
@ MOV (register)
mov r13, r0 @ OK
mov r15, r0 @ OK
mov.w r0, r13 @ OK
mov.w r0, r15
mov.w r15, r0
mov.w r13, r0 @ OK
movs.w r0, r13
movs.w r0, r15
movs.w r13, r0
movs.w r15, r0
mov.w r13, r13
mov.w r15, r13
mov.w r13, r15
mov.w r15, r15
mov r13, r13 @ Deprecated
mov r15, r13 @ Deprecated
mov r13, r15 @ Deprecated
mov r15, r15 @ Deprecated
movs r13, r13
movs r15, r13
movs r13, r15
movs r15, r15
@ MOVT
movt r13, #1
movt r15, #1
@ MRC
mrc p0, #1, r13, cr0, cr0
mrc p0, #1, r15, cr0, cr0 @ OK
@ MRCC
mrrc p0, #1, r13, r0, cr0
mrrc p0, #1, r15, r0, cr0
mrrc p0, #1, r0, r13, cr0
mrrc p0, #1, r0, r15, cr0
@ MRS
mrs r13, cpsr
mrs r15, cpsr
@ MSR (register)
msr cpsr, r13
msr cpsr, r15
@ MUL
mul r13, r0, r0
mul r15, r0, r0
mul r0, r13, r0
mul r0, r15, r0
mul r0, r0, r13
mul r0, r0, r15
@ MVN (immediate)
mvn r13, #1
mvn r15, #1
@ MVN (register)
mvn.w r13, r0
mvn.w r15, r0
mvn.w r0, r13
mvn.w r0, r15
@ ORN (immediate)
orn r13, r0, #1
orn r15, r0, #1
orn r0, r13, #1
orn r0, r15, #1
@ ORN (register)
orn r13, r0, r0
orn r15, r0, r0
orn r0, r13, r0
orn r0, r15, r0
orn r0, r0, r13
orn r0, r0, r15
@ ORR (immediate)
orr r13, r0, #1
orr r15, r0, #1
orr r0, r13, #1
orr r0, r15, #1
@ ORR (register)
orr r13, r0, r0
orr r15, r0, r0
orr r0, r13, r0
orr r0, r15, r0
orr r0, r0, r13
orr r0, r0, r15
@ PKH
pkhbt r13, r0, r0
pkhbt r15, r0, r0
pkhbt r0, r13, r0
pkhbt r0, r15, r0
pkhbt r0, r0, r13
pkhbt r0, r0, r15
@ PLD (register)
pld [r0, r13]
pld [r0, r15]
pld [r13, r0] @ OK
pld [r15, r0]
@ PLI (register)
pli [r0, r13]
pli [r0, r15]
pli [r13, r0] @ OK
pli [r15, r0]
@ QADD
qadd r13, r0, r0
qadd r15, r0, r0
qadd r0, r13, r0
qadd r0, r15, r0
qadd r0, r0, r13
qadd r0, r0, r15
@ QADD16
qadd16 r13, r0, r0
qadd16 r15, r0, r0
qadd16 r0, r13, r0
qadd16 r0, r15, r0
qadd16 r0, r0, r13
qadd16 r0, r0, r15
@ QADD8
qadd8 r13, r0, r0
qadd8 r15, r0, r0
qadd8 r0, r13, r0
qadd8 r0, r15, r0
qadd8 r0, r0, r13
qadd8 r0, r0, r15
@ QASX
qasx r13, r0, r0
qasx r15, r0, r0
qasx r0, r13, r0
qasx r0, r15, r0
qasx r0, r0, r13
qasx r0, r0, r15
@ QDADD
qdadd r13, r0, r0
qdadd r15, r0, r0
qdadd r0, r13, r0
qdadd r0, r15, r0
qdadd r0, r0, r13
qdadd r0, r0, r15
@ QDSUB
qdsub r13, r0, r0
qdsub r15, r0, r0
qdsub r0, r13, r0
qdsub r0, r15, r0
qdsub r0, r0, r13
qdsub r0, r0, r15
@ QSAX
qsax r13, r0, r0
qsax r15, r0, r0
qsax r0, r13, r0
qsax r0, r15, r0
qsax r0, r0, r13
qsax r0, r0, r15
@ QSUB
qsub r13, r0, r0
qsub r15, r0, r0
qsub r0, r13, r0
qsub r0, r15, r0
qsub r0, r0, r13
qsub r0, r0, r15
@ QSUB16
qsub16 r13, r0, r0
qsub16 r15, r0, r0
qsub16 r0, r13, r0
qsub16 r0, r15, r0
qsub16 r0, r0, r13
qsub16 r0, r0, r15
@ QSUB8
qsub8 r13, r0, r0
qsub8 r15, r0, r0
qsub8 r0, r13, r0
qsub8 r0, r15, r0
qsub8 r0, r0, r13
qsub8 r0, r0, r15
@ RBIT
rbit r13, r0
rbit r15, r0
rbit r0, r13
rbit r0, r15
@ REV
rev.w r13, r0
rev.w r15, r0
rev.w r0, r13
rev.w r0, r15
@ REV16
rev16.w r13, r0
rev16.w r15, r0
rev16.w r0, r13
rev16.w r0, r15
@ REVSH
revsh.w r13, r0
revsh.w r15, r0
revsh.w r0, r13
revsh.w r0, r15
@ RFE
rfedb r15
rfeia r15
@ ROR (immediate)
ror r13, r0, #1
ror r15, r0, #1
ror r0, r13, #1
ror r0, r15, #1
@ ROR (register)
ror.w r13, r0, r1
ror.w r15, r0, r1
ror.w r0, r13, r1
ror.w r0, r15, r1
ror.w r0, r1, r13
ror.w r0, r1, r15
@ RRX
rrx r13, r0
rrx r15, r0
rrx r0, r13
rrx r0, r15
@ RSB (immediate)
rsb.w r13, r0, #1
rsb.w r15, r0, #1
rsb.w r0, r13, #1
rsb.w r0, r15, #1
@ RSB (register)
rsb r13, r0, r1
rsb r15, r0, r1
rsb r0, r13, r1
rsb r0, r15, r1
rsb r0, r1, r13
rsb r0, r1, r15
@ SADD16
sadd16 r13, r0, r0
sadd16 r15, r0, r0
sadd16 r0, r13, r0
sadd16 r0, r15, r0
sadd16 r0, r0, r13
sadd16 r0, r0, r15
@ SADD8
sadd8 r13, r0, r0
sadd8 r15, r0, r0
sadd8 r0, r13, r0
sadd8 r0, r15, r0
sadd8 r0, r0, r13
sadd8 r0, r0, r15
@ SASX
sasx r13, r0, r0
sasx r15, r0, r0
sasx r0, r13, r0
sasx r0, r15, r0
sasx r0, r0, r13
sasx r0, r0, r15
@ SBC (immediate)
sbc r13, r0, #1
sbc r15, r0, #1
sbc r0, r13, #1
sbc r0, r15, #1
@ SBC (register)
sbc r13, r0, r1
sbc r15, r0, r1
sbc r0, r13, r1
sbc r0, r15, r1
sbc r0, r1, r13
sbc r0, r1, r15
@ SBFX (immediate)
sbfx r13, r0, #1, #1
sbfx r15, r0, #1, #1
sbfx r0, r13, #1, #1
sbfx r0, r15, #1, #1
@ SDIV (register)
sdiv r13, r0, r1
sdiv r15, r0, r1
sdiv r0, r13, r1
sdiv r0, r15, r1
sdiv r0, r1, r13
sdiv r0, r1, r15
@ SEL (register)
sel r13, r0, r1
sel r15, r0, r1
sel r0, r13, r1
sel r0, r15, r1
sel r0, r1, r13
sel r0, r1, r15
@ SHADD16
shadd16 r13, r0, r0
shadd16 r15, r0, r0
shadd16 r0, r13, r0
shadd16 r0, r15, r0
shadd16 r0, r0, r13
shadd16 r0, r0, r15
@ SHADD8
shadd8 r13, r0, r0
shadd8 r15, r0, r0
shadd8 r0, r13, r0
shadd8 r0, r15, r0
shadd8 r0, r0, r13
shadd8 r0, r0, r15
@ SHASX
shasx r13, r0, r0
shasx r15, r0, r0
shasx r0, r13, r0
shasx r0, r15, r0
shasx r0, r0, r13
shasx r0, r0, r15
@ SHSAX
shsax r13, r0, r0
shsax r15, r0, r0
shsax r0, r13, r0
shsax r0, r15, r0
shsax r0, r0, r13
shsax r0, r0, r15
@ SHSUB16
shsub16 r13, r0, r0
shsub16 r15, r0, r0
shsub16 r0, r13, r0
shsub16 r0, r15, r0
shsub16 r0, r0, r13
shsub16 r0, r0, r15
@ SHSUB8
shsub8 r13, r0, r0
shsub8 r15, r0, r0
shsub8 r0, r13, r0
shsub8 r0, r15, r0
shsub8 r0, r0, r13
shsub8 r0, r0, r15
@ SMLABB
smlabb r13, r0, r0, r0
smlabb r15, r0, r0, r0
smlabb r0, r13, r0, r0
smlabb r0, r15, r0, r0
smlabb r0, r0, r13, r0
smlabb r0, r0, r15, r0
smlabb r0, r0, r0, r13
smlabb r0, r0, r0, r15
@ SMLAD
smlad r13, r0, r0, r0
smlad r15, r0, r0, r0
smlad r0, r13, r0, r0
smlad r0, r15, r0, r0
smlad r0, r0, r13, r0
smlad r0, r0, r15, r0
smlad r0, r0, r0, r13
smlad r0, r0, r0, r15
@ SMLAL
smlal r13, r0, r0, r0
smlal r15, r0, r0, r0
smlal r0, r13, r0, r0
smlal r0, r15, r0, r0
smlal r0, r0, r13, r0
smlal r0, r0, r15, r0
smlal r0, r0, r0, r13
smlal r0, r0, r0, r15
@ SMLALBB
smlalbb r13, r0, r0, r0
smlalbb r15, r0, r0, r0
smlalbb r0, r13, r0, r0
smlalbb r0, r15, r0, r0
smlalbb r0, r0, r13, r0
smlalbb r0, r0, r15, r0
smlalbb r0, r0, r0, r13
smlalbb r0, r0, r0, r15
@ SMLALD
smlald r13, r0, r0, r0
smlald r15, r0, r0, r0
smlald r0, r13, r0, r0
smlald r0, r15, r0, r0
smlald r0, r0, r13, r0
smlald r0, r0, r15, r0
smlald r0, r0, r0, r13
smlald r0, r0, r0, r15
@ SMLAWB
smlawb r13, r0, r0, r0
smlawb r15, r0, r0, r0
smlawb r0, r13, r0, r0
smlawb r0, r15, r0, r0
smlawb r0, r0, r13, r0
smlawb r0, r0, r15, r0
smlawb r0, r0, r0, r13
smlawb r0, r0, r0, r15
@ SMLSD
smlsd r13, r0, r0, r0
smlsd r15, r0, r0, r0
smlsd r0, r13, r0, r0
smlsd r0, r15, r0, r0
smlsd r0, r0, r13, r0
smlsd r0, r0, r15, r0
smlsd r0, r0, r0, r13
smlsd r0, r0, r0, r15
@ SMLSLD
smlsld r13, r0, r0, r0
smlsld r15, r0, r0, r0
smlsld r0, r13, r0, r0
smlsld r0, r15, r0, r0
smlsld r0, r0, r13, r0
smlsld r0, r0, r15, r0
smlsld r0, r0, r0, r13
smlsld r0, r0, r0, r15
@ SMMLA
smmla r13, r0, r0, r0
smmla r15, r0, r0, r0
smmla r0, r13, r0, r0
smmla r0, r15, r0, r0
smmla r0, r0, r13, r0
smmla r0, r0, r15, r0
smmla r0, r0, r0, r13
smmla r0, r0, r0, r15
@ SMMLS
smmls r13, r0, r0, r0
smmls r15, r0, r0, r0
smmls r0, r13, r0, r0
smmls r0, r15, r0, r0
smmls r0, r0, r13, r0
smmls r0, r0, r15, r0
smmls r0, r0, r0, r13
smmls r0, r0, r0, r15
@ SMMUL
smmul r13, r0, r0
smmul r15, r0, r0
smmul r0, r13, r0
smmul r0, r15, r0
smmul r0, r0, r13
smmul r0, r0, r15
@ SMUAD
smuad r13, r0, r0
smuad r15, r0, r0
smuad r0, r13, r0
smuad r0, r15, r0
smuad r0, r0, r13
smuad r0, r0, r15
@ SMULBB
smulbb r13, r0, r0
smulbb r15, r0, r0
smulbb r0, r13, r0
smulbb r0, r15, r0
smulbb r0, r0, r13
smulbb r0, r0, r15
@ SMULL
smull r13, r0, r0, r0
smull r15, r0, r0, r0
smull r0, r13, r0, r0
smull r0, r15, r0, r0
smull r0, r0, r13, r0
smull r0, r0, r15, r0
smull r0, r0, r0, r13
smull r0, r0, r0, r15
@ SMULWB
smulwb r13, r0, r0
smulwb r15, r0, r0
smulwb r0, r13, r0
smulwb r0, r15, r0
smulwb r0, r0, r13
smulwb r0, r0, r15
@ SMUSD
smusd r13, r0, r0
smusd r15, r0, r0
smusd r0, r13, r0
smusd r0, r15, r0
smusd r0, r0, r13
smusd r0, r0, r15
@ SSAT
ssat r13, #1, r0
ssat r15, #1, r0
ssat r0, #1, r13
ssat r0, #1, r15
ssat r1, #1, r3,asr #32
@ SSAT16
ssat16 r13, #1, r0
ssat16 r15, #1, r0
ssat16 r0, #1, r13
ssat16 r0, #1, r15
@ SSAX
ssax r13, r0, r1
ssax r15, r0, r1
ssax r0, r13, r1
ssax r0, r15, r1
ssax r0, r1, r13
ssax r0, r1, r15
@ SSUB16
ssub16 r13, r0, r1
ssub16 r15, r0, r1
ssub16 r0, r13, r1
ssub16 r0, r15, r1
ssub16 r0, r1, r13
ssub16 r0, r1, r15
@ SSUB8
ssub8 r13, r0, r1
ssub8 r15, r0, r1
ssub8 r0, r13, r1
ssub8 r0, r15, r1
ssub8 r0, r1, r13
ssub8 r0, r1, r15
@ SUB (immediate)
sub.w r13, r0, #1
sub.w r15, r0, #1
sub.w r0, r13, #1 @ SUB (SP minus immediate)
sub.w r0, r15, #1 @ ADR
subw r13, r0, #1
subw r15, r0, #1
subw r0, r13, #1 @ SUB (SP minus immediate)
subw r0, r15, #1 @ ADR
@ SUB (register)
sub.w r13, r0, r1
sub.w r15, r0, r1
sub.w r0, r13, r1 @ SUB (SP minus register)
sub.w r0, r15, r1
sub.w r0, r1, r13
sub.w r0, r1, r15
@ SUB (SP minus immediate)
sub.w r0, r13, #1 @ OK
sub.w r15, r13, #1
subs.w r15, r13, #1
subw r15, r13, #1
@ SUB (SP minus register)
sub.w r13, r13, r0 @ OK
sub.w r15, r13, r0
sub.w r0, r13, r13
sub.w r0, r13, r15
@ SXTAB
sxtab r13, r0, r1
sxtab r15, r0, r1
sxtab r0, r13, r1
sxtab r0, r15, r1
sxtab r0, r1, r13
sxtab r0, r1, r15
@ SXTAB16
sxtab16 r13, r0, r1
sxtab16 r15, r0, r1
sxtab16 r0, r13, r1
sxtab16 r0, r15, r1
sxtab16 r0, r1, r13
sxtab16 r0, r1, r15
@ SXTAH
sxtah r13, r0, r1
sxtah r15, r0, r1
sxtah r0, r13, r1
sxtah r0, r15, r1
sxtah r0, r1, r13
sxtah r0, r1, r15
@ SXTB
sxtb r13, r0
sxtb r15, r0
sxtb r0, r13
sxtb r0, r15
@ SXTB16
sxtb16 r13, r0
sxtb16 r15, r0
sxtb16 r0, r13
sxtb16 r0, r15
@ SXTH
sxth r13, r0
sxth r15, r0
sxth r0, r13
sxth r0, r15
@ TBB
tbb [r13, r0]
tbb [r15, r0] @ OK
tbb [r0, r13]
tbb [r0, r15]
@ TBH
tbh [r13, r0]
tbh [r15, r0] @ OK
tbh [r0, r13]
tbh [r0, r15]
@ TEQ (immediate)
teq r13, #1
teq r15, #1
@ TEQ (register)
teq r13, r0
teq r15, r0
teq r0, r13
teq r0, r15
@ TST (immediate)
tst r13, #1
tst r15, #1
@ TST (register)
tst.w r13, r0
tst.w r15, r0
tst.w r0, r13
tst.w r0, r15
@ UADD16
uadd16 r13, r0, r0
uadd16 r15, r0, r0
uadd16 r0, r13, r0
uadd16 r0, r15, r0
uadd16 r0, r0, r13
uadd16 r0, r0, r15
@ UADD8
uadd8 r13, r0, r0
uadd8 r15, r0, r0
uadd8 r0, r13, r0
uadd8 r0, r15, r0
uadd8 r0, r0, r13
uadd8 r0, r0, r15
@ UASX
uasx r13, r0, r0
uasx r15, r0, r0
uasx r0, r13, r0
uasx r0, r15, r0
uasx r0, r0, r13
uasx r0, r0, r15
@ UBFX (immediate)
ubfx r13, r0, #1, #1
ubfx r15, r0, #1, #1
ubfx r0, r13, #1, #1
ubfx r0, r15, #1, #1
@ UDIV (register)
udiv r13, r0, r1
udiv r15, r0, r1
udiv r0, r13, r1
udiv r0, r15, r1
udiv r0, r1, r13
udiv r0, r1, r15
@ UHADD16
uhadd16 r13, r0, r0
uhadd16 r15, r0, r0
uhadd16 r0, r13, r0
uhadd16 r0, r15, r0
uhadd16 r0, r0, r13
uhadd16 r0, r0, r15
@ UHADD8
uhadd8 r13, r0, r0
uhadd8 r15, r0, r0
uhadd8 r0, r13, r0
uhadd8 r0, r15, r0
uhadd8 r0, r0, r13
uhadd8 r0, r0, r15
@ UHASX
uhasx r13, r0, r0
uhasx r15, r0, r0
uhasx r0, r13, r0
uhasx r0, r15, r0
uhasx r0, r0, r13
uhasx r0, r0, r15
@ UHSAX
uhsax r13, r0, r0
uhsax r15, r0, r0
uhsax r0, r13, r0
uhsax r0, r15, r0
uhsax r0, r0, r13
uhsax r0, r0, r15
@ UHSUB16
uhsub16 r13, r0, r0
uhsub16 r15, r0, r0
uhsub16 r0, r13, r0
uhsub16 r0, r15, r0
uhsub16 r0, r0, r13
uhsub16 r0, r0, r15
@ UHSUB8
uhsub8 r13, r0, r0
uhsub8 r15, r0, r0
uhsub8 r0, r13, r0
uhsub8 r0, r15, r0
uhsub8 r0, r0, r13
uhsub8 r0, r0, r15
@ UMAAL
umaal r13, r0, r0, r0
umaal r15, r0, r0, r0
umaal r0, r13, r0, r0
umaal r0, r15, r0, r0
umaal r0, r0, r13, r0
umaal r0, r0, r15, r0
umaal r0, r0, r0, r13
umaal r0, r0, r0, r15
@ UMLAL
umlal r13, r0, r0, r0
umlal r15, r0, r0, r0
umlal r0, r13, r0, r0
umlal r0, r15, r0, r0
umlal r0, r0, r13, r0
umlal r0, r0, r15, r0
umlal r0, r0, r0, r13
umlal r0, r0, r0, r15
@ UMULL
umull r13, r0, r0, r0
umull r15, r0, r0, r0
umull r0, r13, r0, r0
umull r0, r15, r0, r0
umull r0, r0, r13, r0
umull r0, r0, r15, r0
umull r0, r0, r0, r13
umull r0, r0, r0, r15
@ UQADD16
uqadd16 r13, r0, r0
uqadd16 r15, r0, r0
uqadd16 r0, r13, r0
uqadd16 r0, r15, r0
uqadd16 r0, r0, r13
uqadd16 r0, r0, r15
@ UQADD8
uqadd8 r13, r0, r0
uqadd8 r15, r0, r0
uqadd8 r0, r13, r0
uqadd8 r0, r15, r0
uqadd8 r0, r0, r13
uqadd8 r0, r0, r15
@ UQASX
uqasx r13, r0, r0
uqasx r15, r0, r0
uqasx r0, r13, r0
uqasx r0, r15, r0
uqasx r0, r0, r13
uqasx r0, r0, r15
@ UQSAX
uqsax r13, r0, r0
uqsax r15, r0, r0
uqsax r0, r13, r0
uqsax r0, r15, r0
uqsax r0, r0, r13
uqsax r0, r0, r15
@ UQSUB16
uqsub16 r13, r0, r0
uqsub16 r15, r0, r0
uqsub16 r0, r13, r0
uqsub16 r0, r15, r0
uqsub16 r0, r0, r13
uqsub16 r0, r0, r15
@ UQSUB8
uqsub8 r13, r0, r0
uqsub8 r15, r0, r0
uqsub8 r0, r13, r0
uqsub8 r0, r15, r0
uqsub8 r0, r0, r13
uqsub8 r0, r0, r15
@ USAD8
usad8 r13, r0, r0
usad8 r15, r0, r0
usad8 r0, r13, r0
usad8 r0, r15, r0
usad8 r0, r0, r13
usad8 r0, r0, r15
@ USADA8
usada8 r13, r0, r0, r0
usada8 r15, r0, r0, r0
usada8 r0, r13, r0, r0
usada8 r0, r15, r0, r0
usada8 r0, r0, r13, r0
usada8 r0, r0, r15, r0
usada8 r0, r0, r0, r13
usada8 r0, r0, r0, r15
@ USAT
usat r13, #1, r0
usat r15, #1, r0
usat r0, #1, r13
usat r0, #1, r15
usat r1, #1, r3,asr #32
@ USAT16
usat16 r13, #1, r0
usat16 r15, #1, r0
usat16 r0, #1, r13
usat16 r0, #1, r15
@ USAX
usax r13, r0, r1
usax r15, r0, r1
usax r0, r13, r1
usax r0, r15, r1
usax r0, r1, r13
usax r0, r1, r15
@ USUB16
usub16 r13, r0, r1
usub16 r15, r0, r1
usub16 r0, r13, r1
usub16 r0, r15, r1
usub16 r0, r1, r13
usub16 r0, r1, r15
@ USUB8
usub8 r13, r0, r1
usub8 r15, r0, r1
usub8 r0, r13, r1
usub8 r0, r15, r1
usub8 r0, r1, r13
usub8 r0, r1, r15
@ UXTAB
uxtab r13, r0, r1
uxtab r15, r0, r1
uxtab r0, r13, r1
uxtab r0, r15, r1
uxtab r0, r1, r13
uxtab r0, r1, r15
@ UXTAB16
uxtab16 r13, r0, r1
uxtab16 r15, r0, r1
uxtab16 r0, r13, r1
uxtab16 r0, r15, r1
uxtab16 r0, r1, r13
uxtab16 r0, r1, r15
@ UXTAH
uxtah r13, r0, r1
uxtah r15, r0, r1
uxtah r0, r13, r1
uxtah r0, r15, r1
uxtah r0, r1, r13
uxtah r0, r1, r15
@ UXTB
uxtb r13, r0
uxtb r15, r0
uxtb r0, r13
uxtb r0, r15
@ UXTB16
uxtb16 r13, r0
uxtb16 r15, r0
uxtb16 r0, r13
uxtb16 r0, r15
@ UXTH
uxth r13, r0
uxth r15, r0
uxth r0, r13
uxth r0, r15
|
tactcomplabs/xbgas-binutils-gdb
| 1,305
|
gas/testsuite/gas/arm/mve-vmlaldav-bad.s
|
.macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlaldav.s16 r0, sp, q1, q2
cond vmlaldav
cond vmlaldava
cond vmlaldavx
cond vmlaldavax
vmlaldav.s64 r0, r1, q1, q2
vmlaldav.f32 r0, r1, q1, q2
vmlaldav.s8 r0, r1, q1, q2
vmlaldav.s16 r0, q1, q2
vmlaldava.s64 r0, r1, q1, q2
vmlaldava.f32 r0, r1, q1, q2
vmlaldava.s8 r0, r1, q1, q2
vmlaldava.s16 r0, q1, q2
vmlaldavx.s64 r0, r1, q1, q2
vmlaldavx.f32 r0, r1, q1, q2
vmlaldavx.s8 r0, r1, q1, q2
vmlaldavx.s16 r0, q1, q2
vmlaldavax.s64 r0, r1, q1, q2
vmlaldavax.f32 r0, r1, q1, q2
vmlaldavax.s8 r0, r1, q1, q2
vmlaldavax.s16 r0, q1, q2
it eq
vmlaldaveq.s16 r0, r1, q1, q2
vmlaldaveq.s16 r0, r1, q1, q2
vmlaldaveq.s16 r0, r1, q1, q2
vmlaldavt.s16 r0, r1, q1, q2
vpst
vmlaldav.s16 r0, r1, q1, q2
it eq
vmlaldavaeq.s16 r0, r1, q1, q2
vmlaldavaeq.s16 r0, r1, q1, q2
vmlaldavaeq.s16 r0, r1, q1, q2
vmlaldavat.s16 r0, r1, q1, q2
vpst
vmlaldava.s16 r0, r1, q1, q2
it eq
vmlaldavxeq.s16 r0, r1, q1, q2
vmlaldavxeq.s16 r0, r1, q1, q2
vmlaldavxeq.s16 r0, r1, q1, q2
vmlaldavxt.s16 r0, r1, q1, q2
vpst
vmlaldavx.s16 r0, r1, q1, q2
it eq
vmlaldavaxeq.s16 r0, r1, q1, q2
vmlaldavaxeq.s16 r0, r1, q1, q2
vmlaldavaxeq.s16 r0, r1, q1, q2
vmlaldavaxt.s16 r0, r1, q1, q2
vpst
vmlaldavax.s16 r0, r1, q1, q2
|
tactcomplabs/xbgas-binutils-gdb
| 1,225
|
gas/testsuite/gas/arm/bundle-lock.s
|
.syntax unified
.bundle_align_mode 4
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,16) by 2 or 4.
size_arm = 4
size_thumb = 2
.macro offset_sequence which, size, offset
.p2align 4
\which\()_sequence_\size\()_offset_\offset\():
.rept \offset / size_\which
bkpt
.endr
test_sequence \size
.endm
.macro test_offsets_arm size
.arm
offset_sequence arm, \size, 0
offset_sequence arm, \size, 4
offset_sequence arm, \size, 8
offset_sequence arm, \size, 12
.endm
.macro test_offsets_thumb size
.thumb
offset_sequence thumb, \size, 0
offset_sequence thumb, \size, 2
offset_sequence thumb, \size, 4
offset_sequence thumb, \size, 6
offset_sequence thumb, \size, 8
offset_sequence thumb, \size, 10
offset_sequence thumb, \size, 12
offset_sequence thumb, \size, 14
.endm
.macro test_sequence size
.bundle_lock
adds r0, r1
.rept \size - 1
subs r0, r1
.endr
.bundle_unlock
.endm
test_offsets_arm 1
test_offsets_arm 2
test_offsets_arm 3
test_offsets_arm 4
test_offsets_thumb 1
test_offsets_thumb 2
test_offsets_thumb 3
test_offsets_thumb 4
test_offsets_thumb 5
test_offsets_thumb 6
test_offsets_thumb 7
test_offsets_thumb 8
.arm
.p2align 4
bkpt
|
tactcomplabs/xbgas-binutils-gdb
| 12,605
|
gas/testsuite/gas/arm/maverick.s
|
.text
.align
load_store:
cfldrseq mvf5, [sp, #1020]
cfldrsmi mvf14, [r11, #292]
cfldrsvc mvf2, [r12, #-956]
cfldrslt mvf0, [sl, #-1020]
cfldrscc mvf12, [r1, #-156]
cfldrs mvf13, [r9, #416]!
cfldrscs mvf9, [r0, #-1020]!
cfldrsls mvf4, [r1, #-156]!
cfldrsle mvf7, [r9, #416]!
cfldrsvs mvf11, [r0, #-1020]!
cfldrscc mvf12, [r1], #-156
cfldrs mvf13, [r9], #416
cfldrscs mvf9, [r0], #-1020
cfldrsls mvf4, [r1], #-156
cfldrsle mvf7, [r9], #416
cfldrdvs mvd11, [r0, #-1020]
cfldrdcc mvd12, [r1, #-156]
cfldrd mvd13, [r9, #416]
cfldrdcs mvd9, [r0, #-1020]
cfldrdls mvd4, [r1, #-156]
cfldrdle mvd7, [r9, #416]!
cfldrdvs mvd11, [r0, #-1020]!
cfldrdcc mvd12, [r1, #-156]!
cfldrd mvd13, [r9, #416]!
cfldrdcs mvd9, [r0, #-1020]!
cfldrdls mvd4, [r1], #-156
cfldrdle mvd7, [r9], #416
cfldrdvs mvd11, [r0], #-1020
cfldrdcc mvd12, [r1], #-156
cfldrd mvd13, [r9], #416
cfldr32cs mvfx9, [r0, #-1020]
cfldr32ls mvfx4, [r1, #-156]
cfldr32le mvfx7, [r9, #416]
cfldr32vs mvfx11, [r0, #-1020]
cfldr32cc mvfx12, [r1, #-156]
cfldr32 mvfx13, [r9, #416]!
cfldr32cs mvfx9, [r0, #-1020]!
cfldr32ls mvfx4, [r1, #-156]!
cfldr32le mvfx7, [r9, #416]!
cfldr32vs mvfx11, [r0, #-1020]!
cfldr32cc mvfx12, [r1], #-156
cfldr32 mvfx13, [r9], #416
cfldr32cs mvfx9, [r0], #-1020
cfldr32ls mvfx4, [r1], #-156
cfldr32le mvfx7, [r9], #416
cfldr64vs mvdx11, [r0, #-1020]
cfldr64cc mvdx12, [r1, #-156]
cfldr64 mvdx13, [r9, #416]
cfldr64cs mvdx9, [r0, #-1020]
cfldr64ls mvdx4, [r1, #-156]
cfldr64le mvdx7, [r9, #416]!
cfldr64vs mvdx11, [r0, #-1020]!
cfldr64cc mvdx12, [r1, #-156]!
cfldr64 mvdx13, [r9, #416]!
cfldr64cs mvdx9, [r0, #-1020]!
cfldr64ls mvdx4, [r1], #-156
cfldr64le mvdx7, [r9], #416
cfldr64vs mvdx11, [r0], #-1020
cfldr64cc mvdx12, [r1], #-156
cfldr64 mvdx13, [r9], #416
cfstrscs mvf9, [r0, #-1020]
cfstrsls mvf4, [r1, #-156]
cfstrsle mvf7, [r9, #416]
cfstrsvs mvf11, [r0, #-1020]
cfstrscc mvf12, [r1, #-156]
cfstrs mvf13, [r9, #416]!
cfstrscs mvf9, [r0, #-1020]!
cfstrsls mvf4, [r1, #-156]!
cfstrsle mvf7, [r9, #416]!
cfstrsvs mvf11, [r0, #-1020]!
cfstrscc mvf12, [r1], #-156
cfstrs mvf13, [r9], #416
cfstrscs mvf9, [r0], #-1020
cfstrsls mvf4, [r1], #-156
cfstrsle mvf7, [r9], #416
cfstrdvs mvd11, [r0, #-1020]
cfstrdcc mvd12, [r1, #-156]
cfstrd mvd13, [r9, #416]
cfstrdcs mvd9, [r0, #-1020]
cfstrdls mvd4, [r1, #-156]
cfstrdle mvd7, [r9, #416]!
cfstrdvs mvd11, [r0, #-1020]!
cfstrdcc mvd12, [r1, #-156]!
cfstrd mvd13, [r9, #416]!
cfstrdcs mvd9, [r0, #-1020]!
cfstrdls mvd4, [r1], #-156
cfstrdle mvd7, [r9], #416
cfstrdvs mvd11, [r0], #-1020
cfstrdcc mvd12, [r1], #-156
cfstrd mvd13, [r9], #416
cfstr32cs mvfx9, [r0, #-1020]
cfstr32ls mvfx4, [r1, #-156]
cfstr32le mvfx7, [r9, #416]
cfstr32vs mvfx11, [r0, #-1020]
cfstr32cc mvfx12, [r1, #-156]
cfstr32 mvfx13, [r9, #416]!
cfstr32cs mvfx9, [r0, #-1020]!
cfstr32ls mvfx4, [r1, #-156]!
cfstr32le mvfx7, [r9, #416]!
cfstr32vs mvfx11, [r0, #-1020]!
cfstr32cc mvfx12, [r1], #-156
cfstr32 mvfx13, [r9], #416
cfstr32cs mvfx9, [r0], #-1020
cfstr32ls mvfx4, [r1], #-156
cfstr32le mvfx7, [r9], #416
cfstr64vs mvdx11, [r0, #-1020]
cfstr64cc mvdx12, [r1, #-156]
cfstr64 mvdx13, [r9, #416]
cfstr64cs mvdx9, [r0, #-1020]
cfstr64ls mvdx4, [r1, #-156]
cfstr64le mvdx7, [r9, #416]!
cfstr64vs mvdx11, [r0, #-1020]!
cfstr64cc mvdx12, [r1, #-156]!
cfstr64 mvdx13, [r9, #416]!
cfstr64cs mvdx9, [r0, #-1020]!
cfstr64ls mvdx4, [r1], #-156
cfstr64le mvdx7, [r9], #416
cfstr64vs mvdx11, [r0], #-1020
cfstr64cc mvdx12, [r1], #-156
cfstr64 mvdx13, [r9], #416
move:
cfmvsrcs mvf9, r0
cfmvsrpl mvf15, r7
cfmvsrls mvf4, r1
cfmvsrcc mvf8, r2
cfmvsrvc mvf2, r12
cfmvrsgt r9, mvf11
cfmvrseq sl, mvf5
cfmvrsal r4, mvf12
cfmvrsge fp, mvf8
cfmvrs r5, mvf6
cfmvdlrlt mvd4, r9
cfmvdlrls mvd0, r10
cfmvdlr mvd10, r4
cfmvdlrmi mvd14, r11
cfmvdlrhi mvd13, r5
cfmvrdlcs r12, mvd12
cfmvrdlvs r3, mvd0
cfmvrdlvc r13, mvd14
cfmvrdlcc r14, mvd10
cfmvrdlne r8, mvd15
cfmvdhrle mvd6, ip
cfmvdhrmi mvd2, r3
cfmvdhreq mvd5, sp
cfmvdhrge mvd9, lr
cfmvdhral mvd3, r8
cfmvrdhle r5, mvd2
cfmvrdhne r6, mvd6
cfmvrdhlt r0, mvd7
cfmvrdhpl r7, mvd3
cfmvrdhgt r1, mvd1
cfmv64lrhi mvdx15, r5
cfmv64lrvs mvdx11, r6
cfmv64lrcs mvdx9, r0
cfmv64lrpl mvdx15, r7
cfmv64lrls mvdx4, r1
cfmvr64lcc r8, mvdx13
cfmvr64lvc pc, mvdx1
cfmvr64lgt r9, mvdx11
cfmvr64leq sl, mvdx5
cfmvr64lal r4, mvdx12
cfmv64hrge mvdx1, r8
cfmv64hr mvdx13, r15
cfmv64hrlt mvdx4, r9
cfmv64hrls mvdx0, r10
cfmv64hr mvdx10, r4
cfmvr64hmi r1, mvdx3
cfmvr64hhi r2, mvdx7
cfmvr64hcs r12, mvdx12
cfmvr64hvs r3, mvdx0
cfmvr64hvc r13, mvdx14
cfmval32cc mvax0, mvfx10
cfmval32ne mvax1, mvfx15
cfmval32le mvax0, mvfx11
cfmval32mi mvax0, mvfx9
cfmval32eq mvax1, mvfx15
cfmv32alge mvfx9, mvax0
cfmv32alal mvfx3, mvax1
cfmv32alle mvfx7, mvax0
cfmv32alne mvfx12, mvax0
cfmv32allt mvfx0, mvax1
cfmvam32pl mvax2, mvfx3
cfmvam32gt mvax1, mvfx1
cfmvam32hi mvax3, mvfx13
cfmvam32vs mvax3, mvfx4
cfmvam32cs mvax1, mvfx0
cfmv32ampl mvfx15, mvax2
cfmv32amls mvfx4, mvax1
cfmv32amcc mvfx8, mvax3
cfmv32amvc mvfx2, mvax3
cfmv32amgt mvfx6, mvax1
cfmvah32eq mvax1, mvfx5
cfmvah32al mvax2, mvfx12
cfmvah32ge mvax3, mvfx8
cfmvah32 mvax2, mvfx6
cfmvah32lt mvax2, mvfx2
cfmv32ahls mvfx0, mvax1
cfmv32ah mvfx10, mvax2
cfmv32ahmi mvfx14, mvax3
cfmv32ahhi mvfx13, mvax2
cfmv32ahcs mvfx1, mvax2
cfmva32vs mvax1, mvfx0
cfmva32vc mvax3, mvfx14
cfmva32cc mvax0, mvfx10
cfmva32ne mvax1, mvfx15
cfmva32le mvax0, mvfx11
cfmv32ami mvfx2, mvax1
cfmv32aeq mvfx5, mvax3
cfmv32age mvfx9, mvax0
cfmv32aal mvfx3, mvax1
cfmv32ale mvfx7, mvax0
cfmva64ne mvax2, mvdx6
cfmva64lt mvax0, mvdx7
cfmva64pl mvax2, mvdx3
cfmva64gt mvax1, mvdx1
cfmva64hi mvax3, mvdx13
cfmv64avs mvdx11, mvax2
cfmv64acs mvdx9, mvax0
cfmv64apl mvdx15, mvax2
cfmv64als mvdx4, mvax1
cfmv64acc mvdx8, mvax3
cfmvsc32vc dspsc, mvdx1
cfmvsc32gt dspsc, mvdx11
cfmvsc32eq dspsc, mvdx5
cfmvsc32al dspsc, mvdx12
cfmvsc32ge dspsc, mvdx8
cfmv32sc mvdx13, dspsc
cfmv32sclt mvdx4, dspsc
cfmv32scls mvdx0, dspsc
cfmv32sc mvdx10, dspsc
cfmv32scmi mvdx14, dspsc
cfcpyshi mvf13, mvf7
cfcpyscs mvf1, mvf12
cfcpysvs mvf11, mvf0
cfcpysvc mvf5, mvf14
cfcpyscc mvf12, mvf10
cfcpydne mvd8, mvd15
cfcpydle mvd6, mvd11
cfcpydmi mvd2, mvd9
cfcpydeq mvd5, mvd15
cfcpydge mvd9, mvd4
conv:
cfcvtsdal mvd3, mvf8
cfcvtsdle mvd7, mvf2
cfcvtsdne mvd12, mvf6
cfcvtsdlt mvd0, mvf7
cfcvtsdpl mvd14, mvf3
cfcvtdsgt mvf10, mvd1
cfcvtdshi mvf15, mvd13
cfcvtdsvs mvf11, mvd4
cfcvtdscs mvf9, mvd0
cfcvtdspl mvf15, mvd10
cfcvt32sls mvf4, mvfx14
cfcvt32scc mvf8, mvfx13
cfcvt32svc mvf2, mvfx1
cfcvt32sgt mvf6, mvfx11
cfcvt32seq mvf7, mvfx5
cfcvt32dal mvd3, mvfx12
cfcvt32dge mvd1, mvfx8
cfcvt32d mvd13, mvfx6
cfcvt32dlt mvd4, mvfx2
cfcvt32dls mvd0, mvfx5
cfcvt64s mvf10, mvdx9
cfcvt64smi mvf14, mvdx3
cfcvt64shi mvf13, mvdx7
cfcvt64scs mvf1, mvdx12
cfcvt64svs mvf11, mvdx0
cfcvt64dvc mvd5, mvdx14
cfcvt64dcc mvd12, mvdx10
cfcvt64dne mvd8, mvdx15
cfcvt64dle mvd6, mvdx11
cfcvt64dmi mvd2, mvdx9
cfcvts32eq mvfx5, mvf15
cfcvts32ge mvfx9, mvf4
cfcvts32al mvfx3, mvf8
cfcvts32le mvfx7, mvf2
cfcvts32ne mvfx12, mvf6
cfcvtd32lt mvfx0, mvd7
cfcvtd32pl mvfx14, mvd3
cfcvtd32gt mvfx10, mvd1
cfcvtd32hi mvfx15, mvd13
cfcvtd32vs mvfx11, mvd4
cftruncs32cs mvfx9, mvf0
cftruncs32pl mvfx15, mvf10
cftruncs32ls mvfx4, mvf14
cftruncs32cc mvfx8, mvf13
cftruncs32vc mvfx2, mvf1
cftruncd32gt mvfx6, mvd11
cftruncd32eq mvfx7, mvd5
cftruncd32al mvfx3, mvd12
cftruncd32ge mvfx1, mvd8
cftruncd32 mvfx13, mvd6
shift:
cfrshl32lt mvfx4, mvfx2, r3
cfrshl32pl mvfx15, mvfx10, r4
cfrshl32al mvfx3, mvfx8, r2
cfrshl32cs mvfx1, mvfx12, r9
cfrshl32eq mvfx7, mvfx5, r7
cfrshl64gt mvdx10, mvdx1, r8
cfrshl64le mvdx6, mvdx11, r6
cfrshl64ls mvdx0, mvdx5, sp
cfrshl64ls mvdx4, mvdx14, r11
cfrshl64le mvdx7, mvdx2, r12
cfsh32vs mvfx11, mvfx0, #-1
cfsh32al mvfx3, mvfx12, #24
cfsh32hi mvfx15, mvfx13, #33
cfsh32mi mvfx2, mvfx9, #0
cfsh32 mvfx10, mvfx9, #32
cfsh64cc mvdx8, mvdx13, #-31
cfsh64ne mvdx12, mvdx6, #1
cfsh64vc mvdx5, mvdx14, #-32
cfsh64ge mvdx1, mvdx8, #-27
cfsh64vs mvdx11, mvdx4, #-5
comp:
cfcmpseq r10, mvf15, mvf10
cfcmpsmi r1, mvf3, mvf8
cfcmpsvc pc, mvf1, mvf12
cfcmpslt r0, mvf7, mvf5
cfcmpscc r14, mvf10, mvf1
cfcmpd r5, mvd6, mvd11
cfcmpdcs r3, mvd0, mvd5
cfcmpdge r4, mvd4, mvd14
cfcmpdhi r2, mvd7, mvd2
cfcmpdgt r9, mvd11, mvd0
cfcmp32pl r7, mvfx3, mvfx12
cfcmp32ne r8, mvfx15, mvfx13
cfcmp32lt r6, mvfx2, mvfx9
cfcmp32pl sp, mvfx10, mvfx9
cfcmp32al r11, mvfx8, mvfx13
cfcmp64cs r12, mvdx12, mvdx6
cfcmp64eq sl, mvdx5, mvdx14
cfcmp64gt r1, mvdx1, mvdx8
cfcmp64le r15, mvdx11, mvdx4
cfcmp64ls r0, mvdx5, mvdx15
fp_arith:
cfabssls mvf4, mvf14
cfabsscc mvf8, mvf13
cfabssvc mvf2, mvf1
cfabssgt mvf6, mvf11
cfabsseq mvf7, mvf5
cfabsdal mvd3, mvd12
cfabsdge mvd1, mvd8
cfabsd mvd13, mvd6
cfabsdlt mvd4, mvd2
cfabsdls mvd0, mvd5
cfnegs mvf10, mvf9
cfnegsmi mvf14, mvf3
cfnegshi mvf13, mvf7
cfnegscs mvf1, mvf12
cfnegsvs mvf11, mvf0
cfnegdvc mvd5, mvd14
cfnegdcc mvd12, mvd10
cfnegdne mvd8, mvd15
cfnegdle mvd6, mvd11
cfnegdmi mvd2, mvd9
cfaddseq mvf5, mvf15, mvf10
cfaddsmi mvf14, mvf3, mvf8
cfaddsvc mvf2, mvf1, mvf12
cfaddslt mvf0, mvf7, mvf5
cfaddscc mvf12, mvf10, mvf1
cfaddd mvd13, mvd6, mvd11
cfadddcs mvd9, mvd0, mvd5
cfadddge mvd9, mvd4, mvd14
cfadddhi mvd13, mvd7, mvd2
cfadddgt mvd6, mvd11, mvd0
cfsubspl mvf14, mvf3, mvf12
cfsubsne mvf8, mvf15, mvf13
cfsubslt mvf4, mvf2, mvf9
cfsubspl mvf15, mvf10, mvf9
cfsubsal mvf3, mvf8, mvf13
cfsubdcs mvd1, mvd12, mvd6
cfsubdeq mvd7, mvd5, mvd14
cfsubdgt mvd10, mvd1, mvd8
cfsubdle mvd6, mvd11, mvd4
cfsubdls mvd0, mvd5, mvd15
cfmulsls mvf4, mvf14, mvf3
cfmulsle mvf7, mvf2, mvf1
cfmulsvs mvf11, mvf0, mvf7
cfmulsal mvf3, mvf12, mvf10
cfmulshi mvf15, mvf13, mvf6
cfmuldmi mvd2, mvd9, mvd0
cfmuld mvd10, mvd9, mvd4
cfmuldcc mvd8, mvd13, mvd7
cfmuldne mvd12, mvd6, mvd11
cfmuldvc mvd5, mvd14, mvd3
int_arith:
cfabs32ge mvfx1, mvfx8
cfabs32 mvfx13, mvfx6
cfabs32lt mvfx4, mvfx2
cfabs32ls mvfx0, mvfx5
cfabs32 mvfx10, mvfx9
cfabs64mi mvdx14, mvdx3
cfabs64hi mvdx13, mvdx7
cfabs64cs mvdx1, mvdx12
cfabs64vs mvdx11, mvdx0
cfabs64vc mvdx5, mvdx14
cfneg32cc mvfx12, mvfx10
cfneg32ne mvfx8, mvfx15
cfneg32le mvfx6, mvfx11
cfneg32mi mvfx2, mvfx9
cfneg32eq mvfx5, mvfx15
cfneg64ge mvdx9, mvdx4
cfneg64al mvdx3, mvdx8
cfneg64le mvdx7, mvdx2
cfneg64ne mvdx12, mvdx6
cfneg64lt mvdx0, mvdx7
cfadd32pl mvfx14, mvfx3, mvfx12
cfadd32ne mvfx8, mvfx15, mvfx13
cfadd32lt mvfx4, mvfx2, mvfx9
cfadd32pl mvfx15, mvfx10, mvfx9
cfadd32al mvfx3, mvfx8, mvfx13
cfadd64cs mvdx1, mvdx12, mvdx6
cfadd64eq mvdx7, mvdx5, mvdx14
cfadd64gt mvdx10, mvdx1, mvdx8
cfadd64le mvdx6, mvdx11, mvdx4
cfadd64ls mvdx0, mvdx5, mvdx15
cfsub32ls mvfx4, mvfx14, mvfx3
cfsub32le mvfx7, mvfx2, mvfx1
cfsub32vs mvfx11, mvfx0, mvfx7
cfsub32al mvfx3, mvfx12, mvfx10
cfsub32hi mvfx15, mvfx13, mvfx6
cfsub64mi mvdx2, mvdx9, mvdx0
cfsub64 mvdx10, mvdx9, mvdx4
cfsub64cc mvdx8, mvdx13, mvdx7
cfsub64ne mvdx12, mvdx6, mvdx11
cfsub64vc mvdx5, mvdx14, mvdx3
cfmul32ge mvfx1, mvfx8, mvfx15
cfmul32vs mvfx11, mvfx4, mvfx2
cfmul32eq mvfx5, mvfx15, mvfx10
cfmul32mi mvfx14, mvfx3, mvfx8
cfmul32vc mvfx2, mvfx1, mvfx12
cfmul64lt mvdx0, mvdx7, mvdx5
cfmul64cc mvdx12, mvdx10, mvdx1
cfmul64 mvdx13, mvdx6, mvdx11
cfmul64cs mvdx9, mvdx0, mvdx5
cfmul64ge mvdx9, mvdx4, mvdx14
cfmac32hi mvfx13, mvfx7, mvfx2
cfmac32gt mvfx6, mvfx11, mvfx0
cfmac32pl mvfx14, mvfx3, mvfx12
cfmac32ne mvfx8, mvfx15, mvfx13
cfmac32lt mvfx4, mvfx2, mvfx9
cfmsc32pl mvfx15, mvfx10, mvfx9
cfmsc32al mvfx3, mvfx8, mvfx13
cfmsc32cs mvfx1, mvfx12, mvfx6
cfmsc32eq mvfx7, mvfx5, mvfx14
cfmsc32gt mvfx10, mvfx1, mvfx8
acc_arith:
cfmadd32le mvax0, mvfx11, mvfx4, mvfx2
cfmadd32ls mvax0, mvfx5, mvfx15, mvfx10
cfmadd32ls mvax0, mvfx14, mvfx3, mvfx8
cfmadd32le mvax2, mvfx2, mvfx1, mvfx12
cfmadd32vs mvax1, mvfx0, mvfx7, mvfx5
cfmsub32al mvax2, mvfx12, mvfx10, mvfx1
cfmsub32hi mvax3, mvfx13, mvfx6, mvfx11
cfmsub32mi mvax0, mvfx9, mvfx0, mvfx5
cfmsub32 mvax2, mvfx9, mvfx4, mvfx14
cfmsub32cc mvax1, mvfx13, mvfx7, mvfx2
cfmadda32ne mvax2, mvax0, mvfx11, mvfx0
cfmadda32vc mvax3, mvax2, mvfx3, mvfx12
cfmadda32ge mvax3, mvax1, mvfx15, mvfx13
cfmadda32vs mvax3, mvax2, mvfx2, mvfx9
cfmadda32eq mvax1, mvax3, mvfx10, mvfx9
cfmsuba32mi mvax1, mvax3, mvfx8, mvfx13
cfmsuba32vc mvax0, mvax3, mvfx12, mvfx6
cfmsuba32lt mvax0, mvax1, mvfx5, mvfx14
cfmsuba32cc mvax0, mvax1, mvfx1, mvfx8
cfmsuba32 mvax2, mvax0, mvfx11, mvfx4
|
tactcomplabs/xbgas-binutils-gdb
| 1,052
|
gas/testsuite/gas/arm/mve-vcvt-bad-4.s
|
.macro cond
.irp round, a, n, p, m
.irp cond, eq, ne, gt, ge, lt, le
.irp size, .s16.f16, .u16.f16, .s32.f32, .u32.f32
it \cond
vcvt\round\size q0, q1
.endr
.endr
.endr
.endm
.syntax unified
.thumb
cond
vcvta.s64.f64 q0, q1
vcvta.u64.f64 q0, q1
vcvta.f64.s64 q0, q1
vcvta.f64.u64 q0, q1
vcvtn.s64.f64 q0, q1
vcvtn.u64.f64 q0, q1
vcvtn.f64.s64 q0, q1
vcvtn.f64.u64 q0, q1
vcvtp.s64.f64 q0, q1
vcvtp.u64.f64 q0, q1
vcvtp.f64.s64 q0, q1
vcvtp.f64.u64 q0, q1
vcvtm.s64.f64 q0, q1
vcvtm.u64.f64 q0, q1
vcvtm.f64.s64 q0, q1
vcvtm.f64.u64 q0, q1
it eq
vcvtaeq.s32.f32 q0, q1
vcvtaeq.s32.f32 q0, q1
vpst
vcvtaeq.s32.f32 q0, q1
vcvtat.s32.f32 q0, q1
vpst
vcvta.s32.f32 q0, q1
it eq
vcvtneq.s32.f32 q0, q1
vcvtneq.s32.f32 q0, q1
vpst
vcvtneq.s32.f32 q0, q1
vcvtnt.s32.f32 q0, q1
vpst
vcvtn.s32.f32 q0, q1
it eq
vcvtpeq.s32.f32 q0, q1
vcvtpeq.s32.f32 q0, q1
vpst
vcvtpeq.s32.f32 q0, q1
vcvtpt.s32.f32 q0, q1
vpst
vcvtp.s32.f32 q0, q1
it eq
vcvtmeq.s32.f32 q0, q1
vcvtmeq.s32.f32 q0, q1
vpst
vcvtmeq.s32.f32 q0, q1
vcvtmt.s32.f32 q0, q1
vpst
vcvtm.s32.f32 q0, q1
|
tactcomplabs/xbgas-binutils-gdb
| 3,574
|
gas/testsuite/gas/arm/group-reloc-ldc.s
|
@ LDC group relocation tests.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store
\load 0, c0, [r0, #:pc_g0:(f + 0x214)]
\load 0, c0, [r0, #:pc_g1:(f + 0x214)]
\load 0, c0, [r0, #:pc_g2:(f + 0x214)]
\load 0, c0, [r0, #:sb_g0:(f + 0x214)]
\load 0, c0, [r0, #:sb_g1:(f + 0x214)]
\load 0, c0, [r0, #:sb_g2:(f + 0x214)]
\store 0, c0, [r0, #:pc_g0:(f + 0x214)]
\store 0, c0, [r0, #:pc_g1:(f + 0x214)]
\store 0, c0, [r0, #:pc_g2:(f + 0x214)]
\store 0, c0, [r0, #:sb_g0:(f + 0x214)]
\store 0, c0, [r0, #:sb_g1:(f + 0x214)]
\store 0, c0, [r0, #:sb_g2:(f + 0x214)]
\load 0, c0, [r0, #:pc_g0:(f - 0x214)]
\load 0, c0, [r0, #:pc_g1:(f - 0x214)]
\load 0, c0, [r0, #:pc_g2:(f - 0x214)]
\load 0, c0, [r0, #:sb_g0:(f - 0x214)]
\load 0, c0, [r0, #:sb_g1:(f - 0x214)]
\load 0, c0, [r0, #:sb_g2:(f - 0x214)]
\store 0, c0, [r0, #:pc_g0:(f - 0x214)]
\store 0, c0, [r0, #:pc_g1:(f - 0x214)]
\store 0, c0, [r0, #:pc_g2:(f - 0x214)]
\store 0, c0, [r0, #:sb_g0:(f - 0x214)]
\store 0, c0, [r0, #:sb_g1:(f - 0x214)]
\store 0, c0, [r0, #:sb_g2:(f - 0x214)]
.endm
ldctest ldc stc
ldctest ldcl stcl
ldctest ldc2 stc2
ldctest ldc2l stc2l
@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
.fpu fpa
.macro fpa_test load store
\load f0, [r0, #:pc_g0:(f + 0x214)]
\load f0, [r0, #:pc_g1:(f + 0x214)]
\load f0, [r0, #:pc_g2:(f + 0x214)]
\load f0, [r0, #:sb_g0:(f + 0x214)]
\load f0, [r0, #:sb_g1:(f + 0x214)]
\load f0, [r0, #:sb_g2:(f + 0x214)]
\store f0, [r0, #:pc_g0:(f + 0x214)]
\store f0, [r0, #:pc_g1:(f + 0x214)]
\store f0, [r0, #:pc_g2:(f + 0x214)]
\store f0, [r0, #:sb_g0:(f + 0x214)]
\store f0, [r0, #:sb_g1:(f + 0x214)]
\store f0, [r0, #:sb_g2:(f + 0x214)]
\load f0, [r0, #:pc_g0:(f - 0x214)]
\load f0, [r0, #:pc_g1:(f - 0x214)]
\load f0, [r0, #:pc_g2:(f - 0x214)]
\load f0, [r0, #:sb_g0:(f - 0x214)]
\load f0, [r0, #:sb_g1:(f - 0x214)]
\load f0, [r0, #:sb_g2:(f - 0x214)]
\store f0, [r0, #:pc_g0:(f - 0x214)]
\store f0, [r0, #:pc_g1:(f - 0x214)]
\store f0, [r0, #:pc_g2:(f - 0x214)]
\store f0, [r0, #:sb_g0:(f - 0x214)]
\store f0, [r0, #:sb_g1:(f - 0x214)]
\store f0, [r0, #:sb_g2:(f - 0x214)]
.endm
fpa_test ldfs stfs
fpa_test ldfd stfd
fpa_test ldfe stfe
fpa_test ldfp stfp
@ FLDS/FSTS
.fpu vfp
.macro vfp_test load store reg
\load \reg, [r0, #:pc_g0:(f + 0x214)]
\load \reg, [r0, #:pc_g1:(f + 0x214)]
\load \reg, [r0, #:pc_g2:(f + 0x214)]
\load \reg, [r0, #:sb_g0:(f + 0x214)]
\load \reg, [r0, #:sb_g1:(f + 0x214)]
\load \reg, [r0, #:sb_g2:(f + 0x214)]
\store \reg, [r0, #:pc_g0:(f + 0x214)]
\store \reg, [r0, #:pc_g1:(f + 0x214)]
\store \reg, [r0, #:pc_g2:(f + 0x214)]
\store \reg, [r0, #:sb_g0:(f + 0x214)]
\store \reg, [r0, #:sb_g1:(f + 0x214)]
\store \reg, [r0, #:sb_g2:(f + 0x214)]
\load \reg, [r0, #:pc_g0:(f - 0x214)]
\load \reg, [r0, #:pc_g1:(f - 0x214)]
\load \reg, [r0, #:pc_g2:(f - 0x214)]
\load \reg, [r0, #:sb_g0:(f - 0x214)]
\load \reg, [r0, #:sb_g1:(f - 0x214)]
\load \reg, [r0, #:sb_g2:(f - 0x214)]
\store \reg, [r0, #:pc_g0:(f - 0x214)]
\store \reg, [r0, #:pc_g1:(f - 0x214)]
\store \reg, [r0, #:pc_g2:(f - 0x214)]
\store \reg, [r0, #:sb_g0:(f - 0x214)]
\store \reg, [r0, #:sb_g1:(f - 0x214)]
\store \reg, [r0, #:sb_g2:(f - 0x214)]
.endm
vfp_test flds fsts s0
@ FLDD/FSTD
vfp_test fldd fstd d0
@ VLDR/VSTR
vfp_test vldr vstr d0
@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
.cpu ep9312
vfp_test cfldrs cfstrs mvf0
vfp_test cfldrd cfstrd mvd0
vfp_test cfldr32 cfstr32 mvfx0
vfp_test cfldr64 cfstr64 mvdx0
|
tactcomplabs/xbgas-binutils-gdb
| 2,214
|
gas/testsuite/gas/arm/mve-vstr-bad-1.s
|
.macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vstrb.s8 q0, [r0, q1]
vstrb.u8 q0, [r0, q1]
vstrb.s16 q0, [r0, q1]
vstrb.u16 q0, [r0, q1]
vstrb.f16 q0, [r0, q1]
vstrb.u32 q0, [r0, q1]
vstrb.s32 q0, [r0, q1]
vstrb.f32 q0, [r0, q1]
vstrb.64 q0, [r0, q1]
vstrb.16 q0, [pc, q1]
cond vstrb
vstrh.8 q0, [r0, q1]
vstrh.s8 q0, [r0, q1]
vstrh.u8 q0, [r0, q1]
vstrh.s16 q0, [r0, q1]
vstrh.u16 q0, [r0, q1]
vstrh.f16 q0, [r0, q1]
vstrh.u32 q0, [r0, q1]
vstrh.s32 q0, [r0, q1]
vstrh.f32 q0, [r0, q1]
vstrh.64 q0, [r0, q1]
vstrh.16 q0, [pc, q1]
cond vstrh
vstrh.16 q0, [r0, q1, #1]
vstrh.16 q0, [r0, q1, UXTW #2]
vstrw.8 q0, [r0, q1]
vstrw.u8 q0, [r0, q1]
vstrw.s8 q0, [r0, q1]
vstrw.16 q0, [r0, q1]
vstrw.f16 q0, [r0, q1]
vstrw.u16 q0, [r0, q1]
vstrw.s16 q0, [r0, q1]
vstrw.u32 q0, [r0, q1]
vstrw.s32 q0, [r0, q1]
vstrw.f32 q0, [r0, q1]
vstrw.64 q0, [r0, q1]
vstrw.32 q0, [pc, q1]
cond vstrw
vstrw.32 q0, [r0, q1, #2]
vstrw.32 q0, [r0, q1, UXTW #1]
vstrw.32 q0, [r0, q1, UXTW #3]
vstrd.8 q0, [r0, q1]
vstrd.u8 q0, [r0, q1]
vstrd.s8 q0, [r0, q1]
vstrd.16 q0, [r0, q1]
vstrd.u16 q0, [r0, q1]
vstrd.s16 q0, [r0, q1]
vstrd.f16 q0, [r0, q1]
vstrd.32 q0, [r0, q1]
vstrd.u32 q0, [r0, q1]
vstrd.s32 q0, [r0, q1]
vstrd.f32 q0, [r0, q1]
vstrd.f64 q0, [r0, q1]
vstrd.u64 q0, [r0, q1]
vstrd.s64 q0, [r0, q1]
.macro cond64
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vstrd\().64 q0, [r0, q1]
.endr
.endm
cond64
vstrd.64 q0, [r0, q1, #3]
vstrd.64 q0, [r0, q1, UXTW #1]
vstrd.64 q0, [r0, q1, UXTW #2]
vstrd.64 q0, [r0, q1, UXTW #4]
it eq
vstrbeq.32 q0, [r0, q1]
vstrbeq.32 q0, [r0, q1]
vpst
vstrbeq.32 q0, [r0, q1]
vpst
vstrb.32 q0, [r0, q1]
vstrbt.32 q0, [r0, q1]
vstrbe.32 q0, [r0, q1]
it eq
vstrheq.32 q0, [r0, q1]
vstrheq.32 q0, [r0, q1]
vpst
vstrheq.32 q0, [r0, q1]
vpst
vstrh.32 q0, [r0, q1]
vstrht.32 q0, [r0, q1]
vstrhe.32 q0, [r0, q1]
it eq
vstrweq.32 q0, [r0, q1]
vstrweq.32 q0, [r0, q1]
vpst
vstrweq.32 q0, [r0, q1]
vpst
vstrw.32 q0, [r0, q1]
vstrwt.32 q0, [r0, q1]
vstrwe.32 q0, [r0, q1]
it eq
vstrdeq.64 q0, [r0, q1]
vstrdeq.64 q0, [r0, q1]
vpst
vstrdeq.64 q0, [r0, q1]
vpst
vstrd.64 q0, [r0, q1]
vstrdt.64 q0, [r0, q1]
vstrde.64 q0, [r0, q1]
|
tactcomplabs/xbgas-binutils-gdb
| 1,067
|
gas/testsuite/gas/arm/unwind.s
|
# Test generation of unwind tables
.text
foo: @ Simple function
.fnstart
.save {r4, lr}
mov r0, #0
.fnend
foo1: @ Typical frame pointer prologue
.fnstart
.movsp ip
@mov ip, sp
.pad #4
.save {fp, ip, lr}
@stmfd sp!, {fp, ip, lr, pc}
.setfp fp, ip, #4
@sub fp, ip, #4
mov r0, #1
.fnend
foo2: @ Custom personality routine
.fnstart
.save {r1, r4, r6, lr}
@stmfd {r1, r4, r6, lr}
mov r0, #2
.personality foo
.handlerdata
.word 42
.fnend
foo3: @ Saving iwmmxt registers
.fnstart
.save {wr12}
.save {wr13}
.save {wr11}
.save {wr10}
.save {wr10, wr11}
.save {wr0}
mov r0, #3
.fnend
.code 16
foo4: @ Thumb frame pointer
.fnstart
.save {r7, lr}
@push {r7, lr}
.setfp r7, sp
@mov r7, sp
.pad #8
@sub sp, sp, #8
mov r0, #4
.fnend
foo5: @ Save r0-r3 only.
.fnstart
.save {r0, r1, r2, r3}
mov r0, #5
.fnend
.code 32
foo6: @ Nested function with frame pointer
.fnstart
.pad #4
@push {ip}
.movsp ip, #4
@mov ip, sp
.pad #4
.save {fp, ip, lr}
@stmfd sp!, {fp, ip, lr, pc}
.setfp fp, ip, #-8
@sub fp, ip, #8
mov r0, #6
.fnend
|
tactcomplabs/xbgas-binutils-gdb
| 2,681
|
gas/testsuite/gas/arm/armv8-ar+fp.s
|
.syntax unified
.text
.arch_extension fp
.arm
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s31, s31
vmaxnm.f64 d0, d0, d0
vmaxnm.f64 d16, d16, d16
vmaxnm.f64 d15, d15, d15
vmaxnm.f64 d31, d31, d31
vminnm.f32 s0, s0, s0
vminnm.f32 s1, s1, s1
vminnm.f32 s30, s30, s30
vminnm.f32 s31, s31, s31
vminnm.f64 d0, d0, d0
vminnm.f64 d16, d16, d16
vminnm.f64 d15, d15, d15
vminnm.f64 d31, d31, d31
vcvta.s32.f32 s0, s0
vcvtn.s32.f32 s1, s1
vcvtp.u32.f32 s30, s30
vcvtm.u32.f32 s31, s31
vcvta.s32.f64 s0, d0
vcvtn.s32.f64 s1, d16
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d31
vrintz.f32 s0, s0
vrintx.f32 s1, s1
vrintreq.f32 s30, s30
vrinta.f32 s0, s0
vrintn.f32 s1, s1
vrintp.f32 s30, s30
vrintm.f32 s31, s31
vrintz.f64 d0, d0
vrintx.f64 d1, d1
vrintreq.f64 d30, d30
vrinta.f64 d0, d0
vrintn.f64 d1, d1
vrintp.f64 d30, d30
vrintm.f64 d31, d31
vcvtt.f16.f64 s0, d0
vcvtb.f16.f64 s1, d16
vcvtt.f16.f64 s30, d15
vcvtb.f16.f64 s31, d31
vcvtt.f64.f16 d0, s0
vcvtb.f64.f16 d16, s1
vcvtt.f64.f16 d15, s30
vcvtb.f64.f16 d31, s31
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s31, s31
vmaxnm.f64 d0, d0, d0
vmaxnm.f64 d16, d16, d16
vmaxnm.f64 d15, d15, d15
vmaxnm.f64 d31, d31, d31
vminnm.f32 s0, s0, s0
vminnm.f32 s1, s1, s1
vminnm.f32 s30, s30, s30
vminnm.f32 s31, s31, s31
vminnm.f64 d0, d0, d0
vminnm.f64 d16, d16, d16
vminnm.f64 d15, d15, d15
vminnm.f64 d31, d31, d31
vcvta.s32.f32 s0, s0
vcvtn.s32.f32 s1, s1
vcvtp.u32.f32 s30, s30
vcvtm.u32.f32 s31, s31
vcvta.s32.f64 s0, d0
vcvtn.s32.f64 s1, d16
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d31
vrintz.f32 s0, s0
vrintx.f32 s1, s1
vrintr.f32 s30, s30
vrinta.f32 s0, s0
vrintn.f32 s1, s1
vrintp.f32 s30, s30
vrintm.f32 s31, s31
vrintz.f64 d0, d0
vrintx.f64 d1, d1
vrintr.f64 d30, d30
vrinta.f64 d0, d0
vrintn.f64 d1, d1
vrintp.f64 d30, d30
vrintm.f64 d31, d31
vcvtt.f16.f64 s0, d0
vcvtb.f16.f64 s1, d16
vcvtt.f16.f64 s30, d15
vcvtb.f16.f64 s31, d31
vcvtt.f64.f16 d0, s0
vcvtb.f64.f16 d16, s1
vcvtt.f64.f16 d15, s30
vcvtb.f64.f16 d31, s31
vmrs r9, MVFR2
vmsr MVFR2, r7
vmrs r4, mvfr2
vmsr mvfr2, r5
|
tactcomplabs/xbgas-binutils-gdb
| 1,461
|
gas/testsuite/gas/arm/mve-vcadd.s
|
.syntax unified
.thumb
.irp data, i8, i16, f16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
.irp op4, #90, #270
vcadd.\data \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
.endr
.macro vcadd_q0 data, op2, op4
.irp op3, q1, q2, q4, q7
vcadd.\data q0, \op2, \op3, \op4
.endr
.endm
.macro vcadd_q1 data, op2, op4
.irp op3, q0, q2, q4, q7
vcadd.\data q1, \op2, \op3, \op4
.endr
.endm
.macro vcadd_q2 data, op2, op4
.irp op3, q0, q1, q4, q7
vcadd.\data q2, \op2, \op3, \op4
.endr
.endm
.macro vcadd_q3 data, op2, op4
.irp op3, q0, q1, q2, q4, q7
vcadd.\data q3, \op2, \op3, \op4
.endr
.endm
.macro vcadd_q4 data, op2, op4
.irp op3, q0, q1, q2, q3, q7
vcadd.\data q4, \op2, \op3, \op4
.endr
.endm
.macro vcadd_q6 data, op2, op4
.irp op3, q0, q1, q2, q4, q7
vcadd.\data q6, \op2, \op3, \op4
.endr
.endm
.macro vcadd_q7 data, op2, op4
.irp op3, q0, q1, q2, q4, q5
vcadd.\data q7, \op2, \op3, \op4
.endr
.endm
.irp data, i32, f32
.irp op2, q0, q1, q2, q4, q7
.irp op4, #90, #270
vcadd_q0 \data, \op2, \op4
vcadd_q1 \data, \op2, \op4
vcadd_q2 \data, \op2, \op4
vcadd_q3 \data, \op2, \op4
vcadd_q4 \data, \op2, \op4
vcadd_q6 \data, \op2, \op4
vcadd_q7 \data, \op2, \op4
.endr
.endr
.endr
vpstete
vcaddt.i8 q0, q1, q2, #90
vcadde.i8 q7, q7, q7, #270
vcaddt.i16 q0, q1, q2, #90
vcadde.i16 q0, q1, q2, #270
vpstete
vcaddt.i32 q0, q1, q2, #90
vcadde.i32 q0, q1, q2, #270
vcaddt.f16 q0, q1, q2, #90
vcadde.f32 q0, q1, q2, #270
|
tactcomplabs/xbgas-binutils-gdb
| 2,164
|
gas/testsuite/gas/arm/t16-bad.s
|
@ Things you can't do with 16-bit Thumb instructions, but you can
@ do with the equivalent ARM instruction. Does not include errors
@ caught by fixup processing (e.g. out-of-range immediates).
.text
.code 16
.thumb_func
l:
@ Arithmetic instruction templates
.macro ar2 opc
\opc r8,r0
\opc r0,r8
.endm
.macro ar2sh opc
ar2 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
.macro ar2r opc
ar2 \opc
\opc r0,r1,ror #8
.endm
.macro ar3 opc
\opc r1,r2,r3
\opc r8,r0
\opc r0,r8
.endm
.macro ar3sh opc
ar3 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
ar2sh tst
ar2sh cmn
ar2sh mvn
ar2 neg
ar2 rev
ar2 rev16
ar2 revsh
ar2r sxtb
ar2r sxth
ar2r uxtb
ar2r uxth
ar3sh adc
ar3sh and
ar3sh bic
ar3sh eor
ar3sh orr
ar3sh sbc
ar3 mul
@ Shift instruction template
.macro shift opc
\opc r8,r0,#12 @ form 1
\opc r0,r8,#12
ar2 \opc @ form 2
.endm
shift asr
shift lsl
shift lsr
shift ror
ror r0,r1,#12
@ add/sub/mov/cmp are idiosyncratic
add r0,r1,lsl #2
add r0,r1,lsl r3
add r8,r0,#1 @ form 1
add r0,r8,#1
add r8,#10 @ form 2
add r8,r1,r2 @ form 3
add r1,r8,r2
add r1,r2,r8
add r8,pc,#4 @ form 5
add r8,sp,#4 @ form 6
ar3sh sub
sub r8,r0,#1 @ form 1
sub r0,r8,#1
sub r8,#10 @ form 2
sub r8,r1,r2 @ form 3
sub r1,r8,r2
sub r1,r2,r8
cmp r0,r1,lsl #2
cmp r0,r1,lsl r3
cmp r8,#255
mov r0,r1,lsl #2
mov r0,r1,lsl r3
mov r8,#255
@ Load/store template
.macro ldst opc
\opc r8,[r0]
\opc r0,[r8]
\opc r0,[r0,r8]
\opc r0,[r1,#4]!
\opc r0,[r1],#4
\opc r0,[r1,-r2]
\opc r0,[r1],r2
.endm
ldst ldr
ldst ldrb
ldst ldrh
ldst ldrsb
ldst ldrsh
ldst str
ldst strb
ldst strh
ldr r0,[r1,r2,lsl #1]
str r0,[r1,r2,lsl #1]
@ Load/store multiple
ldmia r8!,{r1,r2}
ldmia r7!,{r8}
ldmia r7,{r1,r2}
ldmia r7!,{r1,r7}
stmia r8!,{r1,r2}
stmia r7!,{r8}
stmia r7,{r1,r2}
stmia r7!,{r1,r7}
push {r8,r9}
pop {r8,r9}
@ Miscellaneous
bkpt #257
cpsie ai,#5
cpsid ai,#5
@ Conditional suffixes
addeq r0,r1,r2
@ low register non flag setting add.
.syntax unified
add r0, r1
@ Multiply
.syntax divided
mul r0, r0, r8
mul r0, r8, r0
mul r8, r0, r0
|
tactcomplabs/xbgas-binutils-gdb
| 2,779
|
gas/testsuite/gas/arm/vldconst.s
|
@ Test file for ARM/GAS -- vldr reg, =... expressions.
.fpu neon
.text
.align
foo:
# test both low and high index of the
# Advanced SIMD and Floating-point reg.
.macro vlxr regtype const
.irp regindex, 0, 14, 28, 31
vldr \regtype\regindex, \const
.endr
.endm
.macro vlxreq regtype const
.irp regindex, 0, 14, 28, 31
vldreq \regtype\regindex, \const
.endr
.endm
.macro vlxrmi regtype const
.irp regindex, 0, 14, 28, 31
vldrmi \regtype\regindex, \const
.endr
.endm
vlxr s "=0"
vlxr s "=0xff000000"
vlxr s "=-1"
vlxr s "=0x0fff0000"
.pool
vlxr s "=0"
vlxr s "=0x00ff0000"
vlxr s "=0xff00ffff"
vlxr s "=0x00fff000"
.pool
vlxreq s "=0"
vlxreq s "=0x0000ff00"
vlxreq s "=0xffff00ff"
vlxreq s "=0x000fff00"
.pool
vlxrmi s "=0"
vlxrmi s "=0x000000ff"
vlxrmi s "=0xffffff00"
vlxrmi s "=0x0000fff0"
.pool
vlxr d "=0"
vlxr d "=0xca000000"
vlxr d "=-1"
vlxr d "=0x0fff0000"
.pool
vlxr d "=0"
vlxr d "=0x00ff0000"
vlxr d "=0xff0000ff"
vlxr d "=0x00fff000"
.pool
vlxreq d "=0"
vlxreq d "=0x0000ff00"
vlxreq d "=0xffff00ff"
vlxreq d "=0x000fff00"
.pool
vlxrmi d "=0"
vlxrmi d "=0x000000ff"
vlxrmi d "=0xffffff00"
vlxrmi d "=0x0000ffff"
.pool
vlxr d "=0"
vlxr d "=0xff00000000000000"
vlxr d "=-1"
vlxr d "=0x0fff000000000000"
.pool
vlxr d "=0"
vlxr d "=0x00ff00000000000"
vlxr d "=0xff00ffff0000000"
vlxr d "=0x00fff0000000000"
.pool
vlxreq d "=0"
vlxreq d "=0x0000ff0000000000"
vlxreq d "=0xffff00ff00000000"
vlxreq d "=0x000fff0000000000"
.pool
vlxrmi d "=0"
vlxrmi d "=0x000000ff00000000"
vlxrmi d "=0xffffff0000000000"
vlxrmi d "=0x0000fff000000000"
.pool
# pool should be aligned to 8-byte.
.p2align 3
vldr d1, =0x0000fff000000000
.pool
# no error when code is align already.
.p2align 3
add r0, r1, #0
vldr d1, =0x0000fff000000000
.pool
.p2align 3
vldr d1, =0x0000fff000000000
vldr s2, =0xff000000
# padding A
vldr d3, =0x0000fff000000001
# reuse padding slot A
vldr s4, =0xff000001
# reuse d3
vldr d5, =0x0000fff000000001
# new 8-byte entry
vldr d6, =0x0000fff000000002
# new 8-byte entry
vldr d7, =0x0000fff000000003
# new 4-byte entry
vldr s8, =0xff000002
# padding B
vldr d9, =0x0000fff000000004
# reuse padding slot B
vldr s10, =0xff000003
# new 8-byte entry
vldr d11, =0x0000fff000000005
# new 4 entry
vldr s12, =0xff000004
# new 4 entry
vldr s13, =0xff000005
# reuse value of s4 in pool
vldr s14, =0xff000001
# reuse high part of d1 in pool
vldr s15, =0x0000fff0
# 8-byte entry reuse two 4-byte entries.
# this reuse should only happen for
# little-endian
# d16 reuse s12, s13
vldr d16, =0xff000005ff000004
# d17 should not reuse high part of d11 and s12.
# because the it's align 8-byte aligned.
vldr d17, =0xff0000040000fff0
.pool
|
tactcomplabs/xbgas-binutils-gdb
| 1,101
|
gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s
|
@ Tests that are supposed to fail during parsing of LDRS group relocations.
.text
@ No NC variants exist for the LDRS relocations.
ldrd r0, [r0, #:pc_g0_nc:(f)]
ldrd r0, [r0, #:pc_g1_nc:(f)]
ldrd r0, [r0, #:sb_g0_nc:(f)]
ldrd r0, [r0, #:sb_g1_nc:(f)]
strd r0, [r0, #:pc_g0_nc:(f)]
strd r0, [r0, #:pc_g1_nc:(f)]
strd r0, [r0, #:sb_g0_nc:(f)]
strd r0, [r0, #:sb_g1_nc:(f)]
ldrh r0, [r0, #:pc_g0_nc:(f)]
ldrh r0, [r0, #:pc_g1_nc:(f)]
ldrh r0, [r0, #:sb_g0_nc:(f)]
ldrh r0, [r0, #:sb_g1_nc:(f)]
strh r0, [r0, #:pc_g0_nc:(f)]
strh r0, [r0, #:pc_g1_nc:(f)]
strh r0, [r0, #:sb_g0_nc:(f)]
strh r0, [r0, #:sb_g1_nc:(f)]
ldrsh r0, [r0, #:pc_g0_nc:(f)]
ldrsh r0, [r0, #:pc_g1_nc:(f)]
ldrsh r0, [r0, #:sb_g0_nc:(f)]
ldrsh r0, [r0, #:sb_g1_nc:(f)]
ldrsb r0, [r0, #:pc_g0_nc:(f)]
ldrsb r0, [r0, #:pc_g1_nc:(f)]
ldrsb r0, [r0, #:sb_g0_nc:(f)]
ldrsb r0, [r0, #:sb_g1_nc:(f)]
@ Instructions with a gibberish relocation code.
ldrd r0, [r0, #:foo:(f)]
strd r0, [r0, #:foo:(f)]
ldrh r0, [r0, #:foo:(f)]
strh r0, [r0, #:foo:(f)]
ldrsh r0, [r0, #:foo:(f)]
ldrsb r0, [r0, #:foo:(f)]
|
tactcomplabs/xbgas-binutils-gdb
| 2,935
|
gas/testsuite/gas/arm/msr-reg.s
|
@ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from register
msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
@ Write to CPSR flags
msr CPSR,r9
msr CPSR_s,r9
msr CPSR_f,r9
msr CPSR_c,r9
msr CPSR_x,r9
@ Write to CPSR flag combos
msr CPSR_fs, r9
msr CPSR_fx, r9
msr CPSR_fc, r9
msr CPSR_sf, r9
msr CPSR_sx, r9
msr CPSR_sc, r9
msr CPSR_xf, r9
msr CPSR_xs, r9
msr CPSR_xc, r9
msr CPSR_cf, r9
msr CPSR_cs, r9
msr CPSR_cx, r9
msr CPSR_fsx, r9
msr CPSR_fsc, r9
msr CPSR_fxs, r9
msr CPSR_fxc, r9
msr CPSR_fcs, r9
msr CPSR_fcx, r9
msr CPSR_sfx, r9
msr CPSR_sfc, r9
msr CPSR_sxf, r9
msr CPSR_sxc, r9
msr CPSR_scf, r9
msr CPSR_scx, r9
msr CPSR_xfs, r9
msr CPSR_xfc, r9
msr CPSR_xsf, r9
msr CPSR_xsc, r9
msr CPSR_xcf, r9
msr CPSR_xcs, r9
msr CPSR_cfs, r9
msr CPSR_cfx, r9
msr CPSR_csf, r9
msr CPSR_csx, r9
msr CPSR_cxf, r9
msr CPSR_cxs, r9
msr CPSR_fsxc, r9
msr CPSR_fscx, r9
msr CPSR_fxsc, r9
msr CPSR_fxcs, r9
msr CPSR_fcsx, r9
msr CPSR_fcxs, r9
msr CPSR_sfxc, r9
msr CPSR_sfcx, r9
msr CPSR_sxfc, r9
msr CPSR_sxcf, r9
msr CPSR_scfx, r9
msr CPSR_scxf, r9
msr CPSR_xfsc, r9
msr CPSR_xfcs, r9
msr CPSR_xsfc, r9
msr CPSR_xscf, r9
msr CPSR_xcfs, r9
msr CPSR_xcsf, r9
msr CPSR_cfsx, r9
msr CPSR_cfxs, r9
msr CPSR_csfx, r9
msr CPSR_csxf, r9
msr CPSR_cxfs, r9
msr CPSR_cxsf, r9
@ Write to SPSR flags
msr SPSR,r9
msr SPSR_s,r9
msr SPSR_f,r9
msr SPSR_c,r9
msr SPSR_x,r9
@ Write to Saved status register
msr SPSR_fs, r9
msr SPSR_fx, r9
msr SPSR_fc, r9
msr SPSR_sf, r9
msr SPSR_sx, r9
msr SPSR_sc, r9
msr SPSR_xf, r9
msr SPSR_xs, r9
msr SPSR_xc, r9
msr SPSR_cf, r9
msr SPSR_cs, r9
msr SPSR_cx, r9
msr SPSR_fsx, r9
msr SPSR_fsc, r9
msr SPSR_fxs, r9
msr SPSR_fxc, r9
msr SPSR_fcs, r9
msr SPSR_fcx, r9
msr SPSR_sfx, r9
msr SPSR_sfc, r9
msr SPSR_sxf, r9
msr SPSR_sxc, r9
msr SPSR_scf, r9
msr SPSR_scx, r9
msr SPSR_xfs, r9
msr SPSR_xfc, r9
msr SPSR_xsf, r9
msr SPSR_xsc, r9
msr SPSR_xcf, r9
msr SPSR_xcs, r9
msr SPSR_cfs, r9
msr SPSR_cfx, r9
msr SPSR_csf, r9
msr SPSR_csx, r9
msr SPSR_cxf, r9
msr SPSR_cxs, r9
msr SPSR_fsxc, r9
msr SPSR_fscx, r9
msr SPSR_fxsc, r9
msr SPSR_fxcs, r9
msr SPSR_fcsx, r9
msr SPSR_fcxs, r9
msr SPSR_sfxc, r9
msr SPSR_sfcx, r9
msr SPSR_sxfc, r9
msr SPSR_sxcf, r9
msr SPSR_scfx, r9
msr SPSR_scxf, r9
msr SPSR_xfsc, r9
msr SPSR_xfcs, r9
msr SPSR_xsfc, r9
msr SPSR_xscf, r9
msr SPSR_xcfs, r9
msr SPSR_xcsf, r9
msr SPSR_cfsx, r9
msr SPSR_cfxs, r9
msr SPSR_csfx, r9
msr SPSR_csxf, r9
msr SPSR_cxfs, r9
msr SPSR_cxsf, r9
|
tactcomplabs/xbgas-binutils-gdb
| 1,699
|
gas/testsuite/gas/arm/bfloat16-neon.s
|
.syntax unified
// Check argument encoding by having different arguments.
// We use 20 and 11 since their binary encoding is 10100 and 01011
// respectively which ensures that we distinguish between the D/M/N bit
// encoding the first or last bit of the argument.
// q registers are encoded as double their actual number.
vdot.bf16 d0, d20, d11
vdot d11.bf16, d0.bf16, d20.bf16
.macro conversion_type_specifier_check insn, dest, source
\insn\().bf16.f32 \dest, \source
\insn \dest\().bf16, \source\().f32
\insn \dest\().bf16, \source\().f32
.endm
conversion_type_specifier_check vcvtt,s0,s0
conversion_type_specifier_check vcvtb,s0,s0
conversion_type_specifier_check vcvt,d0,q0
// Here we follow the same encoding sequence as above.
// Since the 'M' bit encodes the index and the last register is encoded in 4
// bits that argument has a different number.
vdot.bf16 d11, d0, d4[1]
vdot d0.bf16, d20.bf16, d11.bf16[0]
// vmmla only works on q registers.
// These registers are encoded as double the number given in the mnemonic.
// Hence we choose different numbers to ensure a similar bit pattern as above.
// 10 & 5 produce the bit patterns 10100 & 01010
vmmla.bf16 q10, q5, q0
vmmla q5.bf16, q0.bf16, q10.bf16
vfmat.bf16 q10, q11, q0
vfmat.bf16 q10, q11, d0[3]
vfmat.bf16 q10, q11, d0[0]
vfmab.bf16 q10, q11, q0
vfmab.bf16 q10, q11, d0[3]
vfmab.bf16 q10, q11, d0[0]
// vcvt
// - no condition allowed in arm
// - no condition allowed in thumb outside IT block
// - Condition *allowed* in thumb in IT block
// - different encoding between thumb and arm
vcvt.bf16.f32 d20, q5
vcvt.bf16.f32 d11, q10
// Only works for thumb mode.
.ifdef COMPILING_FOR_THUMB
it ne
vcvtne.bf16.f32 d0, q0
.endif
|
tactcomplabs/xbgas-binutils-gdb
| 1,295
|
gas/testsuite/gas/arm/fpv5-d16.s
|
.syntax unified
.text
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d8, d8, d8
vselge.f64 d15, d15, d15
vselgt.f64 d10, d10, d10
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s31, s31
vmaxnm.f64 d0, d0, d0
vmaxnm.f64 d8, d8, d8
vmaxnm.f64 d15, d15, d15
vmaxnm.f64 d10, d10, d10
vminnm.f32 s0, s0, s0
vminnm.f32 s1, s1, s1
vminnm.f32 s30, s30, s30
vminnm.f32 s31, s31, s31
vminnm.f64 d0, d0, d0
vminnm.f64 d8, d8, d8
vminnm.f64 d15, d15, d15
vminnm.f64 d10, d10, d10
vcvta.s32.f32 s0, s0
vcvtn.s32.f32 s1, s1
vcvtp.u32.f32 s30, s30
vcvtm.u32.f32 s31, s31
vcvta.s32.f64 s0, d0
vcvtn.s32.f64 s1, d8
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d10
vrintz.f32 s0, s0
vrintx.f32 s1, s1
vrintr.f32 s30, s30
vrinta.f32 s0, s0
vrintn.f32 s1, s1
vrintp.f32 s30, s30
vrintm.f32 s31, s31
vrintz.f64 d0, d0
vrintx.f64 d1, d1
vrintr.f64 d10, d10
vrinta.f64 d0, d0
vrintn.f64 d1, d1
vrintp.f64 d10, d10
vrintm.f64 d10, d10
vcvtt.f16.f64 s0, d0
vcvtb.f16.f64 s1, d8
vcvtt.f16.f64 s30, d15
vcvtb.f16.f64 s31, d10
vcvtt.f64.f16 d0, s0
vcvtb.f64.f16 d8, s1
vcvtt.f64.f16 d15, s30
vcvtb.f64.f16 d10, s31
|
tactcomplabs/xbgas-binutils-gdb
| 1,326
|
gas/testsuite/gas/arm/armv7e-m+fpv5-d16.s
|
.syntax unified
.text
.arch armv7e-m
.fpu fpv5-d16
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d8, d8, d8
vselge.f64 d15, d15, d15
vselgt.f64 d10, d10, d10
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s31, s31
vmaxnm.f64 d0, d0, d0
vmaxnm.f64 d8, d8, d8
vmaxnm.f64 d15, d15, d15
vmaxnm.f64 d10, d10, d10
vminnm.f32 s0, s0, s0
vminnm.f32 s1, s1, s1
vminnm.f32 s30, s30, s30
vminnm.f32 s31, s31, s31
vminnm.f64 d0, d0, d0
vminnm.f64 d8, d8, d8
vminnm.f64 d15, d15, d15
vminnm.f64 d10, d10, d10
vcvta.s32.f32 s0, s0
vcvtn.s32.f32 s1, s1
vcvtp.u32.f32 s30, s30
vcvtm.u32.f32 s31, s31
vcvta.s32.f64 s0, d0
vcvtn.s32.f64 s1, d8
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d10
vrintz.f32 s0, s0
vrintx.f32 s1, s1
vrintr.f32 s30, s30
vrinta.f32 s0, s0
vrintn.f32 s1, s1
vrintp.f32 s30, s30
vrintm.f32 s31, s31
vrintz.f64 d0, d0
vrintx.f64 d1, d1
vrintr.f64 d10, d10
vrinta.f64 d0, d0
vrintn.f64 d1, d1
vrintp.f64 d10, d10
vrintm.f64 d10, d10
vcvtt.f16.f64 s0, d0
vcvtb.f16.f64 s1, d8
vcvtt.f16.f64 s30, d15
vcvtb.f16.f64 s31, d10
vcvtt.f64.f16 d0, s0
vcvtb.f64.f16 d8, s1
vcvtt.f64.f16 d15, s30
vcvtb.f64.f16 d10, s31
|
tactcomplabs/xbgas-binutils-gdb
| 1,038
|
gas/testsuite/gas/arm/archv8m.s
|
.thumb
.syntax unified
T:
blx r4
blx r9
bx r4
bx r9
tt r0, r1
tt r8, r9
ttt r0, r1
ttt r8, r9
movw r0, #0xF123
@ mov accept all immediate formats, including T3. It's also the suggested
@ assembly to use.
mov r8, #0xF123
@ .w means wide, specifies that the assembler must select a 32-bit encoding for
@ the instruction if it is possible, it should accept both T2 (Thumb modified
@ immediate) and T3 (UINT16) encoding. See the section "Standard assembler
@ syntax fields" on latest ARM-ARM.
mov.w r8, #0xF123
movw r8, #0xF123
movt r0, #0xF123
movt r8, #0xF123
cbz r4, .L1
cbnz r4, .L1
b.w .L1
sdiv r0, r1, r2
sdiv r8, r9, r10
udiv r0, r1, r2
udiv r8, r9, r10
.L1:
add r0, r1
clrex
ldrex r0, [r1, #0x4]
ldrexb r0, [r1]
ldrexh r0, [r1]
strex r0, r1, [r2, #0x4]
strexb r0, r1, [r2]
strexh r0, r1, [r2]
lda r0, [r1]
ldab r0, [r1]
ldah r0, [r1]
stl r0, [r1]
stlb r0, [r1]
stlh r0, [r1]
ldaex r0, [r1]
ldaexb r0, [r1]
ldaexh r0, [r1]
stlex r0, r1, [r2]
stlexb r0, r1, [r2]
stlexh r0, r1, [r2]
|
tactcomplabs/xbgas-binutils-gdb
| 1,694
|
gas/testsuite/gas/arm/attr-names.s
|
.eabi_attribute Tag_CPU_raw_name, "random-cpu"
.eabi_attribute Tag_CPU_name, "cpu"
.eabi_attribute Tag_CPU_arch, 1
.eabi_attribute Tag_CPU_arch_profile, 'S'
.eabi_attribute Tag_ARM_ISA_use, 1
.eabi_attribute Tag_THUMB_ISA_use, 1
.eabi_attribute Tag_FP_arch, 1
.eabi_attribute Tag_VFP_arch, 1
.eabi_attribute Tag_WMMX_arch, 1
.eabi_attribute Tag_Advanced_SIMD_arch, 1
.eabi_attribute Tag_PCS_config, 1
.eabi_attribute Tag_ABI_PCS_R9_use, 1
.eabi_attribute Tag_ABI_PCS_RW_data, 1
.eabi_attribute Tag_ABI_PCS_RO_data, 1
.eabi_attribute Tag_ABI_PCS_GOT_use, 1
.eabi_attribute Tag_ABI_PCS_wchar_t, 2
.eabi_attribute Tag_ABI_FP_rounding, 1
.eabi_attribute Tag_ABI_FP_denormal, 1
.eabi_attribute Tag_ABI_FP_exceptions, 1
.eabi_attribute Tag_ABI_FP_user_exceptions, 1
.eabi_attribute Tag_ABI_FP_number_model, 1
.eabi_attribute Tag_ABI_align_needed, 1
.eabi_attribute Tag_ABI_align8_needed, 1
.eabi_attribute Tag_ABI_align_preserved, 1
.eabi_attribute Tag_ABI_align8_preserved, 1
.eabi_attribute Tag_ABI_enum_size, 1
.eabi_attribute Tag_ABI_HardFP_use, 1
.eabi_attribute Tag_ABI_VFP_args, 1
.eabi_attribute Tag_ABI_WMMX_args, 1
.eabi_attribute Tag_ABI_optimization_goals, 1
.eabi_attribute Tag_ABI_FP_optimization_goals, 1
.eabi_attribute Tag_compatibility, 1, "gnu"
.eabi_attribute Tag_CPU_unaligned_access, 1
.eabi_attribute Tag_FP_HP_extension, 1
.eabi_attribute Tag_VFP_HP_extension, 1
.eabi_attribute Tag_ABI_FP_16bit_format, 1
.eabi_attribute Tag_MPextension_use, 1
.eabi_attribute Tag_DIV_use, 1
.eabi_attribute Tag_nodefaults, 0
.eabi_attribute Tag_also_compatible_with, "\06\013"
.eabi_attribute Tag_conformance, "2.08"
.eabi_attribute Tag_T2EE_use, 1
.eabi_attribute Tag_Virtualization_use, 3
|
tactcomplabs/xbgas-binutils-gdb
| 1,341
|
gas/testsuite/gas/arm/mve-vmullbt.s
|
.syntax unified
.thumb
.macro helper_q0 op
.irp op2, q1, q2, q4, q7
.irp op3, q1, q2, q4, q7
\op q0, \op2, \op3
.endr
.endr
.endm
.macro helper_q1 op
.irp op2, q0, q2, q4, q7
.irp op3, q0, q2, q4, q7
\op q1, \op2, \op3
.endr
.endr
.endm
.macro helper_q2 op
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
\op q2, \op2, \op3
.endr
.endr
.endm
.macro helper_q4 op
.irp op2, q0, q1, q2, q7
.irp op3, q0, q1, q2, q7
\op q4, \op2, \op3
.endr
.endr
.endm
.macro helper_q7 op
.irp op2, q0, q1, q2, q4
.irp op3, q0, q1, q2, q4
\op q7, \op2, \op3
.endr
.endr
.endm
.macro all_qqq op
helper_q0 \op
helper_q1 \op
helper_q2 \op
helper_q4 \op
helper_q7 \op
.endm
.irp data, s8, u8, s16, u16, p8, p16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
vmullb.\data \op1, \op2, \op3
vmullt.\data \op1, \op2, \op3
.endr
.endr
.endr
.endr
all_qqq vmullb.s32
all_qqq vmullb.u32
all_qqq vmullt.s32
all_qqq vmullt.u32
vpstete
vmullbt.s8 q0, q1, q2
vmullbe.s16 q1, q0, q3
vmullbt.s32 q2, q3, q4
vmullbe.u8 q3, q2, q1
vpstete
vmullbt.u16 q4, q5, q7
vmullbe.u32 q5, q4, q6
vmullbt.p8 q6, q7, q5
vmullbe.p16 q7, q6, q0
vpstete
vmulltt.s8 q0, q1, q2
vmullte.s16 q1, q0, q3
vmulltt.s32 q2, q3, q4
vmullte.u8 q3, q2, q1
vpstete
vmulltt.u16 q4, q5, q7
vmullte.u32 q5, q4, q6
vmulltt.p8 q6, q7, q5
vmullte.p16 q7, q6, q0
|
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